PIC18CXX8 High-Performance Microcontrollers with CAN Module High Performance RISC CPU: Advanced Analog Features: • C-compiler optimized architecture instruction set (cid:127) 10-bit Analog-to-Digital Converter module (A/D) (cid:127) Linear program memory addressing to 32Kbytes with: - Fast sampling rate (cid:127) Linear data memory addressing to 4Kbytes - Conversion available during SLEEP Program Memory - DNL = ±1 LSb, INL = ±1 LSb - Up to 16 channels available On-Chip Off-Chip On-Chip Device RAM (cid:127) Analog Comparator Module: # Single Maximum EPROM (bytes) - 2 Comparators Word Addressing (bytes) - Programmable input and output multiplexing Instructions (bytes) (cid:127) Comparator Voltage Reference Module PIC18C658 32K 16384 N/A 1536 (cid:127) Programmable Low Voltage Detection (LVD) PIC18C858 32K 16384 N/A 1536 module (cid:127) Up to 10MIPS operation: - Supports interrupt on low voltage detection - DC - 40MHz clock input (cid:127) Programmable Brown-out Reset (BOR) - 4MHz - 10MHz osc./clock input with PLL active CAN BUS Module Features: (cid:127) 16-bit wide instructions, 8-bit wide data path (cid:127) Message bit rates up to 1Mbps (cid:127) Priority levels for interrupts (cid:127) Conforms to CAN 2.0B ACTIVE Spec with: (cid:127) 8 x 8 Single Cycle Hardware Multiplier - 29-bit Identifier Fields Peripheral Features: - 8 byte message length (cid:127) High current sink/source 25mA/25mA (cid:127) 3 Transmit Message Buffers with prioritization (cid:127) Up to 76 I/O with individual direction control (cid:127) 2 Receive Message Buffers (cid:127) Four external interrupt pins (cid:127) 6 full 29-bit Acceptance Filters (cid:127) Timer0 module: 8-bit/16-bit timer/counter with (cid:127) Prioritization of Acceptance Filters 8-bit programmable prescaler (cid:127) Multiple Receive Buffers for High Priority (cid:127) Timer1 module: 16-bit timer/counter Messages to prevent loss due to overflow (cid:127) Timer2 module: 8-bit timer/counter with 8-bit (cid:127) Advanced Error Management Features period register (time base for PWM) Special Microcontroller Features: (cid:127) Timer3 module: 16-bit timer/counter (cid:127) Power-on Reset (POR), Power-up Timer (PWRT), (cid:127) Secondary oscillator clock option - Timer1/Timer3 and Oscillator Start-up Timer (OST) (cid:127) Two Capture/Compare/PWM (CCP) modules (cid:127) Watchdog Timer (WDT) with its own on-chip RC CCP pins can be configured as: oscillator - Capture input: 16-bit, max resolution 6.25ns (cid:127) Programmable code protection - Compare is 16-bit, max resolution 100ns (TCY) (cid:127) Power saving SLEEP mode - PWM output: PWM resolution is 1- to 10-bit. Max. PWM freq. @:8-bit resolution = 156kHz (cid:127) Selectable oscillator options, including: 10-bit resolution = 39kHz - 4X Phase Lock Loop (of primary oscillator) (cid:127) Master Synchronous Serial Port (MSSP) with two - Secondary Oscillator (32kHz) clock input modes of operation: (cid:127) In-Circuit Serial Programming (ICSP™) via two pins - 3-wire SPI™ (Supports all 4 SPI modes) CMOS Technology: - I2C™ Master and Slave mode (cid:127) Low power, high speed EPROM technology (cid:127) Addressable USART module: Supports Interrupt (cid:127) Fully static design on Address bit (cid:127) Wide operating voltage range (2.5V to 5.5V) (cid:127) Industrial and Extended temperature ranges (cid:127) Low power consumption  2000 Microchip Technology Inc. Advanced Information DS30475A-page 1

PIC18CXX8 Pin Diagrams 64-Pin TQFP 2 0 1 2 3 4 5 6 7 P P P P P P P P P S C S S S S S S S S C C P P P P P P P P E2/ E3 E4 E5 E6 E7/ D0/ DD SS D1/ D2/ D3/ D4/ D5/ D6/ D7/ R R R R R R R V V R R R R R R R 64636261605958575655545352515049 RE1/WR 1 48 RB0/INT0 RE0/RD 2 47 RB1/INT1 RG0/CANTX1 3 46 RB2/INT2 RG1/CANTX2 4 45 RB3/INT3 RG2/CANRX 5 44 RB4 RG3 6 43 RB5 MCLR/VPP 7 42 RB6 RG4 8 PIC18C658 41 VSS VSS 9 40 OSC2/CLKO/RA6 VDD 10 39 OSC1/CLKI RF7 11 38 VDD RF6/AN11 12 37 RB7 RF5/AN10/CVREF 13 36 RC5/SDO RF4/AN9 14 35 RC4/SDI/SDA RF3/AN8 15 34 RC3/SCK/SCL RF2/AN7/C1OUT 16 33 RC2/CCP1 1718192021 2223242526272829303132 RF1/AN6/C2OUT RF0/AN5 AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0 VSS VDD A5/SS/AN4/LVDIN RA4/T0CKI RC1/T1OSI C0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT R R DS30475A-page 2 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 Pin Diagrams (Cont.’d) 68-Pin PLCC 20 1234567 PP PPPPPPP S CS SSSSSSS C CP PPPPPPP E2/E3E4E5E6E7/D0/ DDC SS D1/D2/D3/D4/D5/D6/D7/ RRRRRRRVN VRRRRRRR 9 8 7 6 5 4 3 2 1 6867666564636261 RE1/WR 10 60 RB0/INT0 RE0/RD 11 59 RB1/INT1 RG0/CANTX1 12 58 RB2/INT2 RG1/CANTX2 13 57 RB3/INT3 RG2/CANRX 14 56 RB4 RG3 15 55 RB5 MCLR/VPP 16 54 RB6 RG4 17 53 VSS PIC18C658 NC 18 52 NC VSS 19 51 OSC2/CLKO/RA6 VDD 20 50 OSC1/CLKI RF7 21 49 VDD RF6/AN11 22 48 RB7 RF5/AN10/CVREF 23 47 RC5/SDO RF4/AN9 24 46 RC4/SDI/SDA RF3/AN8 25 45 RC3/SCK/SCL RF2/AN7/C1OUT 26 44 RC2/CCP1 2728293031323334353637383940414243 RF1/AN6/C2OUTRF0/AN5 AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0NCVSS VDD A5/SS/AN4/LVDINRA4/T0CKI RC1/T1OSI C0/T1OSO/T13CKIRC6/TX/CKRC7/RX/DT R R  2000 Microchip Technology Inc. Advanced Information DS30475A-page 3

PIC18CXX8 Pin Diagrams (Cont.’d) 80-Pin TQFP 2 0 1 2 3 4 5 6 7 P P P P P P P P P S C S S S S S S S S C C P P P P P P P P H1 H0 E2/ E3 E4 E5 E6 E7/ D0/ DD SS D1/ D2/ D3/ D4/ D5/ D6/ D7/ J0 J1 R R R R R R R R R V V R R R R R R R R R 807978777675 747372717069 68676665 64636261 RH2 1 60 RJ2 RH3 2 59 RJ3 RE1/WR 3 58 RB0/INT0 RE0/RD 4 57 RB1/INT1 RG0/CANTX1 5 56 RB2/INT2 RG1/CANTX2 6 55 RB3/INT3 RG2/CANRX 7 54 RB4 RG3 8 53 RB5 MCLR/VPP 9 52 RB6 RG4 10 51 VSS VSS 11 50 OSC2/CLKO/RA6 PIC18C858 VDD 12 49 OSC1/CLKI RF7 13 48 VDD RF6/AN11 14 47 RB7 RF5/AN10/CVREF 15 46 RC5/SDO RF4/AN9 16 45 RC4/SDI/SDA RF3/AN8 17 44 RC3/SCK/SCL RF2/AN7/C1OUT 18 43 RC2/CCP1 RH7/AN15 19 42 RK3 RH6/AN14 20 41 RK2 212223242526 272829303132 3334 353637 383940 RH5/AN13 RH4/AN12 RF1/AN6/C2OUT RF0/AN5 AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0 VSS VDD A5/SS/AN4/LVDIN RA4/T0CKIRC1/T1OSI C0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT RK0 RK1 R R DS30475A-page 4 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 Pin Diagrams (Cont.’d) 84-Pin PLCC 20 1234567 PP PPPPPPP S CS SSSSSSS C CP PPPPPPP H1 H0 E2/E3E4 E5E6E7/D0/ DDC SS D1/D2/D3/D4/D5/D6/D7/J0J1 R R RRR RRRRVN VRRRRRRRRR 1110 9 8 7 6 5 4 3 2 1 84838281807978777675 RH2 12 74 RJ2 RH3 13 73 RJ3 RE1/WR 14 72 RB0/INT0 RE0/RD 15 71 RB1/INT1 RG0/CANTX1 16 70 RB2/INT2 RG1/CANTX2 17 69 RB3/INT3 RG2/CANRX 18 68 RB4 RG3 19 67 RB5 MCLR/VPP 20 66 RB6 RG4 21 65 VSS PIC18C858 NC 22 64 NC VSS 23 63 OSC2/CLKO/RA6 VDD 24 62 OSC1/CLKI RF7 25 61 VDD RF6/AN11 26 60 RB7 RF5/AN10/CVREF 27 59 RC5/SDO RF4/AN9 28 58 RC4/SDI/SDA RF3/AN8 29 57 RC3/SCK/SCL RF2/AN7/C1OUT 30 56 RC2/CCP1 RH7/AN15 31 55 RK3 RH6/AN14 32 54 RK2 3334353637383940414243444546474849505152 53 RH5/AN13 RH4/AN12RF1/AN6/C2OUT RF0/AN5 AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0NC VSS VDD A5/SS/AN4/LVDINRA4/T0CKI RC1/T1OSI C0/T1OSO/T13CKIRC6/TX/CK RC7/RX/DT RK0 RK1 R R  2000 Microchip Technology Inc. Advanced Information DS30475A-page 5

PIC18CXX8 Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Oscillator Configurations............................................................................................................................................................21 3.0 Reset..........................................................................................................................................................................................29 4.0 Memory Organization.................................................................................................................................................................41 5.0 Table Reads/Table Writes..........................................................................................................................................................65 6.0 8 X 8 Hardware Multiplier...........................................................................................................................................................71 7.0 Interrupts....................................................................................................................................................................................75 8.0 I/O Ports.....................................................................................................................................................................................89 9.0 Parallel Slave Port....................................................................................................................................................................109 10.0 Timer0 Module.........................................................................................................................................................................113 11.0 Timer1 Module.........................................................................................................................................................................117 12.0 Timer2 Module.........................................................................................................................................................................121 13.0 Timer3 Module.........................................................................................................................................................................123 14.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................127 15.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................135 16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)..............................................................167 17.0 CAN Module.............................................................................................................................................................................183 18.0 10-bit Analog-to-Digital Converter (A/D) Module......................................................................................................................227 19.0 Comparator Module..................................................................................................................................................................237 20.0 Comparator Voltage Reference Module...................................................................................................................................243 21.0 Low Voltage Detect..................................................................................................................................................................247 22.0 Special Features of the CPU....................................................................................................................................................251 23.0 Instruction Set Summary..........................................................................................................................................................261 24.0 Development Support...............................................................................................................................................................305 25.0 Electrical Characteristics..........................................................................................................................................................311 26.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................341 27.0 Packaging Information..............................................................................................................................................................343 Appendix A: Data Sheet Revision History......................................................................................................................................349 Appendix B: Device Differences.....................................................................................................................................................349 Appendix C: Device Migrations......................................................................................................................................................350 Appendix D: Migrating from other PICmicro Devices.....................................................................................................................350 Appendix E: Development Tool Version Requirements.................................................................................................................351 Index..................................................................................................................................................................................................353 On-Line Support.................................................................................................................................................................................361 Reader Response..............................................................................................................................................................................362 PIC18CXX8 Product Identification System........................................................................................................................................363 DS30475A-page 6 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Micro- chip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792- 4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: (cid:127) Microchip’s Worldwide Web site; http://www.microchip.com (cid:127) Your local Microchip sales office (see last page) (cid:127) The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit- erature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 7

PIC18CXX8 NOTES: DS30475A-page 8 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 1.0 DEVICE OVERVIEW The following two figures are device block diagrams sorted by pin count; 64/68-pin for Figure1-1 and This document contains device specific information for 80/84-pin for Figure1-2. The 64/68-pin and 80/84-pin the following three devices: pinouts are listed in Table1-2. 1. PIC18C658 2. PIC18C858 The PIC18C658 is available in 64-pin TQFP and 68-pin PLCC packages. The PIC18C858 is available in 80-pin TQFP and 84-pin PLCC packages. An overview of features is shown in Table1-1. TABLE 1-1: DEVICE FEATURES Features PIC18C658 PIC18C858 Operating Frequency DC - 40 MHz DC - 40 MHz Bytes 32 K 32 K Program Memory Internal # of Single word 16384 16384 Instructions Data Memory (Bytes) 1536 1536 Interrupt sources 21 21 I/O Ports Ports A – G Ports A – H, J, K Timers 4 4 Capture/Compare/PWM modules 2 2 MSSP, CAN MSSP, CAN Serial Communications Addressable USART Addressable USART Parallel Communications PSP PSP 10-bit Analog-to-Digital Module 12 input channels 16 input channels Analog Comparators 2 2 POR, BOR, POR, BOR, RESET Instruction, Stack Full, RESET Instruction, Stack Full, RESETS (and Delays) Stack Underflow Stack Underflow (PWRT, OST) (PWRT, OST) Programmable Low Voltage Detect Yes Yes Programmable Brown-out Reset Yes Yes CAN Module Yes Yes In-Circuit Serial Programming (ICSP™) Yes Yes Instruction Set 75 Instructions 75 Instructions 64-pin TQFP 80-pin TQFP 68-pin CERQUAD 84-pin CERQUAD Packages (Windowed) (Windowed) 68-pin PLCC 84-pin PLCC  2000 Microchip Technology Inc. Advanced Information DS30475A-page 9

PIC18CXX8 FIGURE 1-1: PIC18C658 BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0 RA1/AN1 Table Pointer<21> Data Latch 21 RA2/AN2/VREF- 8 8 Data RAM RA3/AN3/VREF+ RA4/T0CKI 21 inc/dec logic ( 1.5 K ) RA5/AN4/SS/LVDIN Address Latch RA6 20 PCLAT U PCLATH 12 PORTB Address<12> PCU PCH PCL RB0/INT0 Program Counter 4 12 4 RB1/INT1 Address Latch BSR FSR0 Bank0, F RB2/INT2 Program Memory 31 Level Stack FSR1 RB3/INT3 (32 Kbytes) FSR2 RB7:RB4 12 Data Latch PORTC inc/dec Decode logic RC0/T1OSO/T13CKI TABLELATCH RC1/T1OSI RC2/CCP1 16 8 RC3/SCK/SCL ROMLATCH RC4/SDI/SDA RC5/SDO RC6/TX/CK IR RC7/RX/DT PORTD 8 RD7/PSP7:RD0/PSP0 PRODH PRODL PORTE IDnestcroudcteio &n 8 x 8 Multiply RE0/RD Control 3 8 RE1/WR RE2/CS BITOP WREG RE3 Power-up 8 8 8 RE4 OSC2/CLKO Timer RE5 OSC1/CLKI Timing Oscillator 8 RE6 Generation Start-up Timer RE7/CCP2 Power-on ALU<8> PORTF Reset RF7 Watchdog 8 Timer RF6/AN11:RF0/AN5 Precision Brown-out Bandgap Reference Reset PORTG RG0/CANTX1 RG1/CANTX2 RG2/CANRX MCLR VDD, VSS RG3 RG4 BLVODR Timer0 Timer1 Timer2 Timer3 1A0D-bCit Synchronous Comparator CCP1 CCP2 USART CAN Module Serial Port DS30475A-page 10 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 1-2: PIC18C858 BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0 RA1/AN1 Table Pointer<21> Data Latch 21 RA2/AN2/VREF- 8 8 Data RAM RA3/AN3/VREF+ RA4/T0CKI 21 inc/dec logic ( 1.5 K ) RA5/AN4/SS/LVDIN Address Latch RA6 20 PCLAT U PCLATH 12 PORTB Address<12> PCU PCH PCL RB0/INT0 Program Counter 4 12 4 RB1/INT1 Address Latch BSR FSR0 Bank0, F RB2/INT2 Program Memory 31 Level Stack FSR1 RB3/INT3 (32 Kbytes) FSR2 RB7:RB4 12 Data Latch PORTC inc/dec Decode logic RC0/T1OSO/T13CKI TABLELATCH RC1/T1OSI RC2/CCP1 16 8 RC3/SCK/SCL ROMLATCH RC4/SDI/SDA RC5/SDO RC6/TX/CK IR RC7/RX/DT PORTD 8 RD7/PSP7:RD0/PSP0 PRODH PRODL PORTE Instruction 8 x 8 Multiply RE0/RD Decode & Control 3 8 RE1/WR RE2/CS BITOP WREG RE3 Power-up 8 8 8 RE4 OSC2/CLKO Timer RE5 OSC1/CLKI Timing Oscillator 8 RE6 Generation Start-up Timer RE7 Power-on ALU<8> PORTF Reset RF7 Watchdog 8 Timer RF6/AN11:RF0/AN5 Precision Brown-out Bandgap Reference Reset PORTG RG0/CANTX1 RG1/CANTX2 RG2/CANRX MCLR VDD, VSS RG3 RG4 PORTH PORTK PORTJ RH0 RK0 RJ0 RH1 RK1 RJ1 RH2 RK2 RJ2 RH3 RK3 RJ3 RH7/AN15:RH4/AN12 BLVODR Timer0 Timer1 Timer2 Timer3 1A0D-bCit Synchronous Comparator CCP1 CCP2 USART CAN Module Serial Port  2000 Microchip Technology Inc. Advanced Information DS30475A-page 11

PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name PIC18C658 PIC18C858 Type Type TQFP PLCC TQFP PLCC Description MCLR/VPP 7 16 9 20 MCLR I ST Master clear (RESET) input. This pin is an active low RESET to the device. VPP P Programming voltage input NC — 1, 18, — 1, 22, — — These pins should be left 35, 52 43, 64 unconnected OSC1/CLKI 39 50 49 62 OSC1 I CMOS/ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. CLKI I CMOS External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). OSC2/CLKO/RA6 40 51 50 63 OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate RA6 I/O TTL General purpose I/O pin Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) DS30475A-page 12 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18C658 PIC18C858 Type Type TQFP PLCC TQFP PLCC Description PORTA is a bi-directional I/O port RA0/AN0 24 34 30 42 RA0 I/O TTL Digital I/O AN0 I Analog Analog input 0 RA1/AN1 23 33 29 41 RA1 I/O TTL Digital I/O AN1 I Analog Analog input 1 RA2/AN2/VREF- 22 32 28 40 RA2 I/O TTL Digital I/O AN2 I Analog Analog input 2 VREF- I Analog A/D reference voltage (Low) input RA3/AN3/VREF+ 21 31 27 39 RA3 I/O TTL Digital I/O AN3 I Analog Analog input 3 VREF+ I Analog A/D reference voltage (High) input RA4/T0CKI 28 39 34 47 RA4 I/O ST/OD Digital I/O – Open drain when configured as output T0CKI I ST Timer0 external clock input RA5/AN4/SS/LVDIN 27 38 33 46 RA5 I/O TTL Digital I/O AN4 I Analog Analog input 4 SS I ST SPI slave select input LVDIN I Analog Low voltage detect input RA6 See the OSC2/CLKO/RA6 pin Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to VDD)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 13

PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18C658 PIC18C858 Type Type TQFP PLCC TQFP PLCC Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 48 60 58 72 RB0 I/O TTL Digital I/O INT0 I ST External interrupt 0 RB1/INT1 47 59 57 71 RB1 I/O TTL Digital I/O INT1 I ST External interrupt 1 RB2/INT2 46 58 56 70 RB2 I/O TTL Digital I/O INT2 I ST External interrupt 2 RB3/INT3 45 57 55 69 RB3 I/O TTL Digital I/O INT3 I/O ST External interrupt 3 RB4 44 56 54 68 I/O TTL Digital I/O Interrupt on change pin RB5 43 55 53 67 I/O TTL Digital I/O Interrupt-on-change pin RB6 42 54 52 66 I/O TTL Digital I/O Interrupt-on-change pin I ST ICSP programming clock RB7 37 48 47 60 I/O TTL Digital I/O Interrupt-on-change pin I/O ST ICSP programming data Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) DS30475A-page 14 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18C658 PIC18C858 Type Type TQFP PLCC TQFP PLCC Description PORTC is a bi-directional I/O port RC0/T1OSO/T13CKI 30 41 36 49 RC0 I/O ST Digital I/O T1OSO O — Timer1 oscillator output T13CKI I ST Timer1/Timer3 external clock input RC1/T1OSI 29 40 35 48 RC1 I/O ST Digital I/O T1OSI I CMOS Timer1 oscillator input RC2/CCP1 33 44 43 56 RC2 I/O ST Digital I/O CCP1 I/O ST Capture1 input/Compare1 output/PWM1 output RC3/SCK/SCL 34 45 44 57 RC3 I/O ST Digital I/O SCK I/O ST Synchronous serial clock input/output for SPI mode SCL I/O ST Synchronous serial clock input/output for I2C mode RC4/SDI/SDA 35 46 45 58 RC4 I/O ST Digital I/O SDI I ST SPI data in SDA I/O ST I2C data I/O RC5/SDO 36 47 46 59 RC5 I/O ST Digital I/O SDO O — SPI data out RC6/TX/CK 31 42 37 50 RC6 I/O ST Digital I/O TX O — USART asynchronous transmit CK I/O ST USART synchronous clock (See RX/DT) RC7/RX/DT 32 43 38 51 RC7 I/O ST Digital I/O RX I ST USART asynchronous receive DT I/O ST USART synchronous data (See TX/CK) Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to VDD)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 15

PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18C658 PIC18C858 Type Type TQFP PLCC TQFP PLCC Description PORTD is a bi-directional I/O port. These pins have TTL input buffers when external memory is enabled. RD0/PSP0 58 3 72 3 RD0 I/O ST Digital I/O PSP0 I/O TTL Parallel slave port data RD1/PSP1 55 67 69 83 RD1 I/O ST Digital I/O PSP1 I/O TTL Parallel slave port data RD2/PSP2 54 66 68 82 RD2 I/O ST Digital I/O PSP2 I/O TTL Parallel slave port data RD3/PSP3 53 65 67 81 RD3 I/O ST Digital I/O PSP3 I/O TTL Parallel slave port data RD4/PSP4 52 64 66 80 RD4 I/O ST Digital I/O PSP4 I/O TTL Parallel slave port data RD5/PSP5 51 63 65 79 RD5 I/O ST Digital I/O PSP5 I/O TTL Parallel slave port data RD6/PSP6 50 62 64 78 RD6 I/O ST Digital I/O PSP6 I/O TTL Parallel slave port data RD7/PSP7 49 61 63 77 RD7 I/O ST Digital I/O PSP7 I/O TTL Parallel slave port data Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) DS30475A-page 16 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18C658 PIC18C858 Type Type TQFP PLCC TQFP PLCC Description PORTE is a bi-directional I/O port RE0/RD 2 11 4 15 RE0 I/O ST Digital I/O RD I TTL Read control for parallel slave port (See WR and CS pins) RE1/WR 1 10 3 14 RE1 I/O ST Digital I/O WR I TTL Write control for parallel slave port (See CS and RD pins) RE2/CS 64 9 78 9 RE2 I/O ST Digital I/O CS I TTL Chip select control for parallel slave port (See RD and WR) RE3 63 8 77 8 I/O ST Digital I/O RE4 62 7 76 7 I/O ST Digital I/O RE5 61 6 75 6 I/O ST Digital I/O RE6 60 5 74 5 I/O ST Digital I/O RE7/CCP2 59 4 73 4 RE7 I/O ST Digital I/O CCP2 I/O ST Capture2 input, Compare2 output, PWM2 output Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to VDD)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 17

PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18C658 PIC18C858 Type Type TQFP PLCC TQFP PLCC Description PORTF is a bi-directional I/O port RF0/AN5 18 28 24 36 RF0 I/O ST Digital I/O AN5 I Analog Analog input 5 RF1/AN6/C2OUT 17 27 23 35 RF1 I/O ST Digital I/O AN6 I Analog Analog input 6 C2OUT O ST Comparator 2 output RF2/AN7/C1OUT 16 26 18 30 RF2 I/O ST Digital I/O AN7 I Analog Analog input 7 C1OUT O ST Comparator 1 output RF3/AN8 15 25 17 29 RF1 I/O ST Digital I/O AN8 I Analog Analog input 8 RF4/AN9 14 24 16 28 RF1 I/O ST Digital I/O AN9 I Analog Analog input 9 RF5/AN10/CVREF 13 23 15 27 RF1 I/O ST Digital I/O AN10 I Analog Analog input 10 CVREF O Analog Comparator VREF output RF6/AN11 12 22 14 26 RF6 I/O ST Digital I/O AN11 I Analog Analog input 11 RF7 11 21 13 25 I/O ST Digital I/O Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) DS30475A-page 18 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18C658 PIC18C858 Type Type TQFP PLCC TQFP PLCC Description PORTG is a bi-directional I/O port RG0/CANTX1 3 12 5 16 RG0 I/O ST Digital I/O CANTX1 O CAN Bus CAN bus output RG1/CANTX2 4 13 6 17 RG1 I/O ST Digital I/O CANTX2 O CAN Bus Complimentary CAN bus output or CAN bus bit time clock RG2/CANRX 5 14 7 18 RG2 I/O ST Digital I/O CANRX I CAN Bus CAN bus input RG3 6 15 8 19 I/O ST Digital I/O RG4 8 17 10 21 I/O ST Digital I/O PORTH is a bi-directional I/O port. RH0 — — 79 10 I/O ST Digital I/O RH1 — — 80 11 I/O ST Digital I/O RH2 — — 1 12 I/O ST Digital I/O RH3 — — 2 13 I/O ST Digital I/O RH4/AN12 — — 22 34 RH4 I/O ST Digital I/O AN12 I Analog Analog input 12 RH5/AN13 — — 21 33 RH5 I/O ST Digital I/O AN13 I Analog Analog input 13 RH6/AN14 — — 20 32 RH6 I/O ST Digital I/O AN14 I Analog Analog input 14 RH7/AN15 — — 19 31 RH7 I/O ST Digital I/O AN15 I Analog Analog input 15 Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to VDD)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 19

PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18C658 PIC18C858 Type Type TQFP PLCC TQFP PLCC Description PORTJ is a bi-directional I/O port RJ0 — — 62 76 RJ0 — — — — RJ0 I/O ST Digital I/O RJ1 — — 61 75 RJ1 — — — — RJ1 I/O ST Digital I/O RJ2 — — 60 74 RJ2 — — — — RJ2 I/O ST Digital I/O RJ3 — — 59 73 RJ3 — — — — RJ3 I/O ST Digital I/O PORTK is a bi-directional I/O port RK0 — — 39 52 I/O ST Digital I/O RK1 — — 40 53 I/O ST Digital I/O RK2 — — 41 54 I/O ST Digital I/O RK3 — — 42 55 I/O ST Digital I/O VSS 9, 25, 19, 36, 11, 31, 23, 44, P — Ground reference for logic and I/O pins 41, 56 53, 68 51, 70 65, 84 VDD 10, 26, 2, 20, 12, 32, 2, 24, P — Positive supply for logic and I/O pins 38, 57 37, 49 48, 71 45, 61 AVSS 20 30 26 38 P — Ground reference for analog modules AVDD 19 29 25 37 P — Positive supply for analog modules Legend: TTL= TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) DS30475A-page 20 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 2.0 OSCILLATOR FIGURE 2-1: CRYSTAL/CERAMIC CONFIGURATIONS RESONATOR OPERATION (HS, XT OR LP 2.1 Oscillator Types OSC CONFIGURATION) The PIC18CXX8 can be operated in one of eight oscil- C1(1) OSC1 lator modes, programmable by three configuration bits To (FOSC2, FOSC1, and FOSC0). internal 1. LP Low Power Crystal XTAL RF(3) logic 2. XT Crystal/Resonator SLEEP 3. HS High Speed Crystal/Resonator RS(2) 4. HS4 High Speed Crystal/Resonator with C2(1) OSC2 PIC18CXX8 PLL enabled 5. RC External Resistor/Capacitor Note 1: See Table2-1 and Table2-2 for recom- mended values of C1 and C2. 6. RCIO External Resistor/Capacitor with I/O pin enabled 2: A series resistor (RS) may be required 7. EC External Clock for AT strip cut crystals. 8. ECIO External Clock with I/O pin enabled 3: RF varies with the crystal chosen. 2.2 Crystal Oscillator/Ceramic Resonators In XT, LP, HS or HS4 (PLL) oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure2-1 shows the pin connections. An external clock source may also be connected to the OSC1 pin, as shown in Figure2-3 and Figure2-4. The PIC18CXX8 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 21

PIC18CXX8 TABLE 2-1: CERAMIC RESONATORS Note 1: Recommended values of C1 and C2 are Ranges Tested: identical to the ranges tested (Table2-1). Mode Freq OSC1 OSC2 2: Higher capacitance increases the stability XT 455 kHz 68 - 100 pF 68 - 100 pF of the oscillator, but also increases the 2.0 MHz 15 - 68 pF 15 - 68 pF start-up time. 4.0 MHz 15 - 68 pF 15 - 68 pF 3: Since each resonator/crystal has its own HS 8.0 MHz 10 - 68 pF 10 - 68 pF characteristics, the user should consult the 16.0 MHz 10 - 22 pF 10 - 22 pF resonator/crystal manufacturer for appropri- 20.0 MHz TBD TBD ate values of external components. 25.0 MHz TBD TBD 4: Rs may be required in HS mode, as well as HS+PLL 4.0 MHz TBD TBD XT mode, to avoid overdriving crystals with 8.0 MHz 10 - 68 pF 10 - 68 pF low drive level specification. 10.0 MHz TBD TBD These values are for design guidance only. See notes on this page. Resonators Used: 455 kHz Panasonic EFO-A455K04B ± 0.3% 2.0 MHz Murata Erie CSA2.00MG ± 0.5% 4.0 MHz Murata Erie CSA4.00MG ± 0.5% 8.0 MHz Murata Erie CSA8.00MT ± 0.5% 16.0 MHz Murata Erie CSA16.00MX ± 0.5% All resonators used did not have built-in capacitors. TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Cap. Range Cap. Range Osc Type Freq C1 C2 LP 32.0 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF XT 200 kHz 47-68 pF 47-68 pF 1.0 MHz 15 pF 15 pF 4.0 MHz 15 pF 15 pF HS 4.0 MHz 15 pF 15 pF 8.0 MHz 15-33 pF 15-33 pF 20.0 MHz 15-33 pF 15-33 pF 25.0 MHz TBD TBD HS+PLL 4.0 MHz 15 pF 15 pF 8.0 MHz 15-33 pF 15-33 pF 10.0 MHz TBD TBD These values are for design guidance only. See notes on this page. Crystals Used 32.0 kHz Epson C-001R32.768K-A ± 20 PPM 200 kHz STD XTL 200.000KHz ± 20 PPM 1.0 MHz ECS ECS-10-13-1 ± 50 PPM 4.0 MHz ECS ECS-40-20-1 ± 50 PPM 8.0 MHz EPSON CA-301 8.000M-C ± 30 PPM 20.0 MHz EPSON CA-301 20.000M-C ± 30 PPM DS30475A-page 22 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 2.3 RC Oscillator 2.4 External Clock Input For timing insensitive applications, the “RC” and The EC and ECIO oscillator modes require an external "RCIO" device options offer additional cost savings. clock source to be connected to the OSC1 pin. The The RC oscillator frequency is a function of the supply feedback device between OSC1 and OSC2 is turned voltage, the resistor (REXT) and capacitor (CEXT) val- off in these modes to save current. There is no oscilla- ues and the operating temperature. In addition to this, tor start-up time required after a Power-on Reset or the oscillator frequency will vary from unit to unit due after a recovery from SLEEP mode. to normal process parameter variation. Furthermore, In the EC oscillator mode, the oscillator frequency the difference in lead frame capacitance between divided by 4 is available on the OSC2 pin. This signal package types will also affect the oscillation frequency, may be used for test purposes or to synchronize other especially for low CEXT values. The user also needs to logic. Figure2-3 shows the pin connections for the EC take into account variation due to tolerance of external oscillator mode. R and C components used. Figure2-2 shows how the R/C combination is connected. FIGURE 2-3: EXTERNAL CLOCK INPUT In the RC oscillator mode, the oscillator frequency OPERATION divided by 4 is available on the OSC2 pin. This signal (EC OSC CONFIGURATION) may be used for test purposes or to synchronize other logic. Clock from OSC1 FIGURE 2-2: RC OSCILLATOR MODE ext. system PIC18CXX8 FOSC/4 OSC2 VDD REXT The ECIO oscillator mode functions like the EC mode, OSC1 Internal except that the OSC2 pin becomes an additional gen- clock eral purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure2-4 shows the pin connections CEXT PIC18CXX8 for the ECIO oscillator mode. VSS OSC2/CLKO/RA6 FOSC/4 FIGURE 2-4: EXTERNAL CLOCK INPUT or I/O OPERATION Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ (ECIO CONFIGURATION) CEXT > 20pF Clock from OSC1 The RCIO oscillator mode functions like the RC mode, ext. system PIC18CXX8 except that the OSC2 pin becomes an additional gen- eral purpose I/O pin. The I/O pin becomes bit 6 of RA6 I/O (OSC2) PORTA (RA6).  2000 Microchip Technology Inc. Advanced Information DS30475A-page 23

PIC18CXX8 2.5 HS4 (PLL) The PLL can only be enabled when the oscillator con- figuration bits are programmed for HS mode. If they A Phase Locked Loop circuit is provided as a pro- are programmed for any other mode, the PLL is not grammable option for users that want to multiply the enabled and the system clock will come directly from frequency of the incoming crystal oscillator signal by 4. OSC1. For an input clock frequency of 10 MHz, the internal The PLL is one of the modes of the FOSC2:FOSC0 clock frequency will be multiplied to 40 MHz. This is configuration bits. The oscillator mode is specified dur- useful for customers who are concerned with EMI due ing device programming. to high frequency crystals. A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out referred to as TPLL. FIGURE 2-5: PLL BLOCK DIAGRAM FOSC2:FOSC0 = ‘110’ OSC2 Phase Comparator FIN Loop VCO Crystal Filter Osc SYSCLK FOUT X U Divide by 4 M OSC1 DS30475A-page 24 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 2.6 Oscillator Switching Feature 2.6.1 SYSTEM CLOCK SWITCH BIT The PIC18CXX8 devices include a feature that allows The system clock source switching is performed under the system clock source to be switched from the main software control. The system clock switch bit, SCS oscillator to an alternate low frequency clock source. (OSCCON register), controls the clock switching. When For the PIC18CXX8 devices, this alternate clock the SCS bit is ’0’, the system clock source comes from source is the Timer1 oscillator. If a low frequency crys- the main oscillator selected by the FOSC2:FOSC0 con- tal (32 kHz, for example) has been attached to the figuration bits. When the SCS bit is set, the system clock Timer1 oscillator pins and the Timer1 oscillator has source will come from the Timer1 oscillator. The SCS bit been enabled, the device can switch to a low power is cleared on all forms of RESET. execution mode. Figure2-6 shows a block diagram of Note: The Timer1 oscillator must be enabled to the system clock sources. The clock switching feature switch the system clock source. The is enabled by programming the Oscillator Switching Timer1 oscillator is enabled by setting the Enable (OSCSEN) bit in Configuration register T1OSCEN bit in the Timer1 control register CONFIG1H to a ’0’. Clock switching is disabled in an (T1CON). If the Timer1 oscillator is not erased device. See Section 9 for further details of the enabled, any write to the SCS bit will be Timer1 oscillator. See Section22.0 for Configuration ignored (SCS bit forced cleared) and the Register details. main oscillator will continue to be the sys- tem clock source. FIGURE 2-6: DEVICE CLOCK SOURCES PIC18CXX8 Main Oscillator OSC2 Tosc/4 SLEEP 4 x PLL OSC1 TOSC M TSCLK U Timer 1 Oscillator X TT1P T1OSO T1OSCEN Enable Clock T1OSI Oscillator Source Clock Source option for other modules Note: I/O pins have diode protection to VDD and VSS. REGISTER 2-1: OSCCON REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 — — — — — — — SCS bit 7 bit 0 bit 7-1 Unimplemented: Read as '0' bit 0 SCS: System Clock Switch bit when OSCSEN configuration bit = ’0’ and T1OSCEN bit is set: 1 = Switch to Timer1 Oscillator/Clock pin 0 = Use primary Oscillator/Clock input pin when OSCSEN is clear or T1OSCEN is clear: bit is forced clear Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 25

PIC18CXX8 2.6.2 OSCILLATOR TRANSITIONS The sequence of events that takes place when switch- ing from the Timer1 oscillator to the main oscillator will The PIC18CXX8 devices contain circuitry to prevent depend on the mode of the main oscillator. In addition "glitches" when switching between oscillator sources. to eight clock cycles of the main oscillator, additional Essentially, the circuitry waits for eight rising edges of delays may take place. the clock source that the processor is switching to. If the main oscillator is configured for an external crys- This ensures that the new clock source is stable and tal (HS, XT, LP), the transition will take place after an that its pulse width will not be less than the shortest pulse width of the two clock sources. oscillator start-up time (TOST) has occurred. A timing diagram indicating the transition from the Timer1 oscil- A timing diagram indicating the transition from the lator to the main oscillator for HS, XT and LP modes is main oscillator to the Timer1 oscillator is shown in shown in Figure2-8. Figure2-7. The Timer1 oscillator is assumed to be running all the time. After the SCS bit is set, the pro- cessor is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after the synchronization cycles. FIGURE 2-7: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 TT1P T1OSI 1 2 3 4 5 6 7 8 Tscs OSC1 TOSC Internal CSylosctekm TDLY SCS (OSCCON<0>) Program PC PC + 2 PC + 4 Counter Note 1: Delay on internal system clock is eight oscillator cycles for synchronization. FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS,XT,LP) Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 TT1P T1OSI OSC1 1 2 3 4 5 6 7 8 TOST TSCS OSC2 TOSC Internal System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 4 Note 1: TOST = 1024TOSC (drawing not to scale). DS30475A-page 26 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 If the main oscillator is configured for HS4 (PLL) mode, If the main oscillator is configured in the RC, RCIO, EC an oscillator start-up time (TOST) plus an additional PLL or ECIO modes, there is no oscillator start-up time-out. time-out (TPLL) will occur. The PLL time-out is typically Operation will resume after eight cycles of the main 2 ms and allows the PLL to lock to the main oscillator oscillator have been counted. A timing diagram indicat- frequency. A timing diagram indicating the transition ing the transition from the Timer1 oscillator to the main from the Timer1 oscillator to the main oscillator for HS4 oscillator for RC, RCIO, EC and ECIO modes is shown mode is shown in Figure2-9. in Figure2-10. FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL) Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 TOST TPLL OSC2 TOSC TSCS PLL Clock 1 2 3 4 5 6 7 8 Input Internal System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 4 Note 1: TOST = 1024TOSC (drawing not to scale). FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC) Q3 Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI TOSC OSC1 1 2 3 4 5 6 7 8 OSC2 Internal System Clock SCS (OSCCON<0>) TSCS Program Counter PC PC + 2 PC + 4 Note 1: RC oscillator mode assumed.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 27

PIC18CXX8 2.7 Effects of SLEEP Mode on the 2.8 Power-up Delays On-chip Oscillator Power up delays are controlled by two timers, so that When the device executes a SLEEP instruction, the no external RESET circuitry is required for most appli- on-chip clocks and oscillator are turned off and the cations. The delays ensure that the device is kept in device is held at the beginning of an instruction cycle RESET until the device power supply and clock are sta- (Q1 state). With the oscillator off, the OSC1 and OSC2 ble. For additional information on RESET operation, signals will stop oscillating. Since all the transistor see Section3.0 RESET. switching currents have been removed, SLEEP mode The first timer is the Power-up Timer (PWRT), which achieves the lowest current consumption of the device optionally provides a fixed delay of TPWRT (parameter (only leakage currents). Enabling any on-chip feature #33) on power-up only (POR and BOR). The second that will operate during SLEEP will increase the current timer is the Oscillator Start-up Timer (OST), intended to consumed during SLEEP. The user can wake from keep the chip in RESET until the crystal oscillator is SLEEP through external RESET, Watchdog Timer stable. Reset or through an interrupt. With the PLL enabled (HS4 oscillator mode), the time-out sequence following a Power-on Reset is differ- ent from other oscillator modes. The time-out sequence is as follows: the PWRT time-out is invoked after a POR time delay has expired, then the Oscillator Start-up Timer (OST) is invoked. However, this is still not a suf- ficient amount of time to allow the PLL to lock at high frequencies. The PWRT timer is used to provide an additional time-out. This time is called TPLL (parameter #7) to allow the PLL ample time to lock to the incoming clock frequency. TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC Floating, external resistor should pull high At logic low RCIO Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating Configured as PORTA, bit 6 EC Floating At logic low LP, XT, and HS Feedback inverter disabled, at quiescent Feedback inverter disabled, at quiescent voltage level voltage level Note: See Table3-1 in Section3.0 RESET, for time-outs due to SLEEP and MCLR Reset. DS30475A-page 28 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 3.0 RESET state on Power-on Reset, MCLR, WDT Reset, Brown-out Reset, MCLR Reset during SLEEP and by The PIC18CXX8 differentiates between various kinds the RESET instruction. of RESET: Most registers are not affected by a WDT wake-up, a) Power-on Reset (POR) since this is viewed as the resumption of normal oper- b) MCLR Reset during normal operation ation. Status bits from the RCON register, RI, TO, PD, c) MCLR Reset during SLEEP POR and BOR are set or cleared differently in different d) Watchdog Timer (WDT) Reset (during normal RESET situations, as indicated in Table3-2. These bits operation) are used in software to determine the nature of the RESET. See Table3-3 for a full description of the e) Programmable Brown-out Reset (PBOR) RESET states of all registers. f) RESET Instruction A simplified block diagram of the on-chip RESET circuit g) Stack Full Reset is shown in Figure3-1. h) Stack Underflow Reset The Enhanced MCU devices have a MCLR noise filter Most registers are unaffected by a RESET. Their status in the MCLR Reset path. The filter will detect and is unknown on POR and unchanged by all other ignore small pulses. RESETs. The other registers are forced to a “RESET” A WDT Reset does not drive MCLR pin low. FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLR SLEEP WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out Reset BOREN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1 PWRT On-chip RC OSC (1) 10-bit Ripple Counter Enable PWRT Enable OST (2) Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table3-1 for time-out situations.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 29

PIC18CXX8 3.1 Power-on Reset (POR) 3.2 Power-up Timer (PWRT) A Power-on Reset pulse is generated on-chip when a The Power-up Timer provides a fixed nominal time-out VDD rise is detected. To take advantage of the POR cir- (parameter #33), only on power-up from the POR. The cuitry, connect the MCLR pin directly (or through a Power-up Timer operates on an internal RC oscillator. resistor) to VDD. This will eliminate external RC compo- The chip is kept in RESET as long as the PWRT is nents usually needed to create a Power-on Reset active. The PWRT’s time delay allows VDD to rise to an delay. A minimum rise rate for VDD is specified (param- acceptable level. A configuration bit (PWRTEN in eter D004). For a slow rise time, see Figure3-2. CONFIG2L register) is provided to enable/disable the PWRT. When the device starts normal operation (exits the RESET condition), device operating parameters (volt- The power-up time delay will vary from chip to chip due age, frequency, temperature,...) must be met to ensure to VDD, temperature and process variation. See DC operation. If these conditions are not met, the device parameter #33 for details. must be held in RESET until the operating conditions 3.3 Oscillator Start-up Timer (OST) are met. Brown-out Reset may be used to meet the voltage start-up condition. The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the FIGURE 3-2: EXTERNAL POWER-ON PWRT delay is over (parameter #32). This ensures that RESET CIRCUIT (FOR SLOW the crystal oscillator or resonator has started and stabi- VDD POWER-UP) lized. The OST time-out is invoked only for XT, LP, HS and VDD HS4 modes and only on Power-on Reset or wake-up from SLEEP. D R 3.4 PLL Lock Time-out R1 MCLR With the PLL enabled, the time-out sequence following C PIC18CXX8 a Power-on Reset is different from other oscillator modes. A portion of the Power-up Timer is used to pro- vide a fixed time-out that is sufficient for the PLL to lock Note 1: External Power-on Reset circuit is required to the main oscillator frequency. This PLL lock time-out only if the VDD power-up slope is too slow. (TPLL) is typically 2 ms and follows the oscillator The diode D helps discharge the capacitor start-up time-out (OST). quickly when VDD powers down. 2: R < 40 kΩ is recommended to make sure 3.5 Brown-out Reset (BOR) that the voltage drop across R does not A configuration bit, BOREN, can disable (if violate the device’s electrical specification. 3: R1 = 100Ω to 1 kΩ will limit any current clear/programmed) or enable (if set) the Brown-out flowing into MCLR from external capacitor Reset circuitry. If VDD falls below parameter D005 for greater than parameter #35, the brown-out situation C in the event of MCLR/VPP pin break- down due to Electrostatic Discharge resets the chip. A RESET may not occur if VDD falls below parameter D005 for less than parameter #35. (ESD) or Electrical Overstress (EOS). The chip will remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will then be invoked and will keep the chip in RESET an additional time delay (parameter #33). If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer will execute the additional time delay. DS30475A-page 30 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 3.6 Time-out Sequence Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. On power-up, the time-out sequence is as follows: Bringing MCLR high will begin execution immediately First, PWRT time-out is invoked after the POR time (Figure3-5). This is useful for testing purposes or to delay has expired, then OST is activated. The total synchronize more than one PIC18CXX8 device operat- time-out will vary based on oscillator configuration and ing in parallel. the status of the PWRT. For example, in RC mode with Table3-2 shows the RESET conditions for some Spe- the PWRT disabled, there will be no time-out at all. cial Function Registers, while Table3-3 shows the Figure3-3, Figure3-4, Figure3-5, Figure3-6 and RESET conditions for all registers. Figure3-7 depict time-out sequences on power-up. TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) Wake-up from Oscillator Brown-out(2) SLEEP or Configuration PWRTEN = 0 PWRTEN = 1 Oscillator Switch HS with PLL enabled(1) 72 ms + 1024Tosc + 2 ms 1024Tosc + 2 ms 72 ms + 1024Tosc + 2 ms 1024Tosc + 2 ms HS, XT, LP 72 ms + 1024Tosc 1024Tosc 72 ms + 1024Tosc 1024Tosc EC 72 ms — 72 ms — External RC 72 ms — 72 ms — Note 1: 2 ms = Nominal time required for the 4X PLL to lock. 2: 72 ms is the nominal power-up timer delay. REGISTER 3-1: RCON REGISTER BITS AND POSITIONS R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IPEN LWRT — RI TO PD POR BOR bit 7 bit 0 TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program RCON Condition RI TO PD POR BOR STKFUL STKUNF Counter Register Power-on Reset 0000h 00-1 1100 1 1 1 0 0 u u MCLR Reset during normal 0000h 00-u uuuu u u u u u u u operation Software Reset during normal 0000h 0u-0 uuuu 0 u u u u u u operation Stack Full Reset during normal 0000h 0u-u uu11 u u u 1 1 u 1 operation Stack Underflow Reset during 0000h 0u-u uu11 u u u 1 1 1 u normal operation MCLR Reset during SLEEP 0000h 00-u 10uu u 1 0 u u u u WDT Reset 0000h 0u-u 01uu u 0 1 u u u u WDT Wake-up PC + 2 uu-u 00uu u 0 0 u u u u Brown-out Reset 0000h 0u-1 11u0 1 1 1 u 0 u u Interrupt wake-up from SLEEP PC + 2(1) uu-u 00uu u 0 0 u u u u Legend: u = unchanged, x = unknown,- = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h).  2000 Microchip Technology Inc. Advanced Information DS30475A-page 31

PIC18CXX8 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30475A-page 32 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 0V 1V MCLR INTERNAL POR TDEADTIME TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 33

PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Reset Applicable Power-on Reset, WDT Reset Wake-up via WDT Register Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TOSU 658 858 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 658 858 0000 0000 0000 0000 uuuu uuuu(3) TOSL 658 858 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 658 858 00-0 0000 00-0 0000 uu-u uuuu(3) PCLATU 658 858 ---0 0000 ---0 0000 ---u uuuu PCLATH 658 858 0000 0000 0000 0000 uuuu uuuu PCL 658 858 0000 0000 0000 0000 PC + 2(2) TBLPTRU 658 858 --00 0000 --00 0000 --uu uuuu TBLPTRH 658 858 0000 0000 0000 0000 uuuu uuuu TBLPTRL 658 858 0000 0000 0000 0000 uuuu uuuu TABLAT 658 858 0000 0000 0000 0000 uuuu uuuu PRODH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 658 858 0000 000x 0000 000u uuuu uuuu(1) INTCON2 658 858 1111 1111 1111 1111 uuuu uuuu(1) INTCON3 658 858 1100 0000 1100 0000 uuuu uuuu(1) INDF0 658 858 N/A N/A N/A POSTINC0 658 858 N/A N/A N/A POSTDEC0 658 858 N/A N/A N/A PREINC0 658 858 N/A N/A N/A PLUSW0 658 858 N/A N/A N/A FSR0H 658 858 ---- 0000 ---- 0000 ---- uuuu FSR0L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu WREG 658 858 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 658 858 N/A N/A N/A POSTINC1 658 858 N/A N/A N/A POSTDEC1 658 858 N/A N/A N/A PREINC1 658 858 N/A N/A N/A PLUSW1 658 858 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. DS30475A-page 34 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Applicable Power-on Reset, WDT Reset Wake-up via WDT Register Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets FSR1H 658 858 ---- 0000 ---- 0000 ---- uuuu FSR1L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu BSR 658 858 ---- 0000 ---- 0000 ---- uuuu INDF2 658 858 N/A N/A N/A POSTINC2 658 858 N/A N/A N/A POSTDEC2 658 858 N/A N/A N/A PREINC2 658 858 N/A N/A N/A PLUSW2 658 858 N/A N/A N/A FSR2H 658 858 ---- 0000 ---- 0000 ---- uuuu FSR2L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 658 858 ---x xxxx ---u uuuu ---u uuuu TMR0H 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TMR0L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 658 858 1111 1111 1111 1111 uuuu uuuu OSCCON 658 858 ---- ---0 ---- ---0 ---- ---u LVDCON 658 858 --00 0101 --00 0101 --uu uuuu WDTCON 658 858 ---- ---0 ---- ---0 ---- ---u RCON(4, 6) 658 858 00-1 11q0 00-1 qquu uu-u qquu TMR1H 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 658 858 0-00 0000 u-uu uuuu u-uu uuuu TMR2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PR2 658 858 1111 1111 1111 1111 1111 1111 T2CON 658 858 -000 0000 -000 0000 -uuu uuuu SSPBUF 658 858 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 658 858 0000 0000 0000 0000 uuuu uuuu SSPSTAT 658 858 0000 0000 0000 0000 uuuu uuuu SSPCON1 658 858 0000 0000 0000 0000 uuuu uuuu SSPCON2 658 858 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 35

PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Applicable Power-on Reset, WDT Reset Wake-up via WDT Register Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets ADRESH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 658 858 --00 0000 --00 0000 --uu uuuu ADCON1 658 858 --00 0000 --00 0000 --uu uuuu ADCON2 658 858 0--- -000 0--- -000 u--- -uuu CCPR1H 658 858 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 658 858 --00 0000 --00 0000 --uu uuuu CCPR2H 658 858 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 658 858 --00 0000 --00 0000 --uu uuuu CVRCON 658 858 0000 0000 0000 0000 uuuu uuuu CMCON 658 858 0000 0000 0000 0000 uuuu uuuu TMR3H 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 658 858 0000 0000 uuuu uuuu uuuu uuuu PSPCON 658 858 0000 ---- 0000 ---- uuuu ---- SPBRG 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RCREG 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXREG 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXSTA 658 858 0000 -01x 0000 -01u uuuu -uuu RCSTA 658 858 0000 000x 0000 000u uuuu uuuu IPR3 658 858 1111 1111 1111 1111 uuuu uuuu PIR3 658 858 0000 0000 0000 0000 uuuu uuuu PIE3 658 858 0000 0000 0000 0000 uuuu uuuu IPR2 658 858 -1-- 1111 -1-- 1111 -u-- uuuu PIR2 658 858 -0-- 0000 -0-- 0000 -u-- uuuu(1) PIE2 658 858 -0-- 0000 -0-- 0000 -u-- uuuu IPR1 658 858 1111 1111 1111 1111 uuuu uuuu 658 858 -111 1111 -111 1111 -uuu uuuu PIR1 658 858 0000 0000 0000 0000 uuuu uuuu(1) 658 858 -000 0000 -000 0000 -uuu uuuu(1) PIE1 658 858 0000 0000 0000 0000 uuuu uuuu 658 858 -000 0000 -000 0000 -uuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. DS30475A-page 36 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Applicable Power-on Reset, WDT Reset Wake-up via WDT Register Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TRISJ(7) - 858 1111 1111 1111 1111 uuuu uuuu TRISH(7) - 858 1111 1111 1111 1111 uuuu uuuu TRISG 658 858 ---1 1111 ---1 1111 ---u uuuu TRISF 658 858 1111 1111 1111 1111 uuuu uuuu TRISE 658 858 1111 1111 1111 1111 uuuu uuuu TRISD 658 858 1111 1111 1111 1111 uuuu uuuu TRISC 658 858 1111 1111 1111 1111 uuuu uuuu TRISB 658 858 1111 1111 1111 1111 uuuu uuuu TRISA(5) 658 858 -111 1111(5) -111 1111(5) -uuu uuuu(5) LATJ(7) - 858 xxxx xxxx uuuu uuuu uuuu uuuu LATH(7) - 858 xxxx xxxx uuuu uuuu uuuu uuuu LATG 658 858 ---x xxxx ---u uuuu ---u uuuu LATF 658 858 xxxx xxxx uuuu uuuu uuuu uuuu LATE 658 858 xxxx xxxx uuuu uuuu uuuu uuuu LATD 658 858 xxxx xxxx uuuu uuuu uuuu uuuu LATC 658 858 xxxx xxxx uuuu uuuu uuuu uuuu LATB 658 858 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 658 858 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5) PORTJ(7) - 858 xxxx xxxx uuuu uuuu uuuu uuuu PORTH(7) - 858 0000 xxxx 0000 uuuu uuuu uuuu PORTG 658 858 ---x xxxx ---u uuuu ---u uuuu PORTF 658 858 x000 0000 u000 0000 uuuu uuuu PORTE 658 858 --00 xxxx uuuu u000 uuuu uuuu PORTD 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5) 658 858 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5) TRISK 658 858 1111 1111 1111 1111 uuuu uuuu LATK 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PORTK 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXERRCNT 658 858 0000 0000 0000 0000 uuuu uuuu RXERRCNT 658 858 0000 0000 0000 0000 uuuu uuuu COMSTAT 658 858 0000 0000 0000 0000 uuuu uuuu CIOCON 658 858 1000 ---- 1000 ---- uuuu ---- BRGCON3 658 858 -0-- -000 -0-- -000 -u-- -uuu BRGCON2 658 858 0000 0000 0000 0000 uuuu uuuu BRGCON1 658 858 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 37

PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Applicable Power-on Reset, WDT Reset Wake-up via WDT Register Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets CANCON 658 858 xxxx xxx- uuuu uuu- uuuu uuu- CANSTAT 658 858 xxx- xxx- uuu- uuu- uuu- uuu- RXB0D7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0DLC 658 858 0xxx xxxx 0uuu uuuu uuuu uuuu RXB0EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0SIDL 658 858 xxxx x-xx uuuu u-uu uuuu u-uu RXB0SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0CON 658 858 000- 0000 000- 0000 uuu- uuuu RXB1D7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1DLC 658 858 0xxx xxxx 0uuu uuuu uuuu uuuu RXB1EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1SIDL 658 858 xxxx x0xx uuuu u0uu uuuu uuuu RXB1SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1CON 658 858 0000 0000 0000 0000 uuuu uuuu TXB0D7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. DS30475A-page 38 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Applicable Power-on Reset, WDT Reset Wake-up via WDT Register Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TXB0D0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0DLC 658 858 0x00 xxxx 0u00 uuuu uuuu uuuu TXB0EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0SIDL 658 858 xxx0 x0xx uuu0 u0uu uuuu uuuu TXB0SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0CON 658 858 0000 0000 0000 0000 uuuu uuuu TXB1D7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1DLC 658 858 0x00 xxxx 0u00 uuuu uuuu uuuu TXB1EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1SIDL 658 858 xxx0 x0xx uuu0 u0uu uuuu uuuu TXB1SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1CON 658 858 0000 0000 0000 0000 uuuu uuuu TXB2D7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2DLC 658 858 0x00 xxxx 0u00 uuuu uuuu uuuu TXB2EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2SIDL 658 858 xxx0 x0xx uuu0 u0uu uuuu uuuu TXB2SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2CON 658 858 0000 0000 0000 0000 uuuu uuuu RXM1EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXM1EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 39

PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Applicable Power-on Reset, WDT Reset Wake-up via WDT Register Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets RXM1SIDL 658 858 xxx- --xx uuu- --uu uuu- --uu RXM1SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXM0SIDL 658 858 xxx- --xx uuu- --uu uuu- --uu RXM0SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF5SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF5SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF4SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF4SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF3SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF3SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF2SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF2SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF1SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF1SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF0SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF0SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. DS30475A-page 40 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR There are two memory blocks in Enhanced MCU PIC18C658/858 devices. These memory blocks are: (cid:127) Program Memory PC<20:0> (cid:127) Data Memory 21 Each block has its own bus so that concurrent access Stack Level 1 can occur. • • • 4.1 Program Memory Organization Stack Level 31 The PIC18CXX8 devices have a 21-bit program RESET Vector 0000h counter that is capable of addressing the 2 Mbyte High Priority Interrupt Vector 0008h program memory space. Low Priority Interrupt Vector 0018h The reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. Figure4-1 shows the diagram for program memory map and stack for the PIC18C658 and PIC18C858. 4.1.1 INTERNAL PROGRAM MEMORY On-chip OPERATION Program Memory e c a p All devices have 32 Kbytes of internal EPROM program S memory. This means that the PIC18CXX8 devices can ory store up to 16K of single word instructions. Accessing m e a location between the physically implemented mem- M ory and the 2 Mbyte address will cause a read of all '0's 7FFFh ser U (a NOP instruction). 8000h Read ’1’ 1FFFFFh  2000 Microchip Technology Inc. Advanced Information DS30475A-page 41

PIC18CXX8 4.2 Return Address Stack 4.2.2 RETURN STACK POINTER (STKPTR) The return address stack allows any combination of up The STKPTR register contains the stack pointer value, to 31 program calls and interrupts to occur. The PC the STKFUL (stack full) status bit, and the STKUNF (Program Counter) is pushed onto the stack when a (stack underflow) status bits. Register4-1 shows the PUSH, CALL or RCALL instruction is executed, or an STKPTR register. The value of the stack pointer can be interrupt is acknowledged. The PC value is pulled off 0 through 31. The stack pointer increments when val- the stack on a RETURN, RETLW or a RETFIE instruc- ues are pushed onto the stack and decrements when tion. PCLATU and PCLATH are not affected by any of values are popped off the stack. At RESET, the stack the return instructions. pointer value will be 0. The user may read and write the stack pointer value. This feature can be used by a Real The stack operates as a 31 word by 21-bit stack mem- Time Operating System for return stack maintenance. ory and a 5-bit stack pointer, with the stack pointer ini- tialized to 00000b after all RESETs. There is no RAM After the PC is pushed onto the stack 31 times (without associated with stack pointer 00000b. This is only a popping any values off the stack), the STKFUL bit is RESET value. During a CALL type instruction causing set. The STKFUL bit can only be cleared in software or a push onto the stack, the stack pointer is first incre- by a POR. mented and the RAM location pointed to by the stack The action that takes place when the stack becomes pointer is written with the contents of the PC. During a full depends on the state of the STVREN (stack over- RETURN type instruction causing a pop from the stack, flow RESET enable) configuration bit. Refer to Section the contents of the RAM location indicated by the 18 for a description of the device configuration bits. If STKPTR is transferred to the PC and then the stack STVREN is set (default) the 31st push will push the pointer is decremented. (PC+ 2) value onto the stack, set the STKFUL bit, and The stack space is not part of either program or data reset the device. The STKFUL bit will remain set and space. The stack pointer is readable and writable, and the stack pointer will be set to 0. the data on the top of the stack is readable and writable If STVREN is cleared, the STKFUL bit will be set on the through SFR registers. Status bits indicate if the stack 31st push and the stack pointer will increment to 31. pointer is at or beyond the 31 levels provided. The 32nd push will overwrite the 31st push (and so on), while STKPTR remains at 31. 4.2.1 TOP-OF-STACK ACCESS When the stack has been popped enough times to The top of the stack is readable and writable. Three unload the stack, the next pop will return a value of zero register locations, TOSU, TOSH and TOSL allow to the PC and sets the STKUNF bit, while the stack access to the contents of the stack location indicated pointer remains at 0. The STKUNF bit will remain set by the STKPTR register. This allows users to imple- until cleared in software or a POR occurs. ment a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the value by reading the TOSU, TOSH and TOSL registers. program to the RESET vector, where the These values can be placed on a user defined software stack conditions can be verified and appro- stack. At return time, the software can replace the priate actions can be taken. TOSU, TOSH and TOSL and do a return. The user should disable the global interrupt enable bits during this time to prevent inadvertent stack opera- tions. DS30475A-page 42 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 4-1: STKPTR - STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as '0' bit 4-0 SP4:SP0: Stack Pointer Location bits Note: Bit 7 and bit 6 can only be cleared in user software or by a POR. Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared C = Clearable bit FIGURE 4-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU TOSH TOSL STKPTR<4:0> 0x00 0x1A 0x34 00010 00011 Top-of-Stack 0x001A34 00010 0x000D58 00001 0x000000 00000(1) Note 1: No RAM associated with this address; always maintained ‘0’s.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 43

PIC18CXX8 4.2.3 PUSH AND POP INSTRUCTIONS 4.3 Fast Register Stack Since the Top-of-Stack (TOS) is readable and writable, A “fast return” option is available for interrupts and the ability to push values onto the stack and pull values calls. A fast register stack is provided for the STATUS, off the stack without disturbing normal program execu- WREG and BSR registers and is only one layer in tion is a desirable option. To push the current PC value depth. The stack is not readable or writable and is onto the stack, a PUSH instruction can be executed. loaded with the current value of the corresponding reg- This will increment the stack pointer and load the cur- ister when the processor vectors for an interrupt. The rent PC value onto the stack. TOSU, TOSH and TOSL values in the fast register stack are then loaded back can then be modified to place a return address on the into the working registers if the fast return instruc- stack. tion is used to return from the interrupt. The POP instruction discards the current TOS by decre- A low or high priority interrupt source will push values menting the stack pointer. The previous value pushed into the stack registers. If both low and high priority onto the stack then becomes the TOS value. interrupts are enabled, the stack registers cannot be used reliably for low priority interrupts. If a high priority 4.2.4 STACK FULL/UNDERFLOW RESETS interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority inter- These RESETs are enabled by programming the rupt will be overwritten. STVREN configuration bit. When the STVREN bit is disabled, a full or underflow condition will set the appro- If high priority interrupts are not disabled during low pri- priate STKFUL or STKUNF bit, but not cause a device ority interrupts, users must save the key registers in RESET. When the STVREN bit is enabled, a full or software during a low priority interrupt. underflow will set the appropriate STKFUL or STKUNF If no interrupts are used, the fast register stack can be bit and then cause a device RESET. The STKFUL or used to restore the STATUS, WREG and BSR registers STKUNF bits are only cleared by the user software or at the end of a subroutine call. To use the fast register a POR. stack for a subroutine call, a fast call instruction must be executed. Example4-1 shows a source code example that uses the fast register stack. EXAMPLE 4-1: FAST REGISTER STACK CODE EXAMPLE CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK • • SUB1 • • • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK DS30475A-page 44 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 4.4 PCL, PCLATH and PCLATU The contents of PCLATH and PCLATU will be trans- ferred to the program counter by an operation that The program counter (PC) specifies the address of the writes PCL. Similarly, the upper two bytes of the pro- instruction to fetch for execution. The PC is 21-bits gram counter will be transferred to PCLATH and wide. The low byte is called the PCL register. This reg- PCLATU by an operation that reads PCL. This is useful ister is readable and writable. The high byte is called for computed offsets to the PC (See Section4.8.1). the PCH register. This register contains the PC<15:8> bits and is not directly readable or writable. Updates to 4.5 Clocking Scheme/Instruction Cycle the PCH register may be performed through the The clock input (from OSC1) is internally divided by PCLATH register. The upper byte is called PCU. This four to generate four non-overlapping quadrature register contains the PC<20:16> bits and is not directly clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro- readable or writable. Updates to the PCU register may gram counter (PC) is incremented every Q1, the be performed through the PCLATU register. instruction is fetched from the program memory and The PC addresses bytes in the program memory. To latched into the instruction register in Q4. The instruc- prevent the PC from becoming misaligned with word tion is decoded and executed during the following Q1 instructions, the LSb of PCL is fixed to a value of ’0’. through Q4. The clocks and instruction execution flow The PC increments by 2 to address sequential instruc- are shown in Figure4-3. tions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. FIGURE 4-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC+2 PC+4 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-2) Fetch INST (PC+2) Execute INST (PC) Fetch INST (PC+4) Execute INST (PC+2)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 45

PIC18CXX8 4.6 Instruction Flow/Pipelining 4.7 Instructions in Program Memory An “Instruction Cycle” consists of four Q cycles (Q1, The program memory is addressed in bytes. Instruc- Q2, Q3 and Q4). The instruction fetch and execute are tions are stored as two bytes or four bytes in program pipelined such that fetch takes one instruction cycle memory. The Least Significant Byte of an instruction while decode and execute takes another instruction word is always stored in a program memory location cycle. However, due to the pipelining, each instruction with an even address (LSB = ’0’). Figure4-1 shows an effectively executes in one cycle. If an instruction example of how instruction words are stored in the pro- causes the program counter to change (e.g., GOTO), gram memory. To maintain alignment with instruction two cycles are required to complete the instruction boundaries, the PC increments in steps of 2 and the (Example4-2). LSB will always read ’0’ (See Section4.4). A fetch cycle begins with the program counter (PC) The CALL and GOTO instructions have an absolute pro- incrementing in Q1. gram memory address embedded into the instruction. Since instructions are always stored on word bound- In the execution cycle, the fetched instruction is latched aries, the data contained in the instruction is a word into the “Instruction Register” (IR) in cycle Q1. This address. The word address is written to PC<20:1>, instruction is then decoded and executed during the which accesses the desired byte address in program Q2, Q3, and Q4 cycles. Data memory is read during Q2 memory. Instruction #2 in Figure4-1 shows how the (operand read) and written during Q4 (destination instruction “GOTO 000006h” is encoded in the program write). memory. Program branch instructions that encode a rel- ative address offset operate in the same manner. The offset value stored in a branch instruction represents the number of single word instructions by which the PC will be offset. Section23.0 provides further details of the instruction set. EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. TABLE 4-1: INSTRUCTIONS IN PROGRAM MEMORY Instruction Opcode Memory Address — 000007h MOVLW 055h 0E55h 55h 000008h 0Eh 000009h GOTO 000006h EF03h, F000h 03h 00000Ah EFh 00000Bh 00h 00000Ch F0h 00000Dh MOVFF 123h, 456h C123h, F456h 23h 00000Eh C1h 00000Fh 56h 000010h F4h 000011h — 000012h DS30475A-page 46 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 4.7.1 TWO WORD INSTRUCTIONS 4.8.1 COMPUTED GOTO The PIC18CXX8 devices have 4 two word instructions: A computed GOTO is accomplished by adding an offset MOVFF, CALL, GOTO and LFSR. The second word of to the program counter (ADDWF PCL). these instructions has the 4 MSB’s set to 1’s and is a A lookup table can be formed with an ADDWF PCL special kind of NOP instruction. The lower 12 bits of the instruction and a group of RETLW 0xnn instructions. second word contain data to be used by the instruction. WREG is loaded with an offset into the table before exe- If the first word of the instruction is executed, the data cuting a call to that table. The first instruction of the called in the second word is accessed. If the second word of routine is the ADDWF PCL instruction. The next instruc- the instruction is executed by itself (first word was tion executed will be one of the RETLW 0xnn instruc- skipped), it will execute as a NOP. This action is neces- tions that returns the value 0xnn to the calling function. sary when the two word instruction is preceded by a conditional instruction that changes the PC. A program The offset value (value in WREG) specifies the number example that demonstrates this concept is shown in of bytes that the program counter should advance. Example4-3. Refer to Section 19.0 for further details of In this method, only one data byte may be stored in the instruction set. each instruction location and room on the return address stack is required. 4.8 Lookup Tables Warning: The LSb of PCL is fixed to a value of ‘0’. Lookup tables are implemented two ways. These are: Hence, computed GOTO to an odd (cid:127) Computed GOTO address is not possible. (cid:127) Table Reads 4.8.2 TABLE READS/TABLE WRITES A better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. Lookup table data may be stored as 2 bytes per pro- gram word by using table reads and writes. The table pointer (TBLPTR) specifies the byte address and the table latch (TABLAT) contains the data that is read from, or written to, program memory. Data is trans- ferred to/from program memory one byte at a time. A description of the Table Read/Table Write operation is shown in Section5.0. EXAMPLE 4-3: TWO WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction 1111 0100 0101 0110 ; 2nd operand holds address of REG2 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes 1111 0100 0101 0110 ; 2nd operand becomes NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code  2000 Microchip Technology Inc. Advanced Information DS30475A-page 47

PIC18CXX8 4.9 Data Memory Organization 4.9.1 GENERAL PURPOSE REGISTER FILE The data memory is implemented as static RAM. Each The register file can be accessed either directly or indi- register in the data memory has a 12-bit address, rectly. Indirect addressing operates through the File allowing up to 4096 bytes of data memory. Figure4-4 Select Registers (FSR). The operation of indirect shows the data memory organization for the addressing is shown in Section4.12. PIC18CXX8 devices. Enhanced MCU devices may have banked memory in The data memory map is divided into as many as 16 the GPR area. GPR’s are not initialized by a Power-on banks that contain 256 bytes each. The lower 4 bits of Reset and are unchanged on all other RESETS. the Bank Select Register (BSR<3:0>) select which Data RAM is available for use as GPR registers by all bank will be accessed. The upper 4 bits for the BSR are instructions. Bank 15 (0xF00 to 0xFFF) contains not implemented. SFR’s. All other banks of data memory contain GPR The data memory contains Special Function Registers registers starting with bank 0. (SFR) and General Purpose Registers (GPR). The 4.9.2 SPECIAL FUNCTION REGISTERS SFR’s are used for control and status of the controller and peripheral functions, while GPR’s are used for data The Special Function Registers (SFR’s) are registers storage and scratch pad operations in the user’s appli- used by the CPU and Peripheral Modules for control- cation. The SFR’s start at the last location of Bank 15 ling the desired operation of the device. These regis- (0xFFF) and grow downwards. GPR’s start at the first ters are implemented as static RAM. A list of these location of Bank 0 and grow upwards. Any read of an registers is given in Table4-2. unimplemented location will read as ’0’s. The SFR’s can be classified into two sets: those asso- The entire data memory may be accessed directly or ciated with the “core” function and those related to the indirectly. Direct addressing may require the use of the peripheral functions. Those registers related to the BSR register. Indirect addressing requires the use of “core” are described in this section, while those related the File Select Register (FSR). Each FSR holds a to the operation of the peripheral features are 12-bit address value that can be used to access any described in the section of that peripheral feature. location in the Data Memory map without banking. The SFR’s are typically distributed among the peripher- The instruction set and architecture allow operations als whose functions they control. across all banks. This may be accomplished by indirect addressing or by the use of the MOVFF instruction. The The unused SFR locations will be unimplemented and MOVFF instruction is a two word/two cycle instruction read as '0's. See Table4-2 for addresses for the SFR’s. that moves a value from one register to another. To ensure that commonly used registers (SFR’s and select GPR’s) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section4.10 pro- vides a detailed description of the Access RAM. DS30475A-page 48 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 4-4: DATA MEMORY MAP FOR PIC18C658/858 BSR<3:0> Data Memory Map 00h Access GPR’s 000h = 0000b 05Fh Bank 0 060h GPR’s FFh 0FFh 00h 100h = 0001b GPR’s Bank 1 FFh 1FFh = 0010b 00h 200h Bank 2 GPR’s FFh 2FFh 00h 300h = 0011b Bank 3 GPR’s FFh 3FFh 400h = 0100b Bank 4 GPR’s Access Bank 4FFh 00h = 0101b 00h 500h Access Bank low 5Fh Bank 5 GPR’s (GPR’s) FFh 5FFh 60h 600h Access Bank high FFh (SFR’s) = 0110b Bank 6 Unused When a = 0, = 1110b to Read ’00h’ the BSR is ignored and the Bank 14 Access Bank is used. The first 96 bytes are Gen- eral Purpose RAM (from Bank 0). EFFh 00h F00h The next 160 bytes are = 1111b SFR’s F5Fh Special Function Registers Bank 15 FFh Access SFR’s FF6F0Fhh (from Bank 15). When a = 1, the BSR is used to specify the RAM location that the instruction uses.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 49

PIC18CXX8 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(2) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(2) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(2) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(2) FBCh CCPR2H F9Ch — FFBh PCLATU FDBh PLUSW2(2) FBBh CCPR2L F9Bh — FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(5) FF9h PCL FD9h FSR2L FB9h — F99h TRISH(5) FF8h TBLPTRU FD8h STATUS FB8h — F98h TRISG FF7h TBLPTRH FD7h TMR0H FB7h — F97h TRISF FF6h TBLPTRL FD6h TMR0L FB6h — F96h TRISE FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD FF4h PRODH FD4h — FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(5) FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH(5) FEFh INDF0(2) FCFh TMR1H FAFh SPBRG F8Fh LATG FEEh POSTINC0(2) FCEh TMR1L FAEh RCREG F8Eh LATF FEDh POSTDEC0(2) FCDh T1CON FADh TXREG F8Dh LATE FECh PREINC0(2) FCCh TMR2 FACh TXSTA F8Ch LATD FEBh PLUSW0(2) FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh — F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h — F89h LATA FE8h WREG FC8h SSPADD FA8h — F88h PORTJ(5) FE7h INDF1(2) FC7h SSPSTAT FA7h — F87h PORTH(5) FE6h POSTINC1(2) FC6h SSPCON1 FA6h — F86h PORTG FE5h POSTDEC1(2) FC5h SSPCON2 FA5h IPR3 F85h PORTF FE4h PREINC1(2) FC4h ADRESH FA4h PIR3 F84h PORTE FE3h PLUSW1(2) FC3h ADRESL FA3h PIE3 F83h PORTD FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: Unimplemented registers are read as ’0’. 2: This is not a physical register. 3: Contents of register is dependent on WIN2:WIN0 bits in CANCON register. 4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register due to the Microchip Header file requirement. 5: Available on PIC18C858 only. DS30475A-page 50 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 Address Name Address Name Address Name Address Name F7Fh TRISK(5) F5Fh — F3Fh — F1Fh RXM1EID0 F7Eh LATK(5) F5Eh CANSTATRO0(4) F3Eh CANSTATRO2(4) F1Eh RXM1EID8 F7Dh PORTK(5) F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch — F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh — F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EID0 F7Ah — F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EID8 F79h — F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F78h — F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH F77h — F57h RXB1D1 F37h TXB1D1 F17h RXF5EID0 F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EID8 F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EID0 F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EID8 F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH F6Fh CANCON F4Fh — F2Fh — F0Fh RXF3EID0 F6Eh CANSTAT F4Eh CANSTATRO1(4) F2Eh CANSTATRO3(4) F0Eh RXF3EID8 F6Dh RXB0D7(3) F4Dh TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL F6Ch RXB0D6(3) F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH F6Bh RXB0D5(3) F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EID0 F6Ah RXB0D4(3) F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EID8 F69h RXB0D3(3) F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL F68h RXB0D2(3) F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH F67h RXB0D1(3) F47h TXB0D1 F27h TXB2D1 F07h RXF1EID0 F66h RXB0D0(3) F46h TXB0D0 F26h TXB2D0 F06h RXF1EID8 F65h RXB0DLC(3) F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL F64h RXB0EIDL(3) F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH F63h RXB0EIDH(3) F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDL F62h RXB0SIDL(3) F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EIDH F61h RXB0SIDH(3) F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL F60h RXB0CON(3) F40h TXB0CON F20h TXB2CON F00h RXF0SIDH Note: Shaded registers are available in Bank 15, while the rest are in Access Bank low. Note 1: Unimplemented registers are read as ’0’. 2: This is not a physical register. 3: Contents of register is dependent on WIN2:WIN0 bits in CANCON register. 4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register due to the Microchip Header file requirement. 5: Available on PIC18C858 only.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 51

PIC18CXX8 TABLE 4-3: REGISTER FILE SUMMARY Value on Value on Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS(3) TOSU — — — Top-of-Stack upper Byte (TOS<20:16>) ---0 0000 ---0 0000 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 0000 0000 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 0000 0000 STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 00-0 0000 PCLATU — — bit 21(3) Holding Register for PC<20:16> --00 0000 --00 0000 PCLATH Holding Register for PC<15:8> 0000 0000 0000 0000 PCL PC Low Byte (PC<7:0>) 0000 0000 0000 0000 TBLPTRU — — bit 21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ---0 0000 ---0 0000 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 0000 0000 TABLAT Program Memory Table Latch 0000 0000 0000 0000 PRODH Product Register High Byte xxxx xxxx uuuu uuuu PRODL Product Register Low Byte xxxx xxxx uuuu uuuu INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 1111 1111 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 1100 0000 INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) n/a n/a POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) n/a n/a POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) n/a n/a PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) n/a n/a PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value n/a n/a of FSR0 offset by WREG FSR0H — — — — Indirect Data Memory Address Pointer 0 High ---- 0000 ---- 0000 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx uuuu uuuu WREG Working Register xxxx xxxx uuuu uuuu INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) n/a n/a POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) n/a n/a POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) n/a n/a PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) n/a n/a PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value n/a n/a of FSR1 offset by WREG FSR1H — — — — Indirect Data Memory Address Pointer 1 High ---- 0000 ---- 0000 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx uuuu uuuu BSR — — — — Bank Select Register ---- 0000 ---- 0000 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. DS30475A-page 52 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 Value on Value on Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS(3) INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) n/a n/a POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) n/a n/a POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) n/a n/a PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) n/a n/a PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value n/a n/a of FSR2 offset by WREG FSR2H — — — — Indirect Data Memory Address Pointer 2 High ---- 0000 ---- 0000 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx uuuu uuuu STATUS — — — N OV Z DC C ---x xxxx ---u uuuu TMR0H Timer0 register high byte 0000 0000 0000 0000 TMR0L Timer0 register low byte xxxx xxxx uuuu uuuu T0CON TMR0ON T08BIT T0CS T0SE T0PS3 T0PS2 T0PS1 T0PS0 1111 1111 1111 1111 OSCCON — — — — — — — SCS ---- ---0 ---- ---0 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 --00 0101 WDTCON — — — — — — — SWDTEN ---- ---0 ---- ---0 RCON IPEN LWRT — RI TO PD POR BOR 00-1 11qq 00-q qquu TMR1H Timer1 Register High Byte xxxx xxxx uuuu uuuu TMR1L Timer1 Register Low Byte xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu TMR2 Timer2 Register 0000 0000 0000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 0000 0000 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000 ADCON2 ADFM — — — — ADCS2 ADCS1 ADCS0 0--- -000 0--- -000 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 53

PIC18CXX8 Value on Value on Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS(3) CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCP1CON — — DC1B1 DC1B0 CCPM3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx uuuu uuuu CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx uuuu uuuu CCP2CON — — DC2B1 DC2B0 CCPM3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000 VRCON VREN VROEN VRR VRSS VR3 VR2 VR1 VR0 0000 0000 0000 0000 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 TMR3H Timer3 Register High Byte xxxx xxxx uuuu uuuu TMR3L Timer3 Register Low Byte xxxx xxxx uuuu uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ---- SPBRG USART Baud Rate Generator 0000 0000 0000 0000 RCREG USART Receive Register 0000 0000 0000 0000 TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x IPR3 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP 1111 1111 1111 1111 PIR3 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF 0000 0000 0000 0000 PIE3 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE 0000 0000 0000 0000 IPR2 — CMIP — — BCLIP LVDIP TMR3IP CCP2IP -1-- 1111 -1-- 1111 PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000 PIE2 — CMIE — — BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 TRISJ(4) Data Direction Control Register for PORTJ 1111 1111 1111 1111 TRISH(4) Data Direction Control Register for PORTH 1111 1111 1111 1111 TRISG — — — Data Direction Control Register for PORTG ---1 1111 ---1 1111 TRISF Data Direction Control Register for PORTF 1111 1111 1111 1111 TRISE Data Direction Control Register for PORTE 1111 1111 1111 1111 TRISD Data Direction Control Register for PORTD 1111 1111 1111 1111 TRISC Data Direction Control Register for PORTC 1111 1111 1111 1111 TRISB Data Direction Control Register for PORTB 1111 1111 1111 1111 TRISA — Bit 6(1) Data Direction Control Register for PORTA --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. DS30475A-page 54 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 Value on Value on Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS(3) LATJ(4) Read PORTJ Data Latch, Write PORTJ Data Latch xxxx xxxx uuuu uuuu LATH(4) Read PORTH Data Latch, Write PORTH Data Latch xxxx xxxx uuuu uuuu LATG — — — Read PORTG Data Latch, Write PORTG Data Latch ---x xxxx ---u uuuu LATF Read PORTF Data Latch, Write PORTF Data Latch xxxx xxxx uuuu uuuu LATE Read PORTE Data Latch, Write PORTE Data Latch xxxx xxxx uuuu uuuu LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx uuuu uuuu LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx uuuu uuuu LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx uuuu uuuu LATA — Bit 6(1) Read PORTA Data Latch, Write PORTA Data Latch --xx xxxx --uu uuuu PORTJ(4) Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx uuuu uuuu PORTH(4) Read PORTH pins, Write PORTH Data Latch xxxx xxxx uuuu uuuu PORTG — — — Read PORTG pins, Write PORTG Data Latch ---x xxxx uuuu uuuu PORTF Read PORTF pins, Write PORTF Data Latch 0000 0000 0000 0000 PORTE Read PORTE pins, Write PORTE Data Latch xxxx xxxx uuuu uuuu PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx uuuu uuuu PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx uuuu uuuu PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx uuuu uuuu PORTA — Bit 6(1) Read PORTA pins, Write PORTA Data Latch --0x 0000 --0u 0000 TRISK(4) Data Direction Control Register for PORTK 1111 1111 1111 1111 LATK(4) Read PORTK Data Latch, Write PORTK Data Latch xxxx xxxx uuuu uuuu PORTK(4) Read PORTK pins, Write PORTK Data Latch xxxx xxxx uuuu uuuu TXERRCNT TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 0000 0000 0000 0000 RXERRCNT REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 0000 0000 0000 0000 COMSTAT RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 0000 0000 CIOCON TX1SRC TX1EN ENDRHI CANCAP — — — — 1000 ---- 1000 ---- BRGCON3 — WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 -0-- -000 -0-- -000 BRGCON2 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 0000 0000 0000 0000 BRGCON1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 0000 0000 0000 CANCON REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 — xxxx xxx- uuuu uuu- CANSTAT OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICOED0 — xxx- xxx- uuu- uuu- Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 55

PIC18CXX8 Value on Value on Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS(3) RXB0D7 RXB0D77 RXB0D76 RXB0D75 RXB0D74 RXB0D73 RXB0D72 RXB0D71 RXB0D70 xxxx xxxx uuuu uuuu RXB0D6 RXB0D67 RXB0D66 RXB0D65 RXB0D64 RXB0D63 RXB0D62 RXB0D61 RXB0D60 xxxx xxxx uuuu uuuu RXB0D5 RXB0D57 RXB0D56 RXB0D55 RXB0D54 RXB0D53 RXB0D52 RXB0D51 RXB0D50 xxxx xxxx uuuu uuuu RXB0D4 RXB0D47 RXB0D46 RXB0D45 RXB0D44 RXB0D43 RXB0D42 RXB0D41 RXB0D40 xxxx xxxx uuuu uuuu RXB0D3 RXB0D37 RXB0D36 RXB0D35 RXB0D34 RXB0D33 RXB0D32 RXB0D31 RXB0D30 xxxx xxxx uuuu uuuu RXB0D2 RXB0D27 RXB0D26 RXB0D25 RXB0D24 RXB0D23 RXB0D22 RXB0D21 RXB0D20 xxxx xxxx uuuu uuuu RXB0D1 RXB0D17 RXB0D16 RXB0D15 RXB0D14 RXB0D13 RXB0D12 RXB0D11 RXB0D10 xxxx xxxx uuuu uuuu RXB0D0 RXB0D07 RXB0D06 RXB0D05 RXB0D04 RXB0D03 RXB0D02 RXB0D0? RXB0D00 xxxx xxxx uuuu uuuu RXB0DLC — RXRTR RESB1 RESB0 DLC3 DLC2 DLC1 DLC0 0xxx xxxx 0uuu uuuu RXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu RXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu RXB0SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx uuuu u-uu RXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu RXB0CON RXFUL RXM1 RXM0 — RXRTRRO RXB0DBEN JTOFF FILHIT0 000- 0000 000- 0000 CANSTAT OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — xxx- xxx- uuu- uuu- RXB1D7 RXB1D77 RXB1D76 RXB1D75 RXB1D74 RXB1D73 RXB1D72 RXB1D71 RXB1D70 xxxx xxxx uuuu uuuu RXB1D6 RXB1D67 RXB1D66 RXB1D65 RXB1D64 RXB1D63 RXB1D62 RXB1D61 RXB1D60 xxxx xxxx uuuu uuuu RXB1D5 RXB1D57 RXB1D56 RXB1D55 RXB1D54 RXB1D53 RXB1D52 RXB1D51 RXB1D50 xxxx xxxx uuuu uuuu RXB1D4 RXB1D47 RXB1D46 RXB1D45 RXB1D44 RXB1D43 RXB1D42 RXB1D41 RXB1D40 xxxx xxxx uuuu uuuu RXB1D3 RXB1D37 RXB1D36 RXB1D35 RXB1D34 RXB1D33 RXB1D32 RXB1D31 RXB1D30 xxxx xxxx uuuu uuuu RXB1D2 RXB1D27 RXB1D26 RXB1D25 RXB1D24 RXB1D23 RXB1D22 RXB1D21 RXB1D20 xxxx xxxx uuuu uuuu RXB1D1 RXB1D17 RXB1D16 RXB1D15 RXB1D14 RXB1D13 RXB1D12 RXB1D11 RXB1D10 xxxx xxxx uuuu uuuu RXB1D0 RXB1D07 RXB1D06 RXB1D05 RXB1D04 RXB1D03 RXB1D02 RXB1D01 RXB1D00 xxxx xxxx uuuu uuuu RXB1DLC — RXRTR RESB1 RESB0 DLC3 DLC2 DLC1 DLC0 0xxx xxxx 0uuu uuuu RXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu RXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu RXB1SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x0xx uuuu u0uu RXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu RXB1CON RXFUL RXM1 RXM0 — RXRTRRO FILHIT2 FILHIT1 FILHIT0 0000 0000 0000 0000 CANSTAT OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — xxx- xxx- uuu- uuu- Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. DS30475A-page 56 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 Value on Value on Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS(3) TXB0D7 TXB0D77 TXB0D76 TXB0D75 TXB0D74 TXB0D73 TXB0D72 TXB0D71 TXB0D70 xxxx xxxx uuuu uuuu TXB0D6 TXB0D67 TXB0D66 TXB0D65 TXB0D64 TXB0D63 TXB0D62 TXB0D61 TXB0D60 xxxx xxxx uuuu uuuu TXB0D5 TXB0D57 TXB0D56 TXB0D55 TXB0D54 TXB0D53 TXB0D52 TXB0D51 TXB0D50 xxxx xxxx uuuu uuuu TXB0D4 TXB0D47 TXB0D46 TXB0D45 TXB0D44 TXB0D43 TXB0D42 TXB0D41 TXB0D40 xxxx xxxx uuuu uuuu TXB0D3 TXB0D37 TXB0D36 TXB0D35 TXB0D34 TXB0D33 TXB0D32 TXB0D31 TXB0D30 xxxx xxxx uuuu uuuu TXB0D2 TXB0D27 TXB0D26 TXB0D25 TXB0D24 TXB0D23 TXB0D22 TXB0D21 TXB0D20 xxxx xxxx uuuu uuuu TXB0D1 TXB0D17 TXB0D16 TXB0D15 TXB0D14 TXB0D13 TXB0D12 TXB0D11 TXB0D10 xxxx xxxx uuuu uuuu TXB0D0 TXB0D07 TXB0D06 TXB0D05 TXB0D04 TXB0D03 TXB0D02 TXB0D01 TXB0D00 xxxx xxxx uuuu uuuu TXB0DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 0x00 xxxx 0u00 uuuu TXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu TXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu TXB0SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx0 x0xx uuu0 u0uu TXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu TXB0CON — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0000 0000 0000 CANSTAT OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — xxx- xxx- uuu- uuu- TXB1D7 TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73 TXB1D72 TXB1D71 TXB1D70 xxxx xxxx uuuu uuuu TXB1D6 TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63 TXB1D62 TXB1D61 TXB1D60 xxxx xxxx uuuu uuuu TXB1D5 TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53 TXB1D52 TXB1D51 TXB1D50 xxxx xxxx uuuu uuuu TXB1D4 TXB1D47 TXB1D46 TXB1D45 TXB1D44 TXB1D43 TXB1D42 TXB1D41 TXB1D40 xxxx xxxx uuuu uuuu TXB1D3 TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33 TXB1D32 TXB1D31 TXB1D30 xxxx xxxx uuuu uuuu TXB1D2 TXB1D27 TXB1D26 TXB1D25 TXB1D24 TXB1D23 TXB1D22 TXB1D21 TXB1D20 xxxx xxxx uuuu uuuu TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 xxxx xxxx uuuu uuuu TXB1D0 TXB1D07 TXB1D06 TXB1D05 TXB1D04 TXB1D03 TXB1D02 TXB1D01 TXB1D00 xxxx xxxx uuuu uuuu TXB1DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 0x00 xxxx 0u00 uuuu TXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu TXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu TXB1SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx0 x0xx uuu0 u0uu TXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu TXB1CON — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0000 0000 0000 CANSTAT OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — xxx- xxx- uuu- uuu- Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 57

PIC18CXX8 Value on Value on Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS(3) TXB2D7 TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 xxxx xxxx uuuu uuuu TXB2D6 TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 xxxx xxxx uuuu uuuu TXB2D5 TXB2D57 TXB2D56 TXB2D55 TXB2D54 TXB2D53 TXB2D52 TXB2D51 TXB2D50 xxxx xxxx uuuu uuuu TXB2D4 TXB2D47 TXB2D46 TXB2D45 TXB2D44 TXB2D43 TXB2D42 TXB2D41 TXB2D40 xxxx xxxx uuuu uuuu TXB2D3 TXB2D37 TXB2D36 TXB2D35 TXB2D34 TXB2D33 TXB2D32 TXB2D31 TXB2D30 xxxx xxxx uuuu uuuu TXB2D2 TXB2D27 TXB2D26 TXB2D25 TXB2D24 TXB2D23 TXB2D22 TXB2D21 TXB2D20 xxxx xxxx uuuu uuuu TXB2D1 TXB2D17 TXB2D16 TXB2D15 TXB2D14 TXB2D13 TXB2D12 TXB2D11 TXB2D10 xxxx xxxx uuuu uuuu TXB2D0 TXB2D07 TXB2D06 TXB2D05 TXB2D04 TXB2D03 TXB2D02 TXB2D01 TXB2D00 xxxx xxxx uuuu uuuu TXB2DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 0x00 xxxx 0u00 uuuu TXB2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu TXB2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu TXB2SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx0 x0xx uuu0 u0uu TXB2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu TXB2CON — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0000 0000 0000 RXM1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu RXM1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu RXM1SIDL SID2 SID1 SID0 — — — EID17 EID16 xxx- --xx uuu- --uu RXM1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu RXM0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu RXM0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu RXM0SIDL SID2 SID1 SID0 — — — EID17 EID16 xxx- --xx uuu- --uu RXM0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu RXF5EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu RXF5EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu RXF5SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx uuu- u-uu RXF5SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu RXF4EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu RXF4EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu RXF4SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx uuu- u-uu RXF4SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu RXF3EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu RXF3EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu RXF3SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx uuu- u-uu RXF3SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. DS30475A-page 58 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 Value on Value on Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS(3) RXF2EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu RXF2EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu RXF2SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx uuu- u-uu RXF2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu RXF1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu RXF1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu RXF1SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx uuu- u-uu RXF1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu RXF0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu RXF0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu RXF0SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx uuu- u-uu RXF0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 59

PIC18CXX8 4.10 Access Bank 4.11 Bank Select Register (BSR) The Access Bank is an architectural enhancement that The need for a large general purpose memory space is very useful for C compiler code optimization. The dictates a RAM banking scheme. The data memory is techniques used by the C compiler are also be useful partitioned into sixteen banks. When using direct for programs written in assembly. addressing, the BSR should be configured for the desired bank. This data memory region can be used for: BSR<3:0> holds the upper 4 bits of the 12-bit RAM (cid:127) Intermediate computational values address. The BSR<7:4> bits will always read ’0’s, and (cid:127) Local variables of subroutines writes will have no effect. (cid:127) Faster context saving/switching of variables (cid:127) Common variables A MOVLB instruction has been provided in the instruc- (cid:127) Faster evaluation/control of SFR’s (no banking) tion set to assist in selecting banks. The Access Bank is comprised of the upper 160 bytes If the currently selected bank is not implemented, any in Bank 15 (SFR’s) and the lower 96 bytes in Bank 0. read will return all '0's and all writes are ignored. The These two sections will be referred to as Access Bank STATUS register bits will be set/cleared as appropriate High and Access Bank Low, respectively. Figure4-4 for the instruction performed. indicates the Access Bank areas. Each Bank extends up to FFh (256 bytes). All data A bit in the instruction word specifies if the operation is memory is implemented as static RAM. to occur in the bank specified by the BSR register, or in A MOVFF instruction ignores the BSR, since the 12-bit the Access Bank. addresses are embedded into the instruction word. When forced in the Access Bank (a = ’0’), the last Section4.12 provides a description of indirect address- address in Access Bank Low is followed by the first ing, which allows linear addressing of the entire RAM address in Access Bank High. Access Bank High maps space. most of the Special Function Registers so that these registers can be accessed without any software over- head. FIGURE 4-5: DIRECT ADDRESSING Direct Addressing (3) BSR<3:0> 7 from opcode 0 (2) (3) bank select location select 00h 01h 0Eh 0Fh 000h 100h E00h F00h Data Memory(1) 0FFh 1FFh EFFh FFFh Bank 0 Bank 1 Bank 14 Bank 15 Note 1: For register file map detail, see Table4-2. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS30475A-page 60 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 4.12 Indirect Addressing, INDF and FSR If an instruction writes a value to INDF0, the value will Registers be written to the address indicated by FSR0H:FSR0L. A read from INDF1 reads the data from the address Indirect addressing is a mode of addressing data mem- indicated by FSR1H:FSR1L. INDFn can be used in ory, where the data memory address in the instruction code anywhere an operand can be used. is not fixed. A SFR register is used as a pointer to the If INDF0, INDF1 or INDF2 are read indirectly via an data memory location that is to be read or written. FSR, all ’0’s are read (zero bit is set). Similarly, if Since this pointer is in RAM, the contents can be mod- INDF0, INDF1 or INDF2 are written to indirectly, the ified by the program. This can be useful for data tables operation will be equivalent to a NOP instruction and the in the data memory and for software stacks. Figure4-6 STATUS bits are not affected. shows the operation of indirect addressing. This shows the moving of the value to the data memory address 4.12.1 INDIRECT ADDRESSING OPERATION specified by the value of the FSR register. Each FSR register has an INDF register associated with Indirect addressing is possible by using one of the it, plus four additional register addresses. Performing an INDF registers. Any instruction using the INDF register operation on one of these five registers determines how actually accesses the register indicated by the File the FSR will be modified during indirect addressing. Select Register, FSR. Reading the INDF register itself indirectly (FSR = ’0’) will read 00h. Writing to the INDF When data access is done to one of the five INDFn register indirectly results in a no-operation. The FSR locations, the address selected will configure the FSRn register contains a 12-bit address, which is shown in register to: Figure4-6. (cid:127) Do nothing to FSRn after an indirect access (no The INDFn (0 ≤ n ≤ 2) register is not a physical register. change) - INDFn Addressing INDFn actually addresses the register (cid:127) Auto-decrement FSRn after an indirect access whose address is contained in the FSRn register (post-decrement) - POSTDECn (FSRn is a pointer). This is indirect addressing. (cid:127) Auto-increment FSRn after an indirect access Example4-4 shows a simple use of indirect addressing (post-increment) - POSTINCn to clear the RAM in Bank 1 (locations 100h-1FFh) in a (cid:127) Auto-increment FSRn before an indirect access minimum number of instructions. (pre-increment) - PREINCn (cid:127) Use the value in the WREG register as an offset EXAMPLE 4-4: HOW TO CLEAR RAM to FSRn. Do not modify the value of the WREG or (BANK 1) USING INDIRECT the FSRn register after an indirect access (no ADDRESSING change) - PLUSWn LFSR FSR0, 0x100 ; When using the auto-increment or auto-decrement NEXT CLRF POSTINC0 ; Clear INDF features, the effect on the FSR is not reflected in the ; register STATUS register. For example, if the indirect address ; & inc pointer causes the FSR to equal '0', the Z bit will not be set. BTFSS FSR0H, 1 ; All done Incrementing or decrementing an FSR affects all 12 ; w/ Bank1? bits. That is, when FSRnL overflows from an increment, GOTO NEXT ; NO, clear next CONTINUE ; FSRnH will be incremented automatically. : ; YES, continue Adding these features allows the FSRn to be used as a software stack pointer in addition to its uses for table There are three indirect addressing registers. To operations in data memory. address the entire data memory space (4096 bytes), Each FSR has an address associated with it that per- these registers are 12-bit wide. To store the 12-bits of forms an indexed indirect access. When a data access addressing information, two 8-bit registers are to this INDFn location (PLUSWn) occurs, the FSRn is required. These indirect addressing registers are: configured to add the 2’s complement value in the 1. FSR0: composed of FSR0H:FSR0L WREG register and the value in FSR to form the address before an indirect access. The FSR value is 2. FSR1: composed of FSR1H:FSR1L not changed. 3. FSR2: composed of FSR2H:FSR2L If an FSR register contains a value that indicates one of In addition, there are registers INDF0, INDF1 and the INDFn, an indirect read will read 00h (zero bit is INDF2, which are not physically implemented. Reading set), while an indirect write will be equivalent to a NOP or writing to these registers activates indirect address- (STATUS bits are not affected). ing, with the value in the corresponding FSR register being the address of the data. If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or post-increment/decrement functions.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 61

PIC18CXX8 FIGURE 4-6: INDIRECT ADDRESSING Indirect Addressing FSR register 11 8 7 0 FSRnH FSRnL location select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table4-2. DS30475A-page 62 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 4.13 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register4-2, contains as 000u u1uu (where u = unchanged). the arithmetic status of the ALU. The STATUS register It is recommended, therefore, that only BCF, BSF, can be the destination for any instruction, as with any SWAPF, MOVFF and MOVWF instructions are used to other register. If the STATUS register is the destination alter the STATUS register, because these instruc- for an instruction that affects the Z, DC, C, OV or N bits, tions do not affect the Z, C, DC, OV or N bits from the then the write to these five bits is disabled. These bits STATUS register. For other instructions which do not are set or cleared according to the device logic. There- affect the status bits, see Table23-2. fore, the result of an instruction with the STATUS regis- ter as destination may be different than intended. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. REGISTER 4-2: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as '0' bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result of the ALU operation was negative, (ALU MSb = 1) 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit mag- nitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRCF, RRNCF, RLCF, and RLNCF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. bit 0 C: Carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 63

PIC18CXX8 4.13.1 RCON REGISTER The Reset Control (RCON) register contains flag bits Note 1: If the BOREN configuration bit is set, BOR that allow differentiation between the sources of a is ’1’ on Power-on Reset. If the BOREN device RESET. These flags include the TO, PD, POR, configuration bit is clear, BOR is unknown BOR and RI bits. This register is readable and writable. on Power-on Reset. The BOR status bit is a “don't care” and is not necessarily predictable if the brown-out circuit is disabled (the BOREN configuration bit is clear). BOR must then be set by the user and checked on subse- quent RESETs to see if it is clear, indicat- ing a brown-out has occurred. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. REGISTER 4-3: RCON REGISTER R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 IPEN LWRT — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX compatibility mode) bit 6 LWRT: Long Write Enable bit 1 = Enable TBLWT to internal program memory Once this bit is set, it can only be cleared by a POR or MCLR Reset 0 = Disable TBLWT to internal program memory; TBLWT only to external program memory bit 5 Unimplemented: Read as '0' bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed 0 = The RESET instruction was executed causing a device RESET (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 64 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 5.0 TABLE READS/TABLE WRITES Table Read operations retrieve data from program memory and place it into the data memory space. All PICmicro® devices have two memory spaces: the Figure5-1 shows the operation of a Table Read with program memory space and the data memory space. program and data memory. Table Reads and Table Writes have been provided to move data between these two memory spaces through Table Write operations store data from the data mem- an 8-bit register (TABLAT). ory space into program memory. Figure5-2 shows the operation of a Table Write with program and data The operations that allow the processor to move data memory. between the data and program memory spaces are: Table operations work with byte entities. A table block (cid:127) Table Read (TBLRD) containing data is not required to be word aligned, so a (cid:127) Table Write (TBLWT) table block can start and end at any byte address. If a table write is being used to write an executable pro- gram to program memory, program instructions will need to be word aligned. FIGURE 5-1: TABLE READ OPERATION TABLE POINTER (1) TABLE LATCH (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT PROGRAM MEMORY Program Memory Instruction: TBLRD* (TBLPTR) Note 1: Table Pointer points to a byte in program memory. FIGURE 5-2: TABLE WRITE OPERATION TABLE POINTER (1) TABLE LATCH (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT PROGRAM MEMORY Program Memory Instruction: TBLWT* (TBLPTR) Note 1: Table Pointer points to a byte in program memory.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 65

PIC18CXX8 5.1 Control Registers 5.1.1 RCON REGISTER Several control registers are used in conjunction with The LWRT bit specifies the operation of Table Writes to the TBLRD and TBLWT instructions. These include: internal memory when the VPP voltage is applied to the MCLR pin. When the LWRT bit is set, the controller (cid:127) RCON register continues to execute user code, but long table writes (cid:127) TABLAT register are allowed (for programming internal program mem- (cid:127) TBLPTR registers ory) from user mode. The LWRT bit can be cleared only by performing either a POR or MCLR Reset. REGISTER 5-1: RCON REGISTER (ADDRESS: 0xFD0h) R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 IPEN LWRT — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX compatibility mode) bit 6 LWRT: Long Write Enable 1 = Enable TBLWT to internal program memory 0 = Disable TBLWT to internal program memory. Note 1: Only cleared on a POR or MCLR reset. This bit has no effect on TBLWTs to external program memory. bit 5 Unimplemented: Read as '0' bit 4 RI: RESET Instruction Flag bit 1 = No RESET instruction occurred 0 = A RESET instruction occurred bit 3 TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset nor POR Reset occurred 0 = A Brown-out Reset or POR Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 66 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 5.1.2 TABLAT - TABLE LATCH REGISTER address up to 2 Mbytes of program memory space. The 22nd bit allows read only access to the Device ID, the The Table Latch (TABLAT) is an 8-bit register mapped User ID and the Configuration bits. into the SFR space. The Table Latch is used to hold The table pointer TBLPTR is used by the TBLRD and 8-bit data during data transfers between program TBLWT instructions. These instructions can update the memory and data memory. TBLPTR in one of four ways based on the table oper- 5.1.3 TBLPTR - TABLE POINTER REGISTER ation. These operations are shown in Table5-1. These operations on the TBLPTR only affect the low The Table Pointer (TBLPTR) addresses a byte within order 21-bits. the program memory. The TBLPTR is comprised of three SFR registers (Table Pointer Upper byte, High byte and Low byte). These three registers (TBLPTRU:TBLPTRH:TBLPTRL) join to form a 22-bit wide pointer. The low order 21-bits allow the device to TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+*  2000 Microchip Technology Inc. Advanced Information DS30475A-page 67

PIC18CXX8 5.2 Program Memory Read/Writes When a Table Write occurs to an even program mem- ory address (TBLPTR<0> = 0), the contents of TABLAT 5.2.1 TABLE READ OVERVIEW (TBLRD) are transferred to an internal holding register. This is performed as a short write and the program memory The TBLRD instructions are used to read data from pro- block is not actually programmed at this time. The gram memory to data memory. holding register is not accessible by the user. TBLPTR points to a byte address in program space. When a Table Write occurs to an odd program memory Executing TBLRD places the byte pointed to into address (TBLPTR<0> = 1), a long write is started. Dur- TABLAT. In addition, TBLPTR can be modified auto- ing the long write, the contents of TABLAT are written matically for the next Table Read operation. to the high byte of the program memory block and the Table Reads from program memory are performed one contents of the holding register are transferred to the byte at a time. The instruction will load TABLAT with the low byte of the program memory block. one byte from program memory pointed to by TBLPTR. Figure5-3 shows the holding register and the program 5.2.2 PROGRAM MEMORY WRITE BLOCK SIZE memory write blocks. If a single byte is to be programmed, the low (even) The program memory of PIC18CXX8 devices is written byte of the destination program word should be read in blocks. For PIC18CXX8 devices, the write block size using TBLRD*, modified or changed, if required, and is 2 bytes. Consequently, Table Write operations to written back to the same address using TBLWT*+. The program memory are performed in pairs, one byte at a high (odd) byte should be read using TBLRD*, modified time. or changed if required, and written back to the same address using TBLWT. The write to an odd address will cause a long write to begin. This process ensures that existing data in either byte will not be changed unless desired. FIGURE 5-3: HOLDING REGISTER AND THE WRITE Program Memory Holding Register Instruction Execution ; TABLPTR points to address n MOVLW DataLow ; Load low data MSB LSB MOVWF TABLAT ; byte to TABLAT DataLow TBLWT*+ ; Write it to LSB ; of Holding register MOVLW DataHigh ; Load high data n - 1 MSB LSB MOVWF TABLAT ; byte to TABLAT n DataLow DataHigh DataLow TBLWT* ; Write it to MSB n + 1 DataHigh ; of Holding n + 2 ; register and ; begin long ; write EXAMPLE 5-1: TABLE READ CODE EXAMPLE ; Read a byte from location 0x0020 CLRF TBLPTRU ; Load upper 5 bits of ; 0x0020 CLRF TBLPTRH ; Load higher 8 bits of ; 0x0020 MOVLW 0x20 ; Load 0x20 into MOVWF TBLPTRL ; TBLPTRL MOVWF TBLRD* ; Data is in TABLAT DS30475A-page 68 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 5.2.2.1 Long Write Operation 5.2.2.2 Sequence of Events The long write is what actually programs words of data The sequence of events for programming an internal into the internal memory. When a TBLWT to the MSB of program memory location should be: the write block occurs, instruction execution is halted. 1. Enable the interrupt that terminates the long During this time, programming voltage and the data write. Disable all other interrupts. stored in internal latches is applied to program memory. 2. Clear the source interrupt flag. For a long write to occur: 3. If Interrupt Service Routine execution is desired 1. MCLR/VPP pin must be at the programming when the device wakes, enable global voltage interrupts. 2. LWRT bit must be set 4. Set LWRT bit in the RCON register. 3. TBLWT to the address of the MSB of the write 5. Raise MCLR/VPP pin to the programming block voltage, VPP. If the LWRT bit is clear, a short write will occur and pro- 6. Clear the WDT (if enabled). gram memory will not be changed. If the TBLWT is not 7. Set the interrupt source to interrupt at the to the MSB of the write block, then the programming required time. phase is not initiated. 8. Execute the Table Write for the lower (even) Setting the LWRT bit enables long writes when the byte. This will be a short write. MCLR pin is taken to VPP voltage. Once the LWRT bit 9. Execute the Table Write for the upper (odd) byte. is set, it can be cleared only by performing a POR or This will be a long write. The controller will HALT MCLR Reset. while programming. The interrupt wakes the controller. To ensure that the memory location has been well pro- grammed, a minimum programming time is required. 10. If GIE was set, service the interrupt request. The long write can be terminated after the program- 11. Go to 7 if more bytes to be programmed. ming time has expired by a RESET or an interrupt. 12. Lower MCLR/VPP pin to VDD. Having only one interrupt source enabled to terminate 13. Verify the memory location (table read). the long write, ensures that no unintended interrupts 14. Reset the device. will prematurely terminate the long write.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 69

PIC18CXX8 5.2.3 LONG WRITE INTERRUPTS 5.3 Unexpected Termination of Write Operations The long write must be terminated by a RESET or any interrupt. If a write is terminated by an unplanned event such as The interrupt source must have its interrupt enable bit loss of power, an unexpected RESET, or an interrupt set. When the source sets its interrupt flag, program- that was not disabled, the memory location just pro- ming will terminate. This will occur regardless of the grammed should be verified and reprogrammed if settings of interrupt priority bits, the GIE/GIEH bit or the needed. PIE/GIEL bit. Depending on the states of interrupt priority bits, the GIE/GIEH bit or the PIE/GIEL bit, program execution can either be vectored to the high or low priority Inter- rupt Service Routine (ISR), or continue execution from where programming commenced. In either case, the interrupt flag will not be cleared when programming is terminated and will need to be cleared by the software. TABLE 5-2: SLEEP MODE, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS GIE/ PIE/ Interrupt Interrupt Priority Action GIEH GIEL Enable Flag X X X 0 X Long write continues even if interrupt flag (default) becomes set during SLEEP. X X X 1 0 Long write continues, will wake when the interrupt flag is set. 0 0 X 1 1 Terminates long write, executes next instruction. (default) (default) Interrupt flag not cleared. 0 1 1 1 1 Terminates long write, executes next instruction. (default) high priority Interrupt flag not cleared. (default) 1 0 0 1 1 Terminates long write, executes next instruction. (default) low Interrupt flag not cleared. 0 1 0 1 1 Terminates long write, branches to low priority (default) low interrupt vector. Interrupt flag can be cleared by ISR. 1 0 1 1 1 Terminates long write, branches to high priority (default) high priority interrupt vector. (default) Interrupt flag can be cleared by ISR. DS30475A-page 70 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 6.0 8 X 8 HARDWARE MULTIPLIER Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: An 8 x 8 hardware multiplier is included in the ALU of the PIC18CXX8 devices. By making the multiply a (cid:127) Higher computational throughput hardware operation, it completes in a single instruction (cid:127) Reduces code size requirements for multiply algo- cycle. This is an unsigned multiply that gives a 16-bit rithms result. The result is stored into the 16-bit product regis- The performance increase allows the device to be used ter pair (PRODH:PRODL). The multiplier does not in applications previously reserved for Digital Signal affect any flags in the STATUS register. Processors. Table6-1 shows a performance comparison between enhanced devices using the single cycle hardware mul- tiply, and performing the same function without the hardware multiply. TABLE 6-1: PERFORMANCE COMPARISON Program Cycles Time Routine Multiply Method Memory (Max) @ 40 MHz @ 10 MHz @ 4 MHz (Words) 8 x 8 unsigned Without hardware multiply 13 69 6.9 µs 27.6 µs 69 µs Hardware multiply 1 1 100 ns 400 ns 1 µs 8 x 8 signed Without hardware multiply 33 91 9.1 µs 36.4 µs 91 µs Hardware multiply 6 6 600 ns 2.4 µs 6 µs 16 x 16 unsigned Without hardware multiply 21 242 24.2 µs 96.8 µs 242 µs Hardware multiply 24 24 2.4 µs 9.6 µs 24 µs 16 x 16 signed Without hardware multiply 52 254 25.4 µs 102.6 µs 254 µs Hardware multiply 36 36 3.6 µs 14.4 µs 36 µs  2000 Microchip Technology Inc. Advanced Information DS30475A-page 71

PIC18CXX8 6.1 Operation Example6-3 shows the sequence to perform a 16 x 16 unsigned multiply. Equation6-1 shows the algorithm Example6-1 shows the sequence to perform an 8 x 8 that is used. The 32-bit result is stored in 4 registers unsigned multiply. Only one instruction is required RES3:RES0. when one argument of the multiply is already loaded in the WREG register. EQUATION 6-1: 16 x 16 UNSIGNED Example6-2 shows the sequence to do an 8 x 8 signed MULTIPLICATION multiply. To account for the sign bits of the arguments, ALGORITHM each argument’s most significant bit (MSb) is tested RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L and the appropriate subtractions are done. = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + EXAMPLE 6-1: 8 x 8 UNSIGNED MULTIPLY (ARG1L • ARG2H • 28) + ROUTINE (ARG1L • ARG2L) MOVFF ARG1, WREG ; MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 6-3: 16 x 16 UNSIGNED MULTIPLY ROUTINE MOVFF ARG1L, WREG EXAMPLE 6-2: 8 x 8 SIGNED MULTIPLY MULWF ARG2L ; ARG1L * ARG2L -> ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVFF ARG1, WREG MOVFF PRODL, RES0 ; MULWF ARG2 ; ARG1 * ARG2 -> ; ; PRODH:PRODL MOVFF ARG1H, WREG BTFSC ARG2, SB ; Test Sign Bit MULWF ARG2H ; ARG1H * ARG2H -> SUBWF PRODH, F ; PRODH = PRODH ; PRODH:PRODL ; - ARG1 MOVFF PRODH, RES3 ; MOVFF ARG2, WREG MOVFF PRODL, RES2 ; BTFSC ARG1, SB ; Test Sign Bit ; SUBWF PRODH, F ; PRODH = PRODH MOVFF ARG1L, WREG ; - ARG2 MULWF ARG2H ; ARG1L * ARG2H -> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ; ; MOVFF ARG1H, WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ; DS30475A-page 72 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 Example6-4 shows the sequence to perform an 16 x EXAMPLE 6-4: 16 x 16 SIGNED MULTIPLY 16 signed multiply. Equation6-2 shows the algorithm ROUTINE used. The 32-bit result is stored in four registers MOVFF ARG1L, WREG RES3:RES0. To account for the sign bits of the argu- MULWF ARG2L ; ARG1L * ARG2L -> ments, each argument pairs most significant bit (MSb) ; PRODH:PRODL is tested and the appropriate subtractions are done. MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ; EQUATION 6-2: 16 x 16 SIGNED ; MOVFF ARG1H, WREG MULTIPLICATION MULWF ARG2H ; ARG1H * ARG2H -> ALGORITHM ; PRODH:PRODL RES3:RES0 MOVFF PRODH, RES3 ; = ARG1H:ARG1L • ARG2H:ARG2L MOVFF PRODL, RES2 ; = (ARG1H • ARG2H • 216) + ; (ARG1H • ARG2L • 28) + MOVFF ARG1L, WREG (ARG1L • ARG2H • 28) + MULWF ARG2H ; ARG1L * ARG2H -> (ARG1L • ARG2L) + ; PRODH:PRODL (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + MOVF PRODL, W ; (-1 • ARG1H<7> • ARG2H:ARG2L • 216) ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ; ; MOVFF ARG1H, WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ; ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? GOTO SIGN_ARG1 ; no, check ARG1 MOVFF ARG1L, WREG ; SUBWF RES2 ; MOVFF ARG1H, WREG ; SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? GOTO CONT_CODE ; no, done MOVFF ARG2L, WREG ; SUBWF RES2 ; MOVFF ARG2H, WREG ; SUBWFB RES3 ; CONT_CODE :  2000 Microchip Technology Inc. Advanced Information DS30475A-page 73

PIC18CXX8 NOTES: DS30475A-page 74 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 7.0 INTERRUPTS When the IPEN bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are com- The PIC18CXX8 devices have multiple interrupt patible with PICmicro® mid-range devices. In sources and an interrupt priority feature that allows Compatibility mode, the interrupt priority bits for each each interrupt source to be assigned a high priority source have no effect. The PEIE bit (INTCON register) level or a low priority level. The high priority interrupt enables/disables all peripheral interrupt sources. The vector is at 000008h and the low priority interrupt vector GIE bit (INTCON register) enables/disables all interrupt is at 000018h. High priority interrupt events will over- sources. All interrupts branch to address 000008h in ride any low priority interrupts that may be in progress. Compatibility mode. There are 13 registers that are used to control interrupt When an interrupt is responded to, the Global Interrupt operation. These registers are: Enable bit is cleared to disable further interrupts. If the (cid:127) RCON IPEN bit is cleared, this is the GIE bit. If interrupt prior- (cid:127) INTCON ity levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low (cid:127) INTCON2 priority interrupt. (cid:127) INTCON3 The return address is pushed onto the stack and the (cid:127) PIR1, PIR2, PIR3 PC is loaded with the interrupt vector address (cid:127) PIE1, PIE2, PIE3 (000008h or 000018h). Once in the interrupt service (cid:127) IPR1, IPR2, IPR3 routine, the source(s) of the interrupt can be deter- It is recommended that the Microchip header files sup- mined by polling the interrupt flag bits. The interrupt plied with MPLAB be used for the symbolic bit names flag bits must be cleared in software before re-enabling in these registers. This allows the assembler/compiler interrupts to avoid recursive interrupts. to automatically take care of the placement of these The "return from interrupt" instruction, RETFIE, exits bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL Each interrupt source has three bits to control its oper- if priority levels are used), which re-enables interrupts. ation. The functions of these bits are: For external interrupt events, such as the INT pins or (cid:127) Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact (cid:127) Enable bit that allows program execution to latency is the same for one or two cycle instructions. branch to the interrupt vector address when Individual interrupt flag bits are set, regardless of the the flag bit is set status of their corresponding enable bit or the GIE bit. (cid:127) Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON register). When interrupt priority is enabled, there are two bits that enable interrupts glo- bally. Setting the GIEH bit (INTCON register) enables all interrupts that have the priority bit set. Setting the GIEL bit (INTCON register) enables all interrupts that have the priority bit cleared. When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. Individual interrupts can be disabled through their cor- responding enable bits.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 75

PIC18CXX8 FIGURE 7-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE Wake-up if in SLEEP mode RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Interrupt to CPU INT3IF Vector to location Peripheral Interrupt Flag bit INT3IE 0008h Peripheral Interrupt Enable bit INT3IP Peripheral Interrupt Priority bit GIE/GIEH TMR1IF TMR1IE TMR1IP IPEN XXXXIF IPEN XXXXIE GIEL/PEIE XXXXIP IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR0IF Interrupt to CPU TMR0IE Vector to Location TMR1IF TMR0IP 0018h TMR1IE TMR1IP RBIF RBIE RBIP PEIE/GIEL XXXXIF XXXXIE INT0IF XXXXIP INT0IE INT1IF Additional Peripheral Interrupts INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP DS30475A-page 76 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 7.1 Control Registers 7.1.1 INTCON REGISTERS This section contains the control and status registers. The INTCON Registers are readable and writable registers, which contain various enable, priority, and flag bits. REGISTER 7-1: INTCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all un-masked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all high priority interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software by reading PORTB) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 77

PIC18CXX8 REGISTER 7-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. DS30475A-page 78 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 7-3: INTCON3 REGISTER R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 79

PIC18CXX8 7.1.2 PIR REGISTERS 7.1.3 PIE REGISTERS The Peripheral Interrupt Request (PIR) registers con- The Peripheral Interrupt Enable (PIE) registers contain tain the individual flag bits for the peripheral interrupts the individual enable bits for the peripheral interrupts (Register7-5). Due to the number of peripheral inter- (Register7-5). Due to the number of peripheral inter- rupt sources, there are three Peripheral Interrupt rupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). Enable registers (PIE1, PIE2, PIE3). When IPEN is clear, the PEIE bit must be set to enable any of these Note 1: Interrupt flag bits are set when an interrupt peripheral interrupts. condition occurs, regardless of the state of its corresponding enable bit or the global 7.1.4 IPR REGISTERS enable bit, GIE (INTCON register). The Interrupt Priority (IPR) registers contain the individ- 2: User software should ensure the appropri- ual priority bits for the peripheral interrupts ate interrupt flag bits are cleared prior to (Register7-7). Due to the number of peripheral inter- enabling an interrupt, and after servicing rupt sources, there are three Peripheral Interrupt Prior- that interrupt. ity registers (IPR1, IPR2, IPR3). The operation of the priority bits requires that the Interrupt Priority Enable bit (IPEN) be set. 7.1.5 RCON REGISTER The Reset Control (RCON) register contains the bit that is used to enable prioritized interrupts (IPEN). REGISTER 7-4: RCON REGISTER R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 IPEN LWRT — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX compatibility mode) bit 6 LWRT: Long Write Enable For details of bit operation see Register4-3 bit 5 Unimplemented: Read as '0' bit 4 RI: RESET Instruction Flag bit For details of bit operation see Register4-3 bit 3 TO: Watchdog Time-out Flag bit For details of bit operation see Register4-3 bit 2 PD: Power-down Detection Flag bit For details of bit operation see Register4-3 bit 1 POR: Power-on Reset Status bit For details of bit operation see Register4-3 bit 0 BOR: Brown-out Reset Status bit For details of bit operation see Register4-3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 80 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 7-5: PIR REGISTERS R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF bit 7 bit 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PIR3 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF bit 7 bit 0 PIR1 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow  2000 Microchip Technology Inc. Advanced Information DS30475A-page 81

PIC18CXX8 REGISTER 7-5: PIR REGISTERS (CONT’D) PIR2 bit 7 Unimplemented: Read as’0’ bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed 0 = Comparator input has not changed bit 5-4 Unimplemented: Read as’0’ bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A Bus Collision occurred (must be cleared in software) 0 = No Bus Collision occurred bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit 1 = A low voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCPx Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode DS30475A-page 82 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 7-5: PIR REGISTERS (CONT’D) PIR3 bit 7 IRXIF: Invalid Message Received Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = An invalid message has not occurred on the CAN bus bit 6 WAKIF: Bus Activity Wake-up Interrupt Flag bit 1 = Activity on the CAN bus has occurred 0 = Activity on the CAN bus has not occurred bit 5 ERRIF: CAN Bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = An error has not occurred in the CAN module bit 4 TXB2IF: Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message, and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message bit 3 TXB1IF: Transmit Buffer 1 Interrupt Flag bit 1 = Transmit Buffer 1 has completed transmission of a message, and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message bit 2 TXB0IF: Transmit Buffer 0 Interrupt Flag bit 1 = Transmit Buffer 0 has completed transmission of a message, and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message bit 1 RXB1IF: Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message bit 0 RXB0IF: Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 83

PIC18CXX8 REGISTER 7-6: PIE REGISTERS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 PIE2 — CMIE — — BCLIE LVDIE TMR3IE CCP2IE bit 7 bit 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PIE3 IVRE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE bit 7 bit 0 PIE1 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS30475A-page 84 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 7-6: PIE REGISTERS (CONT’D) PIE2 bit 7 Unimplemented: Read as ’0’ bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5-4 Unimplemented: Read as ’0’ bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 LVDIE: Low-voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt PIE3 bit 7 IVRE: Invalid CAN Message Received Interrupt Enable bit 1 = Enables the Invalid CAN Message Received Interrupt 0 = Disables the Invalid CAN Message Received Interrupt bit 6 WAKIE: Bus Activity Wake-up Interrupt Enable bit 1 = Enables the Bus Activity Wake-Up Interrupt 0 = Disables the Bus Activity Wake-Up Interrupt bit 5 ERRIE: CAN Bus Error Interrupt Enable bit 1 = Enables the CAN Bus Error Interrupt 0 = Disables the CAN Bus Error Interrupt bit 4 TXB2IE: Transmit Buffer 2 Interrupt Enable bit 1 = Enables the Transmit Buffer 2 Interrupt 0 = Disables the Transmit Buffer 2 Interrupt bit 3 TXB1IE: Transmit Buffer 1 Interrupt Enable bit 1 = Enables the Transmit Buffer 1 Interrupt 0 = Disables the Transmit Buffer 1 Interrupt bit 2 TXB0IE: Transmit Buffer 0 Interrupt Enable bit 1 = Enables the Transmit Buffer 0 Interrupt 0 = Disables the Transmit Buffer 0 Interrupt bit 1 RXB1IE: Receive Buffer 1 Interrupt Enable bit 1 = Enables the Receive Buffer 1 Interrupt 0 = Disables the Receive Buffer 1 Interrupt bit 0 RXB0IE: Receive Buffer 0 Interrupt Enable bit 1 = Enables the Receive Buffer 0 Interrupt 0 = Disables the Receive Buffer 0 Interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 85

PIC18CXX8 REGISTER 7-7: IPR REGISTERS R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 U-0 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 IPR2 — CMIP — — BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IPR3 IVRP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP bit 7 bit 0 IPR1 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: USART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS30475A-page 86 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 7-7: IPR REGISTERS (CONT’D) IPR2 bit 7 Unimplemented: Read as ’0’ bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5-4 Unimplemented: Read as ’0’ bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 LVDIP: Low Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority IPR3 bit 7 IVRP: Invalid Message Received Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: Bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN Bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXB2IP: Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: Transmit Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 TXB0IP: Transmit Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 RXB1IP: Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RXB0IP: Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 87

PIC18CXX8 7.1.6 INT INTERRUPTS TMR0H:TMR0L registers will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clearing External interrupts on the RB0/INT0, RB1/INT1, enable bit TMR0IE (INTCON register). Interrupt priority RB2/INT2, and RB3/INT3 pins are edge triggered: for Timer0 is determined by the value contained in the either rising if the corresponding INTEDGx bit is set in interrupt priority bit TMR0IP (INTCON2 register). See the INTCON2 register, or falling, if the INTEDGx bit is Section10.0 for further details on the Timer0 module. clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxIF is set. This interrupt 7.1.8 PORTB INTERRUPT-ON-CHANGE can be disabled by clearing the corresponding enable bit INTxIE. Flag bit INTxIF must be cleared in software An input change on PORTB<7:4> sets flag bit RBIF in the Interrupt Service Routine before re-enabling the (INTCON register). The interrupt can be enabled/ interrupt. All external interrupts (INT0, INT1, INT2, and disabled by setting/clearing enable bit RBIE (INTCON INT3) can wake-up the processor from SLEEP, if bit register). Interrupt priority for PORTB interrupt- INTxIE was set prior to going into SLEEP. If the global on-change is determined by the value contained in the interrupt enable bit GIE is set, the processor will branch interrupt priority bit RBIP (INTCON2 register). to the interrupt vector following wake-up. 7.2 Context Saving During Interrupts Interrupt priority for INT1, INT2 and INT3 is determined by the value contained in the interrupt priority bits During an interrupt, the return PC value is saved on the INT1IP (INTCON3 register), INT3IP (INTCON3 regis- stack. Additionally, the WREG, STATUS and BSR reg- ter), and INT2IP (INTCON2 register). There is no prior- isters are saved on the fast return stack. If a fast return ity bit associated with INT0; it is always a high priority from interrupt is not used (See Section4.3), the user interrupt source. may need to save the WREG, STATUS and BSR regis- ters in software. Depending on the user’s application, 7.1.7 TMR0 INTERRUPT other registers may also need to be saved. Example7-1 saves and restores the WREG, STATUS In 8-bit mode (which is the default), an overflow (FFh → and BSR registers during an Interrupt Service Routine. 00h) in the TMR0 register will set flag bit TMR0IF. In 16-bit mode, an overflow (FFFFh → 0000h) in the EXAMPLE 7-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in Low Access bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS30475A-page 88 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 8.0 I/O PORTS EXAMPLE 8-1: INITIALIZING PORTA CLRF PORTA ; Initialize PORTA by Depending on the device selected, there are up to ; clearing output eleven ports available. Some pins of the I/O ports are ; data latches multiplexed with an alternate function from the periph- CLRF LATA ; Alternate method eral features on the device. In general, when a periph- ; to clear output eral is enabled, that pin may not be used as a general ; data latches purpose I/O pin. MOVLW 0x07 ; Configure A/D MOVWF ADCON1 ; for digital inputs Each port has three registers for its operation. These MOVLW 0xCF ; Value used to registers are: ; initialize data (cid:127) TRIS register (Data Direction register) ; direction (cid:127) PORT register (reads the levels on the pins of the MOVWF TRISA ; Set RA3:RA0 as inputs device) ; RA5:RA4 as outputs (cid:127) LAT register (output latch) The data latch (LAT register) is useful for read-modify-write operations on the value that the I/O pins are driving. FIGURE 8-1: RA3:RA0 AND RA5 PINS BLOCK DIAGRAM 8.1 PORTA, TRISA and LATA Registers PORTA is a 6-bit wide, bi-directional port. The corre- sponding Data Direction register is TRISA. Setting a RD LATA TRISA bit (=1) will make the corresponding PORTA pin Data Bus an input (i.e., put the corresponding output driver in a D Q hi-impedance mode). Clearing a TRISA bit (=0) will VDD make the corresponding PORTA pin an output (i.e., put WR LATA the contents of the output latch on the selected pin). oWrR PORTA CK Q P Data Latch On a Power-on Reset, these pins are configured as inputs and read as '0'. D Q N I/O Pin(1) Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. WR TRISA CK Q VSS Analog Read-modify-write operations on the LATA register, Input reads and writes the latched output value for PORTA. TRIS Latch Mode The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The TTL RD TRISA Input RA4/T0CKI pin is a Schmitt Trigger input and an open Buffer drain output. All other RA port pins have TTL input lev- Q D els and full CMOS output drivers. The other PORTA pins are multiplexed with analog EN inputs and the analog VREF+ and VREF- inputs. The operation of each pin is selected by clearing/setting the RD PORTA control bits in the ADCON1 register (A/D Control SS Input (RA5 only) Register1). On a Power-on Reset, these pins are con- figured as analog inputs and read as '0'. To A/D Converter and LVD Modules The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. Note 1: I/O pins have diode protection to VDD and VSS. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 89

PIC18CXX8 FIGURE 8-2: RA4/T0CKI PIN BLOCK FIGURE 8-3: RA6 BLOCK DIAGRAM DIAGRAM ECRA6 or RCRA6 Enable Data Bus RD LATA Data RD LATA Bus D Q WR LATA D Q or CK Q VDD WR PORTA Data Latch N I/O Pin(1) WR LATA or CK Q P WR PORTA D Q VSS Data Latch WR TRISA CK Q Schmitt D Q N I/O Pin(1) Trigger Input TRIS Latch Buffer WR CK Q VSS TRISA ECRA6 or TRIS Latch RCRA6 RD TRISA Enable Data Bus TTL Q D Input RD TRISA Buffer ENEN RD PORTA Data Bus TMR0 Clock Input Q D Note 1: I/O pin has diode protection to VSS only. EN RD PORTA Note 1: I/O pins have diode protection to VDD and VSS. TABLE 8-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2/VREF- bit2 TTL Input/output or analog input or VREF-. RA3/AN3/VREF+ bit3 TTL Input/output or analog input or VREF+. RA4/T0CKI bit4 ST/OD Input/output or external clock input for Timer0 output is open drain type. RA5/SS/AN4/LVDIN bit5 TTL Input/output or slave select input for synchronous serial port or analog input, or low voltage detect input. OSC2/CLKO/RA6 bit6 TTL OSC2 or clock output or I/O pin. Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open Drain TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 -uuu uuuu LATA — Latch A Data Output Register -xxx xxxx -uuu uuuu TRISA — PORTA Data Direction Register -111 1111 -111 1111 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. DS30475A-page 90 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 8.2 PORTB, TRISB and LATB Registers Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is per- PORTB is an 8-bit wide bi-directional port. The corre- formed by clearing bit RBPU (INTCON2 register). The sponding Data Direction register is TRISB. Setting a weak pull-up is automatically turned off when the port TRISB bit (=1) will make the corresponding PORTB pin pin is configured as an output. The pull-ups are dis- an input (i.e., put the corresponding output driver in a abled on a Power-on Reset. hi-impedance mode). Clearing a TRISB bit (=0) will Four of PORTB’s pins, RB7:RB4, have an make the corresponding PORTB pin an output ( i.e., interrupt-on-change feature. Only pins configured as put the contents of the output latch on the selected pin). inputs can cause this interrupt to occur (i.e., any Read-modify-write operations on the LATB register RB7:RB4 pin configured as an output is excluded from read and write the latched output value for PORTB. the interrupt-on-change comparison). The input pins (of RB7:RB4) are compared with the old value latched EXAMPLE 8-2: INITIALIZING PORTB on the last read of PORTB. The “mismatch” outputs of CLRF PORTB ; Initialize PORTB by RB7:RB4 are OR’d together to generate the RB Port ; clearing output Change Interrupt with flag bit RBIF (INTCON register). ; data latches This interrupt can wake the device from SLEEP. The CLRF LATB ; Alternate method user, in the Interrupt Service Routine, can clear the ; to clear output interrupt in the following manner: ; data latches a) Any read or write of PORTB (except with the MOVLW 0xCF ; Value used to MOVFF instruction). This will end the mismatch ; initialize data condition. ; direction b) Clear flag bit RBIF. MOVWF TRISB ; Set RB3:RB0 as inputs ; RB5:RB4 as outputs A mismatch condition will continue to set flag bit RBIF. ; RB7:RB6 as inputs Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for FIGURE 8-4: RB7:RB4 PINS BLOCK wake-up on key depression operation and operations DIAGRAM where PORTB is only used for the interrupt on change VDD feature. Polling of PORTB is not recommended while RBPU(2) Weak using the interrupt-on-change feature. P Pull-up Data Latch Data Bus FIGURE 8-5: RB3:RB0 PINS BLOCK D Q DIAGRAM I/O pin(1) WoWrRR LPAOTRBTB CK RBPU(2) VDDWeak TRIS Latch P Pull-up D Q Data Latch Data Bus WR TRISB TTL D Q CK Input I/O Pin(1) Buffer ST WR Port CK Buffer TRIS Latch RD TRISB D Q TTL WR TRIS Input CK Buffer RD LATB Latch Q D RD PORTB EN Q1 RD TRIS Set RBIF Q D RD Port EN From other Q D RB7:RB4 pins RD PORTB Schmitt Trigger EN RBx/INTx Buffer Q3 RBx/INTx RD Port Note 1: I/O pins have diode protection to VDD and VSS. Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). bit(s) and clear the RBPU bit (INTCON2 register).  2000 Microchip Technology Inc. Advanced Information DS30475A-page 91

PIC18CXX8 TABLE 8-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT0 bit0 TTL/ST(1) Input/output pin or external interrupt 0 input. Internal software programmable weak pull-up. RB1/INT1 bit1 TTL/ST(1) Input/output pin or external interrupt 1 input. Internal software programmable weak pull-up. RB2/INT2 bit2 TTL/ST(1) Input/output pin or external interrupt 2 input. Internal software programmable weak pull-up. RB3/INT3 bit3 TTL/ST(1) Input/output pin or external interrupt 3 input. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. TABLE 8-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu LATB LATB Data Output Register xxxx xxxx uuuu uuuu TRISB PORTB Data Direction Register 1111 1111 1111 1111 INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 1111 1111 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 1100 0000 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30475A-page 92 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 8.3 PORTC, TRISC and LATC Registers put, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the correspond- PORTC is an 8-bit wide, bi-directional port. The corre- ing peripheral section for the correct TRIS bit settings. sponding Data Direction register is TRISC. Setting a The pin override value is not loaded into the TRIS reg- TRISC bit (=1) will make the corresponding PORTC pin ister. This allows read-modify-write of the TRIS register, an input (i.e., put the corresponding output driver in a without concern due to peripheral overrides. hi-impedance mode). Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output (i.e., put EXAMPLE 8-3: INITIALIZING PORTC the contents of the output latch on the selected pin). CLRF PORTC ; Initialize PORTC by Read-modify-write operations on the LATC register, ; clearing output read and write the latched output value for PORTC. ; data latches PORTC is multiplexed with several peripheral functions CLRF LATC ; Alternate method (Table8-5). PORTC pins have Schmitt Trigger input ; to clear output ; data latches buffers. MOVLW 0xCF ; Value used to When enabling peripheral functions, care should be ; initialize data taken in defining TRIS bits for each PORTC pin. Some ; direction peripherals override the TRIS bit to make a pin an out- MOVWF TRISC ; Set RC3:RC0 as inputs ; RC5:RC4 as outputs ; RC7:RC6 as inputs FIGURE 8-6: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) Peripheral Out Select Peripheral Data Out 0 VDD P 1 RD LATC Data Bus D Q WR LATC I/O Pin or CK Q WR PORTC Data Latch N D Q WR TRISC TRIS VSS CK Q Override TRIS Latch RD TRISC Schmitt Peripheral Enable Trigger Q D EN RD PORTC Peripheral Data In TRIS OVERRIDE Pin Override Peripheral RC0 Yes Timer1 OSC for Timer1/Timer3 RC1 Yes Timer1 OSC for Timer1/Timer3 RC2 No — RC3 Yes SPI/I2C Master Clock RC4 Yes I2C Data Out RC5 Yes SPI Data Out RC6 Yes USART Async Xmit, Sync Clock RC7 Yes USART Sync Data Out Note: I/O pins have diode protection to VDD and VSS.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 93

PIC18CXX8 TABLE 8-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T13CKI ST Input/output port pin or Timer1 oscillator output or Timer1/Timer3 clock bit0 input. RC1/T1OSI ST Input/output port pin or Timer1 oscillator input. bit1 RC2/CCP1 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 bit2 output. RC3/SCK/SCL ST Input/output port pin or Synchronous Serial clock for SPI/I2C. bit3 RC4/SDI/SDA ST Input/output port pin or SPI Data in (SPI mode) or Data I/O bit4 (I2C mode). RC5/SDO ST Input/output port pin or Synchronous Serial Port data output. bit5 RC6/TX/CK ST Input/output port pin Addressable USART Asynchronous Transmit or bit6 Addressable USART Synchronous Clock. RC7/RX/DT ST Input/output port pin Addressable USART Asynchronous Receive or bit7 Addressable USART Synchronous Data. Legend: ST = Schmitt Trigger input TABLE 8-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu LATC LATC Data Output Register xxxx xxxx uuuu uuuu TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged DS30475A-page 94 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 8.4 PORTD, TRISD and LATD Registers FIGURE 8-7: PORTD BLOCK DIAGRAM IN I/O PORT MODE PORTD is an 8-bit wide, bi-directional port. The corre- sponding Data Direction register is TRISD. Setting a TRISD bit (=1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a RD LATD hi-impedance mode). Clearing a TRISD bit (=0) will Data Bus make the corresponding PORTD pin an output (i.e., put D Q the contents of the output latch on the selected pin). I/O Pin WR LATD CK Read-modify-write operations on the LATD register or WR PORTD reads and writes the latched output value for PORTD. Data Latch PORTD is an 8-bit port with Schmitt Trigger input buff- D Q ers. Each pin is individually configurable as an input or Schmitt WR TRISD Trigger output. CK Input Buffer PORTD can be configured as an 8-bit wide micro- TRIS Latch processor port (parallel slave port), by setting control bit PSPMODE (PSPCON register). In this mode, the input buffers are TTL. See Section9.0 for additional RD TRISD information on the Parallel Slave Port (PSP). Q D EXAMPLE 8-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ENEN ; clearing output RD PORTD ; data latches CLRF LATD ; Alternate method ; to clear output Note: I/O pins have diode protection to VDD and VSS. ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD3:RD0 as inputs ; RD5:RD4 as outputs ; RD7:RD6 as inputs  2000 Microchip Technology Inc. Advanced Information DS30475A-page 95

PIC18CXX8 TABLE 8-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0. RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1. RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2. RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3. RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4. RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5. RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6. RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode. TABLE 8-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on Value on all POR, other Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOR RESETS PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu LATD LATD Data Output Register xxxx xxxx uuuu uuuu TRISD PORTD Data Direction Register 1111 1111 1111 1111 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ---- Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD. DS30475A-page 96 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 8.5 PORTE, TRISE and LATE Registers EXAMPLE 8-5: INITIALIZING PORTE CLRF PORTE ; Initialize PORTE by PORTE is an 8-bit wide, bi-directional port. The corre- ; clearing output sponding Data Direction register is TRISE. Setting a ; data latches TRISE bit (=1) will make the corresponding PORTE pin CLRF LATE ; Alternate method an input (i.e., put the corresponding output driver in a ; to clear output hi-impedance mode). Clearing a TRISE bit (=0) will ; data latches make the corresponding PORTE pin an output (i.e., put MOVLW 0x03 ; Value used to the contents of the output latch on the selected pin). ; initialize data ; direction Read-modify-write operations on the LATE register MOVWF TRISE ; Set RE1:RE0 as inputs reads and writes the latched output value for PORTE. ; RE7:RE2 as outputs PORTE is an 8-bit port with Schmitt Trigger input buff- ers. Each pin is individually configurable as an input or output. PORTE is multiplexed with several peripheral functions (Table8-9). FIGURE 8-8: PORTE BLOCK DIAGRAM Peripheral Out Select Peripheral Data Out 0 VDD P 1 RD LATE Data Bus D Q WR LATE I/O Pin(1) CK Q or WR PORTE Data Latch N D Q WR TRISE TRIS VSS CK Q Override TRIS Latch Peripheral Enable RD TRISE Schmitt Trigger Q D EN RD PORTE Peripheral Data In TRIS OVERRIDE Pin Override Peripheral RE0 Yes PSP RE1 Yes PSP RE2 Yes PSP RE3 No — RE4 No — RE5 No — RE6 No — RE7 No — Note 1: I/O pins have diode protection to VDD and VSS.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 97

PIC18CXX8 TABLE 8-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/RD bit0 ST/TTL(1) Input/output port pin or Read control input in Parallel Slave Port mode. RE1/WR bit1 ST/TTL(1) Input/output port pin or Write control input in Parallel Slave Port mode. RE2/CS bit2 ST/TTL(1) Input/output port pin or Chip Select control input in Parallel Slave Port mode. RE3 bit3 ST Input/output port pin. RE4 bit4 ST Input/output port pin. RE5 bit5 ST Input/output port pin. RE6 bit6 ST Input/output port pin. RE7/CCP2 bit7 ST Input/output port pin or Capture 2 input/Compare 2 output. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode. TABLE 8-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on: Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS TRISE PORTE Data Direction Control Register 1111 1111 1111 1111 PORTE Read PORTE pin/Write PORTE Data Latch xxxx xxxx uuuu uuuu LATE Read PORTE Data Latch/Write PORTE Data Latch xxxx xxxx uuuu uuuu PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ---- Legend: x = unknown, u = unchanged DS30475A-page 98 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 8.6 PORTF, LATF, and TRISF Registers EXAMPLE 8-6: INITIALIZING PORTF CLRF PORTF ; Initialize PORTF by PORTF is an 8-bit wide, bi-directional port. The corre- ; clearing output sponding Data Direction register is TRISF. Setting a ; data latches TRISF bit (=1) will make the corresponding PORTF pin CLRF LATF ; Alternate method an input (i.e., put the corresponding output driver in a ; to clear output hi-impedance mode). Clearing a TRISF bit (=0) will ; data latches make the corresponding PORTF pin an output (i.e., put MOVLW 0x07 ; the contents of the output latch on the selected pin). MOVWF CMCON ; Turn off comparators MOVLW 0x0F ; Read-modify-write operations on the LATF register MOVWF ADCON1 ; Set PORTF as digital I/O reads and writes the latched output value for PORTF. MOVLW 0xCF ; Value used to ; initialize data PORTF is multiplexed with several analog peripheral ; direction functions including the A/D converter inputs and com- MOVWF TRISF ; Set RF3:RF0 as inputs parator inputs, outputs, and voltage reference. ; RF5:RF4 as outputs Note 1: On a Power-on Reset, the RF6:RF0 pins ; RF7:RF6 as inputs are configured as inputs and read as ’0’. 2: To configure PORTF as digital I/O, turn off comparators and set ADCON1 value. FIGURE 8-9: PORTF RF1/AN6/C2OUT, RF2/AN5/C1OUT BLOCK DIAGRAM PORT/Comparator Select Comparator Data Out 0 VDD P 1 RD LATF Data Bus D Q WR LATF I/O Pin CK Q or WR PORTF Data Latch N D Q WR TRISF VSS CK Q TRIS Latch Analog Input Mode RD TRISF Schmitt Trigger Q D EN RD PORTF To A/D Converter Note: I/O pins have diode protection to VDD and VSS.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 99

PIC18CXX8 FIGURE 8-10: RF6:RF3 AND RF0 PINS FIGURE 8-11: RF7 PIN BLOCK DIAGRAM BLOCK DIAGRAM RD LATF RD LATF Data Bus Data D Q Bus D Q WR LATF I/O pin VDD or CK WR LATF WR PORTF or CK Q Data Latch P WR PORTF Data Latch D Q Schmitt D Q N I/O Pin WR TRISF Trigger CK Input Buffer WR TRISF TRIS Latch CK Q VSS Analog TRIS Latch Input Mode RD TRISF RD TRISF ST Q D Input Buffer Q D ENEN RD PORTF EN RD PORTF Note: I/O pins have diode protection to VDD and VSS. To A/D Converter or Comparator Input Note: I/O pins have diode protection to VDD and VSS. TABLE 8-11: PORTF FUNCTIONS Name Bit# Buffer Type Function RF0/AN5 bit0 ST Input/output port pin or analog input. RF1/AN6/C2OUT bit1 ST Input/output port pin or analog input or comparator 2 output. RF2/AN7/C1OUT bit2 ST Input/output port pin or analog input or comparator 1 output. RF3/AN8 bit3 ST Input/output port pin or analog input or comparator input. RF4/AN9 bit4 ST Input/output port pin or analog input or comparator input. RF5/AN10/ bit5 ST Input/output port pin or analog input or comparator input or comparator CVREF reference output. RF6/AN11 bit6 ST Input/output port pin or analog input or comparator input. RF7 bit7 ST Input/output port pin. Legend: ST = Schmitt Trigger input TABLE 8-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Value on: Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other RESETS BOR TRISF PORTF Data Direction Control Register 1111 1111 1111 1111 PORTF Read PORTF pin / Write PORTF Data Latch xxxx xxxx uuuu uuuu LATF Read PORTF Data Latch/Write PORTF Data Latch 0000 0000 uuuu uuuu ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged DS30475A-page 100 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 8.7 PORTG, LATG, and TRISG Registers EXAMPLE 8-7: INITIALIZING PORTG CLRF PORTG ; Initialize PORTG by PORTG is a 5-bit wide, bi-directional port. The corre- ; clearing output sponding Data Direction register is TRISG. Setting a ; data latches TRISG bit (=1) will make the corresponding PORTG pin CLRF LATG ; Alternate method an input (i.e., put the corresponding output driver in a ; to clear output hi-impedance mode). Clearing a TRISG bit (=0) will ; data latches make the corresponding PORTG pin an output (i.e., put MOVLW 0x04 ; Value used to the contents of the output latch on the selected pin). ; initialize data ; direction Read-modify-write operations on the LATG register MOVWF TRISG ; Set RG1:RG0 as outputs read and write the latched output value for PORTG. ; RG2 as input ; RG4:RG3 as outputs Pins RG0-RG2 on PORTG are multiplexed with the CAN peripheral. Refer to "CAN Module", Section17.0 for proper settings of TRISG when CAN is enabled. FIGURE 8-12: RG0/CANTX0 PIN BLOCK DIAGRAM OPMODE2:OPMODE0=000 TXD ENDRHI 0 RD LATG VDD Data Bus 1 D Q P WR PORTG or WR LATG CK Q Data Latch I/O Pin D Q WR TRISG N CK Q TRIS Latch VSS OPMODE2:OPMODE0 = 000 Schmitt RD TRISG Trigger Q D ENEN RD PORTG Note: I/O pins have diode protection to VDD and VSS.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 101

PIC18CXX8 FIGURE 8-13: RG1/CANTX1 PIN BLOCK DIAGRAM TX1SRC OPMODE2:OPMODE0=000 TX1EN TXD 0 CANCLK 1 ENDRHI 0 RD LATG VDD 1 Data Bus D Q P WR PORTG or WR LATG CK Q Data Latch I/O Pin D Q WR TRISG N CK Q TRIS Latch VSS OPMODE2:OPMODE0 = 000 RD TRISG Schmitt Trigger Q D ENEN RD PORTG Note: I/O pins have diode protection to VDD and VSS. FIGURE 8-14: RG2/CANRX PIN BLOCK FIGURE 8-15: RG4:RG3 PINS BLOCK DIAGRAM DIAGRAM RD LATG RD LATG Data Data Bus Bus D Q D Q I/O Pin I/O Pin WR LATG WR LATG or CK or CK WR PORTG Data Latch WR PORTG Data Latch D Q D Q Schmitt Schmitt WR TRISG Trigger WR TRISG Trigger CK Input CK Input Buffer Buffer TRIS Latch TRIS Latch RD TRISG RD TRISG Q D Q D ENEN ENEN RD PORTG RD PORTG CANRX Note: I/O pins have diode protection to VDD and VSS. Note: I/O pins have diode protection to VDD and VSS. DS30475A-page 102 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 8-13: PORTG FUNCTIONS Name Bit# Buffer Type Function RG0/CANTX0 bit0 ST Input/output port pin or CAN bus transmit output. RG1/CANTX1 bit1 ST Input/output port pin or CAN bus complimentary transmit output or CAN bus bit time clock. RG2/CANRX bit2 ST Input/output port pin or CAN bus receive input. RG3 bit3 ST Input/output port pin. RG4 bit4 ST Input/output port pin. Legend: ST = Schmitt Trigger input Note: Refer to "CAN Module", Section17.0 for usage of CAN pin functions. TABLE 8-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Value on: Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS TRISG PORTG Data Direction Control Register ---1 1111 ---1 1111 PORTG Read PORTG pin / Write PORTG Data Latch ---x xxxx ---u uuuu LATG Read PORTG Data Latch/Write PORTG Data Latch ---x xxxx ---u uuuu CIOCON TX1SRC TX1EN ENDRHI CANCAP — — — — 0000 ---- 0000 ---- Legend: x = unknown, u = unchanged  2000 Microchip Technology Inc. Advanced Information DS30475A-page 103

PIC18CXX8 8.8 PORTH, LATH, and TRISH Registers EXAMPLE 8-8: INITIALIZING PORTH CLRF PORTH ; Initialize PORTH by Note: This port is available on PIC18C858. ; clearing output ; data latches PORTH is a 5-bit wide, bi-directional port available only CLRF LATH ; Alternate method on the PIC18C858 devices. The corresponding Data ; to clear output Direction register is TRISH. Setting a TRISH bit (=1) ; data latches will make the corresponding PORTH pin an input (i.e., MOVLW 0x0F ; put the corresponding output driver in a hi-impedance MOVWF ADCON1 ; mode). Clearing a TRISH bit (=0) will make the corre- MOVLW 0xCF ; Value used to ; initialize data sponding PORTH pin an output (i.e., put the contents ; direction of the output latch on the selected pin). MOVWF TRISH ; Set RH3:RH0 as inputs Read-modify-write operations on the LATH register ; RH5:RH4 as outputs read and write the latched output value for PORTH. ; RH7:RH6 as inputs Pins RH0-RH3 on the PIC18C858 are bi-directional I/O pins with ST input buffers. Pins RH4-RH7 on all devices are multiplexed with A/D converter inputs. FIGURE 8-17: RH7:RH4 PINS BLOCK Note: On a Power-on Reset, the RH7:RH4 pins DIAGRAM are configured as inputs and read as ’0’. FIGURE 8-16: RH3:RH0 PINS BLOCK RD LATH DIAGRAM Data Bus D Q VDD WR LATH RD LATH or CK Q P Data Bus WR PORTH D Q Data Latch VDD WR LATH or CK Q P D Q N I/O Pin WR PORTH Data Latch WR TRISH CK Q VSS I/O Pin D Q Analog TRIS Latch Input WR TRISH CK Q N Mode TRIS Latch VSS ST RD TRISH Input RD TRISH Buffer Schmitt Q D Trigger Q D RD EN EN PORTH RD PORTH Note: I/O pins have diode protection to VDD and VSS. To A/D Converter Note: I/O pins have diode protection to VDD and VSS. DS30475A-page 104 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 8-15: PORTH FUNCTIONS Name Bit# Buffer Type Function RH0 bit0 ST Input/output port pin. RH1 bit1 ST Input/output port pin. RH2 bit2 ST Input/output port pin. RH3 bit3 ST Input/output port pin. RH4/AN12 bit4 ST Input/output port pin or analog input channel 12. RH5/AN13 bit5 ST Input/output port pin or analog input channel 13. RH6/AN14 bit6 ST Input/output port pin or analog input channel 14. RH7/AN15 bit7 ST Input/output port pin or analog input channel 15. Legend: ST = Schmitt Trigger input TABLE 8-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Value on: Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS TRISH PORTH Data Direction Control Register 1111 1111 1111 1111 PORTH Read PORTH pin/Write PORTH Data Latch xxxx xxxx uuuu uuuu LATH Read PORTH Data Latch/Write PORTH Data Latch xxxx xxxx uuuu uuuu ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented  2000 Microchip Technology Inc. Advanced Information DS30475A-page 105

PIC18CXX8 8.9 PORTJ, LATJ, and TRISJ Registers EXAMPLE 8-9: INITIALIZING PORTJ CLRF PORTJ ; Initialize PORTJ by Note: This port is available on PIC18C858. ; clearing output ; data latches PORTJ is an 8-bit wide, bi-directional port available CLRF LATJ ; Alternate method only on the PIC18C858 devices. The corresponding ; to clear output Data Direction register is TRISJ. Setting a TRISJ bit ; data latches (=1) will make the corresponding PORTJ pin an input MOVLW 0xCF ; Value used to (i.e., put the corresponding output driver in a ; initialize data hi-impedance mode). Clearing a TRISJ bit (=0) will ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs make the corresponding PORTJ pin an output (i.e., put ; RJ5:RJ4 as outputs the contents of the output latch on the selected pin). ; RJ7:RJ6 as inputs Read-modify-write operations on the LATJ register read and write the latched output value for PORTJ. PORTJ on the PIC18C858 is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually config- urable as an input or output. FIGURE 8-18: PORTJ BLOCK DIAGRAM RD LATJ Data Bus D Q VDD WR LATJ CK Q or P WR PORTJ Data Latch I/O Pin N D Q VSS WR TRISJ CK Q TRIS Latch RD TRISJ Schmitt Trigger Q D EN RD PORTJ Note: I/O pins have diode protection to VDD and VSS. DS30475A-page 106 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 8-17: PORTJ FUNCTIONS Name Bit# Buffer Type Function RJ0 bit0 ST/TTL Input/output port pin. RJ1 bit1 ST/TTL Input/output port pin. RJ2 bit2 ST/TTL Input/output port pin. RJ3 bit3 ST/TTL Input/output port pin. RJ4 bit4 ST/TTL Input/output port pin. RJ5 bit5 ST/TTL Input/output port pin. RJ6 bit6 ST/TTL Input/output port pin. RJ7 bit7 ST/TTL Input/output port pin. Legend: ST = Schmitt Trigger input, TTL = TTL input TABLE 8-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Value on: Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS TRISJ PORTJ Data Direction Control Register 1111 1111 1111 1111 PORTJ Read PORTJ pin/Write PORTJ Data Latch xxxx xxxx uuuu uuuu LATJ Read PORTJ Data Latch/Write PORTJ Data Latch xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged  2000 Microchip Technology Inc. Advanced Information DS30475A-page 107

PIC18CXX8 8.10 PORTK, LATK, and TRISK Registers FIGURE 8-19: PORTK BLOCK DIAGRAM Note: This port is available on PIC18C858. PORTK is an 8-bit wide, bi-directional port available RD LATK only on the PIC18C858 devices. The corresponding Data Bus Data Direction register is TRISK. Setting a TRISK bit D Q (=1) will make the corresponding PORTK pin an input I/O Pin WR LATK (i.e., put the corresponding output driver in a or CK hi-impedance mode). Clearing a TRISK bit (=0) will WR PORTK Data Latch make the corresponding PORTK pin an output (i.e., put D Q the contents of the output latch on the selected pin). Schmitt Read-modify-write operations on the LATK register WR TRISK Trigger CK Input read and write the latched output value for PORTK. Buffer TRIS Latch PORTK is an 8-bit port with Schmitt Trigger input buff- ers. Each pin is individually configurable as an input or output. RD TRISK EXAMPLE 8-10: INITIALIZING PORTK Q D CLRF PORTK ; Initialize PORTK by ; clearing output ENEN ; data latches CLRF LATK ; Alternate method RD PORTK ; to clear output ; data latches MOVLW 0xCF ; Value used to Note: I/O pins have diode protection to VDD and VSS. ; initialize data ; direction MOVWF TRISK ; Set RK3:RK0 as inputs ; RK5:RK4 as outputs ; RK7:RK6 as inputs TABLE 8-19: PORTK FUNCTIONS Name Bit# Buffer Type Function RK0 bit0 ST Input/output port pin. RK1 bit1 ST Input/output port pin. RK2 bit2 ST Input/output port pin. RK3 bit3 ST Input/output port pin. RK4 bit4 ST Input/output port pin. RK5 bit5 ST Input/output port pin. RK6 bit6 ST Input/output port pin. RK7 bit7 ST Input/output port pin. Legend: ST = Schmitt Trigger input TABLE 8-20: SUMMARY OF REGISTERS ASSOCIATED WITH PORTK Value on: Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other RESETS TRISK PORTK Data Direction Control Register 1111 1111 1111 1111 PORTK Read PORTK pin / Write PORTK Data Latch xxxx xxxx uuuu uuuu LATK Read PORTK Data Latch/Write PORTK Data Latch xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged DS30475A-page 108 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 9.0 PARALLEL SLAVE PORT FIGURE 9-1: PORTD AND PORTE BLOCK DIAGRAM The Parallel Slave Port is an 8-bit parallel interface for (PARALLEL SLAVE PORT) transferring data between the PIC18CXX8 device and an external device. PORTD operates as an 8-bit wide Parallel Slave Port, Data Bus D Q or microprocessor port when control bit PSPMODE (PSPCON register) is set. In Slave mode, it is asyn- RDx Pin WR LATD chronously readable and writable by the external world or CK WR PORTD through RD control input pin RE0/RD and WR control Data Latch TTL input pin RE1/WR. Q D It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the RD PORTD ENEN PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) RD LATD must be configured as inputs (set). A write to the PSP occurs when both the CS and WR lines are first detected low. A read from the PSP occurs One bit of PORTD when both the CS and RD lines are first detected low. Set Interrupt Flag The PORTE I/O pins become control inputs for the PSPIF (PIR1<7>) microprocessor port when bit PSPMODE (PSPCON Register) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs). In this mode, the input buffers are TTL. Read TTL RD Chip Select TTL CS Write TTL WR Note: I/O pins have diode protection to VDD and VSS.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 109

PIC18CXX8 REGISTER 9-1: PSPCON REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General purpose I/O mode bit 3-0 Unimplemented: Read as ’0’ Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 110 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 9-2: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF FIGURE 9-3: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF TABLE 9-1: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on all Value on other Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR RESETS PORTD Port data latch when written; port pins when read xxxx xxxx uuuu uuuu LATD LATD Data Output Bits xxxx xxxx uuuu uuuu TRISD PORTD Data Direction Bits 1111 1111 1111 1111 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000 LATE LATE Data Output Bits xxxx xxxx uuuu uuuu TRISE PORTE Data Direction Bits 1111 1111 1111 1111 INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by the Parallel Slave Port.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 111

PIC18CXX8 NOTES: DS30475A-page 112 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 10.0 TIMER0 MODULE Register10-1 shows the Timer0 Control register (T0CON). The Timer0 module has the following features: Figure10-1 shows a simplified block diagram of the (cid:127) Software selectable as an 8-bit or 16-bit Timer0 module in 8-bit mode and Figure10-1 shows a timer/counter simplified block diagram of the Timer0 module in 16-bit (cid:127) Readable and writable mode. (cid:127) Dedicated 8-bit software programmable prescaler (cid:127) Clock source selectable to be external or internal The T0CON register is a readable and writable register (cid:127) Interrupt on overflow from FFh to 00h in 8-bit that controls all the aspects of Timer0, including the mode and FFFFh to 0000h in 16-bit mode prescale selection. (cid:127) Edge select for external clock Note: Timer0 is enabled on POR. REGISTER 10-1: T0CON REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 113

PIC18CXX8 FIGURE 10-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 0 Sync with 1 Internal TMR0L Clocks RA4/T0CKI Programmable 1 Pin(2) Prescaler T0SE (2 TCY delay) 3 PSA Set Interrupt T0PS2, T0PS1, T0PS0 Flag bit TMR0IF T0CS(1) on Overflow Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 2: I/O pins have diode protection to VDD and VSS. FIGURE 10-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE FOSC/4 0 0 Sync with Set Interrupt 1 ICntleorcnkasl TMR0L HTigMh RB0yte Flag bit TMR0IF T0CKI Pin(2) Programmable 1 on Overflow Prescaler 8 T0SE (2 TCY delay) 3 Read TMR0L T0PS2, T0PS1, T0PS0 Write TMR0L T0CS(1) PSA 8 8 TMR0H 8 Data Bus<7:0> Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 2: I/O pins have diode protection to VDD and VSS. DS30475A-page 114 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 10.1 Timer0 Operation 10.2 Prescaler Timer0 can operate as a timer or as a counter. An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or Timer mode is selected by clearing the T0CS bit. In writable. Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0L reg- The PSA and T0PS2:T0PS0 bits determine the ister is written, the increment is inhibited for the follow- prescaler assignment and prescale ratio. ing two instruction cycles. The user can work around Clearing bit PSA will assign the prescaler to the Timer0 this by writing an adjusted value to the TMR0L register. module. When the prescaler is assigned to the Timer0 Counter mode is selected by setting the T0CS bit. In module, prescale values of 1:2, 1:4, ..., 1:256 are Counter mode, Timer0 will increment either on every selectable. rising or falling edge of pin RA4/T0CKI. The increment- When assigned to the Timer0 module, all instructions ing edge is determined by the Timer0 Source Edge writing to the TMR0 register (e.g. CLRF TMR0, Select bit (T0SE). Clearing the T0SE bit selects the ris- MOVWF TMR0, BSF TMR0, x.... etc.) will clear the ing edge. Restrictions on the external clock input are prescaler count. discussed below. Note: Writing to TMR0 when the prescaler is When an external clock input is used for Timer0, it must assigned to Timer0, will clear the prescaler meet certain requirements. The requirements ensure count but will not change the prescaler the external clock can be synchronized with the internal assignment. phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 10.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol (i.e., it can be changed “on-the-fly” during program execution).  2000 Microchip Technology Inc. Advanced Information DS30475A-page 115

PIC18CXX8 10.3 Timer0 Interrupt 10.4 16-Bit Mode Timer Reads and Writes The TMR0 interrupt is generated when the TMR0 reg- Timer0 can be set in 16-bit mode by clearing T0CON ister overflows from FFh to 00h in 8-bit mode or FFFFh T08BIT. Registers TMR0H and TMR0L are used to to 0000h in 16-bit mode. This overflow sets the TMR0IF access 16-bit timer value. bit. The interrupt can be masked by clearing the TMR0H is not the high byte of the timer/counter in TMR0IE bit. The TMR0IF bit must be cleared in soft- 16-bit mode, but is actually a buffered version of the ware by the Timer0 module interrupt service routine high byte of Timer0 (refer to Figure10-1). The high byte before re-enabling this interrupt. The TMR0 interrupt of the Timer0 counter/timer is not directly readable nor cannot awaken the processor from SLEEP, since the writable. TMR0H is updated with the contents of the timer is shut off during SLEEP. high byte of Timer0 during a read of TMR0L. This pro- vides the ability to read all 16-bits of Timer0 without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. A write to the high byte of Timer0 must also take place through the TMR0H buffer register. Timer0 high byte is updated with the contents of buffered value of TMR0H, when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on all other Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR RESETS TMR0L Timer0 Module’s Low Byte Register xxxx xxxx uuuu uuuu TMR0H Timer0 Module’s High Byte Register 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111 TRISA — PORTA Data Direction Register(1) --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read as ‘0’. DS30475A-page 116 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 11.0 TIMER1 MODULE Register11-1 shows the Timer1 control register. This register controls the operating mode of the Timer1 The Timer1 module timer/counter has the following fea- module as well as contains the Timer1 oscillator enable tures: bit (T1OSCEN). Timer1 can be enabled/disabled by (cid:127) 16-bit timer/counter setting/clearing control bit TMR1ON (T1CON register). (Two 8-bit registers: TMR1H and TMR1L) Figure11-1 is a simplified block diagram of the Timer1 (cid:127) Readable and writable (both registers) module. (cid:127) Internal or external clock select Note: Timer1 is disabled on POR. (cid:127) Interrupt on overflow from FFFFh to 0000h (cid:127) RESET from CCP module special event trigger REGISTER 11-1: T1CON REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register Read/Write of TImer1 in one 16-bit operation 0 = Enables register Read/Write of Timer1 in two 8-bit operations bit 6 Unimplemented: Read as '0' bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 Oscillator is enabled 0 = Timer1 Oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 117

PIC18CXX8 11.1 Timer1 Operation When TMR1CS is clear, Timer1 increments every instruction cycle. When TMR1CS is set, Timer1 incre- Timer1 can operate in one of these modes: ments on every rising edge of the external clock input (cid:127) As a timer or the Timer1 oscillator, if enabled. (cid:127) As a synchronous counter When the Timer1 oscillator is enabled (T1OSCEN is (cid:127) As an asynchronous counter set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is The operating mode is determined by the clock select ignored. bit, TMR1CS (T1CON register). Timer1 also has an internal “RESET input”. This RESET can be generated by the CCP module (Section14.0). FIGURE 11-1: TIMER1 BLOCK DIAGRAM CCP Special Event Trigger TMR1IF Overflow Interrupt TMR1 0 Synchronized Flag Bit CLR Clock Input TMR1H TMR1L 1 TMR1ON On/Off T1SYNC T1OSC T13CKI/T1OSO 1 T1OSCEN Prescaler Synchronize T1OSI EOnsaciblllaetor(1) IFnOteSrnCa/4l 0 1, 2, 4, 8 det Clock 2 SLEEP Input T1CKPS1:T1CKPS0 TMR1CS Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. FIGURE 11-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR1H 8 8 Write TMR1L Read TMR1L Special Event Trigger Synchronized TOMveRr1floIFw 8 TMR1 0 Clock Input Timer 1 Interrupt TMR1L high byte Flag bit 1 TMR1ON On/Off T1SYNC T1OSC T13CKI/T1OSO 1 Synchronize Prescaler T1OSCEN Fosc/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 TMR1CS SLEEP Input T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. DS30475A-page 118 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 11.2 Timer1 Oscillator 11.4 Resetting Timer1 using a CCP Trigger Output A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by If the CCP module is configured in Compare mode setting control bit T1OSCEN (T1CON register). The to generate a “special event trigger" oscillator is a low power oscillator rated up to 200 kHz. (CCP1M3:CCP1M0=1011), this signal will reset It will continue to run during SLEEP. It is primarily Timer1 and start an A/D conversion (if the A/D module intended for a 32 kHz crystal. Table11-1 shows the is enabled). capacitor selection for the Timer1 oscillator. Note: The special event triggers from the CCP1 The user must provide a software time delay to ensure module will not set interrupt flag bit proper start-up of the Timer1 oscillator. TMR1IF (PIR registers). TABLE 11-1: CAPACITOR SELECTION FOR Timer1 must be configured for either timer or Synchro- nized Counter mode to take advantage of this feature. THE ALTERNATE OSCILLATOR If Timer1 is running in Asynchronous Counter mode, Osc Type Freq C1 C2 this RESET operation may not work. LP 32 kHz TBD(1) TBD(1) In the event that a write to Timer1 coincides with a spe- cial event trigger from CCP1, the write will take prece- Crystal to be Tested: dence. 32.768 kHz Epson C-001R32.768K-A ± 20 PPM In this mode of operation, the CCPR1H:CCPR1L regis- ters pair, effectively becomes the period register for Note 1: Microchip suggests 33 pF as a starting Timer1. point in validating the oscillator circuit. 2: Higher capacitance increases the stability 11.5 Timer1 16-Bit Read/Write Mode of the oscillator, but also increases the start-up time. Timer1 can be configured for 16-bit reads and writes 3: Since each resonator/crystal has its own (see Figure11-2). When the RD16 control bit (T1CON characteristics, the user should consult the register) is set, the address for TMR1H is mapped to a resonator/crystal manufacturer for appropri- buffer register for the high byte of Timer1. A read from ate values of external components. TMR1L will load the contents of the high byte of Timer1 4: Capacitor values are for design guidance into the Timer1 high byte buffer. This provides the user only. with the ability to accurately read all 16 bits of Timer1, without having to determine whether a read of the high 11.3 Timer1 Interrupt byte followed by a read of the low byte is valid, due to a rollover between reads. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The A write to the high byte of Timer1 must also take place TMR1 Interrupt, if enabled, is generated on overflow, through the TMR1H buffer register. Timer1 high byte is which is latched in interrupt flag bit TMR1IF (PIR regis- updated with the contents of TMR1H when a write ters). This interrupt can be enabled/disabled by set- occurs to TMR1L. This allows a user to write all 16 bits ting/clearing TMR1 interrupt enable bit TMR1IE (PIE to both the high and low bytes of Timer1 at once. registers). The high byte of Timer1 is not directly readable or writ- able in this mode. All reads and writes must take place through the Timer1 high byte buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 119

PIC18CXX8 TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on Value on all other Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. DS30475A-page 120 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 12.0 TIMER2 MODULE 12.1 Timer2 Operation The Timer2 module timer has the following features: Timer2 can be used as the PWM time-base for the (cid:127) 8-bit timer (TMR2 register) PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device (cid:127) 8-bit period register (PR2) RESET. The input clock (FOSC/4) has a prescale option (cid:127) Readable and writable (both registers) of 1:1, 1:4 or 1:16, selected by control bits (cid:127) Software programmable prescaler (1:1, 1:4, 1:16) T2CKPS1:T2CKPS0 (T2CON Register). The match (cid:127) Software programmable postscaler (1:1 to 1:16) output of TMR2 goes through a 4-bit postscaler (which (cid:127) Interrupt on TMR2 match of PR2 gives a 1:1 to 1:16 scaling inclusive) to generate a (cid:127) SSP module optional use of TMR2 output to gen- TMR2 interrupt (latched in flag bit TMR2IF, PIR regis- erate clock shift ters). Register12-1 shows the Timer2 Control register. The prescaler and postscaler counters are cleared Timer2 can be shut off by clearing control bit TMR2ON when any of the following occurs: (T2CON register) to minimize power consumption. (cid:127) A write to the TMR2 register Figure12-1 is a simplified block diagram of the Timer2 (cid:127) A write to the T2CON register module. The prescaler and postscaler selection of (cid:127) Any device RESET (Power-on Reset, MCLR Timer2 are controlled by this register. Reset, Watchdog Timer Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. Note: Timer2 is disabled on POR. REGISTER 12-1: T2CON REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale (cid:127) (cid:127) (cid:127) 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 121

PIC18CXX8 12.2 Timer2 Interrupt 12.3 Output of TMR2 The Timer2 module has an 8-bit period register PR2. The output of TMR2 (before the postscaler) is a clock Timer2 increments from 00h until it matches PR2 and input to the Synchronous Serial Port module, which then resets to 00h on the next increment cycle. PR2 is optionally uses it to generate the shift clock. a readable and writable register. The PR2 register is initialized to FFh upon RESET. FIGURE 12-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 Output(1) bit TMR2IF Prescaler RESET FOSC/4 TMR2 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T2CKPS1:T2CKPS0 PR2 4 TOUTPS3:TOUTPS0 Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on Value on all other Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TMR2 Timer2 module’s register 0000 0000 0000 0000 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ’0’. Shaded cells are not used by the Timer2 module. DS30475A-page 122 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 13.0 TIMER3 MODULE Figure13-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following features: Register13-1 shows the Timer3 Control Register. This register controls the operating mode of the Timer3 (cid:127) 16-bit timer/counter module and sets the CCP clock source. (Two 8-bit registers: TMR3H and TMR3L) Register11-1 shows the Timer1 Control register. This (cid:127) Readable and writable (both registers) register controls the operating mode of the Timer1 (cid:127) Internal or external clock select module, as well as contains the Timer1 oscillator (cid:127) Interrupt on overflow from FFFFh to 0000h enable bit (T1OSCEN), which can be a clock source for (cid:127) RESET from CCP module trigger Timer3. Note: Timer3 is disabled on POR. REGISTER 13-1: T3CON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable 1 = Enables register Read/Write of Timer3 in one 16-bit operation 0 = Enables register Read/Write of Timer3 in two 8-bit operations bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 1x = Timer3 is the clock source for compare/capture CCP modules 01 = Timer3 is the clock source for compare/capture of CCP2, Timer1 is the clock source for compare/capture of CCP1 00 = Timer1 is the clock source for compare/capture CCP modules bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge) 0 = Internal clock (Fosc/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 123

PIC18CXX8 13.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruc- tion cycle. When TMR3CS = 1, Timer3 increments on Timer3 can operate in one of these modes: every rising edge of the Timer1 external clock input or (cid:127) As a timer the Timer1 oscillator, if enabled. (cid:127) As a synchronous counter When the Timer1 oscillator is enabled (T1OSCEN is (cid:127) As an asynchronous counter set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is The operating mode is determined by the clock select ignored. bit, TMR3CS (T3CON register). Timer3 also has an internal “RESET input”. This RESET can be generated by the CCP module (Section13.0). FIGURE 13-1: TIMER3 BLOCK DIAGRAM CCP Special Trigger TMR3IF Overflow T3CCPx Synchronized 0 Interrupt Clock Input Flag bit CLR TMR3H TMR3L 1 TMR3ON on/off T3SYNC T1OSC T1OSO/ 1 Synchronize T13CKI Prescaler T1OSCEN Fosc/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 TMR3CS SLEEP Input T3CKPS1:T3CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 13-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR3H 8 8 Write TMR3L Read TMR3L CCP Special Trigger TMR3IF Overflow 8 TMR3 T3CCPx 0 Synchronized Interrupt Flag CLR Clock Input bit TMR3H TMR3L 1 To Timer1 Clock Input TMR3ON On/Off T3SYNC T1OSC T1OSO/ 1 T13CKI Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 SLEEP Input T3CKPS1:T3CKPS0 TMR3CS Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS30475A-page 124 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 13.2 Timer1 Oscillator 13.4 Resetting Timer3 Using a CCP Trigger Output The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting If the CCP module is configured in Compare mode to the T1OSCEN bit (T1CON Register). The oscillator is generate a “special event trigger" (CCP1M3:CCP1M0 a low power oscillator rated up to 200 kHz. Refer to = 1011), this signal will reset Timer3. “Timer1 Module”, Section11.0 for Timer1 oscillator Note: The special event triggers from the CCP details. module will not set interrupt flag bit 13.3 Timer3 Interrupt TMR3IF (PIR registers). Timer3 must be configured for either timer or Synchro- The TMR3 Register pair (TMR3H:TMR3L) increments nized Counter mode to take advantage of this feature. If from 0000h to FFFFh and rolls over to 0000h. The Timer3 is running in Asynchronous Counter mode, this TMR3 Interrupt, if enabled, is generated on overflow RESET operation may not work. In the event that a write which is latched in interrupt flag bit TMR3IF (PIR Reg- to Timer3 coincides with a special event trigger from isters). This interrupt can be enabled/disabled by set- CCP1, the write will take precedence. In this mode of ting/clearing TMR3 interrupt enable bit TMR3IE (PIE operation, the CCPR1H:CCPR1L registers pair Registers). becomes the period register for Timer3. Refer to “Capture/Compare/PWM (CCP) Modules”, Section14.0 for CCP details. TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000 PIE2 — CMIE — — BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000 IPR2 — CMIP — — BCLIP LVDIP TMR3IP CCP2IP -0-- 0000 -0-- 0000 TMR3L Holding register for the Least Significant Byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu TMR3H Holding register for the Most Significant Byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 125

PIC18CXX8 NOTES: DS30475A-page 126 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 14.0 CAPTURE/COMPARE/PWM Section17.0 for CAN operation.) Therefore, operation (CCP) MODULES of a CCP module in the following sections is described with respect to CCP1. Each CCP (Capture/Compare/PWM) module contains Table14-2 shows the interaction of the CCP modules. a 16-bit register that can operate as a 16-bit capture register, as a 16-bit compare register, or as a PWM Register14-1 shows the CCPx Control registers Duty Cycle register. Table14-1 shows the timer (CCPxCON). For the CCP1 module, the register is resources of the CCP module modes. called CCP1CON and for the CCP2 module, the regis- ter is called CCP2CON. The operation of CCP1 is identical to that of CCP2, with the exception of the special event trigger and the CAN message timestamp received. (Refer to “CAN Module”, REGISTER 14-1: CCP1CON REGISTER CCP2CON REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0 Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Capture mode, CAN message received (CCP1 only) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set) 1001 = Compare mode, Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set) 1010 = Compare mode, Generate software interrupt on compare match (CCPIF bit is set, CCP pin is unaffected) 1011 = Compare mode, Trigger special event (CCPIF bit is set, reset TMR1 or TMR3) 11xx = PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 127

PIC18CXX8 14.1 CCP1 Module 14.3 Capture Mode Capture/Compare/PWM Register1 (CCPR1) is com- In Capture mode, CCPR1H:CCPR1L captures the prised of two 8-bit registers: CCPR1L (low byte) and 16-bit value of the TMR1 or TMR3 registers when an CCPR1H (high byte). The CCP1CON register controls event occurs on pin RC2/CCP1. An event is defined as: the operation of CCP1. All are readable and writable. (cid:127) every falling edge 14.2 CCP2 Module (cid:127) every rising edge (cid:127) every 4th rising edge Capture/Compare/PWM Register2 (CCPR2) is com- (cid:127) every 16th rising edge prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls An event is selected by control bits CCP1M3:CCP1M0 the operation of CCP2. All are readable and writable. (CCP1CON<3:0>). When a capture is made, the inter- rupt request flag bit CCP1IF (PIR registers) is set. It TABLE 14-1: CCP MODE - TIMER must be cleared in software. If another capture occurs RESOURCE before the value in register CCPR1 is read, the old cap- tured value will be lost. CCP Mode Timer Resource 14.3.1 CCP PIN CONFIGURATION Capture Timer1 or Timer3 Compare Timer1 or Timer3 In Capture mode, the RC2/CCP1 pin should be config- PWM Timer2 ured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 is configured as an out- put, a write to the port can cause a capture condition. 14.3.2 TIMER1/TIMER3 MODE SELECTION The timers used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Syn- chronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer used with each CCP module is selected in the T3CON register. TABLE 14-2: INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture TMR1 or TMR3 time-base. Time-base can be different for each CCP. Capture Compare The compare could be configured for the special event trigger, which clears either TMR1 or TMR3, depending upon which time-base is used. Compare Compare The compare(s) could be configured for the special event trigger, which clears TMR1 or TMR3 depending upon which time-base is used. PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt). PWM Capture None PWM Compare None DS30475A-page 128 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 14.3.3 SOFTWARE INTERRUPT 14.3.5 CAN MESSAGE RECEIVED When the Capture mode is changed, a false capture The CAN capture event occurs when a message is interrupt may be generated. The user should keep bit received in either receive buffer. The CAN module pro- CCP1IE (PIE registers) clear to avoid false interrupts vides a rising edge to the CCP module to cause a cap- and should clear the flag bit CCP1IF, following any ture event. This feature is provided to time-stamp the such change in operating mode. received CAN messages. 14.3.4 CCP PRESCALER EXAMPLE 14-1: CHANGING BETWEEN CAPTURE PRESCALERS There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is CLRF CCP1CON, F ; Turn CCP module off turned off, or the CCP module is not in Capture mode, MOVLW NEW_CAPT_PS ; Load WREG with the the prescaler counter is cleared. This means that any ; new prescaler mode ; value and CCP ON RESET will clear the prescaler counter. MOVWF CCP1CON ; Load CCP1CON with Switching from one capture prescaler to another may ; this value generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example14-1 shows the recom- mended method for switching between capture pres- calers. This example also clears the prescaler counter and will not generate the “false” interrupt. FIGURE 14-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L CCP1 Pin Set Flag bit CCP1IF T3CCP2 TMR3 Prescaler ÷ 1, 4, 16 Enable RXB0IF or CCPR1H CCPR1L RXB1IF CCP1CON<3:0> and T3CCP2 TEMnaRb1le edge detect TMR1H TMR1L CCP1M3:CCP1M0 Q’s Set Flag bit CCP2IF T3CCP1 TMR3H TMR3L T3CCP2 TMR3 Prescaler ÷ 1, 4, 16 Enable CCP2 Pin CCPR2H CCPR2L TMR1 and Enable edge detect T3CCP2 T3CCP1 TMR1H TMR1L CCP2M3:CCP2M0 Q’s Note: I/O pins have diode protection to VDD and VSS.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 129

PIC18CXX8 14.4 Compare Mode 14.4.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 (CCPR2) register Timer1 and/or Timer3 must be running in Timer mode value is constantly compared against either the TMR1 or Synchronized Counter mode, if the CCP module is register pair value, or the TMR3 register pair value. using the compare feature. In Asynchronous Counter When a match occurs, the RC2/CCP1 (RC1/CCP2) pin mode, the compare operation may not work. can have one of the following actions: 14.4.3 SOFTWARE INTERRUPT MODE (cid:127) Driven high (cid:127) Driven low When Generate Software Interrupt is chosen, the CCP1 pin is not affected. Only a CCP Interrupt is gen- (cid:127) Toggle output (high to low or low to high) erated (if enabled). (cid:127) Remains unchanged The action on the pin is based on the value of control 14.4.4 SPECIAL EVENT TRIGGER bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the In this mode, an internal hardware trigger is generated, same time, interrupt flag bit CCP1IF (CCP2IF) is set. which may be used to initiate an action. 14.4.1 CCP PIN CONFIGURATION The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to The user must configure the CCPx pin as an output by effectively be a 16-bit programmable period register for clearing the appropriate TRISC bit. Timer1. Note: Clearing the CCP1CON register will force The special trigger output of CCPx resets either the the RC2/CCP1 compare output latch to the TMR1 or TMR3 register pair. Additionally, the CCP2 default low level. This is not the data latch. Special Event Trigger will start an A/D conversion if the A/D module is enabled. Note: The special event trigger from the CCP2 module will not set the Timer1 or Timer3 interrupt flag bits. FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit) Set bit GO/DONE, which starts an A/D conversion (CCP2 only) Special Event Trigger Set Flag bit CCP1IF CCPR1H CCPR1L Q S Output RC2/CCP1 R Logic match Comparator Pin TRISC<2> Output Enable CCP1M3:CCP1M0 T3CCP2 0 1 Mode Select TMR1H TMR1L TMR3H TMR3L Special Event Trigger Set Flag bit CCP2IF T3CCP1 T3CCP2 0 1 Q S Output Comparator RC1/CCP2 R Logic Match Pin TRISC<1> CCPR2H CCPR2L Output Enable CCP2M3:CCP2M0 Mode Select Note: I/O pins have diode protection to VDD and VSS. DS30475A-page 130 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000 PIE2 — CMIE — — BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000 IPR2 — CMIP — — BCLIP LVDIP TMR3IP CCP2IP -0-- 0000 -0-- 0000 TMR3L Holding register for the Least Significant Byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu TMR3H Holding register for the Most Significant Byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 131

PIC18CXX8 14.5 PWM Mode 14.5.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCP1 pin The PWM period is specified by writing to the PR2 reg- produces up to a 10-bit resolution PWM output. Since ister. The PWM period can be calculated using the fol- the CCP1 pin is multiplexed with the PORTC data latch, lowing formula: the TRISC<2> bit must be cleared to make the CCP1 PWM period = [(PR2) + 1] • 4 (cid:127) TOSC (cid:127) pin an output. (TMR2 prescale value) Note: Clearing the CCP1CON register will force PWM frequency is defined as 1 / [PWM period]. the CCP1 PWM output latch to the default When TMR2 is equal to PR2, the following three events low level. This is not the PORTC I/O data occur on the next increment cycle: latch. (cid:127) TMR2 is cleared Figure14-3 shows a simplified block diagram of the (cid:127) The CCP1 pin is set (exception: if PWM duty CCP module in PWM mode. cycle=0%, the CCP1 pin will not be set) For a step-by-step procedure on how to set up the CCP (cid:127) The PWM duty cycle is latched from CCPR1L into module for PWM operation, see Section14.5.3. CCPR1H FIGURE 14-3: SIMPLIFIED PWM BLOCK Note: The Timer2 postscaler (see Section12.0) is not used in the determination of the DIAGRAM PWM frequency. The postscaler could be used to have a servo update rate at a dif- CCP1CON<5:4> Duty Cycle Registers ferent frequency than the PWM output. CCPR1L (Master) 14.5.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up CCPR1H (Slave) to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the Comparator R Q two LSbs. This 10-bit value is represented by RC2/CCP1 CCPR1L:CCP1CON<5:4>. The following equation is TMR2 (Note 1) used to calculate the PWM duty cycle in time: S PWM duty cycle = (CCPR1L:CCP1CON<5:4>) (cid:127) Comparator TRISC<2> TOSC (cid:127) (TMR2 prescale value) Clear Timer, CCPR1L and CCP1CON<5:4> can be written to at any CCP1 pin and latch D.C. time, but the duty cycle value is not latched into PR2 CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, Note 1: 8-bit timer is concatenated with 2-bit internal Q CCPR1H is a read-only register. clock, or 2 bits of the prescaler, to create 10-bit time-base. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double A PWM output (Figure14-4) has a time-base (period) buffering is essential for glitchless PWM operation. and a time that the output stays high (duty cycle). The When the CCPR1H and 2-bit latch match TMR2, con- frequency of the PWM is the inverse of the period catenated with an internal 2-bit Q clock or 2 bits of the (1/period). TMR2 prescaler, the CCP1 pin is cleared. FIGURE 14-4: PWM OUTPUT Maximum PWM resolution (bits) for a given PWM frequency: Period FOSC log--------------- FPWM = -----------------------------bits log(2) Duty Cycle TMR2 = PR2 Note: If the PWM duty cycle value is longer than TMR2 = Duty Cycle the PWM period, the CCP1 pin will not be cleared. TMR2 = PR2 DS30475A-page 132 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 14.5.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 register. 2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. 4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. 5. Configure the CCP1 module for PWM operation. TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.76 kHz 39.06 kHz 156.3 kHz 312.5 kHz 416.6 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 5.5 TABLE 14-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TMR2 Timer2 module’s register 0000 0000 0000 0000 PR2 Timer2 module’s period register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000 PIE2 — CMIE — — BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000 IPR2 — CMIP — — BCLIP LVDIP TMR3IP CCP2IP -0-- 0000 -0-- 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 133

PIC18CXX8 NOTES: DS30475A-page 134 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 15.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc. The MSSP module can operate in one of two modes: (cid:127) Serial Peripheral InterfaceTM (SPI) (cid:127) Inter-Integrated Circuit (I2C) - Full Master mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: (cid:127) Master mode (cid:127) Multi-master mode (cid:127) Slave mode  2000 Microchip Technology Inc. Advanced Information DS30475A-page 135

PIC18CXX8 15.2 Control Registers Register15-1 shows the MSSP Status Register (SSPSTAT), Register15-2 shows the MSSP Control The MSSP module has three associated registers. Register 1 (SSPCON1), and Register15-3 shows the These include a status register and two control registers. MSSP Control Register 2 (SSPCON2). REGISTER 15-1: SSPSTAT REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode SMP must be cleared when SPI is used in Slave mode In I 2 C Master or Slave mode: 1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0= Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: STOP bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET) 0 = STOP bit was not detected last bit 3 S: START bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a START bit has been detected last (this bit is ’0’ on RESET) 0 = START bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit, or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 =Transmit is in progress 0 =Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode. DS30475A-page 136 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 bit 1 UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I 2 C mode only) 1 = Data Transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data Transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 137

PIC18CXX8 REGISTER 15-2: SSPCON1 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. (Must be cleared in software.) 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in Transmit mode. (Must be cleared in software.) 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output. In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I 2 C Slave mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C Master mode Unused in this mode DS30475A-page 138 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 bit 3 - 0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1) ) 1001 = Reserved 1010 = Reserved 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 139

PIC18CXX8 REGISTER 15-3: SSPCON2 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (In I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (In I2C Master mode only) In Master Transmit mode: 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (In I2C Master mode only) In Master Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only) In Master Receive mode: 1 =Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 =Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (In I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: STOP Condition Enable bit (In I2C Master mode only) SCK release control 1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0 = STOP condition idle bit 1 RSEN: Repeated START Condition Enabled bit (In I2C Master mode only) 1 =Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware. 0 =Repeated START condition idle bit 0 SEN: START Condition Enabled bit (In I2C Master mode only) 1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = START condition idle Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 140 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.3 SPI Mode FIGURE 15-1: MSSP BLOCK DIAGRAM (SPIMODE) The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four Internal Data Bus modes of SPI are supported. To accomplish communi- cation, typically three pins are used: Read Write (cid:127) Serial Data Out (SDO) - RC5/SDO SSPBUF reg (cid:127) Serial Data In (SDI) - RC4/SDI/SDA (cid:127) Serial Clock (SCK) - RC3/SCK/SCL/LVOIN Additionally, a fourth pin may be used when in any Slave mode of operation: SSPSR reg (cid:127) Slave Select (SS) - RA5/SS/AN4 SDI bit0 Shift Clock 15.3.1 OPERATION SDO When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits SSPCON1<5:0> and SSPSTAT<7:6>. SS Control These control bits allow the following to be specified: Enable (cid:127) Master mode (SCK is the clock output) SS Edge (cid:127) Slave mode (SCK is the clock input) Select (cid:127) Clock polarity (Idle state of SCK) (cid:127) Data input sample phase (middle or end of data 2 Clock Select output time) (cid:127) Clock edge (output data on rising/falling edge of SSPM3:SSPM0 SCK) SMP:CKE (cid:127) Clock rate (Master mode only) 2 4 (T M R 2 2O u tp u t) (cid:127) Slave Select mode (Slave mode only) Edge Figure15-1 shows the block diagram of the MSSP Select Prescaler TOSC SCK 4, 16, 64 module, when in SPI mode. Data to TX/RX in SSPSR TRIS bit Note: I/O pins have diode protection to VDD and VSS. The MSSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then the buffer full detect bit, BF (SSPSTAT register), and the interrupt flag bit, SSPIF (PIR regis- ters), are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit, WCOL (SSPCON1 register), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 141

PIC18CXX8 When the application software is expecting to receive 15.3.2 ENABLING SPI I/O valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The To enable the serial port, SSP Enable bit, SSPEN buffer full (BF) bit (SSPSTAT register) indicates when (SSPCON1 register), must be set. To reset or reconfig- SSPBUF has been loaded with the received data ure SPI mode, clear the SSPEN bit, re-initialize the (transmission is complete). When the SSPBUF is read, SSPCON registers, and then set the SSPEN bit. This the BF bit is cleared. This data may be irrelevant if the configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port func- SPI is only a transmitter. Generally, the MSSP Interrupt tion, some must have their data direction bits (in the is used to determine when the transmission/reception TRIS register) appropriately programmed. That is: has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, (cid:127) SDI is automatically controlled by the SPI module then software polling can be done to ensure that a write (cid:127) SDO must have TRISC<5> bit cleared collision does not occur. Example15-1 shows the (cid:127) SCK (Master mode) must have TRISC<3> bit loading of the SSPBUF (SSPSR) for data transmission. cleared (cid:127) SCK (Slave mode) must have TRISC<3> bit set The SSPSR is not directly readable or writable, and can only be accessed by addressing the SSPBUF reg- (cid:127) SS must have TRISC<4> bit set ister. Additionally, the MSSP status register (SSPSTAT Any serial port function that is not desired may be over- register) indicates the various status conditions. ridden by programming the corresponding data direc- tion (TRIS) register to the opposite value. EXAMPLE 15-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)? GOTO LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS30475A-page 142 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.3.3 MASTER MODE shown in Figure15-2, Figure15-4, and Figure15-5, where the MSb is transmitted first. In Master mode, the The master can initiate the data transfer at any time SPI clock rate (bit rate) is user programmable to be one because it controls the SCK. The master determines of the following: when the slave is to broadcast data by the software protocol. (cid:127) FOSC/4 (or TCY) (cid:127) FOSC/16 (or 4 (cid:127) TCY) In Master mode, the data is transmitted/received as (cid:127) FOSC/64 (or 16 (cid:127) TCY) soon as the SSPBUF register is written to. If the SPI is (cid:127) Timer2 output/2 only going to receive, the SDO output could be dis- This allows a maximum data rate (at 40 MHz) of 10.00 abled (programmed as an input). The SSPSR register Mbps. will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is Figure15-2 shows the waveforms for Master mode. received, it will be loaded into the SSPBUF register as When the CKE bit is set, the SDO data is valid before a normal received byte (interrupts and status bits there is a clock edge on SCK. The change of the input appropriately set). This could be useful in receiver sample is shown based on the state of the SMP bit. The applications as a “line activity monitor” mode. time when the SSPBUF is loaded with the received data is shown. The clock polarity is selected by appropriately program- ming the CKP bit (SSPCON1 register). This, then, would give waveforms for SPI communication as FIGURE 15-2: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (CKE = 0) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (CKE = 1) SDI (SMP = 0) bit7 bit0 Input Sample (SMP = 0) SDI (SMP = 1) bit7 bit0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2↓ SSPBUF  2000 Microchip Technology Inc. Advanced Information DS30475A-page 143

PIC18CXX8 15.3.4 SLAVE MODE the SDO pin is no longer driven, even if in the mid- dle of a transmitted byte, and becomes a floating In Slave mode, the data is transmitted and received as output. External pull-up/pull-down resistors may be the external clock pulses appear on SCK. When the desirable, depending on the application. last bit is latched, the SSPIF interrupt flag bit is set. Note 1: When the SPI is in Slave mode with SS pin While in Slave mode, the external clock is supplied by control enabled, (SSPCON<3:0> = 0100) the external clock source on the SCK pin. This external the SPI module will reset if the SS pin is clock must meet the minimum high and low times, as set to VDD. specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE While in SLEEP mode, the slave can transmit/receive set, then the SS pin control must be data. When a byte is received, the device will wake-up enabled. from SLEEP. When the SPI module resets, the bit counter is forced 15.3.5 SLAVE SELECT SYNCHRONIZATION to 0. This can be done by either forcing the SS pin to a high level, or clearing the SSPEN bit. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control To emulate two-wire communication, the SDO pin can enabled (SSPCON1<3:0> = 04h). The pin must not be connected to the SDI pin. When the SPI needs to be driven low for the SS pin to function as an input. operate as a receiver, the SDO pin can be configured The Data Latch must be high. When the SS pin is as an input. This disables transmissions from the SDO. low, transmission and reception are enabled and The SDI can always be left as an input (SDI function), the SDO pin is driven. When the SS pin goes high, since it cannot create a bus conflict. FIGURE 15-3: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit7 bit6 bit7 bit0 SDI bit0 (SMP = 0) bit7 bit7 Input Sample (SMP = 0) SSPIF Next Q4 Cycle SSPSR to after Q2↓ SSPBUF DS30475A-page 144 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 15-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 Input Sample (SMP = 0) SSPIF Next Q4 Cycle SSPSR to after Q2↓ SSPBUF FIGURE 15-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Required SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 Input Sample (SMP = 0) SSPIF Next Q4 Cycle after Q2↓ SSPSR to SSPBUF  2000 Microchip Technology Inc. Advanced Information DS30475A-page 145

PIC18CXX8 15.3.6 SLEEP OPERATION 15.3.8 BUS MODE COMPATIBILITY In Master mode, all module clocks are halted, and the Table15-1 shows the compatibility between the stan- transmission/reception will remain in that state until the dard SPI modes and the states of the CKP and CKE device wakes from SLEEP. After the device returns to control bits. normal mode, the module will continue to trans- TABLE 15-1: SPI BUS MODES mit/receive data. In Slave mode, the SPI transmit/receive shift register Standard SPI Mode Control Bits State operates asynchronously to the device. This allows the Terminology CKP CKE device to be placed in SLEEP mode, and data to be 0, 0 0 1 shifted into the SPI transmit/receive shift register. When all eight bits have been received, the MSSP 0, 1 0 0 interrupt flag bit will be set and, if enabled, will wake the 1, 0 1 1 device from SLEEP. 1, 1 1 0 15.3.7 EFFECTS OF A RESET There is also a SMP bit that controls when the data will be sampled. A RESET disables the MSSP module and terminates the current transfer. TABLE 15-2: REGISTERS ASSOCIATED WITH SPI OPERATION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TRISC PORTC Data Direction Register 1111 1111 1111 1111 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 TRISA — PORTA Data Direction Register(1) --11 1111 --11 1111 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode. Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. DS30475A-page 146 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.4 MSSP I 2 C Operation The SSPCON1 register allows control of the I2C oper- ation. The SSPM3:SSPM0 mode selection bits The MSSP module in I2C mode, fully implements all (SSPCON1 register) allow one of the following I2C master and slave functions (including general call sup- modes to be selected: port) and provides interrupts on START and STOP bits (cid:127) I2C Master mode, clock = OSC/4 (SSPADD +1) in hardware to determine a free bus (Multi-master (cid:127) I2C Slave mode (7-bit address) mode). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit (cid:127) I2C Slave mode (10-bit address) addressing. (cid:127) I2C Slave mode (7-bit address), with START and STOP bit interrupts enabled Two pins are used for data transfer. These are the RC3/SCK/SCL pin, which is the clock (SCL), and the (cid:127) I2C Slave mode (10-bit address), with START and RC4/SDI/SDA pin, which is the data (SDA). The user STOP bit interrupts enabled must configure these pins as inputs or outputs through (cid:127) I2C Firmware controlled master operation, slave the TRISC<4:3> bits. is idle The MSSP module functions are enabled by setting Selection of any I2C mode with the SSPEN bit set, MSSP Enable bit SSPEN (SSPCON1 register). forces the SCL and SDA pins to be open drain, pro- vided these pins are programmed to inputs by setting FIGURE 15-6: MSSP BLOCK DIAGRAM the appropriate TRISC bits. (I2C MODE) 15.4.1 SLAVE MODE In Slave mode, the SCL and SDA pins must be config- Internal ured as inputs (TRISC<4:3> set). The MSSP module Data Bus will override the input state with the output data when Read Write required (slave-transmitter). When an address is matched, or the data transfer after SSPBUF reg RC3/SCK/SCL an address match is received, the hardware automati- cally will generate the acknowledge (ACK) pulse and Shift Clock load the SSPBUF register with the received value cur- rently in the SSPSR register. SSPSR reg If either or both of the following conditions are true, the RC4/ MSb LSb SDI/ MSSP module will not give this ACK pulse: SDA a) The buffer full bit BF (SSPCON1 register) was Match Detect Addr Match set before the transfer was received. b) The overflow bit SSPOV (SSPCON1 register) SSPADD reg was set before the transfer was received. In this event, the SSPSR register value is not loaded START and Set, RESET into the SSPBUF, but bit SSPIF (PIR registers) is set. STOP bit detect S, P bits (SSPSTAT reg) The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. Note: I/O pins have diode protection to VDD and VSS. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the The MSSP module has these six registers for I2C oper- I2C specification, as well as the requirement of the ation: MSSP module, is shown in timing parameter #100 and parameter #101. (cid:127) MSSP Control Register1 (SSPCON1) (cid:127) MSSP Control Register2 (SSPCON2) (cid:127) MSSP Status Register (SSPSTAT) (cid:127) Serial Receive/Transmit Buffer (SSPBUF) (cid:127) MSSP Shift Register (SSPSR) - Not directly accessible (cid:127) MSSP Address Register (SSPADD)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 147

PIC18CXX8 15.4.1.1 Addressing The sequence of events for 10-bit addressing is as fol- lows, with steps 7- 9 for slave-transmitter: Once the MSSP module has been enabled, it waits for 1. Receive first (high) byte of address (the SSPIF, a START condition to occur. Following the START con- BF and UA bits (SSPSTAT register) are set). dition, the eight bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the 2. Update the SSPADD register with second (low) clock (SCL) line. The value of register SSPSR<7:1> is byte of address (clears bit UA and releases the compared to the value of the SSPADD register. The SCL line). address is compared on the falling edge of the eighth 3. Read the SSPBUF register (clears bit BF) and clock (SCL) pulse. If the addresses match, and the BF clear flag bit SSPIF. and SSPOV bits are clear, the following events occur: 4. Receive second (low) byte of address (bits a) The SSPSR register value is loaded into the SSPIF, BF, and UA are set). SSPBUF register. 5. Update the SSPADD register with the first (high) b) The buffer full bit BF is set. byte of address. If match releases SCL line, this will clear bit UA. c) An ACK pulse is generated. 6. Read the SSPBUF register (clears bit BF) and d) MSSP interrupt flag bit SSPIF (PIR registers) is clear flag bit SSPIF. set on the falling edge of the ninth SCL pulse (interrupt is generated, if enabled). 7. Receive repeated START condition. 8. Receive first (high) byte of address (bits SSPIF In 10-bit address mode, two address bytes need to be and BF are set). received by the slave. The five Most Significant bits (MSb) of the first address byte specify if this is a 10-bit 9. Read the SSPBUF register (clears bit BF) and address. The R/W bit (SSPSTAT register) must specify clear flag bit SSPIF. a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSb’s of the address. DS30475A-page 148 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.4.1.2 Reception ter. Then pin RC3/SCK/SCL should be enabled by set- ting bit CKP (SSPCON1 register). The master must When the R/W bit of the address byte is clear and an monitor the SCL pin prior to asserting another clock address match occurs, the R/W bit of the SSPSTAT pulse. The slave devices may be holding off the master register is cleared. The received address is loaded into by stretching the clock. The eight data bits are shifted the SSPBUF register. out on the falling edge of the SCL input. This ensures When the address byte overflow condition exists, then that the SDA signal is valid during the SCL high time no acknowledge (ACK) pulse is given. An overflow con- (Figure15-8). dition is defined as either bit BF (SSPSTAT register) is An MSSP interrupt is generated for each data transfer set or bit SSPOV (SSPCON1 register) is set. byte. The SSPIF bit must be cleared in software and An MSSP interrupt is generated for each data transfer the SSPSTAT register is used to determine the status byte. Flag bit SSPIF (PIR registers) must be cleared in of the byte. The SSPIF bit is set on the falling edge of software. The SSPSTAT register is used to determine the ninth clock pulse. the status of the byte. As a slave-transmitter, the ACK pulse from the master-receiver is latched on the rising edge of the 15.4.1.3 Transmission ninth SCL input pulse. If the SDA line is high (not ACK), When the R/W bit of the incoming address byte is set then the data transfer is complete. When the ACK is and an address match occurs, the R/W bit of the latched by the slave, the slave logic is reset (resets SSPSTAT register is set. The received address is SSPSTAT register) and the slave monitors for another loaded into the SSPBUF register. The ACK pulse will occurrence of the START bit. If the SDA line was low be sent on the ninth bit and pin RC3/SCK/SCL is held (ACK), the transmit data must be loaded into the SSP- low. The transmit data must be loaded into the BUF register, which also loads the SSPSR register. Pin SSPBUF register, which also loads the SSPSR regis- RC3/SCK/SCL should be enabled by setting bit CKP. FIGURE 15-7: I2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address R/W=0 Receiving Data ACK Receiving Data Not ACK ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF Bus Master Terminates Transfer BF Cleared in software SSPBUF register is read SSPOV Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. FIGURE 15-8: I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) R/W = 0 Receiving Address R/W = 1 Transmitting Data Not ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Data in SCL held low Sampled while CPU responds to SSPIF SSPIF BF Cleared in software From SSP interrupt SSPBUF is written in software service routine CKP Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 149

PIC18CXX8 15.4.2 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF bit is set (eighth bit), The addressing procedure for the I2C bus is such that and on the falling edge of the ninth bit (ACK bit), the the first byte after the START condition usually deter- SSPIF interrupt flag bit is set. mines which device will be the slave addressed by the When the interrupt is serviced, the source for the inter- master. The exception is the general call address, rupt can be checked by reading the contents of the which can address all devices. When this address is SSPBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device specific or a general call address. acknowledge. In 10-bit mode, the SSPADD is required to be updated The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It for the second half of the address to match, and the UA bit is set (SSPSTAT register). If the general call address consists of all 0’s with R/W = 0. is sampled when the GCEN bit is set, and while the The general call address is recognized (enabled) when slave is configured in 10-bit address mode; then, the the General Call Enable (GCEN) bit is set (SSPCON2 second half of the address is not necessary. The UA bit register). Following a START bit detect, eight bits are will not be set, and the slave will begin receiving data shifted into the SSPSR and the address is compared after the Acknowledge (Figure15-9). against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 15-9: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF Cleared in software SSPBUF is read SSPOV ’0’ GCEN ’1’ DS30475A-page 150 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.4.3 MASTER MODE 15.4.4 I2C MASTER MODE SUPPORT Master mode of operation is supported by interrupt Master mode is enabled by setting and clearing the generation on the detection of the START and STOP appropriate SSPM bits in SSPCON1 and by setting the conditions. The STOP (P) and START (S) bits are SSPEN bit. Once Master mode is enabled, the user cleared from a RESET, or when the MSSP module is has the following six options: disabled. Control of the I2C bus may be taken when the 1. Assert a START condition on SDA and SCL. P bit is set, or the bus is idle, with both the S and P bits 2. Assert a Repeated START condition on SDA clear. and SCL. In Master mode, the SCL and SDA lines are manipu- 3. Write to the SSPBUF register initiating transmis- lated by the MSSP hardware. sion of data/address. The following events will cause SSP Interrupt Flag bit, 4. Generate a STOP condition on SDA and SCL. SSPIF, to be set (SSP Interrupt if enabled): 5. Configure the I2C port to receive data. (cid:127) START condition 6. Generate an Acknowledge condition at the end (cid:127) STOP condition of a received byte of data. (cid:127) Data transfer byte transmitted/received (cid:127) Acknowledge Transmit (cid:127) Repeated START condition Note: The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a START condition and immediately write the SSPBUF register to imitate transmission before the START condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. 2 FIGURE 15-10:MSSP BLOCK DIAGRAM (I C MASTER MODE) Internal SSPM3:SSPM0 Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock ect SSPSR Dete) MSb LSb OL urc able WCk so SCL Receive En STAARcGTk enbnoitew, rlSaeTtdeOgeP bit, Clock Cntl ck arbitrate/hold off cloc o( Cl START bit Detect STOP bit Detect SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT) Clock Arbitration Set SSPIF, BCLIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) End of XMIT/RCV Note: I/O pins have diode protection to VDD and VSS.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 151

PIC18CXX8 15.4.4.1 I2C Master Mode Operation A typical transmit sequence would go as follows: a) The user generates a START condition by set- The master device generates all of the serial clock ting the START Enable (SEN) bit (SSPCON2 pulses and the START and STOP conditions. A trans- register). fer is ended with a STOP condition or with a Repeated START condition. Since the Repeated START condi- b) SSPIF is set. The MSSP module will wait the tion is also the beginning of the next serial transfer, the required start time before any other operation I2C bus will not be released. takes place. c) The user loads the SSPBUF with the address to In Master Transmitter mode, serial data is output transmit. through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the d) Address is shifted out the SDA pin until all eight receiving device (7 bits) and the Read/Write (R/W) bit. bits are transmitted. In this case, the R/W bit will be logic ’0’. Serial data is e) The MSSP module shifts in the ACK bit from the transmitted eight bits at a time. After each byte is trans- slave device and writes its value into the mitted, an Acknowledge bit is received. START and ACKSTAT bit (SSPCON2 register). STOP conditions are output to indicate the beginning f) The MSSP module generates an interrupt at the and the end of a serial transfer. end of the ninth clock cycle by setting the SSPIF In Master Receive mode, the first byte transmitted con- bit. tains the slave address of the transmitting device g) The user loads the SSPBUF with eight bits of (7bits) and the R/W bit. In this case, the R/W bit will be data. logic ’1’. Thus, the first byte transmitted is a 7-bit slave h) Data is shifted out the SDA pin until all eight bits address followed by a ’1’ to indicate receive bit. Serial are transmitted. data is received via SDA, while SCL outputs the serial i) The MSSP module shifts in the ACK bit from the clock. Serial data is received eight bits at a time. After slave device and writes its value into the each byte is received, an Acknowledge bit is transmit- ACKSTAT bit (SSPCON2 register). ted. START and STOP conditions indicate the begin- j) The MSSP module generates an interrupt at the ning and end of transmission. end of the ninth clock cycle by setting the SSPIF The baud rate generator used for the SPI mode opera- bit. tion is now used to set the SCL clock frequency for k) The user generates a STOP condition by setting either 100 kHz, 400 kHz, or 1 MHz I2C operation. The the STOP Enable bit PEN (SSPCON2 register). baud rate generator reload value is contained in the l) Interrupt is generated once the STOP condition lower 7 bits of the SSPADD register. The baud rate is complete. generator will automatically begin counting on a write to the SSPBUF. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. DS30475A-page 152 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.4.5 BAUD RATE GENERATOR remented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is In I2C Master mode, the reload value for the BRG is reloaded automatically. If Clock Arbitration is taking located in the lower 7 bits of the SSPADD register place, for instance, the BRG will be reloaded when the (Figure15-11). When the BRG is loaded with this SCL pin is sampled high (Figure15-12). value, the BRG counts down to 0 and stops until another reload has taken place. The BRG count is dec- FIGURE 15-11: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 Reload Reload SCL Control CLKOUT BRG Down Counter Fosc/4 FIGURE 15-12:BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL de-asserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h value SCL is sampled high, reload takes place and BRG starts its count. BRG reload  2000 Microchip Technology Inc. Advanced Information DS30475A-page 153

PIC18CXX8 15.4.6 I2C MASTER MODE START CONDITION 15.4.6.1 WCOL Status Flag TIMING If the user writes the SSPBUF when a START To initiate a START condition, the user sets the START sequence is in progress, the WCOL is set and the con- Condition Enable (SEN) bit (SSPCON2 register). If the tents of the buffer are unchanged (the write doesn’t SDA and SCL pins are sampled high, the baud rate occur). generator is re-loaded with the contents of Note: Because queueing of events is not SSPADD<6:0> and starts its count. If SCL and SDA are allowed, writing to the lower 5 bits of both sampled high when the baud rate generator times SSPCON2 is disabled until the START out (TBRG), the SDA pin is driven low. The action of the condition is complete. SDA being driven low, while SCL is high, is the START condition, and causes the S bit (SSPSTAT register) to be set. Following this, the baud rate generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the baud rate generator times out (TBRG), the SEN bit (SSPCON2 register) will be automatically cleared by hardware, the baud rate gen- erator is suspended leaving the SDA line held low and the START condition is complete. Note: If at the beginning of the START condition, the SDA and SCL pins are already sam- pled low, or if during the START condition the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag BCLIF is set, the START condition is aborted, and the I2C module is reset into its IDLE state. FIGURE 15-13:FIRST START BIT TIMING Set S bit (SSPSTAT) Write to SEN bit occurs here SDA = 1, At completion of START bit, SCL = 1 Hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st Bit 2nd Bit SDA TBRG SCL TBRG S DS30475A-page 154 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.4.7 I2C MASTER MODE REPEATED START Immediately following the SSPIF bit getting set, the CONDITION TIMING user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. A Repeated START condition occurs when the RSEN After the first eight bits are transmitted and an ACK is bit (SSPCON2 register) is programmed high and the received, the user may then transmit an additional I2C logic module is in the IDLE state. When the RSEN eight bits of address (10-bit mode) or eight bits of data bit is set, the SCL pin is asserted low. When the SCL (7-bit mode). pin is sampled low, the baud rate generator is loaded with the contents of SSPADD<5:0> and begins count- 15.4.7.1 WCOL Status Flag ing. The SDA pin is released (brought high) for one baud rate generator count (TBRG). When the baud rate If the user writes the SSPBUF when a Repeated generator times out, if SDA is sampled high, the SCL START sequence is in progress, the WCOL is set and pin will be de-asserted (brought high). When SCL is the contents of the buffer are unchanged (the write sampled high, the baud rate generator is re-loaded with doesn’t occur). the contents of SSPADD<6:0> and begins counting. Note: Because queueing of events is not SDA and SCL must be sampled high for one TBRG. allowed, writing of the lower 5 bits of This action is then followed by assertion of the SDA pin SSPCON2 is disabled until the Repeated (SDA = 0) for one TBRG, while SCL is high. Following START condition is complete. this, the RSEN bit (SSPCON2 register) will be automat- ically cleared and the baud rate generator will not be reloaded, leaving the SDA pin held low. As soon as a START condition is detected on the SDA and SCL pins, the S bit (SSPSTAT register) will be set. The SSPIF bit will not be set until the baud rate generator has timed-out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated START condition occurs if: (cid:127) SDA is sampled low when SCL goes from low to high. (cid:127) SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". FIGURE 15-14:REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 SDA = 1, occurs here. At completion of START bit, SDA = 1, SCL = 1 hardware clear RSEN bit SCL(no change) and set SSPIF TBRG TBRG TBRG 1st Bit SDA Falling edge of ninth clock Write to SSPBUF occurs here. End of Xmit TBRG SCL TBRG Sr = Repeated START  2000 Microchip Technology Inc. Advanced Information DS30475A-page 155

PIC18CXX8 15.4.8 I2C MASTER MODE TRANSMISSION 15.4.8.2 WCOL Status Flag Transmission of a data byte, a 7-bit address, or the If the user writes the SSPBUF when a transmit is other half of a 10-bit address, is accomplished by sim- already in progress (i.e., SSPSR is still shifting out a ply writing a value to the SSPBUF register. This action data byte), the WCOL is set and the contents of the will set the Buffer Full bit, BF, and allow the baud rate buffer are unchanged (the write doesn’t occur). generator to begin counting and start the next transmis- WCOL must be cleared in software. sion. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted 15.4.8.3 ACKSTAT Status Flag (see data hold time specification parameter 106). SCL is held low for one baud rate generator roll over count In Transmit mode, the ACKSTAT bit (SSPCON2 (TBRG). Data should be valid before SCL is released register) is cleared when the slave has sent an high (see data setup time specification parameter 107). acknowledge (ACK = 0), and is set when the slave When the SCL pin is released high, it is held that way does not acknowledge (ACK = 1). A slave sends an for TBRG. The data on the SDA pin must remain stable acknowledge when it has recognized its address for that duration and some hold time after the next fall- (including a general call), or when the slave has ing edge of SCL. After the eighth bit is shifted out (the properly received its data. falling edge of the eighth clock), the BF bit is cleared 15.4.9 I2C MASTER MODE RECEPTION and the master releases SDA, allowing the slave device being addressed to respond with an ACK bit Master mode reception is enabled by programming the during the ninth bit time if an address match occurs, or Receive Enable bit, RCEN (SSPCON2 register). if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the Note: The MSSP module must be in an IDLE ninth clock. If the master receives an acknowledge, the state before the RCEN bit is set, or the Acknowledge Status bit, ACKSTAT, is cleared. If not, RCEN bit will be disregarded. the bit is set. After the ninth clock, the SSPIF bit is set The baud rate generator begins counting, and on each and the master clock (baud rate generator) is sus- rollover, the state of the SCL pin changes (high to pended until the next data byte is loaded into the SSP- low/low to high) and data is shifted into the SSPSR. BUF, leaving SCL low and SDA unchanged After the falling edge of the eighth clock, the RCEN bit (Figure15-15). is automatically cleared, the contents of the SSPSR are After the write to the SSPBUF, each bit of address will loaded into the SSPBUF, the BF bit is set, the SSPIF be shifted out on the falling edge of SCL, until all seven flag bit is set and the baud rate generator is suspended address bits and the R/W bit, are completed. On the from counting, holding SCL low. The MSSP is now in falling edge of the eighth clock, the master will IDLE state, awaiting the next command. When the de-assert the SDA pin, allowing the slave to respond buffer is read by the CPU, the BF bit is automatically with an acknowledge. On the falling edge of the ninth cleared. The user can then send an Acknowledge bit at clock, the master will sample the SDA pin to see if the the end of reception, by setting the Acknowledge address was recognized by a slave. The status of the Sequence Enable bit ACKEN (SSPCON2 register). ACK bit is loaded into the ACKSTAT status bit 15.4.9.1 BF Status Flag (SSPCON2 register). Following the falling edge of the ninth clock transmission of the address, the SSPIF is In receive operation, the BF bit is set when an address set, the BF bit is cleared and the baud rate generator is or data byte is loaded into SSPBUF from SSPSR. It is turned off, until another write to the SSPBUF takes cleared when the SSPBUF register is read. place, holding SCL low and allowing SDA to float. 15.4.9.2 SSPOV Status Flag 15.4.8.1 BF Status Flag In receive operation, the SSPOV bit is set when eight In Transmit mode, the BF bit (SSPSTAT register) is set bits are received into the SSPSR and the BF bit is when the CPU writes to SSPBUF, and is cleared when already set from a previous reception. all eight bits are shifted out. 15.4.9.3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). DS30475A-page 156 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 15-15:I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A > slave, clear ACKSTAT bit SSPCON2<6 Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1D0 2345678 Cleared in software service routineFrom SSP interrupt SSPBUF is written in software From D7 1 w SPIF o S R/W = 0 ACK = 0 d R/W 89 SCL held lwhile CPUresponds to y hardware. n b A1 s a 7 ed PCON2<0> SEN = 1ondition begins SEN = 0 Transmit Address to Slave A7A6A5A4A3A2 SSPBUF written with 7-bit addresstart transmit 123456 Cleared in software SSPBUF written After START condition, SEN clear Sc ST e R WritSTA S F SDA SCL SSPI BF SEN PEN R/W  2000 Microchip Technology Inc. Advanced Information DS30475A-page 157

PIC18CXX8 FIGURE 15-16:I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN start acknowledge sequenceACK from Masterer configured as a receiverSDA = ACKDT = 1 SDA = ACKDT = 0 ogramming SSPCON2<3>, (RCEN = 1)PEN bit = 1RCEN = 1 startRCEN clearedRCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK Bus MasterACK is not sentterminatestransfer967898756512343124PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Mastby pr ACK from Slave R/W = 1A1ACK 798 Write to SSPCON2<0>(SEN = 1)Begin START Condition SEN = 0Write to SSPBUF occurs hereStart XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 361245SCLS SSPIF Cleared in softwareSDA = 0, SCL = 1while CPU responds to SSPIF BF SSPOV ACKEN DS30475A-page 158 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.4.10 ACKNOWLEDGE SEQUENCE TIMING 15.4.11 STOP CONDITION TIMING An acknowledge sequence is enabled by setting the A STOP bit is asserted on the SDA pin at the end of a Acknowledge Sequence Enable bit ACKEN receive/transmit by setting the Stop Sequence Enable (SSPCON2 register). When this bit is set, the SCL pin bit, PEN (SSPCON2 register). At the end of a is pulled low and the contents of the Acknowledge Data receive/transmit, the SCL line is held low after the fall- bit (ACKDT) is presented on the SDA pin. If the user ing edge of the ninth clock. When the PEN bit is set, the wishes to generate an acknowledge, then the ACKDT master will assert the SDA line low. When the SDA line bit should be cleared. If not, the user should set the is sampled low, the baud rate generator is reloaded and ACKDT bit before starting an acknowledge sequence. counts down to 0. When the baud rate generator times The baud rate generator then counts for one rollover out, the SCL pin will be brought high, and one TBRG period (TBRG) and the SCL pin is de-asserted (pulled (baud rate generator rollover count) later, the SDA pin high). When the SCL pin is sampled high (clock arbitra- will be de-asserted. When the SDA pin is sampled high tion), the baud rate generator counts for TBRG. The while SCL is high, the P bit (SSPSTAT register) is set. SCL pin is then pulled low. Following this, the ACKEN A TBRG later, the PEN bit is cleared and the SSPIF bit bit is automatically cleared, the baud rate generator is is set (Figure15-18). turned off and the MSSP module then goes into IDLE 15.4.11.1 WCOL Status Flag mode (Figure15-17). If the user writes the SSPBUF when a STOP sequence 15.4.10.1 WCOL Status Flag is in progress, then the WCOL bit is set and the con- If the user writes the SSPBUF when an acknowledge tents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the occur). contents of the buffer are unchanged (the write doesn’t occur). FIGURE 15-17:ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared Write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Set SSPIF at the end Cleared in Cleared in of receive software software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one baud rate generator period.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 159

PIC18CXX8 FIGURE 15-18:STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2 SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT) is set Set PEN Falling edge of PEN bit (SSPCON2) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to set up STOP condition. Note: TBRG = one baud rate generator period. DS30475A-page 160 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.4.12 CLOCK ARBITRATION 15.4.13 SLEEP OPERATION Clock arbitration occurs when the master, during any While in SLEEP mode, the I2C module can receive receive, transmit or Repeated START/STOP condition, addresses or data, and when an address match or de-asserts the SCL pin (SCL allowed to float high). complete byte transfer occurs, wake the processor When the SCL pin is allowed to float high, the baud rate from SLEEP (if the MSSP interrupt is enabled). generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is 15.4.14 EFFECT OF A RESET sampled high, the baud rate generator is reloaded with A RESET disables the MSSP module and terminates the contents of SSPADD<6:0> and begins counting. the current transfer. This ensures that the SCL high time will always be at least one BRG rollover count, in the event that the clock is held low by an external device (Figure15-19). FIGURE 15-19:CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE BRG overflow, Release SCL, If SCL = 1 Load BRG with SSPADD<6:0>, and start count BRG overflow occurs, to measure high time interval. Release SCL, Slave device holds SCL low. SCL = 1 BRG starts counting clock high interval. SCL SCL line sampled once every machine cycle (TOSC² 4). Hold off BRG until SCL is sampled high. SDA TBRG TBRG TBRG  2000 Microchip Technology Inc. Advanced Information DS30475A-page 161

PIC18CXX8 15.4.15 MULTI-MASTER MODE 15.4.16 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION In Multi-master mode, the interrupt generation on the detection of the START and STOP conditions allows Multi-master mode support is achieved by bus arbitra- the determination of when the bus is free. The STOP tion. When the master outputs address/data bits onto (P) and START (S) bits are cleared from a RESET, or the SDA pin, arbitration takes place when the master when the MSSP module is disabled. Control of the I2C outputs a '1' on SDA, by letting SDA float high and bus may be taken when the P bit (SSPSTAT register) is another master asserts a '0'. When the SCL pin floats set, or the bus is idle with both the S and P bits clear. high, data should be stable. If the expected data on When the bus is busy, enabling the SSP Interrupt will SDA is a '1' and the data sampled on the SDA pin = '0', generate the interrupt when the STOP condition then a bus collision has taken place. The master will set occurs. the Bus Collision Interrupt Flag (BCLIF) and reset the I2C port to its IDLE state. (Figure15-20). In Multi-master operation, the SDA line must be moni- tored for arbitration, to see if the signal level is the If a transmit was in progress when the bus collision expected output level. This check is performed in hard- occurred, the transmission is halted, the BF bit is ware, with the result placed in the BCLIF bit. cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When the user services Arbitration can be lost in the following states: the bus collision interrupt service routine, and if the I2C (cid:127) Address transfer bus is free, the user can resume communication by (cid:127) Data transfer asserting a START condition. (cid:127) A START condition If a START, Repeated START, STOP, or Acknowledge (cid:127) A Repeated START condition condition was in progress when the bus collision (cid:127) An Acknowledge condition occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user ser- vices the bus collision interrupt service routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. The master will continue to monitor the SDA and SCL pins. If a STOP condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the trans- mitter left off when the bus collision occurred. In Multi-master mode, the interrupt generation on the detection of START and STOP conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is idle and the S and P bits are cleared. FIGURE 15-20:BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE SDA line pulled low Sample SDA. While SCL is high Data changes by another source data doesn’t match what is driven while SCL = 0 by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF DS30475A-page 162 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.4.16.1 Bus Collision During a START Condition The START condition begins with the SDA and SCL pins de-asserted. When the SDA pin is sampled high, During a START condition, a bus collision occurs if: the baud rate generator is loaded from SSPADD<6:0> a) SDA or SCL are sampled low at the beginning of and counts down to 0. If the SCL pin is sampled low the START condition (Figure15-21). while SDA is high, a bus collision occurs, because it is b) SCL is sampled low before SDA is asserted low assumed that another master is attempting to drive a (Figure15-22). data ’1’ during the START condition. During a START condition, both the SDA and the SCL If the SDA pin is sampled low during this count, the pins are monitored. BRG is reset and the SDA line is asserted early (Figure15-23). If, however, a ’1’ is sampled on the SDA If: pin, the SDA pin is asserted low at the end of the BRG the SDA pin is already low count. The baud rate generator is then reloaded and or the SCL pin is already low, counts down to 0, and during this time, if the SCL pin is then: sampled as ’0’, a bus collision does not occur. At the the START condition is aborted, end of the BRG count, the SCL pin is asserted low. and the BCLIF flag is set, Note: The reason that bus collision is not a factor and the MSSP module is reset to its IDLE state during a START condition is that no two (Figure15-21). bus masters can assert a START condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address follow- ing the START condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated START or STOP conditions. FIGURE 15-21:BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. . Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable START SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1. SSP module reset into IDLE state. SEN SDA sampled low before START condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software. S SSPIF SSPIF and BCLIF are cleared in software.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 163

PIC18CXX8 FIGURE 15-22:BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA SCL Set SEN, enable START sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, Bus collision occurs, set BCLIF SEN SCL = 0 before BRG time-out, Bus collision occurs, set BCLIF BCLIF Interrupt cleared in software S ’0’ ’0’ SSPIF ’0’ ’0’ FIGURE 15-23:BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master Reset BRG and assert SDA SCL S SCL pulled low after BRG Time-out SEN Set SEN, enable START sequence if SDA = 1, SCL = 1 BCLIF ’0’ S SSPIF SDA = 0, SCL = 1 Interrupts cleared Set SSPIF in software DS30475A-page 164 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 15.4.16.2 Bus Collision During a Repeated START reloaded and begins counting. If SDA goes from high to Condition low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the During a Repeated START condition, a bus collision same time. occurs if: If SCL goes from high to low before the BRG times out a) A low level is sampled on SDA when SCL goes and SDA has not already been asserted, a bus collision from low level to high level. occurs. In this case, another master is attempting to b) SCL goes low before SDA is asserted low, indi- transmit a data ’1’ during the Repeated START condi- cating that another master is attempting to trans- tion (Figure15-25). mit a data ’1’. If at the end of the BRG time-out both SCL and SDA are When the user de-asserts SDA and the pin is allowed still high, the SDA pin is driven low and the BRG is to float high, the BRG is loaded with SSPADD<6:0> reloaded and begins counting. At the end of the count, and counts down to 0. The SCL pin is then de-asserted, regardless of the status of the SCL pin, the SCL pin is and when sampled high, the SDA pin is sampled. driven low and the Repeated START condition is If SDA is low, a bus collision has occurred (i.e, another complete. master is attempting to transmit a data ’0’, see Figure15-24). If SDA is sampled high, the BRG is FIGURE 15-24:BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software. S '0' SSPIF '0' FIGURE 15-25:BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA. BCLIF Set BCLIF, release SDA and SCL. Interrupt cleared in software. RSEN S ’0’ SSPIF  2000 Microchip Technology Inc. Advanced Information DS30475A-page 165

PIC18CXX8 15.4.16.3 Bus Collision During a STOP Condition The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to Bus collision occurs during a STOP condition if: float. When the pin is sampled high (clock arbitration), a) After the SDA pin has been de-asserted and the baud rate generator is loaded with SSPADD<6:0> allowed to float high, SDA is sampled low after and counts down to 0. After the BRG times out, SDA is the BRG has timed out. sampled. If SDA is sampled low, a bus collision has b) After the SCL pin is de-asserted, SCL is sam- occurred. This is due to another master attempting to pled low before SDA goes high. drive a data ’0’ (Figure15-26). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempt- ing to drive a data ’0’ (Figure15-27). FIGURE 15-26:BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ’0’ SSPIF ’0’ FIGURE 15-27: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ’0’ SSPIF ’0’ DS30475A-page 166 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 16.0 ADDRESSABLE UNIVERSAL The USART can be configured in the following modes: SYNCHRONOUS (cid:127) Asynchronous (full duplex) ASYNCHRONOUS RECEIVER (cid:127) Synchronous - Master (half duplex) TRANSMITTER (USART) (cid:127) Synchronous - Slave (half duplex) The SPEN (RCSTA register) and the TRISC<7> bits The Universal Synchronous Asynchronous Receiver have to be set, and the TRISC<6> bit must be Transmitter (USART) module is one of the two serial cleared, in order to configure pins RC6/TX/CK and I/O modules. (USART is also known as a Serial Com- RC7/RX/DT as the Universal Synchronous Asynchro- munications Interface or SCI). The USART can be con- nous Receiver Transmitter. figured as a full duplex asynchronous system that can communicate with peripheral devices, such as CRT ter- Register16-1 shows the Transmit Status and Control minals and personal computers, or it can be configured Register (TXSTA) and Register16-2 shows the as a half duplex synchronous system that can commu- Receive Status and Control Register (TXSTA). nicate with peripheral devices, such as A/D or D/A inte- grated circuits, Serial EEPROMs, etc. REGISTER 16-1: TXSTA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode Don’t care Synchronous mode 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as '0' bit 2 BRGH: High Baud Rate Select bit Asynchronous mode 1 = High speed 0 = Low speed Synchronous mode Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of transmit data. Can be Address/Data bit or a parity bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 167

PIC18CXX8 REGISTER 16-2: RCSTA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode Don’t care Synchronous mode - Master 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Unused in this mode bit 4 CREN: Continuous Receive Enable bit Asynchronous mode 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1) 1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit bit 2 FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of received data, can be Address/Data bit or a parity bit Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 168 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 16.1 USART Baud Rate Generator (BRG) It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is The BRG supports both the Asynchronous and Syn- because the FOSC/(16(X + 1)) equation can reduce the chronous modes of the USART. It is a dedicated 8-bit baud rate error in some cases. baud rate generator. The SPBRG register controls the Writing a new value to the SPBRG register causes the period of a free running 8-bit timer. In Asynchronous BRG timer to be reset (or cleared). This ensures the mode, bit BRGH (TXSTA register) also controls the BRG does not wait for a timer overflow before output- baud rate. In Synchronous mode, bit BRGH is ignored. ting the new baud rate. Table16-1 shows the formula for computation of the baud rate for different USART modes, which only apply 16.1.1 SAMPLING in Master mode (internal clock). The data on the RC7/RX/DT pin is sampled three times Given the desired baud rate and FOSC, the nearest by a majority detect circuit to determine if a high or a integer value for the SPBRG register can be calculated low level is present at the RX pin. using the formula in Table16-1. From this, the error in baud rate can be determined. Example16-1 shows the calculation of the baud rate error for the following conditions: FOSC = 16 MHz Desired Baud Rate = 9600 BRGH = 0 SYNC = 0 EXAMPLE 16-1: CALCULATING BAUD RATE ERROR Desired Baud Rate = FOSC / (64 (X + 1)) Solving for X: X = ( (FOSC / Desired Baud Rate) / 64 ) - 1 X = ((16000000 / 9600) / 64) - 1 X = [25.042] = 25 Calculated Baud Rate = 16000000 / (64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate = (9615 - 9600) / 9600 = 0.16% TABLE 16-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate = FOSC/(16(X+1)) 1 (Synchronous) Baud Rate = FOSC/(4(X+1)) NA Legend: X = value in SPBRG (0 to 255) TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 169

PIC18CXX8 TABLE 16-3: BAUD RATES FOR SYNCHRONOUS MODE BAUD FOSC = 40 MHz SPBRG 33 MHz SPBRG 25 MHz SPBRG 20 MHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - NA - - NA - - 19.2 NA - - NA - - NA - - NA - - 76.8 76.92 +0.16 129 77.10 +0.39 106 77.16 +0.47 80 76.92 +0.16 64 96 96.15 +0.16 103 95.93 -0.07 85 96.15 +0.16 64 96.15 +0.16 51 300 303.03 +1.01 32 294.64 -1.79 27 297.62 -0.79 20 294.12 -1.96 16 500 500 0 19 485.30 -2.94 16 480.77 -3.85 12 500 0 9 HIGH 10000 - 0 8250 - 0 6250 - 0 5000 - 0 LOW 39.06 - 255 32.23 - 255 24.41 - 255 19.53 - 255 BAUD FOSC = 16 MHz SPBRG 10 MHz SPBRG 7.15909 MHz SPBRG 5.0688 MHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - 9.62 +0.23 185 9.60 0 131 19.2 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 19.20 0 65 76.8 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 74.54 -2.94 16 96 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 97.48 +1.54 12 300 307.70 +2.56 12 312.50 +4.17 7 298.35 -0.57 5 316.80 +5.60 3 500 500 0 7 500 0 4 447.44 -10.51 3 422.40 -15.52 2 HIGH 4000 - 0 2500 - 0 1789.80 - 0 1267.20 - 0 LOW 15.63 - 255 9.77 - 255 6.99 - 255 4.95 - 255 BAUD FOSC = 4 MHz SPBRG 3.579545 MHz SPBRG 1 MHz SPBRG 32.768 kHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - 0.30 +1.14 26 1.2 NA - - NA - - 1.20 +0.16 207 1.17 -2.48 6 2.4 NA - - NA - - 2.40 +0.16 103 2.73 +13.78 2 9.6 9.62 +0.16 103 9.62 +0.23 92 9.62 +0.16 25 8.20 -14.67 0 19.2 19.23 +0.16 51 19.04 -0.83 46 19.23 +0.16 12 NA - - 76.8 76.92 +0.16 12 74.57 -2.90 11 83.33 +8.51 2 NA - - 96 1000 +4.17 9 99.43 +3.57 8 83.33 -13.19 2 NA - - 300 333.33 +11.11 2 298.30 -0.57 2 250 -16.67 0 NA - - 500 500 0 1 447.44 -10.51 1 NA - - NA - - HIGH 1000 - 0 894.89 - 0 250 - 0 8.20 - 0 LOW 3.91 - 255 3.50 - 255 0.98 - 255 0.03 - 255 DS30475A-page 170 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 16-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) BAUD FOSC = 40 MHz SPBRG 33 MHz SPBRG 25 MHz SPBRG 20 MHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - 2.40 -0.07 214 2.40 -0.15 162 2.40 +0.16 129 9.6 9.62 +0.16 64 9.55 -0.54 53 9.53 -0.76 40 9.47 -1.36 32 19.2 18.94 -1.36 32 19.10 -0.54 26 19.53 +1.73 19 19.53 +1.73 15 76.8 78.13 +1.73 7 73.66 -4.09 6 78.13 +1.73 4 78.13 +1.73 3 96 89.29 -6.99 6 103.13 +7.42 4 97.66 +1.73 3 104.17 +8.51 2 300 312.50 +4.17 1 257.81 -14.06 1 NA - - 312.50 +4.17 0 500 625 +25.00 0 NA - - NA - - NA - - HIGH 625 - 0 515.63 - 0 390.63 - 0 312.50 - 0 LOW 2.44 - 255 2.01 - 255 1.53 - 255 1.22 - 255 BAUD FOSC = 16 MHz SPBRG 10 MHz SPBRG 7.15909 MHz SPBRG 5.0688 MHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 1.20 +0.16 207 1.20 +0.16 129 1.20 +0.23 92 1.20 0 65 2.4 2.40 +0.16 103 2.40 +0.16 64 2.38 -0.83 46 2.40 0 32 9.6 9.62 +0.16 25 9.77 +1.73 15 9.32 -2.90 11 9.90 +3.13 7 19.2 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 19.80 +3.13 3 76.8 83.33 +8.51 2 78.13 +1.73 1 111.86 +45.65 0 79.20 +3.13 0 96 83.33 -13.19 2 78.13 -18.62 1 NA - - NA - - 300 250 -16.67 0 156.25 -47.92 0 NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 250 - 0 156.25 - 0 111.86 - 0 79.20 - 0 LOW 0.98 - 255 0.61 - 255 0.44 - 255 0.31 - 255 BAUD FOSC = 4 MHz SPBRG 3.579545 MHz SPBRG 1 MHz SPBRG 32.768 kHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 0.30 -0.16 207 0.30 +0.23 185 0.30 +0.16 51 0.26 -14.67 1 1.2 1.20 +1.67 51 1.19 -0.83 46 1.20 +0.16 12 NA - - 2.4 2.40 +1.67 25 2.43 +1.32 22 2.23 -6.99 6 NA - - 9.6 8.93 -6.99 6 9.32 -2.90 5 7.81 -18.62 1 NA - - 19.2 20.83 +8.51 2 18.64 -2.90 2 15.63 -18.62 0 NA - - 76.8 62.50 -18.62 0 55.93 -27.17 0 NA - - NA - - 96 NA - - NA - - NA - - NA - - 300 NA - - NA - - NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 62.50 - 0 55.93 - 0 15.63 - 0 0.51 - 0 LOW 0.24 - 255 0.22 - 255 0.06 - 255 0.002 - 255  2000 Microchip Technology Inc. Advanced Information DS30475A-page 171

PIC18CXX8 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 40 MHz SPBRG 33 MHz SPBRG 25 MHz SPBRG 20 MHz SPBRG BAUD value value value value RATE % % % % (decimal) (decimal) (decimal) (decimal) (Kbps) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - 9.60 -0.07 214 9.59 -0.15 162 9.62 +0.16 129 19.2 19.23 +0.16 129 19.28 +0.39 106 19.30 +0.47 80 19.23 +0.16 64 76.8 75.76 -1.36 32 76.39 -0.54 26 78.13 +1.73 19 78.13 +1.73 15 96 96.15 +0.16 25 98.21 +2.31 20 97.66 +1.73 15 96.15 +0.16 12 300 312.50 +4.17 7 294.64 -1.79 6 312.50 +4.17 4 312.50 +4.17 3 500 500 0 4 515.63 +3.13 3 520.83 +4.17 2 416.67 -16.67 2 HIGH 2500 - 0 2062.50 - 0 1562.50 - 0 1250 - 0 LOW 9.77 - 255 8,06 - 255 6.10 - 255 4.88 - 255 BAUD FOSC = 16 MHz SPBRG 10 MHz SPBRG 7.15909 MHz SPBRG 5.0688 MHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - 2.41 +0.23 185 2.40 0 131 9.6 9.62 +0.16 103 9.62 +0.16 64 9.52 -0.83 46 9.60 0 32 19.2 19.23 +0.16 51 18.94 -1.36 32 19.45 +1.32 22 18.64 -2.94 16 76.8 76.92 +0.16 12 78.13 +1.73 7 74.57 -2.90 5 79.20 +3.13 3 96 100 +4.17 9 89.29 -6.99 6 89.49 -6.78 4 105.60 +10.00 2 300 333.33 +11.11 2 312.50 +4.17 1 447.44 +49.15 0 316.80 +5.60 0 500 500 0 1 625 +25.00 0 447.44 -10.51 0 NA - - HIGH 1000 - 0 625 - 0 447.44 - 0 316.80 - 0 LOW 3.91 - 255 2.44 - 255 1.75 - 255 1.24 - 255 BAUD FOSC = 4 MHz SPBRG 3.579545 MHz SPBRG 1 MHz SPBRG 32.768 kHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - 0.30 +0.16 207 0.29 -2.48 6 1.2 1.20 +0.16 207 1.20 +0.23 185 1.20 +0.16 51 1.02 -14.67 1 2.4 2.40 +0.16 103 2.41 +0.23 92 2.40 +0.16 25 2.05 -14.67 0 9.6 9.62 +0.16 25 9.73 +1.32 22 8.93 -6.99 6 NA - - 19.2 19.23 +0.16 12 18.64 -2.90 11 20.83 +8.51 2 NA - - 76.8 NA - - 74.57 -2.90 2 62.50 -18.62 0 NA - - 96 NA - - 111.86 +16.52 1 NA - - NA - - 300 NA - - 223.72 -25.43 0 NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 250 - 0 55.93 - 0 62.50 - 0 2.05 - 0 LOW 0.98 - 255 0.22 - 255 0.24 - 255 0.008 - 255 DS30475A-page 172 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 16.2 USART Asynchronous Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is In this mode, the USART uses standard empty and flag bit TXIF (PIR registers) is set. This inter- non-return-to-zero (NRZ) format (one START bit, eight rupt can be enabled/disabled by setting/clearing or nine data bits and one STOP bit). The most common enable bit TXIE (PIE registers). Flag bit TXIF will be data format is 8-bits. An on-chip dedicated 8-bit baud set, regardless of the state of enable bit TXIE and can- rate generator can be used to derive standard baud not be cleared in software. It will reset only when new rate frequencies from the oscillator. The USART trans- data is loaded into the TXREG register. While flag bit mits and receives the LSb first. The USART’s transmit- TXIF indicated the status of the TXREG register, ter and receiver are functionally independent, but use another bit TRMT (TXSTA register) shows the status of the same data format and baud rate. The baud rate the TSR register. Status bit TRMT is a read only bit, generator produces a clock, either x16 or x64 of the bit which is set when the TSR register is empty. No inter- shift rate, depending on the BRGH bit (TXSTA regis- rupt logic is tied to this bit, so the user has to poll this ter). Parity is not supported by the hardware, but can be bit in order to determine if the TSR register is empty. implemented in software (and stored as the ninth data Note 1: The TSR register is not mapped in data bit). Asynchronous mode is stopped during SLEEP. memory, so it is not available to the user. Asynchronous mode is selected by clearing the SYNC 2: Flag bit TXIF is set when enable bit TXEN bit (TXSTA register). is set. The USART Asynchronous module consists of the fol- Steps to follow when setting up an Asynchronous lowing important elements: Transmission: (cid:127) Baud Rate Generator 1. Initialize the SPBRG register for the appropriate (cid:127) Sampling Circuit baud rate. If a high speed baud rate is desired, (cid:127) Asynchronous Transmitter set bit BRGH (Section16.1). (cid:127) Asynchronous Receiver 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 16.2.1 USART ASYNCHRONOUS TRANSMITTER 3. If interrupts are desired, set enable bit TXIE. The USART transmitter block diagram is shown in 4. If 9-bit transmission is desired, set transmit bit Figure16-1. The heart of the transmitter is the Transmit TX9. Can be used as address/data bit. (serial) Shift Register (TSR). The TSR register obtains 5. Enable the transmission by setting bit TXEN, its data from the Read/Write Transmit Buffer register which will also set bit TXIF. (TXREG). The TXREG register is loaded with data in 6. If 9-bit transmission is selected, the ninth bit software. The TSR register is not loaded until the STOP should be loaded in bit TX9D. bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded 7. Load data to the TXREG register (starts trans- with new data from the TXREG register (if available). mission). FIGURE 16-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register TXIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D  2000 Microchip Technology Inc. Advanced Information DS30475A-page 173

PIC18CXX8 FIGURE 16-2: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (shift clock) RC6/TX/CK (pin) START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit Word 1 TXIF bit (Transmit buffer register empty flag) Word 1 TRMT bit Transmit Shift Reg (Transmit shift register empty flag) FIGURE 16-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG Output (shift clock) RC6/TX/CK (pin) START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit START Bit Bit 0 TXIF bit (interrupt reg. flag) Word 1 Word 2 TRMT bit Word 1 Word 2 (rTegra. nesmmpitt ys hflaiftg) Transmit Shift Reg. Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC ADDEN BRGH TRMT TX9D 0000 0010 0000 0010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. DS30475A-page 174 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 16.2.2 USART ASYNCHRONOUS RECEIVER 16.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT The receiver block diagram is shown in Figure16-4. The data is received on the RC7/RX/DT pin and drives This mode would typically be used in RS-485 systems. the data recovery block. The data recovery block is Steps to follow when setting up an Asynchronous actually a high speed shifter, operating at x16 times the Reception with Address Detect Enable: baud rate, whereas the main receive serial shifter oper- 1. Initialize the SPBRG register for the appropriate ates at the bit rate or at FOSC. This mode would typi- baud rate. If a high speed baud rate is required, cally be used in RS-232 systems. set the BRGH bit. Steps to follow when setting up an Asynchronous 2. Enable the asynchronous serial port by clearing Reception: the SYNC bit and setting the SPEN bit. 1. Initialize the SPBRG register for the appropriate 3. If interrupts are required, set the RCEN bit and baud rate. If a high speed baud rate is desired, select the desired priority level with the RCIP bit. set bit BRGH (Section16.1). 4. Set the RX9 bit to enable 9-bit reception. 2. Enable the asynchronous serial port by clearing 5. Set the ADDEN bit to enable address detect. bit SYNC and setting bit SPEN. 6. Enable reception by setting the CREN bit. 3. If interrupts are desired, set enable bit RCIE. 7. The RCIF bit will be set when reception is com- 4. If 9-bit reception is desired, set bit RX9. plete. The interrupt will be acknowledged if the 5. Enable the reception by setting bit CREN. RCIE and GIE bits are set. 6. Flag bit RCIF will be set when reception is com- 8. Read the RCSTA register to determine if any plete and an interrupt will be generated if enable error occurred during reception, as well as read bit RCIE was set. bit 9 of data (if applicable). 7. Read the RCSTA register to get the ninth bit (if 9. Read RCREG to determine if the device is being enabled) and determine if any error occurred addressed. during reception. 10. If any error occurred, clear the CREN bit. 8. Read the 8-bit received data by reading the 11. If the device has been addressed, clear the RCREG register. ADDEN bit to allow all received data into the 9. If any error occurred, clear the error by clearing receive buffer and interrupt the CPU. enable bit CREN. FIGURE 16-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN SPBRG ÷ 64 MSb RSR Register LSb or Baud Rate Generator ÷ 16 STOP (8) 7 • • • 1 0 START RC7/RX/DT Pin Buffer Data and Control Recovery RX9 SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF Data Bus RCIE Note: I/O pins have diode protection to VDD and VSS.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 175

PIC18CXX8 FIGURE 16-5: ASYNCHRONOUS RECEPTION RX (pin) START START START bit bit0 bit1 bit7/8 STOP bit bit0 bit7/8 STOP bit bit7/8 STOP bit bit bit Rcv shift reg Rcv buffer reg Word 1 Word 2 Read Rcv RCREG RCREG buffer reg RCREG RCIF (interrupt flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. TABLE 16-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC ADDEN BRGH TRMT TX9D 0000 0010 0000 0010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. DS30475A-page 176 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 16.3 USART Synchronous Master Mode enabled/disabled by setting/clearing enable bit TXIE (PIE registers). Flag bit TXIF will be set, regardless of In Synchronous Master mode, the data is transmitted in the state of enable bit TXIE, and cannot be cleared in a half-duplex manner (i.e., transmission and reception software. It will reset only when new data is loaded into do not occur at the same time). When transmitting data, the TXREG register. While flag bit TXIF indicates the the reception is inhibited and vice versa. Synchronous status of the TXREG register, another bit TRMT mode is entered by setting bit SYNC (TXSTA register). (TXSTA register) shows the status of the TSR register. In addition, enable bit SPEN (RCSTA register) is set, in TRMT is a read only bit, which is set when the TSR is order to configure the RC6/TX/CK and RC7/RX/DT I/O empty. No interrupt logic is tied to this bit, so the user pins to CK (clock) and DT (data) lines, respectively. The has to poll this bit in order to determine if the TSR reg- Master mode indicates that the processor transmits the ister is empty. The TSR is not mapped in data memory, master clock on the CK line. The Master mode is so it is not available to the user. entered by setting bit CSRC (TXSTA register). Steps to follow when setting up a Synchronous Master 16.3.1 USART SYNCHRONOUS MASTER Transmission: TRANSMISSION 1. Initialize the SPBRG register for the appropriate baud rate (Section16.1). The USART transmitter block diagram is shown in 2. Enable the synchronous master serial port by Figure16-1. The heart of the transmitter is the Transmit setting bits SYNC, SPEN, and CSRC. (serial) Shift register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register 3. If interrupts are desired, set enable bit TXIE. (TXREG). The TXREG register is loaded with data in 4. If 9-bit transmission is desired, set bit TX9. software. The TSR register is not loaded until the last 5. Enable the transmission by setting bit TXEN. bit has been transmitted from the previous load. As 6. If 9-bit transmission is selected, the ninth bit soon as the last bit is transmitted, the TSR is loaded should be loaded in bit TX9D. with new data from the TXREG (if available). Once the 7. Start transmission by loading data to the TXREG register transfers the data to the TSR register TXREG register. (occurs in one TCY), the TXREG is empty and interrupt bit TXIF (PIR registers) is set. The interrupt can be TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC ADDEN BRGH TRMT TX9D 0000 0010 0000 0010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 177

PIC18CXX8 FIGURE 16-6: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT Bit 0 Bit 1 Bit 2 Bit 7 Bit 0 Bit 1 Bit 7 pin Word 1 Word 2 RC6/TX/CK pin Write to TXREG reg Write Word 1 Write Word 2 TXIF bit (Interrupt flag) TRMT bitTRMT ’1’ ’1’ TXEN bit Note: Sync Master mode; SPBRG = ’0’; continuous transmission of two 8-bit words. FIGURE 16-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit0 bit1 bit2 bit6 bit7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit DS30475A-page 178 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 16.3.2 USART SYNCHRONOUS MASTER Steps to follow when setting up a Synchronous Master RECEPTION Reception: 1. Initialize the SPBRG register for the appropriate Once Synchronous Master mode is selected, reception baud rate (Section16.1). is enabled by setting either enable bit SREN (RCSTA register), or enable bit CREN (RCSTA register). Data is 2. Enable the synchronous master serial port by sampled on the RC7/RX/DT pin on the falling edge of setting bits SYNC, SPEN and CSRC. the clock. If enable bit SREN is set, only a single word 3. Ensure bits CREN and SREN are clear. is received. If enable bit CREN is set, the reception is 4. If interrupts are desired, set enable bit RCIE. continuous until CREN is cleared. If both bits are set, 5. If 9-bit reception is desired, set bit RX9. then CREN takes precedence. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC ADDEN BRGH TRMT TX9D 0000 0010 0000 0010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception. FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit ’0’ ’0’ RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRGH = ’0’.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 179

PIC18CXX8 16.4 USART Synchronous Slave Mode 16.4.2 USART SYNCHRONOUS SLAVE RECEPTION Synchronous Slave mode differs from the Master mode, in that the shift clock is supplied externally at the The operation of the Synchronous Master and Slave RC6/TX/CK pin (instead of being supplied internally in modes is identical, except in the case of the SLEEP Master mode). This allows the device to transfer or mode and bit SREN, which is a "don’t care" in Slave receive data while in SLEEP mode. Slave mode is mode. entered by clearing bit CSRC (TXSTA register). If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during 16.4.1 USART SYNCHRONOUS SLAVE SLEEP. On completely receiving the word, the RSR TRANSMIT register will transfer the data to the RCREG register, The operation of the Synchronous Master and Slave and if enable bit RCIE bit is set, the interrupt generated modes are identical, except in the case of the SLEEP will wake the chip from SLEEP. If the global interrupt is mode. enabled, the program will branch to the interrupt vector. If two words are written to the TXREG and then the Steps to follow when setting up a Synchronous Slave SLEEP instruction is executed, the following will occur: Reception: a) The first word will immediately transfer to the 1. Enable the synchronous master serial port by TSR register and transmit. setting bits SYNC and SPEN and clearing bit CSRC. b) The second word will remain in TXREG register. 2. If interrupts are desired, set enable bit RCIE. c) Flag bit TXIF will not be set. 3. If 9-bit reception is desired, set bit RX9. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second 4. To enable reception, set enable bit CREN. word to the TSR and flag bit TXIF will be set. 5. Flag bit RCIF will be set when reception is com- e) If enable bit TXIE is set, the interrupt will wake plete. An interrupt will be generated if enable bit the chip from SLEEP. If the global interrupt is RCIE was set. enabled, the program will branch to the interrupt 6. Read the RCSTA register to get the ninth bit (if vector. enabled) and determine if any error occurred during reception. Steps to follow when setting up a Synchronous Slave Transmission: 7. Read the 8-bit received data by reading the RCREG register. 1. Enable the synchronous slave serial port by set- 8. If any error occurred, clear the error by clearing ting bits SYNC and SPEN and clearing bit bit CREN. CSRC. 2. Clear bits CREN and SREN. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set bit TX9. 5. Enable the transmission by setting enable bit TXEN. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. DS30475A-page 180 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC ADDEN BRGH TRMT TX9D 0000 0010 0000 0010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave transmission. TABLE 16-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC ADDEN BRGH TRMT TX9D 0000 0010 0000 0010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave reception.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 181

PIC18CXX8 NOTES: DS30475A-page 182 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 17.0 CAN MODULE 17.1.1 OVERVIEW OF THE MODULE 17.1 Overview The CAN bus module consists of a Protocol Engine and message buffering and control. The CAN protocol The Controller Area Network (CAN) module is a serial engine handles all functions for receiving and transmit- interface, useful for communicating with other peripher- ting messages on the CAN bus. Messages are trans- als or microcontroller devices. This interface/protocol mitted by first loading the appropriate data registers. was designed to allow communications within noisy Status and errors can be checked by reading the environments. appropriate registers. Any message detected on the CAN bus is checked for errors and then matched The CAN module is a communication controller imple- against filters to see if it should be received and stored menting the CAN 2.0 A/B protocol as defined in the in one of the 2 receive registers. BOSCH specification. The module will support CAN 1.2, CAN 2.0A, CAN2.0B Passive, and CAN 2.0B The CAN Module supports the following Frame types: Active versions of the protocol. The module implemen- (cid:127) Standard Data Frame tation is a Full CAN system. The CAN specification is (cid:127) Extended Data Frame not covered within this data sheet. The reader may (cid:127) Remote Frame refer to the BOSCH CAN specification for further details. (cid:127) Error Frame (cid:127) Overload Frame Reception The module features are as follows: (cid:127) Interframe Space • Implementation of the CAN protocol CAN1.2, CAN2.0A and CAN2.0B (cid:127) Standard and extended data frames (cid:127) 0 - 8 bytes data length (cid:127) Programmable bit rate up to 1 Mbit/sec (cid:127) Support for remote frames (cid:127) Double buffered receiver with two prioritized received message storage buffers (cid:127) 6 full (standard/extended identifier) acceptance fil- ters, 2 associated with the high priority receive buffer, and 4 associated with the low priority receive buffer (cid:127) 2 full acceptance filter masks, one each associ- ated with the high and low priority receive buffers (cid:127) Three transmit buffers with application specified prioritization and abort capability (cid:127) Programmable wake-up functionality with inte- grated low-pass filter (cid:127) Programmable Loopback mode supports self-test operation (cid:127) Signaling via interrupt capabilities for all CAN receiver and transmitter error states (cid:127) Programmable clock source (cid:127) Programmable link to timer module for time-stamping and network synchronization (cid:127) Low power SLEEP mode  2000 Microchip Technology Inc. Advanced Information DS30475A-page 183

PIC18CXX8 17.1.2 TRANSMIT/RECEIVE BUFFERS The PIC18CXX8 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer), and a total of six acceptance filters. Figure 17-1 is a block diagram of these buffers and their connection to the protocol engine. FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask BUFFERS RXM1 Acceptance Filter RXF2 Acceptance Mask Acceptance Filter A TXB0 TXB1 TXB2 RXM0 RXF3 c A c MSGREQTXABTTXLARBTXERRMTXBUFF MESSAGE MSGREQTXABTTXLARBTXERRMTXBUFF MESSAGE MSGREQTXABTTXLARBTXERRMTXBUFF MESSAGE ccep AAcccceeppRRttaaXXnnFFcc01ee FFiilltteerr AAcccceeppRRttaaXXnnFFcc45ee FFiilltteerr ept t R R X Identifier M Identifier X Message B A B Queue 0 B 1 Control Transmit Byte Sequencer Data Field Data Field Receive RXERRCNT Error PROTOCOL Counter TXERRCNT ENGINE Transmit ErrPas Error BusOff Counter Transmit Shift Receive Shift Protocol Finite CRC Generator CRC Check State Machine Bit Transmit Timing Bit Timing Logic Logic Generator TX RX DS30475A-page 184 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 17.2 Control Registers for the CAN Module 17.2.1 CAN CONTROL AND STATUS REGISTERS Note: Not all CAN registers are available in the This section shows the CAN Control and Status access bank. registers. There are many registers associated with the CAN module. Descriptions of these registers are grouped into sections. These sections are: (cid:127) Control and Status Registers (cid:127) Transmit Buffer Registers (cid:127) Receive Buffer Registers (cid:127) Baud Rate Control Registers (cid:127) Interrupt Status and Control Registers REGISTER 17-1: CANCON – CAN CONTROL REGISTER R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 — bit 7 bit 0 bit 7-5 REQOP2:REQOP0: Request CAN Operation Mode bits 1xx = Request Configuration mode 011 = Request Listen Only mode 010 = Request Loopback mode 001 = Request Disable mode 000 = Request Normal mode bit 4 ABAT: Abort All Pending Transmissions bit 1 = Abort all pending transmissions (in all transmit buffers) 0 = Transmissions proceeding as normal bit 3-1 WIN2:WIN0: Window Address bits This selects which of the CAN buffers to switch into the access bank area. This allows access to the buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See Example17-1 for code example. 111 = Receive Buffer 0 110 = Receive Buffer 0 101 = Receive Buffer 1 100 = Transmit Buffer 0 011 = Transmit Buffer 1 010 = Transmit Buffer 2 001 = Receive Buffer 0 000 = Receive Buffer 0 bit 0 Unimplemented: Read as ’0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 185

PIC18CXX8 REGISTER 17-2: CANSTAT – CAN STATUS REGISTER R-1 R-0 R-0 U-0 R-0 R-0 R-0 U-0 OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — bit 7 bit 0 bit 7-5 OPMODE2:OPMODE0: Operation Mode Status bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable mode 000 = Normal mode Note: Before the device goes into SLEEP mode, select Disable mode. bit 4 Unimplemented: Read as ’0’ bit 3-1 ICODE2:ICODE0: Interrupt Code bits When an interrupt occurs, a prioritized coded interrupt value will be present in the ICODE2:ICODE0 bits. These codes indicate the source of the interrupt. The ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer to map into the Access Bank area. See Example17-1 for code example. 111 = Wake-up on Interrupt 110 = RXB0 Interrupt 101 = RXB1 Interrupt 100 = TXB0 Interrupt 011 = TXB1 Interrupt 010 = TXB2 Interrupt 001 = Error Interrupt 000 = No Interrupt bit 0 Unimplemented: Read as ’0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 186 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 EXAMPLE 17-1: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS ; Save application required context. ; Poll interrupt flags and determine source of interrupt ; This was found to be CAN interrupt ; TempCANCON and TempCANSTAT are variables defined in Access Bank low movff CANCON, TempCANCON ; Save CANCON.WIN bits ; This is required to prevent CANCON ; from corrupting CAN buffer access ; in-progress while this interrupt ; occurred movff CANSTAT, TempCANSTAT ; Save CANSTAT register ; This is required to make sure that ; we use same CANSTAT value rather ; than one changed by another CAN ; interrupt. movf TempCANSTAT, W ; Retrieve ICODE bits andlw b’00001110’ addwf PCL, F ; Perform computed GOTO ; to corresponding interrupt cause bra NoInterrupt ; 000 = No interrupt bra ErrorInterrupt ; 001 = Error interrupt bra TXB2Interrupt ; 010 = TXB2 interrupt bra TXB1Interrupt ; 011 = TXB1 interrupt bra TXB0Interrupt ; 100 = TXB0 interrupt bra RXB1Interrupt ; 101 = RXB1 interrupt bra RXB0Interrupt ; 110 = RXB0 interrupt ; 111 = Wake-up on interrupt WakeupInterrupt bcf PIR3, WAKIF ; Clear the interrupt flag ; ; User code to handle wake-up procedure ; ; ; Continue checking for other interrupt source or return from here … NoInterrupt … ; PC should never vector here. User may ; place a trap such as infinite loop or pin/port ; indication to catch this error. ErrorInterrupt bcf PIR3, ERRIF ; Clear the interrupt flag … ; Handle error. retfie TXB2Interrupt bcf PIR3, TXB2IF ; Clear the interrupt flag goto AccessBuffer TXB1Interrupt bcf PIR3, TXB1IF ; Clear the interrupt flag goto AccessBuffer TXB0Interrupt bcf PIR3, TXB0IF ; Clear the interrupt flag goto AccessBuffer RXB1Interrupt bcf PIR3, RXB1IF ; Clear the interrupt flag goto Accessbuffer  2000 Microchip Technology Inc. Advanced Information DS30475A-page 187

PIC18CXX8 RXB0Interrupt bcf PIR3, RXB0IF ; Clear the interrupt flag goto AccessBuffer AccessBuffer ; This is either TX or RX interrupt ; Copy CANCON.ICODE bits to CANSTAT.WIN bits movf TempCANCON, W ; Clear CANCON.WIN bits before copying ; new ones. andlw b’11110001’ ; Use previously saved CANCON value to ; make sure same value. movwf TempCANCON ; Copy masked value back to TempCANCON movf TempCANSTAT, W ; Retrieve ICODE bits andlw b’00001110’ ; Use previously saved CANSTAT value ; to make sure same value. iorwf TempCANCON ; Copy ICODE bits to WIN bits. movff TempCANCON, CANCON ; Copy the result to actual CANCON ; Access current buffer… ; Your code ; Restore CANCON.WIN bits movf CANCON, W ; Preserve current non WIN bits andlw b’11110001’ iorwf TempCANCON ; Restore original WIN bits ; Do not need to restore CANSTAT - it is read-only register. ; Return from interrupt or check for another module interrupt source DS30475A-page 188 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 17-3: COMSTAT – COMMUNICATION STATUS REGISTER R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN bit 7 bit 0 bit 7 RXB0OVFL: Receive Buffer 0 Overflow bit 1 = Receive Buffer 0 overflowed 0 = Receive Buffer 0 has not overflowed bit 6 RXB1OVFL: Receive Buffer 1 Overflow bit 1 = Receive Buffer 1 overflowed 0 = Receive Buffer 1 has not overflowed bit 5 TXB0: Transmitter Bus Off bit 1 = Transmit Error Counter >255 0 = Transmit Error Counter ≤ 255 bit 4 TXBP: Transmitter Bus Passive bit 1 = Transmission Error Counter >127 0 = Transmission Error Counter ≤127 bit 3 RXBP: Receiver Bus Passive bit 1 = Receive Error Counter >127 0 = Receive Error Counter ≤127 bit 2 TXWARN: Transmitter Warning bit 1 = Transmit Error Counter >95 0 = Transmit Error Counter ≤95 bit 1 RXWARN: Receiver Warning bit 1 = Receive Error Counter >95 0 = Receive Error Counter ≤ 95 bit 0 EWARN: Error Warning bit This bit is a flag of the RXWARN and TXWARN bits 1 = The RXWARN or the TXWARN bits are set 0 = Neither the RXWARN or the TXWARN bits are set Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 189

PIC18CXX8 17.2.2 CAN TRANSMIT BUFFER REGISTERS This section describes the CAN Transmit Buffer Register and the associated Transmit Buffer Control Registers. REGISTER 17-4: TXBnCON – TRANSMIT BUFFER n CONTROL REGISTER U-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0 — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 bit 7 bit 0 bit 7 Unimplemented: Read as ’0’ bit 6 TXABT: Transmission Aborted Status bit 1 = Message was aborted 0 = Message was not aborted bit 5 TXLARB: Transmission Lost Arbitration Status bit 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Transmission Error Detected Status bit 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Transmit Request Status bit 1 = Requests sending a message. Clears the TXABT, TLARB, and TXERR bits 0 = Automatically cleared when the message is successfully sent Note: Clearing this bit in software, while the bit is set, will request a message abort. bit 2 Unimplemented: Read as ’0’ bit 1-0 TXPRI1:TXPRI0: Transmit Priority bits 11 = Priority Level 3 (Highest Priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (Lowest Priority) Note: These bits set the order in which Transmit buffer will be transferred. They do not alter CAN message identifier. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-5: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER HIGH BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits, if EXIDE = 0 (TXBnSID Register). Extended Identifier bits EID28:EID21, if EXIDE = 1. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 190 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 17-6: TXBnSIDL – TRANSMIT BUFFER n STANDARD IDENTIFIER LOW BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits, if EXIDE = 0. Extended Identifier bits EID20:EID18, if EXIDE = 1. bit 4 Unimplemented: Read as ’0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Message will transmit Extended ID, SID10:SID0 becomes EID28:EID18 0 = Message will transmit Standard ID, EID17:EID0 are ignored bit 2 Unimplemented: Read as ’0’ bit 1-0 EID17:EID16: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-7: TXBnEIDH – TRANSMIT BUFFER n EXTENDED IDENTIFIER HIGH BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-8: TXBnEIDL – TRANSMIT BUFFER n EXTENDED IDENTIFIER LOW BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 191

PIC18CXX8 REGISTER 17-9: TXBnDm – TRANSMIT BUFFER n DATA FIELD BYTE m REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0 bit 7 bit 0 bit 1-0 TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0≤n<3 and 0<m<8) Each Transmit Buffer has an array of registers. For example, Transmit buffer 0 has 7 registers: TXB0D0 to TXB0D7. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-10: TXBnDLC – TRANSMIT BUFFER n DATA LENGTH CODE REGISTER U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 bit 7 Unimplemented: Read as ’0’ bit 6 TXRTR: Transmission Frame Remote Transmission Request bit 1 = Transmitted message will have TXRTR bit set 0 = Transmitted message will have TXRTR bit cleared. bit 5-4 Unimplemented: Read as ’0’ bit 3-0 DLC3:DLC0: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data Length = 8 bytes 0111 = Data Length = 7 bytes 0110 = Data Length = 6 bytes 0101 = Data Length = 5 bytes 0100 = Data Length = 4 bytes 0011 = Data Length = 3 bytes 0010 = Data Length = 2 bytes 0001 = Data Length = 1 bytes 0000 = Data Length = 0 bytes Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 192 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 17-11: TXERRCNT – TRANSMIT ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 bit 7 bit 0 bit 7-0 TEC7:TEC0: Transmit Error Counter bits This register contains a value which is derived from the rate at which errors occur. When the error count overflows, the bus off state occurs. When the bus has 128 occurrences of 11 con- secutive recessive bits, the counter value is cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 193

PIC18CXX8 17.2.3 CAN RECEIVE BUFFER REGISTERS This section shows the Receive Buffer registers with its associated control registers. REGISTER 17-12: RXB0CON – RECEIVE BUFFER 0 CONTROL REGISTER R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R/W-0 RXFUL RXM1 RXM0 — RXRTRRO RXB0DBEN JTOFF FILHIT0 bit 7 bit 0 bit 7 RXFUL: Receive Full Status bit 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module and should be cleared by software after the buffer is read. bit 6-5 RXM1:RXM0: Receive Buffer Mode bits 11 = Receive all messages (including those with errors) 10 = Receive only valid messages with extended identifier 01 = Receive only valid messages with standard identifier 00 = Receive all valid messages bit 4 Unimplemented: Read as ’0’ bit 3 RXRTRRO: Receive Remote Transfer Request Read Only bit 1 = Remote transfer request 0 = No remote transfer request bit 2 RXB0DBEN: Receive Buffer 0 Double Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 bit 1 JTOFF: Jump Table Offset bit (read only copy of RX0DBEN) 1 = Allows Jump Table offset between 6 and 7 0 = Allows Jump Table offset between 1 and 0 Note: This bit allows same filter jump table for both RXB0CON and RXB1CON. bit 0 FILHIT0: Filter Hit bit This bit indicates which acceptance filter enabled the message reception into receive buffer 0 1 = Acceptance Filter 1 (RXF1) 0 = Acceptance Filter 0 (RXF0) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 194 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 17-13: RXB1CON – RECEIVE BUFFER 1 CONTROL REGISTER R/C-0 R/W-0 R/W-0 U-0 R-0 R-0 R-0 R-0 RXFUL RXM1 RXM0 — RXRTRRO FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 bit 7 RXFUL: Receive Full Status bit 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module and should be cleared by software after the buffer is read. bit 6-5 RXM1:RXM0: Receive Buffer Mode bits 11 = Receive all messages (including those with errors) 10 = Receive only valid messages with extended identifier 01 = Receive only valid messages with standard identifier 00 = Receive all valid messages bit 4 Unimplemented: Read as ’0’ bit 3 RXRTRRO: Receive Remote Transfer Request bit (read only) 1 = Remote transfer request 0 = No remote transfer request bit 2-0 FILHIT2:FILHIT0: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1. 111 = Reserved 110 = Reserved 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1) only possible when RXB0DBEN bit is set 000 = Acceptance Filter 0 (RXF0) only possible when RXB0DBEN bit is set Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-14: RXBnSIDH – RECEIVE BUFFER n STANDARD IDENTIFIER HIGH BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits, if EXID = 0 (RXBnSIDL Register). Extended Identifier bits EID28:EID21, if EXID = 1. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 195

PIC18CXX8 REGISTER 17-15: RXBnSIDL – RECEIVE BUFFER n STANDARD IDENTIFIER LOW BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits, if EXID = 0. Extended Identifier bits EID20:EID18, if EXID = 1. bit 4 SRR: Substitute Remove Request bit (only when EXID = ’1’) 1 = Remote transfer request occurred 0 = No remote transfer request occurred bit 3 EXID: Extended Identifier bit 1 = Received message is an Extended Data Frame, SID10:SID0 are EID28:EID18 0 = Received message is a Standard Data Frame bit 2 Unimplemented: Read as ’0’ bit 1-0 EID17:EID16: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-16: RXBnEIDH – RECEIVE BUFFER n EXTENDED IDENTIFIER HIGH BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-17: RXBnEIDL – RECEIVE BUFFER n EXTENDED IDENTIFIER LOW BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 196 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 17-18: RXBnDLC – RECEIVE BUFFER n DATA LENGTH CODE REGISTER U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 bit 7 Unimplemented: Read as ’0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request bit 5 RB1: Reserved bit 1 Reserved by CAN Spec and read as ’0’ bit 4 RB0: Reserved bit 0 Reserved by CAN Spec and read as ’0’ bit 3-0 DLC3:DLC0: Data Length Code bits 1111 = Invalid 1110 = Invalid 1101 = Invalid 1100 = Invalid 1011 = Invalid 1010 = Invalid 1001 = Invalid 1000 = Data Length = 8 bytes 0111 = Data Length = 7 bytes 0110 = Data Length = 6 bytes 0101 = Data Length = 5 bytes 0100 = Data Length = 4 bytes 0011 = Data Length = 3 bytes 0010 = Data Length = 2 bytes 0001 = Data Length = 1 bytes 0000 = Data Length = 0 bytes Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-19: RXBnDm – RECEIVE BUFFER n DATA FIELD BYTE m REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0 bit 7 bit 0 bit 7-0 RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0≤n<1 and 0<m<7) Each Receive Buffer has an array of registers. For example, Receive buffer 0 has 8 registers: RXB0D0 to RXB0D7. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 197

PIC18CXX8 REGISTER 17-20: RXERRCNT – RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 bit 7 bit 0 bit 7-0 REC7:REC0: Receive Error Counter bits This register contains the Receive Error value as defined by the CAN specifications. When RXERRCNT > 127, the module will go into an error passive state. RXERRCNT does not have the ability to put the module in “Bus Off” state. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 198 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 17.2.4 MESSAGE ACCEPTANCE FILTERS This subsection describes the Message Acceptance filters. REGISTER 17-21: RXFnSIDH – RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER HIGH BYTE R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier Filter bits, if EXIDEN = 0. Extended Identifier Filter bits EID28:EID21, if EXIDEN = 1, Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-22: RXFnSIDL – RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER LOW BYTE R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDEN — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier Filter bits, if EXIDEN = 0. Extended Identifier Filter bits EID20:EID18, if EXIDEN = 0. bit 4 Unimplemented: Read as ’0’ bit 3 EXIDEN: Extended Identifier Filter Enable bit 1 = Filter will only accept Extended ID messages 0 = Filter will only accept Standard ID messages bit 2 Unimplemented: Read as ’0’ bit 1-0 EID17:EID16: Extended Identifier Filter bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-23: RXFnEIDH – RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER HIGH BYTE R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier Filter bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 199

PIC18CXX8 REGISTER 17-24: RXFnEIDL – RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER LOW BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier Filter bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-25: RXMnSIDH – RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK HIGH BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier Mask bits, or Extended Identifier Mask bits EID28:EID21 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-26: RXMnSIDL – RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK LOW BYTE REGISTER R/W-x R/W-x R/W-x U-0 U-0 U-0 R/W-x R/W-x SID2 SID1 SID0 — — — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier Mask bits, or Extended Identifier Mask bits EID20:EID18 bit 4-2 Unimplemented: Read as ’0’ bit 1-0 EID17:EID16: Extended Identifier Mask bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 200 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 17-27: RXMnEIDH – RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK HIGH BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 1-0 EID15:EID8: Extended Identifier Mask bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown REGISTER 17-28: RXMnEIDL – RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK LOW BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 1-0 EID7:EID0: Extended Identifier Mask bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 201

PIC18CXX8 17.2.5 CAN BAUD RATE REGISTERS This subsection describes the CAN Baud Rate registers. REGISTER 17-29: BRGCON1 – BAUD RATE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 bit 7 bit 0 bit 7-6 SJW1:SJW0: Synchronized Jump Width bits 11 = Synchronization Jump Width Time = 4 x TQ 10 = Synchronization Jump Width Time = 3 x TQ 01 = Synchronization Jump Width Time = 2 x TQ 00 = Synchronization Jump Width Time = 1 x TQ bit 5-0 BRP5:BRP0: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FOSC 111110 = TQ = (2 x 63)/FOSC : : 000001 = TQ = (2 x 2)/FOSC 000000 = TQ = (2 x 1)/FOSC Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: This register is only accessible in Configuration mode. DS30475A-page 202 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 17-30: BRGCON2 – BAUD RATE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the CAN Bus Line bit 1 = Bus line is sampled three times prior to the sample point 0 = Bus line is sampled once at the sample point bit 5-3 SEG1PH2:SEG1PH0: Phase Segment 1 bits 111 = Phase Segment 1 Time = 8 x TQ 110 = Phase Segment 1 Time = 7 x TQ 101 = Phase Segment 1 Time = 6 x TQ 100 = Phase Segment 1 Time = 5 x TQ 011 = Phase Segment 1 Time = 4 x TQ 010 = Phase Segment 1 Time = 3 x TQ 001 = Phase Segment 1 Time = 2 x TQ 000 = Phase Segment 1 Time = 1 x TQ bit 2-0 PRSEG2:PRSEG0: Propagation Time Select bits 111 = Propagation Time = 8 x TQ 110 = Propagation Time = 7 x TQ 101 = Propagation Time = 6 x TQ 100 = Propagation Time = 5 x TQ 011 = Propagation Time = 4 x TQ 010 = Propagation Time = 3 x TQ 001 = Propagation Time = 2 x TQ 000 = Propagation Time = 1 x TQ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: This register is only accessible in Configuration mode.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 203

PIC18CXX8 REGISTER 17-31: BRGCON3 – BAUD RATE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 bit 7 bit 0 bit 7 Unimplemented: Read as ’0’ bit 6 WAKFIL: Selects CAN Bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 5-3 Unimplemented: Read as ’0’ bit 2-0 SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits 111 = Phase Segment 2 Time = 8 x TQ 110 = Phase Segment 2 Time = 7 x TQ 101 = Phase Segment 2 Time = 6 x TQ 100 = Phase Segment 2 Time = 5 x TQ 011 = Phase Segment 2 Time = 4 x TQ 010 = Phase Segment 2 Time = 3 x TQ 001 = Phase Segment 2 Time = 2 x TQ 000 = Phase Segment 2 Time = 1 x TQ Note: Ignored if SEG2PHTS bit is clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 204 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 17.2.6 CAN MODULE I/O CONTROL REGISTER This subsection describes the CAN Module I/O Control register. REGISTER 17-32: CIOCON – CAN I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 TX1SRC TX1EN ENDRHI CANCAP — — — — bit 7 bit 0 bit 7 TX1SRC: CAN TX1 Pin Data Source 1 = CAN TX1 pin will output the CAN clock 0 = CAN TX1 pin will output TXD bit 6 TX1EN: CAN TX1 Pin Enable 1 = CAN TX1 pin will output TXD or CAN clock 0 = CAN TX1 pin will have digital I/O function bit 5 ENDRHI: Enable Drive High 1 = CAN TX0, CAN TX1 pins will drive VDD when recessive 0 = CAN TX0, CAN TX1 pins will tri-state when recessive bit 4 CANCAP: CAN Message Receive Capture Enable 1 = Enable CAN capture 0 = Disable CAN capture bit 3-0 Unimplemented: Read as ’0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 205

PIC18CXX8 17.2.7 CAN INTERRUPT REGISTERS REGISTER 17-33: PIR3 – PERIPHERAL INTERRUPT FLAG REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF bit 7 bit 0 bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus bit 6 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit 1 = Activity on CAN bus has occurred 0 = No activity on CAN bus bit 5 ERRIF: CAN Bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors bit 4 TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message, and may be re-loaded 0 = Transmit Buffer 2 has not completed transmission of a message bit 3 TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit 1 = Transmit Buffer 1 has completed transmission of a message, and may be re-loaded 0 = Transmit Buffer 1 has not completed transmission of a message bit 2 TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit 1 = Transmit Buffer 0 has completed transmission of a message, and may be re-loaded 0 = Transmit Buffer 0 has not completed transmission of a message bit 1 RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message bit 0 RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 206 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 17-34: PIE3 – PERIPHERAL INTERRUPT ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE bit 7 bit 0 bit 7 IRXIE: CAN Invalid Received Message Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt bit 6 WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt bit 5 ERRIE: CAN Bus Error Interrupt Enable bit 1 = Enable CAN bus error interrupt 0 = Disable CAN bus error interrupt bit 4 TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt bit 3 TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt bit 2 TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt bit 1 RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt bit 0 RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 207

PIC18CXX8 REGISTER 17-35: IPR3 – PERIPHERAL INTERRUPT PRIORITY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP bit 7 bit 0 bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN Bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 208 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 17-1: CAN CONTROLLER REGISTER MAP Address Name Address Name Address Name Address Name F7Fh F5Fh F3Fh F1Fh RXM1EIDL F7Eh F5Eh CANSTAT F3Eh CANSTAT F1Eh RXM1EIDH F7Dh F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79h F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F78h F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH F77h F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EIDH F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDL F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EIDH F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH F6Fh CANCON F4Fh F2Fh F0Fh RXF3EIDL F6Eh CANSTAT F4Eh CANSTAT F2Eh CANSTAT F0Eh RXF3EIDH F6Dh RXB0D7 F4Dh TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL F6Ch RXB0D6 F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH F6Bh RXB0D5 F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EIDL F6Ah RXB0D4 F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EIDH F69h RXB0D3 F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL F68h RXB0D2 F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH F67h RXB0D1 F47h TXB0D1 F27h TXB2D1 F07h RXF1EIDL F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h RXF1EIDH F65h RXB0DLC F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL F64h RXB0EIDL F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH F63h RXB0EIDH F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDH F62h RXB0SIDL F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EIDL F61h RXB0SIDH F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SIDH Note: Shaded registers are available in Access Bank Low area while the rest are available in Bank 15.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 209

PIC18CXX8 17.3 CAN Modes of Operation 17.3.2 DISABLE MODE The PIC18CXX8 has the following modes of operation. In Disable mode, the module will not transmit or These modes are: receive. The module has the ability to set the WAKIF bit due to bus activity, however, any pending interrupts will (cid:127) Configuration mode remain and the error counters will retain their value. (cid:127) Disable mode If REQOP<2:0> is set to 001, the module will enter the (cid:127) Normal Operation mode module Disable mode. This mode is similar to dis- (cid:127) Listen Only mode abling other peripheral modules by turning off the mod- (cid:127) Loopback mode ule enables. This causes the module internal clock to (cid:127) Error Recognition mode (selected through stop unless the module is active (i.e., receiving or CANRXM bits) transmitting a message). If the module is active, the module will wait for 11 recessive bits on the CAN bus, Modes are requested by setting the REQOP bits, detect that condition as an idle bus, then accept the except the Error Recognition mode, which is requested module disable command. OPMODE<2:0>=001 indi- through the CANRXM bits. Entry into a mode is cates whether the module successfully went into mod- acknowledged by monitoring the OPMODE bits. ule Disable mode When changing modes, the mode will not actually The WAKIF interrupt is the only module interrupt that is change until all pending message transmissions are still active in the module Disable mode. If the WAKIE is complete. Because of this, the user must verify that the set, the processor will receive an interrupt whenever device has actually changed into the requested mode the CAN bus detects a dominant state, as occurs with before further operations are executed. a SOF. 17.3.1 CONFIGURATION MODE The I/O pins will revert to normal I/O function when the module is in the module Disable mode. The CAN module has to be initialized before the activa- tion. This is only possible if the module is in the Config- 17.3.3 NORMAL MODE uration mode. The Configuration mode is requested by setting REQOP2 bit. Only when the status bit This is the standard operating mode of the OPMODE2 has a high level, the initialization can be PIC18CXX8. In this mode, the device actively monitors performed. Afterwards, the configuration registers and all bus messages and generates acknowledge bits, the acceptance mask registers and the acceptance fil- error frames, etc. This is also the only mode in which ter registers can be written. The module is activated by the PIC18CXX8 will transmit messages over the CAN setting the control bits CFGREQ to zero. bus. The module will protect the user from accidentally vio- 17.3.4 LISTEN ONLY MODE lating the CAN protocol through programming errors. All registers which control the configuration of the mod- Listen Only mode provides a means for the ule can not be modified while the module is on-line. PIC18CXX8 to receive all messages, including mes- The CAN module will not be allowed to enter the Con- sages with errors. This mode can be used for bus mon- figuration mode while a transmission is taking place. itor applications, or for detecting the baud rate in ‘hot The CONFIG bit serves as a lock to protect the follow- plugging’ situations. For auto-baud detection, it is nec- ing registers. essary that there are at least two other nodes which are (cid:127) Configuration registers communicating with each other. The baud rate can be detected empirically by testing different values until (cid:127) Bus Timing registers valid messages are received. The Listen Only mode is (cid:127) Identifier Acceptance Filter registers a silent mode, meaning no messages will be transmit- (cid:127) Identifier Acceptance Mask registers ted while in this state, including error flags or acknowl- In the Configuration mode, the module will not transmit edge signals. The filters and masks can be used to or receive. The error counters are cleared and the inter- allow only particular messages to be loaded into the rupt flags remain unchanged. The programmer will receive registers, or the filter masks can be set to all have access to configuration registers that are access zeros to allow a message with any identifier to pass. restricted in other modes. The error counters are reset and deactivated in this state. The Listen Only mode is activated by setting the mode request bits in the CANCON register. DS30475A-page 210 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 17.3.5 LOOPBACK MODE 17.4.2 TRANSMIT PRIORITY This mode will allow internal transmission of messages Transmit priority is a prioritization, within the PIC18CXX8, from the transmit buffers to the receive buffers, without of the pending transmittable messages. This is indepen- actually transmitting messages on the CAN bus. This dent from, and not related to, any prioritization implicit in mode can be used in system development and testing. the message arbitration scheme built into the CAN proto- In this mode, the ACK bit is ignored and the device will col. Prior to sending the SOF, the priority of all buffers that allow incoming messages from itself just as if they were are queued for transmission is compared. The transmit coming from another node. The Loopback mode is a buffer with the highest priority will be sent first. If two buff- silent mode, meaning no messages will be transmitted ers have the same priority setting, the buffer with the while in this state, including error flags or acknowledge highest buffer number will be sent first. There are four lev- signals. The TXCAN pin will revert to port I/O while the els of transmit priority. If TXP bits for a particular message device is in this mode. The filters and masks can be buffer are set to 11, that buffer has the highest possible used to allow only particular messages to be loaded into priority. If TXP bits for a particular message buffer are 00, the receive registers. The masks can be set to all zeros that buffer has the lowest possible priority. to provide a mode that accepts all messages. The Loop- back mode is activated by setting the mode request bits 17.4.3 INITIATING TRANSMISSION in the CANCON register. To initiate message transmission, the TXREQ bit must be 17.3.6 ERROR RECOGNITION MODE set for each buffer to be transmitted. When TXREQ is set, the TXABT, TXLARB and TXERR The module can be set to ignore all errors and receive bits will be cleared. any message. The Error Recognition mode is activated by setting the RXM<1:0> bits in the RXBnCON regis- Setting the TXREQ bit does not initiate a message ters to 11. In this mode, the data which is in the mes- transmission, it merely flags a message buffer as ready sage assembly buffer until the error time, is copied in for transmission. Transmission will start when the the receive buffer and can be read via the CPU inter- device detects that the bus is available. The device will face. In addition, the data which was on the internal then begin transmission of the highest priority message sampling of the CAN bus at the error time and the state that is ready. vector of the protocol state machine and the bit counter When the transmission has completed successfully, the CntCan, are stored in registers and can be read. TXREQ bit will be cleared, the TXBnIF bit will be set, and an interrupt will be generated if the TXBnIE bit is set. 17.4 CAN Message Transmission If the message transmission fails, the TXREQ will remain 17.4.1 TRANSMIT BUFFERS set indicating that the message is still pending for trans- mission and one of the following condition flags will be set. The PIC18CXX8 implements three Transmit Buffers. If the message started to transmit but encountered an Each of these buffers occupies 14 bytes of SRAM and error condition, the TXERR and the IRXIF bits will be set are mapped into the device memory maps. and an interrupt will be generated. If the message lost For the MCU to have write access to the message buffer, arbitration, the TXLARB bit will be set. the TXREQ bit must be clear, indicating that the message 17.4.4 ABORTING TRANSMISSION buffer is clear of any pending message to be transmitted. At a minimum, the TXBNSIDH, TXBNSIDL, and The MCU can request to abort a message by clearing TXBNDLC registers must be loaded. If data bytes are the TXBnCON.TXREQ bit associated with the corre- present in the message, the TXBNDm registers must also sponding message buffer. Setting CANCON.ABAT bit be loaded. If the message is to use extended identifiers, will request an abort of all pending messages. If the the TXBNEIDm registers must also be loaded and the message has not yet started transmission, or if the EXIDE bit set. message started but is interrupted by loss of arbitration Prior to sending the message, the MCU must initialize or an error, the abort will be processed. The abort is the TXINE bit to enable or disable the generation of an indicated when the module sets TXBnCON.ABTF bits. interrupt when the message is sent. The MCU must If the message has started to transmit, it will attempt to also initialize the TXP priority bits (see Section17.4.2). transmit the current message fully. If the current mes- sage is transmitted fully and is not lost to arbitration or an error, the ABTF bit will not be set, because the mes- sage was transmitted successfully. Likewise, if a mes- sage is being transmitted during an abort request and the message is lost to arbitration or an error, the mes- sage will not be re-transmitted and the ABTF bit will be set, indicating that the message was successfully aborted.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 211

PIC18CXX8 FIGURE 17-2: TRANSMIT MESSAGE FLOWCHART Start The message transmission sequence begins when the device determines that the TXREQ for any of the transmit registers has been set. No Are any TXREQ bits = 1 ? Yes Clearing the TXREQ bit while it is set, or setting Clear: TXABT, TXLARB, the ABAT bit before the message has started and TXERR transmission will abort the message. CAN busIs available No TXREIsQ = 0 No to start transmission ABAT = 1 ? ? Yes Yes Examine TXPRI <1:0> to Determine Highest Priority Message Begin transmission (SOF) Was No Set Message Transmitted TXERR = 1 Successfully? Yes Set TXREQ = 0 TXLARIsB = 1? Yes Arbitration lost during transmission Yes Is Generate TXIE = 1? Interrupt No A message can also be aborted if a message is error or lost arbitration TXREQ = 0 Yes condition occurred during Set or TXABT = 1 transmission. TXBUFE = 1 ? The TXIE bit determines if an inter- rupt should be generated when a No message is successfully transmitted. Abort Transmission: Set TXABT = 1 END DS30475A-page 212 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 17.5 Message Reception 17.5.3 RECEIVE PRIORITY 17.5.1 RECEIVE MESSAGE BUFFERING RXB0 is the higher priority buffer and has two message acceptance filters associated with it. RXB1 is the lower The PIC18CXX8 includes two full receive buffers with priority buffer and has four acceptance filters associ- multiple acceptance filters for each. There is also a ated with it. The lower number of acceptance filters separate Message Assembly Buffer (MAB), which acts makes the match on RXB0 more restrictive and implies as a third receive buffer (see Figure17-3). a higher priority for that buffer. Additionally, the RXB0CON register can be configured such that if 17.5.2 RECEIVE BUFFERS RXB0 contains a valid message, and another valid Of the three receive buffers, the MAB is always commit- message is received, an overflow error will not occur ted to receiving the next message from the bus. The and the new message will be moved into RXB1, remaining two receive buffers are called RXB0 and regardless of the acceptance criteria of RXB1. There RXB1 and can receive a complete message from the are also two programmable acceptance filter masks protocol engine. The MCU can access one buffer while available, one for each receive buffer (see Section 4.5). the other buffer is available for message reception, or When a message is received, bits <3:0> of the RXBNCON holding a previously received message. register will indicate the acceptance filter number that enabled reception, and whether the received message is a The MAB assembles all messages received. These messages will be transferred to the RXBN buffers, only remote transfer request. if the acceptance filter criteria are met. The RXM bits set special receive modes. Normally, these bits are set to 00 to enable reception of all valid Note: The entire contents of the MAB is moved into messages, as determined by the appropriate accep- the receive buffer once a message is tance filters. In this case, the determination of whether accepted. This means that regardless of the or not to receive standard or extended messages is type of identifier (standard or extended) and determined by the EXIDE bit in the acceptance filter the number of data bytes received, the entire register. If the RXM bits are set to 01 or 10, the receiver receive buffer is overwritten with the MAB will accept only messages with standard or extended contents. Therefore, the contents of all regis- identifiers, respectively. If an acceptance filter has the ters in the buffer must be assumed to have EXIDE bit set such that it does not correspond with the been modified when any message is RXM mode, that acceptance filter is rendered useless. received. These two modes of RXM bits can be used in systems When a message is moved into either of the receive where it is known that only standard or extended mes- buffers, the appropriate RXBnIF bit is set. This bit must sages will be on the bus. If the RXM bits are set to 11, be cleared by the MCU when it has completed process- the buffer will receive all messages, regardless of the ing the message in the buffer, in order to allow a new values of the acceptance filters. Also, if a message has message to be received into the buffer. This bit pro- an error before the end of frame, that portion of the vides a positive lockout to ensure that the MCU has fin- message assembled in the MAB before the error ished with the message before the PIC18CXX8 frame, will be loaded into the buffer. This mode has attempts to load a new message into the receive buffer. some value in debugging a CAN system and would not If the RXBnIE bit is set, an interrupt will be generated to be used in an actual system environment. indicate that a valid message has been received.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 213

PIC18CXX8 FIGURE 17-3: RECEIVE BUFFER BLOCK DIAGRAM Acceptance Mask RXM1 Acceptance Filter RXF2 Acceptance Mask Acceptance Filter RXM0 RXF3 A c Acceptance Filter Acceptance Filter c RXF0 RXF4 e p A t c c Acceptance Filter Acceptance Filter e RXF1 RXF5 p t R M R X Identifier A Identifier X B B B 0 1 Data Field Data Field DS30475A-page 214 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 17-4: MESSAGE RECEPTION FLOWCHART Start Detect No Start of Message? Yes Begin Loading Message into Message Assembly Buffer (MAB) Valid Generate No Message Error Received? Frame Yes Yes, meets criteria Yes, meets criteria for RXBO Message for RXB1 Identifier meets a filter criteria? No Go to Start The RXRDY bit determines if the receive register is empty and able to accept a new message. The RXB0DBEN bit determines if RXB0 can roll over into RXB1 if it is full. Is No Is Yes RXRDY = 0? RX0DBEN = 1? Yes No Move message into RXB0 GSeetn RerXaBte0 OOVveFrLrun Error: GSeetn RerXaBte1 OOVveFrLrun Error: No RXRDIsY = 0? Set RXRDY = 1 Yes Move message into RXB1 Set FILHIT <0> Is No ERRIE = 1? according to which filter criteria was met Set RXRDY = 1 Yes Go to Start Set FILHIT <2:0> according to which filter criteria was met RXIEIs = 1? GInetenreruraptte Yes RXIEIs = 1? Yes No Set CANSTAT <3:0> according No to which receive buffer the message was loaded into  2000 Microchip Technology Inc. Advanced Information DS30475A-page 215

PIC18CXX8 17.6 Message Acceptance Filters and The coding of the RXB0DBEN bit enables these three Masks bits to be used similarly to the FILHIT bits and to distin- guish a hit on filter RXF0 and RXF1, in either RXB0, or The Message Acceptance Filters and Masks are used after a roll over into RXB1. to determine if a message in the message assembly (cid:127) 111 = Acceptance Filter 1 (RXF1) buffer should be loaded into either of the receive buff- (cid:127) 110 = Acceptance Filter 0 (RXF0) ers. Once a valid message has been received into the MAB, the identifier fields of the message are compared (cid:127) 001 = Acceptance Filter 1 (RXF1) to the filter values. If there is a match, that message will (cid:127) 000 = Acceptance Filter 0 be loaded into the appropriate receive buffer. The filter If the RXB0DBEN bit is clear, there are six codes cor- masks are used to determine which bits in the identifier responding to the six filters. If the RXB0DBEN bit is set, are examined with the filters. A truth table is shown there are six codes corresponding to the six filters, plus below in Table17-2 that indicates how each bit in the two additional codes corresponding to RXF0 and RXF1 identifier is compared to the masks and filters to deter- filters that roll over into RXB1. mine if a the message should be loaded into a receive buffer. The mask essentially determines which bits to If more than one acceptance filter matches, the FILHIT apply the acceptance filters to. If any mask bit is set to bits will encode the binary value of the lowest num- a zero, then that bit will automatically be accepted, bered filter that matched. In other words, if filter RXF2 regardless of the filter bit. and filter RXF4 match, FILHIT will be loaded with the value for RXF2. This essentially prioritizes the accep- TABLE 17-2: FILTER/MASK TRUTH TABLE tance filters with a lower number filter having higher pri- ority. Messages are compared to filters in ascending Message Accept or Mask order of filter number. Filter bit n Identifier Reject bit n bit n001 bit n The mask and filter registers can only be modified when the PIC18CXX8 is in Configuration mode. The 0 X X Accept mask and filter registers cannot be read outside of Con- 1 0 0 Accept figuration mode. When outside of Configuration mode, 1 0 1 Reject all mask and filter registers will be read as ‘0’. 1 1 0 Reject 1 1 1 Accept Legend: X = don’t care As shown in the Receive Buffers Block Diagram (Figure17-3), acceptance filters RXF0 and RXF1, and filter mask RXM0 are associated with RXB0. Filters RXF2, RXF3, RXF4, and RXF5 and mask RXM1 are associated with RXB1. When a filter matches and a message is loaded into the receive buffer, the filter number that enabled the message reception is loaded into the FILHIT bit(s). For RXB1, the RXB1CON regis- ter contains the FILHIT<2:0> bits. They are coded as follows: (cid:127) 101 = Acceptance Filter 5 (RXF5) (cid:127) 100 = Acceptance Filter 4 (RXF4) (cid:127) 011 = Acceptance Filter 3 (RXF3) (cid:127) 010 = Acceptance Filter 2 (RXF2) (cid:127) 001 = Acceptance Filter 1 (RXF1) (cid:127) 000 = Acceptance Filter 0 (RXF0) Note: 000 and 001 can only occur if the RXB0DBEN bit is set in the RXB0CON register, allowing RXB0 messages to roll over into RXB1. DS30475A-page 216 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 17-5: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION Acceptance Filter Register Acceptance Mask Register RXFn RXMn 0 0 RXFn RXMn1 RxRqst 1 RXFn RXMn n n Message Assembly Buffer Identifier  2000 Microchip Technology Inc. Advanced Information DS30475A-page 217

PIC18CXX8 17.7 Baud Rate Setting All devices on the CAN bus must use the same bit rate. However, all devices are not required to have the same All nodes on a given CAN bus must have the same master oscillator clock frequency. For the different nominal bit rate. The CAN protocol uses clock frequencies of the individual devices, the bit rate Non-Return-to-Zero (NRZ) coding, which does not has to be adjusted by appropriately setting the baud encode a clock within the data stream. Therefore, the rate prescaler and number of time quanta in each seg- receive clock must be recovered by the receiving ment. nodes and synchronized to the transmitters clock. The nominal bit rate is the number of bits transmitted As oscillators and transmission time may vary from per second assuming an ideal transmitter with an ideal node to node, the receiver must have some type of oscillator, in the absence of resynchronization. The Phase Lock Loop (PLL) synchronized to data transmis- nominal bit rate is defined to be a maximum of 1Mb/s. sion edges, to synchronize and maintain the receiver Nominal Bit Time is defined as: clock. Since the data is NRZ coded, it is necessary to include bit stuffing to ensure that an edge occurs at TBIT = 1 / NOMlNAL BlT RATE least every six bit times, to maintain the Digital Phase The nominal bit time can be thought of as being divided Lock Loop (DPLL) synchronization. into separate non-overlapping time segments. These The bit timing of the PIC18CXX8 is implemented using segments are shown in Figure17-6. a DPLL that is configured to synchronize to the incom- (cid:127) Synchronization Segment (Sync_Seg) ing data, and provide the nominal timing for the trans- (cid:127) Propagation Time Segment (Prop_Seg) mitted data. The DPLL breaks each bit time into (cid:127) Phase Buffer Segment 1 (Phase_Seg1) multiple segments, made up of minimal periods of time called the time quanta (TQ). (cid:127) Phase Buffer Segment 2 [Phase_Seg2) Bus timing functions executed within the bit time frame, Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg + such as synchronization to the local oscillator, network Phase_Seg1 + Phase_Seg2) transmission delay compensation, and sample point The time segments and also, the nominal bit time, are positioning, are defined by the programmable bit timing made up of integer units of time called time quanta or logic of the DPLL. TQ (see Figure17-6). By definition, the nominal bit time is programmable from a minimum of 8 TQ to a maxi- mum of 25 TQ. Also by definition, the minimum nominal bit time is 1 µs, corresponding to a maximum 1 Mb/s rate. FIGURE 17-6: BIT TIME PARTITIONING Input Signal Prop Phase Phase Sync Segment Segment 1 Segment 2 Sample Point TQ DS30475A-page 218 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 17.7.1 TIME QUANTA 17.7.4 PHASE BUFFER SEGMENTS The Time Quanta is a fixed unit of time derived from the The Phase Buffer Segments are used to optimally locate oscillator period. There is a programmable baud rate the sampling point of the received bit, within the nominal prescaler, with integral values ranging from 1 to 64, in bit time. The sampling point occurs between phase seg- addition to a fixed divide by two for clock generation. ment 1 and phase segment 2. These segments can be lengthened or shortened by the resynchronization pro- EXAMPLE 17-2: CALCULATION FOR cess. The end of phase segment 1 determines the sam- FOSC = 16MHz pling point within a bit time. Phase segment 1 is programmable from 1 TQ to 8 TQ in duration. Phase seg- If Fosc = 16 MHz, BRP<5:0> = 00h, and Nominal Bit ment 2 provides delay before the next transmitted data Time = 8 TQ; then TQ = 125 nsec and Nominal Bit transition and is also programmable from 1 TQ to 8 TQ in Rate = 1 Mb/s duration (however, due to IPT requirements the actual minimum length of phase segment 2 is 2 TQ, or it may be defined to be equal to the greater of phase segment 1 or EXAMPLE 17-3: CALCULATION FOR the Information Processing Time (IPT) ). FOSC = 20MHz If FOSC = 20 MHz, BRP<5:0> = 01h, and Nominal Bit 17.7.5 SAMPLE POINT Time = 8 TQ; then TQ = 200nsec and Nominal Bit The Sample Point is the point of time at which the bus Rate = 625 Kb/s level is read and value of the received bit is determined. The sampling point occurs at the end of phase segment1. If the bit timing is slow and contains many EXAMPLE 17-4: CALCULATION FOR TQ, it is possible to specify multiple sampling of the bus FOSC = 25MHz line at the sample point. The value of the received bit is If Fosc = 25 MHz, BRP<5:0> = 3Fh, and Nominal Bit determined to be the value of the majority decision of Time = 25 TQ; then TQ = 5.12 usec and Nominal Bit three values. The three samples are taken at the sam- Rate = 7.8 Kb/s ple point, and twice before with a time of TQ/2 between each sample. The frequencies of the oscillators in the different nodes 17.7.6 INFORMATION PROCESSING TIME must be coordinated in order to provide a system-wide specified nominal bit time. This means that all oscilla- The Information Processing Time (IPT) is the time seg- tors must have a TOSC that is a integral divisor of TQ. It ment, starting at the sample point, that is reserved for should also be noted that although the number of TQ is calculation of the subsequent bit level. The CAN speci- programmable from 4 to 25, the usable minimum is fication defines this time to be less than or equal to 2 TQ. 8TQ. A bit time of less than 8 TQ in length is not guar- The PIC18CXX8 defines this time to be 2 TQ. Thus, anteed to operate correctly. phase segment 2 must be at least 2 TQ long. 17.7.2 SYNCHRONIZATION SEGMENT This part of the bit time is used to synchronize the var- ious CAN nodes on the bus. The edge of the input sig- nal is expected to occur during the sync segment. The duration is 1 TQ. 17.7.3 PROPAGATION SEGMENT This part of the bit time is used to compensate for phys- ical delay times within the network. These delay times consist of the signal propagation time on the bus line and the internal delay time of the nodes. The length of the Propagation Segment can be programmed from 1TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 219

PIC18CXX8 17.8 Synchronization The phase error of an edge is given by the position of the edge relative to Sync Seg, measured in TQ. The To compensate for phase shifts between the oscillator phase error is defined in magnitude of TQ as follows: frequencies of each of the nodes on the bus, each CAN (cid:127) e = 0 if the edge lies within SYNCESEG. controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in (cid:127) e > 0 if the edge lies before the SAMPLE POINT. the transmitted data is detected, the logic will compare (cid:127) e < 0 if the edge lies after the SAMPLE POINT of the location of the edge to the expected time (Sync the previous bit. Seg). The circuit will then adjust the values of phase If the magnitude of the phase error is less than, or equal segment 1 and phase segment 2, as necessary. There to, the programmed value of the synchronization jump are two mechanisms used for synchronization. width, the effect of a resynchronization is the same as that of a hard synchronization. 17.8.1 HARD SYNCHRONIZATION If the magnitude of the phase error is larger than the Hard Synchronization is only done when there is a synchronization jump width, and if the phase error is recessive to dominant edge during a BUS IDLE condi- positive, then phase segment 1 is lengthened by an tion, indicating the start of a message. After hard syn- amount equal to the synchronization jump width. chronization, the bit time counters are restarted with If the magnitude of the phase error is larger than the Sync Seg. Hard synchronization forces the edge, which resynchronization jump width, and if the phase error is has occurred to lie within the synchronization segment negative, then phase segment 2 is shortened by an of the restarted bit time. Due to the rules of synchroni- amount equal to the synchronization jump width. zation, if a hard synchronization occurs, there will not be a resynchronization within that bit time. 17.8.3 SYNCHRONIZATION RULES 17.8.2 RESYNCHRONIZATION (cid:127) Only one synchronization within one bit time is allowed. As a result of Resynchronization, phase segment 1 may be lengthened, or phase segment 2 may be short- (cid:127) An edge will be used for synchronization only if ened. The amount of lengthening or shortening of the the value detected at the previous sample point phase buffer segments has an upper bound given by (previously read bus value) differs from the bus the Synchronization Jump Width (SJW). The value of value immediately after the edge. the SJW will be added to phase segment 1 (see (cid:127) All other recessive to dominant edges, fulfilling Figure17-7), or subtracted from phase segment 2 (see rules 1 and 2, will be used for resynchronization Figure17-8). The SJW is programmable between 1 TQ with the exception that a node transmitting a dom- and 4 TQ. inant bit will not perform a resynchronization, as a result of a recessive to dominant edge with a pos- Clocking information will only be derived from reces- itive phase error. sive to dominant transitions. The property that only a fixed maximum number of successive bits have the same value, ensures resynchronization to the bit stream during a frame. DS30475A-page 220 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 17-7: LENGTHENING A BIT PERIOD Input Signal Prop Phase Phase Sync ≤ SJW Segment Segment 1 Segment 2 Sample Nominal Actual Bit Point Bit Length Length TQ FIGURE 17-8: SHORTENING A BIT PERIOD Input Signal Prop Phase Phase Sync ≤ SJW Segment Segment 1 Segment 2 Sample Actual Nominal Point Bit Length Bit Length TQ  2000 Microchip Technology Inc. Advanced Information DS30475A-page 221

PIC18CXX8 17.9 Programming Time Segments 17.11 Bit Timing Configuration Registers Some requirements for programming of the time The configuration registers (BRGCON1, BRGCON2, segments: BRGCON3) control the bit timing for the CAN bus inter- (cid:127) Prop Seg + Phase Seg 1 ≥ Phase Seg 2 face. These registers can only be modified when the PIC18CXX8 is in Configuration mode. (cid:127) Phase Seg 2 ≥ Sync Jump Width For example, assuming that a 125 kHz CAN baud rate 17.11.1 BRGCON1 with FOSC = 20 MHz is desired: The BRP bits control the baud rate prescaler. The TOSC = 50nsec, choose BRP<5:0> = 04h, then SJW<1:0> bits select the synchronization jump width in TQ = 500nsec. To obtain 125 kHz, the bit time must be terms of number of TQ’s. 16 TQ. 17.11.2 BRGCON2 Sync Seg = 1 TQ; Prop Seg = 2 TQ; So, setting Phase Seg 1 = 7 TQ would place the sample at 10 TQ after the The PRSEG bits set the length, in TQ’s, of the propaga- transition. This would leave 6 TQ for Phase Seg 2. tion segment. The SEG1PH bits set the length, in TQ’s, Since Phase Seg 2 is 6, by the rules, SJW could be the of phase segment 1. The SAM bit controls how many maximum of 4 TQ. However, normally a large SJW is times the RXCAN pin is sampled. Setting this bit to a ‘1’ only necessary when the clock generation of the differ- causes the bus to be sampled three times; twice at ent nodes is inaccurate or unstable, such as using TQ/2 before the sample point, and once at the normal ceramic resonators. So an SJW of 1 is typically sample point (which is at the end of phase segment 1). enough. The value of the bus is determined to be the value read during at least two of the samples. If the SAM bit is set 17.10 Oscillator Tolerance to a ‘0’, then the RXCAN pin is sampled only once at the sample point. The SEG2PHTS bit controls how the The bit timing requirements allow ceramic resonators length of phase segment 2 is determined. If this bit is to be used in applications with transmission rates of up set to a ‘1’, then the length of phase segment 2 is deter- to 125 kbit/sec, as a rule of thumb. For the full bus mined by the SEG2PH bits of BRGCON3. If the speed range of the CAN protocol, a quartz oscillator is SEG2PHTS bit is set to a ‘0’, then the length of phase required. A maximum node-to-node oscillator variation segment 2 is the greater of phase segment 1 and the of 1.7% is allowed. information processing time (which is fixed at 2 TQ for the PIC18CXX8). 17.11.3 BRGCON3 The PHSEG2<2:0> bits set the length, in TQ’s, of phase segment 2, if the SEG2PHTS bit is set to a ‘1’. If the SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0> bits have no effect. DS30475A-page 222 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 17.12 Error Detection 17.12.6 ERROR STATES The CAN protocol provides sophisticated error detec- Detected errors are made public to all other nodes via tion mechanisms. The following errors can be detected. error frames. The transmission of the erroneous mes- sage is aborted and the frame is repeated as soon as 17.12.1 CRC ERROR possible. Furthermore, each CAN node is in one of the three error states “error-active”, “error-passive” or With the Cyclic Redundancy Check (CRC), the trans- “bus-off” according to the value of the internal error mitter calculates special check bits for the bit counters. The error-active state is the usual state, sequence, from the start of a frame until the end of the where the bus node can transmit messages and active data field. This CRC sequence is transmitted in the error frames (made of dominant bits), without any CRC Field. The receiving node also calculates the restrictions. In the error-passive state, messages and CRC sequence using the same formula and performs passive error frames (made of recessive bits) may be a comparison to the received sequence. If a mismatch transmitted. The bus-off state makes it temporarily is detected, a CRC error has occurred and an error impossible for the station to participate in the bus com- frame is generated. The message is repeated. munication. During this state, messages can neither be 17.12.2 ACKNOWLEDGE ERROR received nor transmitted. In the acknowledge field of a message, the transmitter 17.12.7 ERROR MODES AND ERROR COUNTERS checks if the acknowledge slot (which has sent out as The PIC18CXX8 contains two error counters: the a recessive bit) contains a dominant bit. If not, no other Receive Error Counter (RXERRCNT), and the Trans- node has received the frame correctly. An acknowl- mit Error Counter (TXERRCNT). The values of both edge error has occurred; an error frame is generated counters can be read by the MCU. These counters are and the message will have to be repeated. incremented or decremented in accordance with the 17.12.3 FORM ERROR CAN bus specification. The PIC18CXX8 is error-active if both error counters lf a node detects a dominant bit in one of the four seg- are below the error-passive limit of 128. It is ments, including end of frame, interframe space, error-passive if at least one of the error counters equals acknowledge delimiter, or CRC delimiter, then a form or exceeds 128. It goes to bus-off if the transmit error error has occurred and an error frame is generated. counter equals or exceeds the bus-off limit of 256. The The message is repeated. device remains in this state, until the bus-off recovery sequence is received. The bus-off recovery sequence 17.12.4 BIT ERROR consists of 128 occurrences of 11 consecutive reces- A Bit Error occurs if a transmitter sends a dominant bit sive bits (see Figure17-9). Note that the CAN module, and detects a recessive bit, or if it sends a recessive bit after going bus-off, will recover back to error-active, and detects a dominant bit, when monitoring the actual without any intervention by the MCU, if the bus remains bus level and comparing it to the just transmitted bit. In idle for 128 X 11 bit times. If this is not desired, the error the case where the transmitter sends a recessive bit interrupt service routine should address this. The cur- and a dominant bit is detected during the arbitration rent error mode of the CAN module can be read by the field and the acknowledge slot, no bit error is generated MCU via the COMSTAT register. because normal arbitration is occurring. Additionally, there is an error state warning flag bit, EWARN, which is set if at least one of the error 17.12.5 STUFF BIT ERROR counters equals or exceeds the error warning limit of lf, between the start of frame and the CRC delimiter, six 96. EWARN is reset if both error counters are less than consecutive bits with the same polarity are detected, the error warning limit. the bit stuffing rule has been violated. A Stuff Bit Error occurs and an error frame is generated. The message is repeated.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 223

PIC18CXX8 FIGURE 17-9: ERROR MODES STATE DIAGRAM RESET Error RXERRCNT < 127 or Active TXERRCNT < 127 128 occurrences of 11 consecutive "recessive" bits RXERRCNT > 127 or TXERRCNT > 127 Error Passive TXERRCNT > 255 Bus Off DS30475A-page 224 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 17.13 CAN Interrupts 17.13.2 TRANSMIT INTERRUPT The module has several sources of interrupts. Each of When the Transmit Interrupt is enabled, an interrupt will these interrupts can be individually enabled or dis- be generated when the associated transmit buffer abled. The CANINTF register contains interrupt flags. becomes empty and is ready to be loaded with a new The CANINTE register contains the enables for the 8 message. The TXBnIF bit will be set to indicate the main interrupts. A special set of read only bits in the source of the interrupt. The interrupt is cleared by the CANSTAT register (ICODE bits) can be used in combi- MCU resetting the TXBnIF bit to a ‘0’. nation with a jump table for efficient handling of inter- 17.13.3 RECEIVE INTERRUPT rupts. All interrupts have one source, with the exception of the When the Receive Interrupt is enabled, an interrupt will Error Interrupt. Any of the Error Interrupt sources can be generated when a message has been successfully set the Error Interrupt Flag. The source of the Error received and loaded into the associated receive buffer. Interrupt can be determined by reading the Communi- This interrupt is activated immediately after receiving the cation Status register COMSTAT. EOF field. The RXBnIF bit will be set to indicate the source of the interrupt. The interrupt is cleared by the The interrupts can be broken up into two categories: MCU resetting the RXBnIF bit to a ‘0’. receive and transmit interrupts. The receive related interrupts are: 17.13.4 MESSAGE ERROR INTERRUPT (cid:127) Receive Interrupts When an error occurs during transmission or reception (cid:127) Wake-up Interrupt of a message, the message error flag IRXIF will be set (cid:127) Receiver Overrun Interrupt and, if the IRXIE bit is set, an interrupt will be gener- (cid:127) Receiver Warning Interrupt ated. This is intended to be used to facilitate baud rate determination when used in conjunction with Listen (cid:127) Receiver Error Passive Interrupt Only mode. The Transmit related interrupts are 17.13.5 BUS ACTIVITY WAKE-UP INTERRUPT (cid:127) Transmit Interrupts (cid:127) Transmitter Warning Interrupt When the PIC18CXX8 is in SLEEP mode and the bus (cid:127) Transmitter Error Passive Interrupt activity wake-up interrupt is enabled, an interrupt will be (cid:127) Bus Off Interrupt generated, and the WAKIF bit will be set, when activity is detected on the CAN bus. This interrupt causes the 17.13.1 INTERRUPT CODE BITS PIC18CXX8 to exit SLEEP mode. The interrupt is reset by the MCU clearing the WAKIF bit. The source of a pending interrupt is indicated in the ICODE (interrupt code) bits. Interrupts are internally prioritized, such that the lower the ICODE value, the higher the interrupt priority. Once the highest priority interrupt condition has been cleared, the code for the next highest priority interrupt that is pending (if any), will be reflected by the ICODE bits (see Table17-3). Note that only those interrupt sources that have their associated CANINTE enable bit set will be reflected in the ICODE bits. TABLE 17-3: ICODE<2:0> DECODE ICODE<2:0> Boolean Expression 000 ERR(cid:127) WAK(cid:127) TX0(cid:127) TX1(cid:127) TX2(cid:127) RX0(cid:127) RX1 001 ERR 010 ERR(cid:127) WAK 011 ERR(cid:127) WAK(cid:127) TX0 100 ERR(cid:127) WAK(cid:127) TX0(cid:127) TX1 101 ERR(cid:127) WAK(cid:127) TX0(cid:127) TX1(cid:127) TX2 110 ERR(cid:127) WAK(cid:127) TX0(cid:127) TX1(cid:127) TX2(cid:127) RX0 111 ERR(cid:127) WAK(cid:127) TX0(cid:127) TX1(cid:127) TX2(cid:127) RX0(cid:127) RX1  2000 Microchip Technology Inc. Advanced Information DS30475A-page 225

PIC18CXX8 17.13.6 ERROR INTERRUPT 17.13.6.4 Receiver Bus-Passive When the error interrupt is enabled, an interrupt is gen- The receive error counter has exceeded the erated if an overflow condition occurs, or if the error error-passive limit of 127 and the device has gone to state of transmitter or receiver has changed. The Error error-passive state. Flags in COMSTAT will indicate one of the following conditions. 17.13.6.5 Transmitter Bus-Passive 17.13.6.1 Receiver Overflow The transmit error counter has exceeded the error- passive limit of 127 and the device has gone to error- An overflow condition occurs when the MAB has assem- passive state. bled a valid received message (the message meets the criteria of the acceptance filters) and the receive buffer 17.13.6.6 Bus-Off associated with the filter is not available for loading of a The transmit error counter has exceeded 255 and the new message. The associated COMSTAT.RXNOVFL bit device has gone to bus-off state. will be set to indicate the overflow condition. This bit must be cleared by the MCU. 17.13.7 INTERRUPT ACKNOWLEDGE 17.13.6.2 Receiver Warning Interrupts are directly associated with one or more sta- tus flags in the PIF register. Interrupts are pending as The receive error counter has reached the MCU warn- long as one of the flags is set. Once an interrupt flag is ing limit of 96. set by the device, the flag can not be reset by the MCU 17.13.6.3 Transmitter Warning until the interrupt condition is removed. The transmit error counter has reached the MCU warn- ing limit of 96. DS30475A-page 226 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 18.0 10-BIT ANALOG-TO-DIGITAL The A/D module has five registers: CONVERTER (A/D) MODULE (cid:127) A/D Result High Register (ADRESH) (cid:127) A/D Result Low Register (ADRESL) The analog-to-digital (A/D) converter module has twelve inputs for the PIC18C658 devices and sixteen (cid:127) A/D Control Register 0 (ADCON0) for the PIC18C858 devices. This module has the (cid:127) A/D Control Register 1 (ADCON1) ADCON0, ADCON1, and ADCON2 registers. (cid:127) A/D Control Register 2 (ADCON2) The A/D allows conversion of an analog input signal to The ADCON0 register, shown in Register18-1, con- a corresponding 10-bit digital number. trols the operation of the A/D module. The ADCON1 register, shown in Register18-2, configures the func- tions of the port pins. The ADCON2, shown in Register 16-3, configures the A/D clock source and justification. REGISTER 18-1: ADCON0 REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-2 CHS3:CHS0: Analog Channel Select bits 0000 = channel 00, (AN0) 0001 = channel 01, (AN1) 0010 = channel 02, (AN2) 0011 = channel 03, (AN3) 0100 = channel 04, (AN4) 0101 = channel 05, (AN5) 0110 = channel 06, (AN6) 0111 = channel 07, (AN7) 1000 = channel 08, (AN8) 1001 = channel 09, (AN9) 1010 = channel 10, (AN10) 1011 = channel 11, (AN11) 1100 = channel 12, (AN12)(1) 1101 = channel 13, (AN13)(1) 1110 = channel 14, (AN14)(1) 1111 = channel 15, (AN15)(1) Note 1: These channels are not available on the PIC18C658 devices. bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1 1 = A/D conversion in progress. Setting this bit starts an A/D conversion cycle. This bit is auto- matically cleared by hardware when the A/D conversion is complete. 0 = A/D conversion not in progress bit 0 ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut off and consumes no operating current Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 227

PIC18CXX8 REGISTER 18-2: ADCON1 REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits A/D VREF+ A/D VREF- 00 AVDD AVSS 01 External VREF+ AVSS 10 AVDD External VREF- 11 External VREF+ External VREF- bit 3:0 PCFG3:PCFG0: A/D Port Configuration Control bits AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 0000 A A A A A A A A A A A A A A A A 0001 D D A A A A A A A A A A A A A A 0010 D D D A A A A A A A A A A A A A 0011 D D D D A A A A A A A A A A A A 0100 D D D D D A A A A A A A A A A A 0101 D D D D D D A A A A A A A A A A 0110 D D D D D D D A A A A A A A A A 0111 D D D D D D D D A A A A A A A A 1000 D D D D D D D D D A A A A A A A 1001 D D D D D D D D D D A A A A A A 1010 D D D D D D D D D D D A A A A A 1011 D D D D D D D D D D D D A A A A 1100 D D D D D D D D D D D D D A A A 1101 D D D D D D D D D D D D D D A A 1110 D D D D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D D D D A = Analog input D = Digital I/O Shaded cells = additional A/D channels available on the PIC18C858 devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: Channels AN15 through AN12 are not available on the 68-pin devices. DS30475A-page 228 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 18-3: ADCON2 REGISTER R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 ADFM — — — — ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6-3 Unimplemented: Read as '0' bit 2-0 ADCS1:ADCS0: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from an RC oscillator = 1 MHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock derived from an RC oscillator = 1 MHz max) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 229

PIC18CXX8 The analog reference voltage is software selectable to Each port pin associated with the A/D converter can either the device’s positive and negative supply voltage be configured as an analog input (RA3 can also be a (VDD and VSS), or the voltage level on the voltage reference), or as a digital I/O. RA3/AN3/VREF+ pin and RA2/AN2/VREF-. The ADRESH and ADRESL registers contain the result The A/D converter has a unique feature of being able to of the A/D conversion. When the A/D conversion is operate while the device is in SLEEP mode. To operate complete, the result is loaded into the in SLEEP, the A/D conversion clock must be derived ADRESH/ADRESL registers, the GO/DONE bit from the A/D’s internal RC oscillator. (ADCON0 register) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is The output of the sample and hold is the input into the shown in Figure18-1. converter, which generates the result via successive approximation. A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion is aborted. FIGURE 18-1: A/D BLOCK DIAGRAM CHS3:CHS0 1111 AN15 (1) 1110 AN14 (1) 1101 AN13 (1) 1100 AN12 (1) 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7 0110 AN6 0101 AN5 0100 AN4 VAIN 10-bit (Input Voltage) 0011 AN3 Converter A/D 0010 AN2 0001 VCFG1:VCFG0 AN1 0000 AN0 VDD VREF+ Reference Voltage VREF- VSS Note 1: Channels AN15 through AN12 are not available on the PIC18C658. 2: I/O pins have diode protection to VDD and VSS. DS30475A-page 230 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 The value in the ADRESH/ADRESL registers is not 2. Configure A/D interrupt (if desired): modified for a Power-on Reset. The ADRESH/ADRESL (cid:127) Clear ADIF bit registers will contain unknown data after a Power-on (cid:127) Set ADIE bit Reset. (cid:127) Set GIE bit After the A/D module has been configured as desired, 3. Wait the required acquisition time. the selected channel must be acquired before the con- 4. Start conversion: version is started. The analog input channels must (cid:127) Set GO/DONE bit (ADCON0 register) have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section18.1. 5. Wait for A/D conversion to complete, by either: After this acquisition time has elapsed, the A/D conver- (cid:127) Polling for the GO/DONE bit to be cleared sion can be started. The following steps should be fol- OR lowed to do an A/D conversion: (cid:127) Waiting for the A/D interrupt 1. Configure the A/D module: 6. Read A/D Result registers (ADRESH:ADRESL); (cid:127) Configure analog pins, voltage reference and clear bit ADIF, if required. digital I/O (ADCON1) 7. For next conversion, go to step 1 or step 2, as (cid:127) Select A/D input channel (ADCON0) required. The A/D conversion time per bit is (cid:127) Select A/D conversion clock (ADCON2) defined as TAD. A minimum wait of 2TAD is (cid:127) Turn on A/D module (ADCON0) required before next acquisition starts. FIGURE 18-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6 V Rs ANx RIC ≤ 1 k SS RSS VAIN C5 PpIFN VT = 0.6 V I± l e5a0k0a ngAe CHOLD = 120 pF VSS Legend:CPIN = input capacitance 6V VT = threshold voltage 5V I LEAKAGE = leakage current at the pin due to VDD 4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) RSS = sampling switch resistance 5 6 7 8 9 10 11 Sampling Switch ( kΩ )  2000 Microchip Technology Inc. Advanced Information DS30475A-page 231

PIC18CXX8 18.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation18-1 may be used. This equation assumes For the A/D converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is shown in Figure18-2. The Example18-1 shows the calculation of the minimum source impedance (RS) and the internal sampling required acquisition time TACQ. This calculation is switch (RSS) impedance directly affect the time based on the following application system assump- required to charge the capacitor CHOLD. The sampling tions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 120 pF at the analog input (due to pin leakage current). The Rs = 2.5 kΩ maximum recommended impedance for analog Conversion Error ≤ 1/2 LSb sources is 2.5kΩ. After the analog input channel is VDD = 5V → Rss = 7 kΩ selected (changed), this acquisition must be done Temperature = 50°C (system max.) before the conversion can be started. VHOLD = 0V @ time = 0 Note: When the conversion is started, the hold- ing capacitor is disconnected from the input pin. EQUATION 18-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 18-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF - (VREF/2048)) (cid:127) (1 - e(-Tc/CHOLD(RIC + RSS + RS))) or Tc = -(120 pF)(1 kΩ + RSS + RS) ln(1/2047) EXAMPLE 18-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF Temperature coefficient is only required for temperatures > 25°C. TACQ = 2 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)] TC = -CHOLD (RIC + RSS + RS) ln(1/2047) -120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885) -120 pF (10.5 kΩ) ln(0.0004885) -1.26 µs (-7.6241) 9.61 µs TACQ = 2 µs + 9.61 µs + [(50°C - 25°C)(0.05 µs/°C)] 11.61 µs + 1.25 µs 12.86 µs DS30475A-page 232 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 18.2 Selecting the A/D Conversion Clock 18.3 Configuring Analog Port Pins The A/D conversion time per bit is defined as TAD. The The ADCON1, TRISA, TRISF and TRISH registers A/D conversion requires 12 TAD per 10-bit conversion. control the operation of the A/D port pins. The port pins The source of the A/D conversion clock is software needed as analog inputs must have their correspond- selectable. There are seven possible options for TAD: ing TRIS bits set (input). If the TRIS bit is cleared (out- (cid:127) 2TOSC put), the digital output level (VOH or VOL) will be converted. (cid:127) 4TOSC (cid:127) 8TOSC The A/D operation is independent of the state of the (cid:127) 16TOSC CHS3:CHS0 bits and the TRIS bits. (cid:127) 32TOSC Note 1: When reading the port register, all pins (cid:127) 64TOSC configured as analog input channels will (cid:127) Internal RC oscillator read as cleared (a low level). Pins config- For correct A/D conversions, the A/D conversion clock ured as digital inputs will convert an ana- (TAD) must be selected to ensure a minimum TAD time log input. Analog levels on a digitally of 1.6 µs. configured input will not affect the conver- Table18-1 shows the resultant TAD times derived from sion accuracy. the device operating frequencies and the A/D clock 2: Analog levels on any pin defined as a dig- source selected. ital input may cause the input buffer to consume current out of the device’s spec- ification limits. TABLE 18-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS2:ADCS0 PIC18CXX8 PIC18LCXX8(6) 2TOSC 000 1.25 MHz 666 kHz 4TOSC 100 2.50 MHz 1.33 MHz 8TOSC 001 5.00 MHz 2.67 MHz 16TOSC 101 10.0 MHz 5.33 MHz 32TOSC 010 20.0 MHz 10.67 MHz 64TOSC 110 40.0 MHz 21.33 MHz RC x11 — — Note 1: The RC source has a typical TAD time of 4 ms. 2: The RC source has a typical TAD time of 6 ms. 3: These values violate the minimum required TAD time. 4: For faster conversion times, the selection of another clock source is recommended. 5: For device frequencies above 1 MHz, the device must be in SLEEP for the entire conversion or the A/D accuracy may be out of specification. 6: This column is for the LC devices only.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 233

PIC18CXX8 18.4 A/D Conversions 18.5 Use of the CCP2 Trigger Figure18-3 shows the operation of the A/D converter An A/D conversion can be started by the “special event after the GO bit has been set. Clearing the GO/DONE trigger” of the CCP2 module. This requires that the bit during a conversion will abort the current conver- CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- sion. The A/D result register pair will NOT be updated grammed as 1011 and that the A/D module is enabled with the partially completed A/D conversion sample. (ADON bit is set). When the trigger occurs, the That is, the ADRESH:ADRESL registers will continue GO/DONE bit will be set, starting the A/D conversion, to contain the value of the last completed conversion and the Timer1 (or Timer3) counter will be reset to zero. (or the last value written to the ADRESH:ADRESL reg- Timer1 (or Timer3) is reset to automatically repeat the isters). After the A/D conversion is aborted, a 2TAD wait A/D acquisition period with minimal software overhead is required before the next acquisition is started. After (moving ADRESH/ADRESL to the desired location). this 2TAD wait, acquisition on the selected channel is The appropriate analog input channel must be selected automatically started. and the minimum acquisition done before the “special event trigger” sets the GO/DONE bit (starts a conver- Note: The GO/DONE bit should NOT be set in sion). the same instruction that turns on the A/D. If the A/D module is not enabled (ADON is cleared), the “special event trigger” will be ignored by the A/D mod- ule, but will still reset the Timer1 (or Timer3) counter. FIGURE 18-3: A/D CONVERSION TAD CYCLES Tcy - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0 Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS30475A-page 234 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 18-2: SUMMARY OF A/D REGISTERS Value on all Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR RESETS INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000 PIE2 — CMIE — — BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000 IPR2 — CMIP — — BCLIP LVDIP TMR3IP CCP2IP -0-- 0000 -0-- 0000 ADRESH A/D Result Register xxxx xxxx uuuu uuuu ADRESL A/D Result Register xxxx xxxx uuuu uuuu ADCON0 — — CHS3 CHS3 CHS1 CHS0 GO/DONE ADON 0000 00-0 0000 00-0 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 ADCON2 ADFM — — — — ADCS2 ADCS1 ADCS0 0--- -000 0--- -000 PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 TRISA — PORTA Data Direction Register --11 1111 --11 1111 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 x000 0000 u000 0000 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx uuuu uuuu TRISF PORTF Data Direction Control Register 1111 1111 1111 1111 PORTH(1) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 0000 xxxx 0000 xxxx LATH(1) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx uuuu uuuu TRISH(1) PORTH Data Direction Control Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: Only available on PIC18C858 devices.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 235

PIC18CXX8 NOTES: DS30475A-page 236 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 19.0 COMPARATOR MODULE The CMCON register, shown as Register19-1, con- trols the comparator input and output multiplexers. A The comparator module contains two analog compara- block diagram of the comparator is shown in tors. The inputs to the comparators are multiplexed Figure19-1. with the RF1 through RF6 pins. The on-chip Voltage Reference (Section20.0) can also be an input to the comparators. REGISTER 19-1: CMCON REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 Output When C2INV = 0: 1 = C2 VIN+ > C2 VIN– 0 = C2 VIN+ < C2 VIN– When C2INV = 1: 1 = C2 VIN+ < C2 VIN– 0 = C2 VIN+ > C2 VIN– bit 6 C1OUT: Comparator 1 Output When C1INV = 0: 1 = C1 VIN+ > C1 VIN– 0 = C1 VIN+ < C1 VIN– When C1INV = 1: 1 = C1 VIN+ < C1 VIN– 0 = C1 VIN+ > C1 VIN– bit 5 C2INV: Comparator 2 Output Inversion 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion 1 = C1 Output inverted 0 = C1 Output not inverted bit 3 CIS: Comparator Input Switch When CM2:CM0 = 110: 1 = C1 VIN– connects to RF5/AN10 C2 VIN– connects to RF3/AN8 0 = C1 VIN– connects to RF6/AN11 C2 VIN– connects to RF4/AN9 bit 2-0 CM2:CM0: Comparator Mode Figure19-1 shows the Comparator modes and CM2:CM0 bit settings Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 237

PIC18CXX8 19.1 Comparator Configuration mode is changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Electrical Specifications (Section25.0). tors. The CMCON register is used to select these Note: Comparator interrupts should be disabled modes. Figure19-1 shows the eight possible modes. during a Comparator mode change. Other- The TRISF register controls the data direction of the wise, a false interrupt may occur. comparator pins for each mode. If the Comparator FIGURE 19-1: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) Comparators Off CM2:CM0 = 000 CM2:CM0 = 111 RF6/AN11 A VIN- RF6/AN11 D VIN- RF5/AN10 A VIN+ C1 Off (Read as ’0’) RF5/AN10 D VIN+ C1 Off (Read as ’0’) RF4/AN9 A VIN- RF4/AN9 D VIN- RF3/AN8 A VIN+ C2 Off (Read as ’0’) RF3/AN8 D VIN+ C2 Off (Read as ’0’) Two Independent Comparators with Outputs Two Independent Comparators CM2:CM0 = 011 CM2:CM0 = 010 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10 A VIN+ C1 C1OUT RF5/AN10 A VIN+ C1 C1OUT RF2/AN7/C1OUT RF4/AN9 A VIN- RF4/AN9 A VIN- RF3/AN8 A VIN+ C2 C2OUT RF3/AN8 A VIN+ C2 C2OUT RF1/AN6/C2OUT Two Common Reference Comparators Two Common Reference Comparators with Outputs CM2:CM0 = 100 CM2:CM0 = 101 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10 A VIN+ C1 C1OUT RF5/AN10 A VIN+ C1 C1OUT RF2/AN7/C1OUT RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF1/AN6/C2OUT One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM2:CM0 = 001 CM2:CM0 = 110 RF6/AN11 A VIN- RF6/AN11 A CIS = 0 VIN- RF5/AN10 A VIN+ C1 C1OUT RF5/AN10 A CIS = 1 VIN+ C1 C1OUT RF2/AN7/C1OUT A RF4/AN9 CIS = 0 VIN- RF4/AN9 D VIN- RF3/AN8 A CIS = 1 VIN+ C2 C2OUT RF3/AN8 D VIN+ C2 Off (Read as ’0’) CVREF From VREF Module A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch. DS30475A-page 238 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 19.2 Comparator Operation 19.4 Comparator Response Time A single comparator is shown in Figure19-2 along with Response time is the minimum time, after selecting a the relationship between the analog input levels and new reference voltage or input source, before the the digital output. When the analog input at VIN+ is less comparator output has a valid level. If the internal ref- than the analog input VIN–, the output of the erence is changed, the maximum delay of the internal comparator is a digital low level. When the analog input voltage reference must be considered when using the at VIN+ is greater than the analog input VIN–, the output comparator outputs. Otherwise the maximum delay of of the comparator is a digital high level. The shaded the comparators should be used (Section25.0). areas of the output of the comparator in Figure19-2 19.5 Comparator Outputs represent the uncertainty due to input offsets and response time. The comparator outputs are read through the CMCON 19.3 Comparator Reference Register. These bits are read-only. The comparator outputs may also be directly output to the RF1 and RF2 An external or internal reference signal may be used I/O pins. When enabled, multiplexors in the output path depending on the comparator operating mode. The of the RF1 and RF2 pins will switch and the output of analog signal present at VIN– is compared to the signal each pin will be the unsynchronized output of the com- at VIN+, and the digital output of the comparator is parator. The uncertainty of each of the comparators is adjusted accordingly (Figure19-2). related to the input offset voltage and the response time given in the specifications. Figure19-3 shows the FIGURE 19-2: SINGLE COMPARATOR comparator output block diagram. The TRISA bits will still function as an output enable/disable for the RF1 and RF2 pins while in this mode. VIN+ + Output The polarity of the comparator outputs can be changed VIN– – using the C2INV and C1INV bits (CMCON<4:5>). Note 1: When reading the PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert an analog input, according to the VIVNI–N– Schmitt Trigger input specification. VIVNIN++ 2: Analog levels on any pin defined as a dig- ital input, may cause the input buffer to consume more current than is specified. Output utput 19.3.1 EXTERNAL REFERENCE SIGNAL When external voltage references are used, the comparator module can be configured to have the com- parators operate from the same, or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD, and can be applied to either pin of the comparator(s). 19.3.2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section20.0 contains a detailed descrip- tion of the Comparator Voltage Reference Module that provides this signal. The internal reference signal is used when comparators are in mode CM<2:0>=110 (Figure19-1). In this mode, the internal voltage refer- ence is applied to the VIN+ pin of both comparators.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 239

PIC18CXX8 FIGURE 19-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + - CxINV To RF1 or RF2 Pin Bus Q D Data Read CMCON EN Set CMIF Q D bit From Other EN Comparator CL Read CMCON RESET DS30475A-page 240 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 19.6 Comparator Interrupts 19.7 Comparator Operation During SLEEP The comparator interrupt flag is set whenever there is When a comparator is active and the device is placed a change in the output value of either comparator. in SLEEP mode, the comparator remains active and Software will need to maintain information about the the interrupt is functional if enabled. This interrupt will status of the output bits, as read from CMCON<7:6>, to wake-up the device from SLEEP mode, when enabled. determine the actual change that occurred. The CMIF While the comparator is powered up, higher SLEEP bit (PIR registers) is the comparator interrupt flag. The currents than shown in the power-down current CMIF bit must be RESET by clearing ‘0’. Since it is also specification will occur. Each operational comparator possible to write a '1' to this register, a simulated inter- will consume additional current, as shown in the com- rupt may be initiated. parator specifications. To minimize power consumption while in SLEEP mode, turn off the comparators, The CMIE bit (PIE registers) and the PEIE bit (INTCON CM<2:0>=111, before entering SLEEP. If the device register) must be set to enable the interrupt. In addition, wakes up from SLEEP, the contents of the CMCON the GIE bit must also be set. If any of these bits are register are not affected. clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. 19.8 Effects of a RESET . A device RESET forces the CMCON register to its Note: If a change in the CMCON register RESET state, causing the comparator module to be in (C1OUT or C2OUT) should occur when a the comparator RESET mode, CM<2:0>=000. This read operation is being executed (start of ensures that all potential inputs are analog inputs. the Q2 cycle), then the CMIF (PIR regis- Device current is minimized when analog inputs are ters) interrupt flag may not get set. present at RESET time. The comparators will be The user, in the interrupt service routine, can clear the powered down during the RESET interval. interrupt in the following manner: a) Any read or write of CMCON will end the mis- match condition. b) Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition, and allow flag bit CMIF to be cleared.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 241

PIC18CXX8 19.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure19-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6 V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10kΩ is rec- ommended for the analog sources. Any external com- ponent connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leak- age current. FIGURE 19-4: ANALOG INPUT MODEL VDD RS < 10k VT = 0.6 V RIC AIN VA C5 PpIFN VT = 0.6 V I±L5E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 19-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR RESETS CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 0000 0000 0000 0000 GIE/ PEIE/ INTCON TMR0IE INTIE RBIE TMR0IF INTIF RBIF 0000 000x 0000 000u GIEH GIEL PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000 PIE2 — CMIE — — BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000 IPR2 — CMIP — — BCLIP LVDIP TMR3IP CCP2IP -1-- 1111 -1-- 1111 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 x000 0000 u000 0000 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx uuuu uuuu TRISF PORTF Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as "0" DS30475A-page 242 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 20.0 COMPARATOR VOLTAGE 20.1 Configuring the Comparator Voltage REFERENCE MODULE Reference The Comparator Voltage Reference is a 16-tap resistor The Comparator Voltage Reference can output 16 dis- ladder network that provides a selectable voltage refer- tinct voltage levels for each range. The equations used ence. The resistor ladder is segmented to provide two to calculate the output of the Comparator Voltage Ref- ranges of CVREF values and has a power-down func- erence are as follows: tion to conserve power when the reference is not being If CVRR = 1: used. The CVRCON register controls the operation of CVREF= (CVR<3:0>/24) x CVRSRC the reference as shown in Register20-1. The block dia- If CVRR = 0: gram is given in Figure20-1. CVREF = (CVDD x 1/4) + (CVR<3:0>/32) x CVRSRC The comparator reference supply voltage can come from either VDD or VSS, or the external VREF+ and The settling time of the Comparator Voltage Reference VREF- that are multiplexed with RA3 and RA2. The must be considered when changing the CVREF output comparator reference supply voltage is controlled by (Section25.0). the CVRSS bit. REGISTER 20-1: VRCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN VROE VRR VRSS VR3 VR2 VR1 VR0 bit 7 bit 0 bit 7 VREN: Comparator Voltage Reference Enable 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 VROE: Comparator VREF Output Enable 1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin bit 5 VRR: Comparator VREF Range Selection 1 = 0.00 CVRSRC to 0.75 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size bit 4 VRSS: Comparator VREF Source Selection 1 = Comparator reference source CVRSRC = VREF+-VREF- 0 = Comparator reference source CVRSRC = VDD-VSS bit 3-0 VR3:VR0: Comparator VREF Value Selection 0 ≤ VR3:VR0 ≤ 15 When VRR = 1: CVREF = (VR<3:0>/ 24) • (CVRSRC) When VRR = 0: CVREF = 1/4 • (CVRSRC) + (VR3:VR0/ 32) • (CVRSRC) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2000 Microchip Technology Inc. Advanced Information DS30475A-page 243

PIC18CXX8 FIGURE 20-1: VOLTAGE REFERENCE BLOCK DIAGRAM VDD VREF+ CVRSS=0 CVRSS=1 16 Stages CVREN 8R R R R R CVRR 8R VRSS=0 VRSS=1 VREF- CVR3 CVREF 16-1 Analog Mux (From VRCON<3:0>) CVR0 Note: R is defined in Section25.0. DS30475A-page 244 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 20.2 Voltage Reference Accuracy/Error 20.5 Connection Considerations The full range of voltage reference cannot be realized The voltage reference module operates independently due to the construction of the module. The transistors of the comparator module. The output of the reference on the top and bottom of the resistor ladder network generator may be connected to the RF5 pin if the (Figure20-1) keep VREF from approaching the refer- TRISF<5> bit is set and the VROE bit (VRCON regis- ence source rails. The voltage reference is derived ter) is set. Enabling the voltage reference output onto from the reference source; therefore, the VREF output the RF5 pin, with an input signal present, will increase changes with fluctuations in that source. The tested current consumption. Connecting RF5 as a digital absolute accuracy of the voltage reference can be output with VRSS enabled will also increase current found in Section25.0. consumption. The RF5 pin can be used as a simple D/A output with 20.3 Operation During SLEEP limited drive capability. Due to the limited current drive When the device wakes up from SLEEP through an capability, a buffer must be used on the voltage refer- interrupt or a Watchdog Timer time-out, the contents of ence output for external connections to VREF. the VRCON register are not affected. To minimize Figure20-2 shows an example buffering technique. current consumption in SLEEP mode, the voltage reference should be disabled. 20.4 Effects of a RESET A device RESET disables the voltage reference by clearing bit VREN (VRCON register). This RESET also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON register) and selects the high volt- age range by clearing bit CVRR (VRCON register). The VRSS value select bits, CVRCON<3:0>, are also cleared. FIGURE 20-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE R(1) RF5 CVREF (cid:127) + Module (cid:127) CVREF Output – Voltage Reference Output Impedance Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>. TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Value On Value On Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR RESETS VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 0000 0000 0000 0000 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111  2000 Microchip Technology Inc. Advanced Information DS30475A-page 245

PIC18CXX8 NOTES: DS30475A-page 246 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 21.0 LOW VOLTAGE DETECT Figure21-2 shows the block diagram for the LVD mod- ule. A comparator uses an internally generated refer- In many applications, the ability to determine if the ence voltage as the set point. When the selected tap device voltage (VDD) is below a specified voltage level output of the device voltage crosses the set point (is is a desirable feature. A window of operation for the lower than), the LVDIF bit (PIR registers) is set. application can be created, where the application soft- ware can do "housekeeping tasks" before the device Each node in the resister divider represents a “trip voltage exits the valid operating range. This can be point” voltage. The “trip point” voltage is the minimum done using the Low Voltage Detect module. supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the This module is software programmable circuitry, where supply voltage is equal to the trip point, the voltage a device voltage trip point can be specified (internal ref- tapped off of the resistor array (or external LVDIN input erence voltage or external voltage input). When the pin) is equal to the voltage generated by the internal voltage of the device becomes lower than the specified voltage reference module. The comparator then gener- point, an interrupt flag is set. If the interrupt is enabled, ates an interrupt signal setting the LVDIF bit. This volt- the program execution will branch to the interrupt vec- age is software programmable to any one of 16 values tor address and the software can then respond to that (See Figure21-2). The trip point is selected by pro- interrupt source. gramming the LVDL3:LVDL0 bits (LVDCON<3:0>). The Low Voltage Detect circuitry is completely under software control. This allows the circuitry to be "turned FIGURE 21-2: LOW VOLTAGE DETECT off" by the software, which minimizes the current con- (LVD) BLOCK DIAGRAM sumption for the device. Figure21-1 shows a possible application voltage curve VDD LVDIN (typically for batteries). Over time, the device voltage LVD Control decreases. When the device voltage equals voltage Register VA, the LVD logic generates an interrupt. This occurs at time TA. The application software then has the time, until the device voltage is no longer in valid operating range, to shut down the system. Voltage point VB is the minimum valid operating voltage specification. This occurs at time TB. TB - TA is the total time for shutdown. X U FIGURE 21-1: TYPICAL LOW VOLTAGE M 1 LVDIF DETECT APPLICATION o 6 t 1 VA VB e g a LVDEN olt Internally Generated V Reference Voltage Time TA TB Legend: VA = LVD trip point VB = Minimum valid device operating range  2000 Microchip Technology Inc. Advanced Information DS30475A-page 247

PIC18CXX8 21.1 Control Register The Low Voltage Detect Control register (Register21-1) controls the operation of the Low Voltage Detect circuitry. REGISTER 21-1: LVDCON REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the spec- ified voltage range and the LVD interrupt should not be enabled bit 4 LVDEN: Low Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 3-0 LVDL3:LVDL0: Low Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.5V min - 4.77V max. 1101 = 4.2V min - 4.45V max. 1100 = 4.0V min - 4.24V max.; Reserved on PIC18CXX8 1011 = 3.8V min - 4.03V max.; Reserved on PIC18CXX8 1010 = 3.6V min - 3.82V max.; Reserved on PIC18CXX8 1001 = 3.5V min - 3.71V max.; Reserved on PIC18CXX8 1000 = 3.3V min - 3.50V max.; Reserved on PIC18CXX8 0111 = 3.0V min - 3.18V max.; Reserved on PIC18CXX8 0110 = 2.8V min - 2.97V max.; Reserved on PIC18CXX8 0101 = 2.7V min - 2.86V max.; Reserved on PIC18CXX8 0100 = 2.5V min - 2.65V max.; Reserved on PIC18CXX8 0011 = Reserved on PIC18CXX8 and PIC18LCXX8 0010 = Reserved on PIC18CXX8 and PIC18LCXX8 0001 = Reserved on PIC18CXX8 and PIC18LCXX8 0000 = Reserved on PIC18CXX8 and PIC18LCXX8 Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device are not tested. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30475A-page 248 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 21.2 Operation The following steps are needed to setup the LVD module: Depending on the power source for the device voltage, 1. Write the value to the LVDL3:LVDL0 bits the voltage normally decreases relatively slowly. This (LVDCON register), which selects the desired means that the LVD module does not need to be con- LVD Trip Point. stantly operating. To decrease current consumption, the LVD circuitry only needs to be enabled for short 2. Ensure that LVD interrupts are disabled (the periods, where the voltage is checked. After doing the LVDIE bit is cleared or the GIE bit is cleared). check, the LVD module may be disabled. 3. Enable the LVD module (set the LVDEN bit in the LVDCON register). Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has 4. Wait for the LVD module to stabilize (the IRVST bit to become set). stabilized, all status flags may be cleared. The module will then indicate the proper state of the system. 5. Clear the LVD interrupt flag, which may have falsely become set, until the LVD module has stabilized (clear the LVDIF bit). 6. Enable the LVD interrupt (set the LVDIE and the GIE bits). Figure21-3 shows typical waveforms that the LVD module may be used to detect. FIGURE 21-3: LOW VOLTAGE DETECT WAVEFORMS CASE 1: LVDIF may not be set VDD . VLVD LVDIF Enable LVD Internally Generated 50 ms Reference Stable LVDIF cleared in software CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated 50 ms Reference Stable LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists  2000 Microchip Technology Inc. Advanced Information DS30475A-page 249

PIC18CXX8 21.2.1 REFERENCE VOLTAGE SET POINT 21.4 Operation During SLEEP The Internal Reference Voltage of the LVD module may When enabled, the LVD circuitry continues to operate be used by other internal circuitry (the programmable during SLEEP. If the device voltage crosses the trip Brown-out Reset). If these circuits are disabled (lower point, the LVDIF bit will be set and the device will wake- current consumption), the reference voltage circuit up from SLEEP. Device execution will continue from requires time to become stable before a low voltage the interrupt vector address if interrupts have been glo- condition can be reliably detected. This time is invariant bally enabled. of system clock speed. This start-up time is specified in electrical specification parameter #36. The low voltage 21.5 Effects of a RESET interrupt flag will not be enabled until a stable reference A device RESET forces all registers to their RESET voltage is reached. Refer to the waveform in state. This forces the LVD module to be turned off. Figure21-3. 21.2.2 CURRENT CONSUMPTION When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static cur- rent. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B. 21.3 External Analog Voltage Input The LVD module has an additional feature that allows the user to supply the trip point voltage to the module from an external source (the LVDIN pin). The LVDIN pin is used as the trip point when the LVDL3:LVDL0 bits = ’1111’. This state connects the LVDIN pin voltage to the comparator. The other comparator input is con- nected to an internal reference voltage source. DS30475A-page 250 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 22.0 SPECIAL FEATURES OF THE SLEEP mode is designed to offer a very low current CPU Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer There are several features intended to maximize sys- Wake-up or through an interrupt. Several oscillator tem reliability, minimize cost through elimination of options are also made available to allow the part to fit external components, provide power saving operating the application. The RC oscillator option saves system modes and offer code protection: cost, while the LP crystal option saves power. A set of (cid:127) OSC Selection configuration bits are used to select various options. (cid:127) RESET 22.1 Configuration Bits - Power-on Reset (POR) - Power-up Timer (PWRT) The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various - Oscillator Start-up Timer (OST) device configurations. These bits are mapped starting - Programmable Brown-out Reset (BOR) at program memory location 300000h. (cid:127) Interrupts The user will note that address 300000h is beyond the (cid:127) Watchdog Timer (WDT) user program memory space. In fact, it belongs to the (cid:127) SLEEP configuration memory space (300000h - 3FFFFFh), (cid:127) Code Protection which can only be accessed using table reads and (cid:127) ID Locations table writes. (cid:127) In-circuit Serial Programming PIC18CXX8 devices have a Watchdog Timer, which is permanently enabled via the configuration bits or it can be software-controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer nec- essary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay on power-up only, designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. TABLE 22-1: CONFIGURATION BITS AND DEVICE ID’S Default/ Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300000h CONFIG1L CP CP CP CP CP CP CP CP 1111 1111 300001h CONFIG1H r r OSCSEN — — FOSC2 FOSC1 FOSC0 111- -111 300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN ---- 1111 300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111 300006h CONFIG4L — — — — — — r STVREN ---- --11 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 1111 1111 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Grayed cells are unimplemented, read as ’0’.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 251

PIC18CXX8 REGISTER 22-1: CONFIGURATION REGISTER 1 LOW (CONFIG1L: BYTE ADDRESS 0x300000) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP CP CP CP CP CP CP CP bit 7 bit 0 bit 7-0 CP: Code Protection bits (apply when in Code Protected Microcontroller mode) 1 = Program memory code protection off 0 = All of program memory code protected Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 22-2: CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 0x300001) R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 Reserved Reserved OSCSEN — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7-6 Reserved: Maintain this bit set bit 5 OSCSEN: Oscillator System Clock Switch Enable bit 1 = Oscillator system clock switch option is disabled (Main oscillator is source) 0 = Oscillator system clock switch option is enabled (Oscillator switching is enabled) bit 4-3 Unimplemented: Read as ’0’ bit 2-0 FOSC2:FOSC0: Oscillator Selection bits 111 = RC oscillator w/ OSC2 configured as RA6 110 = HS4 oscillator with PLL enabled/Clock frequency = (4 x Fosc) 101 = EC oscillator w/ OSC2 configured as RA6 100 = EC oscillator w/ OSC2 configured as divide by 4 clock output 011 = RC oscillator 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS30475A-page 252 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 REGISTER 22-3: CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 0x300002) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOREN PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ’0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 =VBOR set to 2.5V 10 =VBOR set to 2.7V 01 =VBOR set to 4.2V 00 =VBOR set to 4.5V bit 1 BOREN: Brown-out Reset Enable bit(1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 0 PWRTEN: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT), regardless of the value of bit PWRTEN. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 22-4: CONFIGURATION REGISTER 2 HIGH (CONFIG2H: BYTE ADDRESS 0x300003) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ’0’ bit 3-1 WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits 000 = 1:128 001 = 1:64 010 = 1:32 011 = 1:16 100 = 1:8 101 = 1:4 110 = 1:2 111 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state  2000 Microchip Technology Inc. Advanced Information DS30475A-page 253

PIC18CXX8 REGISTER 22-5: CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 0x300006) U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 — — — — — — Reserved STVREN bit 7 bit 0 bit 7-2 Unimplemented: Read as ’0’ bit 1 Reserved: Maintain this bit set bit 0 STVREN: Stack Full/Underflow RESET Enable bit 1 = Stack Full/Underflow will cause RESET 0 = Stack Full/Underflow will not cause RESET Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS30475A-page 254 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 22.2 Watchdog Timer (WDT) The WDT time-out period values may be found in the Electrical Specifications section under parameter #31. The Watchdog Timer is a free running on-chip RC oscil- Values for the WDT postscaler may be assigned using lator, which does not require any external components. the configuration bits. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler if assigned to even if the clock on the OSC1/CLKI and OSC2/CLKO/RA6 pins of the device has been stopped; the WDT, and prevent it from timing out for example, by execution of a SLEEP instruction. and generating a device RESET condition. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is Note: When a CLRWDT instruction is executed in SLEEP mode, a WDT time-out causes the device to and the prescaler is assigned to the WDT, wake-up and continue with normal operation (Watch- the prescaler count will be cleared, but the dog Timer Wake-up). The TO bit in the RCON register prescaler assignment is not changed. will be cleared upon a WDT time-out. 22.2.1 CONTROL REGISTER The Watchdog Timer is enabled/disabled by a device configuration bit. If the WDT is enabled, software exe- Register22-6 shows the WDTCON register. This is a cution may not disable this function. When the WDTEN readable and writable register, which contains a control configuration bit is cleared, the SWDTEN bit bit that allows software to override the WDT enable enables/disables the operation of the WDT. configuration bit, only when the configuration bit has disabled the WDT. REGISTER 22-6: WDTCON REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN bit 7 bit 0 bit 7-1 Unimplemented: Read as ’0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is turned off if the WDTEN configuration bit in the configuration register = ’0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR  2000 Microchip Technology Inc. Advanced Information DS30475A-page 255

PIC18CXX8 22.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming, by the value written to the CONFIG2H configuration register. FIGURE 22-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 8 8 - to - 1 MUX WDTPS2:WDTPS0 WDTEN SWDTEN bit Configuration bit WDT Time-out Note: WDPS2:WDPS0 are bits in a configuration register. TABLE 22-2: SUMMARY OF WATCHDOG TIMER REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONFIG2H — — — — WDTPS2 WDTPS2 WDTPS0 WDTEN RCON IPEN LWRT — RI TO PD POR BOR WDTCON — — — — — — — SWDTEN Legend: Shaded cells are not used by the Watchdog Timer. DS30475A-page 256 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 22.3 Power-down Mode (SLEEP) The following peripheral interrupts can wake the device from SLEEP: Power-down mode is entered by executing a SLEEP 1. PSP read or write. instruction. 2. TMR1 interrupt. Timer1 must be operating as Upon entering into Power-down mode, the following an asynchronous counter. actions are performed: 3. TMR3 interrupt. Timer3 must be operating as 1. Watchdog Timer is cleared and kept running. an asynchronous counter. 2. PD bit in RCON register is cleared. 4. CCP Capture mode interrupt. 3. TO bit in RCON register is set. 5. Special event trigger (Timer1 in Asynchronous 4. Oscillator driver is turned off. mode using an external clock). 5. I/O ports maintain the status they had before the 6. MSSP (START/STOP) bit detect interrupt. SLEEP instruction was executed. 7. MSSP transmit or receive in Slave mode To achieve lowest current consumption, follow these (SPI/I2C). steps before switching to Power-down mode: 8. USART RX or TX (Synchronous Slave mode). 1. Place all I/O pins at either VDD or VSS and 9. A/D conversion (when A/D clock source is RC). ensure no external circuitry is drawing current 10. Activity on CAN bus receive line. from I/O pin. Other peripherals cannot generate interrupts, since 2. Power-down A/D and external clocks. during SLEEP, no on-chip clocks are present. 3. Pull all hi-impedance inputs to high or low External MCLR Reset will cause a device RESET. All externally. other events are considered a continuation of program 4. Place T0CKI at VSS or VDD. execution and will cause a "wake-up". The TO and PD 5. Current consumption by PORTB on-chip bits in the RCON register can be used to determine the pull-ups should be taken into account and dis- cause of the device RESET. The PD bit, which is set on abled if necessary. power-up, is cleared when SLEEP is invoked. The TO bit is cleared, if a WDT time-out occurred (and caused The MCLR pin must be at a logic high level (VIHMC). wake-up). 22.3.1 WAKE-UP FROM SLEEP When the SLEEP instruction is being executed, the next instruction (PC + 2) is pre-fetched. For the device to The device can wake-up from SLEEP through one of wake-up through an interrupt event, the corresponding the following events: interrupt enable bit must be set (enabled). Wake-up is 1. External RESET input on MCLR pin. regardless of the state of the GIE bit. If the GIE bit is 2. Watchdog Timer Wake-up (if WDT was clear (disabled), the device continues execution at the enabled). instruction after the SLEEP instruction. If the GIE bit is 3. Interrupt from INT pin, RB port change or a set (enabled), the device executes the instruction after Peripheral Interrupt. the SLEEP instruction and then branches to the inter- rupt address. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 257

PIC18CXX8 22.3.2 WAKE-UP USING INTERRUPTS Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to When global interrupts are disabled (GIE cleared) and become set before the SLEEP instruction completes. To any interrupt source has both its interrupt enable bit determine whether a SLEEP instruction executed, test and interrupt flag bit set, one of the following will occur: the PD bit. If the PD bit is set, the SLEEP instruction (cid:127) If an interrupt condition (interrupt flag bit and inter- was executed as a NOP. rupt enable bits are set) occurs before the execu- To ensure that the WDT is cleared, a CLRWDT instruc- tion of a SLEEP instruction, the SLEEP instruction tion should be executed before a SLEEP instruction. will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. (cid:127) If the interrupt condition occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. FIGURE 22-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTIF bit Interrupt Latency(3) GIEH bit Processor in SLEEP INSTRUCTION FLOW PC PC PC+2 PC+4 PC+4 PC + 4 0008h 000Ah Ifnestctrhuecdtion Inst(PC) = SLEEP Inst(PC + 2) Inst(PC + 4) Inst(0008h) Inst(000Ah) Ienxsetrcuuctetidon Inst(PC - 1) SLEEP Inst(PC + 2) Dummy cycle Dummy cycle Inst(0008h) Note 1: XT, HS or LP oscillator mode assumed. 2: GIE set is assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE is cleared, execution will continue in-line. 3: TOST = 1024TOSC (drawing not to scale). This delay will not occur for RC and EC osc modes. 4: CLKOUT is not available in these oscillator modes, but shown here for timing reference. DS30475A-page 258 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 22.4 Program Verification/Code Protection 22.6 In-Circuit Serial Programming If the code protection bit(s) have not been pro- PIC18CXX8 microcontrollers can be serially pro- grammed, the on-chip program memory can be read grammed while in the end application circuit. This is out for verification purposes. simply done with two lines for clock and data, and three other lines for power, ground and the programming Note: Microchip Technology does not recom- voltage. This allows customers to manufacture boards mend code protecting windowed devices. with unprogrammed devices, and then program the 22.5 ID Locations microcontroller just before shipping the product. This also allows the most recent firmware or a custom firm- Five memory locations (200000h - 200004h) are desig- ware to be programmed. nated as ID locations, where the user can store check- 22.7 Device ID Bits sum or other code identification numbers. These locations are accessible during normal execution Device ID bits are located in program memory at through the TBLRD instruction, or during program/ver- 3FFFFEh and 3FFFFFh. The Device ID bits are used ify. The ID locations can be read when the device is by programmers to retrieve part number and revision code protected. information about a device. These registers may also be accessed using a TBLRD instruction (Register22-8 and Register22-7). REGISTER 22-7: DEVID1 ID REGISTER FOR THE PIC18CXX8 DEVICE (0x3FFFFE) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits These bits are used with the DEV10:DEV3 bits in the Device ID register 2 to identify the part number bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the revision of the device Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Unprogrammed Value (x = unknown) REGISTER 22-8: DEVID2 ID REGISTER FOR THE PIC18CXX8 DEVICE (0x3FFFFF) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID register 1 to identify the part number Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Unprogrammed Value (x = unknown)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 259

PIC18CXX8 NOTES: DS30475A-page 260 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 23.0 INSTRUCTION SET SUMMARY The control instructions may use some of the following operands: The PIC18CXX8 instruction set adds many enhance- ments to the previous PICmicro® instruction sets, while (cid:127) A program memory address (specified by the maintaining an easy migration from these PICmicro value of ’n’) instruction sets. (cid:127) The mode of the Call or Return instructions (spec- ified by the value of ’s’) Most instructions are a single program memory word (cid:127) The mode of the Table Read and Table Write (16-bits), but there are three instructions that require instructions (specified by the value of ’m’) two program memory locations. (cid:127) No operand required Each single word instruction is a 16-bit word divided (specified by the value of ’—’) into an OPCODE, which specifies the instruction type All instructions are a single word, except for four double and one or more operands, which further specify the word instructions. These three instructions were made operation of the instruction. double word instructions so that all the required infor- The instruction set is highly orthogonal and is grouped mation is available in these 32-bits. In the second word, into four basic categories: the 4-MSb’s are 1’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. (cid:127) Byte-oriented operations (cid:127) Bit-oriented operations All single word instructions are executed in a single (cid:127) Literal operations instruction cycle, unless a conditional test is true or the (cid:127) Control operations program counter is changed as a result of the instruc- tion. In these cases, the execution takes two instruction The PIC18CXX8 instruction set summary in cycles with the additional instruction cycle(s) executed Table23-2 lists byte-oriented, bit-oriented, literal as a NOP. and control operations. Table23-1 shows the opcode field descriptions. The double word instructions execute in two instruction cycles. Most byte-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. 1. The file register (specified by the value of ’f’) Thus, for an oscillator frequency of 4 MHz, the normal 2. The destination of the result instruction execution time is 1 µs. If a conditional test is (specified by the value of ’d’) true or the program counter is changed as a result of an 3. The accessed memory instruction, the instruction execution time is 2 µs. Two (specified by the value of ’a’) word branch instructions (if true) would take 3 µs. 'f' represents a file register designator and 'd' repre- Figure23-1 shows the general formats that the instruc- sents a destination designator. The file register desig- tions can have. nator specifies which file register is to be used by the All examples use the following format to represent a instruction. hexadecimal number: The destination designator specifies where the result of 0xhh the operation is to be placed. If 'd' is zero, the result is placed in the WREG register. If 'd' is one, the result is where h signifies a hexadecimal digit. placed in the file register specified in the instruction. The Instruction Set Summary, shown in Table23-2, All bit-oriented instructions have three operands: lists the instructions recognized by the Microchip assembler (MPASMTM). 1. The file register (specified by the value of ’f’) 2. The bit in the file register Section23.1 provides a description of each instruction. (specified by the value of ’b’) 3. The accessed memory (specified by the value of ’a’) 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' rep- resents the number of the file in which the bit is located. The literal instructions may use some of the following operands: (cid:127) A literal value to be loaded into a file register (specified by the value of ’k’) (cid:127) The desired FSR register to load the literal value into (specified by the value of ’f’) (cid:127) No operand required (specified by the value of ’—’)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 261

PIC18CXX8 TABLE 23-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register ACCESS ACCESS = 0: RAM access bit symbol BANKED BANKED = 1: RAM access bit symbol bbb Bit address within an 8-bit file register (0 to 7) BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit; d = 0: store result in WREG, d = 1: store result in file register f. dest Destination either the WREG register or the specified register file location f 8-bit Register file address (0x00 to 0xFF) f 12-bit Register file address (0x000 to 0xFFF). This is the source address. s f 12-bit Register file address (0x000 to 0xFFF). This is the destination address. d k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) label Label name mm The mode of the TBLPTR register for the Table Read and Table Write instructions Only used with Table Read and Table Write instructions: * No Change to register (such as TBLPTR with Table reads and writes) *+ Post-Increment register (such as TBLPTR with Table reads and writes) *- Post-Decrement register (such as TBLPTR with Table reads and writes) +* Pre-Increment register (such as TBLPTR with Table reads and writes) n The relative address (2’s complement number) for relative branch instructions, or the direct address for Call/Branch and Return instructions PRODH Product of Multiply high byte (Register at address 0xFF4) PRODL Product of Multiply low byte (Register at address 0xFF3) s Fast Call / Return mode select bit. s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) u Unused or Unchanged (Register at address 0xFE8) W W = 0: Destination select bit symbol WREG Working register (accumulator) (Register at address 0xFE8) x Don't care (0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a Program Memory location) (Register at address 0xFF6) TABLAT 8-bit Table Latch (Register at address 0xFF5) TOS Top-of-Stack PC Program Counter PCL Program Counter Low Byte (Register at address 0xFF9) PCH Program Counter High Byte PCLATH Program Counter High Byte Latch (Register at address 0xFFA) PCLATU Program Counter Upper Byte Latch (Register at address 0xFFB) GIE Global Interrupt Enable bit WDT Watchdog Timer TO Time-out bit PD Power-down bit C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative [ ] Optional ( ) Contents → Assigned to < > Register bit field ∈ In the set of italics User defined term (font is courier) DS30475A-page 262 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 23-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select Bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select Bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 0x7F k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 CALL MYFUNC OPCODE S n<7:0> (literal) 15 12 11 0 11 1 1 n<19:8> (literal) S = Fast bit 15 11 10 0 BRA MYFUNC OPCODE n<10:0> (literal) 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC 15 6 4 0 LFSR FSR0, 0x100 OPCODE f k (literal) 15 11 7 0 1111 0 0 0 0 k (literal)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 263

PIC18CXX8 TABLE 23-2: PIC18CXX8 INSTRUCTION SET Mnemonic, 16-Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f [,d] [,a] Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2, 6 ADDWFC f [,d] [,a] Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2, 6 ANDWF f [,d] [,a] AND WREG with f 1 0001 01da ffff ffff Z, N 1,2, 6 CLRF f [,a] Clear f 1 0110 101a ffff ffff Z 2, 6 COMF f [,d] [,a] Complement f 1 0001 11da ffff ffff Z, N 1, 2, 6 CPFSEQ f [,a] Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4, 6 CPFSGT f [,a] Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4, 6 CPFSLT f [,a] Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2, 6 DECF f [,d] [,a] Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4, 6 DECFSZ f [,d] [,a] Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4, 6 DCFSNZ f [,d] [,a] Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2, 6 INCF f [,d] [,a] Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4, 6 INCFSZ f [,d] [,a] Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4, 6 INFSNZ f [,d] [,a] Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2, 6 IORWF f [,d] [,a] Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2, 6 MOVF f [,d] [,a] Move f 1 0101 00da ffff ffff Z, N 1, 6 MOVFF f , f Move f (source) to 1st word 2 1100 ffff ffff ffff None s d s f (destination)2nd word 1111 ffff ffff ffff d MOVWF f [,a] Move WREG to f 1 0110 111a ffff ffff None 6 MULWF f [,a] Multiply WREG with f 1 0000 001a ffff ffff None 6 NEGF f [,a] Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N 1, 2, 6 RLCF f [,d] [,a] Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 6 RLNCF f [,d] [,a] Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N 1, 2, 6 RRCF f [,d] [,a] Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N 6 RRNCF f [,d] [,a] Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N 6 SETF f [,a] Set f 1 0110 100a ffff ffff None 6 SUBFWB f [,d] [,a] Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N 1, 2, 6 borrow SUBWF f [,d] [,a] Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 6 SUBWFB f [,d] [,a] Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N 1, 2, 6 borrow SWAPF f [,d] [,a] Swap nibbles in f 1 0011 10da ffff ffff None 4, 6 TSTFSZ f [,a] Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2, 6 XORWF f [,d] [,a] Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N 6 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b [,a] Bit Clear f 1 1001 bbba ffff ffff None 1, 2, 6 BSF f, b [,a] Bit Set f 1 1000 bbba ffff ffff None 1, 2, 6 BTFSC f, b [,a] Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4, 6 BTFSS f, b [,a] Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4, 6 BTG f [,d] [,a] Bit Toggle f 1 0111 bbba ffff ffff None 1, 2, 6 Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ’0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. 6: Microchip Assembler MASM automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’ according to address of register being used. DS30475A-page 264 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 23-2: PIC18CXX8 INSTRUCTION SET (CONTINUED) Mnemonic, 16-Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 2 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 1 (2) 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call subroutine1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to address1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation (Note 4) 1 1111 xxxx xxxx xxxx None POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software device RESET 1 0000 0000 1111 1111 All RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. 6: Microchip Assembler MASM automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’ according to address of register being used.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 265

PIC18CXX8 TABLE 23-2: PIC18CXX8 INSTRUCTION SET (CONTINUED) Mnemonic, 16-Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Load FSR(f) with a 12-bit 2 1110 1110 00ff kkkk None literal (k) 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 (5) 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ’0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. 6: Microchip Assembler MASM automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’ according to address of register being used. DS30475A-page 266 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 23.1 Instruction Set ADDLW ADD literal to W ADDWF ADD W to f Syntax: [ label ] ADDLW k Syntax: [ label ] ADDWF f [,d] [,a] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 Operation: (WREG) + k → WREG d ∈ [0,1] a ∈ [0,1] Status Affected: N,OV, C, DC, Z Operation: (WREG) + (f) → dest Encoding: 0000 1111 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of WREG are added Encoding: 0010 01da ffff ffff to the 8-bit literal ’k’ and the result is placed in WREG. Description: Add WREG to register ’f’. If ’d’ is 0, the result is stored in WREG. If ’d’ Words: 1 is 1, the result is stored back in reg- Cycles: 1 ister 'f' (default). If ’a’ is 0, the Q Cycle Activity: Access Bank will be selected. If ’a’ is 1, the Bank will be selected as Q1 Q2 Q3 Q4 per the BSR value. Decode Read Process Write to W literal ’k’ Data Words: 1 Cycles: 1 Example: ADDLW 0x15 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 WREG = 0x10 Decode Read Process Write to N = ? register ’f’ Data destination OV = ? C = ? DC = ? Example: ADDWF REG, W Z = ? Before Instruction After Instruction WREG = 0x17 WREG = 0x25 REG = 0xC2 N = 0 N = ? OV = 0 OV = ? C = 0 C = ? DC = 0 DC = ? Z = 0 Z = ? After Instruction WREG = 0xD9 REG = 0xC2 N = 1 OV = 0 C = 0 DC = 0 Z = 0  2000 Microchip Technology Inc. Advanced Information DS30475A-page 267

PIC18CXX8 ADDWFC ADD WREG and Carry bit to f ANDLW AND literal with WREG Syntax: [ label ] ADDWFC f [ ,d [,a] ] Syntax: [ label ] ANDLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (WREG) .AND. k → WREG Operation: (WREG) + (f) + (C) → dest Status Affected: N,Z Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of WREG are AND’ed Encoding: 0010 00da ffff ffff with the 8-bit literal 'k'. The result is Description: Add WREG, the Carry Flag and data placed in WREG. memory location ’f’. If ’d’ is 0, the Words: 1 result is placed in WREG. If ’d’ is 1, the result is placed in data memory Cycles: 1 location 'f'. If ’a’ is 0, the Access Q Cycle Activity: Bank will be selected. If ’a’ is 1, the Q1 Q2 Q3 Q4 Bank will be selected as per the BSR value. Decode Read literal Process Write to W ’k’ Data Words: 1 Cycles: 1 Example: ANDLW 0x5F Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 WREG = 0xA3 Decode Read Process Write to N = ? register ’f’ Data destination Z = ? After Instruction Example: ADDWFC REG, W WREG = 0x03 N = 0 Before Instruction Z = 0 C = 1 REG = 0x02 WREG = 0x4D N = ? OV = ? DC = ? Z = ? After Instruction C = 0 REG = 0x02 WREG = 0x50 N = 0 OV = 0 DC = 0 Z = 0 DS30475A-page 268 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 ANDWF AND WREG with f BC Branch if Carry Syntax: [ label ] ANDWF f [ ,d [,a] ] Syntax: [ label ] BC n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 d ∈ [0,1] Operation: if carry bit is ’1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (WREG) .AND. (f) → dest Status Affected: None Status Affected: N,Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ’1’, then the pro- Description: The contents of WREG are AND’ed gram will branch. with register 'f'. If 'd' is 0, the result The 2’s complement number ’2n’ is is stored in WREG. If 'd' is 1, the added to the PC. Since the PC will result is stored back in register 'f' have incremented to fetch the next (default). If ’a’ is 0, the Access instruction, the new address will be Bank will be selected. If ’a’ is 1, the PC+2+2n. This instruction is then bank will be selected as per the a two-cycle instruction. BSR value. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1 Q Cycle Activity: Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process Write to PC register ’f’ Data destination ’n’ Data No No No No Example: ANDWF REG, W operation operation operation operation If No Jump: Before Instruction WREG = 0x17 Q1 Q2 Q3 Q4 REG = 0xC2 Decode Read literal Process No N = ? ’n’ Data operation Z = ? After Instruction Example: HERE BC 5 WREG = 0x02 Before Instruction REG = 0xC2 N = 0 PC = address (HERE) Z = 0 After Instruction If Carry = 1; PC = address (HERE+12) If Carry = 0; PC = address (HERE+2)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 269

PIC18CXX8 BCF Bit Clear f BN Branch if Negative Syntax: [ label ] BCF f, b [,a] Syntax: [ label ] BN n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b ≤ 7 Operation: if negative bit is ’1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: 0 → f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ’1’, then the Description: Bit 'b' in register 'f' is cleared. If ’a’ program will branch. is 0, the Access Bank will be The 2’s complement number ’2n’ is selected, overriding the BSR value. added to the PC. Since the PC will If ’a’ = 1, the Bank will be selected have incremented to fetch the next as per the BSR value. instruction, the new address will be Words: 1 PC+2+2n. This instruction is then a two-cycle instruction. Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1(2) Q1 Q2 Q3 Q4 Decode Read Process Write Q Cycle Activity: register ’f’ Data register ’f’ If Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7 Decode Read literal Process Write to PC ’n’ Data Before Instruction No No No No FLAG_REG = 0xC7 operation operation operation operation After Instruction If No Jump: FLAG_REG = 0x47 Q1 Q2 Q3 Q4 Decode Read literal Process No ’n’ Data operation Example: HERE BN Jump Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE+2) DS30475A-page 270 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC n Syntax: [ label ] BNN n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if carry bit is ’0’ Operation: if negative bit is ’0’ (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ’0’, then the pro- Description: If the Negative bit is ’0’, then the gram will branch. program will branch. The 2’s complement number ’2n’ is The 2’s complement number ’2n’ is added to the PC. Since the PC will added to the PC. Since the PC will have incremented to fetch the next have incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then PC+2+2n. This instruction is then a two-cycle instruction. a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ’n’ Data ’n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ’n’ Data operation ’n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE+2) PC = address (HERE+2)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 271

PIC18CXX8 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV n Syntax: [ label ] BNZ n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if overflow bit is ’0’ Operation: if zero bit is ’0’ (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ’0’, then the Description: If the Zero bit is ’0’, then the pro- program will branch. gram will branch. The 2’s complement number ’2n’ is The 2’s complement number ’2n’ is added to the PC. Since the PC will added to the PC. Since the PC will have incremented to fetch the next have incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then PC+2+2n. This instruction is then a two-cycle instruction. a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ’n’ Data ’n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ’n’ Data operation ’n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE+2) PC = address (HERE+2) DS30475A-page 272 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA n Syntax: [ label ] BSF f, b [,a] Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255 Operation: (PC) + 2 + 2n → PC 0 ≤ b ≤ 7 a ∈ [0,1] Status Affected: None Operation: 1 → f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number Encoding: 1000 bbba ffff ffff ’2n’ to the PC. Since the PC will have incremented to fetch the next Description: Bit 'b' in register 'f' is set. If ’a’ is 0 instruction, the new address will be Access Bank will be selected, over- PC+2+2n. This instruction is a two- riding the BSR value. If ’a’ is 1, the cycle instruction. Bank will be selected as per the BSR value (default). Words: 1 Words: 1 Cycles: 2 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process Write to PC Q1 Q2 Q3 Q4 ’n’ Data Decode Read Process Write No No No No register ’f’ Data register ’f’ operation operation operation operation Example: BSF FLAG_REG, 7, 1 Example: HERE BRA Jump Before Instruction FLAG_REG = 0x0A Before Instruction PC = address (HERE) After Instruction FLAG_REG = 0x8A After Instruction PC = address (Jump)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 273

PIC18CXX8 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f, b [,a] Syntax: [ label ] BTFSS f, b [,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 0 ≤ b < 7 a ∈ [0,1] a ∈ [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit 'b' in register ’f' is 0, then the Description: If bit 'b' in register 'f' is 1 then the next next instruction is skipped. instruction is skipped. If bit 'b' is 0, then the next instruction If bit 'b' is 1, then the next instruction fetched during the current instruction fetched during the current instruc- execution is discarded, and a NOP is tion execution, is discarded and an executed instead, making this a two- NOP is executed instead, making this cycle instruction. If ’a’ is 0, the a two-cycle instruction. If ’a’ is 0, the Access Bank will be selected, over- Access Bank will be selected, over- riding the BSR value. If ’a’ is 1, the riding the BSR value. If ’a’ is 1, the Bank will be selected as per the BSR Bank will be selected as per the BSR value. value. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note:3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ’f’ Data operation register ’f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, ACCESS Example: HERE BTFSS FLAG, 1, ACCESS FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS30475A-page 274 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f, b [,a] Syntax: [ label ] BOV n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b < 7 Operation: if overflow bit is ’1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (f<b>) → f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ’1’, then the Description: Bit ’b’ in data memory location ’f’ is program will branch. inverted. If ’a’ is 0, the Access Bank The 2’s complement number ’2n’ is will be selected, overriding the BSR added to the PC. Since the PC will value. If ’a’ is 1, the Bank will be have incremented to fetch the next selected as per the BSR value. instruction, the new address will be Words: 1 PC+2+2n. This instruction is then a two-cycle instruction. Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1(2) Q1 Q2 Q3 Q4 Decode Read Process Write Q Cycle Activity: register ’f’ Data register ’f’ If Jump: Q1 Q2 Q3 Q4 Example: BTG PORTC, 4 Decode Read literal Process Write to PC ’n’ Data Before Instruction: No No No No PORTC = 0111 0101 [0x75] operation operation operation operation After Instruction: If No Jump: PORTC = 0110 0101 [0x65] Q1 Q2 Q3 Q4 Decode Read literal Process No ’n’ Data operation Example: HERE BOV Jump Before Instruction PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE+2)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 275

PIC18CXX8 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ n Syntax: [ label ] CALL k [,s] Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: if Zero bit is ’1’ (PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS, k → PC<20:1>, Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (WREG) → WS, Description: If the Zero bit is ’1’, then the pro- (STATUS) → STATUSS, gram will branch. (BSR) → BSRS The 2’s complement number ’2n’ is Status Affected: None added to the PC. Since the PC will Encoding: have incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 PC+2+2n. This instruction is then a two-cycle instruction. Description: Subroutine call of entire 2M byte memory range. First, return Words: 1 address (PC+ 4) is pushed onto the Cycles: 1(2) return stack. If ’s’ = 1, the WREG, STATUS and BSR registers are Q Cycle Activity: also pushed into their respective If Jump: shadow registers, WS, STATUSS Q1 Q2 Q3 Q4 and BSRS. If 's' = 0, no update Decode Read literal Process Write to PC occurs (default). Then the 20-bit ’n’ Data value ’k’ is loaded into PC<20:1>. No No No No CALL is a two-cycle instruction. operation operation operation operation If No Jump: Words: 2 Q1 Q2 Q3 Q4 Cycles: 2 Decode Read literal Process No Q Cycle Activity: ’n’ Data operation Q1 Q2 Q3 Q4 Decode Read literal Push PC to Read literal Example: HERE BZ Jump ’k’<7:0>, stack ’k’<19:8>, Before Instruction Write to PC PC = address (HERE) No No No No operation operation operation operation After Instruction If Zero = 1; PC = address (Jump) Example: HERE CALL THERE, FAST If Zero = 0; Before Instruction PC = address (HERE+2) PC = Address(HERE) After Instruction PC = Address(THERE) TOS = Address (HERE + 4) WS = WREG BSRS = BSR STATUSS = STATUS DS30475A-page 276 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: [label] CLRF f [,a] Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: 000h → WDT, Operation: 000h → f 000h → WDT postscaler, 1 → Z 1 → TO, 1 → PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. If ’a’ is 0, the Access Bank Description: CLRWDT instruction resets the will be selected, overriding the BSR Watchdog Timer. It also resets the value. If ’a’ is 1, the Bank will be postscaler of the WDT. Status bits selected as per the BSR value. TO and PD are set. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write Decode No Process No register ’f’ Data register ’f’ operation Data operation Example: CLRF FLAG_REG Example: CLRWDT Before Instruction Before Instruction FLAG_REG = 0x5A WDT counter = ? Z = ? WDT postscaler = ? TO = ? After Instruction PD = ? FLAG_REG = 0x00 Z = 0 After Instruction WDT counter = 0x00 WDT postscaler = 0 TO = 1 PD = 1  2000 Microchip Technology Inc. Advanced Information DS30475A-page 277

PIC18CXX8 Compare f with WREG, CPFSEQ COMF Complement f skip if f = WREG Syntax: [ label ] COMF f [ ,d [,a] ] Syntax: [ label ] CPFSEQ f [,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (WREG), Operation: skip if (f) = (WREG) (f) → dest (unsigned comparison) Status Affected: N,Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ’f’ are com- Description: Compares the contents of data plemented. If ’d’ is 0 the result is memory location 'f' to the contents stored in W. If ’d’ is 1 the result is of W by performing an unsigned stored back in register ’f’ (default). subtraction. If ’a’ is 0, the Access Bank will be If 'f' = WREG, then the fetched selected, overriding the BSR value. instruction is discarded and an NOP If ’a’ is 1, the Bank will be selected is executed instead making this a as per the BSR value. two-cycle instruction. If ’a’ is 0, the Words: 1 Access Bank will be selected, over- riding the BSR value. If ’a’ is 1, the Cycles: 1 Bank will be selected as per the Q Cycle Activity: BSR value. Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1(2) register ’f’ Data destination Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Example: COMF REG Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 0x13 register ’f’ Data operation N = ? If skip: Z = ? Q1 Q2 Q3 Q4 After Instruction REG = 0x13 No No No No WREG = 0xEC operation operation operation operation N = 1 If skip and followed by 2-word instruction: Z = 0 Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG NEQUAL : EQUAL : Before Instruction PC Address = HERE WREG = ? REG = ? After Instruction If REG = WREG; PC = Address (EQUAL) If REG ≠ WREG; PC = Address (NEQUAL) DS30475A-page 278 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 Compare f with WREG, Compare f with WREG, CPFSGT CPFSLT skip if f > WREG skip if f < WREG Syntax: [ label ] CPFSGT f [,a] Syntax: [ label ] CPFSLT f [,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] a ∈ [0,1] Operation: (f) − (WREG), Operation: (f) – (WREG), skip if (f) > (WREG) skip if (f) < (WREG) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data Description: Compares the contents of data memory location ’f’ to the contents memory location 'f' to the contents of the WREG by performing an of W by performing an unsigned unsigned subtraction. subtraction. If the contents of ’f’ are greater than If the contents of 'f' are less than the contents of , then the fetched the contents of WREG, then the instruction is discarded and a NOP fetched instruction is discarded and is executed instead making this a a NOP is executed instead making two-cycle instruction. If ’a’ is 0, the this a two-cycle instruction. If ’a’ is Access Bank will be selected, over- 0, the Access Bank will be riding the BSR value. If ’a’ is 1, the selected. If ’a’ is 1, the Bank will be Bank will be selected as per the selected as per the BSR value. BSR value. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note:3 cycles if skip and followed Note:3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ’f’ Data operation register ’f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE CPFSLT REG Example: HERE CPFSGT REG NLESS : NGREATER : LESS : GREATER : Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) WREG = ? WREG = ? After Instruction After Instruction If REG < WREG; If REG > WREG; PC = Address (LESS) PC = Address (GREATER) If REG ≥ WREG; If REG ≤ WREG; PC = Address (NLESS) PC = Address (NGREATER)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 279

PIC18CXX8 DAW Decimal Adjust WREG Register DECF Decrement f Syntax: [label] DAW Syntax: [ label ] DECF f [ ,d [,a] ] Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: If [WREG<3:0> >9] or [DC = 1] a ∈ [0,1] then (WREG<3:0>) + 6 → W<3:0>; Operation: (f) – 1 → dest else Status Affected: C,DC,N,OV,Z (WREG<3:0>) → W<3:0>; Encoding: 0000 01da ffff ffff If [WREG<7:4> >9] or [C = 1] then Description: Decrement register 'f'. If 'd' is 0, the (WREG<7:4>) + 6 → WREG<7:4>; result is stored in WREG. If 'd' is 1, the result is stored back in register else 'f' (default). If ’a’ is 0, the Access (WREG<7:4>) → WREG<7:4>; Bank will be selected, overriding Status Affected: C the BSR value. If ’a’ is 1, the Bank Encoding: 0000 0000 0000 0111 will be selected as per the BSR value. Description: DAW adjusts the eight bit value in WREG resulting from the earlier Words: 1 addition of two variables (each in Cycles: 1 packed BCD format) and produces Q Cycle Activity: a correct packed BCD result. Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1 register ’f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: DECF CNT Decode Read Process Write Before Instruction register WREG Data WREG CNT = 0x01 Example1: DAW Z = 0 Before Instruction After Instruction WREG = 0xA5 CNT = 0x00 C = 0 Z = 1 DC = 0 After Instruction WREG = 0x05 C = 1 DC = 0 Example 2: Before Instruction WREG = 0xCE C = 0 DC = 0 After Instruction WREG = 0x34 C = 1 DC = 0 DS30475A-page 280 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: [ label ] DECFSZ f [ ,d [,a] ] Syntax: [label] DCFSNZ f [ ,d [,a] ] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, Operation: (f) – 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register 'f' are dec- Description: The contents of register 'f' are dec- remented. If 'd' is 0, the result is remented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the placed in WREG. If 'd' is 1, the result is placed back in register 'f' result is placed back in register 'f' (default). (default). If the result is 0, the next instruc- If the result is not 0, the next tion, which is already fetched, is instruction, which is already discarded, and a NOP is executed fetched, is discarded, and a NOP is instead making it a two-cycle executed instead making it a two- instruction. If ’a’ is 0, the Access cycle instruction. If ’a’ is 0, the Bank will be selected, overriding Access Bank will be selected, the BSR value. If ’a’ is 1, the Bank overriding the BSR value. If ’a’ is will be selected as per the BSR 1, the Bank will be selected as per value. the BSR value. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note:3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ’f’ Data destination register ’f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE DECFSZ CNT Example: HERE DCFSNZ TEMP GOTO LOOP ZERO : CONTINUE NZERO : Before Instruction Before Instruction PC = Address (HERE) TEMP = ? After Instruction After Instruction CNT = CNT - 1 TEMP = TEMP - 1, If CNT = 0; If TEMP = 0; PC = Address (CONTINUE) PC = Address (ZERO) If CNT ≠ 0; If TEMP ≠ 0; PC = Address (HERE+2) PC = Address (NZERO)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 281

PIC18CXX8 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] GOTO k Syntax: [ label ] INCF f [ ,d [,a] ] Operands: 0 ≤ k ≤ 1048575 Operands: 0 ≤ f ≤ 255 Operation: k → PC<20:1> d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: (f) + 1 → dest Encoding: Status Affected: C,DC,N,OV,Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 Encoding: 0010 10da ffff ffff Description: GOTO allows an unconditional Description: The contents of register ’f’ are branch anywhere within entire 2M incremented. If ’d’ is 0, the result is byte memory range. The 20-bit placed in WREG. If ’d’ is 1, the value ’k’ is loaded into PC<20:1>. result is placed back in register ’f’ GOTO is always a two-cycle (default). If ’a’ is 0, the Access instruction. Bank will be selected, overriding the BSR value. If ’a’ is 1, the Bank Words: 2 will be selected as per the BSR Cycles: 2 value. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal No Read literal Q Cycle Activity: ’k’<7:0>, operation ’k’<19:8>, Write to PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write to operation operation operation operation register ’f’ Data destination Example: GOTO THERE Example: INCF CNT After Instruction Before Instruction PC = Address (THERE) CNT = 0xFF Z = 0 C = ? DC = ? After Instruction CNT = 0x00 Z = 1 C = 1 DC = 1 DS30475A-page 282 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: [ label ] INCFSZ f [ ,d [,a] ] Syntax: [label] INFSNZ f [, d [,a] ] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, Operation: (f) + 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 11da ffff ffff Encoding: 0100 10da ffff ffff Description: The contents of register ’f’ are Description: The contents of register 'f' are incremented. If ’d’ is 0, the result is incremented. If 'd' is 0, the result is placed in WREG. If ’d’ is 1, the placed in WREG. If 'd' is 1, the result is placed back in register ’f’ result is placed back in register 'f' (default). (default). If the result is 0, the next instruc- If the result is not 0, the next tion, which is already fetched, is instruction, which is already discarded, and a NOP is executed fetched, is discarded, and a NOP is instead making it a two-cycle executed instead making it a two- instruction. If ’a’ is 0, the Access cycle instruction. If ’a’ is 0, the Bank will be selected, overriding Access Bank will be selected, over- the BSR value. If ’a’ is 1, the Bank riding the BSR value. If ’a’ is 1, the will be selected as per the BSR Bank will be selected as per the value. BSR value. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note:3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ’f’ Data destination register ’f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT Example: HERE INFSNZ REG NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG ≠ 0; PC = Address(ZERO) PC = Address (NZERO) If CNT ≠ 0; If REG = 0; PC = Address(NZERO) PC = Address (ZERO)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 283

PIC18CXX8 IORLW Inclusive OR literal with WREG IORWF Inclusive OR WREG with f Syntax: [ label ] IORLW k Syntax: [ label ] IORWF f [ ,d [,a] ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 Operation: (WREG) .OR. k → WREG d ∈ [0,1] a ∈ [0,1] Status Affected: N,Z Operation: (WREG) .OR. (f) → dest Encoding: 0000 1001 kkkk kkkk Status Affected: N,Z Description: The contents of WREG are OR’ed Encoding: 0001 00da ffff ffff with the eight bit literal 'k'. The result is placed in WREG. Description: Inclusive OR W with register 'f'. If 'd' is 0, the result is placed in WREG. Words: 1 If 'd' is 1, the result is placed back Cycles: 1 in register 'f' (default). If ’a’ is 0, the Q Cycle Activity: Access Bank will be selected, over- riding the BSR value. If ’a’ is 1, the Q1 Q2 Q3 Q4 Bank will be selected as per the Decode Read Process Write to W BSR value. literal ’k’ Data Words: 1 Example: IORLW 0x35 Cycles: 1 Before Instruction Q Cycle Activity: WREG = 0x9A Q1 Q2 Q3 Q4 N = ? Decode Read Process Write to Z = ? register ’f’ Data destination After Instruction WREG = 0xBF Example: IORWF RESULT, W N = 1 Z = 0 Before Instruction RESULT = 0x13 WREG = 0x91 N = ? Z = ? After Instruction RESULT = 0x13 WREG = 0x93 N = 1 Z = 0 DS30475A-page 284 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 LFSR Load FSR MOVF Move f Syntax: [ label ] LFSR f,k Syntax: [ label ] MOVF f [ ,d [,a] ] Operands: 0 ≤ f ≤ 2 Operands: 0 ≤ f ≤ 255 0 ≤ k ≤ 4095 d ∈ [0,1] Operation: k → FSRf a ∈ [0,1] Operation: f → dest Status Affected: None Status Affected: N,Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k7kkk kkkk Encoding: 0101 00da ffff ffff Description: The 12-bit literal ’k’ is loaded into Description: The contents of register ’f’ is moved the file select register pointed to to a destination dependent upon by ’f’ the status of ’d’. If 'd' is 0, the result Words: 2 is placed in WREG. If 'd' is 1, the result is placed back in register 'f' Cycles: 2 (default). Location 'f' can be any- Q Cycle Activity: where in the 256 byte Bank. If ’a’ is Q1 Q2 Q3 Q4 0, the Access Bank will be selected, overriding the BSR value. Decode Read literal Process Write ’k’ MSB Data literal ’k’ If ’a’ is 1, the Bank will be selected MSB to as per the BSR value. FSRfH Words: 1 Decode Read literal Process Write literal Cycles: 1 ’k’ LSB Data ’k’ to FSRfL Q Cycle Activity: Example: LFSR FSR2, 0x3AB Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write W FSR2H = 0x03 register ’f’ Data FSR2L = 0xAB Example: MOVF REG, W Before Instruction REG = 0x22 WREG = 0xFF N = ? Z = ? After Instruction REG = 0x22 WREG = 0x22 N = 0 Z = 0  2000 Microchip Technology Inc. Advanced Information DS30475A-page 285

PIC18CXX8 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: [label] MOVFF f ,f Syntax: [ label ] MOVLB k s d Operands: 0 ≤ f ≤ 4095 Operands: 0 ≤ k ≤ 255 s 0 ≤ fd ≤ 4095 Operation: k → BSR Operation: (f ) → f Status Affected: None s d Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The 8-bit literal ’k’ is loaded into 1st word (source) 1100 ffff ffff ffffs the Bank Select Register (BSR). 2nd word (destin.) 1111 ffff ffff ffffd Words: 1 Description: The contents of source register ’fs’ Cycles: 1 are moved to destination register Q Cycle Activity: ’f ’. Location of source ’f ’ can be d s Q1 Q2 Q3 Q4 anywhere in the 4096 byte data space (000h to FFFh), and location Decode Read literal Process Write of destination ’f ’ can also be any- ’k’ Data literal ’k’ to d BSR where from 000h to FFFh. Either source or destination can be WREG (a useful special situation). Example: MOVLB 0x05 MOVFF is particularly useful for Before Instruction transferring a data memory location BSR register = 0x02 to a peripheral register (such as the After Instruction transmit buffer or an I/O port). BSR register = 0x05 The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ’f’ Data operation (src) Decode No No Write operation operation register ’f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 0x33 REG2 = 0x11 After Instruction REG1 = 0x33, REG2 = 0x33 DS30475A-page 286 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 MOVLW Move literal to WREG MOVWF Move WREG to f Syntax: [ label ] MOVLW k Syntax: [ label ] MOVWF f [,a] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 Operation: k → WREG a ∈ [0,1] Operation: (WREG) → f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight bit literal ’k’ is loaded into WREG. Description: Move data from WREG to register ’f’. Location ’f’ can be anywhere in Words: 1 the 256 byte Bank. If ’a’ is 0, the Cycles: 1 Access Bank will be selected, over- Q Cycle Activity: riding the BSR value. If ’a’ is 1, the Bank will be selected as per the Q1 Q2 Q3 Q4 BSR value. Decode Read Process Write to W literal ’k’ Data Words: 1 Cycles: 1 Example: MOVLW 0x5A Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 WREG = 0x5A Decode Read Process Write register ’f’ Data register ’f’ Example: MOVWF REG Before Instruction WREG = 0x4F REG = 0xFF After Instruction WREG = 0x4F REG = 0x4F  2000 Microchip Technology Inc. Advanced Information DS30475A-page 287

PIC18CXX8 MULLW Multiply Literal with WREG MULWF Multiply WREG with f Syntax: [ label ] MULLW k Syntax: [ label ] MULWF f [,a] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 Operation: (WREG) x k → PRODH:PRODL a ∈ [0,1] Operation: (WREG) x (f) → PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is car- ried out between the contents of Description: An unsigned multiplication is car- WREG and the 8-bit literal ’k’. ried out between the contents of The 16-bit result is placed in WREG and the register file loca- PRODH:PRODL register pair. tion ’f’. The 16-bit result is stored PRODH contains the high byte. in the PRODH:PRODL register WREG is unchanged. pair. PRODH contains the high byte. None of the status flags are affected. Both WREG and ’f’ are unchanged. Note that neither overflow nor carry is possible in this opera- None of the status flags are tion. A zero result is possible but affected. not detected. Note that neither overflow nor carry is possible in this opera- Words: 1 tion. A zero result is possible but Cycles: 1 not detected. If ’a’ is 0, the Q Cycle Activity: Access Bank will be selected, overriding the BSR value. If ’a’ is Q1 Q2 Q3 Q4 1, the Bank will be selected as Decode Read Process Write per the BSR value. literal ’k’ Data registers PRODH: Words: 1 PRODL Cycles: 1 Q Cycle Activity: Example: MULLW 0xC4 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write WREG = 0xE2 register ’f’ Data registers PRODH = ? PRODH: PRODL = ? PRODL After Instruction WREG = 0xE2 Example: MULWF REG PRODH = 0xAD PRODL = 0x08 Before Instruction WREG = 0xC4 REG = 0xB5 PRODH = ? PRODL = ? After Instruction WREG = 0xC4 REG = 0xB5 PRODH = 0x8A PRODL = 0x94 DS30475A-page 288 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 NEGF Negate f NOP No Operation Syntax: [label] NEGF f [,a] Syntax: [ label ] NOP Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: No operation Operation: (f) + 1 → f Status Affected: None Status Affected: N,OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ’f’ is negated using two’s Description: No operation. complement. The result is placed in Words: 1 the data memory location 'f'. If ’a’ is Cycles: 1 0, the Access Bank will be selected, overriding the BSR value. Q Cycle Activity: If ’a’ is 1, the Bank will be selected Q1 Q2 Q3 Q4 as per the BSR value. Decode No No No Words: 1 operation operation operation Cycles: 1 Example: Q Cycle Activity: Q1 Q2 Q3 Q4 None. Decode Read Process Write register ’f’ Data register ’f’ Example: NEGF REG Before Instruction REG = 0011 1010 [0x3A] N = ? OV = ? C = ? DC = ? Z = ? After Instruction REG = 1100 0110 [0xC6] N = 1 OV = 0 C = 0 DC = 0 Z = 0  2000 Microchip Technology Inc. Advanced Information DS30475A-page 289

PIC18CXX8 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] POP Syntax: [ label ] PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC+2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the Description: The PC+2 is pushed onto the top of return stack and is discarded. The the return stack. The previous TOS TOS value then becomes the previ- value is pushed down on the stack. ous value that was pushed onto the This instruction allows implement- return stack. ing a software stack by modifying This instruction is provided to TOS, and then push it onto the enable the user to properly manage return stack. the return stack to incorporate a Words: 1 software stack. Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Push PC+2 No No Q1 Q2 Q3 Q4 onto return operation operation Decode No Pop TOS No stack operation value operation Example: PUSH Example: POP Before Instruction GOTO NEW TOS = 00345Ah Before Instruction PC = 000124h TOS = 0031A2h Stack (1 level down) = 014332h After Instruction PC = 000126h After Instruction TOS = 000126h TOS = 014332h Stack (1 level down) = 00345Ah PC = NEW DS30475A-page 290 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 RCALL Relative Call RESET Reset Syntax: [ label ] RCALL n Syntax: [ label ] RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that (PC) + 2 + 2n → PC are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to Description: This instruction provides a way to 1K from the current location. First, execute a MCLR Reset in software. return address (PC+2) is pushed Words: 1 onto the stack. Then, add the 2’s complement number ’2n’ to the PC. Cycles: 1 Since the PC will have incremented Q Cycle Activity: to fetch the next instruction, the Q1 Q2 Q3 Q4 new address will be PC+2+2n. Decode Start No No This instruction is a two-cycle reset operation operation instruction. Words: 1 Example: RESET Cycles: 2 After Instruction Q Cycle Activity: Registers= Reset Value Flags* = Reset Value Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC ’n’ Data Push PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address(HERE) After Instruction PC = Address(Jump) TOS= Address (HERE+2)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 291

PIC18CXX8 RETFIE Return from Interrupt RETLW Return Literal to WREG Syntax: [ label ] RETFIE [s] Syntax: [ label ] RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, Operation: k → W, 1 → GIE/GIEH or PEIE/GIEL, (TOS) → PC, if s = 1 PCLATU, PCLATH are unchanged (WS) → W, (STATUSS) → STATUS, Status Affected: None (BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged. Description: W is loaded with the eight bit literal Status Affected: None 'k'. The program counter is loaded from the top of the stack (the return Encoding: 0000 0000 0001 000s address). The high address latch Description: Return from Interrupt. Stack is (PCLATH) remains unchanged. popped and Top-of-Stack (TOS) Words: 1 is loaded into the PC. Interrupts are enabled by setting the either Cycles: 2 the high or low priority global Q Cycle Activity: interrupt enable bit. If ’s’ = 1, the Q1 Q2 Q3 Q4 contents of the shadow registers WS, STATUSS and BSRS are Decode Read Process Pop PC from literal ’k’ Data stack, write loaded into their corresponding to W registers, WREG, STATUS and No No No No BSR. If ’s’ = 0, no update of operation operation operation operation these registers occurs (default). Words: 1 Example: Cycles: 2 CALL TABLE ; WREG contains table Q Cycle Activity: ; offset value Q1 Q2 Q3 Q4 ; WREG now has Decode No No Pop PC from ; table value operation operation stack : Set GIEH or TABLE GIEL ADDWF PCL ; WREG = offset RETLW k0 ; Begin table No No No No RETLW k1 ; operation operation operation operation : : Example: RETFIE 1 RETLW kn ; End of table After Interrupt PC = TOS Before Instruction WREG = WS WREG = 0x07 BSR = BSRS After Instruction STATUS = STATUSS WREG = value of kn GIE/GIEH, PEIE/GIEL = 1 DS30475A-page 292 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] RETURN [s] Syntax: [ label ] RLCF f [ ,d [,a] ] Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255 Operation: (TOS) → PC, d ∈ [0,1] a ∈ [0,1] if s = 1 (WS) → W, Operation: (f<n>) → dest<n+1>, (STATUSS) → STATUS, (f<7>) → C, (BSRS) → BSR, (C) → dest<0> PCLATU, PCLATH are unchanged Status Affected: C,N,Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register 'f' are Description: Return from subroutine. The rotated one bit to the left through stack is popped and the top of the the Carry Flag. If 'd' is 0 the result is stack (TOS) is loaded into the placed in WREG. If 'd' is 1 the program counter. If ’s’ = 1, the result is stored back in register 'f' contents of the shadow registers (default). If ’a’ is 0, the Access WS, STATUSS and BSRS are Bank will be selected, overriding loaded into their corresponding the BSR value. If ’a’ is 1, the Bank registers, WREG, STATUS and will be selected as per the BSR BSR. If ’s’ = 0, no update of value. these registers occurs (default). C register f Words: 1 Cycles: 2 Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode No Process Pop PC from Q1 Q2 Q3 Q4 operation Data stack Decode Read Process Write to No No No No register ’f’ Data destination operation operation operation operation Example: RLCF REG, W Before Instruction Example: RETURN REG = 1110 0110 After Call C = 0 PC = TOS N = ? Z = ? RETURN FAST After Instruction Before Instruction REG = 1110 0110 WRG = 0x04 WREG = 1100 1100 STATUS = 0x00 C = 1 BSR = 0x00 N = 1 After Instruction Z = 0 WREG = 0x04 STATUS = 0x00 BSR = 0x00 PC = TOS  2000 Microchip Technology Inc. Advanced Information DS30475A-page 293

PIC18CXX8 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] RLNCF f [ ,d [,a] ] Syntax: [ label ] RRCF f [ ,d [,a] ] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n+1>, Operation: (f<n>) → dest<n-1>, (f<7>) → dest<0> (f<0>) → C, (C) → dest<7> Status Affected: N,Z Status Affected: C,N,Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ’f’ are rotated one bit to the left. If ’d’ is 0 Description: The contents of register 'f' are the result is placed in WREG. If ’d’ rotated one bit to the right through is 1, the result is stored back in reg- the Carry Flag. If 'd' is 0, the result ister 'f' (default). If ’a’ is 0, the is placed in WREG. If 'd' is 1, the Access Bank will be selected, over- result is placed back in register 'f' riding the BSR value. If ’a’ is 1, the (default). If ’a’ is 0, the Access Bank will be selected as per the Bank will be selected, overriding BSR value. the BSR value. If ’a’ is 1, the Bank will be selected as per the BSR register f value. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register ’f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to Example: RLNCF REG register ’f’ Data destination Before Instruction REG = 1010 1011 Example: RRCF REG, W N = ? Before Instruction Z = ? REG = 1110 0110 C = 0 After Instruction N = ? REG = 0101 0111 Z = ? N = 0 After Instruction Z = 0 REG = 1110 0110 WREG = 0111 0011 C = 0 N = 0 Z = 0 DS30475A-page 294 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] RRNCF f [ ,d [,a] ] Syntax: [label] SETF f [,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: FFh → f Operation: (f<n>) → dest<n-1>, Status Affected: None (f<0>) → dest<7> Encoding: 0110 100a ffff ffff Status Affected: N,Z Description: The contents of the specified regis- Encoding: 0100 00da ffff ffff ter are set to FFh. If ’a’ is 0, the Description: The contents of register ’f’ are Access Bank will be selected, over- rotated one bit to the right. If ’d’ is 0, riding the BSR value. If ’a’ is 1, the the result is placed in WREG. If ’d’ Bank will be selected as per the is 1, the result is placed back in BSR value. register 'f' (default). If ’a’ is 0, the Words: 1 Access Bank will be selected, over- riding the BSR value. If ’a’ is 1, the Cycles: 1 Bank will be selected as per the Q Cycle Activity: BSR value. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ’f’ Data register ’f’ Words: 1 Cycles: 1 Example: SETF REG Q Cycle Activity: Before Instruction REG = 0x5A Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to register ’f’ Data destination REG = 0xFF Example 1: RRNCF REG Before Instruction REG = 1101 0111 N = ? Z = ? After Instruction REG = 1110 1011 N = 1 Z = 0 Example 2: RRNCF REG, 0, 0 Before Instruction WREG = ? REG = 1101 0111 N = ? Z = ? After Instruction WREG = 1110 1011 REG = 1101 0111 N = 1 Z = 0  2000 Microchip Technology Inc. Advanced Information DS30475A-page 295

PIC18CXX8 SLEEP Enter SLEEP mode SUBFWB Subtract f from WREG with borrow Syntax: [ label ] SLEEP Syntax: [ label ] SUBFWB f [ ,d [,a] ] Operands: None Operands: 0 ≤ f ≤ 255 Operation: 00h → WDT, d ∈ [0,1] 0 → WDT postscaler, a ∈ [0,1] 1 → TO, Operation: (WREG) – (f) – (C) → dest 0 → PD Status Affected: N,OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register 'f' and carry flag Description: The power-down status bit (PD) is (borrow) from WREG (2’s comple- cleared. The time-out status bit ment method). If 'd' is 0, the result (TO) is set. Watchdog Timer and is stored in WREG. If 'd' is 1, the its postscaler are cleared. result is stored in register 'f' The processor is put into SLEEP (default) . If ’a’ is 0, the Access mode with the oscillator stopped. Bank will be selected, overriding the BSR value. If ’a’ is 1, the Bank Words: 1 will be selected as per the BSR Cycles: 1 value. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode No Process Go to Q Cycle Activity: operation Data sleep Q1 Q2 Q3 Q4 Decode Read Process Write to Example: SLEEP register ’f’ Data destination Before Instruction TO = ? PD = ? After Instruction TO = 1 † PD = 0 † If WDT causes wake-up, this bit is cleared. DS30475A-page 296 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 SUBFWB (Cont.) SUBLW Subtract WREG from literal Example 1: SUBFWB REG Syntax: [ label ] SUBLW k Before Instruction Operands: 0 ≤ k ≤ 255 REG = 3 Operation: k – (WREG) → WREG WREG = 2 C = 1 Status Affected: N,OV, C, DC, Z After Instruction Encoding: 0000 1000 kkkk kkkk REG = 0xFF Description: WREG is subtracted from the WREG = 2 eight bit literal 'k'. The result is C = 0 Z = 0 placed in WREG. N = 1 ; result is negative Words: 1 Cycles: 1 Example 2: SUBFWB REG Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 2 WREG = 5 Decode Read Process Write to W C = 1 literal ’k’ Data After Instruction Example 1: SUBLW 0x02 REG = 2 Before Instruction WREG = 3 C = 1 WREG = 1 Z = 0 C = ? N = 0 ; result is positive After Instruction Example 3: SUBFWB REG WREG = 1 C = 1 ; result is positive Before Instruction Z = 0 REG = 1 N = 0 WREG = 2 C = 0 Example 2: SUBLW 0x02 After Instruction Before Instruction REG = 0 WREG = 2 WREG = 2 C = 1 C = ? Z = 1 ; result is zero After Instruction N = 0 WREG = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBLW 0x02 Before Instruction WREG = 3 C = ? After Instruction WREG = 0xFF ; (2’s complement) C = 0 ; result is negative Z = 0 N = 1  2000 Microchip Technology Inc. Advanced Information DS30475A-page 297

PIC18CXX8 SUBWF Subtract WREG from f SUBWF Subtract WREG from f (cont’d) Syntax: [ label ] SUBWF f [ ,d [,a] ] Example 1: SUBWF REG Operands: 0 ≤ f ≤ 255 Before Instruction d ∈ [0,1] REG = 3 a ∈ [0,1] WREG = 2 C = ? Operation: (f) – (WREG) → dest After Instruction Status Affected: N,OV, C, DC, Z REG = 1 Encoding: 0101 11da ffff ffff WREG = 2 C = 1 ; result is positive Description: Subtract WREG from register 'f' Z = 0 (2’s complement method). If 'd' is N = 0 0, the result is stored in WREG. If Example 2: SUBWF REG, W 'd' is 1, the result is stored back in register 'f' (default). If ’a’ is 0, the Before Instruction Access Bank will be selected, REG = 2 overriding the BSR value. If ’a’ is WREG = 2 1, the Bank will be selected as per C = ? the BSR value. After Instruction REG = 2 Words: 1 WREG = 0 Cycles: 1 C = 1 ; result is zero Z = 1 Q Cycle Activity: N = 0 Q1 Q2 Q3 Q4 Example 3: SUBWF REG Decode Read Process Write to register ’f’ Data destination Before Instruction REG = 1 WREG = 2 C = ? After Instruction REG = 0xFF ;(2’s complement) WREG = 2 C = 0 ; result is negative Z = 0 N = 1 DS30475A-page 298 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 Subtract WREG from f with Subtract WREG from f with SUBWFB SUBWFB Borrow Borrow (cont’d) Syntax: [ label ] SUBWFB f [ ,d [,a] ] Example 1: SUBWFB REG Operands: 0 ≤ f ≤ 255 Before Instruction d ∈ [0,1] REG = 0x19 (0001 1001) a ∈ [0,1] WREG = 0x0D (0000 1101) C = 1 Operation: (f) – (WREG) – (C) → dest After Instruction Status Affected: N,OV, C, DC, Z REG = 0x0C (0000 1011) WREG = 0x0D (0000 1101) Encoding: 0101 10da ffff ffff C = 1 Description: Subtract WREG and the carry flag Z = 0 (borrow) from register 'f' (2’s com- N = 0 ; result is positive plement method). If 'd' is 0, the result is stored in WREG. If 'd' is Example 2: SUBWFB REG, W 1, the result is stored back in reg- Before Instruction ister 'f' (default). If ’a’ is 0, the REG = 0x1B (0001 1011) Access Bank will be selected, WREG = 0x1A (0001 1010) overriding the BSR value. If ’a’ is C = 0 1, the Bank will be selected as per After Instruction the BSR value. REG = 0x1B (0001 1011) Words: 1 WREG = 0x00 C = 1 Cycles: 1 Z = 1 ; result is zero Q Cycle Activity: N = 0 Q1 Q2 Q3 Q4 Example 3: SUBWFB REG Decode Read Process Write to Before Instruction register ’f’ Data destination REG = 0x03 (0000 0011) WREG = 0x0E (0000 1101) C = 1 After Instruction REG = 0xF5 (1111 0100) [2’s comp] WREG = 0x0E (0000 1101) C = 0 Z = 0 N = 1 ; result is negative  2000 Microchip Technology Inc. Advanced Information DS30475A-page 299

PIC18CXX8 SWAPF Swap nibbles in f Syntax: [ label ] SWAPF f [ ,d [,a] ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: 0011 10da ffff ffff Description: The upper and lower nibbles of reg- ister ’f’ are exchanged. If ’d’ is 0, the result is placed in WREG. If ’d’ is 1, the result is placed in register ’f’ (default). If ’a’ is 0, the Access Bank will be selected, overriding the BSR value. If ’a’ is 1, the Bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ’f’ Data destination Example: SWAPF REG Before Instruction REG = 0x53 After Instruction REG = 0x35 DS30475A-page 300 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TBLRD Table Read TBLRD Table Read (cont’d) Syntax: [ label ] TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 0x55 Operation: if TBLRD *, TBLPTR = 0x00A356 (Prog Mem (TBLPTR)) → TABLAT; MEMORY(0x00A356) = 0x34 TBLPTR - No Change; After Instruction if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT; TABLAT = 0x34 (TBLPTR) +1 → TBLPTR; TBLPTR = 0x00A357 if TBLRD *-, Example 2: TBLRD +* ; (Prog Mem (TBLPTR)) → TABLAT; Before Instruction (TBLPTR) -1 → TBLPTR; TABLAT = 0xAA if TBLRD +*, TBLPTR = 0x01A357 (TBLPTR) +1 → TBLPTR; MEMORY(0x01A357) = 0x12 (Prog Mem (TBLPTR)) → TABLAT; MEMORY(0x01A358) = 0x34 Status Affected: None After Instruction TABLAT = 0x34 Encoding: 0000 0000 0000 10nn TBLPTR = 0x01A358 nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: (cid:127) no change (cid:127) post-increment (cid:127) post-decrement (cid:127) pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No No No operation operation operation operation (Read (Write Program TABLAT) Memory)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 301

PIC18CXX8 TBLWT Table Write TBLWT Table Write (Continued) Syntax: [ label ] TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction TABLAT = 0x55 Operation: if TBLWT*, (TABLAT) → Prog Mem (TBLPTR) or TBLPTR = 0x00A356 MEMORY(0x00A356) = 0xFF Holding Register; After Instructions (table write completion) TBLPTR - No Change; if TBLWT*+, TABLAT = 0x55 (TABLAT) → Prog Mem (TBLPTR) or TBLPTR = 0x00A357 MEMORY(0x00A356) = 0x55 Holding Register; (TBLPTR) +1 → TBLPTR; Example 2: TBLWT +*; if TBLWT*-, Before Instruction (TABLAT) → Prog Mem (TBLPTR) or TABLAT = 0x34 Holding Register; TBLPTR = 0x01389A (TBLPTR) -1 → TBLPTR; MEMORY(0x01389A) = 0xFF if TBLWT+*, MEMORY(0x01389B) = 0xFF (TBLPTR) +1 → TBLPTR; After Instruction (table write completion) (TABLAT) → Prog Mem (TBLPTR) or TABLAT = 0x34 Holding Register; TBLPTR = 0x01389B MEMORY(0x01389A) = 0xFF Status Affected: None MEMORY(0x01389B) = 0x34 Encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to program the contents of Program Memory (P.M.). The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 MBtye address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0:Least Significant Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: (cid:127) no change (cid:127) post-increment (cid:127) post-decrement (cid:127) pre-increment Words: 1 Cycles: 2 (many if long write is to on-chip EPROM program memory) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No No No operation operation operation operation (Read (Write to Holding TABLAT) Register or Memory) DS30475A-page 302 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with WREG Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 a ∈ [0,1] Operation: (WREG) .XOR. k → WREG Operation: skip if f = 0 Status Affected: N,Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of WREG are Description: If ’f’ = 0, the next instruction, XOR’ed with the 8-bit literal 'k'. fetched during the current instruc- The result is placed in WREG. tion execution, is discarded and a Words: 1 NOP is executed making this a two- cycle instruction. If ’a’ is 0, the Cycles: 1 Access Bank will be selected, over- Q Cycle Activity: riding the BSR value. If ’a’ is 1, the Q1 Q2 Q3 Q4 Bank will be selected as per the BSR value. Decode Read Process Write to literal ’k’ Data WREG Words: 1 Cycles: 1(2) Example: XORLW 0xAF Note: 3 cycles if skip and followed Before Instruction by a 2-word instruction WREG = 0xB5 Q Cycle Activity: N = ? Q1 Q2 Q3 Q4 Z = ? Decode Read Process No After Instruction register ’f’ Data operation WREG = 0x1A If skip: N = 0 Z = 0 Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 0x00, PC = Address (ZERO) If CNT ≠ 0x00, PC = Address (NZERO)  2000 Microchip Technology Inc. Advanced Information DS30475A-page 303

PIC18CXX8 XORWF Exclusive OR WREG with f Syntax: [ label ] XORWF f [ ,d [,a] ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (WREG) .XOR. (f) → dest Status Affected: N,Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of WREG with register ’f’. If ’d’ is 0, the result is stored in WREG. If ’d’ is 1, the result is stored back in the reg- ister 'f' (default). If ’a’ is 0, the Access Bank will be selected, over- riding the BSR value. If ’a’ is 1, the Bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ’f’ Data destination Example: XORWF REG Before Instruction REG = 0xAF WREG = 0xB5 N = ? Z = ? After Instruction REG = 0x1A WREG = 0xB5 N = 0 Z = 0 DS30475A-page 304 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 24.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to: The PICmicro® microcontrollers are supported with a (cid:127) Edit your source files (either assembly or ‘C’) full range of hardware and software development tools: (cid:127) One touch assemble (or compile) and download to PICmicro tools (automatically updates all (cid:127) Integrated Development Environment project information) - MPLAB® IDE Software (cid:127) Debug using: (cid:127) Assemblers/Compilers/Linkers - source files - MPASMTM Assembler - absolute listing file - MPLAB C17 and MPLAB C18 C Compilers - object code - MPLINKTM Linker/MPLIBTM Librarian The ability to use MPLAB IDE with Microchip’s MPLAB (cid:127) Simulators SIM simulator, allows a consistent platform and the - MPLAB SIM Software Simulator ability to easily switch from the cost effective simulator (cid:127) Emulators to the full featured emulator with minimal retraining. - MPLAB ICE 2000 In-Circuit Emulator 24.2 MPASM Assembler - ICEPIC™ In-Circuit Emulator (cid:127) In-Circuit Debugger The MPASM assembler is a full featured universal - MPLAB ICD for PIC16F877 macro assembler for all PICmicro MCU’s. It can pro- (cid:127) Device Programmers duce absolute code directly in the form of HEX files for - PRO MATE® II Universal Device Programmer device programmers, or it can generate relocatable objects for the MPLINK object linker. - PICSTART® Plus Entry-Level Development Programmer The MPASM assembler has a command line interface and a Windows shell and can be used as a stand-alone (cid:127) Low Cost Demonstration Boards application on a Windows 3.x, or greater, system. The - PICDEMTM 1 Demonstration Board MPASM assembler generates relocatable object files, - PICDEM 2 Demonstration Board Intel® standard HEX files, MAP files to detail memory - PICDEM 3 Demonstration Board usage and symbol reference, an absolute LST file, - PICDEM 17 Demonstration Board which contains source lines and generated machine - KEELOQ® Demonstration Board code, and a COD file for debugging. The MPASM assembler features include: 24.1 MPLAB Integrated Development (cid:127) MPASM assembler and MPLINK object linker are Environment Software integrated into MPLAB IDE projects. The MPLAB IDE software brings an ease of software (cid:127) MPASM assembler allows user defined macros to development previously unseen in the 8-bit microcon- be created for streamlined assembly. troller market. The MPLAB IDE is a Windows®-based (cid:127) MPASM assembler allows conditional assembly application which contains: for multi-purpose source files. (cid:127) Multiple functionality (cid:127) MPASM assembler directives allow complete - editor control over the assembly process. - simulator 24.3 MPLAB C17 and MPLAB C18 - programmer (sold separately) C Compilers - emulator (sold separately) (cid:127) A full featured editor The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI ‘C’ compilers and inte- (cid:127) A project manager grated development environments for Microchip’s (cid:127) Customizable tool bar and key mapping PIC17CXXX and PIC18CXXX family of microcontrol- (cid:127) A status bar lers, respectively. These compilers provide powerful (cid:127) On-line help integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers pro- vide symbol information that is compatible with the MPLAB IDE memory display.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 305

PIC18CXX8 24.4 MPLINK Linker/MPLIB Librarian 24.6 MPLAB ICE High Performance Universal In-Circuit Emulator with The MPLINK object linker is a relocatable linker for the MPLAB IDE MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from The MPLAB ICE universal in-circuit emulator is intended assembly or C source files, along with pre-compiled to provide the product development engineer with a libraries, using directives from a linker script. complete microcontroller design tool set for PICmicro The MPLIB object librarian is a librarian for pre- microcontrollers (MCUs). Software control of the compiled code to be used with the MPLINK object MPLAB ICE in-circuit emulator is provided by the linker. When a routine from a library is called from MPLAB Integrated Development Environment (IDE), another source file, only the modules that contain that which allows editing, “make” and download and source routine will be linked in with the application. This allows debugging from a single environment. large libraries to be used efficiently in many different Interchangeable processor modules allow the system applications. The MPLIB object librarian manages the to be easily reconfigured for emulation of different pro- creation and modification of library files. cessors. The universal architecture of the MPLAB ICE The MPLINK object linker features include: in-circuit emulator allows expansion to support new PICmicro microcontrollers. (cid:127) MPLINK object linker works with MPASM assem- bler and MPLAB C17 and MPLAB C18 C compilers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with (cid:127) MPLINK object linker allows all memory areas to advanced features that are generally found on more be defined as sections to provide link-time expensive development tools. The PC platform and flexibility. Microsoft® Windows 3.x/95/98 environment were cho- The MPLIB object librarian features include: sen to best make these features available to you, the (cid:127) MPLIB object librarian makes linking easier end user. because single libraries can be included instead The MPLAB ICE in-circuit emulator is available in two of many smaller files. versions: MPLAB ICE1000 and MPLAB ICE2000. (cid:127) MPLIB object librarian helps keep code maintain- The MPLAB ICE 1000 is a basic, low cost emulator able by grouping related modules together. system with simple trace capabilities. The MPLAB ICE (cid:127) MPLIB object librarian commands allow libraries 2000 is a full featured emulator system with enhanced to be created and modules to be added, listed, trace, trigger and data monitoring features. Both sys- replaced, deleted or extracted. tems use the same processor modules and will operate across the full operating speed range of the PICmicro 24.5 MPLAB SIM Software Simulator MCU. The MPLAB SIM software simulator allows code devel- 24.7 ICEPIC In-Circuit Emulator opment in a PC host environment by simulating the PICmicro series microcontrollers on an instruction The ICEPIC low cost, in-circuit emulator is a solution level. On any given instruction, the data areas can be for the Microchip Technology PIC16C5X, PIC16C6X, examined or modified and stimuli can be applied from PIC16C7X and PIC16CXXX families of 8-bit One- a file, or user-defined key press, to any of the pins. The Time-Programmable (OTP) microcontrollers. The mod- execution can be performed in single step, execute ular system can support different subsets of PIC16C5X until break, or trace mode. or PIC16CXXX products through the use of inter- changeable personality modules, or daughter boards. The MPLAB SIM simulator fully supports symbolic The emulator is capable of emulating without target debugging using the MPLAB C17 and the MPLAB C18 application circuitry being present. C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi-project software development tool. DS30475A-page 306 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 24.8 MPLAB ICD In-Circuit Debugger 24.11 PICDEM 1 Low Cost PICmicro Demonstration Board Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow- erful, low cost, run-time development tool. This tool is The PICDEM 1 demonstration board is a simple board based on the FLASH PIC16F877 and can be used to which demonstrates the capabilities of several of develop this and other PICmicro microcontrollers from Microchip’s microcontrollers. The microcontrollers sup- the PIC16CXXX family. The MPLAB ICD utilizes the in- ported are: PIC16C5X (PIC16C54 to PIC16C58A), circuit debugging capability built into the PIC16F87X. PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, This feature, along with Microchip’s In-Circuit Serial PIC17C42, PIC17C43 and PIC17C44. All necessary ProgrammingTM protocol, offers cost effective in-circuit hardware and software is included to run basic demo FLASH programming and debugging from the graphical programs. The user can program the sample microcon- user interface of the MPLAB Integrated Development trollers provided with the PICDEM 1 demonstration Environment. This enables a designer to develop and board on a PROMATE II device programmer, or a debug source code by watching variables, single-step- PICSTART Plus development programmer, and easily ping and setting break points. Running at full speed test firmware. The user can also connect the enables testing hardware in real-time. The MPLAB ICD PICDEM1 demonstration board to the MPLAB ICE in- is also a programmer for the FLASH PIC16F87X family. circuit emulator and download the firmware to the emu- lator for testing. A prototype area is available for the 24.9 PRO MATE II Universal Device user to build some additional hardware and connect it Programmer to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simu- The PRO MATE II universal device programmer is a full lated analog input, push button switches and eight featured programmer, capable of operating in stand- LEDs connected to PORTB. alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. 24.12 PICDEM 2 Low Cost PIC16CXX The PRO MATE II device programmer has program- Demonstration Board mable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for The PICDEM 2 demonstration board is a simple dem- maximum reliability. It has an LCD display for instruc- onstration board that supports the PIC16C62, tions and error messages, keys to enter commands PIC16C64, PIC16C65, PIC16C73 and PIC16C74 and a modular detachable socket assembly to support microcontrollers. All the necessary hardware and soft- various package types. In stand-alone mode, the PRO ware is included to run the basic demonstration pro- MATE II device programmer can read, verify, or pro- grams. The user can program the sample gram PICmicro devices. It can also set code-protect microcontrollers provided with the PICDEM2 demon- bits in this mode. stration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer and 24.10 PICSTART Plus Entry Level easily test firmware. The MPLAB ICE in-circuit emula- Development Programmer tor may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been pro- The PICSTART Plus development programmer is an vided to the user for adding additional hardware and easy-to-use, low cost, prototype programmer. It con- connecting it to the microcontroller socket(s). Some of nects to the PC via one of the COM (RS-232) ports. the features include a RS-232 interface, push button MPLAB Integrated Development Environment software switches, a potentiometer for simulated analog input, a makes using the programmer simple and efficient. Serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD The PICSTART Plus development programmer sup- module and a keypad. ports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 307

PIC18CXX8 24.13 PICDEM 3 Low Cost PIC16CXXX 24.14 PICDEM 17 Demonstration Board Demonstration Board The PICDEM 17 demonstration board is an evaluation The PICDEM 3 demonstration board is a simple dem- board that demonstrates the capabilities of several onstration board that supports the PIC16C923 and Microchip microcontrollers, including PIC17C752, PIC16C924 in the PLCC package. It will also support PIC17C756, PIC17C762 and PIC17C766. All neces- future 44-pin PLCC microcontrollers with an LCD Mod- sary hardware is included to run basic demo programs, ule. All the necessary hardware and software is which are supplied on a 3.5-inch disk. A programmed included to run the basic demonstration programs. The sample is included and the user may erase it and user can program the sample microcontrollers pro- program it with the other sample programs using the vided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or the PICSTART PRO MATE II device programmer, or a PICSTART Plus Plus development programmer, and easily debug and development programmer with an adapter socket, and test the sample code. In addition, the PICDEM17 dem- easily test firmware. The MPLAB ICE in-circuit emula- onstration board supports down-loading of programs to tor may also be used with the PICDEM 3 demonstration and executing out of external FLASH memory on board. board to test firmware. A prototype area has been pro- The PICDEM 17 demonstration board is also usable vided to the user for adding hardware and connecting it with the MPLAB ICE in-circuit emulator, or the to the microcontroller socket(s). Some of the features PICMASTER emulator and all of the sample programs include an RS-232 interface, push button switches, a can be run and modified using either emulator. Addition- potentiometer for simulated analog input, a thermistor ally, a generous prototype area is available for user and separate headers for connection to an external hardware. LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is an LCD panel, with 24.15 KEELOQ Evaluation and Programming Tools 4 commons and 12 segments, that is capable of dis- playing time, temperature and day of the week. The KEELOQ evaluation and programming tools support PICDEM 3 demonstration board provides an additional Microchip’s HCS Secure Data Products. The HCS RS-232 interface and Windows 3.1 software for show- evaluation kit includes an LCD display to show chang- ing the demultiplexed LCD signals on a PC. A simple ing codes, a decoder to decode transmissions and a serial interface allows the user to construct a hardware programming interface to program test transmitters. demultiplexer for the LCD signals. DS30475A-page 308 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 24-1: DEVELOPMENT TOOLS FROM MICROCHIP 0152PCM Æ 7. 7 6, XXXFRCM Æ Æ Æ Æ 4, 7 7 3, 7 XXXSCH Æ Æ Æ Æ 2, 7 5, 6 XXC39 4, //XXXXCC4522 Æ Æ 3, 6 6 2, 6 2XXC81CIP Æ Æ Æ Æ Æ Æ Æ 6C 1 C PI h XX7C71CIP Æ Æ Æ Æ Æ Æ Æ wit 1) 0 0 4 X4C71CIP Æ Æ Æ Æ Æ Æ Æ 16 V D er ( XX9C61CIP Æ Æ Æ Æ Æ Æ Æ gg u b e D XX8F61CIP Æ Æ Æ Æ Æ Æ cuit Cir n- D I X8C61CIP Æ Æ Æ Æ Æ Æ Æ C ® I B A L XX7C61CIP Æ Æ Æ Æ Æ Æ MP e h e t X7C61CIP Æ Æ Æ Æ *Æ Æ Æ †Æ †Æ us o w t o h X26F61CIP Æ Æ **Æ **Æ **Æ on n o ati m XXXC61CIP Æ Æ Æ Æ Æ Æ Æ or nf or i X6C61CIP Æ Æ Æ Æ *Æ Æ Æ †Æ m f o c p. hi c X5C61CIP Æ Æ Æ Æ Æ Æ Æ cro mi ww.e. 00041CIP Æ Æ Æ Æ Æ Æ at wy dat XXXC21CIP ®MPLAB IntegratedDevelopment EnvironmentÆ ®MPLAB C17 C Compiler ®MPLAB C18 C Compiler TMMPASM Assembler/ TMMPLINKObject LinkerÆ ®MPLAB ICE In-Circuit EmulatorÆ TMICEPIC In-Circuit EmulatorÆ ®MPLAB ICD In-Circuit Debugger ®PICSTART Plus Entry LevelDevelopment ProgrammerÆ ®PRO MATE II Universal Device ProgrammerÆ TMPICDEM 1 Demonstration Board TMPICDEM 2 Demonstration Board TMPICDEM 3 Demonstration Board TMPICDEM 14A Demonstration Board TMPICDEM 17 Demonstration Board ® KLEvaluation KitEEOQ ®KL Transponder KitEEOQ TMmicroID Programmer’s Kit TM125 kHz microID Developer’s Kit TM125 kHz Anticollision microID Developer’s Kit 13.56 MHz Anticollision TMmicroID Developer’s Kit MCP2510 CAN Developer’s Kit Contact the Microchip Technology Inc. web site Contact Microchip Technology Inc. for availabilit slooT erawtfoS srotalumE reggubeD sremmargorP stiK lavE dna sdraoB omeD ***  2000 Microchip Technology Inc. Advanced Information DS30475A-page 309

PIC18CXX8 NOTES: DS30475A-page 310 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 25.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Voltage on RA4 with respect to Vss...............................................................................................................0V to +8.5V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20 mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by all ports (combined)....................................................................................................200 mA Maximum current sourced by all ports (combined)...............................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 311

PIC18CXX8 FIGURE 25-1: PIC18CXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0 V 5.5 V 5.0 V PIC18CXX8 4.5 V e g 4.2V a 4.0 V t l o 3.5 V V 3.0 V 2.5 V 2.0 V 40 MHz Frequency FIGURE 25-2: PIC18LCXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0 V 5.5 V 5.0 V 4.5 V PIC18LCXX8 e g 4.2V a 4.0 V t l o 3.5 V V 3.0 V 2.5 V 2.0 V 6 MHz 40 MHz Frequency FMAX = (20.0 MHz/V) (VDDAPPMIN - 2.5 V) + 6 MHz Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. DS30475A-page 312 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 25.1 DC Characteristics PIC18LCXX8 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18CXX8 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic/ Min Typ Max Units Conditions No. Device D001 VDD Supply Voltage PIC18LCXX8 2.5 — 5.5 V HS, XT, RC and LP osc mode D001 PIC18CXX8 4.2 — 5.5 V D002 VDR RAM Data Retention Voltage(1) 1.5 — — V D003 VPOR VDD Start Voltage to ensure inter- — — 0.7 V See section on Power-on Reset for nal Power-on Reset signal details D004 SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See section on Power-on Reset for Power-on Reset signal details D005 VBOR Brown-out Reset Voltage PIC18LCXX8 BORV1:BORV0 = 11 2.5 — 2.66 V BORV1:BORV0 = 10 2.7 — 2.86 V BORV1:BORV0 = 01 4.2 — 4.46 V BORV1:BORV0 = 00 4.5 — 4.78 V D005 PIC18CXX8 BORV1:BORV0 = 1x N.A. — N.A. V Not in operating voltage range of device BORV1:BORV0 = 01 4.2 — 4.46 V BORV1:BORV0 = 00 4.5 — 4.78 V Legend: Rows are shaded for improved readability. Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all fea- tures that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 313

PIC18CXX8 25.1 DC Characteristics (cont’d) PIC18LCXX8 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature-40°C≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18CXX8 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic/ Min Typ Max Units Conditions No. Device D010 IDD Supply Current(2,4) PIC18LCXX8 XT, RC, RCIO osc configurations — — 4 mA FOSC = 4 MHz, VDD = 2.5V D010 PIC18CXX8 XT, RC, RCIO osc configurations — — TBD mA FOSC = 4 MHz, VDD = 4.2V D010A PIC18LCXX8 — — 48 µA LP osc configuration FOSC = 32 kHz, VDD = 2.5V D010A PIC18CXX8 — — TBD µA LP osc configuration FOSC = 32 kHz, VDD = 4.2V D010C PIC18LCXX8 — — 45 mA EC, ECIO osc configurations, Fosc = 40 MHz, VDD = 5.5V D010C PIC18CXX8 — — 45 mA EC, ECIO osc configurations, Fosc = 40 MHz, VDD = 5.5V D013 PIC18LCXX8 HS osc configurations — — TBD mA Fosc = 6 MHz, VDD = 2.5V — — 50 mA Fosc = 25 MHz, VDD = 5.5V — — 50 mA HS + PLL osc configuration Fosc = 10 MHz, VDD = 5.5V D013 PIC18CXX8 — — 50 mA HS osc configurations Fosc = 25 MHz, VDD = 5.5V — — 50 mA HS + PLL osc configuration Fosc = 10 MHz, VDD = 5.5V D014 PIC18LCXX8 Timer1 osc configuration — — 48 µA FOSC = 32 kHz, VDD = 2.5V — — TBD µA FOSC = 32 kHz, VDD = 2.5V, 25°C D014 PIC18CXX8 OSCB osc configuration — — TBD µA FOSC = 32 kHz, VDD = 4.2V — — TBD µA FOSC = 32 kHz, VDD = 4.2V, 25°C Legend: Rows are shaded for improved readability. Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. DS30475A-page 314 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 25.1 DC Characteristics (cont’d) PIC18LCXX8 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature-40°C≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18CXX8 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic/ Min Typ Max Units Conditions No. Device D020 IPD Power-down Current(3) PIC18LCXX8 — <2.5 5 µA VDD = 2.5V, -40°C to +85°C — — 36 µA VDD = 5.5V, -40°C to +85°C — — TBD µA VDD = 2.5V, 25°C D020 PIC18CXX8 — <1 TBD µA VDD = 4.2V, -40°C to +85°C — — 36 µA VDD = 5.5V, -40°C to +85°C D020A — — TBD µA VDD = 4.2V, 25°C D021B — TBD TBD µA VDD = 4.2V, -40°C to +125°C — — 42 VDD = 5.5V, -40°C to +125°C D022 ∆IWDT Module Differential Current PIC18LCXX8 — — 12 µA VDD = 2.5V Watchdog Timer — — 25 µA VDD = 5.5V — — TBD µA VDD = 2.5V, 25°C D022 PIC18CXX8 — — 25 µA VDD = 5.5V, -40°C to +85°C Watchdog Timer — — TBD µA VDD = 5.5V, -40°C to +125°C — — TBD µA VDD = 4.2V, 25°C D022A ∆IBOR PIC18LCXX8 — — 50 µA VDD = 5.5V Brown-out Reset — — TBD µA VDD = 2.5V, 25°C D022A PIC18CXX8 — — 50 µA VDD = 5.5V, -40°C to +85°C Brown-out Reset — — TBD µA VDD = 5.5V, -40°C to +125° — — TBD µA VDD = 4.2V, 25°C D022B ∆ILVD PIC18LCXX8 — — 50 µA VDD = 2.5V Low Voltage Detect — — TBD µA VDD = 2.5V, 25°C D022B PIC18CXX8 — — TBD µA VDD = 4.2V, -40°C to +85°C Low Voltage Detect — — TBD µA VDD = 4.2V, -40°C to +125°C — — TBD µA VDD = 4.2V, 25°C D025 ∆IOSCB PIC18LCXX8 — — 3 µA VDD = 2.5V Timer1 Oscillator — — TBD µA VDD = 2.5V, 25°C D025 PIC18CXX8 — — TBD µA VDD = 4.2V, -40°C to +85°C Timer1 Oscillator — — TBD µA VDD = 4.2V, -40°C to +125°C — — TBD µA VDD = 4.2V, 25°C Legend: Rows are shaded for improved readability. Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 315

PIC18CXX8 25.2 DC Characteristics: PIC18CXX8 (Industrial, Extended) and PIC18LCXX8 (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic/ Min Max Units Conditions No. Device VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS 0.15VDD V VDD < 4.5V D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger buffer VSS 0.2VDD V RC3 and RC4 VSS 0.3VDD V D032 MCLR VSS 0.2VDD V D032A OSC1 (in XT, HS and LP modes) VSS 0.3VDD V and T1OSI D033 OSC1(in RC mode)(1) VSS 0.2VDD V VIH Input High Voltage I/O ports: D040 with TTL buffer 0.25VDD + VDD V VDD < 4.5V 0.8V D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V D041 with Schmitt Trigger buffer 0.8VDD VDD V RC3 and RC4 0.7VDD VDD V D042 MCLR 0.8VDD VDD V D042A OSC1 (in XT, HS and LP modes) 0.7VDD VDD V and T1OSI D043 OSC1 (RC mode)(1) 0.9VDD VDD V VHYS Hysteresis of Schmitt Trigger Inputs D050 TBD TBD V IIL Input Leakage Current(2,3) D060 I/O ports — ±1 µA VSS ≤ VPIN ≤ VDD, Pin at hi-impedance D061 MCLR — ±5 µA Vss ≤ VPIN ≤ VDD D063 OSC1 — ±5 µA Vss ≤ VPIN ≤ VDD IPU Weak Pull-up Current D070 IPURB PORTB weak pull-up current 50 400 µA VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30475A-page 316 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 25.2 DC Characteristics: PIC18CXX8 (Industrial, Extended) and PIC18LCXX8 (Industrial) (cont’d) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic/ Min Max Units Conditions No. Device VOL Output Low Voltage D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D080A — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC mode) -40°C to +85°C D083A — 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40°C to +125°C VOH Output High Voltage(3) D090 I/O ports VDD - 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C D090A VDD - 0.7 — V IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C D092 OSC2/CLKO VDD - 0.7 — V IOH = -1.3 mA, VDD = 4.5V, (RC mode) -40°C to +85°C D092A VDD - 0.7 — V IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C VOD Open-drain High Voltage D150 — 7.5 V RA4 pin Capacitive Loading Specs on Output Pins D101 CIO All I/O pins and OSC2 — 50 pF To meet the AC Timing Specifications (in RC mode) D102 CB SCL, SDA — 400 pF In I2C mode Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 317

PIC18CXX8 FIGURE 25-3: LOW VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be VLVD cleared in software) (LVDIF set by hardware) LVDIF TABLE 25-1: LOW VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic/ Min Max Units Conditions No. D420 VLVD LVD Voltage LVDL<3:0> = 0100 2.5 2.66 V LVDL<3:0> = 0101 2.7 2.86 V LVDL<3:0> = 0110 2.8 2.98 V LVDL<3:0> = 0111 3.0 3.2 V LVDL<3:0> = 1000 3.3 3.52 V LVDL<3:0> = 1001 3.5 3.72 V LVDL<3:0> = 1010 3.6 3.84 V LVDL<3:0> = 1011 3.8 4.04 V LVDL<3:0> = 1100 4.0 4.26 V LVDL<3:0> = 1101 4.2 4.46 V LVDL<3:0> = 1110 4.5 4.78 V DS30475A-page 318 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 25-2: EPROM PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +40°C Param. No. Sym Characteristic Min Max Units Conditions Internal Program Memory Programming Specs (Note 1) D110 VPP Voltage on MCLR/VPP pin 12.75 13.25 V (Note 2) D111 VDDP Supply voltage during 4.75 5.25 V programming D112 IPP Current into MCLR/VPP pin — 50 mA D113 IDDP Supply current during — 30 mA programming D114 TPROG Programming pulse width 100 1000 µs Terminated via internal/external interrupt or a RESET D115 TERASE EPROM erase time Device operation ≤ 3V 4 — hrs Device operation ≥ 3V TBD — hrs Note 1: These specifications are for the programming of the on-chip program memory EPROM through the use of the table write instructions. The complete programming specifications can be found in: PIC18CXX8 Program- ming Specifications (Literature number DS39028). 2: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 319

PIC18CXX8 25.3 AC (Timing) Characteristics 25.3.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created fol- lowing one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data-in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition DS30475A-page 320 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 25.3.2 TIMING CONDITIONS The temperature and voltages specified in Table25-3 apply to all timing specifications, unless otherwise noted. Figure25-4 specifies the load conditions for the timing specifications. TABLE 25-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial AC CHARACTERISTICS -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC spec Section25.1. LC parts operate for industrial temperatures only. FIGURE 25-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports  2000 Microchip Technology Inc. Advanced Information DS30475A-page 321

PIC18CXX8 25.3.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 25-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 25-4: EXTERNAL CLOCK TIMING REQUIREMENTS Param. No. Symbol Characteristic Min Max Units Conditions 1A Fosc External CLKIN DC 40 MHz XT osc Frequency(1) DC 40 MHz HS osc 4 10 MHz HS + PLL osc DC 40 kHz LP osc DC 40 MHz EC Oscillator Frequency(1) DC 4 MHz RC osc 0.1 4 MHz XT osc 4 25 MHz HS osc 4 10 MHz HS + PLL osc 5 200 kHz LP osc mode 1 Tosc External CLKIN Period(1) 250 — ns XT and RC osc 40 — ns HS osc 100 — ns HS + PLL osc 5 — µs LP osc 5 — ns EC Oscillator Period(1) 250 — ns RC osc 250 10,000 ns XT osc 100 10,000 ns HS osc 40 100 ns HS + PLL osc 5 — µs LP osc 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) 30 — ns XT osc TosH High or Low Time 2.5 — ns LP osc 10 — µs HS osc 4 TosR, External Clock in (OSC1) — 20 ns XT osc TosF Rise or Fall Time — 50 ns LP osc — 7.5 ns HS osc Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. DS30475A-page 322 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 25-5: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V) Param Symbol Characteristic Min Max Units Conditions No. 7 TPLL PLL Start-up Time — 2 ms (Lock Time) ∆CLK CLKOUT Stability (Jitter) using PLL -2 +2 %  2000 Microchip Technology Inc. Advanced Information DS30475A-page 323

PIC18CXX8 FIGURE 25-6: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure25-4 for load conditions. TABLE 25-6: CLKOUT AND I/O TIMING REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 10 TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns (1) 11 TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns (1) 12 TckR CLKOUT rise time — 35 100 ns (1) 13 TckF CLKOUT fall time — 35 100 ns (1) 14 TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns (1) 15 TioV2ckH Port in valid before CLKOUT ↑ 0.25TCY + 25 — — ns (1) 16 TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns (1) 17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 50 150 ns 18 TosH2ioI OSC1↑ (Q2 cycle) to PIC18CXX8 100 — — ns 18A Port input invalid PIC18LCXX8 200 — — ns (I/O in hold time) 19 TioV2osH Port input valid to OSC1↑ 0 — — ns (I/O in setup time) 20 TioR Port output rise time PIC18CXX8 — 10 25 ns 20A PIC18LCXX8 — — 60 ns 21 TioF Port output fall time PIC18CXX8 — 10 25 ns 21A PIC18LCXX8 — — 60 ns 22†† TINP INT pin high or low time TCY — — ns 23†† TRBP RB7:RB4 change INT high or low time TCY — — ns 24†† TRCP RC7:RC4 change INT high or low time 20 — — ns ††These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC mode where CLKO pin output is 4 x TOSC. DS30475A-page 324 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 25-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure25-4 for load conditions. FIGURE 25-8: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage stable 36 TABLE 25-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — µs 31 TWDT Watchdog Timer Time-out Period 7 18 33 ms (No Prescaler) 32 TOST Oscillation Start-up Timer Period 1024TOSC — 1024TOSC — TOSC = OSC1 period 33 TPWRT Power up Timer Period 28 72 132 ms 34 TIOZ I/O Hi-impedance from MCLR Low — 2 — µs or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — µs VDD ≤ BVDD (See D005) 36 TIVRST Time for Internal Reference — 20 50 µs Voltage to become stable  2000 Microchip Technology Inc. Advanced Information DS30475A-page 325

PIC18CXX8 FIGURE 25-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure25-4 for load conditions. TABLE 25-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — ns With Prescaler 10 — ns 41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — ns With Prescaler 10 — ns 42 Tt0P T0CKI Period No Prescaler TCY + 10 — ns With Prescaler Greater of: — ns N = prescale 20 nS or TCY + 40 value N (1, 2, 4,..., 256) 45 Tt1H T1CKI Synchronous, no prescaler 0.5TCY + 20 — ns High Synchronous, PIC18CXX8 10 — ns Time with prescaler PIC18LCXX8 25 — ns Asynchronous PIC18CXX8 30 — ns PIC18LCXX8 50 — ns 46 Tt1L T1CKI Synchronous, no prescaler 0.5TCY + 5 — ns Low Synchronous, PIC18CXX8 10 — ns Time with prescaler PIC18LCXX8 25 — ns Asynchronous PIC18CXX8 30 — ns PIC18LCXX8 TBD TBD ns 47 Tt1P T1CKI Synchronous Greater of: — ns N = prescale Input 20 nS or TCY + 40 value Period N (1, 2, 4, 8) Asynchronous 60 — ns Ft1 T1CKI oscillator input frequency range DC 50 kHz 48 Tcke2tmrI Delay from external T1CKI clock edge to 2Tosc 7Tosc — timer increment DS30475A-page 326 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 25-10:CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure25-4 for load conditions. TABLE 25-9: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param. Symbol Characteristic Min Max Units Conditions No. 50 TccL CCPx input low No Prescaler 0.5TCY + 20 — ns time With PIC18CXX8 10 — ns Prescaler PIC18LCXX8 20 — ns 51 TccH CCPx input No Prescaler 0.5TCY + 20 — ns high time With PIC18CXX8 10 — ns Prescaler PIC18LCXX8 20 — ns 52 TccP CCPx input period 3TCY + 40 — ns N = prescale N value (1,4 or 16) 53 TccR CCPx output fall time PIC18CXX8 — 25 ns PIC18LCXX8 — 45 ns 54 TccF CCPx output fall time PIC18CXX8 — 25 ns PIC18LCXX8 — 45 ns  2000 Microchip Technology Inc. Advanced Information DS30475A-page 327

PIC18CXX8 FIGURE 25-11: PARALLEL SLAVE PORT TIMING (PIC18C658 AND PIC18C858) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure25-4 for load conditions. TABLE 25-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18C658 AND PIC18C858) Param. Symbol Characteristic Min Max Units Conditions No. 62 TdtV2wrH Data-in valid before WR↑ or CS↑ 20 — ns (setup time) 25 — ns Extended Temp range 63 TwrH2dtI WR↑ or CS↑ to data-in invalid PIC18CXX8 20 — ns (hold time) PIC18LCXX8 35 — ns 64 TrdL2dtV RD↓ and CS↓ to data-out valid — 80 ns — 90 ns Extended Temp range 65 TrdH2dtI RD↑ or CS↓ to data-out invalid 10 30 ns 66 TibfINH Inhibit the IBF flag bit being cleared from — 3TCY ns WR↑ or CS↑ DS30475A-page 328 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 25-12:EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb Bit6 - - - - - -1 LSb 75, 76 SDI MSb In Bit6 - - - -1 LSb In 74 73 Note: Refer to Figure25-4 for load conditions. TABLE 25-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param. Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS↓ to SCK↓ or SCK↑ input TCY — ns TssL2scL 71 TscH SCK input high time Continuous 1.25TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK input low time Continuous 1.25TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the 1st clock edge of 1.5TCY + 40 — ns (Note 2) Byte2 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — ns TscL2diL 75 TdoR SDO data output rise time PIC18CXX8 — 25 ns PIC18LCXX8 — 45 ns 76 TdoF SDO data output fall time — 25 ns 78 TscR SCK output rise time PIC18CXX8 — 25 ns (Master mode) PIC18LCXX8 — 45 ns 79 TscF SCK output fall time (Master mode) — 25 ns 80 TscH2doV, SDO data output valid after PIC18CXX8 — 50 ns TscL2doV SCK edge PIC18LCXX8 — 100 ns Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 329

PIC18CXX8 FIGURE 25-13:EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb Bit6 - - - - - -1 LSb 75, 76 SDI MSb In Bit6 - - - -1 LSb In 74 Note: Refer to Figure25-4 for load conditions. TABLE 25-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 71 TscH SCK input high time Continuous 1.25TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK input low time Continuous 1.25TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the 1st clock edge of 1.5TCY + 40 — ns (Note 2) Byte2 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — ns TscL2diL 75 TdoR SDO data output rise time PIC18CXX8 — 25 ns PIC18LCXX8 — 45 ns 76 TdoF SDO data output fall time — 25 ns 78 TscR SCK output rise time PIC18CXX8 — 25 ns (Master mode) PIC18LCXX8 — 45 ns 79 TscF SCK output fall time (Master mode) — 25 ns 80 TscH2doV, SDO data output valid after PIC18CXX8 — 50 ns TscL2doV SCK edge PIC18LCXX8 — 100 ns 81 TdoV2scH, SDO data output setup to SCK edge TCY — ns TdoV2scL Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used. DS30475A-page 330 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 25-14:EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb Bit6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In Bit6 - - - -1 LSb In 74 73 Note: Refer to Figure25-4 for load conditions. TABLE 25-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE=0)) Parm. Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS↓ to SCK↓ or SCK↑ input TCY — ns TssL2scL 71 TscH SCK input high time Continuous 1.25TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK input low time Continuous 1.25TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40 — ns (Note 2) 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — ns TscL2diL 75 TdoR SDO data output rise time PIC18CXX8 — 25 ns PIC18LCXX8 45 ns 76 TdoF SDO data output fall time — 25 ns 77 TssH2doZ SS↑ to SDO output hi-impedance 10 50 ns 78 TscR SCK output rise time PIC18CXX8 — 25 ns (Master mode) PIC18LCXX8 45 ns 79 TscF SCK output fall time (Master mode) — 25 ns 80 TscH2doV, SDO data output valid after SCK PIC18CXX8 — 50 ns TscL2doV edge PIC18LCXX8 100 ns 83 TscH2ssH, SS ↑ after SCK edge 1.5TCY + 40 — ns TscL2ssH Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 331

PIC18CXX8 FIGURE 25-15:EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb Bit6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In Bit6 - - - -1 LSb In 74 Note: Refer to Figure25-4 for load conditions. TABLE 25-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Parm. Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS↓ to SCK↓ or SCK↑ input TCY — ns TssL2scL 71 TscH SCK input high time Continuous 1.25TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK input low time Continuous 1.25TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40 — ns (Note 2) 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — ns TscL2diL 75 TdoR SDO data output rise time PIC18CXX8 — 25 ns PIC18LCXX8 — 45 ns 76 TdoF SDO data output fall time — 25 ns 77 TssH2doZ SS↑ to SDO output hi-impedance 10 50 ns 78 TscR SCK output rise time PIC18CXX8 — 25 ns (Master mode) PIC18LCXX8 — 45 ns 79 TscF SCK output fall time (Master mode) — 25 ns 80 TscH2doV, SDO data output valid after SCK PIC18CXX8 — 50 ns TscL2doV edge PIC18LCXX8 — 100 ns 82 TssL2doV SDO data output valid after SS↓ PIC18CXX8 — 50 ns edge PIC18LCXX8 — 100 ns 83 TscH2ssH, SS ↑ after SCK edge 1.5TCY + 40 — ns TscL2ssH Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used. DS30475A-page 332 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 25-16:I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure25-4 for load conditions. TABLE 25-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Parm. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA START condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup time 400 kHz mode 600 — START condition 91 THD:STA START condition 100 kHz mode 4000 — ns After this period, the first Hold time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO STOP condition 100 kHz mode 4700 — ns Setup time 400 kHz mode 600 — 93 THD:STO STOP condition 100 kHz mode 4000 — ns Hold time 400 kHz mode 600 —  2000 Microchip Technology Inc. Advanced Information DS30475A-page 333

PIC18CXX8 FIGURE 25-17:I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure25-4 for load conditions. TABLE 25-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100 kHz mode 4.0 — µs PIC18CXX8 must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — µs PIC18CXX8 must operate at a minimum of 10 MHz SSP Module 1.5TCY — 101 TLOW Clock low time 100 kHz mode 4.7 — µs PIC18CXX8 must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — µs PIC18CXX8 must operate at a minimum of 10 MHz SSP module 1.5TCY — ns 102 TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 103 TF SDA and SCL fall 100 kHz mode — 300 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 90 TSU:STA START condition 100 kHz mode 4.7 — µs Only relevant for repeated setup time 400 kHz mode 0.6 — µs START condition 91 THD:STA START condition hold 100 kHz mode 4.0 — µs After this period the first clock time 400 kHz mode 0.6 — µs pulse is generated 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 µs 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO STOP condition 100 kHz mode 4.7 — µs setup time 400 kHz mode 0.6 — µs 109 TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns 110 TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free 400 kHz mode 1.3 — µs before a new transmission can start D102 Cb Bus capacitive loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tsu;DAT≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, TR max. + tsu;DAT=1000+250=1250ns (according to the standard mode I2C bus specification). DS30475A-page 334 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 25-18:MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure25-4 for load conditions. TABLE 25-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — Only relevant for Repeated START Setup time 400 kHz mode 2(TOSC)(BRG + 1) — ns condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — After this period, the first clock pulse is Hold time 400 kHz mode 2(TOSC)(BRG + 1) — ns generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — Setup time 400 kHz mode 2(TOSC)(BRG + 1) — ns 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — Hold time 400 kHz mode 2(TOSC)(BRG + 1) — ns 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 335

PIC18CXX8 FIGURE 25-19:MASTER SSP I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure25-4 for load conditions. TABLE 25-18: MASTER SSP I2C BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns Cb is specified to be from rise time 400 kHz mode 20 + 0.1Cb 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns Cb is specified to be from fall time 400 kHz mode 20 + 0.1Cb 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for setup time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated START 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms condition 91 THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period the first hold time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data input 100 kHz mode 0 — ns hold time 400 kHz mode 0 0.9 ms 1 MHz mode(1) TBD — ns 107 TSU:DAT Data input 100 kHz mode 250 — ns (Note 2) setup time 400 kHz mode 100 — ns 1 MHz mode(1) TBD — ns 92 TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ms setup time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output valid from 100 kHz mode — 3500 ns clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus free time 100 kHz mode 4.7 — ms Time the bus must be free 400 kHz mode 1.3 — ms before a new transmis- 1 MHz mode(1) TBD — ms sion can start D102 Cb Bus capacitive loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, parameter #102+ parameter #107=1000+250=1250ns (for 100 kHz mode). DS30475A-page 336 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 FIGURE 25-20:USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure25-4 for load conditions. TABLE 25-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 120 TckH2dtV SYNC XMIT (Master & Slave) Clock high to data-out valid PIC18CXX8 — 40 ns PIC18LCXX8 — 100 ns 121 Tckrf Clock out rise time and fall time PIC18CXX8 — 20 ns (Master mode) PIC18LCXX8 — 50 ns 122 Tdtrf Data-out rise time and fall time PIC18CXX8 — 20 ns PIC18LCXX8 — 50 ns  2000 Microchip Technology Inc. Advanced Information DS30475A-page 337

PIC18CXX8 FIGURE 25-21:USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure25-4 for load conditions. TABLE 25-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TdtV2ckl SYNC RCV (Master & Slave) Data-hold before CK ↓ (DT hold time) 10 — ns 126 TckL2dtl Data-hold after CK ↓ (DT hold time) 15 — ns DS30475A-page 338 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 TABLE 25-21: A/D CONVERTER CHARACTERISTICS: PIC18CXX8 (INDUSTRIAL, EXTENDED) PIC18LCXX8 (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit VREF = VDD ≥ 3.0V — — TBD bit VREF = VDD < 3.0V A03 EIL Integral linearity error — — <±1 LSb VREF = VDD ≥ 3.0V — — TBD LSb VREF = VDD < 3.0V A04 EDL Differential linearity error — — <±1 LSb VREF = VDD ≥ 3.0V — — TBD LSb VREF = VDD < 3.0V A05 EFS Full scale error — — <±1 LSb VREF = VDD ≥ 3.0V — — TBD LSb VREF = VDD < 3.0V A06 EOFF Offset error — — <±1 LSb VREF = VDD ≥ 3.0V — — TBD LSb VREF = VDD < 3.0V A10 — Monotonicity guaranteed(3) — VSS ≤ VAIN ≤ VREF A20 VREF Reference voltage 0V — — V A20A (VREFH - VREFL) 3V — — V For 10-bit resolution A21 VREFH Reference voltage High AVSS — AVDD + 0.3V V A22 VREFL Reference voltage Low AVSS - 0.3V — AVDD V A25 VAIN Analog input voltage AVSS - 0.3V — VREF + 0.3V V A30 ZAIN Recommended impedance of — — 10.0 kΩ analog voltage source A40 IAD A/D conversion PIC18CXX8 — 180 — µA Average current current (VDD) PIC18LCXXX — 90 — µA consumption when A/D is on(1). A50 IREF VREF input current(2) 10 — 1000 µA During VAIN acquisition. Based on differential of VHOLD to VAIN. To charge CHOLD see Section18.0. During A/D conversion — — 10 µA cycle. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is selected as reference input. 2: VSS ≤ VAIN ≤ VREF 3: The A/D conversion result either increases or remains constant as the analog input increases.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 339

PIC18CXX8 FIGURE 25-22:A/D CONVERSION TIMING BSF ADCON0, GO Note 2 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 25-22: A/D CONVERSION REQUIREMENTS Param Sym- Characteristic Min Max Units Conditions No. bol 130 TAD A/D clock period PIC18CXX8 1.6 20(5) µs TOSC based, VREF ≥ 3.0V PIC18LCXX8 3.0 20(5) µs TOSC based, VREF full range PIC18CXX8 2.0 6.0 µs A/D RC mode PIC18LCXX8 3.0 9.0 µs A/D RC mode 131 TCNV Conversion time 11 12 TAD (not including acquisition time)(1) 132 TACQ Acquisition time(3) 15 — µs -40°C ≤ Temp ≤ 125°C 10 — µs 0°C ≤ Temp ≤ 125°C 135 TSWC Switching time from convert → sample — (Note 4) 136 TAMP Amplifier settling time (Note 2) 1 — µs This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). Note 1: ADRES register may be read on the following TCY cycle. 2: See Section18.0 for minimum conditions, when input voltage has changed more than 1 LSb. 3: The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50 Ω. 4: On the next Q4 cycle of the device clock. 5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. DS30475A-page 340 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 26.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and Tables are not available at this time.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 341

PIC18CXX8 NOTES: DS30475A-page 342 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX PIC18C658-I/PT XXXXXXXXXX XXXXXXXXXX YYWWNNN 0017017 68-Lead PLCC Example XXXXXXXXXXXXXXXXX PIC18C658-I/L XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 0017017 80-Lead TQFP Example XXXXXXXXXXXX PIC18C858-I/PT XXXXXXXXXXXX YYWWNNN 0017017 Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code and traceability code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 343

PIC18CXX8 Package Marking Information (Cont’d) 84-Lead PLCC Example XXXXXXXXXXXXXXXXX PIC18C858-I/L XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 0017017 DS30475A-page 344 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45° α A c L φ A2 β A1 (F) Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 64 64 Pitch p .020 0.50 Pins per Side n1 16 16 Overall Height A .039 .043 .047 1.00 1.10 1.20 Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Foot Length L .018 .024 .030 0.45 0.60 0.75 Footprint (Reference) (F) .039 1.00 Foot Angle φ 0 3.5 7 0 3.5 7 Overall Width E .463 .472 .482 11.75 12.00 12.25 Overall Length D .463 .472 .482 11.75 12.00 12.25 Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10 Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10 Lead Thickness c .005 .007 .009 0.13 0.18 0.23 Lead Width B .007 .009 .011 0.17 0.22 0.27 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-085  2000 Microchip Technology Inc. Advanced Information DS30475A-page 345

PIC18CXX8 68-Lead Plastic Leaded Chip Carrier (L) –Square (PLCC) E E1 #leads=n1 D1 D n12 CH2 x 45° CH1 x 45° α A3 A2 A 32° c B1 β B p A1 D2 E2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 68 68 Pitch p .050 1.27 Pins per Side n1 17 17 Overall Height A .165 .173 .180 4.19 4.39 4.57 Molded Package Thickness A2 .145 .153 .160 3.68 3.87 4.06 Standoff § A1 .020 .028 .035 0.51 0.71 0.89 Side 1 Chamfer Height A3 .024 .029 .034 0.61 0.74 0.86 Corner Chamfer 1 CH1 .040 .045 .050 1.02 1.14 1.27 Corner Chamfer (others) CH2 .000 .005 .010 0.00 0.13 0.25 Overall Width E .985 .990 .995 25.02 25.15 25.27 Overall Length D .985 .990 .995 25.02 25.15 25.27 Molded Package Width E1 .950 .954 .958 24.13 24.23 24.33 Molded Package Length D1 .950 .954 .958 24.13 24.23 24.33 Footprint Width E2 .890 .920 .930 22.61 23.37 23.62 Footprint Length D2 .890 .920 .930 22.61 23.37 23.62 Lead Thickness c .008 .011 .013 0.20 0.27 0.33 Upper Lead Width B1 .026 .029 .032 0.66 0.74 0.81 Lower Lead Width B .013 .020 .021 0.33 0.51 0.53 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-049 DS30475A-page 346 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 B 1 n CH x 45° A α c β φ A2 L A1 (F) Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 80 80 Pitch p .020 0.50 Pins per Side n1 20 20 Overall Height A .039 .043 .047 1.00 1.10 1.20 Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Foot Length L .018 .024 .030 0.45 0.60 0.75 Footprint (Reference) (F) .039 1.00 Foot Angle φ 0 3.5 7 0 3.5 7 Overall Width E .541 .551 .561 13.75 14.00 14.25 Overall Length D .541 .551 .561 13.75 14.00 14.25 Molded Package Width E1 .463 .472 .482 11.75 12.00 12.25 Molded Package Length D1 .463 .472 .482 11.75 12.00 12.25 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .009 .011 0.17 0.22 0.27 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-092  2000 Microchip Technology Inc. Advanced Information DS30475A-page 347

PIC18CXX8 84-Lead Plastic Leaded Chip Carrier (L) –Square (PLCC) E E1 #leads=n1 D1 D n12 CH2 x 45° CH1 x 45° α A3 A2 A 32° c B1 β B p A1 D2 E2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 68 68 Pitch p .050 1.27 Pins per Side n1 17 17 Overall Height A .165 .173 .180 4.19 4.39 4.57 Molded Package Thickness A2 .145 .153 .160 3.68 3.87 4.06 Standoff § A1 .020 .028 .035 0.51 0.71 0.89 Side 1 Chamfer Height A3 .024 .029 .034 0.61 0.74 0.86 Corner Chamfer 1 CH1 .040 .045 .050 1.02 1.14 1.27 Corner Chamfer (others) CH2 .000 .005 .010 0.00 0.13 0.25 Overall Width E .985 .990 .995 25.02 25.15 25.27 Overall Length D .985 .990 .995 25.02 25.15 25.27 Molded Package Width E1 .950 .954 .958 24.13 24.23 24.33 Molded Package Length D1 .950 .954 .958 24.13 24.23 24.33 Footprint Width E2 .890 .920 .930 22.61 23.37 23.62 Footprint Length D2 .890 .920 .930 22.61 23.37 23.62 Lead Thickness c .008 .011 .013 0.20 0.27 0.33 Upper Lead Width B1 .026 .029 .032 0.66 0.74 0.81 Lower Lead Width B .013 .020 .021 0.33 0.51 0.53 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-093 DS30475A-page 348 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 APPENDIX A: DATA SHEET APPENDIX B: DEVICE REVISION HISTORY DIFFERENCES Revision A The differences between the PIC18CXX8 devices listed in this data sheet are shown in TableB-1. This is a new data sheet. TABLE B-1: DEVICE DIFFERENCES Feature PIC18C658 PIC18C858 Program Memory (Bytes) 32K 32K Data Memory (Bytes) 1.5K 1.5K A/D Channels 12 16 Parallel Slave Port (PSP) Yes Yes External Memory Capability No No Package TQFP 64-pin 80-pin Types PLCC 68-pin 84-pin JCERPACK 68-pin 84-pin  2000 Microchip Technology Inc. Advanced Information DS30475A-page 349

PIC18CXX8 APPENDIX C: DEVICE MIGRATIONS APPENDIX D: MIGRATING FROM OTHER PICMICRO This section is intended to describe the functional and electrical specification differences when migrating DEVICES between functionally similar devices (such as from a This discusses some of the issues in migrating from PIC16C74A to a PIC16C74B). other PICmicro devices to the PIC18CXXX family of Not Applicable devices. D.1 PIC16CXXX to PIC18CXXX See application note AN716. D.2 PIC17CXXX to PIC18CXXX See application note AN726. DS30475A-page 350 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 APPENDIX E: DEVELOPMENT TOOL VERSION REQUIREMENTS This lists the minimum requirements (software/firm- ware) of the specified development tool to support the devices listed in this data sheet. MPLAB-IDE: version 5.11 MPLAB-SIM: version 7.10 MPLAB-ICE 2000: PIC18CXX8 Processor Module: Part Number - PCM 18XB0 PIC18CXX8 Device Adapter: Socket Part Number 64-pin TQFP DVD18P2640 68-pin PLCC DVD18XL680 80-pin TQFP DVD18PQ800 84-pin PLCC DVD18XL840 MPLAB-ICD: Not Available PROMATE II: version 5.20 PICSTART Plus: version 2.20 MPASM: version 2.50 MPLAB-C18: version 1.00 CAN-TOOL: Not available at time of printing. Note: Please read all associated README.TXT files that are supplied with the develop- ment tools. These "read me" files will dis- cuss product support and any known limitations.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 351

PIC18CXX8 NOTES: DS30475A-page 352 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 INDEX A BSF ..........................269, 270, 271, 272, 273, 275, 276, 291 BTFSC .............................................................................274 A/D ...................................................................................227 BTFSS .............................................................................274 A/D Converter Flag (ADIF Bit) .................................230 BTG .................................................................................275 A/D Converter Interrupt, Configuring .......................231 Bus Activity Wake-up Interrupt ........................................225 ADCON0 Register ............................................227, 229 Bus Collision During a RESTART Condition ...................165 ADCON1 Register ............................................227, 228 Bus Collision During a START Condition ........................163 ADCON2 Register ....................................................227 Bus Collision During a STOP Condition ..........................166 ADRES Register ..............................................227, 230 Bus Off .............................................................................226 Analog Port Pins, Configuring ..................................233 Block Diagram ..........................................................230 C Block Diagram, Analog Input Model .........................231 CALL ................................................................................276 Configuring the Module ............................................231 CAN Buffers and Protocol Engine Block Diagram ...........184 Conversion Clock (TAD) ...........................................233 Capture (CCP Module) ....................................................128 Conversion Status (GO/DONE Bit) ..........................230 Block Diagram .........................................................129 Conversions .............................................................234 CCP Pin Configuration ............................................128 Converter Characteristics ........................................339 CCPR1H:CCPR1L Registers ..................................128 converter characteristics ..........................................318 Changing Between Capture Prescalers ..................129 Effects of a RESET ..................................................250 Software Interrupt ....................................................129 Equations .................................................................232 Timer1 Mode Selection ............................................128 Operation During SLEEP .........................................250 Capture/Compare/PWM (CCP) .......................................127 Sampling Requirements ...........................................232 Capture Mode. See Capture Sampling Time .........................................................232 CCP1 .......................................................................128 Special Event Trigger (CCP) ............................130, 234 CCPR1H Register ...........................................128 Timing Diagram ........................................................340 CCPR1L Register ............................................128 Absolute Maximum Ratings .............................................311 CCP2 .......................................................................128 Acknowledge Error ...........................................................223 CCPR2H Register ...........................................128 ADCON0 Register ....................................................227, 229 CCPR2L Register ............................................128 GO/DONE Bit ...........................................................230 Compare Mode. See Compare ADCON1 Register ....................................................227, 228 Interaction of Two CCP Modules .............................128 ADCON2 Register ............................................................227 PWM Mode. See PWM ADDLW ............................................................................267 Timer Resources .....................................................128 ADDWF ............................................................................267 Timing Diagram .......................................................327 ADDWFC .........................................................................268 Clocking Scheme ...............................................................45 ADRES Register ......................................................227, 230 CLRF .......................................................................277, 295 AKS ..................................................................................156 CLRWDT .........................................................................277 Analog-to-Digital Converter. See A/D Code Examples ANDLW ............................................................................268 Loading the SSPBUF Register ................................142 ANDWF ............................................................................269 Code Protection .......................................................251, 259 Assembler COMF ..............................................................................278 MPASM Assembler ..................................................305 Comparator Interrupts ......................................................241 B Comparator Operation .....................................................239 Comparator Reference ....................................................239 Baud Rate Generator .......................................................153 Compare (CCP Module) ..................................................130 BCF ..................................................................................270 Block Diagram .........................................................130 BF ....................................................................................156 CCP Pin Configuration ............................................130 Bit Error ............................................................................223 CCPR1H:CCPR1L Registers ..................................130 Bit Timing .........................................................................218 Software Interrupt ....................................................130 Bit Timing Configuration Registers ..................................222 Special Event Trigger ......................119, 125, 130, 234 Block Diagrams Timer1 Mode Selection ............................................130 Baud Rate Generator ...............................................153 Configuration Bits ............................................................251 Comparator I/O Operating Modes ............................238 Configuration Mode .........................................................210 PORTK .....................................................................108 Configuring the Voltage Reference ..................................243 SSP (SPI Mode) .......................................................141 CPFSEQ ..........................................................................278 Timer3 ......................................................................124 CPFSGT ..........................................................................279 BOR. See Brown-out Reset CPFSLT ...........................................................................279 BRG .................................................................................153 CRC Error ........................................................................223 Brown-out Reset (BOR) .............................................30, 251 CVRCON Register ...........................................................243 Timing Diagram ........................................................325  2000 Microchip Technology Inc. Advanced Information DS30475A-page 353

PIC18CXX8 D Bus Collision timing .................................................162 Clock Arbitration ......................................................161 Data Memory ......................................................................48 Clock Arbitration Timing (Master Transmit) .............161 General Purpose Registers ........................................48 General Call Address Support .................................150 Special Function Registers ........................................48 Master Mode 7-bit Reception timing ........................158 DAW .................................................................................280 Master Mode Operation ...........................................152 DC Characteristics ...........................313, 314, 315, 316, 317 Master Mode Start Condition ...................................154 DECF ...............................................................................280 Master Mode Transmission .....................................156 DECFSNZ ........................................................................281 Master Mode Transmit Sequence ............................152 DECFSZ ...........................................................................281 Multi-Master Mode ...................................................162 Device Differences ...........................................................349 Repeat START Condition timing ..............................155 Device Functionality .........................................................184 STOP Condition Receive or Transmit timing ...........160 Direct Addressing ...............................................................62 STOP Condition timing ............................................159 E Waveforms for 7-bit Reception ................................149 Electrical Characteristics ..................................................311 Waveforms for 7-bit Transmission ...........................149 Errata ...................................................................................7 ID Locations .............................................................251, 259 Error Detection .................................................................223 INCF ................................................................................282 Error Interrupt ...................................................................226 INCFSNZ .........................................................................283 Error Modes .....................................................................224 INCFSZ ............................................................................283 Error Modes and Error Counters ......................................223 In-Circuit Serial Programming (ICSP) ......................251, 259 Error States ......................................................................223 Indirect Addressing ............................................................62 FSR Register .............................................................61 F Information Processing Time ...........................................219 Filter/Mask Truth Table ....................................................216 Initiating Message Transmission .....................................211 Firmware Instructions .......................................................261 Instruction Cycle ................................................................45 Form Error ........................................................................223 Instruction Flow/Pipelining .................................................46 Instruction Format ............................................................263 G Instruction Set ..................................................................261 General Call Address Sequence ......................................150 ADDLW ....................................................................267 General Call Address Support .........................................150 ADDWF ....................................................................267 GOTO ...............................................................................282 ADDWFC .................................................................268 ANDLW ....................................................................268 H ANDWF ....................................................................269 Hard Synchronization .......................................................220 BCF .........................................................................270 BSF ..................269, 270, 271, 272, 273, 275, 276, 291 I BTFSC .....................................................................274 I/O Ports .............................................................................89 BTFSS .....................................................................274 I2C (SSP Module) .............................................................147 BTG .........................................................................275 ACK Pulse ................................................147, 148, 149 CALL ........................................................................276 Addressing ...............................................................148 CLRF ...............................................................277, 295 Block Diagram ..........................................................147 CLRWDT .................................................................277 Read/Write Bit Information (R/W Bit) ...............148, 149 COMF ......................................................................278 Reception .................................................................149 CPFSEQ ..................................................................278 Serial Clock (RC3/SCK/SCL) ...................................149 CPFSGT ..................................................................279 Slave Mode ..............................................................147 CPFSLT ...................................................................279 Timing Diagram, Data ..............................................334 DAW ........................................................................280 Timing Diagram, Start/Stop Bits ...............................333 DECF .......................................................................280 Transmission ............................................................149 DECFSNZ ................................................................281 I2C Master Mode Reception .............................................156 DECFSZ ..................................................................281 I2C Master Mode Restart Condition .................................155 GOTO ......................................................................282 I2C Module INCF ........................................................................282 Acknowledge Sequence timing ................................159 INCFSNZ .................................................................283 Baud Rate Generator ...............................................153 INCFSZ ....................................................................283 BRG Block Diagram .................................................153 IORLW .....................................................................284 BRG Reset due to SDA Collision .............................164 IORWF .....................................................................284 BRG Timing .............................................................153 MOVFP ....................................................................286 Bus Collision MOVLB ....................................................................285 Acknowledge ....................................................162 MOVLR ............................................................285, 286 Restart Condition .............................................165 MOVLW ...................................................................287 Restart Condition Timing (Case1) ....................165 MOVWF ...................................................................287 Restart Condition Timing (Case2) ....................165 MULLW ....................................................................288 START Condition .............................................163 MULWF ....................................................................288 Start Condition Timing .............................163, 164 NEGW .....................................................................289 STOP Condition ...............................................166 NOP .........................................................................289 STOP Condition Timing (Case1) .....................166 RETFIE ............................................................291, 292 STOP Condition Timing (Case2) .....................166 RETLW ....................................................................292 Transmit Timing ...............................................162 DS30475A-page 354 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 RETURN ..................................................................293 MPLAB Integrated Development RLCF ........................................................................293 Environment Software .....................................................305 RLNCF .....................................................................294 MULLW ............................................................................288 RRCF .......................................................................294 Multi-Master Mode ...........................................................162 RRNCF ....................................................................295 Multiply Examples SLEEP .....................................................................296 16 x 16 Routine .........................................................72 SUBLW ....................................................................297 16 x 16 Signed Routine .............................................73 SUBWF ............................................................297, 298 8 x 8 Routine .............................................................72 SUBWFB ..................................................................299 8 x 8 Signed Routine .................................................72 SWAPF ....................................................................300 MULWF ............................................................................288 TABLRD ...................................................................301 N TABLWT ..................................................................302 TSTFSZ ...................................................................303 NEGW .............................................................................289 XORLW ....................................................................303 NOP .................................................................................289 XORWF ....................................................................304 Normal Mode ...................................................................210 Summary Table ........................................................264 O INT Interrupt (RB0/INT). See Interrupt Sources INTCON Register OPTION_REG Register .....................................................64 RBIF Bit ......................................................................91 PS2:PS0 Bits ...........................................................115 Inter-Integrated Circuit. See I2C PSA Bit ....................................................................115 Interrupt Acknowledge .....................................................226 T0CS Bit ..................................................................115 Interrupt Sources .......................................................75, 251 T0SE Bit ..................................................................115 A/D Conversion Complete .......................................231 OSCCON ...........................................................................25 Capture Complete (CCP) .........................................129 OSCCON Register .............................................................25 Compare Complete (CCP) .......................................130 Oscillator Configuration .............................................21, 251 Interrupt-on-Change (RB7:RB4 ) ...............................91 HS ..............................................................................21 RB0/INT Pin, External ................................................88 HS + PLL ...................................................................21 SSP Receive/Transmit Complete ............................135 LP ..............................................................................21 TMR0 Overflow ........................................................116 RC .......................................................................21, 23 TMR1 Overflow ................................................117, 119 RCIO ..........................................................................21 TMR2 to PR2 Match ................................................122 XT ..............................................................................21 TMR2 to PR2 Match (PWM) ............................121, 132 Oscillator Tolerance .........................................................222 TMR3 Overflow ................................................123, 125 Oscillator, Timer1 .............................................117, 119, 123 USART Receive/Transmit Complete .......................167 Oscillator, Timer3 .............................................................125 Interrupts ..........................................................................225 Oscillator, WDT ................................................................255 Interrupts, Enable Bits Overview ..........................................................................183 CCP1 Enable (CCP1IE Bit) ......................................129 P Interrupts, Flag Bits Packaging ........................................................................343 A/D Converter Flag (ADIF Bit) .................................230 Parallel Slave Port (PSP) ...........................................95, 109 CCP1 Flag (CCP1IF Bit) ..........................128, 129, 130 Block Diagram .........................................................109 Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ........91 RE0/RD ...................................................................109 IORLW .............................................................................284 RE1/WR ...................................................................109 IORWF .............................................................................284 RE2/CS ....................................................................109 K Read Waveforms .....................................................111 KEELOQ Evaluation and Programming Tools ...................308 Select (PSPMODE Bit) ......................................95, 109 Timing Diagram .......................................................328 L Write Waveforms .....................................................111 Lengthening a Bit Period ..................................................221 Phase Buffer Segments ...................................................219 Listen Only Mode .............................................................210 PICDEM 1 Low Cost PICmicro Demo Board ...................307 Loopback Mode ...............................................................211 PICDEM 2 Low Cost PIC16CXX Demo Board ................307 PICDEM 3 Low Cost PIC16CXXX Demo Board ..............308 M PICSTART Plus Entry Level Development System .........307 Memory Organization Pin Functions Data Memory .............................................................48 AVDD ..........................................................................20 Program Memory .......................................................41 AVSS ..........................................................................20 Message Acceptance Filter ..............................................217 MCLR/VPP .................................................................12 Message Acceptance Filters and Masks .........................216 OSC1/CLKI ................................................................12 Message Reception .........................................................213 OSC2/CLKO ..............................................................12 Message Reception Flowchart .........................................215 RA0/AN0 ....................................................................13 MOVFP ............................................................................286 RA1/AN1 ....................................................................13 MOVLB ............................................................................285 RA2/AN2/VREF- .........................................................13 MOVLR ....................................................................285, 286 RA3/AN3/VREF+ ........................................................13 MOVLW ...........................................................................287 RA4/T0CKI ................................................................13 MOVWF ...........................................................................287 RA5/AN4/SS/LVDIN ..................................................13 RA6 ............................................................................13 RB0/INT0 ...................................................................14  2000 Microchip Technology Inc. Advanced Information DS30475A-page 355

PIC18CXX8 RB1/INT1 ...................................................................14 RK0 ............................................................................20 RB2/INT2 ...................................................................14 RK1 ............................................................................20 RB3/INT3 ...................................................................14 RK2 ............................................................................20 RB4 ............................................................................14 RK3 ............................................................................20 RB5 ............................................................................14 VDD ............................................................................20 RB6 ............................................................................14 VSS ............................................................................20 RB7 ............................................................................14 Pointer, FSR ......................................................................61 RC0/T1OSO/T1CKI ...................................................15 POR. See Power-on Reset RC1/T1OSI ................................................................15 PORTA RC2/CCP1 .................................................................15 Initialization ................................................................89 RC3/SCK/SCL ...........................................................15 PORTA Register ........................................................89 RC4/SDI/SDA ............................................................15 RA3:RA0 and RA5 Port Pins .....................................89 RC5/SDO ...................................................................15 RA4/T0CKI Pin ..........................................................90 RC6/TX/CK ................................................................15 TRISA Register ..........................................................89 RC7/RX/DT ................................................................15 PORTB RD0/AD0 ....................................................................16 Initialization ................................................................91 RD0/PSP0 ..................................................................16 PORTB Register ........................................................91 RD1/AD1 ....................................................................16 RB0/INT Pin, External ................................................88 RD1/PSP1 ..................................................................16 RB3:RB0 Port Pins ....................................................91 RD2/AD2 ....................................................................16 RB7:RB4 Interrupt on Change Flag (RBIF Bit) ..........91 RD2/PSP2 ..................................................................16 RB7:RB4 Port Pins ....................................................91 RD3/AD3 ....................................................................16 TRISB Register ..........................................................91 RD3/PSP3 ..................................................................16 PORTC RD4/AD4 ....................................................................16 Block Diagram ...........................................................93 RD4/PSP4 ..................................................................16 Initialization ................................................................93 RD5/AD5 ....................................................................16 PORTC Register ........................................................93 RD5/PSP5 ..................................................................16 RC3/SCK/SCL Pin ...................................................149 RD6/AD6 ....................................................................16 RC7/RX/DT Pin ........................................................169 RD6/PSP6 ..................................................................16 TRISC Register ..................................................93, 167 RD7/AD7 ....................................................................16 PORTD ............................................................................109 RD7/PSP7 ..................................................................16 Block Diagram ...........................................................95 RE0/ALE ....................................................................17 Initialization ................................................................95 RE0/RD ......................................................................17 Parallel Slave Port (PSP) Function ............................95 RE1/OE ......................................................................17 PORTD Register ........................................................95 RE1/WR .....................................................................17 TRISD Register ..........................................................95 RE2/CS ......................................................................17 PORTE RE2/WRL ...................................................................17 Block Diagram ...........................................................97 RE3/WRH ..................................................................17 Initialization ................................................................97 RE4 ............................................................................17 PORTE Register ........................................................97 RE5 ............................................................................17 PSP Mode Select (PSPMODE Bit) ....................95, 109 RE6 ............................................................................17 RE0/RD ...................................................................109 RE7/CCP2 .................................................................17 RE1/WR ...................................................................109 RF0/AN5 ....................................................................18 RE2/CS ....................................................................109 RF1/AN6 ....................................................................18 TRISE Register ..........................................................97 RF2/AN7 ....................................................................18 PORTF RF3/AN8 ....................................................................18 Block Diagram ...........................................................99 RF4/AN9 ....................................................................18 Block Diagram of RF7 Pin .......................................100 RF5/AN10 ..................................................................18 C1OUT, C2OUT ........................................................99 RF6/AN11 ..................................................................18 Initialization ................................................................99 RF7 ............................................................................18 PORTF Register ........................................................99 RG0/CANTX1 ............................................................19 RF6/RF3 and RF0 Pins Block Diagram ...................100 RG1/CANTX2 ............................................................19 TRISF ........................................................................99 RG2/CANRX ..............................................................19 PORTG RG3 ............................................................................19 Initialization ..............................................................101 RG4 ............................................................................19 PORTG ....................................................................101 RH0/A16 ....................................................................19 RG0/CANTX0 Pin Block Diagram ............................101 RH1/A17 ....................................................................19 RG1/CANTX1 Pin Block Diagram ............................102 RH2/A18 ....................................................................19 RG2 Pin Block Diagram ...........................................102 RH3/A19 ....................................................................19 RG4/RG3 Pins Block Diagram .................................102 RH4/AN12 ..................................................................19 TRISG ......................................................................101 RH5/AN13 ..................................................................19 PORTH RH6/AN14 ..................................................................19 Initialization ..............................................................104 RH7/AN15 ..................................................................19 PORTH ....................................................................104 RJ0/AD8 .....................................................................20 RH3/RH0 Pins Block Diagram .................................104 RJ1/AD9 .....................................................................20 RH7/RH4 Pins Block Diagram .................................104 RJ2/AD10 ...................................................................20 TRISH ......................................................................104 RJ3/AD11 ...................................................................20 DS30475A-page 356 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 PORTJ Registers Initialization ..............................................................106 SSPSTAT ................................................................136 PORTJ .....................................................................106 T3CON TRISJ .......................................................................106 Diagram ...........................................................123 PORTJ Block Diagram .....................................................106 Section ............................................................123 PORTK RESET .......................................................................29, 251 Initialization ..............................................................108 Timing Diagram .......................................................325 PORTK .....................................................................108 Resynchronization ...........................................................220 TRISK ......................................................................108 RETFIE ....................................................................291, 292 Postscaler, WDT RETLW ............................................................................292 Assignment (PSA Bit) ..............................................115 RETURN ..........................................................................293 Rate Select (PS2:PS0 Bits) .....................................115 Revision History ...............................................................349 Switching Between Timer0 and WDT ......................115 RLCF ...............................................................................293 Power-down Mode. See SLEEP RLNCF .............................................................................294 Power-on Reset (POR) ..............................................30, 251 RRCF ...............................................................................294 Oscillator Start-up Timer (OST) .........................30, 251 RRNCF ............................................................................295 Power-up Timer (PWRT) ...................................30, 251 S Time-out Sequence ....................................................31 Time-out Sequence on Power-up ........................32, 33 Sample Point ...................................................................219 Timing Diagram ........................................................325 SCI. See USART Prescaler, Capture ...........................................................129 SCK .................................................................................141 Prescaler, Timer0 .............................................................115 SDI ...................................................................................141 Assignment (PSA Bit) ..............................................115 SDO .................................................................................141 Rate Select (PS2:PS0 Bits) .....................................115 Serial Clock, SCK ............................................................141 Switching Between Timer0 and WDT ......................115 Serial Communication Interface. See USART Prescaler, Timer1 .............................................................118 Serial Data In, SDI ...........................................................141 Prescaler, Timer2 .............................................................132 Serial Data Out, SDO ......................................................141 PRO MAT“ II Universal Programmer ...............................307 Serial Peripheral Interface. See SPI Program Counter Shortening a Bit Period ....................................................221 PCL Register ..............................................................45 Simplified Block Diagram of On-Chip Reset Circuit ...........29 PCLATH Register ......................................................45 Slave Select Synchronization ..........................................144 Program Memory ...............................................................41 Slave Select, SS ..............................................................141 Program Verification ........................................................259 SLEEP .............................................................251, 257, 296 Programmable .................................................................251 Software Simulator (MPLAB-SIM) ...................................306 Programming Time Segments .........................................222 Special Event Trigger. See Compare Programming, Device Instructions ...................................261 Special Features of the CPU ...................................247, 251 Propagation Segment ......................................................219 Special Function Registers ................................................48 PSPCON Register SPI PSPMODE Bit ....................................................95, 109 Master Mode ............................................................143 PWM (CCP Module) ........................................................132 Serial Clock .............................................................141 Block Diagram ..........................................................132 Serial Data In ...........................................................141 CCPR1H:CCPR1L Registers ...................................132 Serial Data Out ........................................................141 Duty Cycle ................................................................132 Slave Select .............................................................141 Example Frequencies/Resolutions ..........................133 SPI Clock .................................................................143 Output Diagram ........................................................132 SPI Mode .................................................................141 Period .......................................................................132 SPI Module Setup for PWM Operation ........................................133 Slave Mode ..............................................................144 TMR2 to PR2 Match ........................................121, 132 Slave Select Synchronization ..................................144 Slave Synch Timing .................................................144 Q Slave Timing with CKE = 0 ......................................145 Q-Clock ............................................................................132 Slave Timing with CKE = 1 ......................................145 SS ....................................................................................141 R SSP .................................................................................135 RAM. See Data Memory Block Diagram (SPI Mode) ......................................141 RCSTA Register I2C Mode. See I2C SPEN Bit ..................................................................167 SPI Mode .................................................................141 Receive Buffers ................................................................213 SPI Mode. See SPI Receive Buffers Diagram .................................................214 SSPBUF ..................................................................143 Receive Interrupt ..............................................................225 SSPCON1 ...............................................................138 Receive Message Buffering .............................................213 SSPCON2 ...............................................................140 Receiver Error Passive ....................................................226 SSPSR ....................................................................143 Receiver Overrun .............................................................226 SSPSTAT ................................................................136 Receiver Warning ............................................................226 TMR2 Output for Clock Shift ............................121, 122 Register File .......................................................................48 SSP Module SPI Master Mode .....................................................143 SPI Slave Mode .......................................................144 SSPCON1 .......................................................................138 SSPCON2 .......................................................................140  2000 Microchip Technology Inc. Advanced Information DS30475A-page 357

PIC18CXX8 SSPOV .............................................................................156 Master Mode Transmit Clock Arbitration .................161 SSPSTAT .........................................................................136 Repeat Start Condition ............................................155 SSPSTAT Register Slave Synchronization .............................................144 R/W Bit .............................................................148, 149 Slow Rise Time ..........................................................33 Stuff Error .........................................................................223 SPI Mode Timing (Master Mode) SPI Mode SUBLW ............................................................................297 Master Mode Timing Diagram .........................143 SUBWF ....................................................................297, 298 SPI Mode Timing (Slave Mode with CKE = 0) .........145 SUBWFB ..........................................................................299 SPI Mode Timing (Slave Mode with CKE = 1) .........145 SWAPF ............................................................................300 Stop Condition Receive or Transmit ........................160 Synchronization ................................................................220 Time-out Sequence on Power-up ..............................32 Synchronization Rules .....................................................220 USART Asynchronous Master Transmission ..........174 Synchronization Segment ................................................219 USART Asynchronous Reception ............................176 Synchronous Serial Port. See SSP USART Synchronous Reception .............................179 USART Synchronous Transmission ........................178 T Wake-up from SLEEP via Interrupt ..........................258 TABLRD ...........................................................................301 Timing Diagrams and Specifications ...............................322 TABLWT ...........................................................................302 A/D Conversion ........................................................340 Time Quanta ....................................................................219 Brown-out Reset (BOR) ...........................................325 Timer Modules Capture/Compare/PWM (CCP) ...............................327 Timer3 CLKOUT and I/O .....................................................324 Block Diagram ..................................................124 External Clock ..........................................................322 Timer0 ..............................................................................113 I2C Bus Data ............................................................334 Clock Source Edge Select (T0SE Bit) ......................115 I2C Bus START/STOP Bits ......................................333 Clock Source Select (T0CS Bit) ...............................115 Oscillator Start-up Timer (OST) ...............................325 Overflow Interrupt ....................................................116 Parallel Slave Port (PSP) .........................................328 Prescaler. See Prescaler, Timer0 Power-up Timer (PWRT) .........................................325 Timing Diagram ........................................................326 Reset .......................................................................325 Timer1 ..............................................................................117 Timer0 and Timer1 ..................................................326 Block Diagram ..........................................................118 USART Synchronous Receive ( Master/Slave) .......338 Oscillator ..........................................................117, 119 USART Synchronous Transmission ( Master/Slave) 337 Overflow Interrupt ............................................117, 119 Watchdog Timer (WDT) ...........................................325 Prescaler. See Prescaler, Timer1 Transmit Interrupt ............................................................225 Special Event Trigger (CCP) ............................119, 130 Transmit Message Aborting .............................................211 Timing Diagram ........................................................326 Transmit Message Buffering ............................................211 TMR1H Register ......................................................117 Transmit Message Buffers ...............................................211 TMR1L Register .......................................................117 Transmit Message flowchart ............................................212 TMR3L Register .......................................................123 Transmit Message Priority ...............................................211 Timer2 Transmitter Error Passive ................................................226 Block Diagram ..........................................................122 Transmitter Warning ........................................................226 Postscaler. See Postscaler, Timer2 TRISE Register ..................................................................97 PR2 Register ....................................................121, 132 TSTFSZ ...........................................................................303 Prescaler. See Prescaler, Timer2 TXSTA Register SSP Clock Shift ................................................121, 122 BRGH Bit .................................................................169 TMR2 Register .........................................................121 U TMR2 to PR2 Match Interrupt ..................121, 122, 132 Timer3 ..............................................................................123 Universal Synchronous Asynchronous Receiver Oscillator ..........................................................123, 125 Transmitter. See USART Overflow Interrupt ............................................123, 125 USART .............................................................................167 Special Event Trigger (CCP) ....................................125 Asynchronous Mode ................................................173 TMR3H Register ......................................................123 Master Transmission .......................................174 Timing Diagrams Receive Block Diagram ...................................175 Acknowledge Sequence Timing ...............................159 Reception ........................................................176 Baud Rate Generator with Clock Arbitration ............153 Transmit Block Diagram ..................................173 BRG Reset Due to SDA Collision ............................164 Baud Rate Generator (BRG) ...................................169 Bus Collision Baud Rate Error, Calculating ...........................169 START Condition Timing .................................163 Baud Rate Formula .........................................169 Bus Collision During a RESTART Condition High Baud Rate Select (BRGH Bit) .................169 (Case 1) ...................................................................165 Sampling ..........................................................169 Bus Collision During a RESTART Condition Serial Port Enable (SPEN Bit) .................................167 (Case2) ....................................................................165 Synchronous Master Mode ......................................177 Bus Collision During a START Condition (SCL = 0) 164 Reception ........................................................179 Bus Collision During a STOP Condition ...................166 Timing Diagram, Synchronous Receive ..........338 Bus Collision for Transmit and Acknowledge ...........162 Timing Diagram, Synchronous Transmission ..337 I2C Bus Data ............................................................336 Transmission ...................................................178 I2C Master Mode First Start bit timing ......................154 Synchronous Slave Mode ........................................180 I2C Master Mode Reception timing ..........................158 I2C Master Mode Transmission timing .....................157 DS30475A-page 358 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 W Wake-up from SLEEP ..............................................251, 257 Timing Diagram ........................................................258 Watchdog Timer (WDT) ...........................................251, 255 Block Diagram ..........................................................256 Postscaler. See Postscaler, WDT Programming Considerations ..................................255 RC Oscillator ............................................................255 Time-out Period .......................................................255 Timing Diagram ........................................................325 Waveform for General Call Address Sequence ...............150 WCOL ..............................................................154, 156, 159 WCOL Status Flag ...........................................................154 WWW, On-Line Support ......................................................7 X XORLW ............................................................................303 XORWF ............................................................................304  2000 Microchip Technology Inc. Advanced Information DS30475A-page 359

PIC18CXX8 NOTES: DS30475A-page 360 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 ON-LINE SUPPORT Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides Microchip provides on-line support on the Microchip system users a listing of the latest versions of all of World Wide Web (WWW) site. Microchip’s development systems software products. The web site is used by Microchip as a means to make Plus, this line provides information on how customers files and information easily available to customers. To can receive any currently available upgrade kits.The view the site, the user must have access to the Internet Hot Line Numbers are: and a web browser, such as Netscape or Microsoft 1-800-755-2345 for U.S. and most of Canada, and Explorer. Files are also available for FTP download from our FTP site. 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your 001024 favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User’s Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: Trademarks: The Microchip name, logo, PIC, PICmicro, (cid:127) Latest Microchip Press Releases PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, (cid:127) Technical Support Section with Frequently Asked MPLAB and The Embedded Control Solutions Company Questions are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. (cid:127) Design Tips Total Endurance, ICSP, In-Circuit Serial Programming, (cid:127) Device Errata FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICDEM, ICEPIC and Migratable (cid:127) Job Postings Memory are trademarks and SQTP is a service mark of (cid:127) Microchip Consultant Program Member Listing Microchip in the U.S.A. (cid:127) Links to other useful web sites related to All other trademarks mentioned herein are the property of Microchip Products their respective companies. (cid:127) Conferences for products, Development Systems, technical information and more (cid:127) Listing of seminars and events  2000 Microchip Technology Inc. Advanced Information DS30475A-page 361

PIC18CXX8 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18CXX8 Literature Number: DS30475A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30475A-page362 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 PIC18CXX8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales offic.e PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18LC658 - I/L 301 = Industrial temp., PLCC Range package, Extended VDD limits, QTP pattern #301. b) PIC18LC858 - I/PT = Industrial temp., TQFP package, Extended VDD limits. Device PIC18CXX8(1), PIC18CXX8T(2); c) PIC18C658 - E/L = Extended temp., PLCC P I CV1D8DL rCaXngXe5 (41.)2, VP ItCo1 58.L5CVXX8T(2); package, normal VDD limits. VDD range 2.5V to 5.5V Temperature Range I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Note1: C = Standard Voltage Range Package CL = Windowed JCERPACK LC = Wide Voltage Range PT = TQFP (Thin Quad Flatpack) 2: T = in tape and reel PLCC, and TQFP L = PLCC packages only. 3: CL devices are UV erasable and can be pro- grammed to any device configuration. CL devices meet the electrical requirement of Pattern QTP, SQTP, Code or Special Requirements each oscillator type (including LC devices). (blank otherwise) * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2000 Microchip Technology Inc. Advanced Information DS30475A-page 363

PIC18CXX8 NOTES: DS30475A-page 364 Advanced Information  2000 Microchip Technology Inc.

PIC18CXX8 NOTES:  2000 Microchip Technology Inc. Advanced Information DS30475A-page 365

WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC (continued) Corporate Office China - Beijing Singapore 2355 West Chandler Blvd. Microchip Technology Beijing Office Microchip Technology Singapore Pte Ltd. Chandler, AZ 85224-6199 Unit 915 200 Middle Road Tel: 480-792-7200 Fax: 480-792-7277 New China Hong Kong Manhattan Bldg. #07-02 Prime Centre Technical Support: 480-792-7627 No. 6 Chaoyangmen Beidajie Singapore, 188980 Web Address: http://www.microchip.com Beijing, 100027, No. China Tel: 65-334-8870 Fax: 65-334-8850 Rocky Mountain Tel: 86-10-85282100 Fax: 86-10-85282104 Taiwan 2355 West Chandler Blvd. China - Shanghai Microchip Technology Taiwan Chandler, AZ 85224-6199 Microchip Technology Shanghai Office 11F-3, No. 207 Tel: 480-792-7966 Fax: 480-792-7456 Room 701, Bldg. B Tung Hua North Road Far East International Plaza Taipei, 105, Taiwan Atlanta No. 317 Xian Xia Road Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 500 Sugar Mill Road, Suite 200B Shanghai, 200051 EUROPE Atlanta, GA 30350 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Tel: 770-640-0034 Fax: 770-640-0307 Hong Kong Denmark Boston Microchip Asia Pacific Microchip Technology Denmark ApS 2 Lan Drive, Suite 120 RM 2101, Tower 2, Metroplaza Regus Business Centre Westford, MA 01886 223 Hing Fong Road Lautrup hoj 1-3 Tel: 978-692-3838 Fax: 978-692-3821 Kwai Fong, N.T., Hong Kong Ballerup DK-2750 Denmark Chicago Tel: 852-2401-1200 Fax: 852-2401-3431 Tel: 45 4420 9895 Fax: 45 4420 9910 333 Pierce Road, Suite 180 India France Itasca, IL 60143 Microchip Technology Inc. Arizona Microchip Technology SARL Tel: 630-285-0071 Fax: 630-285-0075 India Liaison Office Parc d’Activite du Moulin de Massy Dallas Divyasree Chambers 43 Rue du Saule Trapu 4570 Westgrove Drive, Suite 160 1 Floor, Wing A (A3/A4) Batiment A - ler Etage Addison, TX 75001 No. 11, O’Shaugnessey Road 91300 Massy, France Tel: 972-818-7423 Fax: 972-818-2924 Bangalore, 560 025, India Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Dayton Tel: 91-80-2290061 Fax: 91-80-2290062 Germany Two Prestige Place, Suite 130 Japan Arizona Microchip Technology GmbH Miamisburg, OH 45342 Microchip Technology Intl. Inc. Gustav-Heinemann Ring 125 Tel: 937-291-1654 Fax: 937-291-9175 Benex S-1 6F D-81739 Munich, Germany Detroit 3-18-20, Shinyokohama Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Tri-Atria Office Building Kohoku-Ku, Yokohama-shi Italy 32255 Northwestern Highway, Suite 190 Kanagawa, 222-0033, Japan Arizona Microchip Technology SRL Farmington Hills, MI 48334 Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Centro Direzionale Colleoni Tel: 248-538-2250 Fax: 248-538-2260 Korea Palazzo Taurus 1 V. Le Colleoni 1 Los Angeles Microchip Technology Korea 20041 Agrate Brianza 1Ir8vi2n0e1, CVoAn 9K2a6r1m2an, Suite 1090 1S6a8m-1su, Yngo-uDnognbgo, BKladngg. n3a Fmlo-oKru MTeilla: 3n,9 -It0a3ly9 -65791-1 Fax: 39-039-6899883 Tel: 949-263-1888 Fax: 949-263-1338 Seoul, Korea United Kingdom New York Tel: 82-2-554-7200 Fax: 82-2-558-5934 Arizona Microchip Technology Ltd. 505 Eskdale Road 150 Motor Parkway, Suite 202 Winnersh Triangle Hauppauge, NY 11788 Wokingham Tel: 631-273-5305 Fax: 631-273-5335 Berkshire, England RG41 5TU San Jose Tel: 44 118 921 5869 Fax: 44-118 921-5820 Microchip Technology Inc. 2107 North First Street, Suite 590 10/01/00 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Microchip received QS-9000 quality system Toronto certification for its worldwide headquarters, 6285 Northam Drive, Suite 108 design and wafer fabrication facilities in Mississauga, Ontario L4V 1X5, Canada Chandler and Tempe, Arizona in July 1999. The Tel: 905-673-0699 Fax: 905-673-6509 Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 11/00 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS30475A-page 366 Advanced Information  2000 Microchip Technology Inc.