PIC16(L)F1782/3 28-Pin 8-Bit Advanced Analog Flash Microcontroller High-Performance RISC CPU: Extreme Low-Power Management PIC16LF1782/3 with XLP: • Only 49 Instructions • Operating Speed: • Sleep mode: 50nA @ 1.8V, typical - DC – 32MHz clock input • Watchdog Timer: 500nA @ 1.8V, typical - DC – 125 ns instruction cycle • Timer1 Oscillator: 500nA @ 32kHz • Interrupt Capability with Automatic Context • Operating Current: Saving - 8A @ 32kHz, 1.8V, typical • 16-Level Deep Hardware Stack with optional - 32A/MHz @ 1.8V, typical Overflow/Underflow Reset Analog Peripheral Features: • Direct, Indirect and Relative Addressing modes: • Two full 16-bit File Select Registers (FSRs) • Analog-to-Digital Converter (ADC): - FSRs can read program and data memory - Fully differential 12-bit converter - Up to 75 ksps conversion rate Memory Features: - 11 single-ended channels - 5 differential channels • Up to 4 KW Flash Program Memory: - Positive and negative reference selection - Self-programmable under software control • 8-bit Digital-to-Analog Converter (DAC): - Programmable code protection - Output available externally - Programmable write protection - Positive and negative reference selection • 256 Bytes of Data EEPROM - Internal connections to comparators, op amps, • Up to 512 Bytes of RAM Fixed Voltage Reference (FVR) and ADC High Performance PWM Controller: • Three High-Speed Comparators: - 50 ns response time @ VDD = 5V • Two Programmable Switch Mode Controller - Rail-to-rail inputs (PSMC) modules: - Software selectable hysteresis - Digital and/or analog feedback control of - Internal connection to op amps, FVR and DAC PWM frequency and pulse begin/end times • Two Operational Amplifiers: - 16-bit Period, Duty Cycle and Phase - Rail-to-rail inputs/outputs - 16 ns clock resolution - High/Low selectable Gain Bandwidth Product - Supports Single PWM, Complementary, - Internal connection to DAC and FVR Push-Pull and 3-phase modes of operation - Dead-band control with 8-bit counter • Fixed Voltage Reference (FVR): - Auto-shutdown and restart - 1.024V, 2.048V and 4.096V output levels - Leading and falling edge blanking - Internal connection to ADC, comparators and DAC - Burst mode I/O Features: • 25 I/O Pins and 1 Input-only Pin: • High current sink/source for LED drivers • Individually programmable interrupt-on-change pins • Individually programmable weak pull-ups • Individual input level selection • Individually programmable slew rate control • Individually programmable open drain outputs  2011-2014 Microchip Technology Inc. DS40001579E-page 1

PIC16(L)F1782/3 Digital Peripheral Features: General Microcontroller Features: • Timer0: 8-Bit Timer/Counter with 8-Bit • Power-Saving Sleep mode Programmable Prescaler • Power-on Reset (POR) • Enhanced Timer1: • Power-up Timer (PWRT) - 16-bit timer/counter with prescaler • Oscillator Start-up Timer (OST) - External Gate Input mode • Brown-out Reset (BOR) with Selectable Trip Point - Dedicated low-power 32kHz oscillator driver • Extended Watchdog Timer (WDT) • Timer2: 8-Bit Timer/Counter with 8-Bit Period • In-Circuit Serial ProgrammingTM (ICSPTM) Register, Prescaler and Postscaler • In-Circuit Debug (ICD) • Two Capture/Compare/PWM modules (CCP): • Enhanced Low-Voltage Programming (LVP) - 16-bit capture, maximum resolution 12.5 ns • Operating Voltage Range: - 16-bit compare, max resolution 31.25 ns - 1.8V to 3.6V (PIC16LF1782/3) - 10-bit PWM, max frequency 32 kHz - 2.3V to 5.5V (PIC16F1782/3) • Master Synchronous Serial Port (SSP) with SPI and I2CTM with: - 7-bit address masking - SMBus/PMBusTM compatibility • Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART): - RS-232, RS-485 and LIN compatible - Auto-baud detect - Auto-wake-up on start Oscillator Features: • Operate up to 32 MHz from Precision Internal Oscillator: - Factory calibrated to ±1%, typical - Software selectable frequency range from 32MHz to 31kHz • 31kHz Low-Power Internal Oscillator • 32.768 kHz Timer1 Oscillator: - Available as system clock - Low-power RTC • External Oscillator Block with: - 4 crystal/resonator modes up to 32 MHz using 4x PLL - 3 external clock modes up to 32 MHz • 4x Phase-Locked Loop (PLL) • Fail-Safe Clock Monitor: - Detect and recover from external oscillator failure • Two-Speed Start-up: - Minimize latency between code execution and external oscillator start-up DS40001579E-page 2  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 PIC16(L)F178X Family Types h c Device Data Sheet Index Program MemoryFlash (words) Data EEPROM(bytes) Data SRAM(bytes) (2)I/O’s 12-bit ADC (ch) Comparators Operational Amplifiers DAC (8/5-bit) Timers(8/16-bit) ogrammable SwitMode Controllers(PSMC) CCP EUSART 2C™/SPI)MSSP (I (1)Debug XLP r P PIC12(L)F1782 (1) 2048 256 256 25 11 3 2 1/0 2/1 2 2 1 1 I Y PIC16(L)F1783 (1) 4096 256 512 25 11 3 2 1/0 2/1 2 2 1 1 I Y PIC16(L)F1784 (2) 4096 256 512 36 15 4 3 1/0 2/1 3 3 1 1 I Y PIC16(L)F1786 (2) 8192 256 1024 25 11 4 2 1/0 2/1 3 3 1 1 I Y PIC16(L)F1787 (2) 8192 256 1024 36 15 4 3 1/0 2/1 3 3 1 1 I Y PIC16(L)F1788 (3) 16384 256 2048 25 11 4 2 1/3 2/1 4 3 1 1 I Y PIC16(L)F1789 (3) 16384 256 2048 36 15 4 3 1/3 2/1 4 3 1 1 I Y Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header. 2: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS40001579 PIC16(L)F1782/3 Data Sheet, 28-Pin Flash, 8-bit Advanced Analog MCUs. 2: DS40001637 PIC16(L)F1784/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Advanced Analog MCUs. 3: DS40001675 PIC16(L)F1788/9 Data Sheet, 28/40/44-Pin Flash, 8-bit Advanced Analog MCUs. Note: For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office.  2011-2014 Microchip Technology Inc. DS40001579E-page 3

PIC16(L)F1782/3 Pin Diagram – 28-Pin SPDIP, SOIC, SSOP VPP/MCLR/RE3 1 28 RB7/ICSPDAT RA0 2 27 RB6/ICSPCLK RA1 3 26 RB5 RA2 4 25 RB4 RA3 5 3 24 RB3 2/ RA4 6 78 23 RB2 1 RA5 7 F 22 RB1 VSS 8 6(L) 21 RB0 RA7 9 C1 20 VDD RA6 10 PI 19 VSS RC0 11 18 RC7 RC1 12 17 RC6 RC2 13 16 RC5 RC3 14 15 RC4 Note: See Table1 for the location of all peripheral functions. Pin Diagram – 28-Pin QFN, UQFN P PTK VAL R/DC LPP CSS MCC 103/7/I6/I54 AAEBBBB RRRRRRR 8765432 2222222 RA2 1 21 RB3 RA3 2 20 RB2 RA4 3 19 RB1 RA5 4 PIC16(L)F1782/3 18 RB0 VSS 5 17 VDD RA7 6 16 VSS RA6 7 15 RC7 01234 8911111 0123456 CCCCCCC RRRRRRR Note: See Table1 for the location of all peripheral functions. DS40001579E-page 4  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 PIN ALLOCATION TABLE TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1782/3) P O I/O Pin SPDIP, SOIC, SS 28-Pin QFN, UQFN ADC ADC Reference Comparator Operation Amplifiers 8-bit DAC Timers PSMC CCP EUSART MSSP Interrupt Pull-up Basic 8- 2 RA0 2 27 AN0 — C1IN0- — — — — — — — IOC Y — C2IN0- C3IN0- RA1 3 28 AN1 — C1IN1- OPA1OUT — — — — — — IOC Y — C2IN1- C3IN1- RA2 4 1 AN2 VREF- C1IN0+ — DACOUT1 — — — — — IOC Y — C2IN0+ DACVREF- C3IN0+ RA3 5 2 AN3 VREF+ C1IN1+ — DACVREF+ — — — — — IOC Y — RA4 6 3 — — C1OUT OPA1IN+ — T0CKI — — — — IOC Y — RA5 7 4 AN4 — C2OUT OPA1IN- — — — — — SS IOC Y — RA6 10 7 — — C2OUT(1) — — — — — — — IOC Y OSC2/ CLKOUT RA7 9 6 — — — — — — PSMC1CLK — — — IOC Y OSC1/ PSMC2CLK CLKIN RB0 21 18 AN12 — C2IN1+ — — — PSMC1IN CCP1(1) — — INT/ Y — PSMC2IN IOC RB1 22 19 AN10 — C1IN3- OPA2OUT — — — — — — IOC Y — C2IN3- C3IN3- RB2 23 20 AN8 — — OPA2IN- — — — — — — IOC Y CLKR RB3 24 21 AN9 — C1IN2- OPA2IN+ — — — CCP2(1) — — IOC Y — C2IN2- C3IN2- RB4 25 22 AN11 — C3IN1+ — — — — — — — IOC Y — RB5 26 23 AN13 — C3OUT — — T1G — — — SDO(1) IOC Y — RB6 27 24 — — — — — — — — TX(1) SDI(1) IOC Y ICSPCLK CK(1) SDA(1) RB7 28 25 — — — — DACOUT2 — — — RX(1) SCK(1) IOC Y ICSPDAT DT(1) SCL(1) RC0 11 8 — — — — — T1OSO PSMC1A — — — IOC Y — T1CKI RC1 12 9 — — — — — T1OSI PSMC1B CCP2 — — IOC Y — RC2 13 10 — — — — — — PSMC1C CCP1 — — IOC Y — RC3 14 11 — — — — — — PSMC1D — — SCK IOC Y — SCL RC4 15 12 — — — — — — PSMC1E — — SDI IOC Y — SDA RC5 16 13 — — — — — — PSMC1F — — SDO IOC Y — RC6 17 14 — — — — — — PSMC2A — TX — IOC Y — CK RC7 18 15 — — — — — — PSMC2B — RX — IOC Y — DT RE3 1 26 — — — — — — — — — — IOC Y MCLR/ VPP VDD 20 17 — — — — — — — — — — — — VDD VSS 8, 5, — — — — — — — — — — — — VSS 19 16 Note 1: Alternate pin function selected with the APFCON1 (Register13-1) register.  2011-2014 Microchip Technology Inc. DS40001579E-page 5

PIC16(L)F1782/3 Table of Contents 1.0 Device Overview..........................................................................................................................................................................7 2.0 Enhanced Mid-Range CPU........................................................................................................................................................13 3.0 Memory Organization.................................................................................................................................................................15 4.0 Device Configuration..................................................................................................................................................................40 5.0 Resets........................................................................................................................................................................................46 6.0 Oscillator Module (with Fail-Safe Clock Monitor).......................................................................................................................54 7.0 Reference Clock Module............................................................................................................................................................72 8.0 Interrupts....................................................................................................................................................................................75 9.0 Power-Down Mode (Sleep)........................................................................................................................................................88 10.0 Low Dropout (LDO) Voltage Regulator......................................................................................................................................92 11.0 Watchdog Timer (WDT).............................................................................................................................................................93 12.0 Data EEPROM and Flash Program Memory Control.................................................................................................................97 13.0 I/O Ports...................................................................................................................................................................................110 14.0 Interrupt-On-Change................................................................................................................................................................132 15.0 Fixed Voltage Reference (FVR)...............................................................................................................................................136 16.0 Temperature Indicator Module.................................................................................................................................................139 17.0 Analog-to-Digital Converter (ADC) Module..............................................................................................................................141 18.0 Operational Amplifier (OPA) Modules......................................................................................................................................156 19.0 Digital-to-Analog Converter (DAC) Module..............................................................................................................................159 20.0 Comparator Module..................................................................................................................................................................164 21.0 Timer0 Module.........................................................................................................................................................................173 22.0 Timer1 Module with Gate Control.............................................................................................................................................176 23.0 Timer2 Module.........................................................................................................................................................................187 24.0 Programmable Switch Mode Control (PSMC)..........................................................................................................................191 25.0 Capture/Compare/PWM Modules............................................................................................................................................247 26.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................257 27.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................311 28.0 In-Circuit Serial Programming™ (ICSP™)...............................................................................................................................340 29.0 Instruction Set Summary..........................................................................................................................................................342 30.0 Electrical Specifications............................................................................................................................................................356 31.0 DC and AC Characteristics Graphs and Charts.......................................................................................................................389 32.0 Development Support...............................................................................................................................................................413 33.0 Packaging Information..............................................................................................................................................................418 The Microchip Web Site.....................................................................................................................................................................432 Customer Change Notification Service..............................................................................................................................................432 Customer Support..............................................................................................................................................................................432 Product Identification System.............................................................................................................................................................433 DS40001579E-page 6  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 1.0 DEVICE OVERVIEW The PIC16(L)F1782/3 are described within this data sheet. The block diagram of these devices are shown in Figure1-1. The available peripherals are shown in Table1-1, and the pin out descriptions are shown in Table1-2. TABLE 1-1: DEVICE PERIPHERAL SUMMARY 2 3 4 6 7 8 9 8 8 8 8 8 8 8 7 7 7 7 7 7 7 1 1 1 1 1 1 1 F F F F F F F Peripheral L) L) L) L) L) L) L) 6( 6( 6( 6( 6( 6( 6( 1 1 1 1 1 1 1 C C C C C C C PI PI PI PI PI PI PI Analog-to-Digital Converter (ADC) ● ● ● ● ● ● ● Fixed Voltage Reference (FVR) ● ● ● ● ● ● ● Reference Clock Module ● ● ● ● ● ● ● Temperature Indicator ● ● ● ● ● ● ● Capture/Compare/PWM (CCP/ECCP) Modules CCP1 ● ● ● ● ● ● ● CCP2 ● ● ● ● ● ● ● CCP3 ● ● ● ● ● Comparators C1 ● ● ● ● ● ● ● C2 ● ● ● ● ● ● ● C3 ● ● ● ● ● ● ● C4 ● ● ● ● ● Digital-to-Analog Converter (DAC) (8-bit DAC) D1 ● ● ● ● ● ● ● (5-bit DAC) D2 ● (5-bit DAC) D3 ● (5-bit DAC) D4 ● Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) EUSART ● ● ● ● ● ● ● Master Synchronous Serial Ports MSSP ● ● ● ● ● ● ● Op Amp Op Amp 1 ● ● ● ● ● ● ● Op Amp 2 ● ● ● ● ● ● ● Op Amp 3 ● ● ● Programmable Switch Mode Controller (PSMC) PSMC1 ● ● ● ● ● ● ● PSMC2 ● ● ● ● ● ● ● PSMC3 ● ● ● ● ● PSMC4 ● ● Timers Timer0 ● ● ● ● ● ● ● Timer1 ● ● ● ● ● ● ● Timer2 ● ● ● ● ● ● ●  2011-2014 Microchip Technology Inc. DS40001579E-page 7

PIC16(L)F1782/3 FIGURE 1-1: PIC16(L)F1782/3 BLOCK DIAGRAM Program Flash Memory RAM PORTA PORTB CLKOUT Timing Generation HFINTOSC/ CLKIN CPU PORTC LFINTOSC Oscillator Figure2-1 PORTE MCLR Op Amps PSMCs Timer0 Timer1 Timer2 MSSP Comparators Temp. ADC Indicator 12-Bit FVR DAC CCPs EUSART Note 1: See applicable chapters for more information on peripherals. DS40001579E-page 8  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/C1IN0-/C2IN0-/C3IN0- RA0 TTL/ST CMOS General purpose I/O. AN0 AN — A/D Channel 0 input. C1IN0- AN — Comparator C1 negative input. C2IN0- AN — Comparator C2 negative input. C3IN0- AN — Comparator C3 negative input. RA1/AN1/C1IN1-/C2IN1-/ RA1 TTL/ST CMOS General purpose I/O. C3IN1-/OPA1OUT AN1 AN — A/D Channel 1 input. C1IN1- AN — Comparator C1 negative input. C2IN1- AN — Comparator C2 negative input. C3IN1- AN — Comparator C3 negative input. OPA1OUT — AN Operational Amplifier 1 output. RA2/AN2/C1IN0+/C2IN0+/ RA2 TTL/ST CMOS General purpose I/O. C3IN0+/DACOUT1/VREF-/ AN2 AN — A/D Channel 2 input. DACVREF- C1IN0+ AN — Comparator C1 positive input. C2IN0+ AN — Comparator C2 positive input. C3IN0+ AN — Comparator C3 positive input. DACOUT1 — AN Digital-to-Analog Converter output. VREF- AN — A/D Negative Voltage Reference input. DACVREF- AN — Digital-to-Analog Converter negative reference. RA3/AN3/VREF+/C1IN1+/ RA3 TTL/ST CMOS General purpose I/O. DACVREF+ AN3 AN — A/D Channel 3 input. VREF+ AN — A/D Voltage Reference input. C1IN1+ AN — Comparator C1 positive input. DACVREF+ AN — Digital-to-Analog Converter positive reference. RA4/C1OUT/OPA1IN+/T0CKI RA4 TTL/ST CMOS General purpose I/O. C1OUT — CMOS Comparator C1 output. OPA1IN+ AN — Operational Amplifier 1 non-inverting input. T0CKI ST — Timer0 clock input. RA5/AN4/C2OUT(1)/OP1INA-/ RA5 TTL/ST CMOS General purpose I/O. SS AN4 AN — A/D Channel 4 input. C2OUT — CMOS Comparator C2 output. OPA1IN- AN — Operational Amplifier 1 inverting input. SS ST — Slave Select input. RA6/C2OUT/OSC2/CLKOUT RA6 TTL/ST CMOS General purpose I/O. C2OUT — CMOS Comparator C2 output. OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. RA7/PSMC1CLK/ RA7 TTL/ST CMOS General purpose I/O. PSMC2CLK/OSC1/CLKIN PSMC1CLK ST — PSMC1 clock input. PSMC2CLK ST — PSMC2 clock input. OSC1 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKIN st — External clock input (EC mode). Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register13-1. 2: All pins have Interrupt-on-Change functionality.  2011-2014 Microchip Technology Inc. DS40001579E-page 9

PIC16(L)F1782/3 TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RB0/AN12/C2IN1+/PSMC1IN/ RB0 TTL/ST CMOS General purpose I/O. PSMC2IN/CCP1(1)/INT AN12 AN — A/D Channel 12 input. C2IN1+ AN — Comparator C2 positive input. PSMC1IN ST — PSMC1 Event Trigger input. PSMC2IN ST — PSMC2 Event Trigger input. CCP1 ST CMOS Capture/Compare/PWM1. INT ST — External interrupt. RB1/AN10/C1IN3-/C2IN3-/ RB1 TTL/ST CMOS General purpose I/O. C3IN3-/OPA2OUT AN10 AN — A/D Channel 10 input. C1IN3- AN — Comparator C1 negative input. C2IN3- AN — Comparator C2 negative input. C3IN3- AN — Comparator C3 negative input. OPA2OUT — AN Operational Amplifier 2 output. RB2/AN8/OPA2IN-/CLKR RB2 TTL/ST CMOS General purpose I/O. AN8 AN — A/D Channel 8 input. OPA2IN- AN — Operational Amplifier 2 inverting input. CLKR — CMOS Clock output. RB3/AN9/C1IN2-/C2IN2-/ RB3 TTL/ST CMOS General purpose I/O. C3IN2-/OPA2IN+/CCP2(1) AN9 AN — A/D Channel 9 input. C1IN2- AN — Comparator C1 negative input. C2IN2- AN — Comparator C2 negative input. C3IN2- AN — Comparator C3 negative input. OPA2IN+ AN — Operational Amplifier 2 non-inverting input. CCP2 ST CMOS Capture/Compare/PWM2. RB4/AN11/C3IN1+ RB4 TTL/ST CMOS General purpose I/O. AN11 AN — A/D Channel 11 input. C3IN1+ AN — Comparator C3 positive input. RB5/AN13/C3OUT/T1G/SDO(1) RB5 TTL/ST CMOS General purpose I/O. AN13 AN — A/D Channel 13 input. C3OUT — CMOS Comparator C3 output. T1G ST — Timer1 gate input. SDO — CMOS SPI data output. RB6/TX(1)/CK(1)/SDI(1)/SDA(1)/ RB6 TTL/ST CMOS General purpose I/O. ICSPCLK TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. SDI ST — SPI data input. SDA I2C OD I2C™ data input/output. ICSPCLK ST — Serial Programming Clock. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register13-1. 2: All pins have Interrupt-on-Change functionality. DS40001579E-page 10  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RB7/DACOUT2/RX(1)/DT(1)/ RB7 TTL/ST CMOS General purpose I/O. SCK(1)/SCL(1)/ICSPDAT DACOUT2 — AN Voltage Reference output. RX ST — USART asynchronous input. DT ST CMOS USART synchronous data. SCK ST CMOS SPI clock. SCL I2C OD I2C™ clock. ICSPDAT ST CMOS ICSP™ Data I/O. RC0/T1OSO/T1CKI/PSMC1A RC0 TTL/ST CMOS General purpose I/O. T1OSO XTAL XTAL Timer1 oscillator connection. T1CKI ST — Timer1 clock input. PSMC1A — CMOS PSMC1 output A. RC1/T1OSI/PSMC1B/CCP2(1) RC1 TTL/ST CMOS General purpose I/O. T1OSI XTAL XTAL Timer1 oscillator connection. PSMC1B — CMOS PSMC1 output B. CCP2 ST CMOS Capture/Compare/PWM2. RC2/PSMC1C/CCP1(1) RC2 TTL/ST CMOS General purpose I/O. PSMC1C — CMOS PSMC1 output C. CCP1 ST CMOS Capture/Compare/PWM1. RC3/PSMC1D/SCK(1)/SCL(1) RC3 TTL/ST CMOS General purpose I/O. PSMC1D — CMOS PSMC1 output D. SCK ST CMOS SPI clock. SCL I2C OD I2C™ clock. RC4/PSMC1E/SDI(1)/SDA(1) RC4 TTL/ST CMOS General purpose I/O. PSMC1E — CMOS PSMC1 output E. SDI ST — SPI data input. SDA I2C OD I2C™ data input/output. RC5/PSMC1F/SDO(1) RC5 TTL/ST CMOS General purpose I/O. PSMC1F — CMOS PSMC1 output F. SDO — CMOS SPI data output. RC6/PSMC2A/TX(1)/CK(1) RC6 TTL/ST CMOS General purpose I/O. PSMC2A — CMOS PSMC2 output A. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. RC7/PSMC2B/RX(1)/DT(1) RC7 TTL/ST CMOS General purpose I/O. PSMC2B — CMOS PSMC2 output B. RX ST — USART asynchronous input. DT ST CMOS USART synchronous data. RE3/MCLR/VPP RE3 TTL/ST — General purpose input. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register13-1. 2: All pins have Interrupt-on-Change functionality.  2011-2014 Microchip Technology Inc. DS40001579E-page 11

PIC16(L)F1782/3 2.0 ENHANCED MID-RANGE CPU Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read This family of devices contain an enhanced mid-range program and data memory. 8-bit CPU core. The CPU has 49 instructions. Interrupt • Automatic Interrupt Context Saving capability includes automatic context saving. The • 16-level Stack with Overflow and Underflow hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and • File Select Registers • Instruction Set FIGURE 2-1: CORE BLOCK DIAGRAM 15 CCCooonnnfffiiiggguuurrraaatttiiiooonnn 15 888 DDDaaatttaaa BBBuuusss PPPrrrooogggrrraaammm CCCooouuunnnttteeerrr Flash X Program U M Memory 1886 -LLLeeevvveeell lSS Sttaataccckkk RAM (((111335---bbbiiittt))) PPPrrrooogggrrraaammm 111444 Program Memory 12 RAM Addr BBBuuusss Read (PMR) AAAddddddrrr MMMUUUXXX IIInnnssstttrrruuuccctttiiiooonnn Rrreeeggg Indirect DDDiiirrreeecccttt AAAddddddrrr 777 Addr 5 12 12 15 BFFSSSRRR Rrreeeggg FFFSSSRRR 0rr eeRggeg FFFSSSRRR1 rrReeeggg 15 SSSTTTAAATTTUUUSSS Rrreeeggg 888 333 MMMUUUXXX Power-up Timer IIInnnssstttrrruuuccctttiiiooonnn Oscillator DDDeeecccooodddeee a &&nd Start-up Timer AAALLLUUU CCCooonnntttrrrooolll Power-on OSC1/CLKIN Reset 888 TTTiiimmmiiinnnggg Watchdog OSC2/CLKOUT GGGeeennneeerrraaatttiiiooonnn Timer W reg Brown-out Reset IIInnnttteeerrrnnnaaalll OOOsssccciiillllllaaatttooorrr BBBllloooccckkk VVVDDDDDD VVVSSSSSS DS40001579E-page 12  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See 8.5 “Automatic Context Saving”, for more information. 2.2 16-level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Under- flow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a soft- ware Reset. See Section3.5 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section3.6 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section29.0 “Instruction Set Summary” for more details.  2011-2014 Microchip Technology Inc. DS40001579E-page 13

PIC16(L)F1782/3 3.0 MEMORY ORGANIZATION The following features are associated with access and control of program memory and data memory: These devices contain the following types of memory: • PCL and PCLATH • Program Memory • Stack - Configuration Words • Indirect Addressing - Device ID - User ID 3.1 Program Memory Organization - Flash Program Memory The enhanced mid-range core has a 15-bit program • Data Memory counter capable of addressing a 32K x 14 program - Core Registers memory space. Table3-1 shows the memory sizes - Special Function Registers implemented for the PIC16(L)F1782/3 family. Accessing - General Purpose RAM a location above these boundaries will cause a - Common RAM wrap-around within the implemented memory space. • Data EEPROM memory(1) The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures3-1 and3-2). Note1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section12.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) Last Program Memory Address PIC16(L)F1782 2,048 07FFh PIC16(L)F1783 4,096 0FFFh DS40001579E-page 14  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 3-1: PROGRAM MEMORY MAP FIGURE 3-2: PROGRAM MEMORY MAP AND STACK FOR AND STACK FOR PIC16(L)F1782 PIC16(L)F1783 PC<14:0> PC<14:0> CALL, CALLW 15 CALL, CALLW 15 RETURN, RETLW RETURN, RETLW Interrupt, RETFIE Interrupt, RETFIE Stack Level 0 Stack Level 0 Stack Level 1 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h Interrupt Vector 0004h On-chip 0005h 0005h Program Page 0 Page 0 Memory 07FFh On-chip 07FFh Program 0800h 0800h Rollover to Page 0 Memory Wraps to Page 0 Page 1 0FFFh 1000h Rollover to Page 0 Wraps to Page 0 Wraps to Page 0 Rollover to Page 0 Rollover to Page 1 7FFFh 7FFFh  2011-2014 Microchip Technology Inc. DS40001579E-page 15

PIC16(L)F1782/3 3.1.1 READING PROGRAM MEMORY AS EXAMPLE 3-2: ACCESSING PROGRAM DATA MEMORY VIA FSR There are two methods of accessing constants in constants program memory. The first method is to use tables of RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW instructions. The second method is to set an RETLW DATA2 FSR to point to the program memory. RETLW DATA3 my_function 3.1.1.1 RETLW Instruction ;… LOTS OF CODE… The RETLW instruction can be used to provide access MOVLW LOW constants to tables of constants. The recommended way to create MOVWF FSR1L such a table is shown in Example3-1. MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] EXAMPLE 3-1: RETLW INSTRUCTION ;THE PROGRAM MEMORY IS IN W constants BRW ;Add Index in W to ;program counter to ;select data RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example3-2 demonstrates accessing the program memory via an FSR. The high directive will set bit<7> if a label points to a location in program memory. DS40001579E-page 16  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 3.2 Data Memory Organization 3.2.1 CORE REGISTERS The data memory is partitioned in 32 memory banks The core registers contain the registers that directly with 128 bytes in a bank. Each bank consists of affect the basic operation. The core registers occupy (Figure3-3): the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These • 12 core registers registers are listed below in Table3-2. For detailed • 20 Special Function Registers (SFR) information, see Table3-7. • Up to 80 bytes of General Purpose RAM (GPR) • 16 bytes of common RAM TABLE 3-2: CORE REGISTERS The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be Addresses BANKx accessed either directly (via instructions that use the x00h or x80h INDF0 file registers) or indirectly via the two File Select x01h or x81h INDF1 Registers (FSR). See Section3.6 “Indirect x02h or x82h PCL Addressing” for more information. x03h or x83h STATUS Data memory uses a 12-bit address. The upper 5 bits x04h or x84h FSR0L of the address define the Bank address and the lower x05h or x85h FSR0H 7 bits select the registers/RAM in that bank. x06h or x86h FSR1L x07h or x87h FSR1H x08h or x88h BSR x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON  2011-2014 Microchip Technology Inc. DS40001579E-page 17

PIC16(L)F1782/3 3.2.1.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register3-1, contains: as ‘000u u1uu’ (where u = unchanged). • the arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, • the Reset status SWAPF and MOVWF instructions are used to alter the The STATUS register can be the destination for any STATUS register, because these instructions do not instruction, like any other register. If the STATUS affect any Status bits. For other instructions not register is the destination for an instruction that affects affecting any Status bits (Refer to Section29.0 the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”). disabled. These bits are set or cleared according to the Note: The C and DC bits operate as Borrow and device logic. Furthermore, the TO and PD bits are not Digit Borrow out bits, respectively, in writable. Therefore, the result of an instruction with the subtraction. STATUS register as destination may be different than intended. 3.3 Register Definitions: Status REGISTER 3-1: STATUS: STATUS REGISTER U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — — — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. DS40001579E-page 18  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 3.3.1 SPECIAL FUNCTION REGISTER FIGURE 3-3: BANKED MEMORY PARTITIONING The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function 7-bit Bank Offset Memory Region Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the 00h operation of the peripherals are described in the Core Registers appropriate peripheral chapter of this data sheet. (12 bytes) 0Bh 3.3.2 GENERAL PURPOSE RAM 0Ch There are up to 80bytes of GPR in each data memory Special Function Registers bank. The Special Function Registers occupy the 20 (20 bytes maximum) bytes after the core registers of every data memory 1Fh bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 20h 3.3.2.1 Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section3.6.2 “Linear Data Memory” for more information. General Purpose RAM (80 bytes maximum) 3.3.3 COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh  2011-2014 Microchip Technology Inc. DS40001579E-page 19

D 3.3.4 DEVICE MEMORY MAPS P S 4 0 The memory maps for Bank 0 through Bank 31 are shown in the tables in this section. I 0 C 0 1 5 7 TABLE 3-3: PIC16(L)F1782/3 MEMORY MAP (BANKS 0-7) 1 9 E-p BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 6 ag 000h 080h 100h 180h 200h 280h 300h 380h ( e L 2 Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers 0 (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) ) F 00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA 1 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB 7 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh — 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC 8 00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh — 010h PORTE 090h TRISE 110h — 190h — 210h WPUE 290h — 310h — 390h INLVLE 2 011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP / 3 012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN 013h — 093h — 113h CM2CON0 193h EEDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF 014h PIR4 094h PIE4 114h CM2CON1 194h EEDATH 214h SSP1STAT 294h — 314h — 394h IOCBP 015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSP1CON1 295h — 315h — 395h IOCBN 016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSP1CON2 296h — 316h — 396h IOCBF 017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(2) 217h SSP1CON3 297h — 317h — 397h IOCCP 018h T1CON 098h OSCTUNE 118h DACCON0 198h — 218h — 298h CCPR2L 318h — 398h IOCCN 019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h — 299h CCPR2H 319h — 399h IOCCF 01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah — 39Ah — 01Bh PR2 09Bh ADRESL 11Bh — 19Bh SPBRG 21Bh — 29Bh — 31Bh — 39Bh — 01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch — 01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh IOCEP 01Eh — 09Eh ADCON1 11Eh CM3CON0 19Eh TXSTA 21Eh — 29Eh — 31Eh — 39Eh IOCEN 01Fh — 09Fh ADCON2 11Fh CM3CON1 19Fh BAUDCON 21Fh — 29Fh — 31Fh — 39Fh IOCEF 020h 0A0h 120h 1A0h 220h 2A0h 320h General Purpose 3A0h General General General General General General Register Purpose Purpose 13Fh Purpose Purpose Purpose Purpose 32Fh 16 Bytes(1) Unimplemented  20 8R0e gBiystteesr 8R0e gBiystteesr 140h 8R0e gBiystteesr 8R0 eBgyitsetse(r1) 8R0 eBgyitsetse(r1) 80R eBgyitsetse(r1) 330h Unimplemented Read as ‘0’ 11 Read as ‘0’ -2 06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh 01 070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h 4 M Co7m0mh o–n 7 RFhAM 7A0chc e–s 7sFesh 7A0chc e–s 7sFesh 7A0chc e–s 7sFesh 7A0chc e–s 7sFesh 7A0chc e–s 7sFesh 7A0chc e–s 7sFesh 7A0chc e–s 7sFesh ic ro 07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh c h ip Legend: = Unimplemented data memory locations, read as ‘0’. T e Note 1: PIC16(L)F1783 only. c h 2: PIC16F1782/3 only. n o lo g y In c .

 TABLE 3-4: PIC16(L)F1782/3 MEMORY MAP (BANKS 8-31) 2 0 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 1 1 -2 400h Core Registers 480h Core Registers 500h Core Registers 580h Core Registers 600h Core Registers 680h Core Registers 700h Core Registers 780h Core Registers 0 1 (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) 4 M 40Bh 48Bh 50Bh 58Bh 60Bh 68Bh 70Bh 78Bh ic 40Ch 48Ch 50Ch Unimplemented 58Ch 60Ch 68Ch 70Ch 78Ch ro Read as ‘0’ ch 510h ip T 511h OPA1CON e 512h — c hn Unimplemented Unimplemented 513h OPA2CON Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented olo Read as ‘0’ Read as ‘0’ 514h Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ g Read as ‘0’ y 519h Inc 51Ah CLKRCON . 51Bh Unimplemented Read as ‘0’ 46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh 470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23 800h Core Registers 880h Core Registers 900h Core Registers 980h Core Registers A00h Core Registers A80h Core Registers B00h Core Registers B80h Core Registers (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) 80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh 80Ch 88Ch 90Ch 98Ch A0Ch A8Ch B0Ch B8Ch Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented See Table3-5 Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh 870h 8F0h 970h 9F0h A70h AF0h B70h BF0h Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM P (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) I 87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh C BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31 1 C00h 6 Core Registers C80h Core Registers D00h Core Registers D80h Core Registers E00h Core Registers E80h Core Registers F00h Core Registers F80h Core Registers (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) ( C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh F8Bh L C0Ch C8Ch D0Ch D8Ch E0Ch E8Ch F0Ch F8Ch ) DS Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented See Table3-6 F 4 Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 00 C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh 1 0 1 C70h CF0h D70h DF0h E70h EF0h F70h FF0h 7 57 Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM 9 (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses 8 E -p 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 2 a C7Fh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh ge / 2 Legend: = Unimplemented data memory locations, read as ‘0’ 3 1

PIC16(L)F1782/3 TABLE 3-5: PIC16(L)F1782/3 MEMORY TABLE 3-6: PIC16(L)F1782/3 MEMORY MAP (BANK 16 DETAILS) MAP (BANK 31 DETAILS) BANK 16 BANK 16 BANK 31 811h PSMC1CON 831h PSMC2CON F8Ch Unimplemented 812h PSMC1MDL 832h PSMC2MDL Read as ‘0’ FE3h 813h PSMC1SYNC 833h PSMC2SYNC FE4h STATUS_SHAD 814h PSMC1CLK 834h PSMC2CLK FE5h WREG_SHAD 815h PSMC1OEN 835h PSMC2OEN 816h PSMC1POL 836h PSMC2POL FE6h BSR_SHAD 817h PSMC1BLNK 837h PSMC2BLNK FE7h PCLATH_SHAD 818h PSMC1REBS 838h PSMC2REBS FE8h FSR0L_SHAD 819h PSMC1FEBS 839h PSMC2FEBS FE9h FSR0H_SHAD 81Ah PSMC1PHS 83Ah PSMC2PHS FEAh FSR1L_SHAD 81Bh PSMC1DCS 83Bh PSMC2DCS FEBh FSR1H_SHAD 81Ch PSMC1PRS 83Ch PSMC2PRS FECh — 81Dh PSMC1ASDC 83Dh PSMC2ASDC FEDh STKPTR 81Eh PSMC1ASDD 83Eh PSMC2ASDD FEEh TOSL 81Fh PSMC1ASDS 83Fh PSMC2ASDS FEFh TOSH 820h PSMC1INT 840h PSMC2INT 821h PSMC1PHL 841h PSMC2PHL 822h PSMC1PHH 842h PSMC2PHH 823h PSMC1DCL 843h PSMC2DCL 824h PSMC1DCH 844h PSMC2DCH 825h PSMC1PRL 845h PSMC2PRL 826h PSMC1PRH 846h PSMC2PRH 827h PSMC1TMRL 847h PSMC2TMRL 828h PSMC1TMRH 848h PSMC2TMRH 829h PSMC1DBR 849h PSMC2DBR 82Ah PSMC1DBF 84Ah PSMC2DBF 82Bh PSMC1BLKR 84Bh PSMC2BLKR 82Ch PSMC1BLKF 84Ch PSMC2BLKF 82Dh PSMC1FFA 84Dh PSMC1FFA 82Eh PSMC1STR0 84Eh PSMC2STR0 82Fh PSMC1STR1 84Fh PSMC2STR1 830h — 840h Unimplemented Read as ‘0’ 86Fh Legend: = Unimplemented data memory locations, read as ‘0’. Legend: = Unimplemented data memory locations, read as ‘0’. DS40001579E-page 22  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 3.3.5 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table3-7 can be addressed from any Bank. TABLE 3-7: CORE FUNCTION REGISTERS SUMMARY Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 0-31 x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory INDF0 xxxx xxxx uuuu uuuu x80h (not a physical register) x01h or Addressing this location uses contents of FSR1H/FSR1L to address data memory INDF1 xxxx xxxx uuuu uuuu x81h (not a physical register) x02h or PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x82h x03h or STATUS — — — TO PD Z DC C ---1 1000 ---q quuu x83h x04h or FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x84h x05h or FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x85h x06h or FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x86h x07h or FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x87h x08h or BSR — — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 x88h x09h or WREG Working Register 0000 0000 uuuu uuuu x89h x0Ah or PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 x8Ah x0Bh or INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 x8Bh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’.  2011-2014 Microchip Technology Inc. DS40001579E-page 23

PIC16(L)F1782/3 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets Bank 0 00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu 00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 00Fh — Unimplemented — — 010h PORTE — — — — RE3 — — — ---- x--- ---- u--- 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF — C3IF CCP2IF 0000 0-00 0000 0-00 013h — Unimplemented — — 014h PIR4 — — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF --00 --00 --00 --00 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 018h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 0000 00-0 uuuu uu-u 019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu DONE 016h TMR2 Holding Register for the Least Significant Byte of the 16-bit TMR2 Register xxxx xxxx uuuu uuuu 017h PR2 Holding Register for the Most Significant Byte of the 16-bit TMR2 Register xxxx xxxx uuuu uuuu 018h T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000 01Dh to — Unimplemented — — 01Fh Bank 1 08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111 08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111 08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111 08Fh — Unimplemented — — 090h TRISE — — — — —(2) — — — ---- 1--- ---- 1--- 091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 092h PIE2 OSEIE C2IE C1IE EEIE BCL1IE — C3IE CCP2IE 0000 0-00 0000 0-00 093h — Unimplemented — — 094h PIE4 — — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC1SIE --00 --00 --00 --00 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111 096h PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu 097h WDTCON — — WDTPS<4:0> SWDTEN --01 0110 --01 0110 098h OSCTUNE — — TUN<5:0> --00 0000 --00 0000 099h OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 0011 1-00 0011 1-00 09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 00q0 --00 qqqq --0q 09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu 09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu 09Dh ADCON0 ADRMD CHS<4:0> GO/DONE ADON 0000 0000 0000 0000 09Eh ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 0000 -000 0000 -000 09Fh ADCON2 TRIGSEL<3:0> CHSN<3:0> 000- -000 000- -000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: Unimplemented, read as ‘1’. 3: PIC16F1782/3 only. DS40001579E-page 24  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets Bank 2 10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu 10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu 10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu 10Fh — Unimplemented — — 110h — Unimplemented — — 111h CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 0000 0100 0000 0100 112h CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 0000 0000 0000 0000 113h CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 0000 0100 0000 0100 114h CM2CON1 C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> 0000 0000 0000 0000 115h CMOUT — — — — — MC3OUT MC2OUT MC1OUT ---- -000 ---- -000 116h BORCON SBOREN BORFS — — — — — BORRDY 1x-- ---q uu-- ---u 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000 118h DACCON0 DACEN — DACOE1 DACOE2 DACPSS<1:0> — DACNSS 0-00 00-0 0-00 00-0 119h DACCON1 DACR<7:0> 0000 0000 0000 0000 11Ah to — Unimplemented — — 11Ch 11Dh APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 0000 0000 0000 0000 11Eh CM3CON0 C3ON C3OUT C3OE C3POL C3ZLF C3SP C3HYS C3SYNC 0000 0100 0000 0100 11Fh CM3CON1 C3INTP C3INTN C3PCH<2:0> C3NCH<2:0> 0000 0000 0000 0000 Bank 3 18Ch ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1-11 1111 1-11 1111 18Dh ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111 18Eh to — Unimplemented — — 190h 191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000 192h EEADRH —(2) EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000 193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu 194h EEDATH — — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu 195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000 196h EECON2 EEPROM / Program Memory Control Register 2 0000 0000 0000 0000 197h VREGCON(3) — — — — — — VREGPM Reserved ---- --01 ---- --01 198h — Unimplemented — — 199h RCREG USART Receive Data Register 0000 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRG BRG<7:0> 0000 0000 0000 0000 19Ch SPBRGH BRG<15:8> 0000 0000 0000 0000 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: Unimplemented, read as ‘1’. 3: PIC16F1782/3 only.  2011-2014 Microchip Technology Inc. DS40001579E-page 25

PIC16(L)F1782/3 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets Bank 4 20Ch WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 1111 1111 1111 1111 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 20Eh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111 20Fh — Unimplemented — — 210h WPUE — — — — WPUE3 — — — ---- 1--- ---- 1--- 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD ADD<7:0> 0000 0000 0000 0000 213h SSP1MSK MSK<7:0> 1111 1111 1111 1111 214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h — — Unimplemented — — 21Fh Bank 5 28Ch ODCONA Open Drain Control for PORTA 0000 0000 0000 0000 28Dh ODCONB Open Drain Control for PORTB 0000 0000 0000 0000 28Eh ODCONC Open Drain Control for PORTC 0000 0000 0000 0000 28Fh — Unimplemented — — 290h — Unimplemented — — 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 293h CCP1CON — — DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000 294h — — Unimplemented — — 297h 298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu 299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu 29Ah CCP2CON — — DC2B<1:0> CCP2M<3:0> --00 0000 --00 0000 29Bh — — Unimplemented — — 29Fh Bank 6 30Ch SLRCONA Slew Rate Control for PORTA 0000 0000 0000 0000 30Dh SLRCONB Slew Rate Control for PORTB 0000 0000 0000 0000 30Eh SLRCONC Slew Rate Control for PORTC 0000 0000 0000 0000 30Fh — — Unimplemented — — 31Fh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: Unimplemented, read as ‘1’. 3: PIC16F1782/3 only. DS40001579E-page 26  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets Bank 7 38Ch INLVLA Input Type Control for PORTA 0000 0000 0000 0000 38Dh INLVLB Input Type Control for PORTB 0000 0000 0000 0000 38Eh INLVLC Input Type Control for PORTC 1111 1111 1111 1111 38Fh — Unimplemented — — 390h INLVLE — — — — INLVLE3 — — — ---- 1--- ---- 1--- 391h IOCAP IOCAP<7:0> 0000 0000 0000 0000 392h IOCAN IOCAN<7:0> 0000 0000 0000 0000 393h IOCAF IOCAF<7:0> 0000 0000 0000 0000 394h IOCBP IOCBP<7:0> 0000 0000 0000 0000 395h IOCBN IOCBN<7:0> 0000 0000 0000 0000 396h IOCBF IOCBF<7:0> 0000 0000 0000 0000 397h IOCCP IOCCP<7:0> 0000 0000 0000 0000 398h IOCCN IOCCN<7:0> 0000 0000 0000 0000 399h IOCCF IOCCF<7:0> 0000 0000 0000 0000 39Ah — — Unimplemented — — 39Ch 39Dh IOCEP — — — — IOCEP3 — — — ---- 0--- ---- 0--- 39Eh IOCEN — — — — IOCEN3 — — — ---- 0--- ---- 0--- 39Fh IOCEF — — — — IOCEF3 — — — ---- 0--- ---- 0--- Bank 8-9 40Ch or 41Fh and — Unimplemented — — 48Ch or 49Fh Bank 10 50Ch — — Unimplemented — — 510h 511h OPA1CON OPA1EN OPA1SP — — — — OPA1PCH<1:0> 00-- --00 00-- --00 512h — Unimplemented — — 513h OPA2CON OPA2EN OPA2SP — — — — OPA2PCH<1:0> 00-- --00 00-- --00 514h — — Unimplemented — — 519h 51Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> 0011 0000 0011 0000 51Bh — — Unimplemented — — 51Fh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: Unimplemented, read as ‘1’. 3: PIC16F1782/3 only.  2011-2014 Microchip Technology Inc. DS40001579E-page 27

PIC16(L)F1782/3 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets Bank 11-15 x0Ch or x8Ch to — Unimplemented — — x6Fh or xEFh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: Unimplemented, read as ‘1’. 3: PIC16F1782/3 only. DS40001579E-page 28  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets Bank 16 80Ch — — Unimplemented — — 810h 811h PSMC1CON PSMC1EN PSMC1LD PSMC1DBFE PSMC1DBRE P1MODE<3:0> 0000 0000 0000 0000 812h PSMC1MDL P1MDLEN P1MDLPOL P1MDLBIT — P1MSRC<3:0> 000- 0000 000- 0000 813h PSMC1SYNC — — — — — — P1SYNC<1:0> ---- --00 ---- --00 814h PSMC1CLK — — P1CPRE<1:0> — — P1CSRC<1:0> --00 --00 --00 --00 815h PSMC1OEN — — P1OEF P1OEE P1OED P1OEC P1OEB P1OEA --00 0000 --00 0000 816h PSMC1POL — P1INPOL P1POLF P1POLE P1POLD P1POLC P1POLB P1POLA -000 0000 -000 0000 817h PSMC1BLNK — — P1FEBM<1:0> — — P1REBM<1:0> --00 --00 --00 --00 818h PSMC1REBS P1REBIN — — — P1REBSC3 P1REBSC2 P1REBSC1 — 0--- 000- 0--- 000- 819h PSMC1FEBS P1FEBIN — — — P1FEBSC3 P1FEBSC2 P1FEBSC1 — 0--- 000- 0--- 000- 81Ah PSMC1PHS P1PHSIN — — — P1PHSC3 P1PHSC2 P1PHSC1 P1PHST 0--- 0000 0--- 0000 81Bh PSMC1DCS P1DCSIN — — — P1DCSC3 P1DCSC2 P1DCSC1 P1DCST 0--- 0000 0--- 0000 81Ch PSMC1PRS P1PRSIN — — — P1PRSC3 P1PRSC2 P1PRSC1 P1PRST 0--- 0000 0--- 0000 81Dh PSMC1ASDC P1ASE P1ASDEN P1ARSEN — — — — P1ASDOV 000- ---0 000- ---0 81Eh PSMC1ASDL — — P1ASDLF P1ASDLE P1ASDLD P1ASDLC P1ASDLB P1ASDLA --00 0000 --00 0000 81Fh PSMC1ASDS P1ASDSIN — — — P1ASDSC3 P1ASDSC2 P1ASDSC1 — 0--- 000- 0--- 000- 820h PSMC1INT P1TOVIE P1TPHIE P1TDCIE P1TPRIE P1TOVIF P1TPHIF P1TDCIF P1TPRIF 0000 0000 0000 0000 821h PSMC1PHL Phase Low Count 0000 0000 0000 0000 822h PSMC1PHH Phase High Count 0000 0000 0000 0000 823h PSMC1DCL Duty Cycle Low Count 0000 0000 0000 0000 824h PSMC1DCH Duty Cycle High Count 0000 0000 0000 0000 825h PSMC1PRL Period Low Count 0000 0000 0000 0000 826h PSMC1PRH Period High Count 0000 0000 0000 0000 827h PSMC1TMRL Time base Low Counter 0000 0001 0000 0001 828h PSMC1TMRH Time base High Counter 0000 0000 0000 0000 829h PSMC1DBR rising Edge Dead-band Counter 0000 0000 0000 0000 82Ah PSMC1DBF Falling Edge Dead-band Counter 0000 0000 0000 0000 82Bh PSMC1BLKR rising Edge Blanking Counter 0000 0000 0000 0000 82Ch PSMC1BLKF Falling Edge Blanking Counter 0000 0000 0000 0000 82Dh PSMC1FFA — — — — Fractional Frequency Adjust Register ---- 0000 ---- 0000 82Eh PSMC1STR0 — — P1STRF P1STRE P1STRD P1STRC P1STRB P1STRA --00 0001 --00 0001 82Fh PSMC1STR1 P1SYNC — — — — — P1LSMEN P1HSMEN 0--- --00 0--- --00 830h — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: Unimplemented, read as ‘1’. 3: PIC16F1782/3 only.  2011-2014 Microchip Technology Inc. DS40001579E-page 29

PIC16(L)F1782/3 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets Bank 16 (Continued) 831h PSMC2CON PSMC2EN PSMC2LD PSMC2DBFE PSMC2DBRE P2MODE<3:0> 0000 0000 0000 0000 832h PSMC2MDL P2MDLEN P2MDLPOL P2MDLBIT — P2MSRC<3:0> 000- 0000 000- 0000 833h PSMC2SYNC — — — — — — P2SYNC<1:0> ---- --00 ---- --00 834h PSMC2CLK — — P2CPRE<1:0> — — P2CSRC<1:0> --00 --00 --00 --00 835h PSMC2OEN — — — — — — P2OEB P2OEA ---- --00 ---- --00 836h PSMC2POL — P2INPOL — — — — P2POLB P2POLA -0-- --00 -0-- --00 837h PSMC2BLNK — — P2FEBM<1:0> — — P2REBM<1:0> --00 --00 --00 --00 838h PSMC2REBS P2REBIN — — — P2REBSC3 P2REBSC2 P2REBSC1 — 0--- 000- 0--- 000- 839h PSMC2FEBS P2FEBIN — — — P2FEBSC3 P2FEBSC2 P2FEBSC1 — 0--- 000- 0--- 000- 83Ah PSMC2PHS P2PHSIN — — — P2PHSC3 P2PHSC2 P2PHSC1 P2PHST 0--- 0000 0--- 0000 83Bh PSMC2DCS P2DCSIN — — — P2DCSC3 P2DCSC2 P2DCSC1 P2DCST 0--- 0000 0--- 0000 83Ch PSMC2PRS P2PRSIN — — — P2PRSC3 P2PRSC2 P2PRSC1 P2PRST 0--- 0000 0--- 0000 83Dh PSMC2ASDC P2ASE P2ASDEN P2ARSEN — — — — P2ASDOV 000- ---0 000- ---0 83Eh PSMC2ASDL — — P2ASDLF P2ASDLE P2ASDLD P2ASDLC P2ASDLB P2ASDLA --00 0000 --00 0000 83Fh PSMC2ASDS P2ASDSIN — — — P2ASDSC3 P2ASDSC2 P2ASDSC1 — 0--- 000- 0--- 000- 840h PSMC2INT P2TOVIE P2TPHIE P2TDCIE P2TPRIE P2TOVIF P2TPHIF P2TDCIF P2TPRIF 0000 0000 0000 0000 841h PSMC2PHL Phase Low Count 0000 0000 0000 0000 842h PSMC2PHH Phase High Count 0000 0000 0000 0000 843h PSMC2DCL Duty Cycle Low Count 0000 0000 0000 0000 844h PSMC2DCH Duty Cycle High Count 0000 0000 0000 0000 845h PSMC2PRL Period Low Count 0000 0000 0000 0000 846h PSMC2PRH Period High Count 0000 0000 0000 0000 847h PSMC2TMRL Time base Low Counter 0000 0001 0000 0001 848h PSMC2TMRH Time base High Counter 0000 0000 0000 0000 849h PSMC2DBR rising Edge Dead-band Counter 0000 0000 0000 0000 84Ah PSMC2DBF Falling Edge Dead-band Counter 0000 0000 0000 0000 84Bh PSMC2BLKR rising Edge Blanking Counter 0000 0000 0000 0000 84Ch PSMC2BLKF Falling Edge Blanking Counter 0000 0000 0000 0000 84Dh PSMC2FFA — — — — Fractional Frequency Adjust Register ---- 0000 ---- 0000 84Eh PSMC2STR0 — — — — — — P2STRB P2STRA ---- --01 ---- --01 84Fh PSMC2STR1 P2SYNC — — — — — P2LSMEN P2HSMEN 0--- --00 0--- --00 850h — — Unimplemented — — 86Fh Bank 17-30 x0Ch or x8Ch to — Unimplemented — — x1Fh or x9Fh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: Unimplemented, read as ‘1’. 3: PIC16F1782/3 only. DS40001579E-page 30  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets Bank 31 F8Ch to — Unimplemented — — FE3h FE4h STATUS_ — — — — — Z DC C ---- -xxx ---- -uuu SHAD FE5h WREG_SHAD Working Register Shadow xxxx xxxx uuuu uuuu FE6h BSR_SHAD — — — Bank Select Register Shadow ---x xxxx ---u uuuu FE7h PCLATH_ — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FECh — Unimplemented — — FEDh STKPTR — — — Current Stack Pointer ---1 1111 ---1 1111 FEEh TOSL Top of Stack Low byte xxxx xxxx uuuu uuuu FEFh TOSH — Top of Stack High byte -xxx xxxx -uuu uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: Unimplemented, read as ‘1’. 3: PIC16F1782/3 only.  2011-2014 Microchip Technology Inc. DS40001579E-page 31

PIC16(L)F1782/3 3.4 PCL and PCLATH 3.4.3 COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte A computed function CALL allows programs to maintain comes from the PCL register, which is a readable and tables of functions and provide another way to execute writable register. The high byte (PC<14:8>) is not directly state machines or look-up tables. When performing a readable or writable and comes from PCLATH. On any table read using a computed function CALL, care Reset, the PC is cleared. Figure3-4 shows the five should be exercised if the table location crosses a PCL situations for the loading of the PC. memory boundary (each 256-byte block). If using the CALL instruction, the PCH<2:0> and PCL FIGURE 3-4: LOADING OF PC IN registers are loaded with the operand of the CALL DIFFERENT SITUATIONS instruction. PCH<6:3> is loaded with PCLATH<6:3>. The CALLW instruction enables computed calls by 14 PCH PCL 0 Instruction with combining PCLATH and W to form the destination PC PCL as Destination address. A computed CALLW is accomplished by loading the W register with the desired address and 6 7 0 8 PCLATH ALU Result executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. 14 PCH PCL 0 3.4.4 BRANCHING PC GOTO, CALL The branching instructions add an offset to the PC. 6 4 0 11 This allows relocatable code and code that crosses PCLATH OPCODE <10:0> page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch 14 PCH PCL 0 PC CALLW the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be 6 7 0 8 crossed. PCLATH W If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 14 PCH PCL 0 be loaded with the address PC + 1 + W. PC BRW If using BRA, the entire PC will be loaded with PC+1+, 15 the signed value of the operand of the BRA instruction. PC + W 14 PCH PCL 0 PC BRA 15 PC + OPCODE <8:0> 3.4.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 3.4.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556). DS40001579E-page 32  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 3.5 Stack 3.5.1 ACCESSING THE STACK All devices have a 16-levelx15-bit wide hardware The stack is available through the TOSH, TOSL and stack (refer to Figures3-1 and3-2). The stack space is STKPTR registers. STKPTR is the current value of the not part of either program or data space. The PC is Stack Pointer. TOSH:TOSL register pair points to the PUSHed onto the stack when CALL or CALLW instruc- TOP of the stack. Both registers are read/writable. TOS tions are executed or an interrupt causes a branch. The is split into TOSH and TOSL due to the 15-bit size of the stack is POPed in the event of a RETURN, RETLW or a PC. To access the stack, adjust the value of STKPTR, RETFIE instruction execution. PCLATH is not affected which will position TOSH:TOSL, then read/write to by a PUSH or POP operation. TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Words). This Note: Care should be taken when modifying the means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled. times, the seventeenth PUSH overwrites the value that During normal program operation, CALL, CALLW and was stored from the first PUSH. The eighteenth PUSH interrupts will increment STKPTR while RETLW, overwrites the second PUSH (and so on). The RETURN, and RETFIE will decrement STKPTR. At any STKOVF and STKUNF flag bits will be set on an Over- time, STKPTR can be inspected to see how much flow/Underflow, regardless of whether the Reset is stack is left. The STKPTR always points at the currently enabled. used place on the stack. Therefore, a CALL or CALLW Note: There are no instructions/mnemonics will increment the STKPTR and then write the PC, and called PUSH or POP. These are actions a return will unload the PC and then decrement the that occur from the execution of the CALL, STKPTR. CALLW, RETURN, RETLW and RETFIE Reference Figure3-5 through Figure3-8 for examples instructions or the vectoring to an interrupt of accessing the stack. address. FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1 Stack Reset Disabled TOSH:TOSL 0x0F STKPTR = 0x1F (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The 0x08 empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack 0x07 Overflow/Underflow Reset is enabled, the 0x06 TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is 0x05 disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x04 0x03 0x02 0x01 0x00 Stack Reset Enabled TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F (STVREN = 1)  2011-2014 Microchip Technology Inc. DS40001579E-page 33

PIC16(L)F1782/3 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the return address will be placed in the 0x07 Program Counter and the Stack Pointer 0x06 decremented to the empty state (0x1F). 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL 0x00 Return Address STKPTR = 0x00 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an 0x0B interrupt, the stack looks like the figure on the left. A series of RETURN instructions 0x0A will repeatedly place the return addresses into the Program Counter and pop the stack. 0x09 0x08 0x07 TOSH:TOSL 0x06 Return Address STKPTR = 0x06 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address DS40001579E-page 34  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address When the stack is full, the next CALL or 0x09 Return Address an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 0x08 Return Address so the stack will wrap and overwrite the return address at 0x00. If the Stack 0x07 Return Address Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will 0x06 Return Address not be overwritten. 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address TOSH:TOSL 0x00 Return Address STKPTR = 0x10 3.5.2 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.6 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2011-2014 Microchip Technology Inc. DS40001579E-page 35

PIC16(L)F1782/3 FIGURE 3-9: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Reserved 0x7FFF Address Range 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS40001579E-page 36  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing Indirect Addressing 4 BSR 0 6 From Opcode 0 7 FSRxH 0 7 FSRxL 0 0 0 0 0 Bank Select Location Select Bank Select Location Select 00000 00001 00010 11111 0x00 0x7F Bank 0 Bank 1 Bank 2 Bank 31  2011-2014 Microchip Technology Inc. DS40001579E-page 37

PIC16(L)F1782/3 3.6.2 LINEAR DATA MEMORY 3.6.3 PROGRAM FLASH MEMORY The linear data memory is the region from FSR To make constant data access easier, the entire address 0x2000 to FSR address 0x29AF. This region is program Flash memory is mapped to the upper half of a virtual region that points back to the 80-byte blocks of the FSR address space. When the MSB of FSRnH is GPR memory in all the banks. set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the Unimplemented memory reads as 0x00. Use of the lower 8 bits of each memory location is accessible via linear data memory region allows buffers to be larger INDF. Writing to the program Flash memory cannot be than 80 bytes because incrementing the FSR beyond accomplished via the FSR/INDF interface. All one bank will go directly to the GPR memory of the next instructions that access program Flash memory via the bank. FSR/INDF interface will require one additional The 16 bytes of common memory are not included in instruction cycle to complete. the linear data memory region. FIGURE 3-12: PROGRAM FLASH FIGURE 3-11: LINEAR DATA MEMORY MEMORY MAP MAP 7 FSRnH 0 7 FSRnL 0 7 FSRnH 0 7 FSRnL 0 1 0 0 1 Location Select 0x8000 0x0000 Location Select 0x2000 0x020 Bank 0 0x06F 0x0A0 Bank 1 Program 0x0EF Flash 0x120 Memory (low 8 Bank 2 bits) 0x16F 0xF20 Bank 30 0xFFFF 0x7FFF 0x29AF 0xF6F DS40001579E-page 38  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2011-2014 Microchip Technology Inc. DS40001579E-page 39

PIC16(L)F1782/3 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FCMEN IESO CLKOUTEN BOREN<1:0> CPD bit 13 bit 8 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor and internal/external switchover are both enabled. 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit If FOSC configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin. All other FOSC modes: 1 =CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 =CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 CPD: Data Code Protection bit(1) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 7 CP: Code Protection bit 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 =MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 =MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit. bit 5 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 =WDT enabled 10 =WDT enabled while running and disabled in Sleep 01 =WDT controlled by the SWDTEN bit in the WDTCON register 00 =WDT disabled DS40001579E-page 40  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 =LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins Note 1: The entire data EEPROM will be erased when the code protection is turned off during an erase.Once the Data Code Protection bit is enabled, (CPD = 0), the Bulk Erase Program Memory Command (through ICSP) can disable the Data Code Protection (CPD =1). When a Bulk Erase Program Memory Command is executed, the entire Program Flash Memory, Data EEPROM and configuration memory will be erased.  2011-2014 Microchip Technology Inc. DS40001579E-page 41

PIC16(L)F1782/3 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 LVP DEBUG LPBOR BORV STVREN PLLEN bit 13 bit 8 U-1 U-1 R/P-1 U-1 U-1 U-1 R/P-1 R/P-1 — — VCAPEN — — — WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(3) 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 LPBOR: Low-Power BOR Enable bit 1 = Low-Power Brown-out Reset is disabled 0 = Low-Power Brown-out Reset is enabled bit 10 BORV: Brown-out Reset Voltage Selection bit(4) 1 = Brown-out Reset voltage (VBOR), low trip point selected. 0 = Brown-out Reset voltage (VBOR), high trip point selected. bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7-6 Unimplemented: Read as ‘1’ bit 5 VCAPEN: Voltage Regulator Capacitor Enable bit(2) 1 = VCAP functionality is disabled on RA6 0 = VCAP functionality is enabled on RA6 bit 4-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 2 kW Flash memory (PIC16(L)F1782 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control 00 = 000h to 7FFh write-protected, no addresses may be modified by EECON control 4 kW Flash memory (PIC16(L)F1783 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write-protected, no addresses may be modified by EECON control Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. 2: Not implemented on “LF” devices. 3: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 4: See VBOR parameter for specific trip point voltages. DS40001579E-page 42  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section4.4 “Write Protection” for more information. 4.3.2 DATA EEPROM PROTECTION The entire data EEPROM is protected from external reads and writes by the CPD bit. When CPD = 0, external reads and writes of data EEPROM are inhibited. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 4.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected. 4.5 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section12.5 “User ID, Device ID and Configuration Word Access”for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16(L)F178X Memory Programming Specification” (DS41457).  2011-2014 Microchip Technology Inc. DS40001579E-page 43

PIC16(L)F1782/3 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section12.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.7 Register Definitions: Device and Revision REGISTER 4-3: DEVID: DEVICE ID REGISTER R R R R R R DEV<8:3> bit 13 bit 8 R R R R R R R R DEV<2:0> REV<4:0> bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-5 DEV<8:0>: Device ID bits DEVICEID<13:0> Values Device DEV<8:0> REV<4:0> PIC16F1782 10 1010 000 x xxxx PIC16LF1782 10 1010 101 x xxxx PIC16F1783 10 1010 001 x xxxx PIC16LF1783 10 1010 110 x xxxx bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision (see Table under DEV<8:0> above). DS40001579E-page 44  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 5.0 RESETS A simplified block diagram of the On-Chip Reset Circuit is shown in Figure5-1. There are multiple ways to reset this device: • Power-On Reset (POR) • Brown-Out Reset (BOR) • Low-Power Brown-Out Reset (LPBOR) • MCLR Reset • WDT Reset • RESET instruction • Stack Overflow • Stack Underflow • Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT ICSP™ Programming Mode Exit RESET Instruction Stack Pointer MCLRE Sleep WDT Time-out Device Reset Power-on Reset VDD Brown-out R PWRT Reset Done LPBOR Reset PWRTE LFINTOSC BOR Active(1) Note 1: See Table5-1 for BOR active conditions.  2011-2014 Microchip Technology Inc. DS40001579E-page 45

PIC16(L)F1782/3 5.1 Power-On Reset (POR) 5.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when VDD reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for performance may require greater than minimum VDD. execution protection can be implemented. The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in Configu- conditions have been met. ration Words. The four operating modes are: 5.1.1 POWER-UP TIMER (PWRT) • BOR is always on • BOR is off when in Sleep The Power-up Timer provides a nominal 64ms time-out on POR or Brown-out Reset. • BOR is controlled by software • BOR is always off The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to Refer to Table5-1 for more information. rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by enabled by clearing the PWRTE bit in Configuration configuring the BORV bit in Configuration Words. Words. A VDD noise rejection filter prevents the BOR from The Power-up Timer starts after the release of the POR triggering on small events. If VDD falls below VBOR for and BOR. a duration greater than parameter TBORDC, the device For additional information, refer to Application Note will reset. See Figure5-2 for more information. AN607, “Power-up Trouble Shooting” (DS00607). TABLE 5-1: BOR OPERATING MODES Instruction Execution upon: BOREN<1:0> SBOREN Device Mode BOR Mode Release of POR or Wake-up from Sleep 11 X X Active Waits for BOR ready(1) (BORRDY = 1) Awake Active 10 X Waits for BOR ready (BORRDY = 1) Sleep Disabled 1 X Active Waits for BOR ready(1) (BORRDY = 1) 01 0 X Disabled Begins immediately (BORRDY = x) 00 X X Disabled Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. 5.2.1 BOR IS ALWAYS ON 5.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Words are When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device programmed to ‘01’, the BOR is controlled by the start-up will be delayed until the BOR is ready and VDD SBOREN bit of the BORCON register. The device is higher than the BOR threshold. start-up is not delayed by the BOR ready condition or BOR protection is active during Sleep. The BOR does the VDD level. not delay wake-up from Sleep. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the 5.2.2 BOR IS OFF IN SLEEP BORRDY bit of the BORCON register. When the BOREN bits of Configuration Words are BOR protection is unchanged by Sleep. programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. DS40001579E-page 46  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 5-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal < TPWRT Reset TPWRT(1) VDD VBOR Internal Reset TPWRT(1) Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’. 5.3 Register Definitions: BOR Control REGISTER 5-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Words  01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect. If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control): 1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Words.  2011-2014 Microchip Technology Inc. DS40001579E-page 47

PIC16(L)F1782/3 5.4 Low-Power Brown-Out Reset 5.6 Watchdog Timer (WDT) Reset (LPBOR) The Watchdog Timer generates a Reset if the firmware The Low-Power Brown-Out Reset (LPBOR) is an does not issue a CLRWDT instruction within the time-out essential part of the Reset subsystem. Refer to period. The TO and PD bits in the STATUS register are Figure5-1 to see how the BOR interacts with other changed to indicate the WDT Reset. See Section11.0 modules. “Watchdog Timer (WDT)” for more information. The LPBOR is used to monitor the external VDD pin. 5.7 RESET Instruction When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is A RESET instruction will cause a device Reset. The RI changed to indicate that a BOR Reset has occurred. bit in the PCON register will be set to ‘0’. See Table5-4 The same bit is set for both the BOR and the LPBOR. for default conditions after a RESET instruction has Refer to Register5-2. occurred. 5.4.1 ENABLING LPBOR 5.8 Stack Overflow/Underflow Reset The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the The device can reset when the Stack Overflows or LPBOR module defaults to disabled. Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are 5.4.1.1 LPBOR Module Output enabled by setting the STVREN bit in Configuration Words. See Section5.8 “Stack Overflow/Underflow The output of the LPBOR module is a signal indicating Reset” for more information. whether or not a Reset is to be asserted. This signal is OR’d together with the Reset signal of the BOR mod- 5.9 Programming Mode Exit ule to provide the generic BOR signal, which goes to the PCON register and to the power control block. Upon exit of Programming mode, the device will behave as if a POR had just occurred. 5.5 MCLR 5.10 Power-Up Timer The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the The Power-up Timer optionally delays device execution MCLRE bit of Configuration Words and the LVP bit of after a BOR or POR event. This timer is typically used to Configuration Words (Table5-2). allow VDD to stabilize before allowing the device to start running. TABLE 5-2: MCLR CONFIGURATION The Power-up Timer is controlled by the PWRTE bit of Configuration Words. MCLRE LVP MCLR 0 0 Disabled 5.11 Start-up Sequence 1 0 Enabled Upon the release of a POR or BOR, the following must x 1 Enabled occur before the device will begin executing: 5.5.1 MCLR ENABLED 1. Power-up Timer runs to completion (if enabled). 2. Oscillator start-up timer runs to completion (if When MCLR is enabled and the pin is held low, the required for oscillator source). device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. 3. MCLR must be released (if enabled). The device has a noise filter in the MCLR Reset path. The total time-out will vary based on oscillator configu- The filter will detect and ignore small pulses. ration and Power-up Timer configuration. See Section6.0 “Oscillator Module (with Fail-Safe Note: A Reset does not drive the MCLR pin low. Clock Monitor)” for more information. The Power-up Timer and oscillator start-up timer run 5.5.2 MCLR DISABLED independently of MCLR Reset. If MCLR is kept low When MCLR is disabled, the pin functions as a general long enough, the Power-up Timer and oscillator purpose input and the internal weak pull-up is under start-up timer will expire. Upon bringing MCLR high, the software control. See Section13.9 “PORTE device will begin execution immediately (see Registers” for more information. Figure5-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. DS40001579E-page 48  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 5-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC  2011-2014 Microchip Technology Inc. DS40001579E-page 49

PIC16(L)F1782/3 5.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table5-3 and Table5-4 show the Reset conditions of these registers. TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during normal operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 5-4: RESET CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-- uuuu RESET Instruction Executed 0000h ---u uuuu uu-- u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. DS40001579E-page 50  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 5.13 Power Control (PCON) Register The PCON register bits are shown in Register5-2. The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Reset Instruction Reset (RI) • MCLR Reset (RMCLR) • Watchdog Timer Reset (RWDT) • Stack Underflow Reset (STKUNF) • Stack Overflow Reset (STKOVF) 5.14 Register Definitions: Power Control REGISTER 5-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u STKOVF STKUNF — RWDT RMCLR RI POR BOR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware bit 5 Unimplemented: Read as ‘0’ bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (cleared by hardware) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)  2011-2014 Microchip Technology Inc. DS40001579E-page 51

PIC16(L)F1782/3 TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BORCON SBOREN BORFS — — — — — BORRDY 47 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 51 STATUS — — — TO PD Z DC C 18 WDTCON — — WDTPS<4:0> SWDTEN 94 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. DS40001579E-page 52  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 6.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of eight FAIL-SAFE CLOCK MONITOR) clock modes. 1. ECL – External Clock Low-Power mode 6.1 Overview (0MHz to 0.5MHz) 2. ECM – External Clock Medium-Power mode The oscillator module has a wide variety of clock (0.5MHz to 4MHz) sources and selection features that allow it to be used 3. ECH – External Clock High-Power mode in a wide range of applications while maximizing perfor- (4MHz to 32MHz) mance and minimizing power consumption. Figure6-1 4. LP – 32kHz Low-Power Crystal mode. illustrates a block diagram of the oscillator module. 5. XT – Medium Gain Crystal or Ceramic Resonator Clock sources can be supplied from external oscillators, Oscillator mode (up to 4 MHz) quartz crystal resonators, ceramic resonators and 6. HS – High Gain Crystal or Ceramic Resonator Resistor-Capacitor (RC) circuits. In addition, the system mode (4 MHz to 20 MHz) clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds 7. RC – External Resistor-Capacitor (RC). selectable via software. Additional clock features 8. INTOSC – Internal oscillator (31kHz to 32 MHz). include: Clock Source modes are selected by the FOSC<2:0> • Selectable system clock source between external bits in the Configuration Words. The FOSC bits or internal sources via software. determine the type of oscillator that will be used when • Two-Speed Start-up mode, which minimizes the device is first powered. latency between external oscillator start-up and The EC clock mode relies on an external logic level code execution. signal as the device clock source. The LP, XT, and HS • Fail-Safe Clock Monitor (FSCM) designed to clock modes require an external crystal or resonator to detect a failure of the external clock source (LP, be connected to the device. Each mode is optimized for XT, HS, EC or RC modes) and switch a different frequency range. The RC clock mode automatically to the internal oscillator. requires an external resistor and capacitor to set the • Oscillator Start-up Timer (OST) ensures stability oscillator frequency. of crystal oscillator sources The INTOSC internal oscillator block produces low, medium, and high-frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure6-1). A wide selection of device clock frequencies may be derived from these three clock sources.  2011-2014 Microchip Technology Inc. DS40001579E-page 53

PIC16(L)F1782/3 FIGURE 6-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM Oscillator Timer1 Timer1 Clock Source Option T1OSO for other modules T1OSCEN Enable T1OSI Oscillator T1OSC 01 External LP, XT, HS, RC, EC Oscillator OSC2 0 10 Sleep 1 Sleep FOSC OSC1 PRIMUX PSMCMUX ÷ 2 01 00 To CPU and Peripherals 0 4 x PLL 00 1 PLLMUX IRCF<3:0> INTOSC 16 MHz 1X 1111 8 MHz Internal Oscillator 4 MHz Block 2 MHz SCS<1:0> er 1 MHz HFPLL 16 MHz scal 500 kHz UX PSMC 64 MHz (HFINTOSC) ost 250 kHz M P 125 kHz 500 kHz Source 500 kHz 62.5 kHz (MFINTOSC) 31.25 kHz 31 kHz 31 kHz Source 0000 31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules PLLEN or SCS FOSC<2:0> PRIMUX PSMCMUX PLLMUX SPLLEN 0 1 1 10 =100 1 1 1 01 =00 0 0 1 10 ≠100 1(1) 0 0 00 ≠00 XXX X X 1 XX Note 1: This selection should not be made when the PSMC is using the 64 MHz clock option. DS40001579E-page 54  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 6.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully clock source to function. Examples are: oscillator static, stopping the external clock input will have the modules (EC mode), quartz crystal resonators or effect of halting the device while leaving all data intact. ceramic resonators (LP, XT and HS modes) and Upon restarting the external clock, the device will Resistor-Capacitor (RC) mode circuits. resume operation as if no time had elapsed. Internal clock sources are contained within the FIGURE 6-2: EXTERNAL CLOCK (EC) oscillator module. The internal oscillator block has two MODE OPERATION internal oscillators and a dedicated Phase-Lock Loop (HFPLL) that are used to generate three internal system clock sources: the 16MHz High-Frequency Clock from OSC1/CLKIN Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) Ext. System and the 31kHz Low-Frequency Internal Oscillator PIC® MCU (LFINTOSC). OSC2/CLKOUT The system clock can be selected between external or FOSC/4 or I/O(1) internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section6.3 Note 1: Output depends upon CLKOUTEN bit of the “Clock Switching” for additional information. Configuration Words. 6.2.1 EXTERNAL CLOCK SOURCES 6.2.1.2 LP, XT, HS Modes An external clock source can be used as the device system clock by performing one of the following The LP, XT and HS modes support the use of quartz actions: crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure6-3). The three modes select • Program the FOSC<2:0> bits in the Configuration a low, medium or high gain setting of the internal Words to select an external clock source that will inverter-amplifier to support various resonator types be used as the default system clock upon a and speed. device Reset. • Write the SCS<1:0> bits in the OSCCON register LP Oscillator mode selects the lowest gain setting of the to switch the system clock source to: internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to - Timer1 oscillator during run-time, or drive only 32.768 kHz tuning-fork type crystals (watch - An external clock source determined by the crystals). value of the FOSC bits. XT Oscillator mode selects the intermediate gain See Section6.3 “Clock Switching”for more informa- setting of the internal inverter-amplifier. XT mode tion. current consumption is the medium of the three modes. This mode is best suited to drive resonators with a 6.2.1.1 EC Mode medium drive level specification. The External Clock (EC) mode allows an externally HS Oscillator mode selects the highest gain setting of the generated logic level signal to be the system clock internal inverter-amplifier. HS mode current consumption source. When operating in this mode, an external clock is the highest of the three modes. This mode is best source is connected to the OSC1 input. suited for resonators that require a high drive setting. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure6-2 shows the pin connections for EC Figure6-3 and Figure6-4 show typical circuits for mode. quartz crystal and ceramic resonators, respectively. EC mode has three power modes to select from through Configuration Words: • High power, 4-32MHz (FOSC = 111) • Medium power, 0.5-4MHz (FOSC = 110) • Low power, 0-0.5MHz (FOSC = 101)  2011-2014 Microchip Technology Inc. DS40001579E-page 55

PIC16(L)F1782/3 FIGURE 6-3: QUARTZ CRYSTAL FIGURE 6-4: CERAMIC RESONATOR OPERATION (LP, XT OR OPERATION HS MODE) (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN OSC1/CLKIN C1 To Internal C1 To Internal Logic Logic QCruyasrttazl RF(2) Sleep RP(3) RF(2) Sleep C2 RS(1) OSC2/CLKOUT C2 Ceramic RS(1) OSC2/CLKOUT Resonator Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 3: An additional parallel feedback resistor (RP) Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator according to type, package and operation. manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 6.2.1.3 Oscillator Start-up Timer (OST) 2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts expected for the application. 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer 3: For oscillator design assistance, reference (PWRT) has expired (if configured), or a wake-up from the following Microchip Applications Notes: Sleep. During this time, the program counter does not • AN826, “Crystal Oscillator Basics and increment and program execution is suspended, Crystal Selection for rfPIC® and PIC® unless either FSCM or Two-Speed Start-Up are Devices” (DS00826) enabled. In this case, code will continue to execute at • AN849, “Basic PIC® Oscillator Design” the selected INTOSC frequency while the OST is (DS00849) counting. The OST ensures that the oscillator circuit, • AN943, “Practical PIC® Oscillator using a quartz crystal resonator or ceramic resonator, Analysis and Design” (DS00943) has started and is providing a stable system clock to the oscillator module. • AN949, “Making Your Oscillator Work” (DS00949) In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section6.4 “Two-Speed Clock Start-up Mode”). DS40001579E-page 56  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 6.2.1.4 4x PLL Note 1: Quartz crystal characteristics vary The oscillator module contains a 4x PLL that can be according to type, package and used with both external and internal clock sources to manufacturer. The user should consult the provide a system clock source. The input frequency for manufacturer data sheets for specifications the 4x PLL must fall within specifications. See the PLL and recommended application. Clock Timing Specifications in Section30.0 2: Always verify oscillator performance over “Electrical Specifications”. the VDD and temperature range that is The 4x PLL may be enabled for use by one of two expected for the application. methods: 3: For oscillator design assistance, reference 1. Program the PLLEN bit in Configuration Words the following Microchip Applications Notes: to a ‘1’. • AN826, “Crystal Oscillator Basics and 2. Write the SPLLEN bit in the OSCCON register to Crystal Selection for rfPIC® and PIC® a ‘1’. If the PLLEN bit in Configuration Words is Devices” (DS00826) programmed to a ‘1’, then the value of SPLLEN • AN849, “Basic PIC® Oscillator Design” is ignored. (DS00849) 6.2.1.5 TIMER1 Oscillator • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) The Timer1 oscillator is a separate crystal oscillator • AN949, “Making Your Oscillator Work” that is associated with the Timer1 peripheral. It is opti- (DS00949) mized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI • TB097, “Interfacing a Micro Crystal device pins. MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) The Timer1 oscillator can be used as an alternate • AN1288, “Design Practices for system clock source and can be selected during Low-Power External Oscillators” run-time using clock switching. Refer to Section6.3 (DS01288) “Clock Switching” for more information. FIGURE 6-5: QUARTZ CRYSTAL OPERATION (TIMER1 OSCILLATOR) PIC® MCU T1OSI C1 To Internal Logic 32.768 kHz Quartz Crystal C2 T1OSO  2011-2014 Microchip Technology Inc. DS40001579E-page 57

PIC16(L)F1782/3 6.2.1.6 External RC Mode 6.2.2 INTERNAL CLOCK SOURCES The external Resistor-Capacitor (RC) modes support The device may be configured to use the internal the use of an external RC circuit. This allows the oscillator block as the system clock by performing one designer maximum flexibility in frequency choice while of the following actions: keeping costs to a minimum when clock accuracy is not • Program the FOSC<2:0> bits in Configuration required. Words to select the INTOSC clock source, which The RC circuit connects to OSC1. OSC2/CLKOUT is will be used as the default system clock upon a available for general purpose I/O or CLKOUT. The device Reset. function of the OSC2/CLKOUT pin is determined by the • Write the SCS<1:0> bits in the OSCCON register CLKOUTEN bit in Configuration Words. to switch the system clock source to the internal Figure6-6 shows the external RC mode connections. oscillator during run-time. See Section6.3 “Clock Switching”for more information. FIGURE 6-6: EXTERNAL RC MODES In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. VDD PIC® MCU The function of the OSC2/CLKOUT pin is determined REXT by the CLKOUTEN bit in Configuration Words. OSC1/CLKIN Internal The internal oscillator block has two independent Clock oscillators and a dedicated Phase-Lock Loop, HFPLL CEXT that can produce one of three internal system clock sources. VSS 1. The HFINTOSC (High-Frequency Internal FOSC/4 or I/O(1) OSC2/CLKOUT Oscillator) is factory calibrated and operates at 16MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the Recommended values: 10 k  REXT  100 k, <3V dedicated Phase-Lock Loop, HFPLL. The 3 k  REXT  100 k, 3-5V frequency of the HFINTOSC can be CEXT > 20 pF, 2-5V user-adjusted via software using the OSCTUNE Note 1: Output depends upon CLKOUTEN bit of the register (Register6-3). Configuration Words. 2. The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at The RC oscillator frequency is a function of the supply 500kHz. The frequency of the MFINTOSC can voltage, the resistor (REXT) and capacitor (CEXT) values be user-adjusted via software using the and the operating temperature. Other factors affecting OSCTUNE register (Register6-3). the oscillator frequency are: 3. The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at • threshold voltage variation 31kHz. • component tolerances • packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. DS40001579E-page 58  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 6.2.2.1 HFINTOSC 6.2.2.3 Internal Oscillator Frequency Adjustment The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16MHz internal clock source. The The 500 kHz internal oscillator is factory calibrated. frequency of the HFINTOSC can be altered via This internal oscillator can be adjusted in software by software using the OSCTUNE register (Register6-3). writing to the OSCTUNE register (Register6-3). Since The output of the HFINTOSC connects to a postscaler the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in and multiplexer (see Figure6-1). One of multiple frequencies derived from the HFINTOSC can be the OSCTUNE register value will apply to both. selected via software using the IRCF<3:0> bits of the The default value of the OSCTUNE register is ‘0’. The OSCCON register. See Section6.2.2.7 “Internal value is a 6-bit two’s complement number. A value of Oscillator Clock Switch Timing” for more information. 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to The HFINTOSC is enabled by: the minimum frequency. • Configure the IRCF<3:0> bits of the OSCCON When the OSCTUNE register is modified, the oscillator register for the desired HF frequency, and frequency will begin shifting to the new frequency. Code • FOSC<2:0> = 100, or execution continues during this shift. There is no • Set the System Clock Source (SCS) bits of the indication that the shift has occurred. OSCCON register to ‘1x’. OSCTUNE does not affect the LFINTOSC frequency. A fast startup oscillator allows internal circuits to power Operation of features that depend on the LFINTOSC up and stabilize before switching to HFINTOSC. clock source frequency, such as the Power-up Timer The High Frequency Internal Oscillator Ready bit (PWRT), Watchdog Timer (WDT), Fail-Safe Clock (HFIOFR) of the OSCSTAT register indicates when the Monitor (FSCM) and peripherals, are not affected by the HFINTOSC is running. change in frequency. The High Frequency Internal Oscillator Status Locked 6.2.2.4 LFINTOSC bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31kHz internal clock source. The High Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the The output of the LFINTOSC connects to a multiplexer HFINTOSC is running within 0.5% of its final value. (see Figure6-1). Select 31kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See 6.2.2.2 MFINTOSC Section6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The LFINTOSC is also The Medium-Frequency Internal Oscillator the frequency for the Power-up Timer (PWRT), (MFINTOSC) is a factory calibrated 500kHz internal Watchdog Timer (WDT) and Fail-Safe Clock Monitor clock source. The frequency of the MFINTOSC can be (FSCM). altered via software using the OSCTUNE register (Register6-3). The LFINTOSC is enabled by selecting 31kHz (IRCF<3:0> bits of the OSCCON register=000) as the The output of the MFINTOSC connects to a postscaler system clock source (SCS bits of the OSCCON and multiplexer (see Figure6-1). One of nine register= 1x), or when any of the following are frequencies derived from the MFINTOSC can be enabled: selected via software using the IRCF<3:0> bits of the OSCCON register. See Section6.2.2.7 “Internal • Configure the IRCF<3:0> bits of the OSCCON Oscillator Clock Switch Timing” for more information. register for the desired LF frequency, and The MFINTOSC is enabled by: • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the • Configure the IRCF<3:0> bits of the OSCCON OSCCON register to ‘1x’ register for the desired HF frequency, and • FOSC<2:0> = 100, or Peripherals that use the LFINTOSC are: • Set the System Clock Source (SCS) bits of the • Power-up Timer (PWRT) OSCCON register to ‘1x’ • Watchdog Timer (WDT) The Medium Frequency Internal Oscillator Ready bit • Fail-Safe Clock Monitor (FSCM) (MFIOFR) of the OSCSTAT register indicates when the The Low-Frequency Internal Oscillator Ready bit MFINTOSC is running. (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running.  2011-2014 Microchip Technology Inc. DS40001579E-page 59

PIC16(L)F1782/3 6.2.2.5 Internal Oscillator Frequency 6.2.2.6 32 MHz Internal Oscillator Selection Frequency Selection The system clock speed can be selected via software The Internal Oscillator Block can be used with the using the Internal Oscillator Frequency Select bits 4xPLL associated with the External Oscillator Block to IRCF<3:0> of the OSCCON register. produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz The output of the 16MHz HFINTOSC, 500kHz internal clock source: MFINTOSC, and 31kHz LFINTOSC connects to a postscaler and multiplexer (see Figure6-1). The • The FOSC bits in Configuration Words must be Internal Oscillator Frequency Select bits IRCF<3:0> of set to use the INTOSC source as the device the OSCCON register select the frequency output of the system clock (FOSC<2:0> = 100). internal oscillators. One of the following frequencies • The SCS bits in the OSCCON register must be can be selected via software: cleared to use the clock determined by - 32 MHz (requires 4x PLL) FOSC<2:0> in Configuration Words (SCS<1:0>=00). - 16 MHz • The IRCF bits in the OSCCON register must be - 8 MHz set to the 8 MHz or 16MHz HFINTOSC set to use - 4 MHz (IRCF<3:0>=111x). - 2 MHz • The SPLLEN bit in the OSCCON register must be - 1 MHz set to enable the 4x PLL, or the PLLEN bit of the - 500 kHz (default after Reset) Configuration Words must be programmed to a - 250 kHz ‘1’. - 125 kHz Note: When using the PLLEN bit of the - 62.5 kHz Configuration Words, the 4x PLL cannot be disabled by software and the SPLLEN - 31.25 kHz option will not be available. - 31 kHz (LFINTOSC) The 4x PLL is not available for use with the internal Note: Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to ‘0111’ oscillator when the SCS bits of the OSCCON register and the frequency selection is set to are set to ‘1x’. The SCS bits must be set to ‘00’ to use 500kHz. The user can modify the IRCF the 4x PLL with the internal oscillator. bits to select a different frequency. The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These dupli- cate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes that use the same oscillator source. DS40001579E-page 60  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 6.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure6-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. IRCF<3:0> bits of the OSCCON register are modified. 2. If the new clock is shut down, a clock start-up delay is started. 3. Clock switch circuitry waits for a falling edge of the current clock. 4. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. The new clock is now active. 6. The OSCSTAT register is updated as required. 7. Clock switch is complete. See Figure6-7 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table6-1. Start-up delay specifications are located in the oscillator tables of Section30.0 “Electrical Specifications”.  2011-2014 Microchip Technology Inc. DS40001579E-page 61

PIC16(L)F1782/3 FIGURE 6-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ LFINTOSC (FSCM and WDT disabled) MFINTOSC HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled) MFINTOSC HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC   IRCF <3:0> 0 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> = 0  0 System Clock DS40001579E-page 62  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 6.3 Clock Switching 6.3.3 TIMER1 OSCILLATOR The system clock source can be switched between The Timer1 oscillator is a separate crystal oscillator external and internal clock sources via software using associated with the Timer1 peripheral. It is optimized the System Clock Select (SCS) bits of the OSCCON for timekeeping operations with a 32.768 kHz crystal register. The following clock sources can be selected connected between the T1OSO and T1OSI device using the SCS bits: pins. • Default system oscillator determined by FOSC The Timer1 oscillator is enabled using the T1OSCEN bits in Configuration Words control bit in the T1CON register. See Section22.0 “Timer1 Module with Gate Control” for more • Timer1 32 kHz crystal oscillator information about the Timer1 peripheral. • Internal Oscillator Block (INTOSC) 6.3.4 TIMER1 OSCILLATOR READY 6.3.1 SYSTEM CLOCK SELECT (SCS) (T1OSCR) BIT BITS The user must ensure that the Timer1 oscillator is The System Clock Select (SCS) bits of the OSCCON ready to be used before it is selected as a system clock register selects the system clock source that is used for source. The Timer1 Oscillator Ready (T1OSCR) bit of the CPU and peripherals. the OSCSTAT register indicates whether the Timer1 • When the SCS bits of the OSCCON register = 00, oscillator is ready to be used. After the T1OSCR bit is the system clock source is determined by the set, the SCS bits can be configured to select the Timer1 value of the FOSC<2:0> bits in the Configuration oscillator. Words. • When the SCS bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table6-1. 6.3.2 OSCILLATOR START-UP TIMER STATUS (OSTS) BIT The Oscillator Start-up Timer Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the Timer1 oscillator.  2011-2014 Microchip Technology Inc. DS40001579E-page 63

PIC16(L)F1782/3 6.4 Two-Speed Clock Start-up Mode 6.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode provides additional power savings by minimizing the latency between external Two-Speed Start-up mode is configured by the oscillator start-up and code execution. In applications following settings: that make heavy use of the Sleep mode, Two-Speed • IESO (of the Configuration Words) = 1; Start-up will remove the external oscillator start-up Internal/External Switchover bit (Two-Speed time from the time spent awake and can reduce the Start-up mode enabled). overall power consumption of the device. This mode • SCS (of the OSCCON register) = 00. allows the application to wake-up from Sleep, perform • FOSC<2:0> bits in the Configuration Words a few instructions using the INTOSC internal oscillator configured for LP, XT or HS mode. block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up mode is entered after: Two-Speed Start-up provides benefits when the oscil- • Power-on Reset (POR) and, if enabled, after lator module is configured for LP, XT or HS modes. Power-up Timer (PWRT) has expired, or The Oscillator Start-up Timer (OST) is enabled for • Wake-up from Sleep. these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 6-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) 31kHz Sleep/POR MFINTOSC(1) 31.25kHz-500 kHz Oscillator Warm-up Delay (TWARM) HFINTOSC(1) 31.25kHz-16MHz Sleep/POR EC, RC(1) DC – 32MHz 2 cycles LFINTOSC EC, RC(1) DC – 32MHz 1 cycle of each Timer1 Oscillator Sleep/POR 32kHz-20MHz 1024 Clock Cycles (OST) LP, XT, HS(1) MFINTOSC(1) 31.25kHz-500kHz Any clock source 2s (approx.) HFINTOSC(1) 31.25kHz-16MHz Any clock source LFINTOSC(1) 31kHz 1 cycle of each Any clock source Timer1 Oscillator 32kHz 1024 Clock Cycles (OST) PLL inactive PLL active 16-32MHz 2ms (approx.) Note 1: PLL inactive. DS40001579E-page 64  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 6.4.2 TWO-SPEED START-UP 6.4.3 CHECKING TWO-SPEED CLOCK SEQUENCE STATUS 1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCSTAT 2. Instructions begin execution by the internal register will confirm if the microcontroller is running oscillator at the frequency set in the IRCF<3:0> from the external clock source, as defined by the bits of the OSCCON register. FOSC<2:0> bits in the Configuration Words, or the internal oscillator. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. 5. OSTS is set. 6. System clock held low until the next falling edge of new clock (LP, XT or HS mode). 7. System clock is switched to external clock source. FIGURE 6-8: TWO-SPEED START-UP INTOSC TTOST OSC1 0 1 1022 1023 OSC2 Program Counter P C - N PC PC + 1 System Clock  2011-2014 Microchip Technology Inc. DS40001579E-page 65

PIC16(L)F1782/3 6.5 Fail-Safe Clock Monitor 6.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset, to continue operating should the external oscillator fail. executing a SLEEP instruction or changing the SCS bits The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bits are the Oscillator Start-up Timer (OST) has expired. The changed, the OST is restarted. While the OST is FSCM is enabled by setting the FCMEN bit in the running, the device continues to operate from the Configuration Words. The FSCM is applicable to all INTOSC selected in OSCCON. When the OST times external Oscillator modes (LP, XT, HS, EC, Timer1 out, the Fail-Safe condition is cleared after successfully Oscillator and RC). switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the FIGURE 6-9: FSCM BLOCK DIAGRAM OSFIF flag will again become set by hardware. Clock Monitor 6.5.4 RESET OR WAKE-UP FROM SLEEP Latch External S Q The FSCM is designed to detect an oscillator failure Clock after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after LFINTOSC any type of Reset. The OST is not used with the EC or Oscillator ÷ 64 R Q RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When 31 kHz 488 Hz the FSCM is enabled, the Two-Speed Start-up is also (~32 s) (~2 ms) enabled. Therefore, the device will always be executing code while the OST is operating. Sample Clock Clock Failure Note: Due to the wide range of oscillator start-up Detected times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate 6.5.1 FAIL-SAFE DETECTION amount of time, the user should check the The FSCM module detects a failed oscillator by Status bits in the OSCSTAT register to comparing the external oscillator to the FSCM sample verify the oscillator start-up and that the clock. The sample clock is generated by dividing the system clock switchover has successfully LFINTOSC by 64. See Figure6-9. Inside the fail completed. detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 6.5.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. DS40001579E-page 66  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 6-10: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.  2011-2014 Microchip Technology Inc. DS40001579E-page 67

PIC16(L)F1782/3 6.6 Register Definitions: Oscillator Control REGISTER 6-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0 SPLLEN IRCF<3:0> — SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Words = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Words = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 1111 = 16MHz HF or 32 MHz HF(2) 1110 = 8MHz or 32 MHz HF(2) 1101 = 4MHz HF 1100 = 2MHz HF 1011 = 1MHz HF 1010 = 500kHz HF(1) 1001 = 250kHz HF(1) 1000 = 125kHz HF(1) 0111 = 500kHz MF (default upon Reset) 0110 = 250kHz MF 0101 = 125kHz MF 0100 = 62.5kHz MF 0011 = 31.25kHz HF(1) 0010 = 31.25kHz MF 000x = 31kHz LF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words. Note 1: Duplicate frequency derived from HFINTOSC. 2: 32 MHz when SPLLEN bit is set. Refer to Section6.2.2.6 “32 MHz Internal Oscillator Frequency Selection”. DS40001579E-page 68  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 6-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator is ready 0 = Timer1 oscillator is not ready If T1OSCEN = 0: 1 = Timer1 clock source is always ready bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Timer Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<2:0> = 100) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate  2011-2014 Microchip Technology Inc. DS40001579E-page 69

PIC16(L)F1782/3 REGISTER 6-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 = Minimum frequency • • • 111111 = 000000 = Oscillator module is running at the factory-calibrated frequency. 000001 = • • • 011110 = 011111 = Maximum frequency TABLE 6-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 68 OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 69 OSCTUNE — — TUN<5:0> 70 PIE2 OSEIE C2IE C1IE EEIE BCL1IE — C3IE CCP2IE 81 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — C3IF CCP2IF 84 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 183 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. TABLE 6-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 40 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Note 1: PIC16F1782/3 only. DS40001579E-page 70  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 7.0 REFERENCE CLOCK MODULE 7.3 Conflicts with the CLKR Pin The reference clock module provides the ability to send There are two cases when the reference clock output a divided clock to the clock output pin of the device signal cannot be output to the CLKR pin, if: (CLKR). This module is available in all oscillator config- • LP, XT or HS Oscillator mode is selected. urations and allows the user to select a greater range • CLKOUT function is enabled. of clock submultiples to drive external devices in the application. The reference clock module includes the 7.3.1 OSCILLATOR MODES following features: If LP, XT or HS oscillator modes are selected, the • System clock is the source OSC2/CLKR pin must be used as an oscillator input pin • Available in all oscillator configurations and the CLKR output cannot be enabled. See • Programmable clock divider Section6.2 “Clock Source Types”for more informa- • Output enable to a port pin tion on different oscillator modes. • Selectable duty cycle 7.3.2 CLKOUT FUNCTION • Slew rate control The CLKOUT function has a higher priority than the The reference clock module is controlled by the reference clock module. Therefore, if the CLKOUT CLKRCON register (Register7-1) and is enabled when function is enabled by the CLKOUTEN bit in Configura- setting the CLKREN bit. To output the divided clock tion Words, FOSC/4 will always be output on the port signal to the CLKR port pin, the CLKROE bit must be pin. Reference Section4.0 “Device Configuration” set. The CLKRDIV<2:0> bits enable the selection of for more information. eight different clock divider options. The CLKRDC<1:0> bits can be used to modify the duty 7.4 Operation During Sleep cycle of the output clock(1). The CLKRSLR bit controls slew rate limiting. As the reference clock module relies on the system clock as its source, and the system clock is disabled in Note1: If the base clock rate is selected without Sleep, the module does not function in Sleep, even if a divider, the output clock will always an external clock source or the Timer1 clock source is have a duty cycle equal to that of the configured as the system clock. The module outputs source clock, unless a 0% duty cycle is will remain in their current state until the device exits selected. If the clock divider is set to base Sleep. clock/2, then 25% and 75% duty cycle accuracy will be dependent upon the source clock. 7.1 Slew Rate The slew rate limitation on the output port pin can be disabled. The slew rate limitation is removed by clearing the CLKRSLR bit in the CLKRCON register. 7.2 Effects of a Reset Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values.  2011-2014 Microchip Technology Inc. DS40001579E-page 71

PIC16(L)F1782/3 7.5 Register Definition: Reference Clock Control REGISTER 7-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 = Reference clock module is enabled 0 = Reference clock module is disabled bit 6 CLKROE: Reference Clock Output Enable bit 1 = Reference clock output is enabled on CLKR pin 0 = Reference clock output disabled on CLKR pin bit 5 CLKRSLR: Reference Clock Slew Rate Control Limiting Enable bit 1 = Slew rate limiting is enabled 0 = Slew rate limiting is disabled bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits 11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0% bit 2-0 CLKRDIV<2:0> Reference Clock Divider bits 111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2(1) 000 = Base clock value(2) Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle. 2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0% is selected. 3: To route CLKR to pin, CLKOUTEN of Configuration Words = 1 is required. CLKOUTEN of Configuration Words = 0 will result in FOSC/4. See Section7.3 “Conflicts with the CLKR Pin” for details. DS40001579E-page 72  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> 72 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. TABLE 7-2: SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 40 7:0 CP MCLRE PWRTE WDTE1<:0> FOSC<2:0> Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.  2011-2014 Microchip Technology Inc. DS40001579E-page 73

PIC16(L)F1782/3 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • Operation • Interrupt Latency • Interrupts During Sleep • INT Pin • Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure8-1. FIGURE 8-1: INTERRUPT LOGIC TMR0IF Wake-up TMR0IE (If in Sleep mode) INTF Peripheral Interrupts INTE (TMR1IF) PIR1<0> IOCIF (TMR1IE) PIE1<0> Interrupt IOCIE to CPU PEIE PIRn<7> GIE PIEn<7> DS40001579E-page 74  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 8.1 Operation 8.2 Interrupt Latency Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the are enabled by setting the following bits: interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous • GIE bit of the INTCON register interrupts is three or four instruction cycles. For • Interrupt Enable bit(s) for the specific interrupt asynchronous interrupts, the latency is three to five event(s) instruction cycles, depending on when the interrupt • PEIE bit of the INTCON register (if the Interrupt occurs. See Figure8-2 and Figure8.3 for more details. Enable bit of the interrupt event is contained in the PIE1 or PIE2 registers) The INTCON, PIR1 and PIR2 registers record individ- ual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See “Section8.5 “Automatic Context Saving”.”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.  2011-2014 Microchip Technology Inc. DS40001579E-page 75

PIC16(L)F1782/3 FIGURE 8-2: INTERRUPT LATENCY OSC1 Q1Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC PC-1 PC PC+1 0004h 0005h Execute 1 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC+1/FSR New PC/ PC PC-1 PC ADDR PC+1 0004h 0005h Execute 2 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h) DS40001579E-page 76  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 8-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 (3) CLKOUT (4) INT pin (1) (1) (2) INTF (5) Interrupt Latency GIE INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Forced NOP Forced NOP Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section30.0 “Electrical Specifications””. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.  2011-2014 Microchip Technology Inc. DS40001579E-page 77

PIC16(L)F1782/3 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section9.0 “Power-Down Mode (Sleep)” for more details. 8.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 8.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • W register • STATUS register (except for TO and PD) • BSR register • FSR registers • PCLATH register Upon exiting the Interrupt Service Routine, these regis- ters are automatically restored. Any modifications to these registers during the ISR will be lost. If modifica- tions to any of these registers are desired, the corre- sponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved. DS40001579E-page 78  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 8.6 Register Definitions: Interrupt Control REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-change flags in the IOCBF register have been cleared by software. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2011-2014 Microchip Technology Inc. DS40001579E-page 79

PIC16(L)F1782/3 REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001579E-page 80  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE EEIE BCL1IE — C3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit 1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 C3IE: Comparator C3 Interrupt Enable bit 1 = Enables the Comparator C3 Interrupt 0 = Disables the Comparator C3 Interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2011-2014 Microchip Technology Inc. DS40001579E-page 81

PIC16(L)F1782/3 REGISTER 8-4: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC1SIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 PSMC2TIE: PSMC2 Time Base Interrupt Enable bit 1 = Enables PSMC2 time base generated interrupts 0 = Disables PSMC2 time base generated interrupts bit 4 PSMC1TIE: PSMC1 Time Base Interrupt Enable bit 1 = Enables PSMC1 time base generated interrupts 0 = Disables PSMC1 time base generated interrupts bit 3-2 Unimplemented: Read as ‘0’ bit 1 PSMC2SIE: PSMC2 Auto-Shutdown Interrupt Enable bit 1 = Enables PSMC2 auto-shutdown interrupts 0 = Disables PSMC2 auto-shutdown interrupts bit 0 PSMC1SIE: PSMC1 Auto-Shutdown Interrupt Enable bit 1 = Enables PSMC1 auto-shutdown interrupts 0 = Disables PSMC1 auto-shutdown interrupts Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001579E-page 82  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 8-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: ADC Converter Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2011-2014 Microchip Technology Inc. DS40001579E-page 83

PIC16(L)F1782/3 REGISTER 8-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 OSFIF C2IF C1IF EEIF BCL1IF — C3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 C2IF: Comparator C2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 Unimplemented: Read as ‘0’ bit 1 C3IF: Comparator C3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001579E-page 84  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 8-7: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 PSMC2TIF: PSMC2 Time Base Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 PSMC1TIF: PSMC1 Time Base Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3-2 Unimplemented: Read as ‘0’ bit 1 PSMC2SIF: PSMC2 Auto-shutdown Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 PSMC1SIF: PSMC1 Auto-shutdown Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2011-2014 Microchip Technology Inc. DS40001579E-page 85

PIC16(L)F1782/3 TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 174 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIE2 OSEIE C2IE C1IE EEIE BCL1IE — C3IE CCP2IE 81 — Unimplemented — PIE4 — — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC1SIE 82 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — C3IF CCP2IF 84 — Unimplemented — PIR4 — — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF 85 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts. DS40001579E-page 86  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-down mode is entered by executing a The device can wake-up from Sleep through one of the SLEEP instruction. following events: Upon entering Sleep mode, the following conditions 1. External Reset input on MCLR pin, if enabled exist: 2. BOR Reset, if enabled 1. WDT will be cleared but keeps running, if 3. POR Reset enabled for operation during Sleep. 4. Watchdog Timer, if enabled 2. PD bit of the STATUS register is cleared. 5. Any external interrupt 3. TO bit of the STATUS register is set. 6. Interrupts by peripherals capable of running 4. CPU clock is disabled. during Sleep (see individual peripheral for more 5. 31 kHz LFINTOSC is unaffected and peripherals information) that operate from it may continue operation in The first three events will cause a device Reset. The Sleep. last three events are considered a continuation of 6. Timer1 and peripherals that operate from Tim- program execution. To determine whether a device er1 continue operation in Sleep when the Tim- Reset or wake-up event occurred, refer to er1 clock source selected is: Section5.12 “Determining the Cause of a Reset”. • LFINTOSC When the SLEEP instruction is being executed, the next • T1CKI instruction (PC + 1) is prefetched. For the device to • Timer1 oscillator wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will 7. ADC is unaffected, if the dedicated FRC occur regardless of the state of the GIE bit. If the GIE oscillator is selected. bit is disabled, the device continues execution at the 8. I/O ports maintain the status they had before instruction after the SLEEP instruction. If the GIE bit is SLEEP was executed (driving high, low or enabled, the device executes the instruction after the high-impedance). SLEEP instruction, the device will then call the Interrupt 9. Resets other than WDT are not affected by Service Routine. In cases where the execution of the Sleep mode. instruction following SLEEP is not desirable, the user Refer to individual chapters for more details on should have a NOP after the SLEEP instruction. peripheral operation during Sleep. The WDT is cleared when the device wakes up from To minimize current consumption, the following Sleep, regardless of the source of wake-up. conditions should be considered: • I/O pins should not be floating • External circuitry sinking current from I/O pins • Internal circuitry sourcing current from I/O pins • Current draw from pins with internal weak pull-ups • Modules using 31 kHz LFINTOSC • Modules using Timer1 oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section19.0 “Digital-to-Analog Converter (DAC) Module” and Section15.0 “Fixed Voltage Reference (FVR)” for more information on these modules.  2011-2014 Microchip Technology Inc. DS40001579E-page 87

PIC16(L)F1782/3 9.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the execution of a SLEEP instruction When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit - SLEEP instruction will be completely and interrupt flag bit set, one of the following will occur: executed - Device will immediately wake-up from Sleep • If the interrupt occurs before the execution of a SLEEP instruction - WDT and WDT prescaler will be cleared - SLEEP instruction will execute as a NOP. - TO bit of the STATUS register will be set - WDT and WDT prescaler will not be cleared - PD bit of the STATUS register will be cleared. - TO bit of the STATUS register will not be set Even if the flag bits were checked before executing a - PD bit of the STATUS register will not be SLEEP instruction, it may be possible for flag bits to cleared. become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) CLKOUT(2) T1OSC(3) Interrupt flag Interrupt Latency(4) GIE bit Processor in (INTCON reg.) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC - 1) Sleep Inst(PC + 1) Forced NOP Forced NOP Inst(0004h) Note 1: External clock. High, Medium, Low mode assumed. 2: CLKOUT is shown here for timing reference. 3: T1OSC; See Section30.0 “Electrical Specifications”. 4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. DS40001579E-page 88  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 9.2 Low-Power Sleep Mode 9.2.2 PERIPHERAL USAGE IN SLEEP “F” devices contain an internal Low Dropout (LDO) Some peripherals that can operate in Sleep mode will voltage regulator, which allows the device I/O pins to not operate properly with the Low-Power Sleep mode operate at voltages up to 5.5V while the internal device selected. The LDO will remain in the normal power logic operates at a lower voltage. The LDO and its mode when those peripherals are enabled. The associated reference circuitry must remain active when Low-Power Sleep mode is intended for use with these the device is in Sleep mode. “F” devices allow the user peripherals: to optimize the operating current in Sleep, depending • Brown-Out Reset (BOR) on the application requirements. • Watchdog Timer (WDT) A Low-Power Sleep mode can be selected by setting • External interrupt pin/Interrupt-on-change pins the VREGPM bit of the VREGCON register. With this • Timer1 (with external clock source) bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep. Note: “LF” devices do not have a configurable 9.2.1 SLEEP CURRENT VS. WAKE-UP Low-Power Sleep mode. “LF” devices are TIME an unregulated device and are always in In the default operating mode, the LDO and reference the lowest power state when in Sleep, with circuitry remain in the normal configuration while in no wake-up time penalty. These devices Sleep. The device is able to exit Sleep mode quickly have a lower maximum VDD and I/O since all circuits remain active. In Low-Power Sleep voltage than “F” devices. See mode, when waking up from Sleep, an extra delay time Section30.0 “Electrical Specifications” is required for these circuits to return to the normal for more information. configuration and stabilize. The Low-Power Sleep mode is beneficial for applica- tions that stay in Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.  2011-2014 Microchip Technology Inc. DS40001579E-page 89

PIC16(L)F1782/3 9.3 Register Definitions: Voltage Regulator Control REGISTER 9-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 — — — — — — VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up 0 = Normal-Power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as ‘1’. Maintain this bit set. Note 1: “F” devices only. 2: See Section30.0 “Electrical Specifications”. TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF RAIF 79 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 134 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 133 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 133 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIE2 OSEIE C2IE C1IE EEIE BCL1IE — C3IE CCP2IE 81 — Unimplemented — PIE4 — — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC1SIE 82 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 80 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — C3IF CCP2IF 84 — Unimplemented — PIR4 — — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF 85 STATUS — — — TO PD Z DC C 18 VREGCON — — — — — — VREGPM Reserved 90 WDTCON — — WDTPS<4:0> SWDTEN 94 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode. DS40001579E-page 90  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 10.0 LOW DROPOUT (LDO) On power-up, the external capacitor will load the LDO VOLTAGE REGULATOR voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source The “F” devices have an internal Low Dropout charges the external capacitor. After the cap is fully Regulator (LDO) which provide operation above 3.6V. charged, the device is released from Reset. For more The LDO regulates a voltage for the internal device information on the constant current rate, refer to the logic while permitting the VDD and I/O pins to operate LDO Regulator Characteristics Table in Section30.0 at a higher voltage. There is no user enable/disable “Electrical Specifications”. control available for the LDO, it is always active. The “LF” devices operate at a maximum VDD of 3.6V and does not incorporate an LDO. A device I/O pin may be configured as the LDO voltage output, identified as the VCAP pin. Although not required, an external low-ESR capacitor may be connected to the VCAP pin for additional regulator stability. The VCAPEN bit of Configuration Words determines if which pin is assigned as the VCAP pin. Refer to Table10-1. TABLE 10-1: VCAPEN SELECT BIT VCAPEN Pin 1 No VCAP 0 RA6 TABLE 10-2: SUMMARY OF CONFIGURATION WORD WITH LDO Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN CONFIG2 42 7:0 — — VCAPEN(1) — — — WRT<1:0> Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO. Note 1: “F” devices only.  2011-2014 Microchip Technology Inc. DS40001579E-page 91

PIC16(L)F1782/3 11.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (nominal) • Multiple Reset conditions • Operation during Sleep FIGURE 11-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0>=01 SWDTEN 23-bit Programmable WDTE<1:0>=11 LFINTOSC WDT Time-out Prescaler WDT WDTE<1:0>=10 Sleep WDTPS<4:0> DS40001579E-page 92  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 11.1 Independent Clock Source 11.3 Time-Out Period The WDT derives its time base from the 31kHz The WDTPS bits of the WDTCON register set the LFINTOSC internal oscillator. Time intervals in this time-out period from 1 ms to 256 seconds (nominal). chapter are based on a nominal interval of 1ms. See After a Reset, the default time-out period is two Section30.0 “Electrical Specifications” for the seconds. LFINTOSC tolerances. 11.4 Clearing the WDT 11.2 WDT Operating Modes The WDT is cleared when any of the following The Watchdog Timer module has four operating modes conditions occur: controlled by the WDTE<1:0> bits in Configuration • Any Reset Words. See Table11-1. • CLRWDT instruction is executed 11.2.1 WDT IS ALWAYS ON • Device enters Sleep • Device wakes up from Sleep When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on. • Oscillator fail • WDT is disabled WDT protection is active during Sleep. • Oscillator Start-up TImer (OST) is running 11.2.2 WDT IS OFF IN SLEEP See Table11-2 for more information. When the WDTE bits of Configuration Words are set to ‘10’, the WDT is on, except in Sleep. 11.5 Operation During Sleep WDT protection is not active during Sleep. When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes 11.2.3 WDT CONTROLLED BY SOFTWARE counting. When the WDTE bits of Configuration Words are set to When the device exits Sleep, the WDT is cleared ‘01’, the WDT is controlled by the SWDTEN bit of the again. The WDT remains clear until the OST, if WDTCON register. enabled, completes. See Section6.0 “Oscillator WDT protection is unchanged by Sleep. See Module (with Fail-Safe Clock Monitor)” for more Table11-1 for more details. information on the OST. When a WDT time-out occurs while the device is in TABLE 11-1: WDT OPERATING MODES Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits Device WDT WDTE<1:0> SWDTEN in the STATUS register are changed to indicate the Mode Mode event. See Section3.0 “Memory Organization” and 11 X X Active Status Register (Register3-1) for more information. Awake Active 10 X Sleep Disabled 1 Active 01 X 0 Disabled 00 X X Disabled TABLE 11-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0>=00 WDTE<1:0>=01 and SWDTEN = 0 WDTE<1:0>=10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) Unaffected  2011-2014 Microchip Technology Inc. DS40001579E-page 93

PIC16(L)F1782/3 11.6 Register Definitions: Watchdog Control REGISTER 11-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 — — WDTPS<4:0> SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32) • • • 10011 = Reserved. Results in minimum interval (1:32) 10010 = 1:8388608 (223) (Interval 256s nominal) 10001 = 1:4194304 (222) (Interval 128s nominal) 10000 = 1:2097152 (221) (Interval 64s nominal) 01111 = 1:1048576 (220) (Interval 32s nominal) 01110 = 1:524288 (219) (Interval 16s nominal) 01101 = 1:262144 (218) (Interval 8s nominal) 01100 = 1:131072 (217) (Interval 4s nominal) 01011 = 1:65536 (Interval 2s nominal) (Reset value) 01010 = 1:32768 (Interval 1s nominal) 01001 = 1:16384 (Interval 512ms nominal) 01000 = 1:8192 (Interval 256ms nominal) 00111 = 1:4096 (Interval 128ms nominal) 00110 = 1:2048 (Interval 64ms nominal) 00101 = 1:1024 (Interval 32ms nominal) 00100 = 1:512 (Interval 16ms nominal) 00011 = 1:256 (Interval 8ms nominal) 00010 = 1:128 (Interval 4ms nominal) 00001 = 1:64 (Interval 2ms nominal) 00000 = 1:32 (Interval 1ms nominal) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 1x: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 00: This bit is ignored. Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC. DS40001579E-page 94  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 68 STATUS — — — TO PD Z DC C 18 WDTCON — — WDTPS<4:0> SWDTEN 94 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer. TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 40 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.  2011-2014 Microchip Technology Inc. DS40001579E-page 95

PIC16(L)F1782/3 12.0 DATA EEPROM AND FLASH 12.1 EEADRL and EEADRH Registers PROGRAM MEMORY The EEADRH:EEADRL register pair can address up to CONTROL a maximum of 256bytes of data EEPROM or up to a maximum of 32K words of program memory. The data EEPROM and Flash program memory are readable and writable during normal operation (full VDD When selecting a program address value, the MSB of range). These memories are not directly mapped in the the address is written to the EEADRH register and the register file space. Instead, they are indirectly LSB is written to the EEADRL register. When selecting addressed through the Special Function Registers a EEPROM address value, only the LSB of the address (SFRs). There are six SFRs used to access these is written to the EEADRL register. memories: 12.1.1 EECON1 AND EECON2 REGISTERS • EECON1 EECON1 is the control register for EE memory • EECON2 accesses. • EEDATL Control bit EEPGD determines if the access will be a • EEDATH program or data memory access. When clear, any • EEADRL subsequent operations will operate on the EEPROM • EEADRH memory. When set, any subsequent operations will When interfacing the data memory block, EEDATL operate on the program memory. On Reset, EEPROM is holds the 8-bit data for read/write, and EEADRL holds selected by default. the address of the EEDATL location being accessed. Control bits RD and WR initiate read and write, These devices have 256 bytes of data EEPROM with respectively. These bits cannot be cleared, only set, in an address range from 0h to 0FFh. software. They are cleared in hardware at completion When accessing the program memory block, the of the read or write operation. The inability to clear the EEDATH:EEDATL register pair forms a 2-byte word WR bit in software prevents the accidental, premature that holds the 14-bit data for read/write, and the termination of a write operation. EEADRL and EEADRH registers form a 2-byte word The WREN bit, when set, will allow a write operation to that holds the 15-bit address of the program memory occur. On power-up, the WREN bit is clear. The location being read. WRERR bit is set when a write operation is interrupted The EEPROM data memory allows byte read and write. by a Reset during normal operation. In these situations, An EEPROM byte write automatically erases the following Reset, the user can check the WRERR bit location and writes the new data (erase before write). and execute the appropriate error handling routine. The write time is controlled by an on-chip timer. The Interrupt flag bit EEIF of the PIR2 register is set when write/erase voltages are generated by an on-chip write is complete. It must be cleared in the software. charge pump rated to operate over the voltage range of Reading EECON2 will read all ‘0’s. The EECON2 the device for byte or word operations. register is used exclusively in the data EEPROM write Depending on the setting of the Flash Program sequence. To enable writes, a specific pattern must be Memory Self Write Enable bits WRT<1:0> of the written to EECON2. Configuration Words, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are always allowed. When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. DS40001579E-page 96  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 12.2 Using the Data EEPROM 12.2.2 WRITING TO THE DATA EEPROM MEMORY The data EEPROM is a high-endurance, byte address- able array that has been optimized for the storage of To write an EEPROM data location, the user must first frequently changing information (e.g., program write the address to the EEADRL register and the data variables or other data that are updated often). When to the EEDATL register. Then the user must follow a variables in one section change frequently, while specific sequence to initiate the write for each byte. variables in another section do not change, it is The write will not initiate if the above sequence is not possible to exceed the total number of write cycles to followed exactly (write 55h to EECON2, write AAh to the EEPROM without exceeding the total number of EECON2, then set the WR bit) for each byte. Interrupts write cycles to a single byte. Refer to Section30.0 should be disabled during this codesegment. “Electrical Specifications”. If this is the case, then a Additionally, the WREN bit in EECON1 must be set to refresh of the array must be performed. For this reason, enable write. This mechanism prevents accidental variables that change infrequently (such as constants, writes to data EEPROM due to errant (unexpected) IDs, calibration, etc.) should be stored in Flash program code execution (i.e., lost programs). The user should memory. keep the WREN bit clear at all times, except when 12.2.1 READING THE DATA EEPROM updating EEPROM. The WREN bit is not cleared byhardware. MEMORY After a write sequence has been initiated, clearing the To read a data memory location, the user must write the WREN bit will not affect this write cycle. The WR bit will address to the EEADRL register, clear the EEPGD and be inhibited from being set unless the WREN bit is set. CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next At the completion of the write cycle, the WR bit is cycle, in the EEDATL register; therefore, it can be read cleared in hardware and the EE Write Complete in the next instruction. EEDATL will hold this value until Interrupt Flag bit (EEIF) is set. The user can either another read or until it is written to by the user (during enable this interrupt or poll this bit. EEIF must be a write operation). cleared by software. 12.2.3 PROTECTION AGAINST SPURIOUS EXAMPLE 12-1: DATA EEPROM READ WRITE BANKSELEEADRL ; MOVLW DATA_EE_ADDR ; There are conditions when the user may not want to MOVWF EEADRL ;Data Memory write to the data EEPROM memory. To protect against ;Address to read spurious EEPROM writes, various mechanisms have BCF EECON1, CFGS ;Deselect Config space been built-in. On power-up, WREN is cleared. Also, the BCF EECON1, EEPGD;Point to DATA memory Power-up Timer (64ms duration) prevents EEPROM BSF EECON1, RD ;EE Read write. MOVF EEDATL, W ;W = EEDATL The write initiate sequence and the WREN bit together help prevent an accidental write during: • Brown-out Note: Data EEPROM can be read regardless of • Power Glitch the setting of the CPD bit. • Software Malfunction 12.2.4 DATA EEPROM OPERATION DURING CODE-PROTECT Data memory can be code-protected by programming the CPD bit in the Configuration Words to ‘0’. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM.  2011-2014 Microchip Technology Inc. DS40001579E-page 97

PIC16(L)F1782/3 EXAMPLE 12-2: DATA EEPROM WRITE BANKSEL EEADRL ; MOVLW DATA_EE_ADDR ; MOVWF EEADRL ;Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATL ;Data Memory Value to write BCF EECON1, CFGS ;Deselect Configuration space BCF EECON1, EEPGD ;Point to DATA memory BSF EECON1, WREN ;Enable writes BCF INTCON, GIE ;Disable INTs. MOVLW 55h ; RequiredSequence MMMBOOOSVVVFWLWFWF E0EEEAEECACCOhOONNN221, WR ;;;;WWSerriit ttWeeR 5Ab5Aihht to begin write BSF INTCON, GIE ;Enable Interrupts BCF EECON1, WREN ;Disable writes BTFSC EECON1, WR ;Wait for write to complete GOTO $-2 ;Done FIGURE 12-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR PC PC + 1 EEADRH,EEADRL PPCC ++ 33 PC + 4 PC + 5 Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4) INSTR(PC - 1) BSF PMCON1,RD INSTR(PC + 1) Forced NOP INSTR(PC + 3) INSTR(PC + 4) executed here executed here executed here executed here executed here executed here RD bit EEDATH EEDATL Register DS40001579E-page 98  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 12.3 Flash Program Memory Overview 12.3.1 READING THE FLASH PROGRAM MEMORY It is important to understand the Flash program memory structure for erase and programming To read a program memory location, the user must: operations. Flash program memory is arranged in 1. Write the Least and Most Significant address rows. A row consists of a fixed number of 14-bit bits to the EEADRH:EEADRL register pair. program memory words. A row is the minimum block 2. Clear the CFGS bit of the EECON1 register. size that can be erased by user software. 3. Set the EEPGD control bit of the EECON1 Flash program memory may only be written or erased register. if the destination address is in a segment of memory 4. Then, set control bit RD of the EECON1 register. that is not write-protected, as defined in bits WRT<1:0> Once the read control bit is set, the program memory of Configuration Words. Flash controller will use the second instruction cycle to After a row has been erased, the user can reprogram read the data. This causes the second instruction all or a portion of this row. Data to be written into the immediately following the “BSF EECON1,RD” instruction program memory row is written to 14-bit wide data write to be ignored. The data is available in the very next cycle, latches. These write latches are not directly accessible in the EEDATH:EEDATL register pair; therefore, it can to the user, but may be loaded via sequential writes to be read as two bytes in the following instructions. the EEDATH:EEDATL register pair. EEDATH:EEDATL register pair will hold this value until Note: If the user wants to modify only a portion another read or until it is written to by the user. of a previously programmed row, then the Note1: The two instructions following a program contents of the entire row must be read and saved in RAM prior to the erase. memory read are required to be NOPs. This prevents the user from executing a The number of data write latches may not be equivalent two-cycle instruction on the next to the number of row locations. During programming, instruction after the RD bit is set. user software may need to fill the set of write latches 2: Flash program memory can be read and initiate a programming operation multiple times in regardless of the setting of the CP bit. order to fully reprogram an erased row. For example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times. The size of a program memory row and the number of program memory write latches may vary by device. See Table12-1 for details. TABLE 12-1: FLASH MEMORY ORGANIZATION BY DEVICE Device Erase Block (Row) Size/Boundary Number of Write Latches/Boundary PIC16(L)F1782/3 32 words, EEADRL<4:0> = 00000 32 words, EEADRL<4:0> = 00000  2011-2014 Microchip Technology Inc. DS40001579E-page 99

PIC16(L)F1782/3 EXAMPLE 12-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL EEADRL ; Select Bank for EEPROM registers MOVLW PROG_ADDR_LO ; MOVWF EEADRL ; Store LSB of address MOVLW PROG_ADDR_HI ; MOVWL EEADRH ; Store MSB of address BCF EECON1,CFGS ; Do not select Configuration Space BSF EECON1,EEPGD ; Select Program Memory BCF INTCON,GIE ; Disable interrupts BSF EECON1,RD ; Initiate read NOP ; Executed (Figure 12-1) NOP ; Ignored (Figure 12-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS40001579E-page 100  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 12.3.2 ERASING FLASH PROGRAM unlock sequence is required to load a write latch with MEMORY data or initiate a Flash programming operation. This unlock sequence should not be interrupted. While executing code, program memory can only be erased by rows. To erase a row: 1. Set the EEPGD and WREN bits of the EECON1 register. 1. Load the EEADRH:EEADRL register pair with 2. Clear the CFGS bit of the EECON1 register. the address of new row to be erased. 3. Set the LWLO bit of the EECON1 register. When 2. Clear the CFGS bit of the EECON1 register. the LWLO bit of the EECON1 register is ‘1’, the 3. Set the EEPGD, FREE, and WREN bits of the write sequence will only load the write latches EECON1 register. and will not initiate the write to Flash program 4. Write 55h, then AAh, to EECON2 (Flash memory. programming unlock sequence). 4. Load the EEADRH:EEADRL register pair with 5. Set control bit WR of the EECON1 register to the address of the location to be written. begin the erase operation. 5. Load the EEDATH:EEDATL register pair with 6. Poll the FREE bit in the EECON1 register to the program memory data to be written. determine when the row erase has completed. 6. Write 55h, then AAh, to EECON2, then set the See Example12-4. WR bit of the EECON1 register (Flash programming unlock sequence). The write latch After the “BSF EECON1,WR” instruction, the processor is now loaded. requires two cycles to set up the erase operation. The user must place two NOP instructions after the WR bit is 7. Increment the EEADRH:EEADRL register pair set. The processor will halt internal operations for the to point to the next location. typical 2ms erase time. This is not Sleep mode as the 8. Repeat steps 5 through 7 until all but the last clocks and peripherals will continue to run. After the write latch has been loaded. erase cycle, the processor will resume operation with 9. Clear the LWLO bit of the EECON1 register. the third instruction after the EECON1 write instruction. When the LWLO bit of the EECON1 register is ‘0’, the write sequence will initiate the write to 12.3.3 WRITING TO FLASH PROGRAM Flash program memory. MEMORY 10. Load the EEDATH:EEDATL register pair with Program memory is programmed using the following the program memory data to be written. steps: 11. Write 55h, then AAh, to EECON2, then set the 1. Load the starting address of the word(s) to be WR bit of the EECON1 register (Flash programmed. programming unlock sequence). The entire 2. Load the write latches with data. latch block is now written to Flash program memory. 3. Initiate a programming operation. 4. Repeat steps 1 through 3 until all data is written. It is not necessary to load the entire write latch block with user program data. However, the entire write latch Before writing to program memory, the word(s) to be block will be written to program memory. written must be erased or previously unwritten. Program memory can only be erased one row at a time. An example of the complete write sequence for eight No automatic erase occurs upon the initiation of the words is shown in Example12-5. The initial address is write. loaded into the EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing. Program memory can be written one or more words at a time. The maximum number of words written at one After the “BSF EECON1,WR” instruction, the processor time is equal to the number of write latches. See requires two cycles to set up the write operation. The Figure12-2 (block writes to program memory with 32 user must place two NOP instructions after the WR bit is write latches) for more details. The write latches are set. The processor will halt internal operations for the aligned to the address boundary defined by EEADRL typical 2ms, only during the cycle in which the write as shown in Table12-1. Write operations do not cross takes place (i.e., the last word of the block write). This these boundaries. At the completion of a program is not Sleep mode as the clocks and peripherals will memory write operation, the write latches are reset to continue to run. The processor does not stall when contain 0x3FFF. LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third The following steps should be completed to load the instruction after the EECON1 WRITE instruction. write latches and program a block of program memory. These steps are divided into two parts. First, all write latches are loaded with data except for the last program memory location. Then, the last write latch is loaded and the programming sequence is initiated. A special  2011-2014 Microchip Technology Inc. DS40001579E-page 101

PIC16(L)F1782/3 FIGURE 12-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 7 5 0 7 0 EEDATH EEDATA 6 8 First word of block Last word of block to be written to be written 14 14 14 14 EEADRL<4:0> = 00000 EEADRL<4:0> = 00001 EEADRL<4:0> = 00010 EEADRL<4:0> = 11111 Buffer Register Buffer Register Buffer Register Buffer Register Program Memory EXAMPLE 12-4: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL EEADRL MOVF ADDRL,W ; Load lower 8 bits of erase address boundary MOVWF EEADRL MOVF ADDRH,W ; Load upper 6 bits of erase address boundary MOVWF EEADRH BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space BSF EECON1,FREE ; Specify an erase operation BSF EECON1,WREN ; Enable writes MOVLW 55h ; Start of required sequence to initiate erase MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne reer aasree ignored as processor ; halts to begin erase sequence NOP ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts DS40001579E-page 102  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 EXAMPLE 12-5: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL ; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) ; BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL EEADRH ; Bank 3 MOVF ADDRH,W ; Load initial address MOVWF EEADRH ; MOVF ADDRL,W ; MOVWF EEADRL ; MOVLW LOW DATA_ADDR ; Load initial data address MOVWF FSR0L ; MOVLW HIGH DATA_ADDR ; Load initial data address MOVWF FSR0H ; BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space BSF EECON1,WREN ; Enable writes BSF EECON1,LWLO ; Only Load Write Latches LOOP MOVIW FSR0++ ; Load first data byte into lower MOVWF EEDATL ; MOVIW FSR0++ ; Load second data byte into upper MOVWF EEDATH ; MOVF EEADRL,W ; Check if lower bits of address are '000' XORLW 0x07 ; Check if we're on the last of 8 addresses ANDLW 0x07 ; BTFSC STATUS,Z ; Exit if last of eight words, GOTO START_WRITE ; MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne rwer iatree ignored as processor ; halts to begin write sequence NOP ; Processor will stop here and wait for write to complete. ; After write processor continues with 3rd instruction. INCF EEADRL,F ; Still loading latches Increment address GOTO LOOP ; Write next latches START_WRITE BCF EECON1,LWLO ; No more loading latches - Actually start Flash program ; memory write MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne rwer iatree ignored as processor ; halts to begin write sequence NOP ; Processor will stop here and wait for write complete. ; after write processor continues with 3rd instruction BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts  2011-2014 Microchip Technology Inc. DS40001579E-page 103

PIC16(L)F1782/3 12.4 Modifying Flash Program Memory 12.5 User ID, Device ID and Configuration Word Access When modifying existing data in a program memory row, and data within that row must be preserved, it must Instead of accessing program memory or EEPROM first be read and saved in a RAM image. Program data memory, the User ID’s, Device ID/Revision ID and memory is modified using the following steps: Configuration Words can be accessed when CFGS=1 1. Load the starting address of the row to be in the EECON1 register. This is the region that would modified. be pointed to by PC<15>=1, but not all addresses are accessible. Different access may exist for reads and 2. Read the existing data from the row into a RAM writes. Refer to Table12-2. image. 3. Modify the RAM image to contain the new data When read access is initiated on an address outside the to be written into program memory. parameters listed in Table12-2, the EEDATH:EEDATL register pair is cleared. 4. Load the starting address of the row to be rewritten. 5. Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. 8. Repeat steps 6 and 7 as many times as required to reprogram the erased row. TABLE 12-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS=1) Address Function Read Access Write Access 8000h-8003h User IDs Yes Yes 8006h Device ID/Revision ID Yes No 8007h-8008h Configuration Words 1 and 2 Yes No EXAMPLE 12-3: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL EEADRL ; Select correct Bank MOVLW PROG_ADDR_LO ; MOVWF EEADRL ; Store LSB of address CLRF EEADRH ; Clear MSB of address BSF EECON1,CFGS ; Select Configuration Space BCF INTCON,GIE ; Disable interrupts BSF EECON1,RD ; Initiate read NOP ; Executed (See Figure 12-1) NOP ; Ignored (See Figure 12-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS40001579E-page 104  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 12.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example12-6) to the desired value to be written. Example12-6 shows how to verify a write to EEPROM. EXAMPLE 12-6: EEPROM WRITE VERIFY BANKSELEEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL, W ; BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue  2011-2014 Microchip Technology Inc. DS40001579E-page 105

PIC16(L)F1782/3 12.7 Register Definitions: EEPROM and Flash Control REGISTER 12-1: EEDATL: EEPROM DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 12-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — EEDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 EEDAT<13:8>: Read/write value for Most Significant bits of program memory REGISTER 12-3: EEADRL: EEPROM ADDRESS REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address REGISTER 12-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 —(1) EEADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address Note 1: Unimplemented, read as ‘1’. DS40001579E-page 106  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 12-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Accesses program space Flash memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, User ID and Device ID registers 0 = Accesses Flash program or data EEPROM memory bit 5 LWLO: Load Write Latches Only bit If CFGS=1 (Configuration space) OR CFGS=0 and EEPGD=1 (program Flash): 1 = The next WR command does not initiate a write; only the program memory latches are updated. 0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write of all the data stored in the program memory latches. If CFGS=0 and EEPGD=0: (Accessing data EEPROM) LWLO is ignored. The next WR command initiates a write to the data EEPROM. bit 4 FREE: Program Flash Erase Enable bit If CFGS=1 (Configuration space) OR CFGS=0 and EEPGD=1 (program Flash): 1 = Performs an erase operation on the next WR command (cleared by hardware after comple- tion of erase). 0 = Performs a write operation on the next WR command. If EEPGD=0 and CFGS=0: (Accessing data EEPROM) FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle. bit 3 WRERR: EEPROM Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit). 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash and data EEPROM bit 1 WR: Write Control bit 1 = Initiates a program Flash or data EEPROM program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash or data EEPROM is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash or data EEPROM data read.  2011-2014 Microchip Technology Inc. DS40001579E-page 107

PIC16(L)F1782/3 REGISTER 12-6: EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. Refer to Section12.2.2 “Writing to the Data EEPROM Memory” for more information. TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 107 EECON2 EEPROM Control Register 2 (not a physical register) 108* EEADRL EEADRL<7:0> 106 EEADRH —(1) EEADRH<6:0> 106 EEDATL EEDATL<7:0> 106 EEDATH — — EEDATH<5:0> 106 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE2 OSEIE C2IE C1IE EEIE BCL1IE — C3IE CCP2IE 81 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — C3IF CCP2IF 84 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by data EEPROM module. * Page provides register information. 2: Unimplemented, read as ‘1’. DS40001579E-page 108  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 13.0 I/O PORTS FIGURE 13-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of Read LATx TRISx the device) • LATx registers (output latch) D Q Some ports may have one or more of the following Write LATx Write PORTx additional registers. These registers are: CK VDD • ANSELx (analog select) Data Register • WPUx (weak pull-up) Data Bus In general, when a peripheral is enabled on a port pin, I/O pin that pin cannot be used as a general purpose output. Read PORTx However, the pin can still be read. To digital peripherals VSS ANSELx TABLE 13-1: PORT AVAILABILITY PER To analog peripherals DEVICE A B C E T T T T Device R R R R O O O O P P P P PIC16(L)F1782 ● ● ● ● PIC16(L)F1783 ● ● ● ● The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure13-1.  2011-2014 Microchip Technology Inc. DS40001579E-page 109

PIC16(L)F1782/3 13.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register13-1. For this device family, the following functions can be moved between different pins. • C2OUT output • CCP1 output • SDO output • SCL/SCK output • SDA/SDI output • TX/RX output • CCP2 output These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. DS40001579E-page 110  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 13.2 Register Definitions: Alternate Pin Function Control REGISTER 13-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 C2OUTSEL CCP1SEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2OUTSEL: C2OUT Pin Selection bit 1 = C2OUT is on pin RA6 0 = C2OUT is on pin RA5 bit 6 CCP1SEL: CCP1 Input/Output Pin Selection bit 1 = CCP1 is on pin RB0 0 = CCP1 is on pin RC2 bit 5 SDOSEL: MSSP SDO Pin Selection bit 1 = SDO is on pin RB5 0 = SDO is on pin RC5 bit 4 SCKSEL: MSSP Serial Clock (SCL/SCK) Pin Selection bit 1 = SCL/SCK is on pin RB7 0 = SCL/SCK is on pin RC3 bit 3 SDISEL: MSSP Serial Data (SDA/SDI) Output Pin Selection bit 1 = SDA/SDI is on pin RB6 0 = SDA/SDI is on pin RC4 bit 2 TXSEL: TX Pin Selection bit 1 = TX is on pin RB6 0 = TX is on pin RC6 bit 1 RXSEL: RX Pin Selection bit 1 = RX is on pin RB7 0 = RX is on pin RC7 bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit 1 = CCP2 is on pin RB3 0 = CCP2 is on pin RC1  2011-2014 Microchip Technology Inc. DS40001579E-page 111

PIC16(L)F1782/3 13.3 PORTA Registers 13.3.5 INPUT THRESHOLD CONTROL The INLVLA register (Register13-9) controls the input 13.3.1 DATA REGISTER voltage threshold for each of the available PORTA input PORTA is an 8-bit wide, bidirectional port. The pins. A selection between the Schmitt Trigger CMOS or corresponding data direction register is TRISA the TTL Compatible thresholds is available. The input (Register13-3). Setting a TRISA bit (= 1) will make the threshold is important in determining the value of a corresponding PORTA pin an input (i.e., disable the read of the PORTA register and also the level at which output driver). Clearing a TRISA bit (= 0) will make the an interrupt-on-change occurs, if that feature is corresponding PORTA pin an output (i.e., enables enabled. See SectionTABLE 30-1: “Supply Voltage” output driver and puts the contents of the output latch for more information on threshold levels. on the selected pin). Example13-1 shows how to Note: Changing the input threshold selection initialize PORTA. should be performed while all peripheral Reading the PORTA register (Register13-2) reads the modules are disabled. Changing the status of the pins, whereas writing to it will write to the threshold level during the time a module is PORT latch. All write operations are read-modify-write active may inadvertently generate a operations. Therefore, a write to a port implies that the transition associated with an input pin, port pins are read, this value is modified and then regardless of the actual voltage level on written to the PORT data latch (LATA). that pin. 13.3.2 DIRECTION CONTROL 13.3.6 ANALOG CONTROL The TRISA register (Register13-3) controls the The ANSELA register (Register13-5) is used to PORTA pin output drivers, even when they are being configure the Input mode of an I/O pin to analog. used as analog inputs. The user should ensure the bits Setting the appropriate ANSELA bit high will cause all in the TRISA register are maintained set when using digital reads on the pin to be read as ‘0’ and allow them as analog inputs. I/O pins configured as analog analog functions on the pin to operate correctly. inputs always read ‘0’. The state of the ANSELA bits has no effect on digital 13.3.3 OPEN DRAIN CONTROL output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode The ODCONA register (Register13-7) controls the will be analog. This can cause unexpected behavior open-drain feature of the port. Open drain operation is when executing read-modify-write instructions on the independently selected for each pin. When an affected port. ODCONA bit is set, the corresponding port output becomes an open drain driver capable of sinking Note: The ANSELA bits default to the Analog current only. When an ODCONA bit is cleared, the mode after Reset. To use any pins as corresponding port output pin is the standard push-pull digital general purpose or peripheral drive capable of sourcing and sinking current. inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. 13.3.4 SLEW RATE CONTROL EXAMPLE 13-1: INITIALIZING PORTA The SLRCONA register (Register13-8) controls the ; This code example illustrates slew rate option for each port pin. Slew rate control is ; initializing the PORTA register. The independently selectable for each port pin. When an ; other ports are initialized in the same SLRCONA bit is set, the corresponding port pin drive is ; manner. slew rate limited. When an SLRCONA bit is cleared, The corresponding port pin drive slews at the maximum BANKSEL PORTA ; rate possible. CLRF PORTA ;Init PORTA BANKSEL LATA ;Data Latch CLRF LATA ; BANKSEL ANSELA ; CLRF ANSELA ;digital I/O BANKSEL TRISA ; MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs DS40001579E-page 112  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 13.3.7 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table13-2. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input functions, such as ADC, and comparator inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown in the priority list. TABLE 13-2: PORTA OUTPUT PRIORITY Pin Name Function Priority(1) RA0 RA0 RA1 OPA1OUT RA1 RA2 DACOUT1 RA2 RA3 RA3 RA4 C1OUT RA4 RA5 C2OUT RA5 RA6 CLKOUT C2OUT RA6 RA7 RA7 Note 1: Priority listed from highest to lowest.  2011-2014 Microchip Technology Inc. DS40001579E-page 113

PIC16(L)F1782/3 13.4 Register Definitions: PORTA REGISTER 13-2: PORTA: PORTA REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RA<7:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 13-3: TRISA: PORTA TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISA<7:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output REGISTER 13-4: LATA: PORTA DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 LATA<7:0>: PORTA Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. DS40001579E-page 114  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 13-5: ANSELA: PORTA ANALOG SELECT REGISTER R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 5 ANSA7: Analog Select between Analog or Digital Function on pins RA7, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 6 Unimplemented: Read as ‘0’ bit 5-0 ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 13-6: WPUA: WEAK PULL-UP PORTA REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 WPUA<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output.  2011-2014 Microchip Technology Inc. DS40001579E-page 115

PIC16(L)F1782/3 REGISTER 13-7: ODCONA: PORTA OPEN DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ODA<7:0>: PORTA Open Drain Enable bits For RA<7:0> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) REGISTER 13-8: SLRCONA: PORTA SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SLRA<7:0>: PORTA Slew Rate Enable bits For RA<7:0> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 13-9: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 INLVLA<7:0>: PORTA Input Level Select bits For RA<7:0> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change DS40001579E-page 116  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 13-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 115 INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 116 LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 114 ODCONA ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 116 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 174 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 114 SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 116 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114 WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 115 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. TABLE 13-4: SUMMARY OF CONFIGURATION WORD WITH PORTA Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 40 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.  2011-2014 Microchip Technology Inc. DS40001579E-page 117

PIC16(L)F1782/3 13.5 PORTB Registers 13.5.4 INPUT THRESHOLD CONTROL PORTB is an 8-bit wide, bidirectional port. The The INLVLB register (Register13-17) controls the input corresponding data direction register is TRISB voltage threshold for each of the available PORTB (Register13-11). Setting a TRISB bit (= 1) will make the input pins. A selection between the Schmitt Trigger corresponding PORTB pin an input (i.e., put the CMOS or the TTL Compatible thresholds is available. corresponding output driver in a High-Impedance mode). The input threshold is important in determining the Clearing a TRISB bit (= 0) will make the corresponding value of a read of the PORTB register and also the level PORTB pin an output (i.e., enable the output driver and at which an interrupt-on-change occurs, if that feature put the contents of the output latch on the selected pin). is enabled. See SectionTABLE 30-1: “Supply Volt- Example13-1 shows how to initialize an I/O port. age” for more information on threshold levels. Reading the PORTB register (Register13-10) reads the Note: Changing the input threshold selection status of the pins, whereas writing to it will write to the should be performed while all peripheral PORT latch. All write operations are read-modify-write modules are disabled. Changing the operations. Therefore, a write to a port implies that the threshold level during the time a module is port pins are read, this value is modified and then written active may inadvertently generate a tran- to the PORT data latch (LATB). sition associated with an input pin, regard- less of the actual voltage level on that pin. 13.5.1 DIRECTION CONTROL 13.5.5 ANALOG CONTROL The TRISB register (Register13-11) controls the PORTB pin output drivers, even when they are being used as The ANSELB register (Register13-13) is used to analog inputs. The user should ensure the bits in the configure the Input mode of an I/O pin to analog. TRISB register are maintained set when using them as Setting the appropriate ANSELB bit high will cause all analog inputs. I/O pins configured as analog inputs digital reads on the pin to be read as ‘0’ and allow always read ‘0’. analog functions on the pin to operate correctly. The state of the ANSELB bits has no effect on digital out- 13.5.2 OPEN DRAIN CONTROL put functions. A pin with TRIS clear and ANSELB set will The ODCONB register (Register13-15) controls the still operate as a digital output, but the Input mode will be open-drain feature of the port. Open drain operation is analog. This can cause unexpected behavior when independently selected for each pin. When an executing read-modify-write instructions on the affected ODCONB bit is set, the corresponding port output port. becomes an open drain driver capable of sinking Note: The ANSELB bits default to the Analog current only. When an ODCONB bit is cleared, the mode after Reset. To use any pins as corresponding port output pin is the standard push-pull digital general purpose or peripheral drive capable of sourcing and sinking current. inputs, the corresponding ANSEL bits 13.5.3 SLEW RATE CONTROL must be initialized to ‘0’ by user software. The SLRCONB register (Register13-16) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONB bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONB bit is cleared, The corresponding port pin drive slews at the maximum rate possible. DS40001579E-page 118  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 13.5.6 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table13-5. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the priority list. TABLE 13-5: PORTB OUTPUT PRIORITY Pin Name Function Priority(1) RB0 CCP1 RB0 RB1 OPA2OUT RB1 RB2 CLKR RB2 RB3 CCP2 RB3 RB4 RB4 RB5 SDO C3OUT RB5 RB6 ICSPCLK SDA TX/CK RB6 RB7 ICSPDAT DACOUT2 SCL/SCK DT RB7 Note 1: Priority listed from highest to lowest.  2011-2014 Microchip Technology Inc. DS40001579E-page 119

PIC16(L)F1782/3 13.6 Register Definitions: PORTB REGISTER 13-10: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RB<7:0>: PORTB General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 13-11: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output REGISTER 13-12: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 LATB<7:0>: PORTB Output Latch Value bits(1) Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. DS40001579E-page 120  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 13-13: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Function on pins RB<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 13-14: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output.  2011-2014 Microchip Technology Inc. DS40001579E-page 121

PIC16(L)F1782/3 REGISTER 13-15: ODCONB: PORTB OPEN DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ODB<7:0>: PORTB Open Drain Enable bits For RB<7:0> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) REGISTER 13-16: SLRCONB: PORTB SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SLRB<7:0>: PORTB Slew Rate Enable bits For RB<7:0> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 13-17: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 INLVLB<7:0>: PORTB Input Level Select bits For RB<7:0> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change DS40001579E-page 122  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 13-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 121 INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 122 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 120 ODCONB ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 122 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 120 SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 122 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 120 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 121 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.  2011-2014 Microchip Technology Inc. DS40001579E-page 123

PIC16(L)F1782/3 13.7 PORTC Registers Voltage” for more information on threshold levels. Note: Changing the input threshold selection 13.7.1 DATA REGISTER should be performed while all peripheral PORTC is an 8-bit wide bidirectional port. The modules are disabled. Changing the thresh- corresponding data direction register is TRISC old level during the time a module is active (Register13-19). Setting a TRISC bit (= 1) will make the may inadvertently generate a transition corresponding PORTC pin an input (i.e., put the associated with an input pin, regardless of corresponding output driver in a High-Impedance mode). the actual voltage level on that pin. Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). 13.7.6 PORTC FUNCTIONS AND OUTPUT Example13-1 shows how to initialize an I/O port. PRIORITIES Reading the PORTC register (Register13-18) reads the Each PORTC pin is multiplexed with other functions. The status of the pins, whereas writing to it will write to the pins, their combined functions and their output priorities PORT latch. All write operations are read-modify-write are shown in Table13-7. operations. Therefore, a write to a port implies that the When multiple outputs are enabled, the actual pin port pins are read, this value is modified and then written control goes to the peripheral with the highest priority. to the PORT data latch (LATC). Analog input and some digital input functions are not 13.7.2 DIRECTION CONTROL included in the list below. These input functions can remain active when the pin is configured as an output. The TRISC register (Register13-19) controls the Certain digital input functions override other port PORTC pin output drivers, even when they are being functions and are included in the priority list. used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them TABLE 13-7: PORTC OUTPUT PRIORITY as analog inputs. I/O pins configured as analog inputs always read ‘0’. Pin Name Function Priority(1) RC0 T1OSO 13.7.3 OPEN DRAIN CONTROL PSMC1A The ODCONC register (Register13-22) controls the RC0 open-drain feature of the port. Open drain operation is RC1 PSMC1B independently selected for each pin. When an CCP2 ODCONC bit is set, the corresponding port output RC1 becomes an open drain driver capable of sinking current only. When an ODCONC bit is cleared, the RC2 PSMC1C corresponding port output pin is the standard push-pull CCP1 drive capable of sourcing and sinking current. RC2 RC3 PSMC1D 13.7.4 SLEW RATE CONTROL SCL The SLRCONC register (Register13-23) controls the SCK slew rate option for each port pin. Slew rate control is RC3 independently selectable for each port pin. When an RC4 PSMC1E SLRCONC bit is set, the corresponding port pin drive is SDA slew rate limited. When an SLRCONC bit is cleared, RC4 The corresponding port pin drive slews at the maximum RC5 PSMC1F rate possible. SDO RC5 13.7.5 INPUT THRESHOLD CONTROL RC6 PSMC2A The INLVLC register (Register13-24) controls the input TX/CK voltage threshold for each of the available PORTC RC6 input pins. A selection between the Schmitt Trigger RC7 PSMC2B CMOS or the TTL Compatible thresholds is available. DT The input threshold is important in determining the RC7 value of a read of the PORTC register and also the level at which an interrupt-on-change occurs, if that Note 1: Priority listed from highest to lowest. feature is enabled. See SectionTABLE 30-1: “Supply DS40001579E-page 124  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 13.8 Register Definitions: PORTC REGISTER 13-18: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. REGISTER 13-19: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output REGISTER 13-20: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits(1) Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values.  2011-2014 Microchip Technology Inc. DS40001579E-page 125

PIC16(L)F1782/3 REGISTER 13-21: WPUC: WEAK PULL-UP PORTC REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 WPUC<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. REGISTER 13-22: ODCONC: PORTC OPEN DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ODC<7:0>: PORTC Open Drain Enable bits For RC<7:0> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) REGISTER 13-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SLRC<7:0>: PORTC Slew Rate Enable bits For RC<7:0> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate DS40001579E-page 126  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 13-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 INLVLC<7:0>: PORTC Input Level Select bits For RC<7:0> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change TABLE 13-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 125 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 125 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 126 INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 127 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 125 ODCONC ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 126 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 125 SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 126 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.  2011-2014 Microchip Technology Inc. DS40001579E-page 127

PIC16(L)F1782/3 13.9 PORTE Registers RE3 is input only, and also functions as MCLR. The MCLR feature can be disabled via a configuration fuse. RE3 also supplies the programming voltage. The TRIS bit for RE3 (TRISE3) always reads ‘1’. 13.9.1 INPUT THRESHOLD CONTROL The INLVLE register (Register13-28) controls the input voltage threshold for each of the available PORTE input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTE register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See SectionTABLE 30-1: “Supply Volt- age” for more information on threshold levels. Note: Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. 13.9.2 PORTE FUNCTIONS AND OUTPUT PRIORITIES No output priorities. RE3 is an input-only pin. DS40001579E-page 128  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 13.10 Register Definitions: PORTE REGISTER 13-25: PORTE: PORTE REGISTER U-0 U-0 U-0 U-0 R-x/u U-0 U-0 U-0 — — — — RE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 RE3: PORTE Input Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL bit 2-0 Unimplemented: Read as ‘0’ REGISTER 13-26: TRISE: PORTE TRI-STATE REGISTER U-0 U-0 U-0 U-0 U-1(1) U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 Unimplemented: Read as ‘1’ bit 2-0 Unimplemented: Read as ‘0’ Note 1: Unimplemented, read as ‘1’.  2011-2014 Microchip Technology Inc. DS40001579E-page 129

PIC16(L)F1782/3 REGISTER 13-27: WPUE: WEAK PULL-UP PORTE REGISTER U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0 — — — — WPUE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 WPUE3: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 2-0 Unimplemented: Read as ‘0’ Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. REGISTER 13-28: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0 — — — — INLVLE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 INLVLE3: PORTE Input Level Select bit(1) 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change bit 2-0 Unimplemented: Read as ‘0’ TABLE 13-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 ADRMD CHS<4:0> GO/DONE ADON 147 INLVLE — — — — INLVLE3 — — — 130 PORTE — — — — RE3 — — — 129 TRISE — — — — —(1) — — — 129 WPUE — — — — WPUE3 — — — 130 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Note 1: Unimplemented, read as ‘1’. 2: PIC16(L)F1783 only DS40001579E-page 130  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 14.0 INTERRUPT-ON-CHANGE 14.3 Interrupt Flags All pins on all ports can be configured to operate as The bits located in the IOCxF registers are status flags Interrupt-On-Change (IOC) pins. An interrupt can be that correspond to the Interrupt-on-change pins of each generated by detecting a signal that has either a rising port. If an expected edge is detected on an appropriately edge or a falling edge. Any individual pin, or combination enabled pin, then the status flag for that pin will be set, of pins, can be configured to generate an interrupt. The and an interrupt will be generated if the IOCIE bit is set. interrupt-on-change module has the following features: The IOCIF bit of the INTCON register reflects the status of all IOCxF bits. • Interrupt-on-Change enable (Master Switch) • Individual pin configuration 14.4 Clearing Interrupt Flags • Rising and falling edge detection • Individual pin interrupt flags The individual status flags, (IOCxF register bits), can be cleared by resetting them to zero. If another edge is Figure14-1 is a block diagram of the IOC module. detected during this clearing operation, the associated status flag will be set at the end of the sequence, 14.1 Enabling the Module regardless of the value actually being written. To allow individual pins to generate an interrupt, the In order to ensure that no detected edge is lost while IOCIE bit of the INTCON register must be set. If the clearing flags, only AND operations masking out known IOCIE bit is disabled, the edge detection on the pin will changed bits should be performed. The following still occur, but an interrupt will not be generated. sequence is an example of what should be performed. 14.2 Individual Pin Configuration EXAMPLE 14-1: CLEARING INTERRUPT FLAGS For each pin, a rising edge detector and a falling edge (PORTA EXAMPLE) detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To MOVLW 0xff enable a pin to detect a falling edge, the associated bit XORWF IOCAF, W of the IOCxN register is set. ANDWF IOCAF, F A pin can be configured to detect rising and falling edges simultaneously by setting the associated bits in 14.5 Operation in Sleep both of the IOCxP and IOCxN registers. The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the affected IOCxF register will be updated prior to the first instruction executed out of Sleep.  2011-2014 Microchip Technology Inc. DS40001579E-page 131

PIC16(L)F1782/3 FIGURE 14-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q Q4Q1 CK edge detect R RBx data bus = S to data bus IOCBPx D Q 0 or 1 D Q IOCBFx CK write IOCBFx CK IOCIE R Q2 from all other IOCBFx individual IOC interrupt pin detectors to CPU core Q1 Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q3 Q4 Q4 Q4 Q4 Q4Q1 Q4Q1 Q4Q1 Q4Q1 DS40001579E-page 132  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 14.6 Register Definitions: Interrupt-on-Change Control REGISTER 14-1: IOCxP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCxP7 IOCxP6 IOCxP5 IOCxP4 IOCxP3 IOCxP2 IOCxP1 IOCxP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCxP<7:0>: Interrupt-on-Change Positive Edge Enable bits(1) 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. Note 1: For IOCEP register, bit 3 (IOCEP3) is the only implemented bit in the register. REGISTER 14-2: IOCxN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCxN7 IOCxN6 IOCxN5 IOCxN4 IOCxN3 IOCxN2 IOCxN1 IOCxN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCxN<7:0>: Interrupt-on-Change Negative Edge Enable bits(1) 1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. Note 1: For IOCEN register, bit 3 (IOCEN3) is the only implemented bit in the register.  2011-2014 Microchip Technology Inc. DS40001579E-page 133

PIC16(L)F1782/3 REGISTER 14-3: IOCxF: INTERRUPT-ON-CHANGE FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCxF7 IOCxF6 IOCxF5 IOCxF4 IOCxF3 IOCxF2 IOCxF1 IOCxF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-0 IOCxF<7:0>: Interrupt-on-Change Flag bits(1) 1 = An enabled change was detected on the associated pin. Set when IOCxPx=1 and a rising edge was detected RBx, or when IOCxNx=1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. Note 1: For IOCEF register, bit 3 (IOCEF3) is the only implemented bit in the register. TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 121 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 134 IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 133 IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 133 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 134 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 133 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 133 IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 134 IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 133 IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 133 IOCEF — — — — IOCEF3 — — — 134 IOCEN — — — — IOCEN3 — — — 133 IOCEP — — — — IOCEP3 — — — 133 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 120 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. DS40001579E-page 134  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 15.0 FIXED VOLTAGE REFERENCE 15.1 Independent Gain Amplifiers (FVR) The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two The Fixed Voltage Reference, or FVR, is a stable independent programmable gain amplifiers. Each voltage reference, independent of VDD, with 1.024V, amplifier can be programmed for a gain of 1x, 2x or 4x, 2.048V or 4.096V selectable output levels. The output to produce the three possible voltage levels. of the FVR can be configured to supply a reference voltage to the following: The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for • ADC input channel the reference supplied to the ADC module. Reference • ADC positive reference Section17.0 “Analog-to-Digital Converter (ADC) • Comparator positive input Module” for additional information. • Digital-to-Analog Converter (DAC) The CDAFVR<1:0> bits of the FVRCON register are The FVR can be enabled by setting the FVREN bit of used to enable and configure the gain amplifier settings the FVRCON register. for the reference supplied to the DAC and comparator module. Reference Section19.0 “Digital-to-Analog Converter (DAC) Module” and Section20.0 “Comparator Module” for additional information. 15.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section30.0 “Electrical Specifications” for the minimum delay requirement. 15.3 FVR Buffer Stabilization Period When either FVR Buffer1 or FVR Buffer 2 is enabled, the buffer amplifier circuits require 30s to stabilize. This stabilization time is required even when the FVR is already operating and stable.  2011-2014 Microchip Technology Inc. DS40001579E-page 135

PIC16(L)F1782/3 FIGURE 15-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 X1 X2 FVR BUFFER1 X4 (To ADC Module) CDAFVR<1:0> 2 X1 X2 FVR BUFFER2 X4 (To Comparators, DAC) HFINTOSC Enable HFINTOSC To BOR, LDO + FVREN _ FVRRDY Any peripheral requiring the Fixed Reference (See Table15-1) TABLE 15-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral Conditions Description HFINTOSC FOSC<2:0> = 100 and INTOSC is active and device is not in Sleep IRCF<3:0>  000x BOREN<1:0> = 11 BOR always enabled BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled LDO All PIC16F1782/3 devices, when The device runs off of the ULP regulator when in Sleep mode. VREGPM = 1 and not in Sleep PSMC 64 MHz PxSRC<1:0> 64 MHz clock forces HFINTOSC on during Sleep. DS40001579E-page 136  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 15.4 Register Definitions: FVR Control REGISTER 15-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FVREN FVRRDY(1) TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bit 11 =Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 =Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 =Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 =Comparator and DAC Fixed Voltage Reference Peripheral output is off. bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit 11 =ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 =ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 =ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 =ADC Fixed Voltage Reference Peripheral output is off. Note 1: FVRRDY is always ‘1’ on “F” devices only. 2: Fixed Voltage Reference output cannot exceed VDD. 3: See Section16.0 “Temperature Indicator Module” for additional information. TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 137 Legend: Shaded cells are not used with the Fixed Voltage Reference.  2011-2014 Microchip Technology Inc. DS40001579E-page 137

PIC16(L)F1782/3 16.0 TEMPERATURE INDICATOR FIGURE 16-1: TEMPERATURE CIRCUIT MODULE DIAGRAM This family of devices is equipped with a temperature circuit designed to measure the operating temperature VDD of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The TSEN output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. TSRNG The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A one- point calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point VOUT To ADC calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal Temperature Indicator” (DS01333) for more details regarding the calibration process. 16.1 Circuit Operation 16.2 Minimum Operating VDD Figure16-1 shows a simplified block diagram of the When the temperature circuit is operated in low range, temperature circuit. The proportional voltage output is the device may be operated at any operating voltage achieved by measuring the forward voltage drop across that is within specifications. multiple silicon junctions. When the temperature circuit is operated in high range, Equation16-1 describes the output characteristics of the device operating voltage, VDD, must be high the temperature indicator. enough to ensure that the temperature circuit is correctly biased. EQUATION 16-1: VOUT RANGES Table16-1 shows the recommended minimum VDD vs. range setting. High Range: VOUT = VDD - 4VT TABLE 16-1: RECOMMENDED VDD VS. Low Range: VOUT = VDD - 2VT RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 The temperature sense circuit is integrated with the 3.6V 1.8V Fixed Voltage Reference (FVR) module. See Section15.0 “Fixed Voltage Reference (FVR)” for 16.3 Temperature Output more information. The output of the circuit is measured using the internal The circuit is enabled by setting the TSEN bit of the Analog-to-Digital Converter. A channel is reserved for FVRCON register. When disabled, the circuit draws no the temperature circuit output. Refer to Section17.0 current. “Analog-to-Digital Converter (ADC) Module” for The circuit operates in either high or low range. The high detailed information. range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This 16.4 ADC Acquisition Time provides more resolution over the temperature range, but may be less consistent from part to part. This range To ensure accurate temperature measurements, the requires a higher bias voltage to operate and thus, a user must wait at least 200s after the ADC input higher VDD is needed. multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, The low range is selected by clearing the TSRNG bit of the user must wait 200s between sequential the FVRCON register. The low range generates a lower conversions of the temperature indicator output. voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low- voltage operation. DS40001579E-page 138  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 16-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG — — ADFVR<1:0> 136 Legend: Shaded cells are unused by the temperature indicator module.  2011-2014 Microchip Technology Inc. DS40001579E-page 139

PIC16(L)F1782/3 17.0 ANALOG-TO-DIGITAL the conversion result into the ADC result registers CONVERTER (ADC) MODULE (ADRESH:ADRESL register pair). Figure17-1 shows the block diagram of the ADC. The Analog-to-Digital Converter (ADC) allows The ADC voltage reference is software selectable to be conversion of a single-ended and differential analog either internally generated or externally supplied. input signals to a 12-bit binary representation of that The ADC can generate an interrupt upon completion of signal. This device uses analog inputs, which are a conversion. This interrupt can be used to wake-up the multiplexed into a single sample and hold circuit. The device from Sleep. output of the sample and hold is connected to the input of the converter. The converter generates a 12-bit binary result via successive approximation and stores FIGURE 17-1: ADC BLOCK DIAGRAM ADPREF = 11 VDD ADPREF = 00 VREF+ ADPREF = 01 AN0 00000 AN1 00001 VREF-/AN2 00010 VREF+/AN3 00011 ADNREF = 1 AN4 00100 Reserved 00101 ADPNEF = 0 Reserved 00110 10 Ref+ Ref- Reserved 00111 1 + AN8 01000 ADC - 12 AN9 01001 GO/DONE 0 AN10 01010 ADRMD 12 AN11 01011 0 = Sign Magnitude AN12 01100 ADFM ADON(1) 1 = 2’s Complement AN13 01101 16 VSS ADRESH ADRESL Temperature Indicator 11101 DAC_output 11110 FVR Buffer1 11111 CHS<4:0>(2) CHSN<3:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: See ADCON0 register (Register17-1) and ADCON2 register (Register17-3) for detailed analog channel selection per device. DS40001579E-page 140  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 17.1 ADC Configuration 17.1.3 ADC VOLTAGE REFERENCE When configuring and using the ADC the following The ADPREF bits of the ADCON1 register provide functions must be considered: control of the positive voltage reference. The positive voltage reference can be: • Port configuration • VREF+ • Channel selection • VDD - Single-ended • FVR Buffer1 - Differential • ADC voltage reference selection The ADNREF bits of the ADCON1 register provide control of the negative voltage reference. The negative • ADC conversion clock source voltage reference can be: • Interrupt control • VREF- pin • Result formatting • VSS 17.1.1 PORT CONFIGURATION See Section15.0 “Fixed Voltage Reference (FVR)” The ADC can be used to convert both analog and for more details on the Fixed Voltage Reference. digital signals. When converting analog signals, the I/O 17.1.4 CONVERSION CLOCK pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to The source of the conversion clock is software Section13.0 “I/O Ports” for more information. selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: Note: Analog voltages on any pin that is defined as a digital input may cause the input • FOSC/2 buffer to conduct excess current. • FOSC/4 • FOSC/8 17.1.2 CHANNEL SELECTION • FOSC/16 There are up to 14 channel selections available: • FOSC/32 • AN<13:8, 4:0> pins • FOSC/64 • Temperature Indicator • FRC (dedicated internal FRC oscillator) • DAC_output The time to complete one bit conversion is defined as • FVR (Fixed Voltage Reference) Output TAD. One full 12-bit conversion requires 15 TAD periods as shown in Figure17-2. Refer to Section15.0 “Fixed Voltage Reference (FVR)” and Section16.0 “Temperature Indicator For correct conversion, the appropriate TAD specification Module” for more information on these channel must be met. Refer to the ADC conversion requirements selections. in Section30.0 “Electrical Specifications” for more information. Table17-1 gives examples of appropriate When converting differential signals, the negative input ADC clock selections. for the channel is selected with the CHSN<3:0> bits of the ADCON2 register. Any positive input can be paired Note: Unless using the FRC, any changes in the with any negative input to determine the differential system clock frequency will change the channel. ADC clock frequency, which may The CHS<4:0> bits of the ADCON0 register determine adversely affect the ADC result. which positive channel is selected. When CHSN<3:0> = 1111 then the ADC is effectively a single ended ADC converter. When changing channels, a delay is required before starting the next conversion.  2011-2014 Microchip Technology Inc. DS40001579E-page 141

PIC16(L)F1782/3 TABLE 17-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Clock Source FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3) FOSC/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3) FOSC/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.0 s(3) FOSC/64 110 2.0 s 3.2 s 4.0 s 8.0 s(3) 16.0 s(3) 64.0 s(3) FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 1.6 s for VDD. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 17-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD14 TAD15TAD16 TAD17 sign b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Holding cap. starts discharge Holding cap disconnected Set GO from input bit Input Sample On the following cycle: GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS40001579E-page 142  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 17.1.5 INTERRUPTS 17.1.6 RESULT FORMATTING The ADC module allows for the ability to generate an The 10-bit and 12-bit ADC conversion results can be interrupt upon completion of an Analog-to-Digital supplied in two formats: 2’s complement or conversion. The ADC Interrupt Flag is the ADIF bit in sign-magnitude. The ADFM bit of the ADCON1 register the PIR1 register. The ADC Interrupt Enable is the controls the output format. Sign magnitude is left ADIE bit in the PIE1 register. The ADIF bit must be justified with the sign bit in the LSb position. Negative cleared in software. numbers are indicated when the sign bit is '1'. Note1: The ADIF bit is set at the completion of Two's complement is right justified with the sign every conversion, regardless of whether extended into the most significant bits. or not the ADC interrupt is enabled. Figure17-3 shows the two output formats. Table17-2 2: The ADC operates during Sleep only shows conversion examples. when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. FIGURE 17-3: ADC CONVERSION RESULT FORMAT 12-bit sign and magnitude Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ‘0’ ‘0’ ‘0’ Sign ADFM = 0 bit 7 bit 0 bit 7 bit 0 ADRMD = 0 12-bit ADC Result Loaded with ‘0’ 12-bit 2’s compliment Bit 12 Bit 12 Bit 12 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADFM = 1 bit 7 bit 0 bit 7 bit 0 ADRMD = 0 Loaded with Sign bits’ 12-bit ADC Result 10-bit sign and magnitude Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Sign ADFM = 0 bit 7 bit 0 bit 7 bit 0 ADRMD = 1 10-bit ADC Result Loaded with ‘0’ 10-bit 2’s compliment Bit 10 Bit 10 Bit 10 Bit 10 Bit 10 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADFM = 1 bit 7 bit 0 bit 7 bit 0 ADRMD = 1 Loaded with Sign bits’ 10-bit ADC Result  2011-2014 Microchip Technology Inc. DS40001579E-page 143

PIC16(L)F1782/3 TABLE 17-2: ADC OUTPUT RESULTS FORMAT Sign and Magnitude Result 2’s Compliment Result Absolute ADC Value ADFM = 0, ADRMD = 0 ADFM = 1, ADRMD = 0 (decimal) ADRESH ADRESL ADRESH ADRESL (ADRES<15:8>) (ADRES<7:0>) (ADRES<15:8>) (ADRES<7:0>) + 4095 1111 1111 1111 0000 0000 1111 1111 1111 + 2355 1001 0011 0011 0000 0000 1001 0011 0011 + 0001 0000 0000 0001 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 - 0001 0000 0000 0001 0001 1111 1111 1111 1111 - 4095 1111 1111 1111 0001 1111 0000 0000 0001 - 4096 0000 0000 0000 0001 1111 0000 0000 0000 Note1: For the RSD ADC, the raw 13-bits from the ADC is presented in 2’s compliment format, so no data translation is required for 2’s compliment results. 2: For the SAR ADC, the raw 13-bits from the ADC is presented in sign and magnitude format, so no data translation is required for sign and magnitude results DS40001579E-page 144  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 17.2 ADC Operation 17.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This 17.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC To enable the ADC module, the ADON bit of the option. When the FRC oscillator source is selected, the ADCON0 register must be set to a ‘1’. Setting the ADC waits one additional instruction before starting the GO/DONE bit of the ADCON0 register to a ‘1’ will clear conversion. This allows the SLEEP instruction to be the ADRESH and ADRESL registers and start the executed, which can reduce system noise during the Analog-to-Digital conversion. conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion Note: The GO/DONE bit should not be set in the completes. If the ADC interrupt is disabled, the ADC same instruction that turns on the ADC. module is turned off after the conversion completes, Refer to Section17.2.6 “A/D Conversion although the ADON bit remains set. Procedure”. When the ADC clock source is something other than 17.2.2 COMPLETION OF A CONVERSION FRC, a SLEEP instruction causes the present conver- sion to be aborted and the ADC module is turned off, When the conversion is complete, the ADC module will: although the ADON bit remains set. • Clear the GO/DONE bit 17.2.5 AUTO-CONVERSION TRIGGER • Set the ADIF Interrupt Flag bit The Auto-conversion Trigger allows periodic ADC mea- 17.2.3 TERMINATING A CONVERSION surements without software intervention. When a rising When a conversion is terminated before completion by edge of the selected source occurs, the GO/DONE bit clearing the GO/DONE bit then the partial results are is set by hardware. discarded and the results in the ADRESH and ADRESL The Auto-conversion Trigger source is selected with registers from the previous conversion remain the TRIGSEL<3:0> bits of the ADCON2 register. unchanged. Using the Auto-conversion Trigger does not assure proper ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met. Note: A device Reset forces all registers to their Auto-conversion sources are: Reset state. Thus, the ADC module is turned off and any pending conversion is • CCP1 terminated. • CCP2 • PSMC1(1) • PSMC2(1) Note: The PSMC clock frequency, after the prescaler, must be less than FOSC/4 to ensure that the ADC detects the auto-conversion trigger. This limitation can be overcome by synchronizing a slave PSMC, running at the required slower clock frequency, to the first PSMC and triggering the conversion from the slave PSMC.  2011-2014 Microchip Technology Inc. DS40001579E-page 145

PIC16(L)F1782/3 17.2.6 A/D CONVERSION PROCEDURE EXAMPLE 17-1: A/D CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. 1. Configure Port: ; • Disable pin output driver (Refer to the TRIS ;Conversion start & polling for completion register) ; are included. • Configure pin as analog (Refer to the ANSEL ; register) BANKSEL ADCON1 ; MOVLW B’11110000’ ;2’s complement, Frc 2. Configure the ADC module: ;clock • Select ADC conversion clock MOVWF ADCON1 ;Vdd and Vss Vref • Configure voltage reference MOVLW B’00001111’ ;set negative input MOVWF ADCON2 ;to negative • Select ADC input channel ;reference • Turn on ADC module BANKSEL TRISA ; 3. Configure ADC interrupt (optional): BSF TRISA,0 ;Set RA0 to input • Clear ADC interrupt flag BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog • Enable ADC interrupt BANKSEL ADCON0 ; • Enable peripheral interrupt MOVLW B’00000001’ ;Select channel AN0 • Enable global interrupt(1) MOVWF ADCON0 ;Turn ADC On 4. Wait the required acquisition time(2). CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion 5. Start conversion by setting the GO/DONE bit. BTFSC ADCON0,ADGO ;Is conversion done? 6. Wait for ADC conversion to complete by one of GOTO $-1 ;No, test again the following: BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits • Polling the GO/DONE bit MOVWF RESULTHI ;store in GPR space • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result. 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section17.4 “ADC Acquisition Requirements”. DS40001579E-page 146  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 17.3 Register Definitions: ADC Control REGISTER 17-1: ADCON0: ADC CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADRMD CHS<4:0> GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADRMD: ADC Result Mode bit 1 = ADRESL and ADRESH provide data formatted for a 10-bit result 0 = ADRESL and ADRESH provide data formatted for a 12-bit result See Figure17-3 for details bit 6-2 CHS<4:0>: Positive Differential Input Channel Select bits 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(3) 11110 = DAC_output(2) 11101 = Temperature Indicator(4) 11100 = Reserved. No channel connected. • • • 01110 = Reserved. No channel connected. 01101 = AN13 01100 = AN12 01011 = AN11 01010 = AN10 01001 = AN9 01000 = AN8 00111 = Reserved. No channel connected. 00110 = Reserved. No channel connected. 00101 = Reserved. No channel connected. 00100 = AN4 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0 bit 1 GO/DONE: ADC Conversion Status bit 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC conversion has completed. 0 = ADC conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: See Section19.0 “Digital-to-Analog Converter (DAC) Module” for more information. 2: See Section15.0 “Fixed Voltage Reference (FVR)” for more information. 3: See Section16.0 “Temperature Indicator Module” for more information.  2011-2014 Microchip Technology Inc. DS40001579E-page 147

PIC16(L)F1782/3 REGISTER 17-2: ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit (see Figure17-3) 1 = 2’s complement format. 0 = Sign-magnitude result format. bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits 111 =FRC (clock supplied from a dedicated FRC oscillator) 110 =FOSC/64 101 =FOSC/16 100 =FOSC/4 011 =FRC (clock supplied from a dedicated FRC oscillator) 010 =FOSC/32 001 =FOSC/8 000 =FOSC/2 bit 3 Unimplemented: Read as ‘0’ bit 2 ADNREF: ADC Negative Voltage Reference Configuration bit 1 = VREF- is connected to external VREF- pin(1) 0 = VREF- is connected to VSS bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits 11 = VREF+ is connected internally to FVR Buffer 1 10 = Reserved 01 = VREF+ is connected to VREF+ pin 00 = VREF+ is connected to VDD Note 1: When selecting the FVR or VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section30.0 “Electrical Specifications” for details. DS40001579E-page 148  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 17-3: ADCON2: ADC CONTROL REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TRIGSEL<3:0> CHSN<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 TRIGSEL<3:0>: ADC Auto-conversion Trigger Source Selection bits 1111 = Reserved. Auto-conversion Trigger disabled. 1110 = Reserved. Auto-conversion Trigger disabled. 1101 = Reserved. Auto-conversion Trigger disabled. 1100 = Reserved. Auto-conversion Trigger disabled. 1011 = Reserved. Auto-conversion Trigger disabled. 1010 = Reserved. Auto-conversion Trigger disabled. 1001 = PSMC2 Falling Edge Event 1000 = PSMC2 Rising Edge Event 0111 = PSMC2 Period Match Event 0110 = PSMC1 Falling Edge Event 0101 = PSMC1 Rising Edge Event 0100 = PSMC1 Period Match Event 0011 = Reserved. Auto-conversion Trigger disabled. 0010 = CCP2, Auto-conversion Trigger 0001 = CCP1, Auto-conversion Trigger 0000 = Disabled bit 3-0 CHSN<3:0>: Negative Differential Input Channel Select bits When ADON = 0, all multiplexer inputs are disconnected. 1111 = ADC Negative reference - selected by ADNREF 1110 = Reserved. No channel connected. 1101 = AN13 1100 = AN12 1011 = AN11 1010 = AN10 1001 = AN9 1000 = AN8 0111 = Reserved. No channel connected. 0110 = Reserved. No channel connected. 0101 = Reserved. No channel connected. 0100 = AN4 0011 = AN3 0010 = AN2 0001 = AN1 0000 = AN0  2011-2014 Microchip Technology Inc. DS40001579E-page 149

PIC16(L)F1782/3 REGISTER 17-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u AD<11:4> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 AD<11:4>: ADC Result Register bits Upper 8 bits of 12-bit conversion result REGISTER 17-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u AD<3:0> — — — ADSIGN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 AD<3:0>: ADC Result Register bits Lower 4 bits of 12-bit conversion result bit 3-1 Extended LSb bits: These are cleared to zero by DC conversion. bit 0 ADSIGN: ADC Result Sign bit DS40001579E-page 150  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 17-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADSIGN AD<11:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 ADSIGN: Extended AD Result Sign bit bit 3-0 AD<11:8>: ADC Result Register bits Most Significant 4 bits of 12-bit conversion result REGISTER 17-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u AD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 AD<7:0>: ADC Result Register bits Least Significant 8 bits of 12-bit conversion result  2011-2014 Microchip Technology Inc. DS40001579E-page 151

PIC16(L)F1782/3 17.4 ADC Acquisition Requirements source impedance is decreased, the acquisition time may be decreased. After the analog input channel is For the ADC to meet its specified accuracy, the charge selected (or changed), an ADC acquisition must be holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate charge to the input channel voltage level. The Analog the minimum acquisition time, Equation17-1 may be Input model is shown in Figure17-4. The source used. This equation assumes that 1/2 LSb error is used impedance (RS) and the internal sampling switch (RSS) (4,096 steps for the ADC). The 1/2 LSb error is the impedance directly affect the time required to charge maximum error allowed for the ADC to meet its the capacitor CHOLD. The sampling switch (RSS) specified resolution. impedance varies over the device voltage (VDD), refer to Figure17-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 17-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– ------n----+----1------------ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb 2 –1 –TC  ---------- RC VAPPLIED1–e  = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– ------n---+-----1------------ ;combining [1] and [2]   2  –1 Note: Where n = number of bits of the ADC. Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/8191) = –10pF1k+7k+10k ln(0.000122) = 1.62µs Therefore: TACQ = 2µs+1.62µs+50°C- 25°C0.05µs/°C = 4.87µs Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: Maximum source impedance feeding the input pin should be considered so that the pin leakage does not cause a voltage divider, thereby limiting the absolute accuracy. DS40001579E-page 152  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 17-4: ANALOG INPUT MODEL VDD Analog Sampling Input Switch VT  0.6V Rs pin RIC  1k SS Rss VA C5 PpIFN VT  0.6V I LEAKAGE(1) CHOLD = 10 pF VSS/VREF- 6V 5V RSS Legend: CHOLD = Sample/Hold Capacitance VDD4V 3V CPIN = Input Capacitance 2V I LEAKAGE = Leakage current at the pin due to various junctions 5 6 7891011 RIC = Interconnect Resistance Sampling Switch RSS = Resistance of Sampling Switch (k) SS = Sampling Switch VT = Threshold Voltage Note1: Refer to Section30.0 “Electrical Specifications”. FIGURE 17-5: ADC TRANSFER FUNCTION Full-Scale Range FFFh FFEh FFDh FFCh e od FFBh C ut p ut O C D 03h A 02h 01h 00h Analog Input Voltage (Positive input channel relative to negative 0.5 LSB 1.5 LSB input channel) Zero-Scale VREF- Transition Full-Scale Transition VREF+  2011-2014 Microchip Technology Inc. DS40001579E-page 153

PIC16(L)F1782/3 TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 ADRMD CHS<4:0> GO/DONE ADON 147 ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 148 ADCON2 TRIGSEL<3:0> CHSN<3:0> 149 ADRESH A/D Result Register High 150, 151 ADRESL A/D Result Register Low 150, 151 ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 115 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 121 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 120 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 137 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for the ADC module. DS40001579E-page 154  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 18.0 OPERATIONAL AMPLIFIER (OPA) MODULES The Operational Amplifier (OPA) is a standard three-terminal device requiring external feedback to operate. The OPA module has the following features: • External connections to I/O ports • Low leakage inputs • Factory Calibrated Input Offset Voltage FIGURE 18-1: OPAx MODULE BLOCK DIAGRAM OPAXEN OPAxIN+ 0x OPAXSP(1) DAC_output 10 OPA OPAXOUT FVR Buffer 2 11 OPAxIN- OPAxNCH<1:0> Note 1: The OPAxSP bit must be set to ‘1’. Low Power mode is not supported.  2011-2014 Microchip Technology Inc. DS40001579E-page 155

PIC16(L)F1782/3 18.1 Effects of Reset 18.3 OPAxCON Control Register A device Reset forces all registers to their Reset state. The OPAxCON register, shown in Register18-1, This disables the OPA module. controls the OPA module. The OPA module is enabled by setting the OPAxEN bit 18.2 OPA Module Performance of the OPAxCON register. When enabled, the OPA Common AC and DC performance specifications for forces the output driver of OPAxOUT pin into tri-state to the OPA module: prevent contention between the driver and the OPA output. • Common Mode Voltage Range • Leakage Current Note: When the OPA module is enabled, the OPAxOUT pin is driven by the op amp out- • Input Offset Voltage put, not by the PORT digital driver. Refer • Open Loop Gain to the Electrical specifications for the op • Gain Bandwidth Product amp output drive capability. Common mode voltage range is the specified voltage range for the OPA+ and OPA- inputs, for which the OPA module will perform to within its specifications. The OPA module is designed to operate with input voltages between VSS and VDD. Behavior for Common mode voltages greater than VDD, or below VSS, are not guar- anteed. Leakage current is a measure of the small source or sink currents on the OPA+ and OPA- inputs. To mini- mize the effect of leakage currents, the effective imped- ances connected to the OPA+ and OPA- inputs should be kept as small as possible and equal. Input offset voltage is a measure of the voltage differ- ence between the OPA+ and OPA- inputs in a closed loop circuit with the OPA in its linear region. The offset voltage will appear as a DC offset in the output equal to the input offset voltage, multiplied by the gain of the cir- cuit. The input offset voltage is also affected by the Common mode voltage. The OPA is factory calibrated to minimize the input offset voltage of the module. Open loop gain is the ratio of the output voltage to the differential input voltage, (OPA+) - (OPA-). The gain is greatest at DC and falls off with frequency. Gain Bandwidth Product or GBWP is the frequency at which the open loop gain falls off to 0 dB. DS40001579E-page 156  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 18.4 Register Definitions: Op Amp Control REGISTER 18-1: OPAxCON: OPERATIONAL AMPLIFIERS (OPAx) CONTROL REGISTERS R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 OPAxEN OPAxSP — — — — OPAxCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 OPAxEN: Op Amp Enable bit 1 = Op amp is enabled 0 = Op amp is disabled and consumes no active power bit 6 OPAxSP: Op Amp Speed/Power Select bit 1 = Comparator operates in high GBWP mode 0 = Reserved. Do not use. bit 5-2 Unimplemented: Read as ‘0’ bit 1-0 OPAxCH<1:0>: Non-inverting Channel Selection bits 11 = Non-inverting input connects to FVR Buffer 2 output 10 = Non-inverting input connects to DAC_output 0x = Non-inverting input connects to OPAxIN+ pin TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH OP AMPS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 115 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 121 DACCON0 DACEN — DACOE1 DACOE2 DACPSS<1:0> — DACNSS 161 DACCON1 DACR<7:0> 161 OPA1CON OPA1EN OPA1SP — — — — OPA1PCH<1:0> 157 OPA2CON OPA2EN OPA2SP — — — — OPA2PCH<1:0> 157 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 120 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by op amps. Note 1: PIC16(L)F1783 only  2011-2014 Microchip Technology Inc. DS40001579E-page 157

PIC16(L)F1782/3 19.0 DIGITAL-TO-ANALOG The Digital-to-Analog Converter (DAC) is enabled by CONVERTER (DAC) MODULE setting the DACEN bit of the DACCON0 register. The Digital-to-Analog Converter supplies a variable 19.1 Output Voltage Selection voltage reference, ratiometric with the input source, with 256 selectable output levels. The DAC has 256 voltage level ranges. The 256 levels are set with the DACR<7:0> bits of the DACCON1 The input of the DAC can be connected to: register. • External VREF pins The DAC output voltage is determined by Equation19-1: • VDD supply voltage • FVR (Fixed Voltage Reference) The output of the DAC can be configured to supply a reference voltage to the following: • Comparator positive input • Op amp positive input • ADC input channel • DACOUT1 pin • DACOUT2 pin EQUATION 19-1: DAC OUTPUT VOLTAGE IF DACxEN = 1  DACxR7:0 VOUT = VSOURCE+–VSOURCE---------------------------------- +VSOURCE-  8  2 VSOURCE+ = VDD, VREF, or FVR BUFFER 2 VSOURCE- = VSS 19.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Section30.0 “Electrical Specifications”. 19.3 DAC Voltage Reference Output The DAC voltage can be output to the DACOUT1 and DACOUT2 pins by setting the respective DACOE1 and DACOE2 pins of the DACCON0 register. Selecting the DAC reference voltage for output on either DACOUTX pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACOUTX pin when it has been configured for DAC reference voltage output will always return a ‘0’. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to either DACOUTx pin. Figure19-2 shows an example buffering technique. DS40001579E-page 158  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 19-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSOURCE+ VDD DACxR<7:0> 8 VREF+ R R DACxPSS<1:0> 2 R DACxEN R R X 256 MU DAC_Output (To Comparator and Steps 1 ADC Modules) o- 2-t R 3 R DACXOUT1 R DACXOE1 DACxNSS DACXOUT2 VREF- VSOURCE- DACXOE2 VSS FIGURE 19-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC R Module + Voltage DACXOUTX – Buffered DAC Output Reference Output Impedance  2011-2014 Microchip Technology Inc. DS40001579E-page 159

PIC16(L)F1782/3 19.4 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 19.5 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<7:0> range select bits are cleared. DS40001579E-page 160  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 19.6 Register Definitions: DAC Control REGISTER 19-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 DACEN — DACOE1 DACOE2 DACPSS<1:0> — DACNSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 DACOE1: DAC Voltage Output 1 Enable bit 1 = DAC voltage level is also an output on the DACOUT1 pin 0 = DAC voltage level is disconnected from the DACOUT1 pin bit 4 DACOE2: DAC Voltage Output 2 Enable bit 1 = DAC voltage level is also an output on the DACOUT2 pin 0 = DAC voltage level is disconnected from the DACOUT2 pin bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits 11 = Reserved, do not use 10 = FVR Buffer2 output 01 = VREF+ pin 00 = VDD bit 1 Unimplemented: Read as ‘0’ bit 0 DACNSS: DAC Negative Source Select bits 1 = VREF- pin 0 = VSS REGISTER 19-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DACR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 DACR<7:0>: DAC Voltage Output Select bits  2011-2014 Microchip Technology Inc. DS40001579E-page 161

PIC16(L)F1782/3 TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 137 DACCON0 DACEN — DACOE1 DACOE2 DACPSS<1:0> — DACNSS 161 DACCON1 DACR<7:0> 161 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module. DS40001579E-page 162  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 20.0 COMPARATOR MODULE FIGURE 20-1: SINGLE COMPARATOR Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and VIN+ + providing a digital indication of their relative magnitudes. Output Comparators are very useful mixed signal building VIN- – blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: • Independent comparator control VIN- • Programmable input selection VIN+ • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change Output • Wake-up from Sleep • Programmable Speed/Power optimization • PWM shutdown Note: The black areas of the output of the • Programmable and fixed voltage reference comparator represents the uncertainty 20.1 Comparator Overview due to input offsets and response time. A single comparator is shown in Figure20-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. The comparators available for this device are located in Table20-1. TABLE 20-1: COMPARATOR AVAILABILITY PER DEVICE Device C1 C2 C3 PIC16(L)F1782 ● ● ● PIC16(L)F1783 ● ● ●  2011-2014 Microchip Technology Inc. DS40001579E-page 163

PIC16(L)F1782/3 FIGURE 20-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<2:0> CxON(1) 3 Interrupt CxINTP det CXIN0- 0 Set CxIF CXIN1- 1 CXIN2- 2MUX Interrupt CxINTN (2) det CXIN3- 3 CXPOL Reserved 4 CxVN - Reserved 5 Cx 0 D Q aton Cd MCMXC2OCNO0N (1C (XMOCUXTO)UT) Reserved 6 + ZLF 1 CxVP Q1 EN 7 CxHYS AGND CxZLF CxSP async_CxOUT CXSYNC CXOE TRIS bit 0 CXOUT D Q 1 CXIN0+ 0 From Timer1 tmr1_clk sync_CxOUT CXIN1+ 1MUX To Timer1 and PSMC Logic (2) Reserved 2 Reserved 3 Reserved 4 DAC_Output 5 FVR Buffer2 6 7 AGND CxON CXPCH<2:0> 3 Note 1: When CxON = 0, the comparator will produce a ‘0’ at the output. 2: When CxON = 0, all multiplexer inputs are disconnected. DS40001579E-page 164  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 20.2 Comparator Control 20.2.3 COMPARATOR OUTPUT POLARITY Each comparator has two control registers: CMxCON0 Inverting the output of the comparator is functionally and CMxCON1. equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by The CMxCON0 register (see Register20-1) contains setting the CxPOL bit of the CMxCON0 register. Control and Status bits for the following: Clearing the CxPOL bit results in a non-inverted output. • Enable Table20-2 shows the output state versus input • Output selection conditions, including polarity control. • Output polarity TABLE 20-2: COMPARATOR OUTPUT • Speed/Power selection STATE VS. INPUT • Hysteresis enable CONDITIONS • Output synchronization Input Condition CxPOL CxOUT The CMxCON1 register (see Register20-2) contains CxVN > CxVP 0 0 Control bits for the following: CxVN < CxVP 0 1 • Interrupt enable CxVN > CxVP 1 1 • Interrupt edge polarity CxVN < CxVP 1 0 • Positive input channel selection • Negative input channel selection 20.2.4 COMPARATOR SPEED/POWER SELECTION 20.2.1 COMPARATOR ENABLE The trade-off between speed or power can be Setting the CxON bit of the CMxCON0 register enables optimized during program execution with the CxSP the comparator for operation. Clearing the CxON bit control bit. The default state for this bit is ‘1’ which disables the comparator resulting in minimum current selects the normal speed mode. Device power consumption. consumption can be optimized at the cost of slower 20.2.2 COMPARATOR OUTPUT comparator propagation delay by clearing the CxSP bit to ‘0’. SELECTION The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set Note1: The CxOE bit of the CMxCON0 register overrides the PORT data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched.  2011-2014 Microchip Technology Inc. DS40001579E-page 165

PIC16(L)F1782/3 20.3 Comparator Hysteresis 20.5 Comparator Interrupt A selectable amount of separation voltage can be An interrupt can be generated upon a change in the added to the input pins of each comparator to provide a output value of the comparator for each comparator, a hysteresis function to the overall operation. Hysteresis rising edge detector and a falling edge detector are is enabled by setting the CxHYS bit of the CMxCON0 present. register. When either edge detector is triggered and its associ- See Section30.0 “Electrical Specifications” for ated enable bit is set (CxINTP and/or CxINTN bits of more information. the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. 20.4 Timer1 Gate Operation To enable the interrupt, you must set the following bits: The output resulting from a comparator operation can • CxON, CxPOL and CxSP bits of the CMxCON0 be used as a source for gate control of Timer1. See register Section22.6 “Timer1 Gate” for more information. • CxIE bit of the PIE2 register This feature is useful for timing the duration or interval • CxINTP bit of the CMxCON1 register (for a rising of an analog event. edge detection) It is recommended that the comparator output be • CxINTN bit of the CMxCON1 register (for a falling synchronized to Timer1. This ensures that Timer1 does edge detection) not increment while a change in the comparator is • PEIE and GIE bits of the INTCON register occurring. The associated interrupt flag bit, CxIF bit of the PIR2 20.4.1 COMPARATOR OUTPUT register, must be cleared in software. If another edge is SYNCHRONIZATION detected while this flag is being cleared, the flag will still be set at the end of the sequence. The output from a comparator can be synchronized with Timer1 by setting the CxSYNC bit of the CMx- Note: Although a comparator is disabled, an CON0 register. interrupt can be generated by changing the output polarity with the CxPOL bit of Once enabled, the comparator output is latched on the the CMxCON0 register, or by switching falling edge of the Timer1 source clock. If a prescaler is the comparator on or off with the CxON bit used with Timer1, the comparator output is latched after of the CMxCON0 register. the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the 20.6 Comparator Positive Input Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Selection Block Diagram (Figure20-2) and the Timer1 Block Configuring the CxPCH<2:0> bits of the CMxCON1 Diagram (Figure22-1) for more information. register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: • CxIN+ analog pin • DAC output • FVR (Fixed Voltage Reference) • VSS (Ground) See Section15.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section19.0 “Digital-to-Analog Converter (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. DS40001579E-page 166  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 20.7 Comparator Negative Input Therefore, both of these times must be considered when Selection determining the total response time to a comparator input change. See the Comparator and Voltage The CxNCH<2:0> bits of the CMxCON0 register direct Reference Specifications in Section30.0 “Electrical an analog input pin or analog ground to the inverting Specifications” for more details. input of the comparator: • CxIN- pin 20.9 Zero Latency Filter • Analog Ground In high-speed operation, and under proper circuit Some inverting input selections share a pin with the conditions, it is possible for the comparator output to operational amplifier output function. Enabling both oscillate. This oscillation can have adverse effects on functions at the same time will direct the operational the hardware and software relying on this signal. amplifier output to the comparator inverting input. Therefore, a digital filter has been added to the comparator output to suppress the comparator output oscillation. Once the comparator output changes, the output is prevented from reversing the change for a Note: To use CxINy+ and CxINy- pins as analog nominal time of 20ns. This allows the comparator input, the appropriate bits must be set in output to stabilize without affecting other dependent the ANSEL register and the correspond- devices. Refer to Figure20-3. ing TRIS bits must also be set to disable the output drivers. 20.8 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. FIGURE 20-3: COMPARATOR ZERO LATENCY FILTER OPERATION CxOUT From Comparator CxOUT From ZLF TZLF Output waiting for TZLF to expire before an output change is allowed TZLF has expired so output change of ZLF is immediate based on comparator output change  2011-2014 Microchip Technology Inc. DS40001579E-page 167

PIC16(L)F1782/3 20.10 Analog Input Connection 20.10.1 ALTERNATE PIN LOCATIONS Considerations This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function A simplified circuit for an analog input is shown in register APFCON. To determine which pins can be Figure20-4. Since the analog input pins share their moved and what their default locations are upon a connection with a digital input, they have reverse Reset, see Section13.1 “Alternate Pin Function” for biased ESD protection diodes to VDD and VSS. The more information. analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. FIGURE 20-4: ANALOG INPUT MODEL VDD Analog Input Rs < 10K pin VT  0.6V RIC To Comparator VA C5 PpIFN VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage Note1: See Section30.0 “Electrical Specifications” DS40001579E-page 168  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 20.11 Register Definitions: Comparator Control REGISTER 20-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL CxZLF CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and consumes no active power bit 6 CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 CxZLF: Comparator Zero Latency Filter Enable bit 1 = Comparator output is filtered 0 = Comparator output is unfiltered bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous.  2011-2014 Microchip Technology Inc. DS40001579E-page 169

PIC16(L)F1782/3 REGISTER 20-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CxINTP CxINTN CxPCH<2:0> CxNCH<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-3 CxPCH<2:0>: Comparator Positive Input Channel Select bits 111 = CxVP connects to AGND 110 = CxVP connects to FVR Buffer 2 101 = CxVP connects to DAC_output 100 = Reserved, input floating 011 = Reserved, input floating 010 = Reserved, input floating 001 = CxVP connects to CxIN1+ pin 000 = CxVP connects to CxIN0+ pin bit 2-0 CxNCH<2:0>: Comparator Negative Input Channel Select bits 111 = CxVN connects to AGND 110 = CxVN unconnected, input floating 101 = Reserved, input floating 100 = Reserved, input floating 011 = CxVN connects to CxIN3- pin 010 = CxVN connects to CxIN2- pin 001 = CxVN connects to CxIN1- pin 000 = CxVN connects to CxIN0- pin DS40001579E-page 170  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 20-3: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0 R-0/0 — — — — — MC3OUT MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 MC3OUT: Mirror Copy of C3OUT bit bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 115 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 121 CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 169 CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 169 CM1CON1 C1NTP C1INTN C1PCH<2:0> C1NCH<2:0> 170 CM2CON1 C2NTP C2INTN C2PCH<2:0> C2NCH<2:0> 170 CM3CON0 C3ON C3OUT C3OE C3POL C3ZLF C3SP C3HYS C3SYNC 169 CM3CON1 C3INTP C3INTN C3PCH<2:0> C3NCH<2:0> 170 CMOUT — — — — — MC3OUT MC2OUT MC1OUT 171 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 137 DACCON0 DACEN — DACOE1 DACOE2 DACPSS<1:0> — DACNSS 161 DACCON1 DACR<7:0> 161 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE2 OSEIE C2IE C1IE EEIE BCL1IE — C3IE CCP2IE 81 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — C3IF CCP2IF 84 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 115 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 121 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 Note 1: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.  2011-2014 Microchip Technology Inc. DS40001579E-page 171

PIC16(L)F1782/3 21.0 TIMER0 MODULE 21.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment The Timer0 module is an 8-bit timer/counter with the on every rising or falling edge of the T0CKI pin. following features: 8-Bit Counter mode using the T0CKI pin is selected by • 8-bit timer/counter register (TMR0) setting the TMR0CS bit in the OPTION_REG register to • 8-bit prescaler (independent of Watchdog Timer) ‘1’. • Programmable internal or external clock source The rising or falling transition of the incrementing edge • Programmable external clock edge selection for either input source is determined by the TMR0SE bit • Interrupt on overflow in the OPTION_REG register. • TMR0 can be used to gate Timer1 Figure21-1 is a block diagram of the Timer0 module. 21.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 21.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 21-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 Sync 1 2 TCY TMR0 0 TMR0SE TMR0CS 8-bit Set Flag bit TMR0IF on Overflow Prescaler PSA Overflow to Timer1 8 PS<2:0> DS40001579E-page 172  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 21.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 21.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 21.1.5 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section30.0 “Electrical Specifications”. 21.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode.  2011-2014 Microchip Technology Inc. DS40001579E-page 173

PIC16(L)F1782/3 21.2 Register Definitions: Option Register REGISTER 21-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-Up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate 000 1 : 2 001 1 : 4 010 1 : 8 011 1 : 16 100 1 : 32 101 1 : 64 110 1 : 128 111 1 : 256 TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 174 TMR0 Timer0 Module Register 172* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. DS40001579E-page 174  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 22.0 TIMER1 MODULE WITH GATE • Gate Toggle mode CONTROL • Gate Single-pulse mode • Gate Value Status The Timer1 module is a 16-bit timer/counter with the • Gate Event Interrupt following features: Figure22-1 is a block diagram of the Timer1 module. • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 2-bit prescaler • Dedicated 32 kHz oscillator circuit • Optionally synchronized comparator out • Multiple Timer1 gate (count enable) sources • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Auto-conversion Trigger (with CCP) • Selectable Gate Source Polarity FIGURE 22-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 T1GSPM FrOomve Trfilmower0 01 t1g_in 0 0 T1GVAL D Q Data Bus sync_C1OUT 10 SAicnqg.l eC-oPnutlrsoel 1 Q1 EN T1GRCDON D Q 1 sync_C2OUT 11 CK Q T1GGO/DONE Interrupt Set TMR1ON R det TMR1GIF T1GPOL T1GTM TMR1GE Set flag bit TMR1ON TMR1IF on To Comparator Module Overflow TMR1(2) EN Synchronized To ADC Auto-Conversion 0 clock input TMR1H TMR1L T1CLK Q D 1 TMR1CS<1:0> T1SYNC T1OSO OUT T1OSC Reserved 11 Prescaler Synchronize(3) 1 1, 2, 4, 8 det T1OSI EN 10 2 0 FOSC T1CKPS<1:0> Internal 01 T1OSCEN Clock IFnOteSrCn/a2l Sleep input FOSC/4 Clock Internal 00 (1) Clock T1CKI To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2011-2014 Microchip Technology Inc. DS40001579E-page 175

PIC16(L)F1782/3 22.1 Timer1 Operation 22.2 Clock Source Selection The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> and T1OSCEN bits of the T1CON which is accessed through the TMR1H:TMR1L register register are used to select the clock source for Timer1. pair. Writes to TMR1H or TMR1L directly update the Table22-2 displays the clock source selections. counter. 22.2.1 INTERNAL CLOCK SOURCE When used with an internal clock source, the module is a timer and increments on every instruction cycle. When the internal clock source is selected, the When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples can be used as either a timer or counter and of FOSC as determined by the Timer1 prescaler. increments on every selected edge of the external When the FOSC internal clock source is selected, the source. Timer1 register value will increment by four counts every Timer1 is enabled by configuring the TMR1ON and instruction clock cycle. Due to this condition, a 2LSB TMR1GE bits in the T1CON and T1GCON registers, error in resolution will occur when reading the Timer1 respectively. Table22-1 displays the Timer1 enable value. To utilize the full resolution of Timer1, an selections. asynchronous input signal must be used to gate the Timer1 clock input. TABLE 22-1: TIMER1 ENABLE The following asynchronous sources may be used: SELECTIONS • Asynchronous event on the T1G pin to Timer1 gate Timer1 TMR1ON TMR1GE • C1 or C2 comparator input to Timer1 gate Operation 0 0 Off 22.2.2 EXTERNAL CLOCK SOURCE 0 1 Off When the external clock source is selected, the Timer1 1 0 Always On module may work as a timer or a counter. 1 1 Count Enabled When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI, which can be synchronized to the microcontroller system clock or can run asynchronously. When used as a timer with a clock oscillator, an external 32.768kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • Timer1 enabled after POR • Write to TMR1H or TMR1L • Timer1 is disabled • Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. TABLE 22-2: CLOCK SOURCE SELECTIONS TMR1CS<1:0> T1OSCEN Clock Source 11 x Reserved 10 1 Timer1 Oscillator 10 0 External Clocking on T1CKI Pin 01 x System Clock (FOSC) 00 x Instruction Clock (FOSC/4) DS40001579E-page 176  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 22.3 Timer1 Prescaler 22.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER Timer1 has four prescaler options allowing 1, 2, 4 or 8 MODE divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The Reading TMR1H or TMR1L while the timer is running prescale counter is not directly readable or writable; from an external asynchronous clock will ensure a valid however, the prescaler counter is cleared upon a write to read (taken care of in hardware). However, the user TMR1H or TMR1L. should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the 22.4 Timer1 Oscillator timer may overflow between the reads. For writes, it is recommended that the user simply stop A dedicated low-power 32.768kHz oscillator circuit is the timer and write the desired values. A write built-in between pins T1OSI (input) and T1OSO contention may occur by writing to the timer registers, (amplifier output). This internal circuit is to be used in while the register is incrementing. This may produce an conjunction with an external 32.768kHz crystal. unpredictable value in the TMR1H:TMR1L register pair. The oscillator circuit is enabled by setting the T1OS- CEN bit of the T1CON register. The oscillator will con- 22.6 Timer1 Gate tinue to run during Sleep. Timer1 can be configured to count freely or the count Note: The oscillator requires a start-up and can be enabled and disabled using Timer1 gate stabilization time before use. Thus, circuitry. This is also referred to as Timer1 Gate Enable. T1OSCEN should be set and a suitable delay observed prior to using Timer1. A Timer1 gate can also be driven by multiple selectable suitable delay similar to the OST delay sources. can be implemented in software by 22.6.1 TIMER1 GATE ENABLE clearing the TMR1IF bit then presetting the TMR1H:TMR1L register pair to The Timer1 Gate Enable mode is enabled by setting FC00h. The TMR1IF flag will be set when the TMR1GE bit of the T1GCON register. The polarity 1024 clock cycles have elapsed, thereby of the Timer1 Gate Enable mode is configured using indicating that the oscillator is running and the T1GPOL bit of the T1GCON register. reasonably stable. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock 22.5 Timer1 Operation in source. When Timer1 Gate Enable mode is disabled, Asynchronous Counter Mode no incrementing will occur and Timer1 will hold the current count. See Figure22-3 for timing details. If the control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer TABLE 22-3: TIMER1 GATE ENABLE increments asynchronously to the internal phase clocks. If the external clock source is selected then the SELECTIONS timer will continue to run during Sleep and can T1CLK T1GPOL T1G Timer1 Operation generate an interrupt on overflow, which will wake-up the processor. However, special precautions in  0 0 Counts software are needed to read/write the timer (see  0 1 Holds Count Section22.5.1 “Reading and Writing Timer1 in  1 0 Holds Count Asynchronous Counter Mode”).  1 1 Counts Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.  2011-2014 Microchip Technology Inc. DS40001579E-page 177

PIC16(L)F1782/3 22.6.2 TIMER1 GATE SOURCE Timer1 Gate Toggle mode is enabled by setting the SELECTION T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This Timer1 gate source selections are shown in Table22-4. is necessary in order to control which edge is Source selection is controlled by the T1GSS bits of the measured. T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the Note: Enabling Toggle mode at the same time T1GPOL bit of the T1GCON register. as changing the gate polarity may result in indeterminate operation. TABLE 22-4: TIMER1 GATE SOURCES 22.6.4 TIMER1 GATE SINGLE-PULSE T1GSS Timer1 Gate Source MODE 00 Timer1 Gate Pin When Timer1 Gate Single-Pulse mode is enabled, it is 01 Overflow of Timer0 possible to capture a single-pulse gate event. Timer1 (TMR0 increments from FFh to 00h) Gate Single-Pulse mode is enabled by first setting the 10 Comparator 1 Output sync_C1OUT T1GSPM bit in the T1GCON register. Next, the (optionally Timer1 synchronized output) T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next 11 Comparator 2 Output sync_C2OUT incrementing edge. On the next trailing edge of the (optionally Timer1 synchronized output) pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to 22.6.2.1 T1G Pin Gate Operation increment Timer1 until the T1GGO/DONE bit is once The T1G pin is one source for Timer1 gate control. It again set in software. See Figure22-5 for timing details. can be used to supply an external source to the Timer1 If the Single-Pulse Gate mode is disabled by clearing the gate circuitry. T1GSPM bit in the T1GCON register, the T1GGO/DONE 22.6.2.2 Timer0 Overflow Gate Operation bit should also be cleared. Enabling the Toggle mode and the Single-Pulse mode When Timer0 increments from FFh to 00h, a simultaneously will permit both sections to work low-to-high pulse will automatically be generated and together. This allows the cycle times on the Timer1 gate internally supplied to the Timer1 gate circuitry. source to be measured. See Figure22-6 for timing 22.6.2.3 Comparator C1 Gate Operation details. The output resulting from a Comparator 1 operation can 22.6.5 TIMER1 GATE VALUE be selected as a source for Timer1 gate control. The When Timer1 Gate Value Status is utilized, it is possible Comparator 1 output (sync_C1OUT) can be to read the most current level of the gate control value. synchronized to the Timer1 clock or left asynchronous. The value is accessible by reading the T1GVAL bit in For more information see Section20.4.1 “Comparator the T1GCON register. The T1GVAL bit is valid even Output Synchronization”. when the Timer1 gate is not enabled (TMR1GE bit is 22.6.2.4 Comparator C2 Gate Operation cleared). The output resulting from a Comparator 2 operation 22.6.6 TIMER1 GATE EVENT INTERRUPT can be selected as a source for Timer1 gate control. When Timer1 Gate Event Interrupt is enabled, it is The Comparator 2 output (sync_C2OUT) can be possible to generate an interrupt upon the completion synchronized to the Timer1 clock or left asynchronous. of a gate event. When the falling edge of T1GVAL For more information see Section20.4.1 “Comparator occurs, the TMR1GIF flag bit in the PIR1 register will be Output Synchronization”. set. If the TMR1GIE bit in the PIE1 register is set, then 22.6.3 TIMER1 GATE TOGGLE MODE an interrupt will be recognized. When Timer1 Gate Toggle mode is enabled, it is The TMR1GIF flag bit operates even when the Timer1 possible to measure the full-cycle length of a Timer1 gate is not enabled (TMR1GE bit is cleared). gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure22-4 for timing details. DS40001579E-page 178  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 22.7 Timer1 Interrupt 22.9 CCP Capture/Compare Time Base The Timer1 register pair (TMR1H:TMR1L) increments The CCP modules use the TMR1H:TMR1L register to FFFFh and rolls over to 0000h. When Timer1 rolls pair as the time base when operating in Capture or over, the Timer1 interrupt flag bit of the PIR1 register is Compare mode. set. To enable the interrupt on rollover, you must set In Capture mode, the value in the TMR1H:TMR1L these bits: register pair is copied into the CCPR1H:CCPR1L • TMR1ON bit of the T1CON register register pair on a configured event. • TMR1IE bit of the PIE1 register In Compare mode, an event is triggered when the value • PEIE bit of the INTCON register CCPR1H:CCPR1L register pair matches the value in • GIE bit of the INTCON register the TMR1H:TMR1L register pair. This event can be a Auto-conversion Trigger. The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. For more information, see Section25.0 “Capture/Compare/PWM Modules”. Note: The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before 22.10 CCP Auto-Conversion Trigger enabling interrupts. When any of the CCP’s are configured to trigger a 22.8 Timer1 Operation During Sleep auto-conversion, the trigger will clear the TMR1H:TMR1L register pair. This auto-conversion Timer1 can only operate during Sleep when setup in does not cause a Timer1 interrupt. The CCP module Asynchronous Counter mode. In this mode, an external may still be configured to generate a CCP interrupt. crystal or clock source can be used to increment the In this mode of operation, the CCPR1H:CCPR1L counter. To set up the timer to wake the device: register pair becomes the period register for Timer1. • TMR1ON bit of the T1CON register must be set Timer1 should be synchronized and FOSC/4 should be • TMR1IE bit of the PIE1 register must be set selected as the clock source in order to utilize the • PEIE bit of the INTCON register must be set Auto-conversion Trigger. Asynchronous operation of • T1SYNC bit of the T1CON register must be set Timer1 can cause a Auto-conversion Trigger to be • TMR1CS bits of the T1CON register must be missed. configured In the event that a write to TMR1H or TMR1L coincides • T1OSCEN bit of the T1CON register must be with a Auto-conversion Trigger from the CCP, the write configured will take precedence. The device will wake-up on an overflow and execute For more information, see Section25.2.4 the next instructions. If the GIE bit of the INTCON “Auto-Conversion Trigger”. register is set, the device will call the Interrupt Service Routine. Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 22-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2011-2014 Microchip Technology Inc. DS40001579E-page 179

PIC16(L)F1782/3 FIGURE 22-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 FIGURE 22-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 DS40001579E-page 180  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 22-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 Cleared by TMR1GIF Cleared by software Set by hardware on software falling edge of T1GVAL  2011-2014 Microchip Technology Inc. DS40001579E-page 181

PIC16(L)F1782/3 FIGURE 22-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 Set by hardware on Cleared by TMR1GIF Cleared by software falling edge of T1GVAL software DS40001579E-page 182  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 22.11 Register Definitions: Timer1 Control T REGISTER 22-1: T1CON: TIMER1 CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 = Reserved, do not use. 10 = Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled bit 2 T1SYNC: Timer1 Synchronization Control bit 1 = Do not synchronize asynchronous clock input 0 = Synchronize asynchronous clock input with system clock (FOSC) bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop  2011-2014 Microchip Technology Inc. DS40001579E-page 183

PIC16(L)F1782/3 REGISTER 22-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> DONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 11 = Comparator 2 optionally synchronized output (sync_C2OUT) 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 01 = Timer0 overflow output 00 = Timer1 gate pin DS40001579E-page 184  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 22-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 121 CCP1CON — — DC1B<1:0> CCP1M<3:0> 255 CCP2CON — — DC2B<1:0> CCP2M<3:0> 255 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 175* TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 175* TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 120 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 183 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 184 DONE Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information.  2011-2014 Microchip Technology Inc. DS40001579E-page 185

PIC16(L)F1782/3 23.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2 • Optional use as the shift clock for the MSSP module See Figure23-1 for a block diagram of Timer2. FIGURE 23-1: TIMER2 BLOCK DIAGRAM Prescaler Reset FOSC/4 TMR2 TMR2 Output 1:1, 1:4, 1:16, 1:64 2 Comparator Postscaler Sets Flag bit TMR2IF EQ 1:1 to 1:16 T2CKPS<1:0> PR2 4 T2OUTPS<3:0> DS40001579E-page 186  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 23.1 Timer2 Operation 23.3 Timer2 Output The clock input to the Timer2 modules is the system The unscaled output of TMR2 is available primarily to instruction clock (FOSC/4). the CCP modules, where it is used as a time base for operations in PWM mode. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. Timer2 can be optionally used as the shift clock source These options are selected by the prescaler control bits, for the MSSP module operating in SPI mode. T2CKPS<1:0> of the T2CON register. The value of Additional information is provided in Section26.0 TMR2 is compared to that of the Period register, PR2, on “Master Synchronous Serial Port (MSSP) Module” each clock cycle. When the two values match, the comparator generates a match signal as the timer 23.4 Timer2 Operation During Sleep output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output The Timer2 timers cannot be operated while the counter/postscaler (see Section23.2 “Timer2 processor is in Sleep mode. The contents of the TMR2 Interrupt”). and PR2 registers will remain unchanged while the processor is in Sleep mode. The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • a write to the TMR2 register • a write to the T2CON register • Power-on Reset (POR) • Brown-out Reset (BOR) • MCLR Reset • Watchdog Timer (WDT) Reset • Stack Overflow Reset • Stack Underflow Reset • RESET Instruction Note: TMR2 is not cleared when T2CON is written. 23.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE, of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register.  2011-2014 Microchip Technology Inc. DS40001579E-page 187

PIC16(L)F1782/3 23.5 Register Definitions: Timer2 Control REGISTER 23-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits 1111 =1:16 Postscaler 1110 =1:15 Postscaler 1101 =1:14 Postscaler 1100 =1:13 Postscaler 1011 =1:12 Postscaler 1010 =1:11 Postscaler 1001 =1:10 Postscaler 1000 =1:9 Postscaler 0111 =1:8 Postscaler 0110 =1:7 Postscaler 0101 =1:6 Postscaler 0100 =1:5 Postscaler 0011 =1:4 Postscaler 0010 =1:3 Postscaler 0001 =1:2 Postscaler 0000 =1:1 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 11 =Prescaler is 64 10 =Prescaler is 16 01 =Prescaler is 4 00 =Prescaler is 1 DS40001579E-page 188  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCP2CON — — DC2B<1:0> CCP2M<3:0> 255 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 PR2 Timer2 Module Period Register 186* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 188 TMR2 Holding Register for the 8-bit TMR2 Register 186* Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information.  2011-2014 Microchip Technology Inc. DS40001579E-page 189

PIC16(L)F1782/3 24.0 PROGRAMMABLE SWITCH Modes of operation include: MODE CONTROL (PSMC) • Single-phase • Complementary Single-phase The Programmable Switch Mode Controller (PSMC) is • Push-Pull a high-performance Pulse Width Modulator (PWM) that can be configured to operate in one of several modes • Push-Pull 4-Bridge to support single or multiple phase applications. • Complementary Push-Pull 4-Bridge A simplified block diagram indicating the relationship • Pulse Skipping between inputs, outputs, and controls is shown in • Variable Frequency Fixed Duty Cycle Figure24-1. • Complementary Variable Frequency Fixed Duty This section begins with the fundamental aspects of the Cycle PSMC operation. A more detailed description of opera- • ECCP Compatible modes tion for each mode is located later in Section24.3 - Full-Bridge “Modes of Operation” - Full-Bridge Reverse • 3-Phase 6-Step PWM DS40001579E-page 190  2011-2014 Microchip Technology Inc.

D FIGURE 24-1: PSMC SIMPLIFIED BLOCK DIAGRAM P S 4 0 I 00 PXCPRE<1:0> C 1 PXCSRC<1:0> 5 7 1 9E PSMCXCLK psmc_clk 1,2, 6 -page 64F MOHSCZ 4, 8 PSMCCLXRTMR (L 191 sync_in ) F FFA PSMCXPR = PeriodEvent sync_out PSMCXPOL 178 2 PSMCXOEN / PSMCXPRS 3 PSMCXPH = ngnt PSMCXA PSMCXPHS RisiEve LatchSQ dulation e Control ut Control PPPSSSMMMCCCXXXBCD o d p PSMCXDC = ngnt M Mo Out PSMCXE allive R PSMCXF FE PSMCXDCS PXMODE PSMCXSTR Shutdown  2 0 1 1 Blanking PSMCXREBS -20 PSMCXFEBS PSMCXASDS 1 4 M sync_C1OUT ic sync_C2OUT ro sync_C3OUT c hip PSMCXIN T CCP1 e c CCP2 h n o PSMCXMDL lo g y In c .

PIC16(L)F1782/3 24.1 Fundamental Operation The basic waveform generated from these events is shown in Figure24-2. PSMC operation is based on the sequence of three events: • Period Event – Determines the frequency of the active signal. • Rising Edge Event – Determines start of the active pulse. This is also referred to as the phase. • Falling Edge Event – Determines the end of the active pulse. This is also referred to as the duty cycle. FIGURE 24-2: BASIC PWM WAVEFORM GENERATION PWM Cycle Number 1 2 3 Inputs Period Event Rising Edge Event Falling Edge Event Outputs PWM output Each of the three types of events is triggered by a user PSMC operation can be quickly terminated without selectable combination of synchronous timed and software intervention by the auto-shutdown control. asynchronous external inputs. Auto-shutdown can be triggered by any combination of the following: Asynchronous event inputs may come directly from an input pin or through the comparators. • PSMCxIN pin Synchronous timed events are determined from the • sync_C1OUT PSMCxTMR counter, which is derived from internal • sync_C2OUT clock sources. See Section24.2.5 “PSMC Time Base • sync_C3OUT Clock Sources” for more detail. The active pulse stream can be further modulated by one of several internal or external sources: • Register control bit • Comparator output • CCP output • Input pin User selectable deadtime can be inserted in the drive outputs to prevent shoot through of configurations with two devices connected in series between the supply rails. Applications requiring very small frequency granularity control when the PWM frequency is large can do so with the fractional frequency control available in the variable frequency fixed Duty Cycle modes. DS40001579E-page 192  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.1.1 PERIOD EVENT prevent the PSMC output from chattering in the presence of spurious event inputs. A rising edge event The period event determines the frequency of the is also suppressed when it occurs after a falling edge active pulse. Period event sources include any event in the same period. combination of the following: The rising edge event also triggers the start of two other • PSMCxTMR counter match timers when needed: falling edge blanking and • PSMC input pin dead-band period. For more detail refer to • sync_C1OUT Section24.2.8 “Input Blanking” and Section24.4 • sync_C2OUT “Dead-Band Control”. • sync_C3OUT When the rising edge event is delayed from the period • start, the amount of delay subtracts from the total amount of time available for the drive duty cycle. For example, if Period event sources are selected with the PSMC the rising edge event is delayed by 10% of the period Period Source (PSMCxPRS) register (Register24-13). time, the maximum duty cycle for that period is 90%. A Section24.2.1.2 “16-bit Period Register” contains 100% duty cycle is still possible in this example, but duty details on configuring the PSMCxTMR counter match cycles from 90% to 100% are not possible. for synchronous period events. 24.1.3 FALLING EDGE EVENT All period events cause the PSMCxTMR counter to reset on the counting clock edge immediately following The falling edge event determines the end of the active the period event. The PSMCxTMR counter resumes drive period. The falling edge event is also referred to counting from zero on the counting clock edge after the as the duty cycle because varying the falling edge period event Reset. event, while keeping the rising edge event and period During a period, the rising event and falling event are events fixed, varies the active drive duty cycle. each permitted to occur only once. Subsequent rising Depending on the PSMC mode, one or more of the or falling events that may occur within the period are PSMC outputs will change in immediate response to suppressed, thereby preventing output chatter from the falling edge event. Falling edge event sources spurious inputs. include any combination of the following: 24.1.2 RISING EDGE EVENT • Synchronous: - PSMCxTMR time base counter match The rising edge event determines the start of the active • Asynchronous: drive period. The rising edge event is also referred to as the phase because two synchronized PSMC periph- - PSMC input pin erals may have different rising edge events relative to - sync_C1OUT the period start, thereby creating a phase relationship - sync_C2OUT between the two PSMC peripheral outputs. - sync_C3OUT Depending on the PSMC mode, one or more of the - PSMC outputs will change in immediate response to Falling edge event sources are selected with PSMC Duty the rising edge event. Rising edge event sources Cycle Source (PSMCxDCS) register (Register24-12). include any combination of the following: For configuring the PSMCxTMR time base counter • Synchronous: match for synchronous falling edge events, see - PSMCxTMR time base counter match Section24.2.1.4 “16-bit Duty Cycle Register”. • Asynchronous: The first falling edge event in a cycle period is the only - PSMC input pin one permitted to cause action. All subsequent falling - sync_C1OUT edge events in the same period are suppressed to - sync_C2OUT prevent the PSMC output from chattering in the - sync_C3OUT presence of spurious event inputs. - A falling edge event suppresses any subsequent rising edges that may occur in the same period. In other words, Rising edge event sources are selected with the PSMC if an asynchronous falling event input should come late Phase Source (PSMCxPHS) register (Register24-11). and occur early in the period, following that for which it For configuring the PSMCxTMR time base counter was intended, the rising edge in that period will be sup- match for synchronous rising edge events, see pressed. This will have a similar effect as pulse skipping. Section24.2.1.3 “16-bit Phase Register”. The falling edge event also triggers the start of two The first rising edge event in a cycle period is the only other timers: rising edge blanking and dead-band one permitted to cause action. All subsequent rising period. For more detail refer to Section24.2.8 “Input edge events in the same period are suppressed to Blanking” and Section24.4 “Dead-Band Control”.  2011-2014 Microchip Technology Inc. DS40001579E-page 193

PIC16(L)F1782/3 24.2 Event Sources 24.2.1.2 16-bit Period Register There are two main sources for the period, rising edge The PSMCxPR Period register is used to determine a and falling edge events: synchronous period event referenced to the 16-bit PSMCxTMR digital counter. A match between the • Synchronous input PSMCxTMR and PSMCxPR register values will - Time base generate a period event. • Asynchronous Inputs The match will generate a period match interrupt, - Digital Inputs thereby setting the PxTPRIF bit of the PSMC Time Base - Analog inputs Interrupt Control (PSMCxINT) register (Register24-32). The 16-bit period value is accessible to software as 24.2.1 TIME BASE two 8-bit registers: The Time Base section consists of several smaller • PSMC Period Count Low Byte (PSMCxPRL) pieces. register (Register24-23) • 16-bit time base counter • PSMC Period Count High Byte (PSMCxPRH) • 16-bit Period register register (Register24-24) • 16-bit Phase register (rising edge event) The 16-bit period value is double-buffered before it is • 16-bit Duty Cycle register (falling edge event) presented to the 16-bit time base for comparison. The • Clock control buffered registers are updated on the first period event • Interrupt Generator Reset after the PSMCxLD bit of the PSMCxCON register is set. An example of a fully synchronous PWM waveform generated with the time base is shown in Figure24-2. The synchronous PWM period time can be determined from Equation24-1. The PSMCxLD bit of the PSMCxCON register is provided to synchronize changes to the event Count EQUATION 24-1: PWM PERIOD registers. Changes are withheld from taking action until the first period event Reset after the PSMCxLD bit is PSMCxPR[15:0] +1 set. For example, to change the PWM frequency, while Period = -------------------------------------------------- F maintaining the same effective duty cycle, the Period psmc_clk and Duty Cycle registers need to be changed. The changes to all four registers take effect simultaneously on the period event Reset after the PSMCxLD bit is set. 24.2.1.3 16-bit Phase Register The PSMCxPH Phase register is used to determine a 24.2.1.1 16-bit Counter (Time Base) synchronous rising edge event referenced to the 16-bit The PSMCxTMR is the counter used as a timing PSMCxTMR digital counter. A match between the reference for each synchronous PWM period. The PSMCxTMR and the PSMCxPH register values will counter starts at 0000h and increments to FFFFh on generate a rising edge event. the rising edge of the psmc_clk signal. The match will generate a phase match interrupt, When the counter rolls over from FFFFh to 0000h thereby setting the PxTPHIF bit of the PSMC Time without a period event occurring, the overflow interrupt Base Interrupt Control (PSMCxINT) register will be generated, thereby setting the PxTOVIF bit of (Register24-32). the PSMC Time Base Interrupt Control (PSMCxINT) The 16-bit phase value is accessible to software as register (Register24-32). two 8-bit registers: The PSMCxTMR counter is reset on both synchronous • PSMC Phase Count Low Byte (PSMCxPHL) and asynchronous period events. register (Register24-32) The PSMCxTMR is accessible to software as two 8-bit • PSMC Phase Count High Byte (PSMCxPHH) registers: register (Register24-32) • PSMC Time Base Counter Low (PSMCxTMRL) The 16-bit phase value is double-buffered before it is register (Register24-17) presented to the 16-bit PSMCxTMR for comparison. • PSMC PSMC Time Base Counter High The buffered registers are updated on the first period (PSMCxTMRH) register (Register24-18) event Reset after the PSMCxLD bit of the PSMCxCON register is set. PSMCxTMR is reset to the default POR value when the PSMCxEN bit is cleared. DS40001579E-page 194  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.2.1.4 16-bit Duty Cycle Register Each interrupt has an interrupt flag bit and an interrupt enable bit. The interrupt flag bit is set anytime a given The PSMCxDC Duty Cycle register is used to event occurs, regardless of the status of the enable bit. determine a synchronous falling edge event referenced to the 16-bit PSMCxTMR digital counter. A Time base interrupt enables and flags are located in match between the PSMCxTMR and PSMCxDC the PSMC Time Base Interrupt Control (PSMCxINT) register values will generate a falling edge event. register (Register24-32). The match will generate a duty cycle match interrupt, PSMC time base interrupts also require that the thereby setting the PxTDCIF bit of the PSMC Time Base PSMCxTIE bit in the PIE4 register and the PEIE and Interrupt Control (PSMCxINT) register (Register24-32). GIE bits in the INTCON register be set in order to generate an interrupt. The PSMCxTIF interrupt flag in The 16-bit duty cycle value is accessible to software as two 8-bit registers: the PIR4 register will only be set by a time base interrupt when one or more of the enable bits in the • PSMC Duty Cycle Count Low Byte (PSMCxDCL) PSMCxINT register is set. register (Register24-21) The interrupt flag bits need to be cleared in software. • PSMC Duty Cycle Count High Byte (PSMCxDCH) However, all PMSCx time base interrupt flags, except register (Register24-22) PSMCxTIF, are cleared when the PSMCxEN bit is The 16-bit duty cycle value is double-buffered before it cleared. is presented to the 16-bit time base for comparison. The buffered registers are updated on the first period Interrupt bits that are set by software will generate an event Reset after the PSMCxLD bit of the PSMCxCON interrupt provided that the corresponding interrupt is register is set. enabled. When the period, phase, and duty cycle are all deter- Note: Interrupt flags in both the PIE4 and mined from the time base, the effective PWM duty PSMCxINT registers must be cleared to cycle can be expressed as shown in Equation24-2. clear the interrupt. The PSMCxINT flags must be cleared first. EQUATION 24-2: PWM DUTY CYCLE 24.2.5 PSMC TIME BASE CLOCK PSMCxDC[15:0]–PSMCxPH[15:0] SOURCES DUTYCYCLE = ----------------------------------------------------------------------------------------- PSMCxPR[15:0]+1 There are three clock sources available to the module: • Internal 64 MHz clock 24.2.2 0% DUTY CYCLE OPERATION • Fosc system clock USING TIME BASE • External clock input pin To configure the PWM for 0% duty cycle set The clock source is selected with the PxCSRC<1:0> PSMCxDC<15:0>=PSMCxPH<15:0>. This will trigger bits of the PSMCx Clock Control (PSMCxCLK) register a falling edge event simultaneous with the rising edge (Register24-5). event and prevent the PWM from being asserted. When the Internal 64 MHz clock is selected as the source, the HFINTOSC continues to operate and clock 24.2.3 100% DUTY CYCLE OPERATION the PSMC circuitry in Sleep. However, the system USING TIME BASE clock to other peripherals and the CPU is suppressed. To configure the PWM for 100% duty cycle set Note: When the 64MHz clock is selected, the PSMCxDC<15:0> > PSMCxPR<15:0>. clock continues to operate in Sleep, even This will prevent a falling edge event from occurring as when the PSMC is disabled the PSMCxDC<15:0> value and the time base value (PSMCxEN=0). Select a clock other than PSMCxTMR<15:0> will never be equal. the 64MHz clock to minimize power con- sumption when the PSMC is not enabled. 24.2.4 TIME BASE INTERRUPT GENERATION The Internal 64 MHz clock utilizes the system clock 4xPLL. When the system clock source is external and The Time Base section can generate four unique the PSMC is using the Internal 64 MHz clock, the interrupts: 4xPLL should not be used for the system clock. • Time Base Counter Overflow Interrupt • Time Base Phase Register Match Interrupt • Time Base Duty Cycle Register Match Interrupt • Time Base Period Register Match Interrupt  2011-2014 Microchip Technology Inc. DS40001579E-page 195

PIC16(L)F1782/3 24.2.6 CLOCK PRESCALER The clock source is selected with the PxCPRE<1:0> bits of the PSMCx Clock Control (PSMCxCLK) register There are four prescaler choices available to be (Register24-5). applied to the selected clock: The prescaler output is psmc_clk, which is the clock • Divide by 1 used by all of the other portions of the PSMC module. • Divide by 2 • Divide by 4 • Divide by 8 FIGURE 24-3: TIME BASE WAVEFORM GENERATION Period 1 psmc_clk Counter 0030h 0000h 0001h 0002h 0003h 0027h 0028h 0029h 0030h 0000h PSMCxPH<15:0> 0002h PSMCxDC<15:0> 0028h PSMCxPR<15:0> 0030h Inputs Period Event Rising Edge Event Falling Edge Event Output PWM Output DS40001579E-page 196  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.2.7 ASYNCHRONOUS INPUTS The Falling Edge Blanking mode is set with the PxFEBM<1:0> bits of the PSMCx Blanking Control The PSMC module supports asynchronous inputs (PSMCxBLNK) register (Register24-8). alone or in combination with the synchronous inputs. asynchronous inputs include: The Rising Edge Blanking mode is set with the PxREBM<1:0> bits of the PSMCx Blanking Control • Analog (PSMCxBLNK) register (Register24-8). - sync_C1OUT - sync_C2OUT 24.2.8.1 Blanking Disabled - sync_C3OUT • Digital With blanking disabled, the asynchronous inputs are - PSMCxIN pin passed to the PSMC module without any intervention. 24.2.7.1 Comparator Inputs 24.2.8.2 Immediate Blanking The outputs of any combination of the synchronized With Immediate blanking, a counter is used to comparators may be used to trigger any of the three determine the blanking period. The desired blanking events as well as auto-shutdown. time is measured in psmc_clk periods. A rising edge event will start incrementing the rising edge blanking The event triggers on the rising edge of the compara- counter. A falling edge event will start incrementing the tor output. Except for auto-shutdown, the event input is falling edge blanking counter. not level sensitive. The rising edge blanking time is set with the PSMC 24.2.7.2 PSMCxIN Pin Input Rising Edge Blanking Time (PSMCxBLKR) register The PSMCxIN pin may be used to trigger PSMC (Register24-28). The inputs to be blanked are events. Data is passed through straight to the PSMC selected with the PSMC Rising Edge Blanked Source module without any synchronization to a system clock. (PSMCxREBS) register (Register24-9). During rising This is so that input blanking may be applied to any edge blanking, the selected blanked sources are external circuit using the module. suppressed for falling edge as well as rising edge, auto-shutdown and period events. The event triggers on the rising edge of the PSMCxIN signal. The falling edge blanking time is set with the PSMC Falling Edge Blanking Time (PSMCxBLKF) register 24.2.8 INPUT BLANKING (Register24-29). The inputs to be blanked are selected with the PSMC Falling Edge Blanked Source Input blanking is a function whereby the inputs from (PSMCxFEBS) register (Register24-10). During any selected asynchronous input may be driven falling edge blanking, the selected blanked sources inactive for a short period of time. This is to prevent are suppressed for rising edge, as well as falling edge, electrical transients from the turn-on/off of power auto-shutdown, and period events. components from generating a false event. The blanking counters are incremented on the rising Blanking is initiated by either or both: edge of psmc_clk. Blanked sources are suppressed • Rising event until the counter value equals the blanking time • Falling event register causing the blanking to terminate. Blanked inputs are suppressed from causing all As the rising and falling edge events are from asynchronous events, including: asynchronous inputs, there may be some uncertainty • Rising in the actual blanking time implemented in each cycle. • Falling The maximum uncertainty is equal to one psmc_clk • Period period. • Shutdown Rising edge and falling edge blanking are controlled independently. The following features are available for blanking: • Blanking enable • Blanking time counters • Blanking mode The following Blanking modes are available: • Blanking disabled • Immediate blanking  2011-2014 Microchip Technology Inc. DS40001579E-page 197

PIC16(L)F1782/3 24.2.9 OUTPUT WAVEFORM 24.3 Modes of Operation GENERATION All modes of operation use the period, rising edge, and The PSMC PWM output waveform is generated based falling edge events to generate the various PWM upon the different input events. However, there are output waveforms. several other factors that affect the PWM waveshapes: The 3-phase 6-step PWM mode makes special use of • Output Control the software controlled steering to generate the - Output Enable required waveform. - Output Polarity Modes of operation are selected with the PSMC • Waveform Mode Selection Control (PSMCxCON) register (Register24-1). • Dead-band Control 24.3.1 SINGLE-PHASE MODE • Steering control The single PWM is the most basic of all the 24.2.10 OUTPUT CONTROL waveshapes generated by the PSMC module. It consists of a single output that uses all three events 24.2.10.1 Output Pin Enable (rising edge, falling edge and period events) to Each PSMC PWM output pin has individual output generate the waveform. enable control. 24.3.1.1 Mode Features When the PSMC output enable control is disabled, the • No dead-band control available module asserts no control over the pin. In this state, the pin can be used for general purpose I/O or other • PWM can be steered to any combination of the associate peripheral use. following PSMC outputs: - PSMCxA When the PSMC output enable is enabled, the active PWM waveform is applied to the pin per the port - PSMCxB priority selection. - PSMCxC PSMC output enable selections are made with the - PSMCxD PSMC Output Enable Control (PSMCxOEN) register - PSMCxE (Register24-6). - PSMCxF • Identical PWM waveform is presented to all pins 24.2.10.2 Output Steering for which steering is enabled. PWM output will be presented only on pins for which output steering is enabled. The PSMC has up to six 24.3.1.2 Waveform Generation PWM outputs. The PWM signal in some modes can be Rising Edge Event steered to one or more of these outputs. • All outputs with PxSTR enabled are set to the Steering differs from output enable in the following active state manner: When the output is enabled but the PWM steering to the corresponding output is not enabled, Falling Edge Event then general purpose output to the pin is disabled and • All outputs with PxSTR enabled are set to the the pin level will remain constantly in the inactive PWM inactive state state. Output steering is controlled with the PSMCS Code for setting up the PSMC generate the Steering Control 0 (PSMCxSTR0) register single-phase waveform shown in Figure24-4, and given (Register24-30). in Example24-1. Steering operates only in the following modes: • Single-phase • Complementary Single-phase • 3-phase 6-step PWM 24.2.10.3 Polarity Control Each PSMC output has individual output polarity control. Polarity is set with the PSMC Polarity Control (PSMCxPOL) register (Register24-7). DS40001579E-page 198  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 EXAMPLE 24-1: SINGLE-PHASE SETUP ; Single-phase PWM PSMC setup ; Fully synchronous operation ; Period = 10 us ; Duty cycle = 50% BANKSEL PSMC1CON MOVLW 0x02 ; set period MOVWF PSMC1PRH MOVLW 0x7F MOVWF PSMC1PRL MOVLW 0x01 ; set duty cycle MOVWF PSMC1DCH MOVLW 0x3F MOVWF PSMC1DCL CLRF PSMC1PHH ; no phase offset CLRF PSMC1PHL MOVLW 0x01 ; PSMC clock=64 MHz MOVWF PSMC1CLK ; output on A, normal polarity BSF PSMC1STR0,P1STRA BCF PSMC1POL, P1POLA BSF PSMC1OEN, P1OEA ; set time base as source for all events BSF PSMC1PRS, P1PRST BSF PSMC1PHS, P1PHST BSF PSMC1DCS, P1DCST ; enable PSMC in Single-Phase Mode ; this also loads steering and time buffers MOVLW B’11000000’ MOVWF PSMC1CON BANKSEL TRISC BCF TRISC, 0 ; enable pin driver FIGURE 24-4: SINGLE PWM WAVEFORM – PSMCXSTR0=01H PWM Period Number 1 2 3 Period Event Rising Edge Event Falling Edge Event PSMCxA  2011-2014 Microchip Technology Inc. DS40001579E-page 199

PIC16(L)F1782/3 24.3.2 COMPLEMENTARY PWM EXAMPLE 24-2: COMPLEMENTARY SINGLE-PHASE SETUP The complementary PWM uses the same events as the single PWM, but two waveforms are generated ; Complementary Single-phase PWM PSMC setup instead of only one. ; Fully synchronous operation ; Period = 10 us The two waveforms are opposite in polarity to each ; Duty cycle = 50% other. The two waveforms may also have dead-band ; Deadband = 93.75 +15.6/-0 ns control as well. BANKSEL PSMC1CON MOVLW 0x02 ; set period 24.3.2.1 Mode Features and Controls MOVWF PSMC1PRH MOVLW 0x7F • Dead-band control available MOVWF PSMC1PRL • PWM primary output can be steered to the MOVLW 0x01 ; set duty cycle following pins: MOVWF PSMC1DCH - PSMCxA MOVLW 0x3F MOVWF PSMC1DCL - PSMCxC CLRF PSMC1PHH ; no phase offset - PSMCxE CLRF PSMC1PHL • PWM complementary output can be steered to MOVLW 0x01 ; PSMC clock=64 MHz the following pins: MOVWF PSMC1CLK ; output on A, normal polarity - PSMCxB MOVLW B’00000011’; A and B enables - PSMCxD MOVWF PSMC1OEN - PSMCxE MOVWF PSMC1STR0 CLRF PSMC1POL 24.3.2.2 Waveform Generation ; set time base as source for all events BSF PSMC1PRS, P1PRST Rising Edge Event BSF PSMC1PHS, P1PHST • Complementary output is set inactive BSF PSMC1DCS, P1DCST ; set rising and falling dead-band times • Optional rising edge dead band is activated MOVLW D’6’ • Primary output is set active MOVWF PSMC1DBR Falling Edge Event MOVWF PSMC1DBF ; enable PSMC in Complementary Single Mode • Primary output is set inactive ; this also loads steering and time buffers • Optional falling edge dead band is activated ; and enables rising and falling deadbands • Complementary output is set active MOVLW B’11110001’ MOVWF PSMC1CON Code for setting up the PSMC generate the BANKSEL TRISC complementary single-phase waveform shown in BCF TRISC, 0 ; enable pin drivers Figure24-5, and given in Example24-2. BCF TRISC, 1 FIGURE 24-5: COMPLEMENTARY PWM WAVEFORM – PSMCXSTR0=03H PWM Period Number 1 2 3 Period Event Rising Edge Event Falling Edge Event PSMCxA (Primary Output) Rising Edge Dead Band Rising Edge Dead Band Falling Edge Dead Band Falling Edge Dead Band PSMCxB (Complementary Output) DS40001579E-page 200  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.3.3 PUSH-PULL PWM Code for setting up the PSMC generate the comple- mentary single-phase waveform shown in Figure24-6, The push-pull PWM is used to drive transistor bridge and given in Example24-3. circuits. It uses at least two outputs and generates PWM signals that alternate between the two outputs in EXAMPLE 24-3: PUSH-PULL SETUP even and odd cycles. ; Push-Pull PWM PSMC setup Variations of the push-pull waveform include four ; Fully synchronous operation outputs with two outputs being complementary or two ; Period = 10 us sets of two identical outputs. Refer to Sections24.3.4 ; Duty cycle = 50% (25% each phase) through24.3.6 for the other Push-Pull modes. BANKSEL PSMC1CON MOVLW 0x02 ; set period 24.3.3.1 Mode Features MOVWF PSMC1PRH • No dead-band control available MOVLW 0x7F MOVWF PSMC1PRL • No steering control available MOVLW 0x01 ; set duty cycle • Output is on the following two pins only: MOVWF PSMC1DCH - PSMCxA MOVLW 0x3F MOVWF PSMC1DCL - PSMCxB CLRF PSMC1PHH ; no phase offset CLRF PSMC1PHL MOVLW 0x01 ; PSMC clock=64 MHz Note: This is a subset of the 6-pin output of the MOVWF PSMC1CLK push-pull PWM output, which is why pin ; output on A and B, normal polarity functions are fixed in these positions, so MOVLW B’00000011’ they are compatible with that mode. See MOVWF PSMC1OEN Section24.3.6 “Push-Pull PWM with Four CLRF PSMC1POL Full-Bridge and Complementary Out- ; set time base as source for all events puts” BSF PSMC1PRS, P1PRST BSF PSMC1PHS, P1PHST 24.3.3.2 Waveform Generation BSF PSMC1DCS, P1DCST ; enable PSMC in Push-Pull Mode Odd numbered period rising edge event: ; this also loads steering and time buffers MOVLW B’11000010’ • PSMCxA is set active MOVWF PSMC1CON Odd numbered period falling edge event: BANKSEL TRISC BCF TRISC, 0 ; enable pin drivers • PSMCxA is set inactive BCF TRISC, 1 Even numbered period rising edge event: • PSMCxB is set active Even numbered period falling edge event: • PSMCxB is set inactive FIGURE 24-6: PUSH-PULL PWM WAVEFORM PWM Period Number 1 2 3 A Output A Output Period Event B Output Rising Edge Event Falling Edge Event PSMCxA PSMCxB  2011-2014 Microchip Technology Inc. DS40001579E-page 201

PIC16(L)F1782/3 24.3.4 PUSH-PULL PWM WITH 24.3.4.2 Waveform Generation COMPLEMENTARY OUTPUTS Push-Pull waveforms generate alternating outputs on The complementary push-pull PWM is used to drive the output pairs. Therefore, there are two sets of rising transistor bridge circuits as well as synchronous edge events and two sets of falling edge events switches on the secondary side of the bridge. The Odd numbered period rising edge event: PWM waveform is output on four pins presented as • PSMCxE is set inactive two pairs of two-output signals with a normal and complementary output in each pair. Dead band can be • Dead-band rising is activated (if enabled) inserted between the normal and complementary • PSMCxA is set active outputs at the transition times. Odd numbered period falling edge odd event: 24.3.4.1 Mode Features • PSMCxA is set inactive • Dead-band falling is activated (if enabled) • Dead-band control is available • PSMCxE is set active • No steering control available • Primary PWM output is only on: Even numbered period rising edge event: - PSMCxA • PSMCxF is set inactive - PSMCxB • Dead-band rising is activated (if enabled) • Complementary PWM output is only on: • PSMCxB is set active - PSMCxE Even numbered period falling edge event: - PSMCxF • PSMCxB is set inactive • Dead-band falling is activated (if enabled) Note: This is a subset of the 6-pin output of the • PSMCxF is set active push-pull PWM output, which is why pin func- tions are fixed in these positions, so they are compatible with that mode. See Section24.3.6 “Push-Pull PWM with Four Full-Bridge and Complementary Outputs”. FIGURE 24-7: PUSH-PULL WITH COMPLEMENTARY OUTPUTS PWM WAVEFORM PWM Period Number 1 2 3 Period Event Rising Edge Event Falling Edge Event Rising Edge Dead Band Rising Edge Dead Band PSMCxA Falling Edge Dead Band Falling Edge Dead Band PSMCxE PSMCxB Falling Edge Dead Band Rising Edge Dead Band PSMCxF DS40001579E-page 202  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.3.5 PUSH-PULL PWM WITH FOUR FULL-BRIDGE OUTPUTS Note: This is a subset of the 6-pin output of the The full-bridge push-pull PWM is used to drive push-pull PWM output, which is why pin func- transistor bridge circuits as well as synchronous tions are fixed in these positions, so they are switches on the secondary side of the bridge. compatible with that mode. See Section24.3.6 “Push-Pull PWM with Four 24.3.5.1 Mode Features Full-Bridge and Complementary Outputs”. • No Dead-band control 24.3.5.2 Waveform generation • No Steering control available Push-pull waveforms generate alternating outputs on • PWM is output on the following four pins only: the output pairs. Therefore, there are two sets of rising - PSMCxA edge events and two sets of falling edge events. - PSMCxB Odd numbered period rising edge event: - PSMCxC • PSMCxOUT0 and PSMCxOUT2 is set active - PSMCxD Odd numbered period falling edge event: • PSMCxOUT0 and PSMCxOUT2 is set inactive Note: PSMCxA and PSMCxC are identical waveforms, and PSMCxB and PSMCxD are Even numbered period rising edge event: identical waveforms. • PSMCxOUT1 and PSMCxOUT3 is set active Even numbered period falling edge event: • PSMCxOUT1 and PSMCxOUT3 is set inactive FIGURE 24-8: PUSH-PULL PWM WITH 4 FULL-BRIDGE OUTPUTS PWM Period Number 1 2 3 Period Event Rising Edge Event Falling Edge Event PSMCxA PSMCxC PSMCxB PSMCxD  2011-2014 Microchip Technology Inc. DS40001579E-page 203

PIC16(L)F1782/3 24.3.6 PUSH-PULL PWM WITH FOUR 24.3.6.2 Waveform Generation FULL-BRIDGE AND Push-pull waveforms generate alternating outputs on COMPLEMENTARY OUTPUTS two sets of pin. Therefore, there are two sets of rising The push-pull PWM is used to drive transistor bridge edge events and two sets of falling edge events circuits as well as synchronous switches on the Odd numbered period rising edge event: secondary side of the bridge. It uses six outputs and • PSMCxE is set inactive generates PWM signals with dead band that alternate between the six outputs in even and odd cycles. • Dead-band rising is activated (if enabled) • PSMCxA and PSMCxC are set active 24.3.6.1 Mode Features and Controls Odd numbered period falling edge event: • Dead-band control is available • PSMCxA and PSMCxC are set inactive • No steering control available • Dead-band falling is activated (if enabled) • Primary PWM is output on the following four pins: • PSMCxE is set active - PSMCxA Even numbered period rising edge event: - PSMCxB • PSMCxF is set inactive - PSMCxC • Dead-band rising is activated (if enabled) - PSMCxD • PSMCxB and PSMCxD are set active • Complementary PWM is output on the following two pins: Even numbered period falling edge event: - PSMCxE • PSMCxB and PSMCxOUT3 are set inactive - PSMCxF • Dead-band falling is activated (if enabled) Note: PSMCxA and PSMCxC are identical • PSMCxF is set active waveforms, and PSMCxB and PSMCxD are identical waveforms. FIGURE 24-9: PUSH-PULL 4 FULL-BRIDGE AND COMPLEMENTARY PWM PWM Period Number 1 2 3 Period Event Rising Edge Event Falling Edge Event Rising Edge Dead Band Rising Edge Dead Band PSMCxA PSMCxC Falling Edge Dead Band Falling Edge Dead Band PSMCxE PSMCxB PSMCxD Falling Edge Dead Band Rising Edge Dead Band PSMCxF DS40001579E-page 204  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.3.7 PULSE-SKIPPING PWM 24.3.7.2 Waveform Generation The pulse-skipping PWM is used to generate a series Rising Edge Event of fixed-length pulses that can be triggered at each If any enabled asynchronous rising edge event = 1 period event. A rising edge event will be generated when there is a period event, then upon the next when any enabled asynchronous rising edge input is synchronous rising edge event: active when the period event occurs, otherwise no event will be generated. • PSMCxA is set active The rising edge event occurs based upon the value in Falling Edge Event the PSMCxPH register pair. • PSMCxA is set inactive The falling edge event always occurs according to the enabled event inputs without qualification between any Note: To use this mode, an external source must two inputs. be used for the determination of whether or 24.3.7.1 Mode Features not to generate the set pulse. If the phase time base is used, it will either always gener- • No dead-band control available ate a pulse or never generate a pulse based • No steering control available on the PSMCxPH value. • PWM is output to only one pin: - PSMCxA FIGURE 24-10: PULSE-SKIPPING PWM WAVEFORM PWM Period Number 1 2 3 4 5 6 7 8 9 10 11 12 period_event Asynchronous Rising Edge Event Synchronous Rising Edge Event Falling Edge Event PSMCxA  2011-2014 Microchip Technology Inc. DS40001579E-page 205

PIC16(L)F1782/3 24.3.8 PULSE-SKIPPING PWM WITH 24.3.8.2 Waveform Generation COMPLEMENTARY OUTPUTS Rising Edge Event The pulse-skipping PWM is used to generate a series If any enabled asynchronous rising edge event = 1 of fixed-length pulses that may or not be triggered at when there is a period event, then upon the next each period event. If any of the sources enabled to synchronous rising edge event: generate a rising edge event are high when a period • Complementary output is set inactive event occurs, a pulse will be generated. If the rising edge sources are low at the period event, no pulse will • Dead-band rising is activated (if enabled) be generated. • Primary output is set active The rising edge occurs based upon the value in the Falling Edge Event PSMCxPH register pair. • Primary output is set inactive The falling edge event always occurs according to the • Dead-band falling is activated (if enabled) enabled event inputs without qualification between any • Complementary output is set active two inputs. 24.3.8.1 Mode Features Note: To use this mode, an external source must • Dead-band control is available be used for the determination of whether or not to generate the set pulse. If the phase • No steering control available time base is used, it will either always gener- • Primary PWM is output on only PSMCxA. ate a pulse or never generate a pulse based • Complementary PWM is output on only PSMCxB. on the PSMCxPH value. FIGURE 24-11: PULSE-SKIPPING WITH COMPLEMENTARY OUTPUT PWM WAVEFORM PWM Period Number 1 2 3 4 5 6 7 8 9 10 Period Event Asynchronous Rising Edge Event Synchronous Rising Edge Event PSMCxA Falling Edge Dead Band Rising Edge Dead Band PSMCxB DS40001579E-page 206  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.3.9 ECCP COMPATIBLE FULL-BRIDGE 24.3.9.2 Waveform Generation - Forward PWM In this mode of operation, three of the four pins are This mode of operation is designed to match the static. PSMCxA is the only output that changes based Full-Bridge mode from the ECCP module. It is called on rising edge and falling edge events. ECCP compatible as the term “full-bridge” alone has Static Signal Assignment different connotations in regards to the output • Outputs set to active state waveforms. - PSMCxD Full-Bridge Compatible mode uses the same • Outputs set to inactive state waveform events as the single PWM mode to generate the output waveforms. - PSMCxB - PSMCxC There are both Forward and Reverse modes available for this operation, again to match the ECCP implemen- Rising Edge Event tation. Direction is selected with the mode control bits. • PSMCxA is set active 24.3.9.1 Mode Features Falling Edge Event • Dead-band control available on direction switch • PSMCxA is set inactive - Changing from forward to reverse uses the 24.3.9.3 Waveform Generation – Reverse falling edge dead-band counters. - Changing from reverse to forward uses the In this mode of operation, three of the four pins are rising edge dead-band counters. static. Only PSMCxB toggles based on rising edge and falling edge events. • No steering control available • PWM is output on the following four pins only: Static Signal Assignment - PSMCxA • Outputs set to active state - PSMCxB - PSMCxC - PSMCxC • Outputs set to inactive state - PSMCxD - PSMCxA - PSMCxD Rising Edge Event • PSMCxB is set active Falling Edge Event • PSMCxB is set inactive FIGURE 24-12: ECCP COMPATIBLE FULL-BRIDGE PWM WAVEFORM – PSMCXSTR0=0FH PWM Period Number 1 2 3 4 5 6 7 8 9 10 11 12 Forward mode operation Reverse mode operation Period Event Falling Edge Event PSMCxA PSMCxB PSMCxC Rising Edge Dead Band Falling Edge Dead Band PSMCxD  2011-2014 Microchip Technology Inc. DS40001579E-page 207

PIC16(L)F1782/3 24.3.10 VARIABLE FREQUENCY – FIXED 24.3.10.2 Waveform Generation DUTY CYCLE PWM Period Event This mode of operation is quite different from all of the • Output of PSMCxA is toggled other modes. It uses only the period event for • FFA counter is incremented by the 4-bit value in waveform generation. At each period event, the PWM PSMCxF FA output is toggled. The rising edge and falling edge events are unused in this mode. 24.3.10.1 Mode Features • No dead-band control available • No steering control available • Fractional Frequency Adjust - Fine period adjustments are made with the PSMC Fractional Frequency Adjust (PSMCxFFA) register (Register24-27) • PWM is output on the following pin only: - PSMCxA FIGURE 24-13: VARIABLE FREQUENCY – FIXED DUTY CYCLE PWM WAVEFORM PWM Period Number 1 2 3 4 5 6 7 8 9 10 period_event Rising Edge Event Unused in this mode Falling Edge Event Unused in this mode PSMCxA DS40001579E-page 208  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.3.11 VARIABLE FREQUENCY - FIXED 24.3.11.2 Waveform Generation DUTY CYCLE PWM WITH Period Event COMPLEMENTARY OUTPUTS When output is going inactive to active: This mode is the same as the single output Fixed Duty • Complementary output is set inactive Cycle mode except a complementary output with dead-band control is generated. • FFA counter is incremented by the 4-bit value in PSMCFFA register. The rising edge and falling edge events are unused in • Dead-band rising is activated (if enabled) this mode. Therefore, a different triggering mechanism is required for the dead-band counters. • Primary output is set active A period events that generate a rising edge on When output is going active to inactive: PSMCxA use the rising edge dead-band counters. • Primary output is set inactive A period events that generate a falling edge on • FFA counter is incremented by the 4-bit value in PSMCxA use the falling edge dead-band counters. PSMCFFA register • Dead-band falling is activated (if enabled) 24.3.11.1 Mode Features • Complementary output is set active • Dead-band control is available • No steering control available • Fractional Frequency Adjust - Fine period adjustments are made with the PSMC Fractional Frequency Adjust (PSMCxFFA) register (Register24-27) • Primary PWM is output to the following pin: - PSMCxA • Complementary PWM is output to the following pin: - PSMCxB FIGURE 24-14: VARIABLE FREQUENCY – FIXED DUTY CYCLE PWM WITH COMPLEMENTARY OUTPUTS WAVEFORM PWM Period Number 1 2 3 4 5 6 7 8 9 10 period_event Rising Edge Event Unused in this mode Falling Edge Event Unused in this mode PSMCxA Falling Edge Dead Band Rising Edge Dead Band PSMCxB  2011-2014 Microchip Technology Inc. DS40001579E-page 209

PIC16(L)F1782/3 24.3.12 3-PHASE PWM 24.3.12.2 Waveform Generation The 3-Phase mode of operation is used in 3-phase 3-phase steering has a more complex waveform power supply and motor drive applications configured generation scheme than the other modes. There are as three half-bridges. A half-bridge configuration several factors which go into what waveforms are consists of two power driver devices in series, created. between the positive power rail (high side) and nega- The PSMC outputs are grouped into three sets of tive power rail (low side). The three outputs come from drivers: one for each phase. Each phase has two the junctions between the two drivers in each associated PWM outputs: one for the high-side drive half-bridge. When the steering control selects a phase and one for the low-side drive. drive, power flows from the positive rail through a high-side power device to the load and back to the High Side drives are indicated by 1H, 2H and 3H. power supply through a low-side power device. Low Side drives are indicated by 1L, 2L, 3L. In this mode of operation, all six PSMC outputs are Phase grouping is mapped as shown in Table24-1. used, but only two are active at a time. There are six possible phase drive combinations. The two active outputs consist of a high-side driver Each phase drive combination activates two of the six and low-side driver output. outputs and deactivates the other four. Phase drive is selected with the steering control as shown in 24.3.12.1 Mode Features Table24-2. • No dead-band control is available TABLE 24-1: PHASE GROUPING • PWM can be steered to the following six pairs: PSMC grouping - PSMCxA and PSMCxD PSMCxA 1H - PSMCxA and PSMCxF PSMCxB 1L - PSMCxC and PSMCxF - PSMCxC and PSMCxB PSMCxC 2H - PSMCxE and PSMCxB PSMCxD 2L - PSMCxE and PSMCxD PSMCxE 3H PSMCxF 3L TABLE 24-2: 3-PHASE STEERING CONTROL PSMCxSTR0 Value(1) PSMC outputs 00h 01h 02h 04h 08h 10h 20h PSMCxA 1H inactive active active inactive inactive inactive inactive PSMCxB 1L inactive inactive inactive inactive active active inactive PSMCxC 2H inactive inactive inactive active active inactive inactive PSMCxD 2L inactive active inactive inactive inactive inactive active PSMCxE 3H inactive inactive inactive inactive inactive active active PSMCxF 3L inactive inactive active active inactive inactive inactive Note 1: Steering for any value other than those shown will default to the output combination of the Least Significant steering bit that is set. High/Low Side Modulation Enable When both the PxHSMEN and PxLSMEN bits are cleared, the active outputs listed in Table24-2 go It is also possible to enable the PWM output on the low immediately to the rising edge event states and do not side or high side drive independently using the change. PxLSMEN and PXHSMEN bits of the PSMC Steering Control 1 (PSMCxSTR1) register (Register24-31). Rising Edge Event When the PxHSMEN bit is set, the active-high side • Active outputs are set to their active states output listed in Table24-2 is modulated using the Falling Edge Event normal rising edge and falling edge events. • Active outputs are set to their inactive state When the PxLSMEN bit is set, the active-low side output listed in Table24-2 is modulated using the normal rising edge and falling edge events. DS40001579E-page 210  2011-2014 Microchip Technology Inc.

 FIGURE 24-15: 3-PHASE PWM STEERING WAVEFORM (PXHSMEN = 0 AND PXLSMEN = 1) 2 0 1 1-2 3-Phase State 1 2 3 4 5 6 0 1 4 M PSMCxSTR0 01h 02h 04h 08h 10h 20h ic ro c h ip T Period Event e c h n o Rising Edge Event lo g y In c Falling Edge Event . PSMCxA (1H) PSMCxB (1L) PSMCxC (2H) PSMCxD (2L) PSMCxE (3H) PSMCxF (3L) P I C 1 6 ( L D ) S F 4 0 00 1 1 5 7 7 9 E 8 -p a 2 g e 2 /3 1 1

PIC16(L)F1782/3 24.4 Dead-Band Control 24.4.3 DEAD-BAND CLOCK SOURCE The dead-band control provides non-overlapping The dead-band counters are incremented on every PWM signals to prevent shoot-through current in rising edge of the psmc_clk signal. series connected power switches. Dead-band control 24.4.4 DEAD-BAND UNCERTAINTY is available only in modes with complementary drive and when changing direction in the ECCP compatible When the rising and falling edge events that trigger the Full-Bridge modes. dead-band counters come from asynchronous inputs, there will be uncertainty in the actual dead-band time of The module contains independent 8-bit dead-band each cycle. The maximum uncertainty is equal to one counters for rising edge and falling edge dead-band psmc_clk period. The one clock of uncertainty may still control. be introduced, even when the dead-band count time is 24.4.1 DEAD-BAND TYPES cleared to zero. There are two separate dead-band generators 24.4.5 DEAD-BAND OVERLAP available, one for rising edge events and the other for There are two cases of dead-band overlap and each is falling edge events. treated differently due to system requirements. 24.4.1.1 Rising Edge Dead Band 24.4.5.1 Rising to Falling Overlap Rising edge dead-band control is used to delay the In this case, the falling edge event occurs while the turn-on of the primary switch driver from when the rising edge dead-band counter is still counting. The complementary switch driver is turned off. following sequence occurs: Rising edge dead band is initiated with the rising edge 1. Dead-band rising count is terminated. event. 2. Dead-band falling count is initiated. Rising edge dead-band time is adjusted with the 3. Primary output is suppressed. PSMC Rising Edge Dead-Band Time (PSMCxDBR) register (Register24-25). 24.4.5.2 Falling to Rising Overlap If the PSMCxDBR register value is changed when the In this case, the rising edge event occurs while the PSMC is enabled, the new value does not take effect falling edge dead-band counter is still counting. The until the first period event after the PSMCxLD bit is set. following sequence occurs: 24.4.1.2 Falling Edge Dead Band 1. Dead-band falling count is terminated. Falling edge dead-band control is used to delay the 2. Dead-band rising count is initiated. turn-on of the complementary switch driver from when 3. Complementary output is suppressed. the primary switch driver is turned off. 24.4.5.3 Rising Edge-to-Rising Edge or Falling edge dead band is initiated with the falling Falling Edge-to-Falling Edge edge event. In cases where one of the two dead-band counters is Falling edge dead-band time is adjusted with the set for a short period, or disabled all together, it is PSMC Falling Edge Dead-Band Time (PSMCxDBF) possible to get rising-to-rising or falling-to-falling register (Register24-26). overlap. When this is the case, the following sequence If the PSMCxDBF register value is changed when the occurs: PSMC is enabled, the new value does not take effect 1. Dead-band count is terminated. until the first period event after the PSMCxLD bit is set. 2. Dead-band count is restarted. 24.4.2 DEAD-BAND ENABLE 3. Output waveform control freezes in the present When a mode is selected that may use dead-band state. control, dead-band timing is enabled by setting one of 4. Restarted dead-band count completes. the enable bits in the PSMC Control (PSMCxCON) 5. Output control resumes normally. register (Register24-1). Rising edge dead band is enabled with the PxDBRE bit. Rising edge dead band is enabled with the PxDBFE bit. Enable changes take effect immediately. DS40001579E-page 212  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.5 Output Steering 24.5.1 3-PHASE STEERING Output steering allows for PWM signals generated by 3-phase steering is available in the 3-Phase Modulation the PSMC module to be placed on different pins under mode only. For more details on 3-phase steering refer to software control. Synchronized steering will hold steer- Section24.3.12 “3-Phase PWM”. ing changes until the first period event after the 24.5.2 SINGLE PWM STEERING PSMCxLD bit is set. Unsynchronized steering changes will take place immediately. In Single PWM Steering mode, the single PWM signal can be routed to any combination of the PSMC output Output steering is available in the following modes: pins. Examples of unsynchronized single PWM • 3-phase PWM steering are shown in Figure24-16. • Single PWM • Complementary PWM FIGURE 24-16: SINGLE PWM STEERING WAVEFORM (NO SYNCHRONIZATION) Base_PWM_signal PxSTRA PSMCxA PxSTRB PSMCxB PxSTRC PSMCxC PxSTRD PSMCxD PxSTRE PSMCxE PxSTRF PSMCxF With synchronization disabled, it is possible to get glitches on the PWM outputs.  2011-2014 Microchip Technology Inc. DS40001579E-page 213

PIC16(L)F1782/3 24.5.3 COMPLEMENTARY PWM The complementary PWM signal can be steered to any STEERING of the following outputs: In Complementary PWM Steering mode, the primary • PSMCxB PWM signal (non-complementary) and complementary • PSMCxD signal can be steered according to their respective type. • PSMCxE Primary PWM signal can be steered to any of the Examples of unsynchronized complementary steering following outputs: are shown in Figure24-17. • PSMCxA • PSMCxC • PSMCxE FIGURE 24-17: COMPLEMENTARY PWM STEERING WAVEFORM (NO SYNCHRONIZATION, ZERO DEAD-BAND TIME) Base_PWM_signal PxSTRA PSMCxA PSMCxB PxSTRB Arrows indicate where a change in the steering bit automatically forces a change in the corresponding PSMC output. PxSTRC PSMCxC PSMCxD PxSTRD PxSTRE PSMCxE PSMCxF PxSTRF DS40001579E-page 214  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.5.4 SYNCHRONIZED PWM STEERING Examples of synchronized steering are shown in Figure24-18. In Single, Complementary and 3-phase PWM modes, it is possible to synchronize changes to steering 24.5.5 INITIALIZING SYNCHRONIZED selections with the period event. This is so that PWM STEERING outputs do not change in the middle of a cycle and therefore, disrupt operation of the application. If synchronized steering is to be used, special care should be taken to initialize the PSMC Steering Steering synchronization is enabled by setting the Control 0 (PSMCxSTR0) register (Register24-30) in a PxSSYNC bit of the PSMC Steering Control 1 safe configuration before setting either the PSMCxEN (PSMCxSTR1) register (Register24-31). or PSMCxLD bits. When either of those bits are set, When synchronized steering is enabled while the the PSMCxSTR0 value at that time is loaded into the PSMC module is enabled, steering changes do not synchronized steering output buffer. The buffer load take effect until the first period event after the occurs even if the PxSSYNC bit is low. When the PSMCxLD bit is set. PxSSYNC bit is set, the outputs will immediately go to the drive states in the preloaded buffer. FIGURE 24-18: PWM STEERING WITH SYNCHRONIZATION WAVEFORM Period Number 1 2 3 4 5 6 7 PWM Signal PxSTRA Synchronized PxSTRA PxSTRB Synchronized PxSTRB PSMCxA PSMCxB  2011-2014 Microchip Technology Inc. DS40001579E-page 215

PIC16(L)F1782/3 24.6 PSMC Modulation (Burst Mode) 24.6.2.1 PxMDLBIT Bit PSMC modulation is a method to stop/start PWM The PxMDLBIT bit of the PSMC Modulation Control operation of the PSMC without having to disable the (PSMCxMDL) register (Register24-2) allows for module. It also allows other modules to control the software modulation control without having to operational period of the PSMC. This is also referred enable/disable other module functions. to as Burst mode. 24.6.3 MODULATION EFFECT ON PWM This is a method to implement PWM dimming. SIGNALS 24.6.1 MODULATION ENABLE When modulation starts, the PSMC begins operation on a new period, just as if it had rolled over from one The modulation function is enabled by setting the period to another during continuous operation. PxMDLEN bit of PSMC Modulation Control (PSMCxMDL) register (Register24-2). When modulation stops, its operation depends on the type of waveform being generated. When modulation is enabled, the modulation source controls when the PWM signals are active and In operation modes other than Fixed Duty Cycle, the inactive. PSMC completes its current PWM period and then freezes the module. The PSMC output pins are forced When modulation is disabled, the PWM signals into the default inactive state ready for use when operate continuously, regardless of the selected modulation starts. modulation source. In Fixed Duty Cycle mode operation, the PSMC 24.6.2 MODULATION SOURCES continues to operate until the period event changes the PWM to its inactive state, at which point the PSMC There are multiple sources that can be used for module is frozen. The PSMC output pins are forced modulating the PSMC. However, unlike the PSMC into the default inactive state ready for use when input sources, only one modulation source can be modulation starts. selected at a time. Modulation sources include: • PSMCxIN pin • Any CCP output • Any Comparator output • PxMDLBIT of the PSMCxMDL register FIGURE 24-19: PSMC MODULATION WAVEFORM 1 2 3 4 5 6 7 1 1 2 3 4 5 Modulation Input PPWWMM OOffff PPWWMM OOffff PPWWMM Off PWM Period DS40001579E-page 216  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.7 Auto-Shutdown 24.7.2 PIN OVERRIDE LEVELS Auto-shutdown is a method to immediately override The logic levels driven to the output pins during an the PSMC output levels with specific overrides that auto-shutdown event are determined by the PSMC allow for safe shutdown of the application. Auto-shutdown Output Level (PSMCxASDL) register (Register24-15). Auto-shutdown includes a mechanism to allow the application to restart under different conditions. 24.7.2.1 PIN Override Enable Auto-shutdown is enabled with the PxASDEN bit of the Setting the PxASDOV bit of the PSMC Auto-shutdown PSMC Auto-shutdown Control (PSMCxASDC) register Control (PSMCxASDC) register (Register24-14) will (Register24-14). All auto-shutdown features are also force the override levels onto the pins, exactly like enabled when PxASDEN is set and disabled when what happens when the auto-shutdown is used. cleared. However, whereas setting PxASE causes an auto-shutdown interrupt, setting PxASDOV does not 24.7.1 SHUTDOWN generate an interrupt. There are two ways to generate a shutdown event: 24.7.3 RESTART FROM • Manual AUTO-SHUTDOWN • External Input After an auto-shutdown event has occurred, there are 24.7.1.1 Manual Override two ways for the module to resume operation: The auto-shutdown control register can be used to • Manual restart manually override the pin functions. Setting the PxASE • Automatic restart bit of the PSMC Auto-shutdown Control (PSMCxASDC) The restart method is selected with the PxARSEN bit of register (Register24-14) generates a software the PSMC Auto-shutdown Control (PSMCxASDC) shut-down event. register (Register24-14). The auto-shutdown override will persist as long as PxASE remains set. 24.7.3.1 Manual Restart When PxARSEN is cleared, and once the PxASDE bit 24.7.1.2 External Input Source is set, it will remain set until cleared by software. Any of the given sources that are available for event The PSMC will restart on the period event after generation are also available for system shut-down. PxASDE bit is cleared in software. This is so that external circuitry can monitor and force a shutdown without any software overhead. 24.7.3.2 Auto-Restart Auto-shutdown sources are selected with the PSMC When PxARSEN is set, the PxASDE bit will clear Auto-shutdown Source (PSMCxASDS) register automatically when the source causing the Reset and (Register24-16). no longer asserts the shut-down condition. When any of the selected external auto-shutdown The PSMC will restart on the next period event after sources go high, the PxASE bit is set and an the auto-shutdown condition is removed. auto-shutdown interrupt is generated. Examples of manual and automatic restart are shown in Figure24-20. Note: The external shutdown sources are level sensitive, not edge sensitive. The shutdown condition will persist as long as the circuit is Note: Whether manual or auto-restart is selected, driving the appropriate logic level. the PxASDE bit cannot be cleared in software when the auto-shutdown condition is still present.  2011-2014 Microchip Technology Inc. DS40001579E-page 217

PIC16(L)F1782/3 FIGURE 24-20: AUTO-SHUTDOWN AND RESTART WAVEFORM 1 2 3 4 5 Base PWM signal PxARSEN Next Period Event Auto-Shutdown Source cleared cleared PSMCx Auto-shutdown int flag bit in software in software Cleared Next Period Event in hardware PxASE Cleared in software PSMCxA PSMCxB Operating State Normal Auto- Normal Auto- Normal Output shutdown Output shutdown Output Manual Restart Auto-restart DS40001579E-page 218  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.8 PSMC Synchronization It is possible to synchronize the periods of two or more PSMC modules together, provided that all modules are on the same device. Synchronization is achieved by sending a sync signal from the master PSMC module to the desired slave modules. This sync signal generates a period event in each slave module, thereby aligning all slaves with the master. This is useful when an application requires different PWM signal generation from each module but the waveforms must be consistent within a PWM period. 24.8.1 SYNCHRONIZATION SOURCES The synchronization source can be any PSMC module on the same device. For example, in a device with two PSMC modules, the possible sources for each device is as shown below: • Sources for PSMC1 - PSMC2 • Sources for PSMC2 - PSMC1 24.8.1.1 PSMC Internal Connections The sync signal from the master PSMC module is essentially that modules period event trigger. The slave PSMC modules reset their PSMCxTMR with the sync signal instead of their own period event. Enabling a module as a slave recipient is done with the PxSYNC bits of the PSMC Synchronization Control (PSMCxSYNC) registers; registers24-3 and24-4. 24.8.1.2 Synchronization Skid When the sync_out source is the Period Event, the slave synchronous rising and falling events will lag by one psmc_clk period. When the sync_out source is the Rising Event, the synchronous events will lag by two clock periods. To compensate for this, the values in PHH:PHL and DCH:DCL registers can be reduced by the number of lag cycles.  2011-2014 Microchip Technology Inc. DS40001579E-page 219

PIC16(L)F1782/3 24.9 Fractional Frequency Adjust (FFA) psmc_clk period (TPSMC_CLK) every N events, then the effective resolution of the average event period is FFA is a method by which PWM resolution can be TPSMC_CLK/N. improved on 50% fixed duty cycle signals. Higher When active, after every period event the FFA resolution is achieved by altering the PWM period by a hardware adds the PSMCxFFA value with the single count for calculated intervals. This increased previously accumulated result. Each time the addition resolution is based upon the PWM frequency causes an overflow, the period event time is increased averaged over a large number of PWM periods. For by one. Refer to Figure24-21. example, if the period event time is increased by one FIGURE 24-21: FFA BLOCK DIAGRAM. PSMCxFFA<3:0> PSMCxPR<15:0>   carry Accumulator<3:0> Comparator = Period Event psmc_clk PSMCxTMR<15:0> The FFA function is only available when using one of TABLE 24-3: FRACTIONAL FREQUENCY the two Fixed Duty Cycle modes of operation. In fixed ADJUST CALCULATIONS duty cycle operation each PWM period is comprised of Parameter Value two period events. That is why the PWM periods in Table24-3 example calculations are multiplied by two FPSMC_CLK 64 MHz as opposed to the normal period calculations for TPSMC_CLK 15.625 ns normal mode operation. PSMCxPR<15:0> 00FFh = 255 The extra resolution gained by the FFA is based upon TPWM = (PSMCxPR<15:0>+1)*2*TPSMC_CLK = 256*2*15.625ns the number of bits in the FFA register and the psmc_- = 8 us clk frequency. The parameters of interest are: FPWM 125 kHz • TPWM – this is the lower bound of the PWM period TPWM+1 = (PSMCxPR<15:0>+2)*2*TPSMC_CLK that will be adjusted = 257*2*15.625ns • TPWM+1 – this is the upper bound of the PWM = 8.03125 us period that will be adjusted. This is used to help FPWM+1 = 124.513 kHz determine the step size for each increment of the TRESOLUTION = (TPWM+1-TPWM)/2FFA-Bits FFA register = (8.03125us - 8.0 us)/16 • TRESOLUTION – each increment of the FFA = 0.03125us/16 register will add this amount of period to average ~ 1.95 ns PWM frequency FRESOLUTION (FPWM+1-FPWM)/2FFA-Bits ~ -30.4 Hz DS40001579E-page 220  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 24-4: SAMPLE FFA OUTPUT PERIODS/FREQUENCIES FFA number Output Frequency (kHz) Step Size (Hz) 0 125.000 0 1 124.970 -30.4 2 124.939 -60.8 3 124.909 -91.2 4 124.878 -121.6 5 124.848 -152.0 6 124.818 -182.4 7 124.787 -212.8 8 124.757 -243.2 9 124.726 -273.6 10 124.696 -304.0 11 124.666 -334.4 12 124.635 -364.8 13 124.605 -395.2 14 124.574 -425.6 15 124.544 -456.0  2011-2014 Microchip Technology Inc. DS40001579E-page 221

PIC16(L)F1782/3 24.10 Register Updates 24.11 Operation During Sleep There are 10 double-buffered registers that can be The PSMC continues to operate in Sleep with the updated “on the fly”. However, due to the following clock sources: asynchronous nature of the potential updates, a • Internal 64 MHz special hardware system is used for the updates. • External clock There are two operating cases for the PSMC: • module is enabled • module is disabled 24.10.1 DOUBLE BUFFERED REGISTERS The double-buffered registers that are affected by the special hardware update system are: • PSMCxPRL • PSMCxPRH • PSMCxDCL • PSMCxDCH • PSMCxPHL • PSMCxPHH • PSMCxDBR • PSMCxDBF • PSMCxBLKR • PSMCxBLKF • PSMCxSTR0 (when the PxSSYNC bit is set) 24.10.2 MODULE DISABLED UPDATES When the PSMC module is disabled (PSMCxEN=0), any write to one of the buffered registers will also write directly to the buffer. This means that all buffers are loaded and ready for use when the module is enabled. 24.10.3 MODULE ENABLED UPDATES When the PSMC module is enabled (PSMCxEN=1), the PSMCxLD bit of the PSMC Control (PSMCxCON) register (Register24-1) must be used. When the PSMCxLD bit is set, the transfer from the register to the buffer occurs on the next period event. The PSMCxLD bit is automatically cleared by hardware after the transfer to the buffers is complete. The reason that the PSMCxLD bit is required is that depending on the customer application and operation conditions, all 10 registers may not be updated in one PSMC period. If the buffers are loaded at different times (i.e., DCL gets updated, but DCH does not OR DCL and DCL are updated by PRH and PRL are not), then unintended operation may occur. The sequence for loading the buffer registers when the PSMC module is enabled is as follows: 1. Software updates all registers. 2. Software sets the PSMCxLD bit. 3. Hardware updates all buffers on the next period event. 4. Hardware clears PSMCxLD bit. DS40001579E-page 222  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 24.12 Register Definitions: PSMC Control REGISTER 24-1: PSMCxCON: PSMC CONTROL REGISTER R/W-0/0 R/W/HC-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxEN PSMCxLD PxDBFE PxDBRE PxMODE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PSMCxEN: PSMC Module Enable bit 1 = PSMCx module is enabled 0 = PSMCx module is disabled bit 6 PSMCxLD: PSMC Load Buffer Enable bit 1 = PSMCx registers are ready to be updated with the appropriate register contents 0 = PSMCx buffer update complete bit 5 PxDBFE: PSMC Falling Edge Dead-Band Enable bit 1 = PSMCx falling edge dead band enabled 0 = PSMCx falling edge dead band disabled bit 4 PxDBRE: PSMC Rising Edge Dead-Band Enable bit 1 = PSMCx rising edge dead band enabled 0 = PSMCx rising edge dead band disabled bit 3-0 PxMODE<3:0> PSMC Operating Mode bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = 3-phase steering PWM 1011 = Fixed duty cycle, variable frequency, complementary PWM 1010 = Fixed duty cycle, variable frequency, single PWM 1001 = ECCP compatible Full-Bridge forward output 1000 = ECCP compatible Full-Bridge reverse output 0111 = Pulse-skipping with complementary output 0110 = Pulse-skipping PWM output 0101 = Push-pull with four full-bridge outputs and complementary outputs 0100 = Push-pull with four full-bridge outputs 0011 = Push-pull with complementary outputs 0010 = Push-pull output 0001 = Single PWM with complementary output (with PWM steering capability) 0000 = Single PWM waveform generation (with PWM steering capability)  2011-2014 Microchip Technology Inc. DS40001579E-page 223

PIC16(L)F1782/3 REGISTER 24-2: PSMCxMDL: PSMC MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxMDLEN PxMDLPOL PxMDLBIT — PxMSRC<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxMDLEN: PSMC Periodic Modulation Mode Enable bit 1 = PSMCx is active when input signal selected by PxMSRC<3:0> is in its active state (see PxMPOL) 0 = PSMCx module is always active bit 6 PxMDLPOL: PSMC Periodic Modulation Polarity bit 1 = PSMCx is active when the PSMCx Modulation source output equals logic ‘0’ (active-low) 0 = PSMCx is active when the PSMCx Modulation source output equals logic ‘1’ (active-high) bit 5 PxMDLBIT: PSMC Periodic Modulation Software Control bit PxMDLEN = 1 AND PxMSRC<3:0> = 0000 1 = PSMCx is active when the PxMDLPOL equals logic ‘0’ 0 = PSMCx is active when the PxMDLPOL equals logic ‘1’ PxMDLEN = 0 OR (PxMDLEN = 1 and PxMSRC<3:0> <> ‘0000’) Does not affect module operation bit 4 Unimplemented: Read as ‘0’ bit 3-0 PxMSRC<3:0> PSMC Periodic Modulation Source Selection bits 1111 =Reserved 1110 =Reserved 1101 =Reserved 1100 =Reserved 1011 =Reserved 1010 =Reserved 1001 =Reserved 1000 =PSMCx Modulation Source is PSMCxIN pin 0111 =Reserved 0110 =PSMCx Modulation Source is CCP2 0101 =PSMCx Modulation Source is CCP1 0100 =Reserved 0011 =PSMCx Modulation Source is sync_C3OUT 0010 =PSMCx Modulation Source is sync_C2OUT 0001 =PSMCx Modulation Source is sync_C1OUT 0000 =PSMCx Modulation Source is PxMDLBIT register bit DS40001579E-page 224  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 24-3: PSMC1SYNC: PSMC1 SYNCHRONIZATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — P1SYNC<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 P1SYNC<1:0>: PSMC1 Period Synchronization Mode bits 11 = Reserved – Do not use 10 = PSMC1 is synchronized with the PSMC2 module 01 = Reserved – Do not use 00 = PSMC1 is synchronized with period event REGISTER 24-4: PSMC2SYNC: PSMC2 SYNCHRONIZATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — P2SYNC<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 P2SYNC<1:0>: PSMC2 Period Synchronization Mode bits 11 = Reserved – Do not use 10 = Reserved – Do not use 01 = PSMC2 is synchronized with the PSMC1 module 00 = PSMC2 is synchronized with period event  2011-2014 Microchip Technology Inc. DS40001579E-page 225

PIC16(L)F1782/3 REGISTER 24-5: PSMCxCLK: PSMC CLOCK CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — — PxCPRE<1:0> — — PxCSRC<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 PxCPRE<1:0>: PSMCx Clock Prescaler Selection bits 11 = PSMCx Clock frequency/8 10 = PSMCx Clock frequency/4 01 = PSMCx Clock frequency/2 00 = PSMCx Clock frequency/1 bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 PxCSRC<1:0>: PSMCx Clock Source Selection bits 11 = Reserved 10 = PSMCxCLK pin 01 = 64 MHz clock in from PLL 00 = FOSC system clock REGISTER 24-6: PSMCxOEN: PSMC OUTPUT ENABLE CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — PxOEF(1) PxOEE(1) PxOED(1) PxOEC(1) PxOEB PxOEA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PxOEy: PSMCx Output y Enable bit(1) 1 = PWM output is active on PSMCx output y pin 0 = PWM output is not active, normal port functions in control of pin Note 1: These bits are not implemented on PSMC2. DS40001579E-page 226  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 24-7: PSMCxPOL: PSMC POLARITY CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — PxPOLIN PxPOLF(1) PxPOLE(1) PxPOLD(1) PxPOLC(1) PxPOLB PxPOLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 PxPOLIN: PSMCxIN Polarity bit 1 = PSMCxIN input is active-low 0 = PSMCxIN input is active-high bit 5-0 PxPOLy: PSMCx Output y Polarity bit(1) 1 = PWM PSMCx output y is active-low 0 = PWM PSMCx output y is active-high Note 1: These bits are not implemented on PSMC2. REGISTER 24-8: PSMCxBLNK: PSMC BLANKING CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — — PxFEBM1 PxFEBM0 — — PxREBM1 PxREBM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 PxFEBM<1:0> PSMC Falling Edge Blanking Mode bits 11 = Reserved – do not use 10 = Reserved – do not use 01 = Immediate blanking 00 = No blanking bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 PxREBM<1:0> PSMC Rising Edge Blanking Mode bits 11 = Reserved – do not use 10 = Reserved – do not use 01 = Immediate blanking 00 = No blanking  2011-2014 Microchip Technology Inc. DS40001579E-page 227

PIC16(L)F1782/3 REGISTER 24-9: PSMCxREBS: PSMC RISING EDGE BLANKED SOURCE REGISTER R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 PxREBSIN — — — PxREBSC3 PxREBSC2 PxREBSC1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxREBSIN: PSMCx Rising Edge Event Blanked from PSMCxIN pin 1 = PSMCxIN pin cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = PSMCxIN pin is not blanked bit 6-4 Unimplemented: Read as ‘0’ bit 3 PxREBSC3: PSMCx Rising Edge Event Blanked from sync_C3OUT 1 = sync_C3OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C3OUT is not blanked bit 2 PxREBSC2: PSMCx Rising Edge Event Blanked from sync_C2OUT 1 = sync_C2OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C2OUT is not blanked bit 1 PxREBSC1: PSMCx Rising Edge Event Blanked from sync_C1OUT 1 = sync_C1OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C1OUT is not blanked bit 0 Unimplemented: Read as ‘0’ REGISTER 24-10: PSMCxFEBS: PSMC FALLING EDGE BLANKED SOURCE REGISTER R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 PxFEBSIN — — — PxFEBSC3 PxFEBSC2 PxFEBSC1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxFEBSIN: PSMCx Falling Edge Event Blanked from PSMCxIN pin 1 = PSMCxIN pin cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = PSMCxIN pin is not blanked bit 6-4 Unimplemented: Read as ‘0’ bit 3 PxFEBSC3: PSMCx Falling Edge Event Blanked from sync_C3OUT 1 = sync_C3OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C3OUT is not blanked bit 2 PxFEBSC2: PSMCx Falling Edge Event Blanked from sync_C2OUT 1 = sync_C2OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C2OUT is not blanked bit 1 PxFEBSC1: PSMCx Falling Edge Event Blanked from sync_C1OUT 1 = sync_C1OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C1OUT is not blanked bit 0 Unimplemented: Read as ‘0’ DS40001579E-page 228  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 24-11: PSMCxPHS: PSMC PHASE SOURCE REGISTER(1) R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxPHSIN — — — PxPHSC3 PxPHSC2 PxPHSC1 PxPHST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxPHSIN: PSMCx Rising Edge Event occurs on PSMCxIN pin 1 = Rising edge event will occur when PSMCxIN pin goes true 0 = PSMCxIN pin will not cause rising edge event bit 6-4 Unimplemented: Read as ‘0’ bit 3 PxPHSC3: PSMCx Rising Edge Event occurs on sync_C3OUT output 1 = Rising edge event will occur when sync_C3OUT output goes true 0 = sync_C3OUT will not cause rising edge event bit 2 PxPHSC2: PSMCx Rising Edge Event occurs on sync_C2OUT output 1 = Rising edge event will occur when sync_C2OUT output goes true 0 = sync_C2OUT will not cause rising edge event bit 1 PxPHSC1: PSMCx Rising Edge Event occurs on sync_C1OUT output 1 = Rising edge event will occur when sync_C1OUT output goes true 0 = sync_C1OUT will not cause rising edge event bit 0 PxPHST: PSMCx Rising Edge Event occurs on Time Base match 1 = Rising edge event will occur when PSMCxTMR = PSMCxPH 0 = Time base will not cause rising edge event Note 1: Sources are not mutually exclusive: more than one source can cause a rising edge event.  2011-2014 Microchip Technology Inc. DS40001579E-page 229

PIC16(L)F1782/3 REGISTER 24-12: PSMCxDCS: PSMC DUTY CYCLE SOURCE REGISTER(1) R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxDCSIN — — — PxDCSC3 PxDCSC2 PxDCSC1 PxDCST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxDCSIN: PSMCx Falling Edge Event occurs on PSMCxIN pin 1 = Falling edge event will occur when PSMCxIN pin goes true 0 = PSMCxIN pin will not cause falling edge event bit 6-4 Unimplemented: Read as ‘0’ bit 3 PxDCSC3: PSMCx Falling Edge Event occurs on sync_C3OUT output 1 = Falling edge event will occur when sync_C3OUT output goes true 0 = sync_C3OUT will not cause falling edge event bit 2 PxDCSC2: PSMCx Falling Edge Event occurs on sync_C2OUT output 1 = Falling edge event will occur when sync_C2OUT output goes true 0 = sync_C2OUT will not cause falling edge event bit 1 PxDCSC1: PSMCx Falling Edge Event occurs on sync_C1OUT output 1 = Falling edge event will occur when sync_C1OUT output goes true 0 = sync_C1OUT will not cause falling edge event bit 0 PxDCST: PSMCx Falling Edge Event occurs on Time Base match 1 = Falling edge event will occur when PSMCxTMR = PSMCxDC 0 = Time base will not cause falling edge event Note 1: Sources are not mutually exclusive: more than one source can cause a falling edge event. DS40001579E-page 230  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 24-13: PSMCxPRS: PSMC PERIOD SOURCE REGISTER(1) R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxPRSIN — — — PxPRSC3 PxPRSC2 PxPRSC1 PxPRST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxPRSIN: PSMCx Period Event occurs on PSMCxIN pin 1 = Period event will occur and PSMCxTMR will reset when PSMCxIN pin goes true 0 = PSMCxIN pin will not cause period event bit 6-4 Unimplemented: Read as ‘0’ bit 3 PxPRSC3: PSMCx Period Event occurs on sync_C3OUT output 1 = Period event will occur and PSMCxTMR will reset when sync_C3OUT output goes true 0 = sync_C3OUT will not cause period event bit 2 PxPRSC2: PSMCx Period Event occurs on sync_C2OUT output 1 = Period event will occur and PSMCxTMR will reset when sync_C2OUT output goes true 0 = sync_C2OUT will not cause period event bit 1 PxPRSC1: PSMCx Period Event occurs on sync_C1OUT output 1 = Period event will occur and PSMCxTMR will reset when sync_C1OUT output goes true 0 = sync_C1OUT will not cause period event bit 0 PxPRST: PSMCx Period Event occurs on Time Base match 1 = Period event will occur and PSMCxTMR will reset when PSMCxTMR = PSMCxPR 0 = Time base will not cause period event Note 1: Sources are not mutually exclusive: more than one source can force the period event and reset the PSMCxTMR.  2011-2014 Microchip Technology Inc. DS40001579E-page 231

PIC16(L)F1782/3 REGISTER 24-14: PSMCxASDC: PSMC AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 PxASE PxASDEN PxARSEN — — — — PxASDOV bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxASE: PWM Auto-Shutdown Event Status bit(1) 1 = A shutdown event has occurred, PWM outputs are inactive and in their shutdown states 0 = PWM outputs are operating normally bit 6 PxASDEN: PWM Auto-Shutdown Enable bit 1 = Auto-shutdown is enabled. If any of the sources in PSMCxASDS assert a logic ‘1’, then the out- puts will go into their auto-shutdown state and PSMCxSIF flag will be set. 0 = Auto-shutdown is disabled bit 5 PxARSEN: PWM Auto-Restart Enable bit 1 = PWM restarts automatically when the shutdown condition is removed. 0 = The PxASE bit must be cleared in firmware to restart PWM after the auto-shutdown condition is cleared. bit 4-1 Unimplemented: Read as ‘0’ bit 0 PxASDOV: PWM Auto-Shutdown Override bit PxASDEN = 1: 1 = Force PxASDL[n] levels on the PSMCx[n] pins without causing a PSMCxSIF interrupt 0 = Normal PWM and auto-shutdown execution PxASDEN = 0: No effect Note 1: PASE bit may be set in software. When this occurs the functionality is the same as that caused by hardware. DS40001579E-page 232  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 24-15: PSMCxASDL: PSMC AUTO-SHUTDOWN OUTPUT LEVEL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — PxASDLF(1) PxASDLE(1) PxASDLD(1) PxASDLC(1) PxASDLB PxASDLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 PxASDLF: PSMCx Output F Auto-Shutdown Pin Level bit(1) 1 = When auto-shutdown is asserted, pin PSMCxF will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxF will drive logic ‘0’ bit 4 PxASDLE: PSMCx Output E Auto-Shutdown Pin Level bit(1) 1 = When auto-shutdown is asserted, pin PSMCxE will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxE will drive logic ‘0’ bit 3 PxASDLD: PSMCx Output D Auto-Shutdown Pin Level bit(1) 1 = When auto-shutdown is asserted, pin PSMCxD will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxD will drive logic ‘0’ bit 2 PxASDLC: PSMCx Output C Auto-Shutdown Pin Level bit(1) 1 = When auto-shutdown is asserted, pin PSMCxC will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxC will drive logic ‘0’ bit 1 PxASDLB: PSMCx Output B Auto-Shutdown Pin Level bit 1 = When auto-shutdown is asserted, pin PSMCxB will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxB will drive logic ‘0’ bit 0 PxASDLA: PSMCx Output A Auto-Shutdown Pin Level bit 1 = When auto-shutdown is asserted, pin PSMCxA will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxA will drive logic ‘0’ Note 1: These bits are not implemented on PSMC2.  2011-2014 Microchip Technology Inc. DS40001579E-page 233

PIC16(L)F1782/3 REGISTER 24-16: PSMCxASDS: PSMC AUTO-SHUTDOWN SOURCE REGISTER R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 PxASDSIN — — — PxASDSC3 PxASDSC2 PxASDSC1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxASDSIN: Auto-shutdown occurs on PSMCxIN pin 1 = Auto-shutdown will occur when PSMCxIN pin goes true 0 = PSMCxIN pin will not cause auto-shutdown bit 6-4 Unimplemented: Read as ‘0’ bit 3 PxASDSC3: Auto-shutdown occurs on sync_C3OUT output 1 = Auto-shutdown will occur when sync_C3OUT output goes true 0 = sync_C3OUT will not cause auto-shutdown bit 2 PxASDSC2: Auto-shutdown occurs on sync_C2OUT output 1 = Auto-shutdown will occur when sync_C2OUT output goes true 0 = sync_C2OUT will not cause auto-shutdown bit 1 PxASDSC1: Auto-shutdown occurs on sync_C1OUT output 1 = Auto-shutdown will occur when sync_C1OU output goes true 0 = sync_C1OU will not cause auto-shutdown bit 0 Unimplemented: Read as ‘0’ DS40001579E-page 234  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 24-17: PSMCxTMRL: PSMC TIME BASE COUNTER LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxTMRL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxTMRL<7:0>: 16-bit PSMCx Time Base Counter Least Significant bits = PSMCxTMR<7:0> REGISTER 24-18: PSMCxTMRH: PSMC TIME BASE COUNTER HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 PSMCxTMRH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxTMRH<7:0>: 16-bit PSMCx Time Base Counter Most Significant bits = PSMCxTMR<15:8>  2011-2014 Microchip Technology Inc. DS40001579E-page 235

PIC16(L)F1782/3 REGISTER 24-19: PSMCxPHL: PSMC PHASE COUNT LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxPHL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxPHL<7:0>: 16-bit Phase Count Least Significant bits = PSMCxPH<7:0> REGISTER 24-20: PSMCxPHH: PSMC PHASE COUNT HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxPHH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxPHH<7:0>: 16-bit Phase Count Most Significant bits = PSMCxPH<15:8> DS40001579E-page 236  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 24-21: PSMCxDCL: PSMC DUTY CYCLE COUNT LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxDCL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxDCL<7:0>: 16-bit Duty Cycle Count Least Significant bits = PSMCxDC<7:0> REGISTER 24-22: PSMCxDCH: PSMC DUTY CYCLE COUNT HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxDCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxDCH<7:0>: 16-bit Duty Cycle Count Most Significant bits = PSMCxDC<15:8>  2011-2014 Microchip Technology Inc. DS40001579E-page 237

PIC16(L)F1782/3 REGISTER 24-23: PSMCxPRL: PSMC PERIOD COUNT LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxPRL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxPRL<7:0>: 16-bit Period Time Least Significant bits = PSMCxPR<7:0> REGISTER 24-24: PSMCxPRH: PSMC PERIOD COUNT HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxPRH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxPRH<7:0>: 16-bit Period Time Most Significant bits = PSMCxPR<15:8> DS40001579E-page 238  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 24-25: PSMCxDBR: PSMC RISING EDGE DEAD-BAND TIME REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxDBR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxDBR<7:0>: Rising Edge Dead-Band Time bits = Unsigned number of PSMCx psmc_clk clock periods in rising edge dead band REGISTER 24-26: PSMCxDBF: PSMC FALLING EDGE DEAD-BAND TIME REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxDBF<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxDBF<7:0>: Falling Edge Dead-Band Time bits = Unsigned number of PSMCx psmc_clk clock periods in falling edge dead band REGISTER 24-27: PSMCxFFA: PSMC FRACTIONAL FREQUENCY ADJUST REGISTER U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — PSMCxFFA<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 PSMCxFFA<3:0>: Fractional Frequency Adjustment bits = Unsigned number of fractional PSMCx psmc_clk clock periods to add to each period event time. The fractional time period = 1/(16*psmc_clk)  2011-2014 Microchip Technology Inc. DS40001579E-page 239

PIC16(L)F1782/3 REGISTER 24-28: PSMCxBLKR: PSMC RISING EDGE BLANKING TIME REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxBLKR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxBLKR<7:0>: Rising Edge Blanking Time bits = Unsigned number of PSMCx psmc_clk clock periods in rising edge blanking REGISTER 24-29: PSMCxBLKF: PSMC FALLING EDGE BLANKING TIME REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxBLKF<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxBLKF<7:0>: Falling Edge Blanking Time bits = Unsigned number of PSMCx psmc_clk clock periods in falling edge blanking DS40001579E-page 240  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 24-30: PSMCxSTR0: PSMC STEERING CONTROL REGISTER 0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 — — PxSTRF(2) PxSTRE(2) PxSTRD(2) PxSTRC(2) PxSTRB PxSTRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 PxSTRF: PWM Steering PSMCxF Output Enable bit(2) If PxMODE<3:0> =0000 (Single-phase PWM): 1 = Single PWM output is active on pin PSMCxF 0 = Single PWM output is not active on pin PSMCxF. PWM drive is in inactive state If PxMODE<3:0> =0001 (Complementary Single-phase PWM): 1 = Complementary PWM output is active on pin PSMCxF 0 = Complementary PWM output is not active on pin PSMCxOUT5. PWM drive is in inactive state IF PxMODE<3:0> =1100 (3-phase Steering):(1) 1 = PSMCxD and PSMCxE are high. PSMCxA, PMSCxB, PSMCxC and PMSCxF are low. 0 = 3-phase output combination is not active bit 4 PxSTRE: PWM Steering PSMCxE Output Enable bit(2) If PxMODE<3:0> =000x (single-phase PWM or Complementary PWM): 1 = Single PWM output is active on pin PSMCxE 0 = Single PWM output is not active on pin PSMCxE. PWM drive is in inactive state IF PxMODE<3:0> =1100 (3-phase Steering):(1) 1 = PSMCxB and PSMCxE are high. PSMCxA, PMSCxC, PSMCxD and PMSCxF are low. 0 = 3-phase output combination is not active bit 3 PxSTRD: PWM Steering PSMCxD Output Enable bit(2) If PxMODE<3:0> =0000 (Single-phase PWM): 1 = Single PWM output is active on pin PSMCxD 0 = Single PWM output is not active on pin PSMCxD. PWM drive is in inactive state If PxMODE<3:0> =0001 (Complementary single-phase PWM): 1 = Complementary PWM output is active on pin PSMCxD 0 = Complementary PWM output is not active on pin PSMCxD. PWM drive is in inactive state IF PxMODE<3:0> =1100 (3-phase Steering):(1) 1 = PSMCxB and PSMCxC are high. PSMCxA, PMSCxD, PSMCxE and PMSCxF are low. 0 = 3-phase output combination is not active bit 2 PxSTRC: PWM Steering PSMCxC Output Enable bit(2) If PxMODE<3:0> =000x (Single-phase PWM or Complementary PWM): 1 = Single PWM output is active on pin PSMCxC 0 = Single PWM output is not active on pin PSMCxC. PWM drive is in inactive state IF PxMODE<3:0> =1100 (3-phase Steering):(1) 1 = PSMCxC and PSMCxF are high. PSMCxA, PMSCxB, PSMCxD and PMSCxE are low. 0 = 3-phase output combination is not active  2011-2014 Microchip Technology Inc. DS40001579E-page 241

PIC16(L)F1782/3 REGISTER 24-30: PSMCxSTR0: PSMC STEERING CONTROL REGISTER 0 bit 1 PxSTRB: PWM Steering PSMCxB Output Enable bit If PxMODE<3:0> =0000 (Single-phase PWM): 1 = Single PWM output is active on pin PSMCxOUT1 0 = Single PWM output is not active on pin PSMCxOUT1. PWM drive is in inactive state If PxMODE<3:0> =0001 (Complementary Single-phase PWM): 1 = Complementary PWM output is active on pin PSMCxB 0 = Complementary PWM output is not active on pin PSMCxB. PWM drive is in inactive state IF PxMODE<3:0> =1100 (3-phase Steering):(1) 1 = PSMCxA and PSMCxF are high. PSMCxB, PMSCxC, PSMCxD and PMSCxE are low. 0 = 3-phase output combination is not active bit 0 PxSTRA: PWM Steering PSMCxA Output Enable bit If PxMODE<3:0> =000x (Single-phase PWM or Complementary PWM): 1 = Single PWM output is active on pin PSMCxA 0 = Single PWM output is not active on pin PSMCxA. PWM drive is in inactive state IF PxMODE<3:0> =1100 (3-phase Steering):(1) 1 = PSMCxA and PSMCxD are high. PSMCxB, PMSCxC, PSMCxE and PMSCxF are low. 0 = 3-phase output combination is not active Note 1: In 3-phase Steering mode, only one PSTRx bit should be set at a time. If more than one is set, then the lowest bit number steering combination has precedence. 2: These bits are not implemented on PSMC2. DS40001579E-page 242  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 24-31: PSMCxSTR1: PSMC STEERING CONTROL REGISTER 1 R/W-0/0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 PxSSYNC — — — — — PxLSMEN PxHSMEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxSSYNC: PWM Steering Synchronization bit 1 = PWM outputs are updated on period boundary 0 = PWM outputs are updated immediately bit 6-2 Unimplemented: Read as ‘0’ bit 1 PxLSMEN: 3-Phase Steering Low Side Modulation Enable bit PxMODE =1100: 1 = Low side driver PSMCxB, PSMCxD and PSMCxF outputs are modulated according to PSMCxMDL when the output is high and driven low without modulation when the output is low. 0 = PSMCxB, PSMCxD, and PSMCxF outputs are driven high and low by PSMCxSTR0 control without modulation. PxMODE <>1100: No effect on output bit 0 PxHSMEN: 3-Phase Steering High Side Modulation Enable bit PxMODE =1100: 1 = High side driver PSMCxA, PSMCxC and PSMCxE outputs are modulated according to PSMCxMDL when the output is high and driven low without modulation when the output is low. 0 = PSMCxA, PSMCxC and PSMCxE outputs are driven high and low by PSMCxSTR0 control without modulation. PxMODE <>1100: No effect on output  2011-2014 Microchip Technology Inc. DS40001579E-page 243

PIC16(L)F1782/3 REGISTER 24-32: PSMCxINT: PSMC TIME BASE INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxTOVIE PxTPHIE PxTDCIE PxTPRIE PxTOVIF PxTPHIF PxTDCIF PxTPRIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxTOVIE: PSMC Time Base Counter Overflow Interrupt Enable bit 1 = Time base counter overflow interrupts are enabled 0 = Time base counter overflow interrupts are disabled bit 6 PxTPHIE: PSMC Time Base Phase Interrupt Enable bit 1 = Time base phase match interrupts are enabled 0 = Time base phase match interrupts are disabled bit 5 PxTDCIE: PSMC Time Base Duty Cycle Interrupt Enable bit 1 = Time base duty cycle match interrupts are enabled 0 = Time base duty cycle match interrupts are disabled bit 4 PxTPRIE: PSMC Time Base Period Interrupt Enable bit 1 = Time base period match interrupts are enabled 0 = Time base period match Interrupts are disabled bit 3 PxTOVIF: PSMC Time Base Counter Overflow Interrupt Flag bit 1 = The 16-bit PSMCxTMR has overflowed from FFFFh to 0000h 0 = The 16-bit PSMCxTMR counter has not overflowed bit 2 PxTPHIF: PSMC Time Base Phase Interrupt Flag bit 1 = The 16-bit PSMCxTMR counter has matched PSMCxPH<15:0> 0 = The 16-bit PSMCxTMR counter has not matched PSMCxPH<15:0> bit 1 PxTDCIF: PSMC Time Base Duty Cycle Interrupt Flag bit 1 = The 16-bit PSMCxTMR counter has matched PSMCxDC<15:0> 0 = The 16-bit PSMCxTMR counter has not matched PSMCxDC<15:0> bit 0 PxTPRIF: PSMC Time Base Period Interrupt Flag bit 1 = The 16-bit PSMCxTMR counter has matched PSMCxPR<15:0> 0 = The 16-bit PSMCxTMR counter has not matched PSMCxPR<15:0> DS40001579E-page 244  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 24-5: SUMMARY OF REGISTERS ASSOCIATED WITH PSMC Register Name Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 ODCONC ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 126 PIE4 — — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC1SIE 82 PIR4 — — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF 85 PSMCxASDC PxASE PxASDEN PxARSEN — — — — PxASDOV 232 PSMCxASDL — — PxASDLF(1) PxASDLE(1) PxASDLD(1) PxASDLC(1) PxASDLB PxASDLA 233 PSMCxASDS PxASDSIN — — — PxASDSC3 PxASDSC2 PxASDSC1 — 234 PSMCxBLKF PSMCxBLKF<7:0> 240 PSMCxBLKR PSMCxBLKR<7:0> 240 PSMCxBLNK — — PxFEBM1 PxFEBM0 — — PxREBM1 PxREBM0 227 PSMCxCLK — — PxCPRE<1:0> — — PxCSRC<1:0> 226 PSMCxCON PSMCxEN PSMCxLD PxDBFE PxDBRE PxMODE<3:0> 223 PSMCxDBF PSMCxDBF<7:0> 239 PSMCxDBR PSMCxDBR<7:0> 239 PSMCxDCH PSMCxDC<15:8> 237 PSMCxDCL PSMCxDC<7:0> 237 PSMCxDCS PxDCSIN — — — PxDCSC3 PxDCSC2 PxDCSC1 PxDCST 230 PSMCxFEBS PxFEBSIN — — — PxFEBSC3 PxFEBSC2 PxFEBSC1 — 228 PSMCxFFA — — — — PSMCxFFA<3:0> 239 PSMCxINT PxTOVIE PxTPHIE PxTDCIE PxTPRIE PxTOVIF PxTPHIF PxTDCIF PxTPRIF 244 PSMCxMDL PxMDLEN PxMDLPOL PxMDLBIT — PxMSRC<3:0> 224 PSMCxOEN — — PxOEF(1) PxOEE(1) PxOED(1) PxOEC(1) PxOEB PxOEA 226 PSMCxPHH PSMCxPH<15:8> 236 PSMCxPHL PSMCxPH<7:0> 236 PSMCxPHS PxPHSIN — — — PxPHSC3 PxPHSC2 PxPHSC1 PxPHST 229 PSMCxPOL — PxPOLIN PxPOLF(1) PxPOLE(1) PxPOLD(1) PxPOLC(1) PxPOLB PxPOLA 227 PSMCxPRH PSMCxPR<15:8> 238 PSMCxPRL PSMCxPR<7:0> 238 PSMCxPRS PxPRSIN — — — PxPRSC3 PxPRSC2 PxPRSC1 PxPRST 231 PSMCxREBS PxREBSIN — — — PxREBSC3 PxREBSC2 PxREBSC1 — 228 PSMCxSTR0 — — PxSTRF(1) PxSTRE(1) PxSTRD(1) PxSTRC(1) PxSTRB PxSTRA 241 PSMCxSTR1 PxSSYNC — — — — — PxLSMEN PxHSMEN 243 PSMCxSYNC — — — — — — PxSYNC<1:0> 225 PSMCxTMRH PSMCxTMR<15:8> 235 PSMCxTMRL PSMCxTMR<7:0> 235 SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLCR2 SRC1 SLRC0 126 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PSMC module. Note 1: Unimplemented in PSMC2.  2011-2014 Microchip Technology Inc. DS40001579E-page 245

PIC16(L)F1782/3 25.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral that allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains two standard Capture/Compare/PWM modules (CCP1 and CCP2). The Capture and Compare functions are identical for all CCP modules. Note1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required. DS40001579E-page 246  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 25.1 Capture Mode 25.1.2 TIMER1 MODE RESOURCE The Capture mode function described in this section is Timer1 must be running in Timer mode or Synchronized available and identical for all CCP modules. Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture Capture mode makes use of the 16-bit Timer1 operation may not work. resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and See Section22.0 “Timer1 Module with Gate stores the 16-bit value of the TMR1H:TMR1L register Control” for more information on configuring Timer1. pair, respectively. An event is defined as one of the 25.1.3 SOFTWARE INTERRUPT MODE following and is configured by the CCPxM<3:0> bits of the CCPxCON register: When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the • Every falling edge CCPxIE interrupt enable bit of the PIEx register clear to • Every rising edge avoid false interrupts. Additionally, the user should • Every 4th rising edge clear the CCPxIF interrupt flag bit of the PIRx register • Every 16th rising edge following any change in Operating mode. When a capture is made, the Interrupt Request Flag bit Note: Clocking Timer1 from the system clock CCPxIF of the PIRx register is set. The interrupt flag (FOSC) should not be used in Capture must be cleared in software. If another capture occurs mode. In order for Capture mode to before the value in the CCPRxH, CCPRxL register pair recognize the trigger event on the CCPx is read, the old captured value is overwritten by the new pin, Timer1 must be clocked from the captured value. instruction clock (FOSC/4) or from an Figure25-1 shows a simplified diagram of the capture external clock source. operation. 25.1.4 CCP PRESCALER 25.1.1 CCP PIN CONFIGURATION There are four prescaler settings specified by the In Capture mode, the CCPx pin should be configured CCPxM<3:0> bits of the CCPxCON register. Whenever as an input by setting the associated TRIS control bit. the CCP module is turned off, or the CCP module is not Also, the CCP2 pin function can be moved to in Capture mode, the prescaler counter is cleared. Any alternative pins using the APFCON register. Refer to Reset will clear the prescaler counter. Section13.1 “Alternate Pin Function” for more Switching from one capture prescaler to another does not details. clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by Note: If the CCPx pin is configured as an output, clearing the CCPxCON register before changing the a write to the port can cause a capture prescaler. Equation25-1 demonstrates the code to condition. perform this function. FIGURE 25-1: CAPTURE MODE EXAMPLE 25-1: CHANGING BETWEEN OPERATION BLOCK CAPTURE PRESCALERS DIAGRAM BANKSELCCPxCON ;Set Bank bits to point Set Flag bit CCPxIF ;to CCPxCON (PIRx register) Prescaler CLRF CCPxCON ;Turn CCP module off  1, 4, 16 MOVLW NEW_CAPT_PS;Load the W reg with CCPx CCPRxH CCPRxL ;the new prescaler pin ;move value and CCP ON and Capture MOVWF CCPxCON ;Load CCPxCON with this Edge Detect Enable ;value TMR1H TMR1L CCPxM<3:0> System Clock (FOSC)  2011-2014 Microchip Technology Inc. DS40001579E-page 247

PIC16(L)F1782/3 25.1.5 CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 25.1.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section13.1 “Alternate Pin Function” for more information. DS40001579E-page 248  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 25.2 Compare Mode See Section22.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. The Compare mode function described in this section is available and identical for all CCP modules. Note: Clocking Timer1 from the system clock (FOSC) should not be used in Compare Compare mode makes use of the 16-bit Timer1 mode. In order for Compare mode to resource. The 16-bit value of the CCPRxH:CCPRxL recognize the trigger event on the CCPx register pair is constantly compared against the 16-bit pin, TImer1 must be clocked from the value of the TMR1H:TMR1L register pair. When a instruction clock (FOSC/4) or from an match occurs, one of the following events can occur: external clock source. • Toggle the CCPx output • Set the CCPx output 25.2.3 SOFTWARE INTERRUPT MODE • Clear the CCPx output When Generate Software Interrupt mode is chosen • Generate an Auto-conversion Trigger (CCPxM<3:0>=1010), the CCPx module does not • Generate a Software Interrupt assert control of the CCPx pin (see the CCPxCON register). The action on the pin is based on the value of the CCPxM<3:0> control bits of the CCPxCON register. At 25.2.4 AUTO-CONVERSION TRIGGER the same time, the interrupt flag CCPxIF bit is set. When Auto-conversion Trigger mode is chosen All Compare modes can generate an interrupt. (CCPxM<3:0>=1011), the CCPx module does the Figure25-2 shows a simplified diagram of the compare following: operation. • Resets Timer1 • Starts an ADC conversion if ADC is enabled FIGURE 25-2: COMPARE MODE OPERATION BLOCK The CCPx module does not assert control of the CCPx pin in this mode. DIAGRAM The Auto-conversion Trigger output of the CCP occurs CCPxM<3:0> immediately upon a match between the TMR1H, Mode Select TMR1L register pair and the CCPRxH, CCPRxL register pair. The TMR1H, TMR1L register pair is not Set CCPxIF Interrupt Flag (PIRx) reset until the next rising edge of the Timer1 clock. The CCPx 4 Pin CCPRxH CCPRxL Auto-conversion Trigger output starts an ADC conver- sion (if the ADC module is enabled). This allows the Q S Output Comparator CCPRxH, CCPRxL register pair to effectively provide a Logic Match R 16-bit programmable period register for Timer1. TMR1H TMR1L Refer to Section17.2.5 “Auto-Conversion Trigger” TRIS Output Enable for more information. Auto-conversion Trigger Note1: The Auto-conversion Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. 25.2.1 CCPX PIN CONFIGURATION 2: Removing the match condition by The user must configure the CCPx pin as an output by changing the contents of the CCPRxH clearing the associated TRIS bit. and CCPRxL register pair, between the The CCP2 pin function can be moved to alternate pins clock edge that generates the using the APFCON register (Register13-1). Refer to Auto-conversion Trigger and the clock Section13.1 “Alternate Pin Function” for more edge that generates the Timer1 Reset, details. will preclude the Reset from occurring. Note: Clearing the CCPxCON register will force 25.2.5 COMPARE DURING SLEEP the CCPx compare output latch to the The Compare mode is dependent upon the system default low level. This is not the PORT I/O data latch. clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not 25.2.2 TIMER1 MODE RESOURCE function properly during Sleep. In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode.  2011-2014 Microchip Technology Inc. DS40001579E-page 249

PIC16(L)F1782/3 25.2.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section13.1 “Alternate Pin Function”for more information. DS40001579E-page 250  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 25.3 PWM Overview FIGURE 25-3: CCP PWM OUTPUT SIGNAL Pulse-Width Modulation (PWM) is a scheme that Period provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles Pulse Width a square wave where the high portion of the signal is TMR2 = PR2 considered the on state and the low portion of the signal TMR2 = CCPRxH:CCPxCON<5:4> is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in TMR2 = 0 steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to FIGURE 25-4: SIMPLIFIED PWM BLOCK the load. Lowering the number of steps applied, which DIAGRAM shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete CCP1CON<5:4> cycle or the total amount of on and off time combined. Duty Cycle Registers PWM resolution defines the maximum number of steps CCPR1L that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the To PSMC module load. CCPR1H(2) (Slave) CCP1 The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, Comparator R Q where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher S TMR2 (1) duty cycle corresponds to more power applied. TRIS Figure25-3 shows a typical waveform of the PWM signal. Comparator Clear Timer, toggle CCP1 pin and 25.3.1 STANDARD PWM OPERATION latch duty cycle PR2 The standard PWM function described in this section is Note 1: The 8-bit timer TMR2 register is available and identical for all CCP modules. concatenated with the 2-bit internal system The standard PWM mode generates a Pulse-Width clock (FOSC), or 2 bits of the prescaler, to Modulation (PWM) signal on the CCPx pin with up to 10 create the 10-bit time base. bits of resolution. The period, duty cycle, and resolution 2: In PWM mode, CCPR1H is a read-only are controlled by the following registers: register. • PR2 registers • T2CON registers • CCPRxL registers • CCPxCON registers Figure25-4 shows a simplified block diagram of PWM operation. Note1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 2: Clearing the CCPxCON register will relinquish control of the CCPx pin.  2011-2014 Microchip Technology Inc. DS40001579E-page 251

PIC16(L)F1782/3 25.3.2 SETUP FOR PWM OPERATION 25.3.4 PWM PERIOD The following steps should be taken when configuring The PWM period is specified by the PR2 register of the CCP module for standard PWM operation: Timer2. The PWM period can be calculated using the formula of Equation25-1. 1. Disable the CCPx pin output driver by setting the associated TRIS bit. EQUATION 25-1: PWM PERIOD 2. Load the PR2 register with the PWM period value. PWM Period = PR2+14TOSC 3. Configure the CCP module for the PWM mode (TMR2 Prescale Value) by loading the CCPxCON register with the appropriate values. Note 1: TOSC = 1/FOSC 4. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty When TMR2 is equal to PR2, the following three events cycle value. occur on the next increment cycle: 5. Configure and start Timer2: • TMR2 is cleared • Clear the TMR2IF interrupt flag bit of the • The CCPx pin is set. (Exception: If the PWM duty PIRx register. See Note below. cycle=0%, the pin will not be set.) • Configure the T2CKPS bits of the T2CON • The PWM duty cycle is latched from CCPRxL into register with the Timer prescale value. CCPRxH. • Enable the Timer by setting the TMR2ON bit of the T2CON register. Note: The Timer postscaler (see Section23.1 6. Enable PWM output pin: “Timer2 Operation”) is not used in the • Wait until the Timer overflows and the determination of the PWM frequency. TMR2IF bit of the PIR1 register is set. See Note below. 25.3.5 PWM DUTY CYCLE • Enable the CCPx pin output driver by The PWM duty cycle is specified by writing a 10-bit clearing the associated TRIS bit. value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB<1:0> Note: In order to send a complete duty cycle and bits of the CCPxCON register contain the two LSbs. period on the first PWM output, the above CCPRxL and DCxB<1:0> bits of the CCPxCON steps must be included in the setup register can be written to at any time. The duty cycle sequence. If it is not critical to start with a value is not latched into CCPRxH until after the period complete PWM signal on the first output, completes (i.e., a match between PR2 and TMR2 then step 6 may be ignored. registers occurs). While using the PWM, the CCPRxH register is read-only. 25.3.3 TIMER2 TIMER RESOURCE Equation25-2 is used to calculate the PWM pulse The PWM standard mode makes use of the 8-bit width. Timer2 timer resources to specify the PWM period. Equation25-3 is used to calculate the PWM duty cycle ratio. EQUATION 25-2: PULSE WIDTH Pulse Width = CCPRxL:CCPxCON<5:4>  TOSC  (TMR2 Prescale Value) EQUATION 25-3: DUTY CYCLE RATIO CCPRxL:CCPxCON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------- 4PR2+1 The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. DS40001579E-page 252  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 The 8-bit timer TMR2 register is concatenated with The maximum PWM resolution is 10 bits when PR2 is either the 2-bit internal system clock (FOSC), or 2 bits of 255. The resolution is a function of the PR2 register the prescaler, to create the 10-bit time base. The system value as shown by Equation25-4. clock is used if the Timer2 prescaler is set to 1:1. EQUATION 25-4: PWM RESOLUTION When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure25-4). log4PR2+1 Resolution = ------------------------------------------ bits log2 25.3.6 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution Note: If the pulse width value is greater than the will result in 1024 discrete duty cycles, whereas an 8-bit period the assigned PWM pin(s) will resolution will result in 256 discrete duty cycles. remain unchanged. TABLE 25-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 25-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5  2011-2014 Microchip Technology Inc. DS40001579E-page 253

PIC16(L)F1782/3 25.3.7 OPERATION IN SLEEP MODE In Sleep mode, the TMR2register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 25.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional details. 25.3.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. TABLE 25-3: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 111 CCP1CON — — DC1B<1:0> CCP1M<3:0> 255 CCP2CON — — DC2B<1:0> CCP2M<3:0> 255 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 79 PIE2 OSEIE C2IE C1IE EEIE BCL1IE — C3IE CCP2IE 81 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — C3IF CCP2IF 84 PR2 Timer2 Period Register 186* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 188 TMR2 Timer2 Module Register 186 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. DS40001579E-page 254  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 25.4 Register Definitions: CCP Control REGISTER 25-1: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — DCxB<1:0> CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Mode Select bits 11xx =PWM mode 1011 =Compare mode: Auto-conversion Trigger (sets CCPxIF bit (CCP2), starts ADC conversion if ADC module is enabled)(1) 1010 =Compare mode: generate software interrupt only 1001 =Compare mode: clear output on compare match (set CCPxIF) 1000 =Compare mode: set output on compare match (set CCPxIF) 0111 =Capture mode: every 16th rising edge 0110 =Capture mode: every 4th rising edge 0101 =Capture mode: every rising edge 0100 =Capture mode: every falling edge 0011 =Reserved 0010 =Compare mode: toggle output on match 0001 =Reserved 0000 =Capture/Compare/PWM off (resets CCPx module)  2011-2014 Microchip Technology Inc. DS40001579E-page 255

PIC16(L)F1782/3 26.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 26.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) The SPI interface supports the following modes and features: • Master mode • Slave mode • Clock Parity • Slave Select Synchronization (Slave mode only) • Daisy-chain connection of slave devices Figure26-1 is a block diagram of the SPI interface module. FIGURE 26-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPBUF Reg SDI SSPSR Reg SDO bit 0 Shift Clock SS SS Control 2 (CKP, CKE) Enable Clock Select Edge Select SSPM<3:0> 4 ( T M R 2 O u tp u t ) 2 SCK Edge Prescaler TOSC Select 4, 16, 64 Baud Rate Generator TRIS bit (SSPADD) DS40001579E-page 256  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 The I2C interface supports the following modes and features: • Master mode • Slave mode • Byte NACKing (Slave mode) • Limited multi-master support • 7-bit and 10-bit addressing • Start and Stop interrupts • Interrupt masking • Clock stretching • Bus collision detection • General call address matching • Address masking • Address Hold and Data Hold modes • Selectable SDA hold times Figure26-2 is a block diagram of the I2C interface module in Master mode. Figure26-3 is a diagram of the I2C interface module in Slave mode. FIGURE 26-2: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE) Internal data bus [SSPM<3:0>] Read Write SSP1BUF Baud rate generator (SSPADD) SDA Shift SDA in Clock SSPSR ct e Enable (RCEN) MGSeSbnteAarrcatk tbeni ot(,wS SSletoPdpCg ebOitNL,S2b) Clock Cntl arbitrate/BCOL det d off clock source) SCL ceive Clock (Hol e R Start bit detect, Stop bit detect SCL in Write collision detect Set/Reset: S, P, SSPSTAT, WCOL, SSPOV Clock arbitration Reset SEN, PEN (SSPCON2) Bus Collision State counter for Set SSP1IF, BCL1IF end of XMIT/RCV Address Match detect  2011-2014 Microchip Technology Inc. DS40001579E-page 257

PIC16(L)F1782/3 FIGURE 26-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT Reg) DS40001579E-page 258  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.2 SPI Mode Overview During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master The Serial Peripheral Interface (SPI) bus is a device is sending out the MSb from its shift register (on synchronous serial data communication bus that its SDO pin) and the slave device is reading this bit and operates in Full-Duplex mode. Devices communicate saving it as the LSb of its shift register, that the slave in a master/slave environment where the master device device is also sending out the MSb from its shift register initiates the communication. A slave device is (on its SDO pin) and the master device is reading this controlled through a Chip Select known as Slave bit and saving it as the LSb of its shift register. Select. After 8 bits have been shifted out, the master and slave The SPI bus specifies four signal connections: have exchanged register values. • Serial Clock (SCK) If there is more data to exchange, the shift registers are • Serial Data Out (SDO) loaded with new data and the process repeats itself. • Serial Data In (SDI) Whether the data is meaningful or not (dummy data), • Slave Select (SS) depends on the application software. This leads to Figure26-1 shows the block diagram of the MSSP three scenarios for data transmission: module when operating in SPI mode. • Master sends useful data and slave sends dummy The SPI bus operates with a single master device and data. one or more slave devices. When multiple slave • Master sends useful data and slave sends useful devices are used, an independent Slave Select data. connection is required from the master device to each • Master sends dummy data and slave sends useful slave device. data. Figure26-4 shows a typical connection between a Transmissions may involve any number of clock master device and multiple slave devices. cycles. When there is no more data to be transmitted, The master selects only one slave at a time. Most slave the master stops sending the clock signal and it devices have tri-state outputs so their output signal deselects the slave. appears disconnected from the bus when they are not Every slave device connected to the bus that has not selected. been selected through its slave select line must Transmissions involve two shift registers, 8 bits in size, disregard the clock and transmission signals and must one in the master and one in the slave. With either the not transmit out any data of its own. master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure26-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register.  2011-2014 Microchip Technology Inc. DS40001579E-page 259

PIC16(L)F1782/3 FIGURE 26-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SCK SCK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS General I/O General I/O SCK SDI SPI Slave SDO #2 SS SCK SDI SPI Slave SDO #3 SS 26.2.1 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation. These are: • MSSP STATUS register (SSPSTAT) • MSSP Control register 1 (SSPCON1) • MSSP Control register 3 (SSPCON3) • MSSP Data Buffer register (SSPBUF) • MSSP Address register (SSPADD) • MSSP Shift register (SSPSR) (Not directly accessible) SSPCON1 and SSPSTAT are the control and STATUS registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper 2 bits of the SSPSTAT are read/write. In one SPI master mode, SSPADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section26.7 “Baud Rate Generator”. SSPSR is the shift register used for shifting data in and out. SSPBUF provides indirect access to the SSPSR register. SSPBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSP1IF interrupt is set. During transmission, the SSPBUF is not buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. DS40001579E-page 260  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.2.2 SPI MODE OPERATION Any serial port function that is not desired may be overridden by programming the corresponding data When initializing the SPI, several options need to be direction (TRIS) register to the opposite value. specified. This is done by programming the appropriate The MSSP consists of a transmit/receive shift register control bits (SSPCON1<5:0> and SSPSTAT<7:6>). (SSPSR) and a buffer register (SSPBUF). The SSPSR These control bits allow the following to be specified: shifts the data in and out of the device, MSb first. The • Master mode (SCK is the clock output) SSPBUF holds the data that was written to the SSPSR • Slave mode (SCK is the clock input) until the received data is ready. Once the 8 bits of data • Clock Polarity (Idle state of SCK) have been received, that byte is moved to the SSPBUF • Data Input Sample Phase (middle or end of data register. Then, the Buffer Full Detect bit, BF of the output time) SSPSTAT register, and the interrupt flag bit, SSP1IF, are set. This double-buffering of the received data • Clock Edge (output data on rising/falling edge of (SSPBUF) allows the next byte to start reception before SCK) reading the data that was just received. Any write to the • Clock Rate (Master mode only) SSPBUF register during transmission/reception of data • Slave Select mode (Slave mode only) will be ignored and the write collision detect bit WCOL To enable the serial port, SSP Enable bit, SSPEN of the of the SSPCON1 register, will be set. User software SSPCON1 register, must be set. To reset or reconfig- must clear the WCOL bit to allow the following write(s) ure SPI mode, clear the SSPEN bit, re-initialize the to the SSPBUF register to complete successfully. SSPCONx registers and then set the SSPEN bit. This When the application software is expecting to receive configures the SDI, SDO, SCK and SS pins as serial valid data, the SSPBUF should be read before the next port pins. For the pins to behave as the serial port byte of data to transfer is written to the SSPBUF. The function, some must have their data direction bits (in Buffer Full bit, BF of the SSPSTAT register, indicates the TRIS register) appropriately programmed as when SSPBUF has been loaded with the received data follows: (transmission is complete). When the SSPBUF is read, • SDI must have corresponding TRIS bit set the BF bit is cleared. This data may be irrelevant if the • SDO must have corresponding TRIS bit cleared SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception • SCK (Master mode) must have corresponding has completed. If the interrupt method is not going to TRIS bit cleared be used, then software polling can be done to ensure • SCK (Slave mode) must have corresponding that a write collision does not occur. TRIS bit set The SSPSR is not directly readable or writable and can • SS must have corresponding TRIS bit set FIGURE 26-5: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x = 1010 SDO SDI Serial Input Buffer Serial Input Buffer (BUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK Slave Select General I/O SS Processor 1 (optional) Processor 2  2011-2014 Microchip Technology Inc. DS40001579E-page 261

PIC16(L)F1782/3 26.2.3 SPI MASTER MODE The clock polarity is selected by appropriately programming the CKP bit of the SSPCON1 register The master can initiate the data transfer at any time and the CKE bit of the SSPSTAT register. This then, because it controls the SCK line. The master would give waveforms for SPI communication as determines when the slave (Processor 2, Figure26-5) shown in Figure26-6, Figure26-8 and Figure26-9, is to broadcast data by the software protocol. where the MSB is transmitted first. In Master mode, the In Master mode, the data is transmitted/received as SPI clock rate (bit rate) is user programmable to be one soon as the SSPBUF register is written to. If the SPI is of the following: only going to receive, the SDO output could be • FOSC/4 (or TCY) disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the • FOSC/16 (or 4 * TCY) SDI pin at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY) received, it will be loaded into the SSPBUF register as • Timer2 output/2 if a normal received byte (interrupts and Status bits • Fosc/(4 * (SSPADD + 1)) appropriately set). Figure26-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 26-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSP1IF SSPSR to SSPBUF DS40001579E-page 262  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.2.4 SPI SLAVE MODE 26.2.5 SLAVE SELECT SYNCHRONIZATION In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last The Slave Select can also be used to synchronize bit is latched, the SSP1IF interrupt flag bit is set. communication. The Slave Select line is held high until Before enabling the module in SPI Slave mode, the clock the master device is ready to communicate. When the line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a be observed by reading the SCK pin. The Idle state is new transmission is starting. determined by the CKP bit of the SSPCON1 register. If the slave fails to receive the communication properly, While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the the external clock source on the SCK pin. This external Slave Select line returns to a high state. The slave is clock must meet the minimum high and low times as then ready to receive a new transmission when the specified in the electrical specifications. Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will While in Sleep mode, the slave can transmit/receive eventually become out of sync with the master. If the data. The shift register is clocked from the SCK pin slave misses a bit, it will always be one bit off in future input and when a byte is received, the device will transmissions. Use of the Slave Select line allows the generate an interrupt. If enabled, the device will slave and master to align themselves at the beginning wake-up from Sleep. of each transmission. 26.2.4.1 Daisy-Chain Configuration The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled The SPI bus can sometimes be connected in a (SSPCON1<3:0> = 0100). daisy-chain configuration. The first slave output is con- nected to the second slave input, the second slave When the SS pin is low, transmission and reception are output is connected to the third slave input, and so on. enabled and the SDO pin is driven. The final slave output is connected to the master input. When the SS pin goes high, the SDO pin is no longer Each slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down first group of clock pulses. The whole chain acts as resistors may be desirable depending on the one large communication shift register. The application. daisy-chain feature only requires a single Slave Select line from the master device. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON1<3:0> = Figure26-7 shows the block diagram of a typical 0100), the SPI module will reset if the SS daisy-chain connection when operating in SPI mode. pin is set to VDD. In a daisy-chain configuration, only the most recent 2: When the SPI is used in Slave mode with byte on the bus is required by the slave. Setting the CKE set; the user must enable SS pin BOEN bit of the SSPCON3 register will enable writes control. to the SSPBUF register, even if the previous byte has not been read. This allows the software to ignore data 3: While operated in SPI Slave mode the that may not apply to it. SMP bit of the SSPSTAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit.  2011-2014 Microchip Technology Inc. DS40001579E-page 263

PIC16(L)F1782/3 FIGURE 26-7: SPI DAISY-CHAIN CONNECTION SCK SCK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS SCK SDI SPI Slave SDO #2 SS SCK SDI SPI Slave SDO #3 SS FIGURE 26-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Shift register SSPSR and bit count are reset SSPBUF to SSPSR SDO bit 7 bit 6 bit 7 bit 6 bit 0 SDI bit 0 bit 7 bit 7 Input Sample SSP1IF Interrupt Flag SSPSR to SSPBUF DS40001579E-page 264  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 26-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE=0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSP1IF Interrupt Flag SSPSR to SSPBUF Write Collision detection active FIGURE 26-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSP1IF Interrupt Flag SSPSR to SSPBUF Write Collision detection active  2011-2014 Microchip Technology Inc. DS40001579E-page 265

PIC16(L)F1782/3 26.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmis- In SPI Master mode, module clocks may be operating sion/reception will remain in that state until the device at a different speed than when in Full-Power mode; in wakes. After the device returns to Run mode, the the case of the Sleep mode, all clocks are halted. module will resume transmitting and receiving data. Special care must be taken by the user when the MSSP In SPI Slave mode, the SPI Transmit/Receive Shift clock is much faster than the system clock. register operates asynchronously to the device. This In Slave mode, when MSSP interrupts are enabled, allows the device to be placed in Sleep mode and data after the master completes sending data, an MSSP to be shifted into the SPI Transmit/Receive Shift interrupt will wake the controller from Sleep. register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the If an exit from Sleep mode is not desired, MSSP device. interrupts should be disabled. TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 115 APFCON C2OUTSEL CCP1SEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 111 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 260* SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 306 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 308 SSP1STAT SMP CKE D/A P S R/W UA BF 304 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA0 125 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. * Page provides register information. Note 1: PIC16(L)F1783 only. DS40001579E-page 266  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.3 I2C MODE OVERVIEW FIGURE 26-11: I2C MASTER/ SLAVE CONNECTION The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master VDD devices initiate the communication. A Slave device is controlled through addressing. SCL SCL The I2C bus specifies two signal connections: VDD • Serial Clock (SCL) Master Slave • Serial Data (SDA) SDA SDA Figure26-11 shows the block diagram of the MSSP module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal, supply voltage. Pulling the line to ground is considered which holds the SDA line low to indicate to the transmit- a logical zero and letting the line float is considered a ter that the slave device has received the transmitted logical one. data and is ready to receive more. Figure26-11 shows a typical connection between two The transition of a data bit is always performed while processors configured as master and slave devices. the SCL line is held low. Transitions that occur while the The I2C bus can operate with one or more master SCL line is held high are used to indicate Start and Stop devices and one or more slave devices. bits. There are four potential modes of operation for a given If the master intends to write to the slave, then it repeat- device: edly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the • Master Transmit mode master device is in Master Transmit mode and the (master is transmitting data to a slave) slave is in Slave Receive mode. • Master Receive mode If the master intends to read from the slave, then it (master is receiving data from a slave) repeatedly receives a byte of data from the slave, and • Slave Transmit mode responds after each byte with an ACK bit. In this (slave is transmitting data to a master) example, the master device is in Master Receive mode • Slave Receive mode and the slave is Slave Transmit mode. (slave is receiving data from the master) On the last byte of data communicated, the master To begin communication, a master device starts out in device may end the transmission by sending a Stop bit. Master Transmit mode. The master device sends out a If the master device is in Receive mode, it sends the Start bit followed by the address byte of the slave it Stop bit in place of the last ACK bit. A Stop bit is intends to communicate with. This is followed by a indicated by a low-to-high transition of the SDA line single Read/Write bit, which determines whether the while the SCL line is held high. master intends to transmit to or receive data from the In some cases, the master may want to maintain slave device. control of the bus and re-initiate another transmission. If the requested slave exists on the bus, it will respond If so, the master device may send another Start bit in with an Acknowledge bit, otherwise known as an ACK. place of the Stop bit or last ACK bit when it is in receive The master then continues in either Transmit mode or mode. Receive mode and the slave continues in the comple- The I2C bus specifies three message protocols; ment, either in Receive mode or Transmit mode, respectively. • Single message where a master writes data to a slave. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and • Single message where a master reads data from data bytes are sent out, Most Significant bit (MSb) first. a slave. The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a out as a logical zero when it intends to write data to the combination of writes and reads, to one or more slave. slaves.  2011-2014 Microchip Technology Inc. DS40001579E-page 267

PIC16(L)F1782/3 When one device is transmitting a logical one, or letting 26.3.2 ARBITRATION the line float, and a second device is transmitting a Each master device must monitor the bus for Start and logical zero, or holding the line low, the first device can Stop bits. If the device detects that the bus is busy, it detect that the line is not a logical one. This detection, cannot begin a new message until the bus returns to an when used on the SCL line, is called clock stretching. Idle state. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on However, two master devices may try to initiate a trans- the SDA line, it is called arbitration. Arbitration ensures mission on or about the same time. When this occurs, that there is only one master device communicating at the process of arbitration begins. Each transmitter any single time. checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to 26.3.1 CLOCK STRETCHING observe that the two levels do not match, loses arbitra- tion, and must stop transmitting on the SDA line. When a slave device has not completed processing data, it can delay the transfer of more data through the For example, if one transmitter holds the SDA line to a process of clock stretching. An addressed slave device logical one (lets it float) and a second transmitter holds may hold the SCL clock line low after receiving or send- it to a logical zero (pulls it low), the result is that the ing a bit, indicating that it is not yet ready to continue. SDA line will be low. The first transmitter then observes The master that is communicating with the slave will that the level of the line is different than expected and attempt to raise the SCL line in order to transfer the concludes that another transmitter is communicating. next bit, but will detect that the clock line has not yet The first transmitter to notice this difference is the one been released. Because the SCL connection is that loses arbitration and must stop driving the SDA open-drain, the slave has the ability to hold that line low line. If this transmitter is also a master device, it also until it is ready to continue communicating. must stop driving the SCL line. It then can monitor the Clock stretching allows receivers that cannot keep up lines for a Stop condition before trying to reissue its with a transmitter to control the flow of incoming data. transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitra- tion. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. DS40001579E-page 268  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.4 I2C MODE OPERATION TABLE 26-2: I2C BUS TERMS All MSSP I2C communication is byte oriented and TERM Description shifted out MSb first. Six SFR registers and two Transmitter The device which shifts data out interrupt flags interface the module with the PIC® onto the bus. microcontroller and user software. Two pins, SDA and Receiver The device which shifts data in SCL, are exercised by the module to communicate from the bus. with other external I2C devices. Master The device that initiates a transfer, generates clock signals and 26.4.1 BYTE FORMAT terminates a transfer. All communication in I2C is done in 9-bit segments. A Slave The device addressed by the byte is sent from a master to a slave or vice-versa, master. followed by an Acknowledge bit sent back. After the Multi-master A bus with more than one device 8th falling edge of the SCL line, the device outputting that can initiate data transfers. data on the SDA changes that pin to an input and Arbitration Procedure to ensure that only one reads in an acknowledge value on the next clock master at a time controls the bus. pulse. Winning arbitration ensures that The clock signal, SCL, is provided by the master. Data the message is not corrupted. is valid to change while the SCL signal is low, and Synchronization Procedure to synchronize the sampled on the rising edge of the clock. Changes on clocks of two or more devices on the SDA line while the SCL line is high define special the bus. conditions on the bus, explained below. Idle No master is controlling the bus, 26.4.2 DEFINITION OF I2C TERMINOLOGY and both SDA and SCL lines are high. There is language and terminology in the description Active Any time one or more master of I2C communication that have definitions specific to devices are controlling the bus. I2C. That word usage is defined below and may be Addressed Slave device that has received a used in the rest of this document without explanation. This table was adapted from the Philips I2C Slave matching address and is actively being clocked by a master. specification. Matching Address byte that is clocked into a 26.4.3 SDA AND SCL PINS Address slave that matches the value Selection of any I2C mode with the SSPEN bit set, stored in SSPADD. forces the SCL and SDA pins to be open-drain. These Write Request Slave receives a matching pins should be set by the user to inputs by setting the address with R/W bit clear, and is appropriate TRIS bits. ready to clock in data. Read Request Master sends an address byte with Note: Data is tied to output zero when an I2C the R/W bit set, indicating that it mode is enabled. wishes to clock data out of the Slave. This data is the next and all 26.4.4 SDA HOLD TIME following bytes until a Restart or The hold time of the SDA pin is selected by the SDAHT Stop. bit of the SSPCON3 register. Hold time is the time SDA Clock Stretching When a device on the bus hold is held valid after the falling edge of SCL. Setting the SCL low to stall communication. SDAHT bit selects a longer 300ns minimum hold time Bus Collision Any time the SDA line is sampled and may help on buses with large capacitance. low by the module while it is out- putting and expected high state.  2011-2014 Microchip Technology Inc. DS40001579E-page 269

PIC16(L)F1782/3 26.4.5 START CONDITION 26.4.7 RESTART CONDITION The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid. transition of SDA from a high to a low state while SCL A master can issue a Restart if it wishes to hold the line is high. A Start condition is always generated by bus after terminating the current transfer. A Restart the master and signifies the transition of the bus from has the same effect on the slave that a Start would, an Idle to an Active state. Figure26-10 shows wave resetting all slave logic and preparing it to clock in an forms for Start and Stop conditions. address. The master may want to address the same or another slave. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it In 10-bit Addressing Slave mode a Restart is required low. This does not conform to the I2C Specification that for the master to clock data out of the addressed states no bus collision can occur on a Start. slave. Once a slave has been fully addressed, match- ing both high and low address bytes, the master can 26.4.6 STOP CONDITION issue a Restart and the high address byte with the A Stop condition is a transition of the SDA line from R/W bit set. The slave logic will then hold the clock and prepare to clock out data. low-to-high state while the SCL line is high. After a full match with R/W clear in 10-bit mode, a prior Note: At least one SCL low time must appear match flag is set and maintained. Until a Stop before a Stop is valid, therefore, if the SDA condition, a high address with R/W clear, or high line goes low then high again while the SCL address match fails. line stays high, only the Start condition is detected. 26.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 26-12: I2C START AND STOP CONDITIONS SDA SCL S P Change of Change of Data Allowed Data Allowed Start Stop Condition Condition FIGURE 26-13: I2C RESTART CONDITION Sr Change of Change of Data Allowed Data Allowed Restart Condition DS40001579E-page 270  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.4.9 ACKNOWLEDGE SEQUENCE 26.5 I2C SLAVE MODE OPERATION The 9th SCL pulse for any transferred byte in I2C is The MSSP Slave mode operates in one of four modes dedicated as an Acknowledge. It allows receiving selected in the SSPM bits of SSPCON1 register. The devices to respond back to the transmitter by pulling modes can be divided into 7-bit and 10-bit Addressing the SDA line low. The transmitter must release control mode. 10-bit Addressing modes operate the same as of the line during this time to shift in the response. The 7-bit with some additional overhead for handling the Acknowledge (ACK) is an active-low signal, pulling the larger addresses. SDA line low indicated to the transmitter that the Modes with Start and Stop bit interrupts operated the device has received the transmitted data and is ready same as the other modes with SSP1IF additionally to receive more. getting set upon detection of a Start, Restart, or Stop The result of an ACK is placed in the ACKSTAT bit of condition. the SSPCON2 register. 26.5.1 SLAVE MODE ADDRESSES Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to The SSPADD register (Register26-6) contains the the transmitter. The ACKDT bit of the SSPCON2 Slave mode address. The first byte received after a register is set/cleared to determine the response. Start or Restart condition is compared against the Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the AHEN and DHEN bits of the SSPCON3 register are value is loaded into the SSPBUF register and an clear. interrupt is generated. If the value does not match, the module goes idle and no indication is given to the There are certain conditions where an ACK will not be software that anything happened. sent by the slave. If the BF bit of the SSPSTAT register or the SSPOV bit of the SSPCON1 register are set The SSP Mask register (Register26-5) affects the when a byte is received. address matching process. See Section26.5.9 “SSP Mask Register” for more information. When the module is addressed, after the 8th falling edge of SCL on the bus, the ACKTIM bit of the SSP- 26.5.1.1 I2C Slave 7-bit Addressing Mode CON3 register is set. The ACKTIM bit indicates the In 7-bit Addressing mode, the LSb of the received data acknowledge time of the active bus. The ACKTIM Sta- byte is ignored when determining if there is an address tus bit is only active when the AHEN bit or DHEN bit is match. enabled. 26.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPADD with the low address. The low address byte is clocked in and all 8 bits are compared to the low address value in SSPADD. Even if there is not an address match; SSP1IF and UA are set, and SCL is held low until SSPADD is updated to receive a high byte again. When SSPADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communi- cation. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hard- ware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match.  2011-2014 Microchip Technology Inc. DS40001579E-page 271

PIC16(L)F1782/3 26.5.2 SLAVE RECEPTION 26.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte Slave device reception with AHEN and DHEN set is clear, the R/W bit of the SSPSTAT register is cleared. operate the same as without these options with extra The received address is loaded into the SSPBUF interrupts and clock stretching added after the 8th register and acknowledged. falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK When the overflow condition exists for a received the receive address or data byte, rather than the hard- address, then not Acknowledge is given. An overflow ware. This functionality adds support for PMBus™ that condition is defined as either bit BF of the SSPSTAT was not present on previous versions of this module. register is set, or bit SSPOV of the SSPCON1 register is set. The BOEN bit of the SSPCON3 register modifies This list describes the steps that need to be taken by this operation. For more information see Register26-4. slave software to use these options for I2C communi- cation. Figure26-15 displays a module using both An MSSP interrupt is generated for each transferred address and data holding. Figure26-16 includes the data byte. Flag bit, SSP1IF, must be cleared by soft- operation with the SEN bit of the SSPCON2 register ware. set. When the SEN bit of the SSPCON2 register is set, SCL 1. S bit of SSPSTAT is set; SSP1IF is set if inter- will be held low (clock stretch) following each received rupt on Start detect is enabled. byte. The clock must be released by setting the CKP bit of the SSPCON1 register, except sometimes in 2. Matching address with R/W bit clear is clocked 10-bit mode. See Section26.2.3 “SPI Master Mode” in. SSP1IF is set and CKP cleared after the 8th for more detail. falling edge of SCL. 3. Slave clears the SSP1IF. 26.5.2.1 7-bit Addressing Reception 4. Slave can look at the ACKTIM bit of the This section describes a standard sequence of events SSPCON3 register to determine if the SSP1IF for the MSSP module configured as an I2C Slave in was after or before the ACK. 7-bit Addressing mode. All decisions made by hard- 5. Slave reads the address value from SSPBUF, ware or software and their effect on reception. clearing the BF flag. Figure26-13 and Figure26-14 is used as a visual 6. Slave sets ACK value clocked out to the master reference for this description. by setting ACKDT. This is a step by step process of what typically must 7. Slave releases the clock by setting CKP. be done to accomplish I2C communication. 8. SSP1IF is set after an ACK, not after a NACK. 1. Start bit detected. 9. If SEN=1 the slave hardware will stretch the 2. S bit of SSPSTAT is set; SSP1IF is set if inter- clock after the ACK. rupt on Start detect is enabled. 10. Slave clears SSP1IF. 3. Matching address with R/W bit clear is received. Note: SSP1IF is still set after the 9th falling edge 4. The slave pulls SDA low sending an ACK to the of SCL even if there is no clock stretching master, and sets SSP1IF bit. and BF has been cleared. Only if NACK is 5. Software clears the SSP1IF bit. sent to master is SSP1IF not set 6. Software reads received address from SSPBUF 11. SSP1IF set and CKP cleared after 8th falling clearing the BF flag. edge of SCL for a received data byte. 7. If SEN=1; Slave software sets CKP bit to 12. Slave looks at ACKTIM bit of SSPCON3 to release the SCL line. determine the source of the interrupt. 8. The master clocks out a data byte. 13. Slave reads the received data from SSPBUF 9. Slave drives SDA low sending an ACK to the clearing BF. master, and sets SSP1IF bit. 14. Steps 7-14 are the same for each received data 10. Software clears SSP1IF. byte. 11. Software reads the received byte from SSPBUF 15. Communication is ended by either the slave clearing BF. sending an ACK=1, or the master sending a Stop condition. If a Stop is sent and Interrupt on 12. Steps 8-12 are repeated for all received bytes Stop Detect is disabled, the slave will only know from the master. by polling the P bit of the SSTSTAT register. 13. Master sends Stop condition, setting P bit of SSPSTAT, and the bus goes idle. DS40001579E-page 272  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 26-14: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=0, DHEN=0) s Bus Master sendStop condition 1 P SSP1IF set on 9thfalling edge of SCL = K 9 C A D0 8 e Master eceiving Data D4D3D2D1 4567 eared by software SSPOV set becausSSPBUF is still full. ACK is not sent. e to R D5 3 Cl v From Sla D7D6K 12 First byte of data is available in SSPBUF C 9 A D0 8 D1 7 d a Receiving Data D5D4D3D2 3456 Cleared by software SSPBUF is re D6 2 D7 1 K 9 C A 8 A1 7 2 6 A s s dre A3 5 d A ng A4 4 vi ecei A5 3 R A6 2 A7 1 S V F O A L 1I P D C P F S S S S B S S  2011-2014 Microchip Technology Inc. DS40001579E-page 273

PIC16(L)F1782/3 FIGURE 26-15: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) Bus Master sends Stop condition P SSP1IF set on 9thfalling edge of SCL SCL is not heldlow becauseACK=1 K C 9 A D0 8 e Receive Data D7D6D5D4D3D2D1 1234567 Cleared by software First byte of data is available in SSPBUF SSPOV set becausSSPBUF is still full. ACK is not sent. CKP is written to ‘’ in software, 1releasing SCL N E S K AC 9 D0 8 ’1 o ‘ Data D2D1 67 KP is set t oftware, Receive D7D6D5D4D3 12345 Clock is held low until C Cleared by software SSPBUF is read CKP is written to ‘’ in s1releasing SCL N E S K C A 9 0 = W R/ 8 A1 7 2 6 A s s dre A3 5 d e A A4 4 v ei ec A5 3 R 6 2 A A7 1 S F V P SDA SCL SSP1I BF SSPO CK DS40001579E-page 274  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 26-16: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=1) Master sendsStop condition =1 P No interruptafter not ACKfrom Slave CK 9 A are T to Received DataCKD7D6D5D4D3D2D1D0 912345678 Cleared by software a is read from SSPBUF Slave softwsets ACKDnot ACK CKP set by software, SCL is released ACKTIM set by hardwareon 8th falling edge of SCL A at D D0 8 g Receiving Data D6D5D4D3D2D1 234567 SP1IF is set on h falling edge of CL, after ACK When DHEN=:1CKP is cleared byhardware on 8th fallinedge of SCL KTIM cleared bydware in 9th ng edge of SCL D7 1 S9tS ACharrisi K 9 ce C n A e Aqu De es SCK s sA Master Releato slave for Receiving Address A7A6A5A4A3A2A1 12345678 If AHEN=:1SSP1IF is set Address isread from SSBUF Slave softwareclears ACKDT to ACK the receivedbyte When AHEN=:1CKP is cleared by hardwareand SCL is stretched ACKTIM set by hardwareon 8th falling edge of SCL S M SDA SCL SSP1IF BF ACKDT CKP ACKTI S P  2011-2014 Microchip Technology Inc. DS40001579E-page 275

PIC16(L)F1782/3 FIGURE 26-17: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN= 1, AHEN=1, DHEN=1) Master sendsStop condition P No interrupt afterif not ACKfrom Slave CKP is not clearedif not ACK K 9 C A D0 8 s d D1 7 enK Receive Data D6D5D4D3D2 23456 SSPBUF can beread any time beforenext byte is loaded Slave snot AC Set by software,release SCL D7 1 K C 9 A D0 8 e K sequence Receive Data D7D6D5D4D3D2D1 1245673 Cleared by software Received data isavailable on SSPBUF When DHEN = ;1on the 8th falling edgeof SCL of a receiveddata byte, CKP is cleared ACKTIM is cleared by hardwaron 9th rising edge of SCL C A ster releasesA to slave for ACK 9 aD MS 8 s R/W = 0 Receiving Address A6A5A4A3A2A1 342567 Received address is loaded into SSPBUF Slave software clearACKDT to ACKthe received byte When AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared KTIM is set by hardware8th falling edge of SCL A7 1 ACon S M TI SDA SCL SSP1IF BF ACKDT CKP ACK S P DS40001579E-page 276  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.5.3 SLAVE TRANSMISSION 26.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set A master device can transmit a read request to a and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list SSPSTAT register is set. The received address is below outlines what software for a slave will need to loaded into the SSPBUF register, and an ACK pulse is do to accomplish a standard transmission. sent by the slave on the ninth bit. Figure26-17 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and and the SCL pin is held low (see Section26.5.6 SCL. “Clock Stretching” for more detail). By stretching the 2. S bit of SSPSTAT is set; SSP1IF is set if inter- clock, the master will be unable to assert another clock rupt on Start detect is enabled. pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by data. the Slave setting SSP1IF bit. The transmit data must be loaded into the SSPBUF 4. Slave hardware generates an ACK and sets register which also loads the SSPSR register. Then the SSP1IF. SCL pin should be released by setting the CKP bit of 5. SSP1IF bit is cleared by user. the SSPCON1 register. The eight data bits are shifted 6. Software reads the received address from out on the falling edge of the SCL input. This ensures SSPBUF, clearing BF. that the SDA signal is valid during the SCL high time. 7. R/W is set so CKP was automatically cleared The ACK pulse from the master-receiver is latched on after the ACK. the rising edge of the ninth SCL input pulse. This ACK 8. The slave software loads the transmit data into value is copied to the ACKSTAT bit of the SSPCON2 SSPBUF. register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is 9. CKP bit is set releasing SCL, allowing the latched by the slave, the slave goes idle and waits for master to clock the data out of the slave. another occurrence of the Start bit. If the SDA line was 10. SSP1IF is set after the ACK response from the low (ACK), the next transmit data must be loaded into master is loaded into the ACKSTAT register. the SSPBUF register. Again, the SCL pin must be 11. SSP1IF bit is cleared. released by setting bit CKP. 12. The slave software checks the ACKSTAT bit to An MSSP interrupt is generated for each data transfer see if the master wants to clock out more data. byte. The SSP1IF bit must be cleared by software and Note 1: If the master ACKs the clock will be the SSPSTAT register is used to determine the status stretched. of the byte. The SSP1IF bit is set on the falling edge of 2: ACKSTAT is the only bit updated on the the ninth clock pulse. rising edge of SCL (9th) rather than the 26.5.3.1 Slave Mode Bus Collision falling. A slave receives a Read request and begins shifting 13. Steps 9-13 are repeated for each transmitted data out on the SDA line. If a bus collision is detected byte. and the SBCDE bit of the SSPCON3 register is set, the 14. If the master sends a not ACK; the clock is not BCL1IF bit of the PIR register is set. Once a bus colli- held, but SSP1IF is still set. sion is detected, the slave goes idle and waits to be 15. The master sends a Restart condition or a Stop. addressed again. User software can use the BCL1IF bit 16. The slave is no longer addressed. to handle a slave bus collision.  2011-2014 Microchip Technology Inc. DS40001579E-page 277

PIC16(L)F1782/3 FIGURE 26-18: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=0) sn do enditi er scon P stp ao MSt K C 9 A Transmitting Data D7D6D5D4D3D2D1D0 12345678 BF is automatically cleared after 8th fallingedge of SCL CKP is not held for not ACK Masters not ACKis copied to ACKSTAT c ati m o ut A K AC 9 D0 8 1 D 7 a Dat D2 6 Transmitting D7D6D5D4D3 12345 Cleared by software Data to transmit isloaded into SSPBUF Set by software c ati m o ut A 1CK =A 9 W R/ 8 eceiving Address A5A4A3A2A1 34567 Received addressis read from SSPBUF When R/W is setSCL is alwaysheld low after 9th SCLfalling edge R/W is copied from the matching address byte Indicates an address has been received R 6 A 2 7 A 1 S T F TA SDA SCL SSP1I BF CKP ACKS R/W D/A S P DS40001579E-page 278  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSP1IF interrupt is set. Figure26-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. Bus starts Idle. 2. Master sends Start condition; the S bit of SSPSTAT is set; SSP1IF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCL line the CKP bit is cleared and SSP1IF interrupt is generated. 4. Slave software clears SSP1IF. 5. Slave software reads ACKTIM bit of SSPCON3 register, and R/W and D/A of the SSPSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSPCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSP1IF after the ACK if the R/W bit is set. 11. Slave software clears SSP1IF. 12. Slave loads value to transmit to the master into SSPBUF setting the BF bit. Note: SSPBUF cannot be loaded until after the ACK. 13. Slave sets the CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPCON2 register. 16. Steps 10-15 are repeated for each byte transmit- ted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop.  2011-2014 Microchip Technology Inc. DS40001579E-page 279

PIC16(L)F1782/3 FIGURE 26-19: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=1) endsdition sn aster op co P MSt K C A 9 0 D 8 Transmitting Data D5D4D3D2D1 34567 F is automatically eared after 8th fallingge of SCL Master’s ACKresponse is copiedto SSPSTAT CKP not cleared after not ACK D6 2 Bcled 7 D 1 c ati m o AutK C A 9 D0 8 1 a D 7 at D 2 ence omaticTransmitting D7D6D5D4D3D 123456 Cleared by software Data to transmit isloaded into SSPBUF Set by software,releases SCL KTIM is cleared9th rising edge of SCL DAequ Aut ACon Ss K Master releases to slave for ACK W=1AC 9 When R/W = ;1CKP is alwayscleared after ACK Receiving AddressR/ A7A6A5A4A3A2A1 12345678 Received addressis read from SSPBUF Slave clears ACKDT to ACKaddress When AHEN = ;1CKP is cleared by hardwareafter receiving matchingaddress. ACKTIM is set on 8th fallingedge of SCL S SDA SCL SP1IF BF CKDT STAT CKP KTIM R/W D/A S A K C C A A DS40001579E-page 280  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.5.4 SLAVE MODE 10-BIT ADDRESS 26.5.5 10-BIT ADDRESSING WITH ADDRESS OR RECEPTION DATA HOLD This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or for the MSSP module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only 10-bit Addressing mode. difference is the need to update the SSPADD register using the UA bit. All functionality, specifically when the Figure26-19 is used as a visual reference for this CKP bit is cleared and SCL line is held low are the description. same. Figure26-20 can be used as a reference of a This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set. slave software to accomplish I2C communication. Figure26-21 shows a standard waveform for a slave 1. Bus starts Idle. transmitter in 10-bit Addressing mode. 2. Master sends Start condition; S bit of SSPSTAT is set; SSP1IF is set if interrupt on Start detect is enabled. 3. Master sends matching high address with R/W bit clear; UA bit of the SSPSTAT register is set. 4. Slave sends ACK and SSP1IF is set. 5. Software clears the SSP1IF bit. 6. Software reads received address from SSPBUF clearing the BF flag. 7. Slave loads low address into SSPADD, releasing SCL. 8. Master sends matching low address byte to the slave; UA bit is set. Note: Updates to the SSPADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSP1IF is set. Note: If the low address does not match, SSP1IF and UA are still set so that the slave soft- ware can set SSPADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSP1IF. 11. Slave reads the received matching address from SSPBUF clearing BF. 12. Slave loads high address into SSPADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCL pulse; SSP1IF is set. 14. If SEN bit of SSPCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSP1IF. 16. Slave reads the received byte from SSPBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission.  2011-2014 Microchip Technology Inc. DS40001579E-page 281

PIC16(L)F1782/3 FIGURE 26-20: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) endsdition er scon P stp ao MSt K C 9 A 0 8 D a D1 7 F at dU D 2 6 aB Receive D6D5D4D3D 2345 SCL is held lowwhile CKP = 0 Data is refrom SSP Set by software,releasing SCLyte D7 1 d b e v K cei Receive Data D6D5D4D3D2D1D0AC 92345678 Cleared by software Receive address isread from SSPBUF When SEN = ;1CKP is cleared after9th falling edge of re D7 1 K C e A 9 ess Byt A1A0 78 PADD Receive Second Addr A6A5A4A3A2 23456 Software updates SSand releases SCL A7 1 K C 9 A ve First Address Byte 0A9A811 345678 Set by hardwareon 9th falling edge If address matchesSSPADD it is loaded into SSPBUF When UA = ;1SCL is held low ei 1 2 c e R 1 1 S SDA SCL SP1IF BF UA CKP S DS40001579E-page 282  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 26-21: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=0) a Receive Data D7D6D5 12 Received datis read from SSPBUF K C 9 A D0 8 D1 7 s e Receive Data D6D5D4D3D2 23456 eared by software Update of SSPADD,clears UA and releasSCL CKP with software ases SCL D7 1 Cl Set rele A U K C 9 A 0 A 8 Receive Second Address Byte A6A5A4A3A2A1 345672 ed by software SSPBUF can beread anytime beforethe next received byte ate to SSPADD isallowed until 9thng edge of SCL A7 1 Clear Updnot falli A U K C 9 A 0 = W 8 R/ e eive First Address Byte A9A8110 34567 Set by hardwareon 9th falling edge Slave software clearsACKDT to ACKthe received byte If when AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared ACKTIM is set by hardwaron 8th falling edge of SCL ec 1 2 R 1 1 S F T M SDA SCL SSP1I BF ACKD UA CKP ACKTI  2011-2014 Microchip Technology Inc. DS40001579E-page 283

PIC16(L)F1782/3 FIGURE 26-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN=0, AHEN=0, DHEN=0) ends dition er scon P MastStop K = 1 ds AC 9 en D0 8 K Master snot ACK Transmitting Data Byte D7D6D5D4D3D2D1 1723456 Data to transmit isloaded into SSPBUF Set by softwarereleases SCL Masters not ACis copied K C A 9 e 8 aster sends estart event Receive First Address Byt A9A811110 1672345Sr Set by hardware Received address isread from SSPBUF High address is loadedback into SSPADD When R/W = ;1CKP is cleared on9th falling edge of SCL R/W is copied from thematching address byte MR K yte AC 9 s B A0 8 ed eiving Second Addres A6A5A4A3A2A1 672345 Cleared by software After SSPADD isupdated, UA is clearand SCL is released c Re A7 1 K = 0 AC 9 W 8 Receiving AddressR/ A9A811110 1672345 Set by hardware SSPBUF loadedwith received address UA indicates SSPADDmust be updated Indicates an addresshas been received S AT T S SDA SCL SP1IF BF UA CKP ACK R/W D/A S DS40001579E-page 284  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.5.6 CLOCK STRETCHING 26.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set the holds the SCL line low effectively pausing communica- clock is always stretched. This is the only time the SCL tion. The slave may stretch the clock to allow more is stretched without CKP being cleared. SCL is time to handle data or prepare a response for the released immediately after a write to SSPADD. master device. A master device is not concerned with Note: Previous versions of the module did not stretching as anytime it is active on the bus and not stretch the clock if the second address byte transferring data it is stretching. Any stretching done did not match. by a slave is invisible to the master software and handled by the hardware that generates SCL. 26.5.6.3 Byte NACKing The CKP bit of the SSPCON1 register is used to When AHEN bit of SSPCON3 is set; CKP is cleared by control stretching in software. Any time the CKP bit is hardware after the 8th falling edge of SCL for a cleared, the module will wait for the SCL line to go low received matching address byte. When DHEN bit of and then hold it. Setting CKP will release SCL and SSPCON3 is set; CKP is cleared after the 8th falling allow more communication. edge of SCL for received data. 26.5.6.1 Normal Clock Stretching Stretching after the 8th falling edge of SCL allows the Following an ACK if the R/W bit of SSPSTAT is set, a slave to look at the received address or data and read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data. allows the slave time to update SSPBUF with data to 26.5.7 CLOCK SYNCHRONIZATION AND transfer to the master. If the SEN bit of SSPCON2 is THE CKP BIT set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait is set by software and communication resumes. for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low Note 1: The BF bit has no effect on if the clock will until the SCL output is already sampled low. There- be stretched or not. This is different than fore, the CKP bit will not assert the SCL line until an previous versions of the module that external I2C master device has already asserted the would not stretch the clock, clear CKP, if SCL line. The SCL output will remain low until the CKP SSPBUF was read before the 9th falling bit is set and all other devices on the I2C bus have edge of SCL. released SCL. This ensures that a write to the CKP bit 2: Previous versions of the module did not will not violate the minimum high time requirement for stretch the clock for a transmission if SCL (see Figure26-22). SSPBUF was loaded before the 9th fall- ing edge of SCL. It is now always cleared for read requests. FIGURE 26-23: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX ‚ – 1 SCL Master device CKP asserts clock Master device releases clock WR SSPCON1  2011-2014 Microchip Technology Inc. DS40001579E-page 285

PIC16(L)F1782/3 26.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave The addressing procedure for the I2C bus is such that will prepare to receive the second byte as data, just as the first byte after the Start condition usually it would in 7-bit mode. determines which device will be the slave addressed by the master device. The exception is the general call If the AHEN bit of the SSPCON3 register is set, just as address which can address all devices. When this with any other address reception, the slave hardware address is used, all devices should, in theory, respond will stretch the clock after the 8th falling edge of SCL. with an acknowledge. The slave must then set its ACKDT value and release the clock with communication progressing as it would The general call address is a reserved address in the normally. I2C protocol, defined as address 0x00. When the GCEN bit of the SSPCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPBUF and respond. Figure26-23 shows a general call reception sequence. FIGURE 26-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSP1IF BF (SSPSTAT<0>) Cleared by software SSPBUF is read GCEN (SSPCON2<7>) ’1’ 26.5.9 SSP MASK REGISTER An SSP Mask (SSPMSK) register (Register26-5) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the reception of the first (high) byte of the address. DS40001579E-page 286  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.6 I2C Master Mode 26.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the The master device generates all of the serial clock appropriate SSPM bits in the SSPCON1 register and pulses and the Start and Stop conditions. A transfer is by setting the SSPEN bit. In Master mode, the SDA and ended with a Stop condition or with a Repeated Start SCK pins must be configured as inputs. The MSSP condition. Since the Repeated Start condition is also peripheral hardware will override the output driver TRIS the beginning of the next serial transfer, the I2C bus will controls when necessary to drive the pins low. not be released. Master mode of operation is supported by interrupt In Master Transmitter mode, serial data is output generation on the detection of the Start and Stop through SDA, while SCL outputs the serial clock. The conditions. The Stop (P) and Start (S) bits are cleared first byte transmitted contains the slave address of the from a Reset or when the MSSP module is disabled. receiving device (7 bits) and the Read/Write (R/W) bit. Control of the I2C bus may be taken when the P bit is In this case, the R/W bit will be logic ‘0’. Serial data is set, or the bus is Idle. transmitted 8 bits at a time. After each byte is transmit- ted, an Acknowledge bit is received. Start and Stop In Firmware Controlled Master mode, user code conducts all I2C bus operations based on Start and conditions are output to indicate the beginning and the end of a serial transfer. Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted other communication is done by the user software contains the slave address of the transmitting device directly manipulating the SDA and SCL lines. (7bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave The following events will cause the SSP Interrupt Flag address followed by a ‘1’ to indicate the receive bit. bit, SSP1IF, to be set (SSP interrupt, if enabled): Serial data is received via SDA, while SCL outputs the • Start condition detected serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmit- • Stop condition detected ted. Start and Stop conditions indicate the beginning • Data transfer byte transmitted/received and end of transmission. • Acknowledge transmitted/received A Baud Rate Generator is used to set the clock • Repeated Start generated frequency output on SCL. See Section26.7 “Baud Note 1: The MSSP module, when configured in Rate Generator” for more detail. I2C Master mode, does not allow queue- ing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete.  2011-2014 Microchip Technology Inc. DS40001579E-page 287

PIC16(L)F1782/3 26.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and begins count- ing. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure26-25). FIGURE 26-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX ‚ – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload 26.6.3 WCOL STATUS FLAG If the user writes the SSPBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPBUF was attempted while the module was not idle. Note: Because queuing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the Start condition is complete. DS40001579E-page 288  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.6.4 I2C MASTER MODE START CONDITION TIMING Note 1: If at the beginning of the Start condition, To initiate a Start condition, the user sets the Start the SDA and SCL pins are already Enable bit, SEN bit of the SSPCON2 register. If the sampled low, or if during the Start condi- SDA and SCL pins are sampled high, the Baud Rate tion, the SCL line is sampled low before Generator is reloaded with the contents of the SDA line is driven low, a bus collision SSPADD<7:0> and starts its count. If SCL and SDA occurs, the Bus Collision Interrupt Flag, are both sampled high when the Baud Rate Generator BCL1IF, is set, the Start condition is times out (TBRG), the SDA pin is driven low. The action aborted and the I2C module is reset into of the SDA being driven low while SCL is high is the its Idle state. Start condition and causes the S bit of the SSPSTAT1 2: The Philips I2C specification states that a register to be set. Following this, the Baud Rate bus collision cannot occur on a Start. Generator is reloaded with the contents of SSPADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPCON2 register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. FIGURE 26-26: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPSTAT<3>) At completion of Start bit, SDA = 1, hardware clears SEN bit SCL = 1 and sets SSP1IF bit TBRG TBRG Write to SSPBUF occurs here SDA 1st bit 2nd bit TBRG SCL S TBRG  2011-2014 Microchip Technology Inc. DS40001579E-page 289

PIC16(L)F1782/3 26.6.5 I2C MASTER MODE REPEATED CON2 register will be automatically cleared and the START CONDITION TIMING Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is A Repeated Start condition occurs when the RSEN bit detected on the SDA and SCL pins, the S bit of the of the SSPCON2 register is programmed high and the SSPSTAT register will be set. The SSP1IF bit will not master state machine is no longer active. When the be set until the Baud Rate Generator has timed out. RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is Note1: If RSEN is programmed while any other loaded and begins counting. The SDA pin is released event is in progress, it will not take effect. (brought high) for one Baud Rate Generator count 2: A bus collision during the Repeated Start (TBRG). When the Baud Rate Generator times out, if condition occurs if: SDA is sampled high, the SCL pin will be deasserted • SDA is sampled low when SCL (brought high). When SCL is sampled high, the Baud goes from low-to-high. Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This • SCL goes low before SDA is action is then followed by assertion of the SDA pin asserted low. This may indicate (SDA=0) for one TBRG while SCL is high. SCL is that another master is attempting asserted low. Following this, the RSEN bit of the SSP- to transmit a data ‘1’. FIGURE 26-27: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPCON2 occurs here At completion of Start bit, SDA = 1, SDA = 1, hardware clears RSEN bit SCL (no change) SCL = 1 and sets SSP1IF TBRG TBRG TBRG SDA 1st bit Write to SSPBUF occurs here TBRG SCL Sr TBRG Repeated Start DS40001579E-page 290  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.6.6 I2C MASTER MODE TRANSMISSION 26.6.6.3 ACKSTAT Status Flag Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit of the SSPCON2 other half of a 10-bit address is accomplished by simply register is cleared when the slave has sent an Acknowl- writing a value to the SSPBUF register. This action will edge (ACK=0) and is set when the slave does not set the Buffer Full flag bit, BF and allow the Baud Rate Acknowledge (ACK=1). A slave sends an Acknowl- Generator to begin counting and start the next trans- edge when it has recognized its address (including a mission. Each bit of address/data will be shifted out general call), or when the slave has properly received onto the SDA pin after the falling edge of SCL is its data. asserted. SCL is held low for one Baud Rate Generator 26.6.6.4 Typical transmit sequence: rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it 1. The user generates a Start condition by setting is held that way for TBRG. The data on the SDA pin the SEN bit of the SSPCON2 register. must remain stable for that duration and some hold 2. SSP1IF is set by hardware on completion of the time after the next falling edge of SCL. After the eighth Start. bit is shifted out (the falling edge of the eighth clock), 3. SSP1IF is cleared by software. the BF flag is cleared and the master releases SDA. 4. The MSSP module will wait the required start This allows the slave device being addressed to time before any other operation takes place. respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received 5. The user loads the SSPBUF with the slave properly. The status of ACK is written into the address to transmit. ACKSTAT bit on the rising edge of the ninth clock. If the 6. Address is shifted out the SDA pin until all 8 bits master receives an Acknowledge, the Acknowledge are transmitted. Transmission begins as soon Status bit, ACKSTAT, is cleared. If not, the bit is set. as SSPBUF is written to. After the ninth clock, the SSP1IF bit is set and the mas- 7. The MSSP module shifts in the ACK bit from the ter clock (Baud Rate Generator) is suspended until the slave device and writes its value into the next data byte is loaded into the SSPBUF, leaving SCL ACKSTAT bit of the SSPCON2 register. low and SDA unchanged (Figure26-27). 8. The MSSP module generates an interrupt at the After the write to the SSPBUF, each bit of the address end of the ninth clock cycle by setting the will be shifted out on the falling edge of SCL until all SSP1IF bit. seven address bits and the R/W bit are completed. On 9. The user loads the SSPBUF with eight bits of the falling edge of the eighth clock, the master will data. release the SDA pin, allowing the slave to respond with 10. Data is shifted out the SDA pin until all 8 bits are an Acknowledge. On the falling edge of the ninth clock, transmitted. the master will sample the SDA pin to see if the address 11. The MSSP module shifts in the ACK bit from the was recognized by a slave. The status of the ACK bit is slave device and writes its value into the loaded into the ACKSTAT Status bit of the SSPCON2 ACKSTAT bit of the SSPCON2 register. register. Following the falling edge of the ninth clock 12. Steps 8-11 are repeated for all transmitted data transmission of the address, the SSP1IF is set, the BF bytes. flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, 13. The user generates a Stop or Restart condition holding SCL low and allowing SDA to float. by setting the PEN or RSEN bits of the SSP- CON2 register. Interrupt is generated once the 26.6.6.1 BF Status Flag Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPSTAT register is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 26.6.6.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission.  2011-2014 Microchip Technology Inc. DS40001579E-page 291

PIC16(L)F1782/3 FIGURE 26-28: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) ACKSTAT in SSPCON2 = 1 P ared by software K e C 9 Cl A > <6 D0 8 e 2 n slave, clear ACKSTAT bit SSPCON Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared by software service routifrom SSP interrupt SSPBUF is written by software om D7 1 1IF Fr w SP o S = 0 SCL held lwhile CPUsponds to CK re R/W = 0 A1A ss and R/W 789 d by hardware ave A2 ddre 6 eare PCON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPBUF written with 7-bit astart transmit 12345 Cleared by software SSPBUF written After Start condition, SEN cl Sn Write SStart co S <0>) T A T S 1IF SSP SDA SCL SSP BF ( SEN PEN R/W DS40001579E-page 292  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.6.7 I2C MASTER MODE RECEPTION 26.6.7.4 Typical Receive Sequence: Master mode reception is enabled by programming the 1. The user generates a Start condition by setting Receive Enable bit, RCEN bit of the SSPCON2 the SEN bit of the SSPCON2 register. register. 2. SSP1IF is set by hardware on completion of the Note: The MSSP module must be in an Idle Start. state before the RCEN bit is set or the 3. SSP1IF is cleared by software. RCEN bit will be disregarded. 4. User writes SSPBUF with the slave address to transmit and the R/W bit set. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes 5. Address is shifted out the SDA pin until all 8 bits (high-to-low/low-to-high) and data is shifted into the are transmitted. Transmission begins as soon SSPSR. After the falling edge of the eighth clock, the as SSPBUF is written to. receive enable flag is automatically cleared, the 6. The MSSP module shifts in the ACK bit from the contents of the SSPSR are loaded into the SSPBUF, slave device and writes its value into the the BF flag bit is set, the SSP1IF flag bit is set and the ACKSTAT bit of the SSPCON2 register. Baud Rate Generator is suspended from counting, 7. The MSSP module generates an interrupt at the holding SCL low. The MSSP is now in Idle state end of the ninth clock cycle by setting the awaiting the next command. When the buffer is read by SSP1IF bit. the CPU, the BF flag bit is automatically cleared. The 8. User sets the RCEN bit of the SSPCON2 register user can then send an Acknowledge bit at the end of and the master clocks in a byte from the slave. reception by setting the Acknowledge Sequence 9. After the 8th falling edge of SCL, SSP1IF and Enable, ACKEN bit of the SSPCON2 register. BF are set. 26.6.7.1 BF Status Flag 10. User clears the SSP1IF bit and reads the received byte from SSPUF, which clears the BF flag. In receive operation, the BF bit is set when an address 11. The user either clears the SSPCON2 register’s or data byte is loaded into SSPBUF from SSPSR. It is ACKDT bit to receive another byte or sets the cleared when the SSPBUF register is read. ADKDT bit to suppress further data and then initi- 26.6.7.2 SSPOV Status Flag ates the acknowledge sequence by setting the ACKEN bit. In receive operation, the SSPOV bit is set when 8 bits 12. Master’s ACK or ACK is clocked out to the slave are received into the SSPSR and the BF flag bit is and SSP1IF is set. already set from a previous reception. 13. User clears SSP1IF. 26.6.7.3 WCOL Status Flag 14. Steps 8-13 are repeated for each received byte If the user writes the SSPBUF when a receive is from the slave. already in progress (i.e., SSPSR is still shifting in a data 15. If the ACKST bit was set in step 11 then the user byte), the WCOL bit is set and the contents of the buffer can send a STOP to release the bus. are unchanged (the write does not occur).  2011-2014 Microchip Technology Inc. DS40001579E-page 293

PIC16(L)F1782/3 FIGURE 26-29: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) pt Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from MasterMaster configured as a receiverSDA = ACKDT = SDA = ACKDT = 10by programming SSPCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten hereom Slavenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1ACKD0WACK Bus masterACK is not sentterminatestransfer9967895876512343124PSet SSP1IF at endData shifted in on falling edge of CLKof receiveSet SSP1IF interruat end of Acknow-Set SSP1IF interruptSet SSP1IF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared by softwareCleared by softwareCleared by software(SSPSTAT<4>)Cleared insoftwareand SSP1IF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Master configured as a receiverRCEN clearedACK from MasterRCEN clearedSDA = ACKDT = automatically0by programming SSPCON2<3> (RCEN = )automatically1 K fr R/ 8 AC A1 7 Write to SSPCON2<0>(SEN = ),1begin Start condition SEN = 0Write to SSPBUF occurs here,start XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 361245SCLS SSP1IF Cleared by softwareSDA = , SCL = 01while CPU responds to SSP1IF BF (SSPSTAT<0>) SSPOV ACKEN RCEN DS40001579E-page 294  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.6.8 ACKNOWLEDGE SEQUENCE 26.6.9 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPCON2 register. At the end of a SSPCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDA pin. If the user wishes to the master will assert the SDA line low. When the SDA generate an Acknowledge, then the ACKDT bit should line is sampled low, the Baud Rate Generator is be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate before starting an Acknowledge sequence. The Baud Generator times out, the SCL pin will be brought high Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count) (TBRG) and the SCL pin is deasserted (pulled high). later, the SDA pin will be deasserted. When the SDA When the SCL pin is sampled high (clock arbitration), pin is sampled high while SCL is high, the P bit of the the Baud Rate Generator counts for TBRG. The SCL pin SSPSTAT register is set. A TBRG later, the PEN bit is is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSP1IF bit is set (Figure26-30). matically cleared, the Baud Rate Generator is turned off 26.6.9.1 WCOL Status Flag and the MSSP module then goes into Idle mode (Figure26-29). If the user writes the SSPBUF when a Stop sequence is in progress, then the WCOL bit is set and the 26.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does If the user writes the SSPBUF when an Acknowledge not occur). sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 26-30: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSP1IF Cleared in SSP1IF set at Cleared in software the end of receive software SSP1IF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period.  2011-2014 Microchip Technology Inc. DS40001579E-page 295

PIC16(L)F1782/3 FIGURE 26-31: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSP1IF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 26.6.10 SLEEP OPERATION 26.6.13 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C slave module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 26.6.11 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, 26.6.12 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCL1IF and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure26-31). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit of the SSPSTAT register is set, SSPBUF can be written to. When the user services the or the bus is Idle, with both the S and P bits clear. When bus collision Interrupt Service Routine and if the I2C the bus is busy, enabling the SSP interrupt will bus is free, the user can resume communication by generate the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge monitored for arbitration to see if the signal level is the condition was in progress when the bus collision expected output level. This check is performed by occurred, the condition is aborted, the SDA and SCL hardware with the result placed in the BCL1IF bit. lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user The states where arbitration can be lost are: services the bus collision Interrupt Service Routine and • Address Transfer if the I2C bus is free, the user can resume communica- • Data Transfer tion by asserting a Start condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSP1IF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. DS40001579E-page 296  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 26-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data does not match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCL1IF) BCL1IF  2011-2014 Microchip Technology Inc. DS40001579E-page 297

PIC16(L)F1782/3 26.6.13.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure26-34). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure26-32). counts down to zero; if the SCL pin is sampled as ‘0’ b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the (Figure26-33). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a fac- pins are monitored. tor during a Start condition is that no two bus masters can assert a Start condition If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: at the exact same time. Therefore, one master will always assert SDA before the • the Start condition is aborted, other. This condition does not cause a bus • the BCL1IF flag is set and collision because the two masters must be • the MSSP module is reset to its Idle state allowed to arbitrate the first address (Figure26-32). following the Start condition. If the address The Start condition begins with the SDA and SCL pins is the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded and counts down. If the Start or Stop conditions. SCL pin is sampled low while SDA is high, a bus colli- sion occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 26-33: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCL1IF, S bit and SSP1IF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCL1IF. S bit and SSP1IF set because BCL1IF SDA = 0, SCL = 1. SSP1IF and BCL1IF are cleared by software S SSP1IF SSP1IF and BCL1IF are cleared by software DS40001579E-page 298  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 26-34: BUS COLLISION DURING START CONDITION (SCL=0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCL1IF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCL1IF. BCL1IF Interrupt cleared by software S ’0’ ’0’ SSP1IF ’0’ ’0’ FIGURE 26-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSP1IF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCL1IF ’0’ S SSP1IF SDA = 0, SCL = 1, Interrupts cleared set SSP1IF by software  2011-2014 Microchip Technology Inc. DS40001579E-page 299

PIC16(L)F1782/3 26.6.13.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure26-35). If SDA is sampled high, the BRG is reloaded and begins During a Repeated Start condition, a bus collision counting. If SDA goes from high-to-low before the BRG occurs if: times out, no bus collision occurs because no two a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time. from low level to high level. If SCL goes from high-to-low before the BRG times out b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision indicating that another master is attempting to occurs. In this case, another master is attempting to transmit a data ‘1’. transmit a data ‘1’ during the Repeated Start condition, When the user releases SDA and the pin is allowed to see Figure26-36. float high, the BRG is loaded with SSPADD and counts If, at the end of the BRG time-out, both SCL and SDA down to zero. The SCL pin is then deasserted and are still high, the SDA pin is driven low and the BRG is when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 26-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCL1IF and release SDA and SCL. RSEN BCL1IF Cleared by software S ’0’ SSP1IF ’0’ FIGURE 26-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCL1IF set BCL1IF. Release SDA and SCL. Interrupt cleared by software RSEN ’0’ S SSP1IF DS40001579E-page 300  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.6.13.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD and a) After the SDA pin has been deasserted and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure26-37). If the SCL pin is sampled low before SDA goes high. low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure26-38). FIGURE 26-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCL1IF SDA SDA asserted low SCL PEN BCL1IF P ’0’ SSP1IF ’0’ FIGURE 26-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCL1IF SCL PEN BCL1IF P ’0’ SSP1IF ’0’  2011-2014 Microchip Technology Inc. DS40001579E-page 301

PIC16(L)F1782/3 TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: APFCON C2OUTSEL CCP1SEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 111 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — C3IE CCP2IE 81 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — C3IF CCP2IF 84 SSP1ADD ADD<7:0> 309 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 260* SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 306 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 307 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 306 SSP1MSK MSK<7:0> 309 SSP1STAT SMP CKE D/A P S R/W UA BF 304 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA0 125 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode. * Page provides register information. Note 1: PIC16(L)F1783 only. DS40001579E-page 302  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 26.7 BAUD RATE GENERATOR clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being The MSSP module has a Baud Rate Generator operated in. available for clock generation in both I2C and SPI Table26-4 demonstrates clock rates based on Master modes. The Baud Rate Generator (BRG) instruction cycles and the BRG value loaded into reload value is placed in the SSPADD register SSPADD. (Register26-6). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting EQUATION 26-1: down. Once the given operation is complete, the internal clock FOSC will automatically stop counting and the clock pin will FCLOCK = ------------------------------------------------- SSPxADD+14 remain in its last state. An internal signal “Reload” in Figure26-39 triggers the value from SSPADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module FIGURE 26-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPADD<7:0> SSPM<3:0> Reload Reload SCL Control SSPCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 26-4: MSSP CLOCK RATE W/BRG FCLOCK FOSC FCY BRG Value (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz(1) 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application.  2011-2014 Microchip Technology Inc. DS40001579E-page 303

PIC16(L)F1782/3 26.8 Register Definitions: MSSP Control REGISTER 26-1: SSPSTAT: SSP STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I 2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I 2 C™ mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated DS40001579E-page 304  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 26-1: SSPSTAT: SSP STATUS REGISTER (CONTINUED) bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I 2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty  2011-2014 Microchip Technology Inc. DS40001579E-page 305

PIC16(L)F1782/3 REGISTER 26-2: SSPCON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register (must be cleared in software). 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I 2 C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C Master mode: Unused in this mode bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5) 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: When enabled, the SDA and SCL pins must be configured as inputs. 4: SSPADD values of 0, 1 or 2 are not supported for I2C mode. 5: SSPADD value of ‘0’ is not supported. Use SSPM = 0000 instead. DS40001579E-page 306  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 26-3: SSPCON2: SSP CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKMSSP Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).  2011-2014 Microchip Technology Inc. DS40001579E-page 307

PIC16(L)F1782/3 REGISTER 26-4: SSPCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the SSPCON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPBUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSP- CON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSPCON1 register and SCL is held low. 0 = Data holding is disabled Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF=1, but hardware continues to write the most recent byte to SSPBUF. 2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. 3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. DS40001579E-page 308  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 26-5: SSPMSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 26-6: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode — Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.  2011-2014 Microchip Technology Inc. DS40001579E-page 309

PIC16(L)F1782/3 27.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer • Half-duplex synchronous master independent of device program execution. The • Half-duplex synchronous slave EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous Interface (SCI), can be configured as a full-duplex modes asynchronous system or half-duplex synchronous • Sleep operation system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT The EUSART module implements the following terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems: with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate circuits, serial EEPROMs or other microcontrollers. • Wake-up on Break reception These devices typically do not have internal clocks for • 13-bit Break character transmit baud rate generation and require the external clock signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and receiver are shown in Figure27-1 and Figure27-2. FIGURE 27-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREG Register TXIF 8 MSb LSb TX/CK pin (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT SPEN Baud Rate Generator FOSC ÷ n TX9 BRG16 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 X 0 0 0 SPBRGH SPBRGL BRGH X 1 1 0 0 BRG16 X 1 0 1 0 DS40001579E-page 310  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 27-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN OERR RCIDL RX/DT pin MSb RSR Register LSb Panind BCuoffnetrrol DRaetcaovery Stop (8) 7 • • • 1 0 START Baud Rate Generator FOSC RX9 ÷ n BRG16 n + 1 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 FIFO SPBRGH SPBRGL BRGH X 1 1 0 0 FERR RX9D RCREG Register BRG16 X 1 0 1 0 8 Data Bus RCIF Interrupt RCIE The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These registers are detailed in Register27-1, Register27-2 and Register27-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output.  2011-2014 Microchip Technology Inc. DS40001579E-page 311

PIC16(L)F1782/3 27.1 EUSART Asynchronous Mode 27.1.1.2 Transmitting Data The EUSART transmits and receives data using the A transmission is initiated by writing a character to the standard non-return-to-zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the implemented with two levels: a VOH mark state which previous character has been completely flushed from represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXREG is immediately represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains consecutively transmitted data bits of the same value all or part of a previous character, the new character stay at the output level of that bit without returning to a data is held in the TXREG until the Stop bit of the neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending transmission port idles in the Mark state. Each character character in the TXREG is then transferred to the TSR transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits or nine data bits and is always terminated by one or and Stop bit sequence commences immediately more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data following the transfer of the data to the TSR from the format is 8 bits. Each transmitted bit persists for a period TXREG. of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud 27.1.1.3 Transmit Data Polarity Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table27-5 The polarity of the transmit data can be controlled with for examples of baud rate configurations. the SCKP bit of the BAUDxCON register. The default state of this bit is ‘0’ which selects high true transmit idle The EUSART transmits and receives the LSb first. The and data bits. Setting the SCKP bit to ‘1’ will invert the EUSART’s transmitter and receiver are functionally transmit data resulting in low true idle and data bits. The independent, but share the same data format and baud SCKP bit controls transmit data polarity in rate. Parity is not supported by the hardware, but can Asynchronous mode only. In Synchronous mode, the be implemented in software and stored as the ninth SCKP bit has a different function. See Section27.5.1.2 data bit. “Clock Polarity”. 27.1.1 EUSART ASYNCHRONOUS 27.1.1.4 Transmit Interrupt Flag TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set The EUSART transmitter block diagram is shown in whenever the EUSART transmitter is enabled and no Figure27-1. The heart of the transmitter is the serial character is being held for transmission in the TXREG. Transmit Shift Register (TSR), which is not directly In other words, the TXIF bit is only clear when the TSR accessible by software. The TSR obtains its data from is busy with a character and a new character has been the transmit buffer, which is the TXREG register. queued for transmission in the TXREG. The TXIF flag bit 27.1.1.1 Enabling the Transmitter is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following The EUSART transmitter is enabled for asynchronous the write execution. Polling TXIF immediately following operations by configuring the following three control the TXREG write will return invalid results. The TXIF bit bits: is read-only, it cannot be set or cleared by software. • TXEN = 1 The TXIF interrupt can be enabled by setting the TXIE • SYNC = 0 interrupt enable bit of the PIE1 register. However, the • SPEN = 1 TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. All other EUSART control bits are assumed to be in their default state. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the Setting the TXEN bit of the TXSTA register enables the TXIE interrupt enable bit upon writing the last character transmitter circuitry of the EUSART. Clearing the SYNC of the transmission to the TXREG. bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set. DS40001579E-page 312  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 27.1.1.5 TSR Status 27.1.1.7 Asynchronous Transmission Set-up: The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRGL register pair and status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired TRMT bit is set when the TSR register is empty and is baud rate (see Section27.4 “EUSART Baud cleared when a character is transferred to the TSR Rate Generator (BRG)”). register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit. No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 poll this bit to determine the TSR status. control bit. A set ninth data bit will indicate that Note: The TSR register is not mapped in data the 8 Least Significant data bits are an address memory, so it is not available to the user. when the receiver is set for address detection. 4. Set SCKP bit if inverted transmit is desired. 27.1.1.6 Transmitting 9-Bit Characters 5. Enable the transmission by setting the TXEN The EUSART supports 9-bit character transmissions. control bit. This will cause the TXIF interrupt bit When the TX9 bit of the TXSTA register is set, the to be set. EUSART will shift 9 bits out for each character transmit- 6. If interrupts are desired, set the TXIE interrupt ted. The TX9D bit of the TXSTA register is the ninth, enable bit of the PIE1 register. An interrupt will and Most Significant, data bit. When transmitting 9-bit occur immediately provided that the GIE and data, the TX9D data bit must be written before writing PEIE bits of the INTCON register are also set. the eight Least Significant bits into the TXREG. All 9 7. If 9-bit transmission is selected, the ninth bit bits of data will be transferred to the TSR shift register should be loaded into the TX9D data bit. immediately after the TXREG is written. 8. Load 8-bit data into the TXREG register. This A special 9-bit Address mode is available for use with will start the transmission. multiple receivers. See Section27.1.2.7 “Address Detection” for more information on the address mode. FIGURE 27-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg. (Transmit Shift Reg. Empty Flag)  2011-2014 Microchip Technology Inc. DS40001579E-page 313

PIC16(L)F1782/3 FIGURE 27-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Transmit Buffer Reg. Empty Flag) 1 TCY TRMT bit Word 1 Word 2 (Transmit Shift Transmit Shift Reg. Transmit Shift Reg. Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 27-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 111 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 322 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 321 SPBRGL BRG<7:0> 323 SPBRGH BRG<15:8> 323 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 TXREG EUSART Transmit Data Register 312* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 320 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission. * Page provides register information. DS40001579E-page 314  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 27.1.2 EUSART ASYNCHRONOUS 27.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit, systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data Figure27-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts the baud rate, whereas the serial Receive Shift character reception, without generating an error, and Register (RSR) operates at the bit rate. When all 8 or 9 resumes looking for the falling edge of the Start bit. If bits of the character have been shifted in, they are the Start bit zero verification succeeds then the data immediately transferred to a two character recovery circuit counts a full bit time to the center of the First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. start of a third character before software must start This repeats until all data bits have been sampled and servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always Access to the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this 27.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this character. See Section27.1.2.4 “Receive Framing The EUSART receiver is enabled for asynchronous Error” for more information on framing errors. operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have • CREN = 1 been received, the character in the RSR is transferred • SYNC = 0 to the EUSART receive FIFO and the RCIF interrupt • SPEN = 1 flag bit of the PIR1 register is set. The top character in All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the their default state. RCREG register. Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun of the TXSTA register configures the EUSART for condition is cleared. See Section27.1.2.5 asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more RCSTA register enables the EUSART. The programmer information on overrun errors. must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. 27.1.2.3 Receive Interrupts Note: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is cleared for the receiver to function. an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: • RCIE, Interrupt Enable bit of the PIE1 register • PEIE, Peripheral Interrupt Enable bit of the INTCON register • GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.  2011-2014 Microchip Technology Inc. DS40001579E-page 315

PIC16(L)F1782/3 27.1.2.4 Receive Framing Error 27.1.2.7 Address Detection Each character in the receive FIFO buffer has a A special Address Detection mode is available for use corresponding framing error Status bit. A framing error when multiple receivers share the same transmission indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA FERR bit of the RCSTA register. The FERR bit register. represents the status of the top unread character in the Address detection requires 9-bit character reception. receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters before reading the RCREG. with the ninth data bit set will be transferred to the The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt unread character in the receive FIFO. A framing error bit. All other characters will be ignored. (FERR = 1) does not preclude reception of additional Upon receiving an address character, user software characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon Reading the next character from the FIFO buffer will address match, user software must disable address advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next corresponding framing error. Stop bit occurs. When user software detects the end of The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit. affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. 27.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 27.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. DS40001579E-page 316  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 27.1.2.8 Asynchronous Reception Set-up: 27.1.2.9 9-bit Address Detection Mode Set-up 1. Initialize the SPBRGH, SPBRGL register pair This mode would typically be used in RS-485 systems. and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section27.4 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRGL register pair 2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the 3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section27.4 “EUSART The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”). operation. 2. Clear the ANSEL bit for the RX pin (if applicable). 4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit. PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous INTCON register. operation. 5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the 6. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the 7. The RCIF interrupt flag bit will be set when a INTCON register. character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit. receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN the RCIE interrupt enable bit was also set. bit. 8. Read the RCSTA register to get the error flags 7. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit register. was also set. 10. If an overrun occurred, clear the OERR flag by 9. Read the RCSTA register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. FIGURE 27-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg. Word 1 Word 2 RCREG RCREG RCIDL Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.  2011-2014 Microchip Technology Inc. DS40001579E-page 317

PIC16(L)F1782/3 TABLE 27-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 111 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 322 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 RCREG EUSART Receive Data Register 315* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 321 SPBRGL BRG<7:0> 323 SPBRGH BRG<15:8> 323 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 320 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception. * Page provides register information. DS40001579E-page 318  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 27.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section6.2.2 “Internal Clock Sources” for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section27.4.1 “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.  2011-2014 Microchip Technology Inc. DS40001579E-page 319

PIC16(L)F1782/3 27.3 Register Definitions: EUSART Control REGISTER 27-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS40001579E-page 320  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 REGISTER 27-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.  2011-2014 Microchip Technology Inc. DS40001579E-page 321

PIC16(L)F1782/3 REGISTER 27-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS40001579E-page 322  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 27.4 EUSART Baud Rate Generator EXAMPLE 27-1: CALCULATING BAUD (BRG) RATE ERROR The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. FOSC Desired Baud Rate = ------------------------------------------------------------------------ By default, the BRG operates in 8-bit mode. Setting the 64[SPBRGH:SPBRGL]+1 BRG16 bit of the BAUDCON register selects 16-bit Solving for SPBRGH:SPBRGL: mode. FOSC The SPBRGH, SPBRGL register pair determines the --------------------------------------------- Desired Baud Rate period of the free running baud rate timer. In X = ---------------------------------------------–1 64 Asynchronous mode the multiplier of the baud rate 16000000 period is determined by both the BRGH bit of the TXSTA ------------------------ 9600 register and the BRG16 bit of the BAUDCON register. In = ------------------------–1 64 Synchronous mode, the BRGH bit is ignored. = 25.042 = 25 Table27-3 contains the formulas for determining the baud rate. Example27-1 provides a sample calculation 16000000 Calculated Baud Rate = --------------------------- for determining the baud rate and baud rate error. 6425+1 Typical baud rates and error values for various = 9615 asynchronous modes have been computed for your convenience and are shown in Table27-3. It may be Calc. Baud Rate–Desired Baud Rate Error = -------------------------------------------------------------------------------------------- advantageous to use the high baud rate (BRGH = 1), Desired Baud Rate or the 16-bit BRG (BRG16 = 1) to reduce the baud rate 9615–9600 error. The 16-bit BRG mode is used to achieve slow = ---------------------------------- = 0.16% 9600 baud rates for fast oscillator frequencies. Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock.  2011-2014 Microchip Technology Inc. DS40001579E-page 323

PIC16(L)F1782/3 TABLE 27-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair TABLE 27-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 322 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 321 SPBRGL BRG<7:0> 323 SPBRGH BRG<15:8> 323 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 320 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator. * Page provides register information. DS40001579E-page 324  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 27-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5  2011-2014 Microchip Technology Inc. DS40001579E-page 325

PIC16(L)F1782/3 TABLE 27-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — DS40001579E-page 326  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 27-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —  2011-2014 Microchip Technology Inc. DS40001579E-page 327

PIC16(L)F1782/3 27.4.1 AUTO-BAUD DETECT and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. Note1: If the WUE bit is set with the ABDEN bit, In the Auto-Baud Detect (ABD) mode, the clock to the auto-baud detection will occur on the byte BRG is reversed. Rather than the BRG clocking the following the Break character (see incoming RX signal, the RX signal is timing the BRG. Section27.4.3 “Auto-Wake-up on The Baud Rate Generator is used to time the period of Break”). a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the that it has five rising edges including the Stop bit edge. incoming character baud rate is within the range of the selected BRG clock source. Setting the ABDEN bit of the BAUDCON register starts Some combinations of oscillator frequency the auto-baud calibration sequence (Figure27-6). and EUSART baud rates are not possible. While the ABD sequence takes place, the EUSART state machine is held in idle. On the first rising edge of 3: During the auto-baud process, the the receive line, after the Start bit, the SPBRG begins auto-baud counter starts counting at 1. counting up using the BRG counter clock as shown in Upon completion of the auto-baud Table27-6. The fifth rising edge will occur on the RX pin sequence, to achieve maximum accuracy, at the end of the eighth bit period. At that time, an subtract 1 from the SPBRGH:SPBRGL accumulated value totaling the proper BRG period is register pair. left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag TABLE 27-6: BRG COUNTER CLOCK RATES is set. The value in the RCREG needs to be read to BRG Base BRG ABD clear the RCIF interrupt. RCREG content should be BRG16 BRGH Clock Clock discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the 0 0 FOSC/64 FOSC/512 SPBRGL register did not overflow by checking for 00h in the SPBRGH register. 0 1 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 1 0 FOSC/16 FOSC/128 and BRGH bits as shown in Table27-6. During ABD, 1 1 FOSC/4 FOSC/32 both the SPBRGH and SPBRGL registers are used as Note: During the ABD sequence, SPBRGL and a 16-bit counter, independent of the BRG16 bit setting. SPBRGH registers are both used as a 16-bit While calibrating the baud rate period, the SPBRGH counter, independent of BRG16 setting. FIGURE 27-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL XXh 1Ch SPBRGH XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. DS40001579E-page 328  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 27.4.2 AUTO-BAUD OVERFLOW 27.4.3.1 Special Considerations During the course of automatic baud detection, the Break Character ABDOVF bit of the BAUDCON register will be set if the To avoid character errors or character fragments during baud rate counter overflows before the fifth rising edge a wake-up event, the wake-up character must be all is detected on the RX pin. The ABDOVF bit indicates zeros. that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register When the wake-up is enabled the function works pair. After the ABDOVF bit has been set, the counter independent of the low time on the data stream. If the continues to count until the fifth rising edge is detected WUE bit is set and a valid non-zero character is on the RX pin. Upon detecting the fifth RX edge, the received, the low time from the Start bit to the first rising hardware will set the RCIF interrupt flag and clear the edge will be interpreted as the wake-up event. The ABDEN bit of the BAUDCON register. The RCIF flag remaining bits in the character will be received as a can be subsequently cleared by reading the RCREG fragmented character and subsequent characters can register. The ABDOVF flag of the BAUDCON register result in framing or overrun errors. can be cleared by software directly. Therefore, the initial character in the transmission must To terminate the auto-baud process before the RCIF be all ‘0’s. This must be ten or more bit times, 13-bit flag is set, clear the ABDEN bit then clear the ABDOVF times recommended for LIN bus, or any number of bit bit of the BAUDCON register. The ABDOVF bit will times for standard RS-232 devices. remain set if the ABDEN bit is not cleared first. Oscillator Start-up Time Oscillator start-up time must be considered, especially 27.4.3 AUTO-WAKE-UP ON BREAK in applications using oscillators with longer start-up During Sleep mode, all clocks to the EUSART are intervals (i.e., LP, XT or HS/PLL mode). The Sync suspended. Because of this, the Baud Rate Generator Break (or wake-up signal) character must be of is inactive and a proper character reception cannot be sufficient length, and be followed by a sufficient performed. The Auto-Wake-up feature allows the interval, to allow enough time for the selected oscillator controller to wake-up due to activity on the RX/DT line. to start and provide proper initialization of the EUSART. This feature is available only in Asynchronous mode. WUE Bit The Auto-Wake-up feature is enabled by setting the The wake-up event causes a receive interrupt by WUE bit of the BAUDCON register. Once set, the normal setting the RCIF bit. The WUE bit is cleared in receive sequence on RX/DT is disabled, and the hardware by a rising edge on RX/DT. The interrupt EUSART remains in an Idle state, monitoring for a condition is then cleared in software by reading the wake-up event independent of the CPU mode. A RCREG register and discarding its contents. wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break To ensure that no actual data is lost, check the RCIDL or a wake-up signal character for the LIN protocol.) bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not The EUSART module generates an RCIF interrupt occurring, the WUE bit may then be set just prior to coincident with the wake-up event. The interrupt is entering the Sleep mode. generated synchronously to the Q clocks in normal CPU operating modes (Figure27-7), and asynchronously if the device is in Sleep mode (Figure27-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.  2011-2014 Microchip Technology Inc. DS40001579E-page 329

PIC16(L)F1782/3 FIGURE 27-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note1: The EUSART remains in idle while the WUE bit is set. FIGURE 27-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RX/DT Line Note 1 RCIF Cleared due to User Read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in idle while the WUE bit is set. DS40001579E-page 330  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 27.4.4 BREAK CHARACTER SEQUENCE 27.4.5 RECEIVING A BREAK CHARACTER The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break special Break character sequences that are required by character in two ways. the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the received data To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is bits of the TXSTA register. The Break character assumed to have been initialized to the expected baud transmission is then initiated by a write to the TXREG. rate. The value of data written to TXREG will be ignored and A Break character has been received when; all ‘0’s will be transmitted. • RCIF bit is set The SENDB bit is automatically reset by hardware after • FERR bit is set the corresponding Stop bit is sent. This allows the user • RCREG = 00h to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature character in the LIN specification). described in Section27.4.3 “Auto-Wake-up on Break”. By enabling this feature, the EUSART will The TRMT bit of the TXSTA register indicates when the sample the next two transitions on RX/DT, cause an transmit operation is active or idle, just as it does during RCIF interrupt, and receive the next data byte followed normal transmission. See Figure27-9 for the timing of by another interrupt. the Break character sequence. Note that following a Break character, the user will 27.4.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature. The following sequence will start a message frame For both methods, the user can set the ABDEN bit of header made up of a Break, followed by an auto-baud the BAUDCON register before placing the EUSART in Sync byte. This sequence is typical of a LIN bus Sleep mode. master. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to enable the Break sequence. 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. FIGURE 27-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit)  2011-2014 Microchip Technology Inc. DS40001579E-page 331

PIC16(L)F1782/3 27.5 EUSART Synchronous Mode Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising Synchronous serial communications are typically used edge of each clock. in systems with a single master and one or more slaves. The master device contains the necessary 27.5.1.3 Synchronous Master Transmission circuitry for baud rate generation and supplies the clock Data is transferred out of the device on the RX/DT pin. for all devices in the system. Slave devices can take The RX/DT and TX/CK pin output drivers are automat- advantage of the master clock by eliminating the ically enabled when the EUSART is configured for internal clock generation circuitry. synchronous master transmit operation. There are two signal lines in Synchronous mode: a A transmission is initiated by writing a character to the bidirectional data line and a clock line. Slaves use the TXREG register. If the TSR still contains all or part of a external clock supplied by the master to shift the serial previous character the new character data is held in the data into and out of their respective receive and trans- TXREG until the last bit of the previous character has mit shift registers. Since the data line is bidirectional, been transmitted. If this is the first character, or the synchronous operation is half-duplex only. Half-duplex previous character has been completely flushed from refers to the fact that master and slave devices can the TSR, the data in the TXREG is immediately trans- receive and transmit data but not both simultaneously. ferred to the TSR. The transmission of the character The EUSART can operate as either a master or slave commences immediately following the transfer of the device. data to the TSR from the TXREG. Start and Stop bits are not used in synchronous Each data bit changes on the leading edge of the transmissions. master clock and remains valid until the subsequent leading clock edge. 27.5.1 SYNCHRONOUS MASTER MODE The following bits are used to configure the EUSART Note: The TSR register is not mapped in data for synchronous master operation: memory, so it is not available to the user. • SYNC = 1 27.5.1.4 Synchronous Master Transmission • CSRC = 1 Set-up: • SREN = 0 (for transmit); SREN = 1 (for receive) 1. Initialize the SPBRGH, SPBRGL register pair • CREN = 0 (for transmit); CREN = 1 (for receive) and the BRGH and BRG16 bits to achieve the • SPEN = 1 desired baud rate (see Section27.4 “EUSART Setting the SYNC bit of the TXSTA register configures Baud Rate Generator (BRG)”). the device for synchronous operation. Setting the CSRC 2. Enable the synchronous master serial port by bit of the TXSTA register configures the device as a setting bits SYNC, SPEN and CSRC. master. Clearing the SREN and CREN bits of the RCSTA 3. Disable Receive mode by clearing bits SREN register ensures that the device is in the Transmit mode, and CREN. otherwise the device will be configured to receive. Setting 4. Enable Transmit mode by setting the TXEN bit. the SPEN bit of the RCSTA register enables the 5. If 9-bit transmission is desired, set the TX9 bit. EUSART. 6. If interrupts are desired, set the TXIE bit of the 27.5.1.1 Master Clock PIE1 register and the GIE and PEIE bits of the INTCON register. Synchronous data transfers use a separate clock line, 7. If 9-bit transmission is selected, the ninth bit which is synchronous with the data. A device config- should be loaded in the TX9D bit. ured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled 8. Start transmission by loading data to the TXREG when the EUSART is configured for synchronous register. transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. 27.5.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. DS40001579E-page 332  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 27-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 27-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 27-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 111 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 322 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 321 SPBRGL BRG<7:0> 323 SPBRGH BRG<15:8> 323 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 TXREG EUSART Transmit Data Register 312* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 320 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission. * Page provides register information.  2011-2014 Microchip Technology Inc. DS40001579E-page 333

PIC16(L)F1782/3 27.5.1.5 Synchronous Master Reception will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. Data is received at the RX/DT pin. The RX/DT pin If the overrun error occurred when the SREN bit is set output driver is automatically disabled when the and CREN is clear then the error is cleared by reading EUSART is configured for synchronous master receive RCREG. If the overrun occurred when the CREN bit is operation. set then the error condition is cleared by either clearing In Synchronous mode, reception is enabled by setting the CREN bit of the RCSTA register or by clearing the either the Single Receive Enable bit (SREN of the SPEN bit which resets the EUSART. RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). 27.5.1.8 Receiving 9-bit Characters When SREN is set and CREN is clear, only as many The EUSART supports 9-bit character reception. When clock cycles are generated as there are data bits in a the RX9 bit of the RCSTA register is set the EUSART single character. The SREN bit is automatically cleared will shift 9-bits into the RSR for each character at the completion of one character. When CREN is set, received. The RX9D bit of the RCSTA register is the clocks are continuously generated until CREN is ninth, and Most Significant, data bit of the top unread cleared. If CREN is cleared in the middle of a character character in the receive FIFO. When reading 9-bit data the CK clock stops immediately and the partial charac- from the receive FIFO buffer, the RX9D data bit must ter is discarded. If SREN and CREN are both set, then be read before reading the eight Least Significant bits SREN is cleared at the completion of the first character from the RCREG. and CREN takes precedence. 27.5.1.9 Synchronous Master Reception To initiate reception, set either SREN or CREN. Data is Set-up: sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift 1. Initialize the SPBRGH, SPBRGL register pair for Register (RSR). When a complete character is the appropriate baud rate. Set or clear the received into the RSR, the RCIF bit is set and the char- BRGH and BRG16 bits, as required, to achieve acter is automatically transferred to the two character the desired baud rate. receive FIFO. The Least Significant eight bits of the top 2. Clear the ANSEL bit for the RX pin (if applicable). character in the receive FIFO are available in RCREG. 3. Enable the synchronous master serial port by The RCIF bit remains set as long as there are unread setting bits SYNC, SPEN and CSRC. characters in the receive FIFO. 4. Ensure bits CREN and SREN are clear. Note: If the RX/DT function is on an analog pin, 5. If interrupts are desired, set the RCIE bit of the the corresponding ANSEL bit must be PIE1 register and the GIE and PEIE bits of the cleared for the receiver to function. INTCON register. 6. If 9-bit reception is desired, set bit RX9. 27.5.1.6 Slave Clock 7. Start reception by setting the SREN bit or for Synchronous data transfers use a separate clock line, continuous reception, set the CREN bit. which is synchronous with the data. A device configured 8. Interrupt flag bit RCIF will be set when reception as a slave receives the clock on the TX/CK line. The of a character is complete. An interrupt will be TX/CK pin output driver is automatically disabled when generated if the enable bit RCIE was set. the device is configured for synchronous slave transmit 9. Read the RCSTA register to get the ninth bit (if or receive operation. Serial data bits change on the enabled) and determine if any error occurred leading edge to ensure they are valid at the trailing edge during reception. of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as 10. Read the 8-bit received data by reading the there are data bits. RCREG register. 11. If an overrun error occurs, clear the error by Note: If the device is configured as a slave and either clearing the CREN bit of the RCSTA the TX/CK function is on an analog pin, the register or by clearing the SPEN bit which resets corresponding ANSEL bit must be cleared. the EUSART. 27.5.1.7 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters DS40001579E-page 334  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 27-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 27-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 111 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 322 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 RCREG EUSART Receive Data Register 315* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 321 SPBRGL BRG<7:0> 323 SPBRGH BRG<15:8> 323 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 320 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception. * Page provides register information.  2011-2014 Microchip Technology Inc. DS40001579E-page 335

PIC16(L)F1782/3 27.5.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the EUSART for synchronous slave operation: 1. The first character will immediately transfer to the TSR register and transmit. • SYNC = 1 2. The second word will remain in TXREG register. • CSRC = 0 3. The TXIF bit will not be set. • SREN = 0 (for transmit); SREN = 1 (for receive) 4. After the first character has been shifted out of • CREN = 0 (for transmit); CREN = 1 (for receive) TSR, the TXREG register will transfer the second • SPEN = 1 character to the TSR and the TXIF bit will now be Setting the SYNC bit of the TXSTA register configures the set. device for synchronous operation. Clearing the CSRC bit 5. If the PEIE and TXIE bits are set, the interrupt of the TXSTA register configures the device as a slave. will wake the device from Sleep and execute the Clearing the SREN and CREN bits of the RCSTA register next instruction. If the GIE bit is also set, the ensures that the device is in the Transmit mode, program will call the Interrupt Service Routine. otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the 27.5.2.2 Synchronous Slave Transmission EUSART. Set-up: 27.5.2.1 EUSART Synchronous Slave 1. Set the SYNC and SPEN bits and clear the CSRC bit. Transmit 2. Clear the ANSEL bit for the CK pin (if applicable). The operation of the Synchronous Master and Slave 3. Clear the CREN and SREN bits. modes are identical (see Section27.5.1.3 “Synchronous Master Transmission”), except in the 4. If interrupts are desired, set the TXIE bit of the case of the Sleep mode. PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit transmission is desired, set the TX9 bit. 6. Enable transmission by setting the TXEN bit. 7. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 8. Start transmission by writing the Least Significant 8 bits to the TXREG register. TABLE 27-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 111 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 322 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 321 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 TXREG EUSART Transmit Data Register 312* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 320 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission. * Page provides register information. DS40001579E-page 336  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 27.5.2.3 EUSART Synchronous Slave 27.5.2.4 Synchronous Slave Reception Reception Set-up: The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the modes is identical (Section27.5.1.5 “Synchronous CSRC bit. Master Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins • Sleep (if applicable). • CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RCIE bit of the never idle PIE1 register and the GIE and PEIE bits of the INTCON register. • SREN bit, which is a “don’t care” in Slave mode 4. If 9-bit reception is desired, set the RX9 bit. A character may be received while in Sleep mode by 5. Set the CREN bit to enable reception. setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data 6. The RCIF bit will be set when reception is to the RCREG register. If the RCIE enable bit is set, the complete. An interrupt will be generated if the interrupt generated will wake the device from Sleep RCIE bit was set. and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTA register. 8. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 27-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 111 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 322 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 79 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 80 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 83 RCREG EUSART Receive Data Register 315* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 321 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 320 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception. * Page provides register information.  2011-2014 Microchip Technology Inc. DS40001579E-page 337

PIC16(L)F1782/3 27.6 EUSART Operation During Sleep 27.6.2 SYNCHRONOUS TRANSMIT DURING SLEEP The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the To transmit during Sleep, all the following conditions system clock and therefore cannot generate the must be met before entering Sleep mode: necessary signals to run the Transmit or Receive Shift • RCSTA and TXSTA Control registers must be registers during Sleep. configured for synchronous slave transmission Synchronous Slave mode uses an externally generated (see Section27.5.2.2 “Synchronous Slave clock to run the Transmit and Receive Shift registers. Transmission Set-up:”). • The TXIF interrupt flag must be cleared by writing 27.6.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the SLEEP TSR and transmit buffer. To receive during Sleep, all the following conditions • If interrupts are desired, set the TXIE bit of the must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON reg- ister. • RCSTA and TXSTA Control registers must be • Interrupt enable bits TXIE of the PIE1 register and configured for Synchronous Slave Reception (see PEIE of the INTCON register must set. Section27.5.2.4 “Synchronous Slave Reception Set-up:”). Upon entering Sleep mode, the device will be ready to • If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the PIE1 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been INTCON register. completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and • The RCIF interrupt flag must be cleared by read- the TXIF flag will be set. Thereby, waking the processor ing RCREG to unload any pending characters in from Sleep. At this point, the TXREG is available to the receive buffer. accept another character for transmission, which will Upon entering Sleep mode, the device will be ready to clear the TXIF flag. accept data and clocks on the RX/DT and TX/CK pins, Upon waking from Sleep, the instruction following the respectively. When the data word has been completely SLEEP instruction will be executed. If the Global clocked in by the external device, the RCIF interrupt Interrupt Enable (GIE) bit is also set then the Interrupt flag bit of the PIR1 register will be set. Thereby, waking Service Routine at address 0004h will be called. the processor from Sleep. Upon waking from Sleep, the instruction following the 27.6.3 ALTERNATE PIN LOCATIONS SLEEP instruction will be executed. If the Global Inter- This module incorporates I/O pins that can be moved to rupt Enable (GIE) bit of the INTCON register is also set, other locations with the use of the alternate pin function then the Interrupt Service Routine at address 004h will register, APFCON. To determine which pins can be be called. moved and what their default locations are upon a Reset, see Section13.1 “Alternate Pin Function” for more information. DS40001579E-page 338  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 28.0 IN-CIRCUIT SERIAL 28.3 Common Programming Interfaces PROGRAMMING™ (ICSP™) Connection to a target device is typically done through an ICSP™ header. A commonly found connector on ICSP™ programming allows customers to manufacture development tools is the RJ-11 in the 6P6C (6-pin, 6 circuit boards with unprogrammed devices. Programming connector) configuration. See Figure28-1. can be done after the assembly process, allowing the device to be programmed with the most recent firmware FIGURE 28-1: ICD RJ-11 STYLE or a custom firmware. Five pins are needed for ICSP™ programming: CONNECTOR INTERFACE • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS ICSPDAT 2 4 6 NC In Program/Verify mode the program memory, user IDs VDD ICSPCLK and the Configuration Words are programmed through 1 3 5 Target serial communications. The ICSPDAT pin is a VPP/MCLR VSS PC Board bidirectional I/O used for transferring the serial data Bottom Side and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16(L)F178X Memory Programming Specification” (DS41457). Pin Description* 1 = VPP/MCLR 28.1 High-Voltage Programming Entry 2 = VDD Target Mode 3 = VSS (ground) The device is placed into High-Voltage Programming 4 = ICSPDAT Entry mode by holding the ICSPCLK and ICSPDAT 5 = ICSPCLK pins low then raising the voltage on MCLR/VPP to VIHH. 6 = No Connect 28.2 Low-Voltage Programming Entry Mode Another connector often found in use with the PICkit™ The Low-Voltage Programming Entry mode allows the programmers is a standard 6-pin header with 0.1inch PIC® Flash MCUs to be programmed using VDD only, spacing. Refer to Figure28-2. without high voltage. When the LVP bit of Configuration For additional interface recommendations, refer to your Words is set to ‘1’, the low-voltage ICSP programming specific device programmer manual prior to PCB entry is enabled. To disable the Low-Voltage ICSP design. mode, the LVP bit must be programmed to ‘0’. It is recommended that isolation devices be used to Entry into the Low-Voltage Programming Entry mode separate the programming pins from other circuitry. requires the following steps: The type of isolation is highly dependent on the specific 1. MCLR is brought to VIL. application and may include devices such as resistors, diodes, or even jumpers. See Figure28-3 for more 2. A 32-bit key sequence is presented on information. ICSPDAT, while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section5.5 “MCLR” for more information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode.  2011-2014 Microchip Technology Inc. DS40001579E-page 339

PIC16(L)F1782/3 FIGURE 28-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 1 = VPP/MCLR 2 2 = VDD Target 3 4 3 = VSS (ground) 5 4 = ICSPDAT 6 5 = ICSPCLK 6 = No Connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins. FIGURE 28-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming VDD Device to be Signals Programmed VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). DS40001579E-page 340  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations Each instruction is a 14-bit word containing the Any instruction that specifies a file register as part of operation code (opcode) and all required operands. the instruction performs a Read-Modify-Write (R-M-W) The opcodes are broken into three broad categories. operation. The register is read, the data is modified, and the result is stored according to either the instruc- • Byte Oriented tion, or the destination designator ‘d’. A read operation • Bit Oriented is performed on a register even if the instruction writes • Literal and Control to that register. The literal and control category contains the most varied instruction word format. TABLE 29-1: OPCODE FIELD DESCRIPTIONS Table29-3 lists the instructions recognized by the MPASMTM assembler. Field Description All instructions are executed within a single instruction f Register file address (0x00 to 0x7F) cycle, with the following exceptions, which may take W Working register (accumulator) two or three cycles: b Bit address within an 8-bit file register • Subroutine takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two k Literal field, constant data or label cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1). • Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0. BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for • One additional instruction cycle will be used when compatibility with all Microchip software tools. any instruction references an indirect file register d Destination select; d = 0: store result in W, and the file select register is pointing to program d = 1: store result in file register f. memory. Default is d = 1. One instruction cycle consists of 4 oscillator cycles; for n FSR or INDF number. (0-1) an oscillator frequency of 4 MHz, this gives a nominal mm Pre-post increment-decrement mode instruction execution rate of 1 MHz. selection All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a TABLE 29-2: ABBREVIATION hexadecimal digit. DESCRIPTIONS Field Description PC Program Counter TO Time-out bit C Carry bit DC Digit carry bit Z Zero bit PD Power-down bit  2011-2014 Microchip Technology Inc. DS40001579E-page 341

PIC16(L)F1782/3 FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value MOVLP instruction only 13 7 6 0 OPCODE k (literal) k = 7-bit immediate value MOVLB instruction only 13 5 4 0 OPCODE k (literal) k = 5-bit immediate value BRA instruction only 13 9 8 0 OPCODE k (literal) k = 9-bit immediate value FSR Offset instructions 13 7 6 5 0 OPCODE n k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 3 2 1 0 OPCODE n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE DS40001579E-page 342  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 29-3: INSTRUCTION SET Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2 ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2 ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2 LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2 LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0000 00xx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 2 INCF f, d Increment f 1 00 1010 dfff ffff Z 2 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 2 MOVWF f Move W to f 1 00 0000 1fff ffff 2 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2 SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 2 BIT-ORIENTED SKIP OPERATIONS BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2 LITERAL OPERATIONS ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLB k Move literal to BSR 1 00 0000 001k kkkk MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk MOVLW k Move literal to W 1 11 0000 kkkk kkkk SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.  2011-2014 Microchip Technology Inc. DS40001579E-page 343

PIC16(L)F1782/3 TABLE 29-3: INSTRUCTION SET (CONTINUED) Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected CONTROL OPERATIONS BRA k Relative Branch 2 11 001k kkkk kkkk BRW – Relative Branch with W 2 00 0000 0000 1011 CALL k Call Subroutine 2 10 0kkk kkkk kkkk CALLW – Call Subroutine with W 2 00 0000 0000 1010 GOTO k Go to address 2 10 1kkk kkkk kkkk RETFIE k Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 0100 kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 INHERENT OPERATIONS CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD NOP – No Operation 1 00 0000 0000 0000 OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010 RESET – Software device Reset 1 00 0000 0000 0001 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD TRIS f Load TRIS register with W 1 00 0000 0110 0fff C-COMPILER OPTIMIZED ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3 modifier, mm k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2 MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3 modifier, mm k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2 Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions. DS40001579E-page 344  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 29.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k Operands: -32  k  31 Operands: 0  k  255 n  [ 0, 1] Operation: (W) .AND. (k)  (W) Operation: FSR(n) + k  FSR(n) Status Affected: Z Status Affected: None Description: The contents of W register are Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The the contents of the FSRnH:FSRnL result is placed in the W register. register pair. FSRn is limited to the range 0000h - FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W ANDWF AND W with f Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d Operands: 0  k  255 Operands: 0  f  127 d 0,1 Operation: (W) + k  (W) Operation: (W) .AND. (f)  (destination) Status Affected: C, DC, Z Status Affected: Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the Description: AND the W register with register ‘f’. If result is placed in the W register. ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWF Add W and f ASRF Arithmetic Right Shift Syntax: [ label ] ADDWF f,d Syntax: [ label ] ASRF f {,d} Operands: 0  f  127 Operands: 0  f  127 d 0,1 d [0,1] Operation: (W) + (f)  (destination) Operation: (f<7>) dest<7> (f<7:1>)  dest<6:0>, Status Affected: C, DC, Z (f<0>)  C, Description: Add the contents of the W register Status Affected: C, Z with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the Description: The contents of register ‘f’ are shifted result is stored back in register ‘f’. one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in reg- ister ‘f’. ADDWFC ADD W and CARRY bit to f register f C Syntax: [ label ] ADDWFC f {,d} Operands: 0  f  127 d [0,1] Operation: (W) + (f) + (C)  dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data mem- ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.  2011-2014 Microchip Technology Inc. DS40001579E-page 345

PIC16(L)F1782/3 BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 0  b  7 0  b  7 Operation: 0  (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b [ label ] BRA $+k Operands: 0  f  127 Operands: -256label-PC+1255 0  b < 7 -256  k  255 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k  PC Status Affected: None Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Description: Add the signed 9-bit literal ‘k’ to the instruction is executed. PC. Since the PC will have incre- If bit ‘b’ is ‘1’, then the next mented to fetch the next instruction, instruction is discarded and a NOP is the new address will be PC+1+k. executed instead, making this a This instruction is a 2-cycle instruc- 2-cycle instruction. tion. This branch has a limited range. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W)  PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incre- mented to fetch the next instruction, the new address will be PC+1+(W). This instruction is a 2-cycle instruc- tion. BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0  f  127 0  b  7 Operation: 1  (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. DS40001579E-page 346  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<6:3>)  PC<14:11> 1  TO Status Affected: None 1  PD Description: Call Subroutine. First, return address Status Affected: TO, PD (PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch- The eleven-bit immediate address is dog Timer. It also resets the prescaler loaded into PC bits <10:0>. The upper of the WDT. bits of the PC are loaded from Status bits TO and PD are set. PCLATH. CALL is a 2-cycle instruc- tion. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: (PC) +1  TOS, (W)  PC<7:0>, Operation: (f)  (destination) (PCLATH<6:0>) PC<14:8> Status Affected: Z Description: The contents of register ‘f’ are com- Status Affected: None plemented. If ‘d’ is ‘0’, the result is Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is return address (PC + 1) is pushed stored back in register ‘f’. onto the return stack. Then, the con- tents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a 2-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the and the Z bit is set. result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in regis- ter ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h  (W) 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set.  2011-2014 Microchip Technology Inc. DS40001579E-page 347

PIC16(L)F1782/3 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre- mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. is placed back in register ‘f’. If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is NOP is executed instead, making it a executed instead, making it a 2-cycle 2-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<6:3>  PC<14:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. The OR’ed with the 8-bit literal ‘k’. The 11-bit immediate value is loaded into result is placed in the W register. PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis- mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is is placed back in register ‘f’. placed back in register ‘f’. DS40001579E-page 348  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 LSLF Logical Left Shift MOVF Move f Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d Operands: 0  f  127 Operands: 0  f  127 d [0,1] d  [0,1] Operation: (f<7>)  C Operation: (f)  (dest) (f<6:0>)  dest<7:1> Status Affected: Z 0  dest<0> Description: The contents of register f is moved to Status Affected: C, Z a destination dependent upon the Description: The contents of register ‘f’ are shifted status of d. If d = 0, destination is W one bit to the left through the Carry flag. register. If d = 1, the destination is file A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, register f itself. d = 1 is useful to test a the result is placed in W. If ‘d’ is ‘1’, the file register since status flag Z is result is stored back in register ‘f’. affected. Words: 1 C register f 0 Cycles: 1 Example: MOVF FSR, 0 After Instruction LSRF Logical Right Shift W = value in FSR register Syntax: [ label ] LSRF f {,d} Z = 1 Operands: 0  f  127 d [0,1] Operation: 0  dest<7> (f<7:1>)  dest<6:0>, (f<0>)  C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘0’ is shifted into the MSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 0 register f C  2011-2014 Microchip Technology Inc. DS40001579E-page 349

PIC16(L)F1782/3 MOVIW Move INDFn to W MOVLP Move literal to PCLATH Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k [ label ] MOVIW --FSRn Operands: 0  k  127 [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-- Operation: k  PCLATH [ label ] MOVIW k[FSRn] Status Affected: None Operands: n  [0,1] Description: The 7-bit literal ‘k’ is loaded into the mm  [00,01, 10, 11] PCLATH register. -32  k  31 Operation: INDFn  W Effective address is determined by MOVLW Move literal to W • FSR + 1 (preincrement) Syntax: [ label ] MOVLW k • FSR - 1 (predecrement) • FSR + k (relative offset) Operands: 0  k  255 After the Move, the FSR value will be Operation: k  (W) either: • FSR + 1 (all increments) Status Affected: None • FSR - 1 (all decrements) Description: The 8-bit literal ‘k’ is loaded into W reg- • Unchanged ister. The “don’t cares” will assemble as Status Affected: Z ‘0’s. Words: 1 Mode Syntax mm Cycles: 1 Preincrement ++FSRn 00 Example: MOVLW 0x5A Predecrement --FSRn 01 After Instruction W = 0x5A Postincrement FSRn++ 10 Postdecrement FSRn-- 11 MOVWF Move W to f Syntax: [ label ] MOVWF f Description: This instruction is used to move data between W and one of the indirect Operands: 0  f  127 registers (INDFn). Before/after this Operation: (W)  (f) move, the pointer (FSRn) is updated by Status Affected: None pre/post incrementing/decrementing it. Description: Move data from W register to register Note: The INDFn registers are not ‘f’. physical registers. Any instruction that Words: 1 accesses an INDFn register actually accesses the register at the address Cycles: 1 specified by the FSRn. Example: MOVWF OPTION_REG Before Instruction FSRn is limited to the range 0000h - OPTION_REG = 0xFF FFFFh. Incrementing/decrementing it W = 0x4F beyond these bounds will cause it to After Instruction wrap-around. OPTION_REG = 0x4F W = 0x4F MOVLB Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0  k  31 Operation: k  BSR Status Affected: None Description: The 5-bit literal ‘k’ is loaded into the Bank Select Register (BSR). DS40001579E-page 350  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] NOP Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn Operands: None [ label ] MOVWI FSRn++ Operation: No operation [ label ] MOVWI FSRn-- [ label ] MOVWI k[FSRn] Status Affected: None Operands: n  [0,1] Description: No operation. mm  [00,01, 10, 11] Words: 1 -32  k  31 Cycles: 1 Operation: W  INDFn Example: NOP Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be Load OPTION_REG Register either: OPTION with W • FSR + 1 (all increments) • FSR - 1 (all decrements) Syntax: [ label ] OPTION Unchanged Operands: None Status Affected: None Operation: (W)  OPTION_REG Status Affected: None Mode Syntax mm Description: Move data from W register to Preincrement ++FSRn 00 OPTION_REG register. Predecrement --FSRn 01 Postincrement FSRn++ 10 Words: 1 Postdecrement FSRn-- 11 Cycles: 1 Example: OPTION Description: This instruction is used to move data Before Instruction between W and one of the indirect OPTION_REG = 0xFF registers (INDFn). Before/after this W = 0x4F move, the pointer (FSRn) is updated by After Instruction pre/post incrementing/decrementing it. OPTION_REG = 0x4F W = 0x4F Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually RESET Software Reset accesses the register at the address specified by the FSRn. Syntax: [ label ] RESET Operands: None FSRn is limited to the range 0000h - FFFFh. Incrementing/decrementing it Operation: Execute a device Reset. Resets the beyond these bounds will cause it to RI flag of the PCON register. wrap-around. Status Affected: None The increment/decrement operation on Description: This instruction provides a way to FSRn WILL NOT affect any Status bits. execute a hardware Reset by soft- ware.  2011-2014 Microchip Technology Inc. DS40001579E-page 351

PIC16(L)F1782/3 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] RETFIE Syntax: [ label ] RETURN Operands: None Operands: None Operation: TOS  PC, Operation: TOS  PC 1  GIE Status Affected: None Status Affected: None Description: Return from subroutine. The stack is Description: Return from Interrupt. Stack is POPed POPed and the top of the stack (TOS) and Top-of-Stack (TOS) is loaded in is loaded into the program counter. the PC. Interrupts are enabled by This is a 2-cycle instruction. setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 RETLW Return with literal in W RLF Rotate Left f through Carry Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d Operands: 0  k  255 Operands: 0  f  127 Operation: k  (W); d  [0,1] TOS  PC Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the 8-bit literal ‘k’. The program counter is Description: The contents of register ‘f’ are rotated loaded from the top of the stack (the one bit to the left through the Carry return address). This is a 2-cycle flag. If ‘d’ is ‘0’, the result is placed in instruction. the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Words: 1 C Register f Cycles: 2 Example: CALL TABLE;W contains table Words: 1 ;offset value Cycles: 1 • ;W now has table value TABLE • Example: RLF REG1,0 • Before Instruction ADDWF PC ;W = offset REG1 = 1110 0110 RETLW k1 ;Begin table C = 0 RETLW k2 ; After Instruction • REG1 = 1110 0110 • W = 1100 1100 • C = 1 RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 DS40001579E-page 352  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 SUBLW Subtract W from literal RRF Rotate Right f through Carry Syntax: [ label ] SUBLW k Syntax: [ label ] RRF f,d Operands: 0 k 255 Operands: 0  f  127 d  [0,1] Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s com- plement method) from the 8-bit literal Description: The contents of register ‘f’ are rotated ‘k’. The result is placed in the W regis- one bit to the right through the Carry ter. flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is C = 0 W  k placed back in register ‘f’. C = 1 W  k C Register f DC = 0 W<3:0>  k<3:0> DC = 1 W<3:0>  k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] SLEEP Syntax: [ label ] SUBWF f,d Operands: None Operands: 0 f 127 d  [0,1] Operation: 00h  WDT, 0  WDT prescaler, Operation: (f) - (W) destination) 1  TO, Status Affected: C, DC, Z 0  PD Description: Subtract (2’s complement method) W Status Affected: TO, PD register from register ‘f’. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is result is stored in the W cleared. Time-out Status bit, TO is register. If ‘d’ is ‘1’, the result is stored set. Watchdog Timer and its pres- back in register ‘f. caler are cleared. The processor is put into Sleep mode C = 0 W  f with the oscillator stopped. C = 1 W  f DC = 0 W<3:0>  f<3:0> DC = 1 W<3:0>  f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB f {,d} Operands: 0  f  127 d  [0,1] Operation: (f) – (W) – (B) dest Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s comple- ment method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.  2011-2014 Microchip Technology Inc. DS40001579E-page 353

PIC16(L)F1782/3 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k Operands: 0  f  127 Operands: 0 k 255 d  [0,1] Operation: (W) .XOR. k W) Operation: (f<3:0>)  (destination<7:4>), Status Affected: Z (f<7:4>)  (destination<3:0>) Description: The contents of the W register are Status Affected: None XOR’ed with the 8-bit Description: The upper and lower nibbles of regis- literal ‘k’. The result is placed in the ter ‘f’ are exchanged. If ‘d’ is ‘0’, the W register. result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. TRIS Load TRIS Register with W XORWF Exclusive OR W with f Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d Operands: 5  f  7 Operands: 0  f  127 d  [0,1] Operation: (W)  TRIS register ‘f’ Operation: (W) .XOR. (f) destination) Status Affected: None Status Affected: Z Description: Move data from W register to TRIS register. Description: Exclusive OR the contents of the W When ‘f’ = 5, TRISA is loaded. register with register ‘f’. If ‘d’ is ‘0’, the When ‘f’ = 6, TRISB is loaded. result is stored in the W register. If ‘d’ When ‘f’ = 7, TRISC is loaded. is ‘1’, the result is stored back in regis- ter ‘f’. DS40001579E-page 354  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 30.0 ELECTRICAL SPECIFICATIONS 30.1 Absolute Maximum Ratings(†) Ambient temperature under bias...................................................................................................... -40°C to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on pins with respect to VSS on VDD pin PIC16F1782/3 ........................................................................................................... -0.3V to +6.5V PIC16LF1782/3 ......................................................................................................... -0.3V to +4.0V on MCLR pin ........................................................................................................................... -0.3V to +9.0V on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V) Maximum current on VSS pin(1) -40°C  TA  +85°C .............................................................................................................. 170 mA -40°C  TA  +125°C .............................................................................................................. 70 mA on VDD pin(1) -40°C  TA  +85°C ................................................................................................................ 85 mA -40°C  TA  +125°C .............................................................................................................. 35 mA on any I/O pin ..................................................................................................................................... 25 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Section30.4 “Thermal Considerations” to calculate device specifications. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.  2011-2014 Microchip Technology Inc. DS40001579E-page 355

PIC16(L)F1782/3 30.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: VDDMIN VDD VDDMAX Operating Temperature: TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC16LF1782/3 VDDMIN (Fosc  16 MHz).......................................................................................................... +1.8V VDDMIN (16 MHz < Fosc  32 MHz)......................................................................................... +2.7V VDDMAX.................................................................................................................................... +3.6V PIC16F1782/3 VDDMIN (Fosc  16 MHz).......................................................................................................... +2.3V VDDMIN (16 MHz < Fosc  32 MHz)......................................................................................... +2.7V VDDMAX.................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN...................................................................................................................................... -40°C TA_MAX.................................................................................................................................... +85°C Extended Temperature TA_MIN...................................................................................................................................... -40°C TA_MAX.................................................................................................................................. +125°C Note 1: See Parameter D001, DC Characteristics: Supply Voltage. DS40001579E-page 356  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 30-1: PIC16F1782/3 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C 5.5 ) V ( D D V 2.7 2.3 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-6 for each Oscillator mode’s supported frequencies. FIGURE 30-2: PIC16LF1782/3 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C V) 3.6 ( D D V 2.7 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-6 for each Oscillator mode’s supported frequencies.  2011-2014 Microchip Technology Inc. DS40001579E-page 357

PIC16(L)F1782/3 30.3 DC Characteristics TABLE 30-1: SUPPLY VOLTAGE PIC16LF1782/3 Standard Operating Conditions (unless otherwise stated) PIC16F1782/3 Param Sym. Characteristic Min. Typ† Max. Units Conditions . No. D001 VDD Supply Voltage (VDDMIN, VDDMAX) 1.8 — 3.6 V FOSC  16MHz: 2.7 — 3.6 V FOSC  32MHz (Note 2) D001 2.3 — 5.5 V FOSC  16MHz: 2.7 — 5.5 V FOSC  32MHz (Note 2) D002* VDR RAM Data Retention Voltage(1) 1.5 — — V Device in Sleep mode D002* 1.7 — — V Device in Sleep mode VPOR* Power-on Reset Release Voltage — 1.6 — V VPORR* Power-on Reset Rearm Voltage — 0.8 — V Device in Sleep mode — 1.5 — V Device in Sleep mode D003 VFVR Fixed Voltage Reference -4 — 4 % 1.024V, VDD  2.5V Voltage(3) -4 — 4 % 2.048V, VDD  2.5V -5 — 5 % 4.096V, VDD  4.75V D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See Section5.1 “Power-On Reset Power-on Reset signal (POR)” for details. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation. 3: Industrial temperature range only. DS40001579E-page 358  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 30-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(3) TPOR(2) Note 1: When NPOR is low, the device is held in Reset. 2: TPOR 1s typical. 3: TVLOW 2.7s typical.  2011-2014 Microchip Technology Inc. DS40001579E-page 359

PIC16(L)F1782/3 TABLE 30-2: SUPPLY VOLTAGE (IDD)(1,2) PIC16LF1782/3 Standard Operating Conditions (unless otherwise stated) PIC16F1782/3 Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note D009 LDO Regulator — 75 — A — High-Power mode, normal operation — 15 — A — Sleep VREGCON<1> = 0 — 0.3 — A — Sleep VREGCON<1> = 1 D010 — 8 20 A 1.8 FOSC = 32kHz — 12 24 A 3.0 LP Oscillator mode (Note 4), -40°C  TA  +85°C D010 — 18 63 A 2.3 FOSC = 32kHz — 20 74 A 3.0 LP Oscillator mode (Note 4, 5), -40°C  TA  +85°C — 22 79 A 5.0 D012 — 160 650 A 1.8 FOSC = 4MHz — 320 1000 A 3.0 XT Oscillator mode D012 — 260 700 A 2.3 FOSC = 4MHz — 330 1100 A 3.0 XT Oscillator mode (Note 5) — 380 1300 A 5.0 Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k 4: FVR and BOR are disabled. 5: 0.1F capacitor on VCAP. 6: 8 MHz crystal oscillator with 4x PLL enabled. DS40001579E-page 360  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 30-2: SUPPLY VOLTAGE (IDD)(1,2) (CONTINUED) PIC16LF1782/3 Standard Operating Conditions (unless otherwise stated) PIC16F1782/3 Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note D014 — 125 550 A 1.8 FOSC = 4MHz — 280 1100 A 3.0 EC Oscillator mode Medium-Power mode D014 — 220 650 A 2.3 FOSC = 4MHz — 290 1000 A 3.0 EC Oscillator mode (Note 5) Medium-Power mode — 350 1200 A 5.0 D015 — 2.1 6.2 mA 3.0 FOSC = 32MHz — 2.5 7.5 mA 3.6 EC Oscillator High-Power mode D015 — 2.1 6.5 mA 3.0 FOSC = 32MHz — 2.2 7.5 mA 5.0 EC Oscillator High-Power mode (Note 5) D017 — 130 180 A 1.8 FOSC = 500kHz — 150 250 A 3.0 MFINTOSC mode D017 — 150 250 A 2.3 FOSC = 500kHz — 170 330 A 3.0 MFINTOSC mode (Note 5) — 220 430 A 5.0 D019 — 0.8 2.2 mA 1.8 FOSC = 16MHz — 1.2 3.7 mA 3.0 HFINTOSC mode D019 — 1.0 2.3 mA 2.3 FOSC = 16MHz — 1.3 3.9 mA 3.0 HFINTOSC mode (Note 5) — 1.4 4.1 mA 5.0 D020 — 2.1 6.2 mA 3.0 FOSC = 32 MHz — 2.5 7.5 mA 3.6 HFINTOSC mode D020 — 2.1 6.5 mA 3.0 FOSC = 32 MHz — 2.2 7.5 mA 5.0 HFINTOSC mode D022 — 2.1 6.2 mA 3.0 FOSC = 32MHz — 2.5 7.5 mA 3.6 HS Oscillator mode (Note 6) D022 — 2.1 6.5 mA 3.0 FOSC = 32MHz — 2.2 7.5 mA 5.0 HS Oscillator mode (Note 5, 6) Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k 4: FVR and BOR are disabled. 5: 0.1F capacitor on VCAP. 6: 8 MHz crystal oscillator with 4x PLL enabled.  2011-2014 Microchip Technology Inc. DS40001579E-page 361

PIC16(L)F1782/3 TABLE 30-3: POWER-DOWN CURRENTS (IPD)(1,2,4) Operating Conditions: (unless otherwise stated) PIC16LF1782/3 Low-Power Sleep Mode PIC16F1782/3 Low-Power Sleep Mode, VREGPM = 1 Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D023 — 0.05 1.0 8.0 A 1.8 WDT, BOR, FVR, and T1OSC — 0.08 2.0 9.0 A 3.0 disabled, all Peripherals Inactive D023 — 0.3 3 11 A 2.3 WDT, BOR, FVR, and T1OSC — 0.4 4 12 A 3.0 disabled, all Peripherals Inactive — 0.5 6 15 A 5.0 D024 — 0.5 6 14 A 1.8 LPWDT Current — 0.8 7 17 A 3.0 D024 — 0.8 6 15 A 2.3 LPWDT Current — 0.9 7 20 A 3.0 — 1.0 8 22 A 5.0 D025 — 15 28 30 A 1.8 FVR Current — 18 30 33 A 3.0 D025 — 18 33 35 A 2.3 FVR Current — 19 35 37 A 3.0 — 20 37 39 A 5.0 D026 — 7.5 25 28 A 3.0 BOR Current D026 — 40 25 28 A 3.0 BOR Current — 87 28 31 A 5.0 D027 — 0.5 4 10 A 3.0 LPBOR Current D027 — 0.8 6 14 A 3.0 LPBOR Current — 1 8 17 A 5.0 D028 — 0.5 5 9 A 1.8 SOSC Current — 0.8 8.5 12 A 3.0 D028 — 1.1 6 10 A 2.3 SOSC Current — 1.3 8.5 20 A 3.0 — 1.4 10 25 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. 3: ADC oscillator source is FRC. 4: 0.1F capacitor on VCAP. 5: VREGPM = 0. DS40001579E-page 362  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 30-3: POWER-DOWN CURRENTS (IPD)(1,2,4) (CONTINUED) Operating Conditions: (unless otherwise stated) PIC16LF1782/3 Low-Power Sleep Mode PIC16F1782/3 Low-Power Sleep Mode, VREGPM = 1 Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D029 — 0.05 2 9 A 1.8 ADC Current (Note 3), — 0.08 3 10 A 3.0 no conversion in progress D029 — 0.3 4 12 A 2.3 ADC Current (Note 3), — 0.4 5 13 A 3.0 no conversion in progress — 0.5 7 16 A 5.0 D030 — 250 — — A 1.8 ADC Current (Note 3), — 280 — — A 3.0 conversion in progress D030 — 230 — — A 2.3 ADC Current (Note 3, Note 4, — 250 — — A 3.0 Note 5), conversion in progress — 350 — — A 5.0 D031 — 250 650 — A 3.0 Op Amp (High power) D031 250 650 — A 3.0 Op Amp (High power) (Note 5) — 350 650 — A 5.0 D032 — 250 650 — A 1.8 Comparator, Normal-Power mode — 300 700 — A 3.0 D032 — 280 650 — A 2.3 Comparator, Normal-Power mode — 300 700 — A 3.0 (Note 5) — 310 700 — A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. 3: ADC oscillator source is FRC. 4: 0.1F capacitor on VCAP. 5: VREGPM = 0.  2011-2014 Microchip Technology Inc. DS40001579E-page 363

PIC16(L)F1782/3 TABLE 30-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage I/O PORT: D034 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V D034A — — 0.15VDD V 1.8V  VDD  4.5V D035 with Schmitt Trigger buffer — — 0.2VDD V 2.0V  VDD  5.5V with I2C™ levels — — 0.3VDD V with SMBus levels — — 0.8 V 2.7V  VDD  5.5V D036 MCLR, OSC1 (RC mode)(1) — — 0.2VDD V D036A OSC1 (HS mode) — — 0.3VDD V VIH Input High Voltage I/O ports: D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V D040A 0.25VDD + — — V 1.8V  VDD  4.5V 0.8 D041 with Schmitt Trigger buffer 0.8VDD — — V 2.0V  VDD  5.5V with I2C™ levels 0.7VDD — — V with SMBus levels 2.1 — — V 2.7V  VDD  5.5V D042 MCLR 0.8VDD — — V D043A OSC1 (HS mode) 0.7VDD — — V D043B OSC1 (RC mode) 0.9VDD — — V (Note 1) IIL Input Leakage Current(2) D060 I/O ports — ± 5 ± 125 nA VSS  VPIN  VDD, Pin at high-impedance @ 85°C ± 5 ± 1000 nA 125°C D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD @ 85°C IPUR Weak Pull-up Current D070* 25 100 200 VDD = 3.3V, VPIN = VSS 25 140 300 A VDD = 5.0V, VPIN = VSS VOL Output Low Voltage(4) D080 I/O ports IOL = 8mA, VDD = 5V — — 0.6 V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V VOH Output High Voltage(4) D090 I/O ports IOH = 3.5mA, VDD = 5V VDD - 0.7 — — V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode. DS40001579E-page 364  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 30-4: I/O PORTS (CONTINUED) Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF VCAP Capacitor Charging D102 Charging current — 200 — A D102A Source/sink capability when — 0.0 — mA charging complete * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode.  2011-2014 Microchip Technology Inc. DS40001579E-page 365

PIC16(L)F1782/3 TABLE 30-5: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP/RE3 pin 8.0 — 9.0 V (Note 3) D111 IDDP Supply Current during — — 10 mA Programming D112 VDD for Bulk Erase 2.7 — VDDMAX V D113 VPEW VDD for Write or Row Erase VDDMIN — VDDMAX V D114 IPPPGM Current on MCLR/VPP during — — 1.0 mA Erase/Write D115 IDDPGM Current on VDD during Erase/Write — 5.0 mA Data EEPROM Memory D116 ED Byte Endurance 100K — — E/W -40C to +85C D117 VDRW VDD for Read/Write VDDMIN — VDDMAX V D118 TDEW Erase/Write Cycle Time — 4.0 5.0 ms D119 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D120 TREF Number of Total Erase/Write 100k — — E/W -40°C to +85°C Cycles before Refresh(2) Program Flash Memory D121 EP Cell Endurance 10K — — E/W -40C to +85C (Note 1) D122 VPR VDD for Read VDDMIN — VDDMAX V D123 TIW Self-timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Refer to Section12.2 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. DS40001579E-page 366  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 30.4 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance Junction to Ambient 60 C/W 28-pin SPDIP package 80 C/W 28-pin SOIC package 90 C/W 28-pin SSOP package 27.5 C/W 28-pin UQFN 4x4mm package 27.5 C/W 28-pin QFN 6x6mm package TH02 JC Thermal Resistance Junction to Case 31.4 C/W 28-pin SPDIP package 24 C/W 28-pin SOIC package 24 C/W 28-pin SSOP package 24 C/W 28-pin UQFN 4x4mm package 24 C/W 28-pin QFN 6x6mm package TH03 TJMAX Maximum Junction Temperature 150 C TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature 3: TJ = Junction Temperature  2011-2014 Microchip Technology Inc. DS40001579E-page 367

PIC16(L)F1782/3 30.5 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O PORT t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 30-4: LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins DS40001579E-page 368  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 30-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 30-6: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz EC Oscillator mode (low) DC — 4 MHz EC Oscillator mode (medium) DC — 20 MHz EC Oscillator mode (high) Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 4 MHz HS Oscillator mode 1 — 20 MHz HS Oscillator mode, VDD > 2.7V DC — 4 MHz RC Oscillator mode, VDD > 2.0V OS02 TOSC External CLKIN Period(1) 27 —  s LP Oscillator mode 250 —  ns XT Oscillator mode 50 —  ns HS Oscillator mode 50 —  ns EC Oscillator mode Oscillator Period(1) — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC OS04* TosH, External CLKIN High, 2 — — s LP oscillator TosL External CLKIN Low 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TosR, External CLKIN Rise, 0 —  ns LP oscillator TosF External CLKIN Fall 0 —  ns XT oscillator 0 —  ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.  2011-2014 Microchip Technology Inc. DS40001579E-page 369

PIC16(L)F1782/3 TABLE 30-7: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param Freq. Sym. Characteristic Min. Typ† Max. Units Conditions No. Tolerance OS08 HFOSC Internal Calibrated HFINTOSC ±2% — 16.0 — MHz 0°C  TA  +60°C, VDD 2.5V Frequency(2) ±3% — 16.0 — MHz 60°C TA 85°C, VDD 2.5V ±5% — 16.0 — MHz -40°C  TA  +125°C OS08A MFOSC Internal Calibrated MFINTOSC ±2% — 500 — kHz 0°C  TA  +60°C, VDD 2.5V Frequency(2) ±3% — 500 — kHz 60°C TA 85°C, VDD 2.5V ±5% — 500 — kHz -40°C  TA  +125°C OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz -40°C  TA  +125°C OS10* TIOSC ST HFINTOSC — — 3.2 8 s VREGPM = 0 Wake-up from Sleep Start-up Time MFINTOSC — — 24 35 s VREGPM = 0 Wake-up from Sleep Start-up Time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. 3: By design. FIGURE 30-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 ± 3% C) ° 60 re ( ± 2% u t a r e p 25 m e T 0 -20 ± 5% -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001579E-page 370  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 30-8: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 8 MHz F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz F12 TRC PLL Start-up Time (Lock Time) — — 2 ms F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% % * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19  2011-2014 Microchip Technology Inc. DS40001579E-page 371

PIC16(L)F1782/3 TABLE 30-9: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS11 TosH2ckL FOSC to CLKOUT (1) — — 70 ns VDD = 3.3-5.0V OS12 TosH2ckH FOSC to CLKOUT (1) — — 72 ns VDD = 3.3-5.0V OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3-5.0V OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns VDD = 3.3-5.0V (I/O in hold time) OS17 TioV2osH Port input valid to Fosc(Q2 cycle) 20 — — ns (I/O in setup time) OS18* TioR Port output rise time — 40 72 ns VDD = 1.8V — 15 32 VDD = 3.3-5.0V OS19* TioF Port output fall time — 28 55 ns VDD = 1.8V — 15 30 VDD = 3.3-5.0V OS20* Tinp INT pin input high or low time 25 — — ns OS21* Tioc Interrupt-on-change new input level 25 — — ns time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. DS40001579E-page 372  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 30-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 TPWRT Reset 33(1) (due to BOR) Note 1: The delay, (TPWRT) releasing Reset, only occurs when the Power-up Timer is enabled, (PWRTE=0).  2011-2014 Microchip Technology Inc. DS40001579E-page 373

PIC16(L)F1782/3 TABLE 30-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s VDD = 3.3-5V, -40°C to +85°C 5 — — s VDD = 3.3-5V 31 TWDTLP Low-Power Watchdog Timer 10 16 27 ms VDD = 3.3V-5V Time-out Period 1:16 Prescaler used 32 TOST Oscillator Start-up Timer Period(1), (2) — 1024 — Tosc (Note 3) 33* TPWRT Power-up Timer Period, PWRTE=0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low — — 2.0 s or Watchdog Timer Reset 35 VBOR Brown-out Reset Voltage 2.55 2.70 2.85 V BORV = 0 2.30 2.45 2.6 V BORV=1 (F device) 1.80 1.90 2.10 V BORV=1 (LF device) 35A VLPBOR Low-Power Brown-out 1.8 2.1 2.5 V LPBOR = 1 36* VHYST Brown-out Reset Hysteresis 0 25 75 mV -40°C to +85°C 37* TBORDC Brown-out Reset DC Response 1 3 5 s VDD  VBOR Time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. DS40001579E-page 374  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 30-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 TABLE 30-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value Period 30 or TCY + 40 (1, 2, 4, 8) N Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range 32.4 32.768 33.1 kHz (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync Increment mode * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2011-2014 Microchip Technology Inc. DS40001579E-page 375

PIC16(L)F1782/3 FIGURE 30-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure30-5 for load conditions. TABLE 30-12: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. CC01* TccL CCPx Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCPx Input Period 3TCY + 40 — — ns N = prescale value (1, 4 or 16) N * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001579E-page 376  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 30-13: ADC CONVERTER (ADC) 12-BIT DIFFERENTIAL CHARACTERISTICS: Operating Conditions VDD = 3V, Temp. = 25°C, Single-ended 2 s TAD, VREF+ = 3V, VREF- = VSS Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — ±1 ±1.6 LSb AD03 EDL Differential Error — ±1 ±1.4 LSb No missing codes AD04 EOFF Offset Error — ±1 ±3.5 LSb AD05 EGN Gain Error — ±1 ±2 LSb AD06 VREF Reference Voltage(3) 1.8 — VDD V VREF = (VREF+ minus VREF-) (Note 5) AD07 VAIN Full-Scale Range — — VREF V AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01F capacitor is Analog Voltage Source present on input pin. AD09 NR Resolution — — 12 bit AD10 EIL Integral Error — ±2 — LSb AD11 EDL Differential Error — ±2 — LSb AD12 EOFF Offset Error — ±1 — LSb AD13 EGN Gain Error — ±1 — LSb AD14 VREF Reference Voltage(3) 1.8 — VDD V VREF = (VREF+ minus VREF-) (Note 5) AD15 VAIN Full-Scale Range — — VREF V AD16 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01F capacitor is Analog Voltage Source present on input pin. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input. 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. 5: FVR voltage selected must be 2.048V or 4.096V. TABLE 30-14: ADC CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD130* TAD ADC Clock Period 1.0 — 9.0 s TOSC-based ADC Internal RC Oscillator 1.0 2.5 6.0 s ADCS<1:0> = 11 (ADRC mode) Period AD131 TCNV Conversion Time (not including — 15 (12-bit) — TAD Set GO/DONE bit to conversion Acquisition Time)(1) 13 (10-bit) complete AD132* TACQ Acquisition Time — 5.0 — s * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle.  2011-2014 Microchip Technology Inc. DS40001579E-page 377

PIC16(L)F1782/3 FIGURE 30-12: ADC CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 1 Tcy AD134 (TOSC/2(1)) AD131 Q4 AD130 ADC CLK ADC Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 Tcy GO DONE Sampling Stopped AD132 Sample Note1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. FIGURE 30-13: ADC CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 Tcy AD131 Q4 AD130 ADC CLK ADC Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 Tcy GO DONE Sampling Stopped AD132 Sample Note1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. DS40001579E-page 378  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 30-15: OPERATIONAL AMPLIFIER (OPA) Standard Operating Conditions (unless otherwise stated): DC CHARACTERISTICS VDD = 3.0 Temperature 25°C, High-Power Mode Param. Symbol Parameters Min. Typ. Max. Units Conditions No. OPA01* GBWP Gain Bandwidth Product — 2 — MHz High-Power mode OPA02* TON Turn on Time — 10 — s OPA03* PM Phase Margin — 40 — degrees OPA04* SR Slew Rate — 3 — V/s OPA05 OFF Offset — ±3 ±9 mV OPA06 CMRR Common Mode Rejection Ratio 55 70 — dB OPA07* AOL Open Loop Gain — 90 — dB OPA08 VICM Input Common Mode Voltage 0 — VDD V VDD > 2.5 OPA09* PSRR Power Supply Rejection Ratio — 80 — dB TABLE 30-16: COMPARATOR SPECIFICATIONS Operating Conditions: VDD = 3.0V, Temperature = 25°C (unless otherwise stated). Param. Sym. Characteristics Min. Typ. Max. Units Comments No. CM01 VIOFF Input Offset Voltage — ±2.5 ±9 mV Normal-Power mode VICM = VDD/2 CM02 VICM Input Common Mode Voltage 0 — VDD V CM03 CMRR Common Mode Rejection Ratio 40 50 — dB CM04A Response Time Rising Edge — 60 125 ns Normal-Power mode measured at VDD/2 (Note 1) CM04B Response Time Falling Edge — 60 110 ns Normal-Power mode measured at VDD/2 (Note 1) TRESP CM04C Response Time Rising Edge — 85 — ns Low-Power mode measured at VDD/2 (Note 1) CM04D Response Time Falling Edge — 85 — ns Low-Power mode measured at VDD/2 (Note 1) CM05 Tmc2ov Comparator Mode Change to — — 10 s Output Valid* CM06 CHYSTER Comparator Hysteresis 20 45 75 mV Hystersis ON, High Power measured at VDD/2 (Note 2) * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. 2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.  2011-2014 Microchip Technology Inc. DS40001579E-page 379

PIC16(L)F1782/3 TABLE 30-17: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions: VDD = 3V, Temperature = 25°C (unless otherwise stated). Param. Sym. Characteristics Min. Typ. Max. Units Comments No. DAC01* CLSB Step Size — VDD/256 — V DAC02* CACC Absolute Accuracy — —  1.5 LSb DAC03* CR Unit Resistor Value (R) — 600 —  DAC04* CST Settling Time(1) — — 10 s * These parameters are characterized but not tested. Note 1: Settling time measured while DACR<7:0> transitions from ‘0x00’ to ‘0xFF’. FIGURE 30-14: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US120 US122 Note: Refer to Figure30-4 for load conditions. TABLE 30-18: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Max. Units Conditions No. US120 TCKH2DTV SYNC XMIT (Master and Slave) 3.0-5.5V — 80 ns Clock high to data-out valid 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time 3.0-5.5V — 45 ns (Master mode) 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns FIGURE 30-15: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure30-4 for load conditions. DS40001579E-page 380  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 30-19: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Max. Units Conditions No. US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK  (DT hold time) 10 — ns US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns  2011-2014 Microchip Technology Inc. DS40001579E-page 381

PIC16(L)F1782/3 FIGURE 30-16: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SCK (CKP = 1) SP79 SP78 SP80 SDO MSb bit 6 - - - - - -1 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure30-4 for load conditions. FIGURE 30-17: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SP78 SDO MSb bit 6 - - - - - -1 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure30-4 for load conditions. DS40001579E-page 382  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 FIGURE 30-18: SPI SLAVE MODE TIMING (CKE=0) SS SP70 SCK SP83 (CKP = 0) SP71 SP72 SP78 SP79 SCK (CKP = 1) SP79 SP78 SP80 SDO MSb bit 6 - - - - - -1 LSb SP75, SP76 SP77 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure30-4 for load conditions. FIGURE 30-19: SPI SLAVE MODE TIMING (CKE=1) SP82 SS SP70 SCK SP83 (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure30-4 for load conditions.  2011-2014 Microchip Technology Inc. DS40001579E-page 383

PIC16(L)F1782/3 TABLE 30-20: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Symbol Characteristic Min. Typ† Max. Units Conditions No. SP70* TSSL2SCH, SS to SCK or SCK input 2.25*TCY — — ns TSSL2SCL SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns SP73* TDIV2SCH, Setup time of SDI data input to SCK edge 100 — — ns TDIV2SCL SP74* TSCH2DIL, Hold time of SDI data input to SCK edge 100 — — ns TSCL2DIL SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns 1.8-5.5V — 25 50 ns SP76* TDOF SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time 3.0-5.5V — 10 25 ns (Master mode) 1.8-5.5V — 25 50 ns SP79* TSCF SCK output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, SDO data output valid after 3.0-5.5V — — 50 ns TSCL2DOV SCK edge 1.8-5.5V — — 145 ns SP81* TDOV2SCH, SDO data output setup to SCK edge Tcy — — ns TDOV2SCL SP82* TSSL2DOV SDO data output valid after SS edge — — 50 ns SP83* TSCH2SSH, SS after SCK edge 1.5TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-20: I2C™ BUS START/STOP BITS TIMING SCL SP91 SP93 SP90 SP92 SDA Start Stop Condition Condition Note: Refer to Figure30-4 for load conditions. DS40001579E-page 384  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 TABLE 30-21: I2C™ BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Symbol Characteristic Min. Typ Max. Units Conditions No. SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — Start condition SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first Hold time 400 kHz mode 600 — — clock pulse is generated SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. FIGURE 30-21: I2C™ BUS DATA TIMING SP103 SP100 SP102 SP101 SCL SP90 SP106 SP107 SP91 SP92 SDA In SP110 SP109 SP109 SDA Out Note: Refer to Figure30-4 for load conditions.  2011-2014 Microchip Technology Inc. DS40001579E-page 385

PIC16(L)F1782/3 TABLE 30-22: I2C™ BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Max. Units Conditions No. SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP module 1.5TCY — SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP module 1.5TCY — SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF SP103* TF SDA and SCL fall 100 kHz mode — 250 ns time 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from 10-400 pF SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s SP107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2) time 400 kHz mode 100 — ns SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start SP111 CB Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT=1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS40001579E-page 386  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 NOTES:  2011-2014 Microchip Technology Inc. DS40001579E-page 387

PIC16(L)F1782/3 DS40001579E-page 388  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the L and LF devices. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.” represents (mean+3) or (mean-3) respectively, where  is a standard deviation, over each temperature range.  2011-2014 Microchip Technology Inc. DS40001579E-page 389

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. 14 35 Max: 85°C + 3σ Max. 12 MTyapxi:c a8l5: °2C5 °+C 3 σ Max. 30 Typical: 25°C 10 25 Typical I (μA) DD 68 Typical I (μA) DD1250 4 10 2 5 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-1: IDD, LP Oscillator Mode, FIGURE 31-2: IDD, LP Oscillator Mode, Fosc = 32 kHz, PIC16LF1782/3 Only. Fosc = 32 kHz, PIC16F1782/3 Only. 400 500 350 Typical: 25°C 450 Max: 85°C + 3σ 4 MHz XT 4 MHz XT 400 300 350 4 MHz EXTRC I (μA) DD220500 4 MHz EXTRC I (μA) DD223050000 1 MHz XT 150 1 MHz XT 150 100 100 50 1 MHz EXTRC 50 1 MHz EXTRC 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 31-3: IDD Typical, XT and EXTRC FIGURE 31-4: IDD Maximum, XT and Oscillator, PIC16LF1782/3 Only. EXTRC Oscillator, PIC16LF1782/3 Only. 450 600 400 Typical: 25°C 4 MHz XT Max: 85°C + 3σ 4 MHz XT 500 350 4 MHz EXTRC 300 400 4 MHz EXTRC I (μA) DD220500 1 MHz XT I (μA) DD300 1 MHz XT 150 200 100 1 MHz EXTRC 1 MHz EXTRC 100 50 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-5: IDD Typical, XT and EXTRC FIGURE 31-6: IDD Maximum, XT and Oscillator, PIC16F1782/3 Only. EXTRC Oscillator, PIC16F1782/3 Only. DS40001579E-page 390  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. 9 30 Max. 8 Max: 85°C + 3σ 25 MTyapxi:c a8l5: °2C5 °+C 3 σ Max. 7 Typical: 25°C Typical Typical 6 20 I (μA) DD 45 I (μA) DD 15 3 10 2 5 1 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-7: IDD, EC Oscillator LP Mode, FIGURE 31-8: IDD, EC Oscillator LP Mode, Fosc = 32 kHz, PIC16LF1782/3 Only. Fosc = 32 kHz, PIC16F1782/3 Only. , , , 60 70 Max: 85°C + 3σ Max. 50 MTyapxi:c a8l5: °2C5 °+C 3 σ Max. 60 Typical: 25°C 50 40 Typical I (μA) DD 30 Typical I (μA) DD 3400 20 20 10 10 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-9: IDD, EC Oscillator LP Mode, FIGURE 31-10: IDD, EC Oscillator LP Mode, Fosc = 500 kHz, PIC16LF1782/3 Only. Fosc = 500 kHz, PIC16F1782/3 Only. 350 400 300 Typical: 25°C 4 MHz 350 Max: 85°C + 3σ 4 MHz 300 250 250 I (μA) DD125000 I (μA) DD200 150 100 1 MHz 1 MHz 100 50 50 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 31-11: IDD Typical, EC Oscillator FIGURE 31-12: IDD Maximum, EC Oscillator MP Mode, PIC16LF1782/3 Only. MP Mode, PIC16LF1782/3 Only.  2011-2014 Microchip Technology Inc. DS40001579E-page 391

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. 400 450 350 Typical: 25°C 400 Max: 85°C + 3σ 4 MHz 4 MHz 350 300 300 I (μA) DD220500 I (μA) DD220500 1 MHz 1 MHz 150 150 100 100 50 50 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-13: IDD Typical, EC Oscillator FIGURE 31-14: IDD Maximum, EC Oscillator MP Mode, PIC16F1782/3 Only. MP Mode, PIC16F1782/3 Only. yp , , g 3.0 3.5 Typical: 25°C Max: 85°C + 3σ 3.0 2.5 32 MHz 32 MHz 2.5 2.0 I (mA) DD1.5 16 MHz I (mA) DD 12..50 16 MHz 1.0 1.0 8 MHz 8 MHz 0.5 0.5 0.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 31-15: IDD Typical, EC Oscillator FIGURE 31-16: IDD Maximum, EC Oscillator HP Mode, PIC16LF1782/3 Only. HP Mode, PIC16LF1782/3 Only. yp , , g 2.5 3.0 TTyyppiiccaall:: 2255°°CC 32 MHz Max: 85°C + 3σ 32 MHz 2.5 2.0 2.0 A) 1.5 A) I (mDD 1.0 16 MHz I (mDD 1.5 16 MHz 8 MHz 1.0 8 MHz 0.5 0.5 0.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-17: IDD Typical, EC Oscillator FIGURE 31-18: IDD Maximum, EC Oscillator HP Mode, PIC16F1782/3 Only. HP Mode, PIC16F1782/3 Only. DS40001579E-page 392  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. 9 30 Max. 8 Max: 85°C + 3σ Max. Typical: 25°C 25 7 6 Typical 20 Typical I(μA) DD 45 I (μA) DD15 3 10 2 5 Max: 85°C + 3σ 1 Typical: 25°C 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-19: IDD, LFINTOSC Mode, FIGURE 31-20: IDD, LFINTOSC Mode, Fosc=31kHz, PIC16LF1782/3 Only. Fosc=31kHz, PIC16F1782/3 Only. 600 700 550 Max: 85°C + 3σ Max. Max: 85°C + 3σ Max. 600 Typical: 25°C 500 Typical: 25°C Typical 450 500 I (μA) DD334050000 Typical I (μA) DD400 300 250 200 200 150 100 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-21: IDD, MFINTOSC Mode, FIGURE 31-22: IDD, MFINTOSC Mode, Fosc=500kHz, PIC16LF1782/3 Only. Fosc=500kHz, PIC16F1782/3 Only. 1.8 1.8 16 MHz 1.6 Typical: 25°C 16 MHz 1.6 Max: 85°C + 3σ 1.4 1.4 1.2 1.2 8 MHz mA) 1.0 8 MHz mA) 1.0 I (DD 0.8 4 MHz I (DD 0.8 4 MHz 2 MHz 0.6 2 MHz 0.6 0.4 0.4 1 MHz 1 MHz 0.2 0.2 0.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 31-23: IDD Typical, HFINTOSC FIGURE 31-24: IDD Maximum, HFINTOSC Mode, PIC16LF1782/3 Only. Mode, PIC16LF1782/3 Only.  2011-2014 Microchip Technology Inc. DS40001579E-page 393

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. 1.6 1.8 16 MHz 1.4 Typical: 25°C 1.6 Max: 85°C + 3σ 16 MHz 1.2 1.4 1.0 8 MHz 1.2 8 MHz I (mA) DD 00..68 4 MHz 2 MHz I (mA) DD 01..80 4 MHz 2 MHz 0.6 0.4 1 MHz 1 MHz 0.4 0.2 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-25: IDD Typical, HFINTOSC FIGURE 31-26: IDD Maximum, HFINTOSC Mode, PIC16F1782/3 Only. Mode, PIC16F1782/3 Only. yp , , 2.0 2.0 1.8 20 MHz 1.8 Max: 85°C + 3σ 20 MHz 1.6 1.6 16 MHz 1.4 1.4 I (mA) DD 011...802 168 M MHHzz I (mA) DD 011...802 8 MHz 0.6 0.6 0.4 0.4 4 MHz 4 MHz 0.2 0.2 0.0 0.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 31-27: IDD Typical, HS Oscillator, FIGURE 31-28: IDD Maximum, HS Oscillator, 25°C, PIC16LF1782/3 Only. PIC16LF1782/3 Only. 2.0 2.1 Max: 85°C + 3σ 20 MHz 1.8 20 MHz 1.8 1.6 16 MHz 1.4 16 MHz 1.5 I (mA) DD 011...802 8 MHz I (mA) DD 01..92 48 MMHHzz 0.6 0.6 0.4 4 MHz 0.3 0.2 0.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-29: IDD Typical, HS Oscillator, FIGURE 31-30: IDD Maximum, HS Oscillator, 25°C, PIC16F1782/3 Only. PIC16F1782/3 Only. DS40001579E-page 394  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. 4.0 4.0 Max. Max. 3.5 3.5 3.0 3.0 2.5 2.5 I (mA) DD 12..50 Typical I (mA) DD 12..50 Typical 1.0 1.0 0.5 TMyapxi:c a8l5: °2C5 °+C 3 σ 0.5 TMyapxi:c a8l5: °2C5 °+C 3 σ 0.0 0.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-31: IDD, HS Oscillator, 32 MHz FIGURE 31-32: IDD, HS Oscillator, 32 MHz (8 MHz + 4x PLL), PIC16LF1782/3 Only. (8 MHz + 4x PLL), PIC16F1782/3 Only. p , ( ) 450 1.2 400 Max. Max. 1.0 350 300 0.8 I (nA) PD 220500 MTyapxi:c a8l5: °2C5 °+C 3 σ I (μA) PD 0.6 MTyapxi:c a8l5: °2C5 °+C 3 σ 150 0.4 Typical 100 Typical 0.2 50 0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-33: IPD Base, LP Sleep Mode, FIGURE 31-34: IPD Base, LP Sleep Mode PIC16LF1782/3 Only. (VREGPM = 1), PIC16F1782/3 Only. 3.0 2.5 Max: 85°C + 3σ Typical: 25°C Max: 85°C + 3σ 2.5 Typical: 25°C 2.0 Max. 2.0 Max. I (μA) PD 1.5 I (μA) PD 11..05 1.0 Typical Typical 0.5 0.5 0.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-35: IPD, Watchdog Timer (WDT), FIGURE 31-36: IPD, Watchdog Timer (WDT), PIC16LF1782/3 Only. PIC16F1782/3 Only.  2011-2014 Microchip Technology Inc. DS40001579E-page 395

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. p , g ( ) 35 35 MTyapxi:c a8l5: °2C5 °+C 3 σ Max. 30 30 Max. 25 25 Typical I (nA) PD20 I (nA) PD 1250 Typical 15 10 10 5 MTyapxi:c a8l5: °2C5 °+C 3 σ 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-37: IPD, Fixed Voltage Reference FIGURE 31-38: IPD, Fixed Voltage Reference (FVR), PIC16LF1782/3 Only. (FVR), PIC16F1782/3 Only. p , ( ), p , ( ), 11 13 10 MTyapxi:c a8l5: °2C5 °+C 3 σ Max. 12 MTyapxi:c a8l5: °2C5 °+C 3 σ Max. 11 9 10 A) Typical I (nPD 78 I (nA) PD 89 Typical 7 6 6 5 5 4 4 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 VDD (V) VDD (V) FIGURE 31-39: IPD, Brown-Out Reset FIGURE 31-40: IPD, Brown-Out Reset (BOR), BORV = 1, PIC16LF1782/3 Only. (BOR), BORV = 1, PIC16F1782/3 Only. Ipd, Low-Power Brown-Out Reset (LPBOR = 0) Ipd, Low-Power Brown-Out Reset (LPBOR = 0) 1.8 1.8 1.6 Max. 1.6 MTyapxi:c a8l5: °2C5 °+C 3 σ Max. 1.4 1.4 1.2 1.2 Max: 85°C + 3σ I (nA) PD 01..80 Typical: 25°C I (μA) PD 01..80 0.6 0.6 0.4 Typical 0.4 Typical 0.2 0.2 0.0 0.0 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 FIGURE 31-41: IPD, LP Brown-Out Reset FIGURE 31-42: IPD, LP Brown-Out Reset (LPBOR = 0), PIC16LF1782/3 Only. (LPBOR = 0), PIC16F1782/3 Only. DS40001579E-page 396  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. p , , p , 7 12 6 MTyapxi:c a8l5: °2C5 °+C 3 σ MTyapxi:c a8l5: °2C5 °+C 3 σ Max. 10 5 Max. 8 I (μA) PD 34 I (μA) PD 6 Typical Typical 4 2 1 2 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-43: IPD, Timer1 Oscillator, FIGURE 31-44: IPD, Timer1 Oscillator, FOSC=32 kHz, PIC16LF1782/3 Only. FOSC=32 kHz, PIC16F1782/3 Only. p , , g ( ) p , , g ( ) 700 900 600 MTyapxi:c a8l5: °2C5 °+C 3 σ 800 MTyapxi:c a8l5: °2C5 °+C 3 σ Max. Max. 700 500 600 I (μA) PD340000 Typical I (μA) PD 450000 Typical 300 200 200 100 100 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-45: IPD, Op Amp, High GBWP FIGURE 31-46: IPD, Op Amp, High GBWP Mode (OPAxSP = 1), PIC16LF1782/3 Only. Mode (OPAxSP = 1), PIC16F1782/3 Only. 500 450 Max: 85°C + 3σ 1.4 Typical: 25°C Max. Max: 85°C + 3σ 400 1.2 Typical: 25°C Max. 350 1.0 300 I (μA) PD220500 I (μA) PD 00..68 150 0.4 100 Typical 50 Typical 0.2 0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-47: IPD, ADC Non-Converting, FIGURE 31-48: IPD, ADC Non-Converting, PIC16LF1782/3 Only. PIC16F1782/3 Only.  2011-2014 Microchip Technology Inc. DS40001579E-page 397

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. 800 800 MTyapxi:c a-4l:0 2°5C° C+ 3σ Max. MTyapxi:c a-4l:0 2°5C° C+ 3σ Max. 700 700 600 600 I (μA) PD500 Typical I (μA) PD500 Typical 400 400 300 300 200 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 31-49: IPD, Comparator, NP Mode FIGURE 31-50: IPD, Comparator, NP Mode (CxSP = 1), PIC16LF1782/3 Only. (CxSP = 1), PIC16F1782/3 Only. 6 5 Max: -40°C max + 3σ 5 Typical;:statistical mean @ 25°C 4 Min: +125°C min - 3σ 4 V (V) OH 3 V (V) OL 3 Min. Typical Max. Max. Typical Min. 2 2 1 MTyapxi:c a-4l:0 s°tCa tmistaicxa +l m3σe a n @ 25°C 1 Min: +125°C min - 3σ 0 0 -30 -25 -20 -15 -10 -5 0 0 10 20 30 40 50 60 70 80 IOH (mA) IOL (mA) FIGURE 31-51: VOH vs. IOH Over FIGURE 31-52: VOL vs. IOL Over Temperature, VDD = 5.0V, PIC16F1782/3 Only. Temperature, VDD = 5.0V, PIC16F1782/3 Only. 3.5 3.0 Max: -40°C max + 3σ Max: -40°C max + 3σ 3.0 TMyinp:i c+a1l:2 s5t°aCti smticina l- m3σe a n @ 25°C 2.5 TMyinp:i c+a1l:2 s5t°aCti smticina l- m3σe a n @ 25°C 2.5 2.0 V (V) OH 12..50 V (V) OL 1.5 Min. Typical Max. Max. Typical Min. 1.0 1.0 0.5 0.5 0.0 0.0 -14 -12 -10 -8 -6 -4 -2 0 0 5 10 15 20 25 30 IOH (mA) IOL (mA) FIGURE 31-53: VOH vs. IOH Over FIGURE 31-54: VOL vs. IOL Over Temperature, VDD = 3.0V. Temperature, VDD = 3.0V. DS40001579E-page 398  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. Voh vs. Ioh over Temperature, Vdd = 1.8V Vol vs. Iol over Temperature, Vdd = 1.8V 2.0 1.8 1.8 TMyapxi:c a-4l:0 s°tCa tmistaicxa +l m3σe a n @ 25°C 1.6 TMyapxi:c a-4l:0 s°tCa tmistaicxa +l m3σe a n @ 25°C Min: +125°C min - 3σ Min: +125°C min - 3σ 1.6 1.4 1.4 1.2 1.2 V (V) OH 1.0 Max. Typical Min. V (V) OL 0.81 Min. Typical Max. 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0 1 2 3 4 5 6 7 8 9 10 FIGURE 31-55: VOH vs. IOH Over FIGURE 31-56: VOL vs. IOL Over Temperature, VDD = 1.8V, PIC16LF1782/3 Only. Temperature, VDD = 1.8V, PIC16LF1782/3 Only. q y LFINTOSC Frequency 40 38 40 Max. 38 36 Max. 36 34 Frequency (kHz) 22223332468024 Typical MTMMyaiinpnx:i: .cT aTyly;p psicitcaaatl ils- + t3i c3σaσ l( -m(4-40e0°aC°nC t@ oto +2 +1512°25C5° C°C) ) Frequency (kHz) 2223346802 Min. TMTyyappxiic:c aaTlly; psitcaatils +ti c3aσl m(-4e0a°nC @ to 2 +51°2C5 °C) 20 22 Min: Typical - 3σ (-40°C to +125°C) 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 20 VDD (V) 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) FIGURE 31-57: LFINTOSC Frequency, FIGURE 31-58: LFINTOSC Frequency, PIC16LF1782/3 Only. PIC16F1782/3 Only. 24 24 22 22 Max. Max. 20 20 me (mS) 18 Typical me (mS) 18 Typical Ti 16 Ti 16 Min. 14 14 Max: Typical + 3σ (-40°C to +125°C) Min. Max: Typical + 3σ (-40°C to +125°C) 12 Typical; statistical mean @ 25°C 12 Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) Min: Typical - 3σ (-40°C to +125°C) 10 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 31-59: WDT Time-Out Period, FIGURE 31-60: WDT Time-Out Period, PIC16F1782/3 Only. PIC16LF1782/3 Only.  2011-2014 Microchip Technology Inc. DS40001579E-page 399

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. y ( ) 2.00 70 Max: Typical + 3σ Typical: Statistical Mean Max. 60 Min: Typical - 3σ 1.95 50 Max. Typical Voltage (V) 1.90 Min. Voltage (mV) 3400 Typical 20 1.85 Max: Typical + 3σ Min. TMyinp:i cTayl:p Sictaalt i-s 3ticσa l Mean 10 1.80 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) FIGURE 31-61: Brown-Out Reset Voltage, FIGURE 31-62: Brown-Out Reset Hysteresis, Low Trip Point (BORV = 1), PIC16LF1782/3 Only. Low Trip Point (BORV = 1), PIC16LF1782/3 Only. g, p ( ) 2.60 70 Max: Typical + 3σ Typical: Statistical Mean 60 Min: Typical - 3σ 2.55 Max. Max. Typical 50 2.50 Voltage (V) 2.45 Min. Voltage (mV) 3400 Typical 2.40 20 Max: Typical + 3σ Min. 2.35 TMyinp:i cTayl:p Sictaalt i-s 3ticσa l Mean 10 2.30 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) FIGURE 31-63: Brown-Out Reset Voltage, FIGURE 31-64: Brown-Out Reset Hysteresis, Low Trip Point (BORV = 1), PIC16F1782/3 Only. Low Trip Point (BORV = 1), PIC16F1782/3 Only. 2.85 80 Max: Typical + 3σ Max: Typical + 3σ TMyinp:i cTayl:p Sictaalt i-s 3ticσa l Mean 70 TMyinp:i cTayl:p Sictaalt i-s 3ticσa l Mean 2.80 Max. Max. 60 Voltage (V) 22..7705 Min. Typical Voltage (mV) 345000 Typical 20 2.65 Min. 10 2.60 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) FIGURE 31-65: Brown-Out Reset Voltage, FIGURE 31-66: Brown-Out Reset Hysteresis, High Trip Point (BORV = 0). High Trip Point (BORV = 0). DS40001579E-page 400  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. y 2.6 50 Max. 2.5 45 Max. 2.4 40 Max: Typical + 3σ 2.3 TMyinp:i cTayl:p Sictaalt i-s 3ticσa l Mean 35 Max: Typical + 3σ Voltage (V) 222...012 Typical Voltage (mV) 223050 Typical T ypical: Statistical Mean 15 1.9 Min. 10 1.8 5 1.7 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) FIGURE 31-67: LPBOR Reset Voltage. FIGURE 31-68: LPBOR Reset Hysteresis. 100 110 Max: Typical + 3σ (-40°C to +125°C) Max: Typical + 3σ (-40°C to +125°C) 90 TMyinp:i cTayl;p sictaatl is- t3icσa l( -m40e°aCn t@o +2152°5C° C) 100 TMyinp:i cTayl;p sictaatl is- t3icσa l( -m40e°aCn t@o +2152°5C° C) Max. 90 80 Max. me (mS) 70 Typical me (mS) 80 Typical Ti Ti 70 Min. 60 60 Min. 50 50 40 40 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 31-69: PWRT Period, FIGURE 31-70: PWRT Period, PIC16F1782/3 Only. PIC16LF1782/3 Only. g g, ( ) 1.70 1.58 1.58 1.68 Max. 11..5566 MTyapxi:c aTly: p2i5ca°Cl + 3σ 1.66 Max. Min: Typical - 3σ 1.64 11..5544 Voltage (V) 111...566802 TyMpiinca. l Voltage (V) Voltage (V) 1111...555.5202 Typical Min. 1.56 11..4488 11..5524 MTM yainpx:i: c TaTyly:p pSicictaaalt li -s+ 3t ic3σaσ l Mean 11..4466 - 40 TM Myainpx:i: c TaTy-ly2:p p0Sici ctaaalt li -s+ 3t ic3σaσ l M0 ean 20 Tempera4t0u re (°C) 60 80 100 120 1.50 1.44 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) FIGURE 31-71: POR Release Voltage. FIGURE 31-72: POR Rearm Voltage, NP Mode (VREGPM = 0), PIC16F1782/3 Only.  2011-2014 Microchip Technology Inc. DS40001579E-page 401

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. g, 1.4 12 1.3 10 Max. 1.2 8 Voltage (V) 11..01 Typical Time (μs) 6 Typical Max. 0.9 Min. 4 0.8 0.7 TMyapxi:c aTly: pSictaatli s+t ic3aσl Mean 2 MTyapxi:c aTly; psitcaatils +ti c3aσl m(-4e0a°nC @ to 2 +51°2C5 °C) Min: Typical - 3σ 0.6 0 -60 -40 -20 0 20 40 60 80 100 120 140 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Temperature (°C) VDD (V) FIGURE 31-73: POR Rearm Voltage, FIGURE 31-74: Wake From Sleep, NP Mode, PIC16LF1782/3 Only. VREGPM = 0. 50 40 45 40 35 TMyapxi:c aTly: psitcaatils +ti c3aσl m ean @ 25°C Max. 35 Max. 30 me (μs) 2350 Typical me (μs) 25 Typical Ti Ti 20 15 20 Note: The FVR Stabilization Period applies when: 150 MTyapxi:c aTly; psitcaatils +ti c3aσl m(-4e0a°nC @ to 2 +51°2C5 °C) 15 12In)) acwlohl moentihn eegxr o ictuiants goe fSs R,l etehespee tFm oVorRd e eixs wi tsiinttahgb VSleRl ewEeGhpe PmnM or e=dl ee1 af fosorer dP P IfCIrCo11m22/ 1/R166eLFsFxexxtx.x xxx d deevviciceess . 0 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (mV) FIGURE 31-75: Wake From Sleep, FIGURE 31-76: FVR Stabilization Period. VREGPM = 1. , g , , , , g , , , 1.0 1.0 0.5 0.5 NL (LSb) 0.0 NL (LSb) 0.0 D D -0.5 -0.5 -1.0 -1.0 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Output Code Output Code FIGURE 31-77: ADC 10-bit Mode, FIGURE 31-78: ADC 10-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1S, 25°C. Single-Ended DNL, VDD = 3.0V, TAD = 4S, 25°C. DS40001579E-page 402  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. g , g , , , 1.0 1.0 2.0 1.5 0.5 10..05 INL (LSb) 0.0 DNL (LSb) INL (LSb) -0000....0550 -1.0 -1.5 -0.5 -0.5 -2.0 0 512 1024 1536 2048 2560 3072 3584 4096 Output Code -1.0 -1.0 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Output Code Output Code FIGURE 31-79: ADC 10-bit Mode, FIGURE 31-80: ADC 10-bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1S, 25°C. Single-Ended INL, VDD = 3.0V, TAD = 4S, 25°C. , g , , , g 2.5 2.0 2.0 1.5 1.5 Max -40C Max 125C 1.0 1.0 Max 125C Max -40C Max 25C NL (LSb) 00..05 Max 25C NL (LSb) 00..05 Min 25C D-0.5 Min 25C I-0.5 Min 125C -1.0 Min -40C -1.0 Min 125C -1.5 Min -40C -1.5 -2.0 -2.5 -2.0 0.5 1.0 2.0 4.0 8.0 0.5 1.0 2.0 4.0 8.0 TAD (μs) TAD (μs) FIGURE 31-81: ADC 10-bit Mode, FIGURE 31-82: ADC 10-bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V. Single-Ended INL, VDD = 3.0V, VREF = 3.0V. , g , , , 2.0 2.0 1.5 Max 125C 1.5 Max -40C 1.0 Max 125C 1.0 Max -40C Max 25C Max 25C 0.5 0.5 DNL (LSb) -00..05 Min -40C INL (LSb) --010...005 MMiinn 2-450CC Min 25C -1.5 Min 125C -1.0 Min 125C -2.0 -1.5 -2.5 -2.0 -3.0 1.8 2.3 3.0 1.8 2.3 3.0 Reference Voltage (V) Reference Voltage (V) FIGURE 31-83: ADC 10-bit Mode, FIGURE 31-84: ADC 10-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1S. Single-Ended INL, VDD = 3.0V, TAD = 1S.  2011-2014 Microchip Technology Inc. DS40001579E-page 403

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. g g 3.0 2.5 2.5 2.0 2.0 1.5 NL (LSb) 11..05 NL (LSb) 01..50 D0.5 D 0.0 0.0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 Output Code Output Code FIGURE 31-85: ADC 12-bit Mode, FIGURE 31-86: ADC 12-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1S, 25°C. Single-Ended DNL, VDD = 3.0V, TAD = 4S, 25°C. g 3.5 3.0 3.0 2.5 2.5 2.0 INL (LSb) 112...050 INL (LSb) 011...505 0.5 0.0 0.0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 Output Code Output Code FIGURE 31-87: ADC 12-bit Mode, FIGURE 31-88: ADC 12-bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1S, 25°C. Single-Ended INL, VDD = 3.0V, TAD = 4S, 25°C. , g , , , , g , , , 4.5 5.5 Max -40C 3 Max -40C Max 125C 3.5 Max 25C Max 125C DNL (LSb) 1.50 INL (LSb) 1.5 Max 25C -0.5 Min 25C Min 25C Min -40C -1.5 Min -40C -2.5 Min 125C Min 125C -3 -4.5 0.5 1.0 2.0 4.0 8.0 0.5 1.0 2.0 4.0 8.0 TAD (μs) TAD (μs) FIGURE 31-89: ADC 12-bit Mode, FIGURE 31-90: ADC 12-bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V. Single-Ended INL, VDD = 3.0V, VREF = 3.0V. DS40001579E-page 404  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. , g , , , 5 6 5 4 Max -40C 4 Max -40C 3 3 Max 25C Max 25C DNL (LSb) 12 Max 125C INL (LSb) 012 Max 125C 0 -1 Min 125C Min 125C Min 25C -2 -1 Min -40C Min -40C Min 25C -3 -2 -4 1.8 2.3 3.0 1.8 2.3 3.0 Reference Voltage (V) Reference Voltage (V) FIGURE 31-91: ADC 12-bit Mode, FIGURE 31-92: ADC 12-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1S. Single-Ended INL, VDD = 3.0V, TAD = 1S. , g , , , 2.5 2.5 2.0 2.0 1.5 1.5 DNL (LSb) 01..50 DNL (LSb) 1.0 0.5 0.0 0.0 -0.5 -1.0 -0.5 -1.5 -1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 Output Code Output Code FIGURE 31-93: ADC 12-bit Mode, FIGURE 31-94: ADC 12-bit Mode, Single-Ended DNL, VDD = 5.5V, TAD = 1S, 25°C. Single-Ended DNL, VDD = 5.5V, TAD = 4S, 25°C. 3.5 23..05 3.0 13..50 2.5 12..05 INL (LSb) 12..50 DNL (LSb) INL (LSb) -00012.....50550 1.0 1.0 -1.0 0.5 -10..55 0.0 -20..00 0 512 1024 1536 2048 2560 3072 3584 4096 -0.5 -0.5 Output Code 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 Output Code Output Code FIGURE 31-95: ADC 12-bit Mode, FIGURE 31-96: ADC 12-bit Mode, Single-Ended INL, VDD = 5.5V, TAD = 1S, 25°C. Single-Ended INL, VDD = 5.5V, TAD = 4S, 25°C.  2011-2014 Microchip Technology Inc. DS40001579E-page 405

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. , g , , , , g , , , 4 3 Max -40C 3 Max 25C Max -40C 2 Max 25C Max 125C 2 NL (LSb) 1 Max 125C NL (LSb) 1 D I 0 0 -1 -1 Min 25C Min 25C Min -40C Min -40C Min 125C -2 Min 125C -2 1.0 2.0 4.0 1.0 2.0 4.0 TAD (μs) TAD (μs) FIGURE 31-97: ADC 12-bit Mode, FIGURE 31-98: ADC 12-bit Mode, Single-Ended DNL, VDD = 5.5V, VREF = 5.5V. Single-Ended INL, VDD = 5.5V, VREF = 5.5V. 800 900 700 AADDCC VVrreeff+- sseett ttoo GVnddd AADDCC VVrreeff+- sseett ttoo GVnddd Max. 800 Max. 600 Typical ADC Output Codes 345000000 Typical ADC Output Codes 567000000 Min. Min. 200 Max: Typical + 3σ TMyapxi:c aTly; psitcaatils +ti c3aσl m ean 400 TMyinp:i cTayl;p sictaatl is- t3icσa l mean 100 Min: Typical - 3σ 0 300 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 6 VDD (V) VDD (V) FIGURE 31-99: Temp. Indicator Initial Offset, FIGURE 31-100: Temp. Indicator Initial Offset, High Range, Temp. = 20°C, PIC16F1782/3 Only. Low Range, Temp. = 20°C, PIC16F1782/3 Only. 800 150 AADDCC VVrreeff+- sseett ttoo GVnddd 125 AADDCC VVrreeff+- sseett ttoo GVnddd Max. 700 ADC Output Codes 456000000 Max. Min. DC Output Codes 125705050 Min. A 0 300 Typical Max: Typical + 3σ -25 200 TMyinp:i cTayl;p sictaatl is- t3icσa l mean -50 Typical MTMyainpx:i: cT aTyly;p psicitcaaatl ils- + t3i c3σaσ l m ean 100 -75 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 -60 -40 -20 0 20 40 60 80 100 120 140 VDD (V) Temperature (°C) FIGURE 31-101: Temp. Indicator Initial Offset, FIGURE 31-102: Temp. Indicator Slope Low Range, Temp. = 20°C, PIC16LF1782/3 Only. Normalized to 20°C, High Range, VDD = 5.5V, PIC16F1782/3 Only. DS40001579E-page 406  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. 250 150 ADC Vref+ set to Vdd Max. ADC Vref+ set to Vdd Max. 200 ADC Vref- set to Gnd ADC Vref- set to Gnd 100 ADC Output Codes 115050000 Min. ADC Output Codes 500 Min. -50 -50 -100 Typical MTMyainpx:i: cT aTyly;p psicitcaaatl ils- + t3i c3σaσ l m ean Typical MTMyianpx:i: cT aTyly;p psicitcaaatl ils- + t3i c3σaσ l m ean -150 -100 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) FIGURE 31-103: Temp. Indicator Slope FIGURE 31-104: Temp. Indicator Slope Normalized to 20°C, High Range, VDD = 3.6V, Normalized to 20°C, Low Range, VDD = 3.0V, PIC16F1782/3 Only. PIC16F1782/3 Only. 250 150 200 AADDCC VVrreeff+- sseett ttoo GVnddd Max. AADDCC VVrreeff+- sseett ttoo GVnddd Max. 100 150 ADC Output Codes 150000 Min. ADC Output Codes 500 Min. -50 -50 -100 Typical MTMyainpx:i: cT aTyly;p psicitcaaatl ils- + t3i c3σaσ l m ean Typical MTMyainpx:i: cT aTyly;p psicitcaaatl ils- + t3i c3σaσ l m ean -150 -100 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) FIGURE 31-105: Temp. Indicator Slope FIGURE 31-106: Temp. Indicator Slope Normalized to 20°C, Low Range, VDD = 1.8V, Normalized to 20°C, Low Range, VDD = 3.0V, PIC16LF1782/3 Only. PIC16LF1782/3 Only. 250 80 200 AADDCC VVrreeff+- sseett ttoo GVnddd Max. 75 Max 150 70 Output Codes 15000 Min. CMRR (dB) 6605 Typical C Min AD 0 55 -50 50 -100 Typical MTMyianpx:i: cT aTyly;p psicitcaaatl ils- + t3i c3σaσ l m ean 45 MTMyainpx:i: cT aTyly;p psicitcaaatl ils- + t3i c3σaσ l m ean -150 40 -60 -40 -20 0 20 40 60 80 100 120 140 -50 -30 -10 10 30 50 70 90 110 130 Temperature (°C) Temperature (°C) FIGURE 31-107: Temp. Indicator Slope FIGURE 31-108: Op Amp, Common Mode Normalized to 20°C, High Range, VDD = 3.6V, Rejection Ratio (CMRR), VDD = 3.0V. PIC16LF1782/3 Only.  2011-2014 Microchip Technology Inc. DS40001579E-page 407

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. g g 35% 8 Sample Size = 3,200 30% 6 Max 25% 4 Percent of Units 1250%% -284550°°°CCC Offset Voltage (V) -202 TyMpiinca l 125°C 10% -4 Max: Typical + 3σ 5% -6 TMyinp:i cTayl;p sictaatl is- t3icσa l mean -8 0% 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 -7 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 Offset Voltage (mV) Common Mode Voltage (V) FIGURE 31-109: Op Amp, Output Voltage FIGURE 31-110: Op Amp, Offset Over Histogram, VDD = 3.0V, VCM = VDD/2. Common Mode Voltage, VDD = 3.0V, Temp. = 25°C. , p , g g 8 3.8 Max 6 3.7 Vdd = 3.6V 4 3.6 Offset Voltage (V) -202 Typical Slew Rate (V/us) 333...345 VVdddd = = 5 2.5.3VV Vdd = 3V -4 3.2 Min Max: Typical + 3σ -6 TMyinp:i cTayl;p sictaatl is- t3icσa l mean 3.1 -8 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -60 -40 -20 0 20 40 60 80 100 120 140 Common Mode Voltage (V) Temperature (°C) FIGURE 31-111: Op Amp, Offset Over FIGURE 31-112: Op Amp, Output Slew Rate, Common Mode Voltage, VDD = 5.0V, Rising Edge. Temp. = 25°C, PIC16F1782/3 Only. 5.4 45 5.2 43 Vdd = 2.3V -40°C 5.0 41 Slew Rate (V/us) 444...468 Vdd = 3.6V Hysteresis (mV) 33333579 218525°5°CC° 4.2 31 4.0 Vdd = 5.5V 29 3.8 Vdd = 3V 27 3.6 25 -60 -40 -20 0 20 40 60 80 100 120 140 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Temperature (°C) Common Mode Voltage (V) FIGURE 31-113: Op Amp, Output Slew Rate, FIGURE 31-114: Comparator Hysteresis, Falling Edge. NP Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values. DS40001579E-page 408  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. yp 30 30 25 25 20 20 Offset Voltage (mV) 11-50505 MAX Offset Voltage (mV) 11-50505 MAX -10 MIN -10 MIN -15 -15 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Common Mode Voltage (V) Common Mode Voltage (V) FIGURE 31-115: Comparator Offset, NP Mode FIGURE 31-116: Comparator Offset, NP Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values (CxSP = 1), VDD = 3.0V, Typical Measured Values at 25°C. From -40°C to 125°C. 50 30 25 45 20 Hysteresis (mV) 3450 18255°° 25°C Hysteresis (mV) 110505 MAX 30 -5 -40°C -10 25 MIN -15 20 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Voltage (V) Common Mode Voltage (V) FIGURE 31-117: Comparator Hysteresis, FIGURE 31-118: Comparator Offset, NP Mode NP Mode (CxSP = 1), VDD = 5.5V, Typical (CxSP = 1), VDD = 5.0V, Typical Measured Values Measured Values, PIC16F1782/3 Only. at 25°C, PIC16F1782/3 Only. yp 40 140 Max: Typical + 3σ (-40°C to +125°C) 30 120 TMyinp:i cTayl;p sictaatl is- t3icσa l( -m40e°aCn t@o +2152°5C° C) Offset Voltage (mV) 12000 MAX Time (nS) 1680000 25°C12 5°C 40 -10 -40°C MIN 20 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1.8 2.1 2.4 2.7 3.0 3.3 3.6 Common Mode Voltage (V) VDD (V) FIGURE 31-119: Comparator Offset, NP Mode FIGURE 31-120: Comparator Response Time (CxSP = 1), VDD = 5.0V, Typical Measured Values Over Voltage, NP Mode (CxSP = 1), Typical From -40°C to 125°C, PIC16F1782/3 Only. Measured Values, PIC16LF1782/3 Only.  2011-2014 Microchip Technology Inc. DS40001579E-page 409

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. 90 1,400 80 MTMyainpx:i: cT aTyly;p psicitcaaatl ils- + t3i c3σaσ l( -m(4-04e°0aC°nC t@ oto +2 +1521°52C°5 C°C) ) 1,200 MTMyainpx:i: cT aTyly;p psicitcaaatl ils- + t3i c3σaσ l( -m(4-04e°0aC°nC t@ oto +2 +1521°52C°5 C°C) ) 70 125°C 1,000 60 Time (nS) 4500 25°C Time (nS) 680000 125°C 30 25°C 400 20 -40°C 10 200 -40°C 0 0 2.2 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) VDD (V) FIGURE 31-121: Comparator Response Time FIGURE 31-122: Comparator Output Filter Over Voltage, NP Mode (CxSP = 1), Typical Delay Time Over Temp., NP Mode (CxSP = 1), Measured Values, PIC16F1782/3 Only. Typical Measured Values, PIC16LF1782/3 Only. 800 0.025 Max: Typical + 3σ (-40°C to +125°C) 0.020 700 Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) 0.015 600 Time (nS) 345000000 251°C25 °C Absolute DNL (LSb) -0000....000000100505 -28145520°°5°CC°CC 200 -0.010 100 -40°C -0.015 0 2.2 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 -0.020 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 VDD (V) Output Code FIGURE 31-123: Comparator Output Filter FIGURE 31-124: Typical DAC DNL Error, Delay Time Over Temp., NP Mode (CxSP = 1), VDD = 3.0V, VREF = External 3V. Typical Measured Values, PIC16F1782/3 Only. 0.00 0.020 -0.05 0.015 -0.10 0.010 Absolute INL (LSb) ----0000....32210505 -28145520°°5°CC°CC Absolute DNL (LSb) 00..000005 -28145520°°5°CC°CC -0.005 -0.35 -0.010 -0.40 -0.45 -0.015 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code Output Code FIGURE 31-125: Typical DAC INL Error, FIGURE 31-126: Typical DAC INL Error, VDD = 3.0V, VREF = External 3V. VDD = 5.0V, VREF = External 5V, PIC16F1782/3 Only. DS40001579E-page 410  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: Unless otherwise noted, VIN=5V, FOSC=300kHz, CIN=0.1µF, TA=25°C. 0.00 00..445 0.4 -0.05 0.35 Vref = Int. Vdd Absolute INL (LSb) -----00000.....3221105050 -28145520°°5°CC°CC Absolute DNL (LSb) Absolute DNL (LSb) 00000000.....01223...123555 V1V2..rr80eeVVff == EExxtt.. VVVVrrrreeeeffff ==== IEEEnxxxt.ttt ...V 123d...800dVVV 0.10 -0.35 -50 0 50 100 150 Temperature (°C) -0.40 -0.45 0.0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 -60 -40 -20 0 20 40 60 80 100 120 140 Output Code Temperature (°C) FIGURE 31-127: Typical DAC INL Error, FIGURE 31-128: Absolute Value of DAC DNL VDD = 5.0V, VREF = External 5V, PIC16F1782/3 Error, VDD = 3.0V, VREF = VDD. Only. 0.90 00.3.30 -2.1 0-2.8.38 Vref = Int. Vdd 0.25 Vref = Int. Vdd Absolute INL (LSb) Absolute INL (LSb) 000-----33222...888.....31975246 V1V2V3...rrr800eeeVVVfff === EEExxxttt... -28145520 5 Absolute DNL (LSb) Absolute DNL (LSb) 0000000.....01122..1255826 V1V2V3V5....rrrr8000eeeeVVVVffff ==== EEEExxxxtttt.... -28145520 5 -3.5 0 0.0 1.0 2.0 3.0 4.0 5.0 0.14 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.80 Temperature (°C) Temperature (°C) 0.78 0.10 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) FIGURE 31-129: Absolute Value of DAC INL FIGURE 31-130: Absolute Value of DAC DNL Error, VDD = 3.0V. Error, VDD = 5.0V, PIC16F1782/3 Only. 0.9 -2.1 0-2.8.38 Vref = Int. Vdd Absolute INL (LSb) Absolute INL (LSb) 000-----33222...888.....31975246 V1V2V3...rrr800eeeVVVfff === EEExxxttt... -28145520 5 -3.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.8 Temperature (°C) 0.78 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-131: Absolute Value of DAC INL Error, VDD = 5.0V, PIC16F1782/3 Only.  2011-2014 Microchip Technology Inc. DS40001579E-page 411

PIC16(L)F1782/3 32.0 DEVELOPMENT SUPPORT 32.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker DS40001579E-page 412  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 32.2 MPLAB XC Compilers 32.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 32.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 32.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process  2011-2014 Microchip Technology Inc. DS40001579E-page 413

PIC16(L)F1782/3 32.6 MPLAB X SIM Software Simulator 32.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 32.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 32.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 32.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS40001579E-page 414  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 32.11 Demonstration/Development 32.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2011-2014 Microchip Technology Inc. DS40001579E-page 415

PIC16(L)F1782/3 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC16F1782 -I/SP e3 1204017 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX PIC16F1782 XXXXXXXXXXXXXXXXXXXX -I/SO e3 XXXXXXXXXXXXXXXXXXXX YYWWNNN 1204017 28-Lead SSOP (5.30 mm) Example PIC16F1782 -I/SS e3 1204017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS40001579E-page 416  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 16F1782 XXXXXXXX XXXXXXXX -I/ML e3 YYWWNNN 120417 28-Lead UQFN (4x4x0.5 mm) Example PIC16 PIN 1 PIN 1 LF1782 I/MV 204017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011-2014 Microchip Technology Inc. DS40001579E-page 417

PIC16(L)F1782/3 33.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)(cid:26)(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 4(cid:11)(cid:10)(cid:3)’(cid:12)(cid:15)(cid:3)((cid:11)"’(cid:3)(cid:9)#(cid:10)(cid:10)(cid:15)(cid:16)’(cid:3)(cid:13)(cid:29)(cid:9)5(cid:29)(cid:18)(cid:15)(cid:3)$(cid:10)(cid:29)+(cid:8)(cid:16)(cid:18)")(cid:3)(cid:13)(cid:17)(cid:15)(cid:29)"(cid:15)(cid:3)"(cid:15)(cid:15)(cid:3)’(cid:12)(cid:15)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:3) (cid:29)(cid:9)5(cid:29)(cid:18)(cid:8)(cid:16)(cid:18)(cid:3)(cid:23)(cid:13)(cid:15)(cid:9)(cid:8)&(cid:8)(cid:9)(cid:29)’(cid:8)(cid:11)(cid:16)(cid:3)(cid:17)(cid:11)(cid:9)(cid:29)’(cid:15)$(cid:3)(cid:29)’(cid:3) (cid:12)’’(cid:13)366+++(cid:21)((cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:21)(cid:9)(cid:11)(6(cid:13)(cid:29)(cid:9)5(cid:29)(cid:18)(cid:8)(cid:16)(cid:18) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 7(cid:16)(cid:8)’" (cid:20)8-9/(cid:23) (cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16)(cid:3):(cid:8)((cid:8)’" (cid:7)(cid:20)8 8;(cid:7) (cid:7)(cid:26)< 8#(*(cid:15)(cid:10)(cid:3)(cid:11)&(cid:3) (cid:8)(cid:16)" 8 (cid:4)= (cid:8)’(cid:9)(cid:12) (cid:15) (cid:21)(cid:31)(cid:5)(cid:5)(cid:3)2(cid:23)- (cid:14)(cid:11)(cid:13)(cid:3)’(cid:11)(cid:3)(cid:23)(cid:15)(cid:29)’(cid:8)(cid:16)(cid:18)(cid:3) (cid:17)(cid:29)(cid:16)(cid:15) (cid:26) > > (cid:21)(cid:4)(cid:5)(cid:5) (cid:7)(cid:11)(cid:17)$(cid:15)$(cid:3) (cid:29)(cid:9)5(cid:29)(cid:18)(cid:15)(cid:3)(cid:14)(cid:12)(cid:8)(cid:9)5(cid:16)(cid:15)"" (cid:26)(cid:4) (cid:21)(cid:31)(cid:4)(cid:5) (cid:21)(cid:31).(cid:30) (cid:21)(cid:31)(cid:30)(cid:5) 2(cid:29)"(cid:15)(cid:3)’(cid:11)(cid:3)(cid:23)(cid:15)(cid:29)’(cid:8)(cid:16)(cid:18)(cid:3) (cid:17)(cid:29)(cid:16)(cid:15) (cid:26)(cid:31) (cid:21)(cid:5)(cid:31)(cid:30) > > (cid:23)(cid:12)(cid:11)#(cid:17)$(cid:15)(cid:10)(cid:3)’(cid:11)(cid:3)(cid:23)(cid:12)(cid:11)#(cid:17)$(cid:15)(cid:10)(cid:3)?(cid:8)$’(cid:12) / (cid:21)(cid:4)(cid:25)(cid:5) (cid:21).(cid:31)(cid:5) (cid:21)..(cid:30) (cid:7)(cid:11)(cid:17)$(cid:15)$(cid:3) (cid:29)(cid:9)5(cid:29)(cid:18)(cid:15)(cid:3)?(cid:8)$’(cid:12) /(cid:31) (cid:21)(cid:4)(cid:24)(cid:5) (cid:21)(cid:4)=(cid:30) (cid:21)(cid:4)(cid:25)(cid:30) ;!(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3):(cid:15)(cid:16)(cid:18)’(cid:12) (cid:22) (cid:31)(cid:21).(cid:24)(cid:30) (cid:31)(cid:21).@(cid:30) (cid:31)(cid:21)(cid:24)(cid:5)(cid:5) (cid:14)(cid:8)(cid:13)(cid:3)’(cid:11)(cid:3)(cid:23)(cid:15)(cid:29)’(cid:8)(cid:16)(cid:18)(cid:3) (cid:17)(cid:29)(cid:16)(cid:15) : (cid:21)(cid:31)(cid:31)(cid:5) (cid:21)(cid:31).(cid:5) (cid:21)(cid:31)(cid:30)(cid:5) :(cid:15)(cid:29)$(cid:3)(cid:14)(cid:12)(cid:8)(cid:9)5(cid:16)(cid:15)"" (cid:9) (cid:21)(cid:5)(cid:5)= (cid:21)(cid:5)(cid:31)(cid:5) (cid:21)(cid:5)(cid:31)(cid:30) 7(cid:13)(cid:13)(cid:15)(cid:10)(cid:3):(cid:15)(cid:29)$(cid:3)?(cid:8)$’(cid:12) *(cid:31) (cid:21)(cid:5)(cid:24)(cid:5) (cid:21)(cid:5)(cid:30)(cid:5) (cid:21)(cid:5)(cid:6)(cid:5) :(cid:11)+(cid:15)(cid:10)(cid:3):(cid:15)(cid:29)$(cid:3)?(cid:8)$’(cid:12) * (cid:21)(cid:5)(cid:31)(cid:24) (cid:21)(cid:5)(cid:31)= (cid:21)(cid:5)(cid:4)(cid:4) ;!(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3)(cid:27)(cid:11)+(cid:3)(cid:23)(cid:13)(cid:29)(cid:9)(cid:8)(cid:16)(cid:18)(cid:3)(cid:3), (cid:15)2 > > (cid:21)(cid:24).(cid:5) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:31)(cid:21) (cid:8)(cid:16)(cid:3)(cid:31)(cid:3)!(cid:8)"#(cid:29)(cid:17)(cid:3)(cid:8)(cid:16)$(cid:15)%(cid:3)&(cid:15)(cid:29)’#(cid:10)(cid:15)(cid:3)((cid:29)(cid:19)(cid:3)!(cid:29)(cid:10)(cid:19))(cid:3)*#’(cid:3)(#"’(cid:3)*(cid:15)(cid:3)(cid:17)(cid:11)(cid:9)(cid:29)’(cid:15)$(cid:3)+(cid:8)’(cid:12)(cid:8)(cid:16)(cid:3)’(cid:12)(cid:15)(cid:3)(cid:12)(cid:29)’(cid:9)(cid:12)(cid:15)$(cid:3)(cid:29)(cid:10)(cid:15)(cid:29)(cid:21) (cid:4)(cid:21) ,(cid:3)(cid:23)(cid:8)(cid:18)(cid:16)(cid:8)&(cid:8)(cid:9)(cid:29)(cid:16)’(cid:3)-(cid:12)(cid:29)(cid:10)(cid:29)(cid:9)’(cid:15)(cid:10)(cid:8)"’(cid:8)(cid:9)(cid:21) .(cid:21) (cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16)"(cid:3)(cid:22)(cid:3)(cid:29)(cid:16)$(cid:3)/(cid:31)(cid:3)$(cid:11)(cid:3)(cid:16)(cid:11)’(cid:3)(cid:8)(cid:16)(cid:9)(cid:17)#$(cid:15)(cid:3)((cid:11)(cid:17)$(cid:3)&(cid:17)(cid:29)"(cid:12)(cid:3)(cid:11)(cid:10)(cid:3)(cid:13)(cid:10)(cid:11)’(cid:10)#"(cid:8)(cid:11)(cid:16)"(cid:21)(cid:3)(cid:7)(cid:11)(cid:17)$(cid:3)&(cid:17)(cid:29)"(cid:12)(cid:3)(cid:11)(cid:10)(cid:3)(cid:13)(cid:10)(cid:11)’(cid:10)#"(cid:8)(cid:11)(cid:16)"(cid:3)"(cid:12)(cid:29)(cid:17)(cid:17)(cid:3)(cid:16)(cid:11)’(cid:3)(cid:15)%(cid:9)(cid:15)(cid:15)$(cid:3)(cid:21)(cid:5)(cid:31)(cid:5)0(cid:3)(cid:13)(cid:15)(cid:10)(cid:3)"(cid:8)$(cid:15)(cid:21) (cid:24)(cid:21) (cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16)(cid:8)(cid:16)(cid:18)(cid:3)(cid:29)(cid:16)$(cid:3)’(cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:8)(cid:16)(cid:18)(cid:3)(cid:13)(cid:15)(cid:10)(cid:3)(cid:26)(cid:23)(cid:7)/(cid:3)1(cid:31)(cid:24)(cid:21)(cid:30)(cid:7)(cid:21) 2(cid:23)-3 2(cid:29)"(cid:8)(cid:9)(cid:3)(cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16)(cid:21)(cid:3)(cid:14)(cid:12)(cid:15)(cid:11)(cid:10)(cid:15)’(cid:8)(cid:9)(cid:29)(cid:17)(cid:17)(cid:19)(cid:3)(cid:15)%(cid:29)(cid:9)’(cid:3)!(cid:29)(cid:17)#(cid:15)(cid:3)"(cid:12)(cid:11)+(cid:16)(cid:3)+(cid:8)’(cid:12)(cid:11)#’(cid:3)’(cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:15)"(cid:21) (cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:14)(cid:15)(cid:9)(cid:12)(cid:16)(cid:11)(cid:17)(cid:11)(cid:18)(cid:19)(cid:22)(cid:10)(cid:29)+(cid:8)(cid:16)(cid:18)-(cid:5)(cid:24)(cid:28)(cid:5)(cid:6)(cid:5)2 DS40001579E-page 418  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2014 Microchip Technology Inc. DS40001579E-page 419

PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001579E-page 420  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2014 Microchip Technology Inc. DS40001579E-page 421

PIC16(L)F1782/3 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)#$(cid:12)(cid:13)(cid:11)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)%(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:10)(cid:24)(cid:9)(cid:25)(cid:9)&’(cid:26)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:10)%(cid:15) !(cid:30)(cid:18)(cid:6)" 4(cid:11)(cid:10)(cid:3)’(cid:12)(cid:15)(cid:3)((cid:11)"’(cid:3)(cid:9)#(cid:10)(cid:10)(cid:15)(cid:16)’(cid:3)(cid:13)(cid:29)(cid:9)5(cid:29)(cid:18)(cid:15)(cid:3)$(cid:10)(cid:29)+(cid:8)(cid:16)(cid:18)")(cid:3)(cid:13)(cid:17)(cid:15)(cid:29)"(cid:15)(cid:3)"(cid:15)(cid:15)(cid:3)’(cid:12)(cid:15)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:3) (cid:29)(cid:9)5(cid:29)(cid:18)(cid:8)(cid:16)(cid:18)(cid:3)(cid:23)(cid:13)(cid:15)(cid:9)(cid:8)&(cid:8)(cid:9)(cid:29)’(cid:8)(cid:11)(cid:16)(cid:3)(cid:17)(cid:11)(cid:9)(cid:29)’(cid:15)$(cid:3)(cid:29)’(cid:3) (cid:12)’’(cid:13)366+++(cid:21)((cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:21)(cid:9)(cid:11)(6(cid:13)(cid:29)(cid:9)5(cid:29)(cid:18)(cid:8)(cid:16)(cid:18) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 7(cid:16)(cid:8)’" (cid:7)(cid:20)::(cid:20)(cid:7)/(cid:14)/(cid:27)(cid:23) (cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16)(cid:3):(cid:8)((cid:8)’" (cid:7)(cid:20)8 8;(cid:7) (cid:7)(cid:26)< 8#(*(cid:15)(cid:10)(cid:3)(cid:11)&(cid:3) (cid:8)(cid:16)" 8 (cid:4)= (cid:8)’(cid:9)(cid:12) (cid:15) (cid:5)(cid:21)@(cid:30)(cid:3)2(cid:23)- ;!(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3)9(cid:15)(cid:8)(cid:18)(cid:12)’ (cid:26) > > (cid:4)(cid:21)(cid:5)(cid:5) (cid:7)(cid:11)(cid:17)$(cid:15)$(cid:3) (cid:29)(cid:9)5(cid:29)(cid:18)(cid:15)(cid:3)(cid:14)(cid:12)(cid:8)(cid:9)5(cid:16)(cid:15)"" (cid:26)(cid:4) (cid:31)(cid:21)@(cid:30) (cid:31)(cid:21)(cid:6)(cid:30) (cid:31)(cid:21)=(cid:30) (cid:23)’(cid:29)(cid:16)$(cid:11)&&(cid:3) (cid:26)(cid:31) (cid:5)(cid:21)(cid:5)(cid:30) > > ;!(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3)?(cid:8)$’(cid:12) / (cid:6)(cid:21)(cid:24)(cid:5) (cid:6)(cid:21)=(cid:5) =(cid:21)(cid:4)(cid:5) (cid:7)(cid:11)(cid:17)$(cid:15)$(cid:3) (cid:29)(cid:9)5(cid:29)(cid:18)(cid:15)(cid:3)?(cid:8)$’(cid:12) /(cid:31) (cid:30)(cid:21)(cid:5)(cid:5) (cid:30)(cid:21).(cid:5) (cid:30)(cid:21)@(cid:5) ;!(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3):(cid:15)(cid:16)(cid:18)’(cid:12) (cid:22) (cid:25)(cid:21)(cid:25)(cid:5) (cid:31)(cid:5)(cid:21)(cid:4)(cid:5) (cid:31)(cid:5)(cid:21)(cid:30)(cid:5) 4(cid:11)(cid:11)’(cid:3):(cid:15)(cid:16)(cid:18)’(cid:12) : (cid:5)(cid:21)(cid:30)(cid:30) (cid:5)(cid:21)(cid:6)(cid:30) (cid:5)(cid:21)(cid:25)(cid:30) 4(cid:11)(cid:11)’(cid:13)(cid:10)(cid:8)(cid:16)’ :(cid:31) (cid:31)(cid:21)(cid:4)(cid:30)(cid:3)(cid:27)/4 :(cid:15)(cid:29)$(cid:3)(cid:14)(cid:12)(cid:8)(cid:9)5(cid:16)(cid:15)"" (cid:9) (cid:5)(cid:21)(cid:5)(cid:25) > (cid:5)(cid:21)(cid:4)(cid:30) 4(cid:11)(cid:11)’(cid:3)(cid:26)(cid:16)(cid:18)(cid:17)(cid:15) (cid:3) (cid:5)A (cid:24)A =A :(cid:15)(cid:29)$(cid:3)?(cid:8)$’(cid:12) * (cid:5)(cid:21)(cid:4)(cid:4) > (cid:5)(cid:21).= !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:31)(cid:21) (cid:8)(cid:16)(cid:3)(cid:31)(cid:3)!(cid:8)"#(cid:29)(cid:17)(cid:3)(cid:8)(cid:16)$(cid:15)%(cid:3)&(cid:15)(cid:29)’#(cid:10)(cid:15)(cid:3)((cid:29)(cid:19)(cid:3)!(cid:29)(cid:10)(cid:19))(cid:3)*#’(cid:3)(#"’(cid:3)*(cid:15)(cid:3)(cid:17)(cid:11)(cid:9)(cid:29)’(cid:15)$(cid:3)+(cid:8)’(cid:12)(cid:8)(cid:16)(cid:3)’(cid:12)(cid:15)(cid:3)(cid:12)(cid:29)’(cid:9)(cid:12)(cid:15)$(cid:3)(cid:29)(cid:10)(cid:15)(cid:29)(cid:21) (cid:4)(cid:21) (cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16)"(cid:3)(cid:22)(cid:3)(cid:29)(cid:16)$(cid:3)/(cid:31)(cid:3)$(cid:11)(cid:3)(cid:16)(cid:11)’(cid:3)(cid:8)(cid:16)(cid:9)(cid:17)#$(cid:15)(cid:3)((cid:11)(cid:17)$(cid:3)&(cid:17)(cid:29)"(cid:12)(cid:3)(cid:11)(cid:10)(cid:3)(cid:13)(cid:10)(cid:11)’(cid:10)#"(cid:8)(cid:11)(cid:16)"(cid:21)(cid:3)(cid:7)(cid:11)(cid:17)$(cid:3)&(cid:17)(cid:29)"(cid:12)(cid:3)(cid:11)(cid:10)(cid:3)(cid:13)(cid:10)(cid:11)’(cid:10)#"(cid:8)(cid:11)(cid:16)"(cid:3)"(cid:12)(cid:29)(cid:17)(cid:17)(cid:3)(cid:16)(cid:11)’(cid:3)(cid:15)%(cid:9)(cid:15)(cid:15)$(cid:3)(cid:5)(cid:21)(cid:4)(cid:5)(cid:3)(((cid:3)(cid:13)(cid:15)(cid:10)(cid:3)"(cid:8)$(cid:15)(cid:21) .(cid:21) (cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16)(cid:8)(cid:16)(cid:18)(cid:3)(cid:29)(cid:16)$(cid:3)’(cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:8)(cid:16)(cid:18)(cid:3)(cid:13)(cid:15)(cid:10)(cid:3)(cid:26)(cid:23)(cid:7)/(cid:3)1(cid:31)(cid:24)(cid:21)(cid:30)(cid:7)(cid:21) 2(cid:23)-3 2(cid:29)"(cid:8)(cid:9)(cid:3)(cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16)(cid:21)(cid:3)(cid:14)(cid:12)(cid:15)(cid:11)(cid:10)(cid:15)’(cid:8)(cid:9)(cid:29)(cid:17)(cid:17)(cid:19)(cid:3)(cid:15)%(cid:29)(cid:9)’(cid:3)!(cid:29)(cid:17)#(cid:15)(cid:3)"(cid:12)(cid:11)+(cid:16)(cid:3)+(cid:8)’(cid:12)(cid:11)#’(cid:3)’(cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:15)"(cid:21) (cid:27)/43 (cid:27)(cid:15)&(cid:15)(cid:10)(cid:15)(cid:16)(cid:9)(cid:15)(cid:3)(cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16))(cid:3)#"#(cid:29)(cid:17)(cid:17)(cid:19)(cid:3)+(cid:8)’(cid:12)(cid:11)#’(cid:3)’(cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:15))(cid:3)&(cid:11)(cid:10)(cid:3)(cid:8)(cid:16)&(cid:11)(cid:10)((cid:29)’(cid:8)(cid:11)(cid:16)(cid:3)(cid:13)#(cid:10)(cid:13)(cid:11)"(cid:15)"(cid:3)(cid:11)(cid:16)(cid:17)(cid:19)(cid:21) (cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:14)(cid:15)(cid:9)(cid:12)(cid:16)(cid:11)(cid:17)(cid:11)(cid:18)(cid:19)(cid:22)(cid:10)(cid:29)+(cid:8)(cid:16)(cid:18)-(cid:5)(cid:24)(cid:28)(cid:5)(cid:6).2 DS40001579E-page 422  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2014 Microchip Technology Inc. DS40001579E-page 423

PIC16(L)F1782/3 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)((cid:21)(cid:7)(cid:8)(cid:9))(cid:16)(cid:7)(cid:18)*(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)+(cid:6)(cid:9)(cid:23),(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)-.-(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)()! /(cid:12)(cid:18)#(cid:9)(cid:27)’&&(cid:9)(cid:28)(cid:28)(cid:9)0(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13)+(cid:18)# !(cid:30)(cid:18)(cid:6)" 4(cid:11)(cid:10)(cid:3)’(cid:12)(cid:15)(cid:3)((cid:11)"’(cid:3)(cid:9)#(cid:10)(cid:10)(cid:15)(cid:16)’(cid:3)(cid:13)(cid:29)(cid:9)5(cid:29)(cid:18)(cid:15)(cid:3)$(cid:10)(cid:29)+(cid:8)(cid:16)(cid:18)")(cid:3)(cid:13)(cid:17)(cid:15)(cid:29)"(cid:15)(cid:3)"(cid:15)(cid:15)(cid:3)’(cid:12)(cid:15)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:3) (cid:29)(cid:9)5(cid:29)(cid:18)(cid:8)(cid:16)(cid:18)(cid:3)(cid:23)(cid:13)(cid:15)(cid:9)(cid:8)&(cid:8)(cid:9)(cid:29)’(cid:8)(cid:11)(cid:16)(cid:3)(cid:17)(cid:11)(cid:9)(cid:29)’(cid:15)$(cid:3)(cid:29)’(cid:3) (cid:12)’’(cid:13)366+++(cid:21)((cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:21)(cid:9)(cid:11)(6(cid:13)(cid:29)(cid:9)5(cid:29)(cid:18)(cid:8)(cid:16)(cid:18) D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 7(cid:16)(cid:8)’" (cid:7)(cid:20)::(cid:20)(cid:7)/(cid:14)/(cid:27)(cid:23) (cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16)(cid:3):(cid:8)((cid:8)’" (cid:7)(cid:20)8 8;(cid:7) (cid:7)(cid:26)< 8#(*(cid:15)(cid:10)(cid:3)(cid:11)&(cid:3) (cid:8)(cid:16)" 8 (cid:4)= (cid:8)’(cid:9)(cid:12) (cid:15) (cid:5)(cid:21)@(cid:30)(cid:3)2(cid:23)- ;!(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3)9(cid:15)(cid:8)(cid:18)(cid:12)’ (cid:26) (cid:5)(cid:21)=(cid:5) (cid:5)(cid:21)(cid:25)(cid:5) (cid:31)(cid:21)(cid:5)(cid:5) (cid:23)’(cid:29)(cid:16)$(cid:11)&&(cid:3) (cid:26)(cid:31) (cid:5)(cid:21)(cid:5)(cid:5) (cid:5)(cid:21)(cid:5)(cid:4) (cid:5)(cid:21)(cid:5)(cid:30) -(cid:11)(cid:16)’(cid:29)(cid:9)’(cid:3)(cid:14)(cid:12)(cid:8)(cid:9)5(cid:16)(cid:15)"" (cid:26). (cid:5)(cid:21)(cid:4)(cid:5)(cid:3)(cid:27)/4 ;!(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3)?(cid:8)$’(cid:12) / @(cid:21)(cid:5)(cid:5)(cid:3)2(cid:23)- /%(cid:13)(cid:11)"(cid:15)$(cid:3) (cid:29)$(cid:3)?(cid:8)$’(cid:12) /(cid:4) .(cid:21)@(cid:30) .(cid:21)(cid:6)(cid:5) (cid:24)(cid:21)(cid:4)(cid:5) ;!(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3):(cid:15)(cid:16)(cid:18)’(cid:12) (cid:22) @(cid:21)(cid:5)(cid:5)(cid:3)2(cid:23)- /%(cid:13)(cid:11)"(cid:15)$(cid:3) (cid:29)$(cid:3):(cid:15)(cid:16)(cid:18)’(cid:12) (cid:22)(cid:4) .(cid:21)@(cid:30) .(cid:21)(cid:6)(cid:5) (cid:24)(cid:21)(cid:4)(cid:5) -(cid:11)(cid:16)’(cid:29)(cid:9)’(cid:3)?(cid:8)$’(cid:12) * (cid:5)(cid:21)(cid:4). (cid:5)(cid:21).(cid:5) (cid:5)(cid:21).(cid:30) -(cid:11)(cid:16)’(cid:29)(cid:9)’(cid:3):(cid:15)(cid:16)(cid:18)’(cid:12) : (cid:5)(cid:21)(cid:30)(cid:5) (cid:5)(cid:21)(cid:30)(cid:30) (cid:5)(cid:21)(cid:6)(cid:5) -(cid:11)(cid:16)’(cid:29)(cid:9)’(cid:28)’(cid:11)(cid:28)/%(cid:13)(cid:11)"(cid:15)$(cid:3) (cid:29)$ B (cid:5)(cid:21)(cid:4)(cid:5) > > !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:31)(cid:21) (cid:8)(cid:16)(cid:3)(cid:31)(cid:3)!(cid:8)"#(cid:29)(cid:17)(cid:3)(cid:8)(cid:16)$(cid:15)%(cid:3)&(cid:15)(cid:29)’#(cid:10)(cid:15)(cid:3)((cid:29)(cid:19)(cid:3)!(cid:29)(cid:10)(cid:19))(cid:3)*#’(cid:3)(#"’(cid:3)*(cid:15)(cid:3)(cid:17)(cid:11)(cid:9)(cid:29)’(cid:15)$(cid:3)+(cid:8)’(cid:12)(cid:8)(cid:16)(cid:3)’(cid:12)(cid:15)(cid:3)(cid:12)(cid:29)’(cid:9)(cid:12)(cid:15)$(cid:3)(cid:29)(cid:10)(cid:15)(cid:29)(cid:21) (cid:4)(cid:21) (cid:29)(cid:9)5(cid:29)(cid:18)(cid:15)(cid:3)(cid:8)"(cid:3)"(cid:29)+(cid:3)"(cid:8)(cid:16)(cid:18)#(cid:17)(cid:29)’(cid:15)$(cid:21) .(cid:21) (cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16)(cid:8)(cid:16)(cid:18)(cid:3)(cid:29)(cid:16)$(cid:3)’(cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:8)(cid:16)(cid:18)(cid:3)(cid:13)(cid:15)(cid:10)(cid:3)(cid:26)(cid:23)(cid:7)/(cid:3)1(cid:31)(cid:24)(cid:21)(cid:30)(cid:7)(cid:21) 2(cid:23)-3 2(cid:29)"(cid:8)(cid:9)(cid:3)(cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16)(cid:21)(cid:3)(cid:14)(cid:12)(cid:15)(cid:11)(cid:10)(cid:15)’(cid:8)(cid:9)(cid:29)(cid:17)(cid:17)(cid:19)(cid:3)(cid:15)%(cid:29)(cid:9)’(cid:3)!(cid:29)(cid:17)#(cid:15)(cid:3)"(cid:12)(cid:11)+(cid:16)(cid:3)+(cid:8)’(cid:12)(cid:11)#’(cid:3)’(cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:15)"(cid:21) (cid:27)/43 (cid:27)(cid:15)&(cid:15)(cid:10)(cid:15)(cid:16)(cid:9)(cid:15)(cid:3)(cid:22)(cid:8)((cid:15)(cid:16)"(cid:8)(cid:11)(cid:16))(cid:3)#"#(cid:29)(cid:17)(cid:17)(cid:19)(cid:3)+(cid:8)’(cid:12)(cid:11)#’(cid:3)’(cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:15))(cid:3)&(cid:11)(cid:10)(cid:3)(cid:8)(cid:16)&(cid:11)(cid:10)((cid:29)’(cid:8)(cid:11)(cid:16)(cid:3)(cid:13)#(cid:10)(cid:13)(cid:11)"(cid:15)"(cid:3)(cid:11)(cid:16)(cid:17)(cid:19)(cid:21) (cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:14)(cid:15)(cid:9)(cid:12)(cid:16)(cid:11)(cid:17)(cid:11)(cid:18)(cid:19)(cid:22)(cid:10)(cid:29)+(cid:8)(cid:16)(cid:18)-(cid:5)(cid:24)(cid:28)(cid:31)(cid:5)(cid:30)2 DS40001579E-page 424  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)((cid:21)(cid:7)(cid:8)(cid:9))(cid:16)(cid:7)(cid:18)*(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)+(cid:6)(cid:9)(cid:23),(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)-.-(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)()! /(cid:12)(cid:18)#(cid:9)(cid:27)’&&(cid:9)(cid:28)(cid:28)(cid:9)0(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13)+(cid:18)# !(cid:30)(cid:18)(cid:6)" 4(cid:11)(cid:10)(cid:3)’(cid:12)(cid:15)(cid:3)((cid:11)"’(cid:3)(cid:9)#(cid:10)(cid:10)(cid:15)(cid:16)’(cid:3)(cid:13)(cid:29)(cid:9)5(cid:29)(cid:18)(cid:15)(cid:3)$(cid:10)(cid:29)+(cid:8)(cid:16)(cid:18)")(cid:3)(cid:13)(cid:17)(cid:15)(cid:29)"(cid:15)(cid:3)"(cid:15)(cid:15)(cid:3)’(cid:12)(cid:15)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:3) (cid:29)(cid:9)5(cid:29)(cid:18)(cid:8)(cid:16)(cid:18)(cid:3)(cid:23)(cid:13)(cid:15)(cid:9)(cid:8)&(cid:8)(cid:9)(cid:29)’(cid:8)(cid:11)(cid:16)(cid:3)(cid:17)(cid:11)(cid:9)(cid:29)’(cid:15)$(cid:3)(cid:29)’(cid:3) (cid:12)’’(cid:13)366+++(cid:21)((cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:21)(cid:9)(cid:11)(6(cid:13)(cid:29)(cid:9)5(cid:29)(cid:18)(cid:8)(cid:16)(cid:18)  2011-2014 Microchip Technology Inc. DS40001579E-page 425

PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001579E-page 426  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2014 Microchip Technology Inc. DS40001579E-page 427

PIC16(L)F1782/3 DS40001579E-page 428  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (04/2011) Original release. Revision B (06/2011) Revised Section 18.0; Revised Table 30-8; Add Operational Amplifier Table. Revision C (03/2012) Electrical Specifications update. Revision D (11/2012) Revised: Table 5-4, Section 6.2.1.3, 9.0, Table 15-1 (LDO), Figure 16-1, Section 17.1.6, 17.2.3, 20.7, 24.1, 24.1.1-24.1.3, 24.2.7, 24.2.8, 24.3.4.1, 24.3.11, 24.8.1.1-24.8.1.3; Register 24.2 (PxMSRC descrip- tion); Registers 24-9-24-13, 24-16, 25-1 (Bits 0-3 descriptions); Add Table 16-2, Section 24.2.7.3. Electrical Specifications update: Revised 30.2 (D010, D012), 30.3 (D023, D025, D026, D029-D031); Table 30-4 (delete Note 2); Table 30-1 (Param. OPA08, OPA09), Table 30-11, Table 30-12 (Param. DAC02). Revision E (3/2014) Change from Preliminary to Final data sheet. Corrected the following Tables: Family Types Table on page 3, Table 3-3, Table 3-8, Table 20-3, Table 22-2, Table 22-3, Table 23-1, Table 25-3, Table 30-1, Table 30-2, Table 30-3, Table 30-6, Table 30-7, Table 30-13, Table 30-14, Table 30-15, Table 30-16, Table 30-20. Corrected the following Sections: Section 3.2, Section 9.2, Section 13.3, Section 17.1.6, Section 15.1, Section 15.3, Section 17.2.5, Section 18.2, Section 18.3, Sec- tion 19.0, Section 22.6.5, Section 22.9, Section 23.0, Section 23.1, Section 24.2.4, Section 24.2.5, Section 24.2.7, Section 24.8, Section 25.0, Section 26.6.7.4, Section 30.3. Corrected the following Registers: Register 4-2, Regis- ter 8-2, Register 8-5, Register 17-3, Register 18-1, Register 24-3, Register 24-4. Corrected Equation 17-1. Corrected Figure 30-9. Removed Figure 24-21.  2011-2014 Microchip Technology Inc. DS40001579E-page 429

PIC16(L)F1782/3 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. DS40001579E-page 430  2011-2014 Microchip Technology Inc.

PIC16(L)F1782/3 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) - X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC16LF1782T- I/MV 301 Option Range Tape and Reel, Industrial temperature, UQFN package, QTP pattern #301 Device: PIC16F1782, PIC16LF1782, b) PIC16LF1783- I/P PIC16F1783, PIC16LF1783 Industrial temperature SPDIP package c) PIC16F1783- E/SS Tape and Reel Blank = Standard packaging (tube or tray) Extended temperature, Option: T = Tape and Reel(1) SSOP package Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Package: ML = QFN MV = UQFN Note 1: Tape and Reel identifier only appears in SP = SPDIP the catalog part number description. This SO = SOIC identifier is used for ordering purposes and SS = SSOP is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Pattern: QTP, SQTP, Code or Special Requirements Reel option. (blank otherwise) 2: Small form-factor packaging options may be available. Please check www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office.  2011-2014 Microchip Technology Inc. DS40001579E-page 431

PIC16(L)F1782/3 NOTES: DS40001579E-page 432  2011-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2011-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-63276-249-8 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2011-2014 Microchip Technology Inc. DS40001579E-page 433

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2943-5100 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://www.microchip.com/ support Fax: 852-2401-3431 India - Pune France - Paris Web Address: Australia - Sydney Tel: 91-20-3019-1500 Tel: 33-1-69-53-63-20 Tel: 61-2-9868-6733 Fax: 33-1-69-30-90-79 www.microchip.com Japan - Osaka Fax: 61-2-9868-6755 Atlanta Tel: 81-6-6152-7160 Germany - Dusseldorf Duluth, GA China - Beijing Fax: 81-6-6152-9310 Tel: 49-2129-3766400 Tel: 86-10-8569-7000 TFealx: :6 67788-9-95577-9-1641545 Fax: 86-10-8528-2104 JTealp: a8n1 --3 T-6o8k8y0o- 3770 GTeel:r m49a-n8y9 --6 M27u-n1i4c4h-0 China - Chengdu Fax: 49-89-627-144-44 Austin, TX Fax: 81-3-6880-3771 Tel: 86-28-8665-5511 Tel: 512-257-3370 Germany - Pforzheim Korea - Daegu Fax: 86-28-8665-7889 Tel: 49-7231-424750 Boston Tel: 82-53-744-4301 Westborough, MA China - Chongqing Fax: 82-53-744-4302 Italy - Milan Tel: 774-760-0087 Tel: 86-23-8980-9588 Tel: 39-0331-742611 Korea - Seoul Fax: 774-760-0088 Fax: 86-23-8980-9500 Tel: 82-2-554-7200 Fax: 39-0331-466781 Chicago China - Hangzhou Fax: 82-2-558-5932 or Italy - Venice Itasca, IL Tel: 86-571-8792-8115 82-2-558-5934 Tel: 39-049-7625286 Tel: 630-285-0071 Fax: 86-571-8792-8116 Malaysia - Kuala Lumpur Netherlands - Drunen Fax: 630-285-0075 China - Hong Kong SAR Tel: 60-3-6201-9857 Tel: 31-416-690399 Cleveland Tel: 852-2943-5100 Fax: 60-3-6201-9859 Fax: 31-416-690340 Independence, OH Fax: 852-2401-3431 Malaysia - Penang Poland - Warsaw Tel: 216-447-0464 China - Nanjing Tel: 60-4-227-8870 Tel: 48-22-3325737 Fax: 216-447-0643 Tel: 86-25-8473-2460 Fax: 60-4-227-4068 Spain - Madrid Dallas Fax: 86-25-8473-2470 Tel: 34-91-708-08-90 Philippines - Manila Addison, TX China - Qingdao Tel: 63-2-634-9065 Fax: 34-91-708-08-91 Tel: 972-818-7423 Tel: 86-532-8502-7355 Fax: 63-2-634-9069 Sweden - Stockholm Fax: 972-818-2924 Fax: 86-532-8502-7205 Tel: 46-8-5090-4654 Singapore Detroit Novi, MI China - Shanghai Tel: 65-6334-8870 UK - Wokingham Tel: 248-848-4000 Tel: 86-21-5407-5533 Fax: 65-6334-8850 Tel: 44-118-921-5800 Fax: 86-21-5407-5066 Taiwan - Hsin Chu Fax: 44-118-921-5820 Houston, TX Tel: 281-894-5983 China - Shenyang Tel: 886-3-5778-366 Tel: 86-24-2334-2829 Fax: 886-3-5770-955 Indianapolis Fax: 86-24-2334-2393 Noblesville, IN Taiwan - Kaohsiung Tel: 317-773-8323 China - Shenzhen Tel: 886-7-213-7830 Tel: 86-755-8864-2200 Fax: 317-773-5453 Taiwan - Taipei Fax: 86-755-8203-1760 Tel: 886-2-2508-8600 Los Angeles China - Wuhan Fax: 886-2-2508-0102 Mission Viejo, CA Tel: 86-27-5980-5300 Tel: 949-462-9523 Thailand - Bangkok Fax: 949-462-9608 Fax: 86-27-5980-5118 Tel: 66-2-694-1351 China - Xian Fax: 66-2-694-1350 New York, NY Tel: 631-435-6000 Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 San Jose, CA Tel: 408-735-9110 China - Xiamen Tel: 86-592-2388138 Canada - Toronto Fax: 86-592-2388130 Tel: 905-673-0699 Fax: 905-673-6509 China - Zhuhai Tel: 86-756-3210040 03/25/14 Fax: 86-756-3210049 DS40001579E-page 434  2011-2014 Microchip Technology Inc.