PIC16(L)F1512/3 28-Pin Flash Microcontrollers with XLP Technology High-Performance RISC CPU Analog Features • C Compiler Optimized Architecture • Analog-to-Digital Converter (ADC): • Only 49 Instructions - 10-bit resolution • Operating Speed: - Up to 17 channels - DC – 20MHz clock input @ 2.5V - Special Event Triggers - DC – 16MHz clock input @ 1.8V - Conversion available during Sleep - DC – 200 ns instruction cycle • Hardware Capacitive Voltage Divider (CVD) • Interrupt Capability with Automatic Context - Double sample conversions Saving - Two-result registers • 16-Level Deep Hardware Stack with Optional - Inverted acquisition Overflow/Underflow Reset - 7-bit pre-charge timer • Direct, Indirect and Relative Addressing modes: - 7-bit acquisition timer - Two full 16-bit File Select Registers (FSRs) - Two guard ring output drives - FSRs can read program and data memory - Adjustable sample and hold capacitor array • Voltage Reference module: Memory - Fixed Voltage Reference (FVR) with 1.024V, • Up to 7 Kbytes Linear Program Memory 2.048V and 4.096V output levels Addressing - Integrated Temperature Indicator • Up to 256 Linear Data Memory Addressing eXtreme Low-Power (XLP) Management • High-Endurance Flash Data Memory (HEF) PIC16LF1512/3 with XLP - 128B of nonvolatile data storage • Sleep mode: 20 nA @ 1.8V, typical • 100K erase/write cycles • Watchdog Timer: 300 nA @ 1.8V, typical Flexible Oscillator Structure • Secondary Oscillator: 600 nA @ 32 kHz, 1.8V, • 16 MHz Internal Oscillator Block: typical - Factory-calibrated to ± 1%, typical • Operating Current: 30A/MHz @ 1.8V, typical - Software selectable frequency range from Special Microcontroller Features 16MHz to 31kHz • 31kHz Low-Power Internal Oscillator • Operating Voltage Range: - 2.3V-5.5V (PIC16F1512/3) • External Oscillator Block with: - Four crystal/resonator modes up to 20 MHz - 1.8V-3.6V (PIC16LF1512/3) • Self-Programmable under Software Control - Three external clock modes up to 20 MHz • Fail-Safe Clock Monitor: • Power-on Reset (POR) • Power-up Timer (PWRT) - Allows for safe shutdown if peripheral clock • Programmable Low-Power Brown-out Reset stops (LPBOR) • Two-Speed Oscillator Start-up • Extended Watchdog Timer (WDT) • Oscillator Start-up Timer (OST) • In-Circuit Serial Programming™ (ICSP™) via Two Pins • In-Circuit Debug (ICD) via Two Pins • Enhanced Low-Voltage Programming (LVP) • Programmable Code Protection • Low-Power Sleep mode  2012-2016 Microchip Technology Inc. DS40001624D-page 1

PIC16(L)F1512/3 Peripheral Highlights • Up to 25 I/O Pins (1 input-only pin): - High current sink/source 25mA/25mA - Individually programmable weak pull-ups - Individually programmable interrupt-on-change (IOC) pins • Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Low-power 32 kHz secondary oscillator driver • Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler • Two Capture/Compare (CCP) modules: • Master Synchronous Serial Port (MSSP) with SPI and I2C with: - 7-bit address masking - SMBus/PMBusTM compatibility • Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module: - RS-232, RS-485 and LIN compatible - Auto-Baud Detect - Auto-wake-up on start DS40001624D-page 2  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 PIC16(L)F151X/152X Family Types sh ADC x y a Device Data Sheet Inde Program MemorFlash (words) Data SRAM(bytes) gh Endurance Fl(bytes) (2)I/Os 10-bit (ch) dvanced Control Timers(8/16-bit) EUSART 2MSSP (IC/SPI) CCP (1)Debug XLP Hi A PIC16(L)F1512 (1) 2048 128 128 25 17 Y 2/1 1 1 2 I Y PIC16(L)F1513 (1) 4096 256 128 25 17 Y 2/1 1 1 2 I Y PIC16(L)F1516 (2) 8192 512 128 25 17 N 2/1 1 1 2 I Y PIC16(L)F1517 (2) 8192 512 128 36 28 N 2/1 1 1 2 I Y PIC16(L)F1518 (2) 16384 1024 128 25 17 N 2/1 1 1 2 I Y PIC16(L)F1519 (2) 16384 1024 128 36 28 N 2/1 1 1 2 I Y PIC16(L)F1526 (3) 8192 768 128 54 30 N 6/3 2 2 10 I Y PIC16(L)F1527 (3) 16384 1536 128 54 30 N 6/3 2 2 10 I Y Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header. 2: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS40001624 PIC16(L)F1512/13 Data Sheet, 28-Pin Flash, 8-bit MCUs. 2: DS40001452 PIC16(L)F1516/7/8/9 Data Sheet, 28/40/44-Pin Flash, 8-bit MCUs. 3: DS40001458 PIC16(L)F1526/27 Data Sheet, 64-Pin Flash, 8-bit MCUs. FIGURE 1: 28-PIN SPDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1512/3 VPP/MCLR/RE3 1 28 RB7/ICSPDAT/ICDDAT RA0 2 27 RB6/ICSPCLK/ICDCLK RA1 3 26 RB5 RA2 4 25 RB4 RA3 5 24 RB3 RRVRAASAS457 6789 PIC16F1512/3PIC16LF1512/3 22220312 RRRVBBDBD102 RA6 10 19 VSS RC0 11 18 RC7 RC1 12 17 RC6 RC2 13 16 RC5 RC3 14 15 RC4  2012-2016 Microchip Technology Inc. DS40001624D-page 3

PIC16(L)F1512/3 FIGURE 2: 28-PIN UQFN (4X4) PACKAGE DIAGRAM FOR PIC16(L)F1512/3 TK AL DC DD CC PP T/IK/I V AL R/ DC L PP C SS M CC 1 0 3/ 7/I6/I54 A A E BBBB R R R RRRR 876 5432 222 2222 RA2 1 21 RB3 RA3 2 20 RB2 RA4 3 19 RB1 PIC16F1512/3 RA5 4 PIC16LF1512/3 18 RB0 VSS 5 17 VDD RA7 6 16 VSS RA6 7 15 RC7 0 1234 891 1111 01 2 3 456 CC C C CCC RR R R RRR DS40001624D-page 4  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1512/3) P O S S C, N I/O SPDIP, SOI 28-Pin UQF A/D Timers CCP EUSART MSSP Interrupt Pull-up Basic n Pi 8- 2 RA0 2 27 AN0 — — — SS(2) — — — RA1 3 28 AN1 — — — — — — — RA2 4 1 AN2 — — — — — — — RA3 5 2 AN3/VREF+ — — — — — — — RA4 6 3 — T0CKI — — — — — — RA5 7 4 AN4 — — — SS(1) — — VCAP RA6 10 7 — — — — — — — OSC2/CLKOUT RA7 9 6 — — — — — — — OSC1/CLKIN RB0 21 18 AN12 — — — — INT/IOC Y — RB1 22 19 AN10 — — — — IOC Y — RB2 23 20 AN8 — — — — IOC Y — RB3 24 21 AN9 — CCP2(2) — — IOC Y — RB4 25 22 AN11 — — — — IOC Y — ADOUT RB5 26 23 AN13 T1G — — — IOC Y — RB6 27 24 ADGRDA — — — — IOC Y ICSPCLK/ICDCLK RB7 28 25 ADGRDB — — — — IOC Y ICSPDAT/ICDDAT RC0 11 8 — SOSCO/T1CKI — — — — — — RC1 12 9 — SOSCI CCP2(1) — — — — — RC2 13 10 AN14 — CCP1 — — — — — RC3 14 11 AN15 — — — SCK/SCL — — — RC4 15 12 AN16 — — — SDI/SDA — — — RC5 16 13 AN17 — — — SDO — — — RC6 17 14 AN18 — — TX/CK — — — — RC7 18 15 AN19 — — RX/DT — — — — RE3 1 26 — — — — — — Y MCLR/VPP VDD 20 17 — — — — — — — — VSS 8,19 5,16 — — — — — — — — NC — — — — — — — — — — Note 1: Peripheral pin location selected using APFCON register. Default location. 2: Peripheral pin location selected using APFCON register. Alternate location.  2012-2016 Microchip Technology Inc. DS40001624D-page 5

PIC16(L)F1512/3 Table of Contents 1.0 Device Overview..........................................................................................................................................................................7 2.0 Enhanced Mid-range CPU.........................................................................................................................................................11 3.0 Memory Organization.................................................................................................................................................................13 4.0 Device Configuration..................................................................................................................................................................35 5.0 Oscillator Module (With Fail-Safe Clock Monitor).......................................................................................................................41 6.0 Resets........................................................................................................................................................................................56 7.0 Interrupts....................................................................................................................................................................................64 8.0 Power-Down Mode (Sleep)........................................................................................................................................................75 9.0 Low Dropout (LDO) Voltage Regulator......................................................................................................................................79 10.0 Watchdog Timer (WDT).............................................................................................................................................................80 11.0 Flash Program Memory Control.................................................................................................................................................84 12.0 I/O Ports...................................................................................................................................................................................100 13.0 Interrupt-On-Change................................................................................................................................................................115 14.0 Fixed Voltage Reference (FVR)...............................................................................................................................................119 15.0 Temperature Indicator Module.................................................................................................................................................121 16.0 Analog-to-Digital Converter (ADC) Module..............................................................................................................................123 17.0 Timer0 Module.........................................................................................................................................................................157 18.0 Timer1 Module with Gate Control.............................................................................................................................................160 19.0 Timer2 Module.........................................................................................................................................................................171 20.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................175 21.0 Capture/Compare/PWM Modules............................................................................................................................................228 22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................237 23.0 In-Circuit Serial Programming™ (ICSP™)...............................................................................................................................266 24.0 Instruction Set Summary..........................................................................................................................................................268 25.0 Electrical Specifications............................................................................................................................................................282 26.0 DC and AC Characteristics Graphs and Charts.......................................................................................................................312 27.0 Development Support...............................................................................................................................................................343 28.0 Packaging Information..............................................................................................................................................................347 The Microchip Website.......................................................................................................................................................................359 Customer Change Notification Service..............................................................................................................................................359 Customer Support..............................................................................................................................................................................359 Product Identification System.............................................................................................................................................................360 DS40001624D-page 6  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products.  2012-2016 Microchip Technology Inc. DS40001624D-page 7

PIC16(L)F1512/3 1.0 DEVICE OVERVIEW The PIC16(L)F1512/3 are described within this data sheet. They are available in 28-pin packages. Figure1-1 shows a block diagram of the PIC16(L)F1512/3 devices. Table1-2 shows the pinout descriptions. Reference Table1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY 2 3 1 1 5 5 1 1 F F Peripheral L) L) ( ( 6 6 1 1 C C PI PI Analog-to-Digital Converter (ADC) ● ● Fixed Voltage Reference (FVR) ● ● Temperature Indicator ● ● Capture/Compare/PWM Modules CCP1 ● ● CCP2 ● ● EUSARTs EUSART ● ● Master Synchronous Serial Ports MSSP ● ● Timers Timer0 ● ● Timer1 ● ● Timer2 ● ● DS40001624D-page 8  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 1-1: PIC16(L)F1512/3 BLOCK DIAGRAM Program Flash Memory RAM PORTA PORTB OSC2/CLKOUT Timing Generation OSC1/CLKIN CPU INTRC PORTC Oscillator (Figure2-1) MCLR PORTE Temp. ADC CCP1 Timer0 FVR Indicator 10-Bit CCP2 MSSP Timer1 Timer2 EUSART Note 1: See applicable chapters for more information on peripherals. 2: See Table1-1 for peripherals available on specific devices.  2012-2016 Microchip Technology Inc. DS40001624D-page 9

PIC16(L)F1512/3 TABLE 1-2: PIC16(L)F1512/3 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/SS(2) RA0 TTL CMOS General purpose I/O. AN0 AN — A/D Channel 0 input. SS ST — Slave Select input. RA1/AN1 RA1 TTL CMOS General purpose I/O. AN1 AN — A/D Channel 1 input. RA2/AN2 RA2 TTL CMOS General purpose I/O. AN2 AN — A/D Channel 2 input. RA3/AN3/VREF+ RA3 TTL CMOS General purpose I/O. AN3 AN — A/D Channel 3 input. VREF+ AN — A/D Positive Voltage Reference input. RA4/T0CKI RA4 TTL CMOS General purpose I/O. T0CKI ST — Timer0 clock input. RA5/AN4/SS(1)/VCAP RA5 TTL CMOS General purpose I/O. AN4 AN — A/D Channel 4 input. SS ST — Slave Select input. VCAP Power Power Filter capacitor for Voltage Regulator (PIC16(L)F1512/3 only). RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O. OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O. OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes). CLKIN ST — External clock input (EC mode). RB0/AN12/INT RB0 TTL CMOS General purpose I/O with IOC and WPU. AN12 AN — A/D Channel 12 input. INT ST — External interrupt. RB1/AN10 RB1 TTL CMOS General purpose I/O with IOC and WPU. AN10 AN — A/D Channel 10 input. RB2/AN8 RB2 TTL CMOS General purpose I/O with IOC and WPU. AN8 AN — A/D Channel 8 input. RB3/AN9/CCP2(2) RB3 TTL CMOS General purpose I/O with IOC and WPU. AN9 AN — A/D Channel 9 input. CCP2 ST CMOS Capture/Compare/PWM 2. RB4/AN11/ADOUT RB4 TTL CMOS General purpose I/O with IOC and WPU. AN11 AN — A/D Channel 11 input. ADOUT CMOS — A/D with CVD output. RB5/AN13/T1G RB5 TTL CMOS General purpose I/O with IOC and WPU. AN13 AN — A/D Channel 13 input. T1G ST — Timer1 Gate input. RB6/ICSPCLK/ADGRDA RB6 TTL CMOS General purpose I/O with IOC and WPU. ICSPCLK ST CMOS In-Circuit Data I/O. ADGRDA — CMOS Guard Ring output A. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Peripheral pin location selected using APFCON register (Register12-1). Default location. 2: Peripheral pin location selected using APFCON register (Register12-1). Alternate location. DS40001624D-page 10  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 1-2: PIC16(L)F1512/3 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RB7/ICSPDAT/ADGRDB RB7 TTL CMOS General purpose I/O with IOC and WPU. ICSPDAT ST CMOS ICSP™ Data I/O. ADGRDB — CMOS Guard Ring output B. RC0/SOSCO/T1CKI RC0 ST CMOS General purpose I/O. SOSCO — XTAL Secondary oscillator connection. T1CKI ST — Timer1 clock input. RC1/SOSCI/CCP2(1) RC1 ST CMOS General purpose I/O. SOSCI — XTAL Secondary oscillator connection. CCP2 ST CMOS Capture/Compare/PWM 2. RC2/AN14/CCP1 RC2 ST CMOS General purpose I/O. AN14 AN — A/D Channel 14 input. CCP1 ST CMOS Capture/Compare/PWM 1. RC3/AN15/SCK/SCL RC3 ST CMOS General purpose I/O. AN15 AN — A/D Channel 15 input. SCK ST CMOS SPI clock. SCL I2C OD I2C clock. RC4/AN16/SDI/SDA RC4 ST CMOS General purpose I/O. AN16 AN — A/D Channel 16 input. SDI ST — SPI data input. SDA I2C OD I2C data input/output. RC5/AN17/SDO RC5 ST CMOS General purpose I/O. AN17 AN — A/D Channel 17 input. SDO — CMOS SPI data output. RC6/AN18/TX/CK RC6 ST CMOS General purpose I/O. AN18 AN — A/D Channel 18 input. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. RC7/AN19/RX/DT RC7 ST CMOS General purpose I/O. AN19 AN — A/D Channel 19 input. RX ST — USART asynchronous input. DT ST CMOS USART synchronous data. RE3/MCLR/VPP RE3 ST — General purpose input with WPU. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Peripheral pin location selected using APFCON register (Register12-1). Default location. 2: Peripheral pin location selected using APFCON register (Register12-1). Alternate location.  2012-2016 Microchip Technology Inc. DS40001624D-page 11

PIC16(L)F1512/3 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. • Automatic Interrupt Context Saving • 16-level Stack with Overflow and Underflow • File Select Registers • Instruction Set 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section7.5 “Automatic Context Saving”, for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Under- flow will set the appropriate bit (STKOVF or STKUNF) in the PCON register and, if enabled, will cause a software Reset. See Section3.4 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section3.5 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section24.0 “Instruction Set Summary” for more details. DS40001624D-page 12  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 2-1: CORE BLOCK DIAGRAM 15 CCCooonnnfffiiiggguuurrraaatttiiiooonnn 15 888 DDDaaatttaaa BBBuuusss PPPrrrooogggrrraaammm CCCooouuunnnttteeerrr Flash X U Program M Memory 1886 -LLLeeevvveeell lSS Sttaataccckkk RAM (((111335---bbbiiittt))) PPPrrrooogggrrraaammm 111444 Program Memory 12 RAM Addr BBBuuusss Read (PMR) AAAddddddrrr MMMUUUXXX IIInnnssstttrrruuuccctttiiiooonnn Rrreeeggg Indirect DDDiiirrreeecccttt AAAddddddrrr 777 Addr 5 12 12 15 BFFSSSRRR Rrreeeggg FFFSSSRRR 0rr eeRggeg FFFSSSRRR1 rrReeeggg 15 SSSTTTAAATTTUUUSSS Rrreeeggg 888 333 MMMUUUXXX Power-up Timer IIInnnssstttrrruuuccctttiiiooonnn Oscillator DDDeeecccooodddeee a &&nd Start-up Timer AAALLLUUU CCCooonnntttrrrooolll Power-on OSC1/CLKIN Reset 888 TTTiiimmmiiinnnggg Watchdog OSC2/CLKOUT GGGeeennneeerrraaatttiiiooonnn Timer W Reg Brown-out Reset IIInnnttteeerrrnnnaaalll OOOsssccciiillllllaaatttooorrr BBBllloooccckkk VVVDDDDDD VVVSSSSSS  2012-2016 Microchip Technology Inc. DS40001624D-page 13

PIC16(L)F1512/3 3.0 MEMORY ORGANIZATION 3.1 Program Memory Organization These devices contain the following types of memory: The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program • Program Memory memory space. Table3-1 shows the memory sizes - Configuration Words implemented for these devices. Accessing a location - Device ID above these boundaries will cause a wrap-around within - User ID the implemented memory space. The Reset vector is at - Flash Program Memory 0000h and the interrupt vector is at 0004h (see Figure3-1 and Figure3-2). • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing TABLE 3-1: DEVICE SIZES AND ADDRESSES Program Memory Last Program Memory High-Endurance Flash Device Space (Words) Address Memory Address Range (1) PIC16F1512 2,048 07FFh 0780h-07FFh PIC16LF1512 PIC16F1513 4,096 0FFFh 0F80h-0FFFh PIC16LF1513 Note1: High-endurance Flash applies to low byte of each address in the range. DS40001624D-page 14  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 3-1: PROGRAM MEMORY MAP FIGURE 3-2: PROGRAM MEMORY MAP AND STACK FOR AND STACK FOR PIC16(L)F1512 PARTS PIC16(L)F1513 PARTS PC<14:0> PC<14:0> CALL, CALLW 15 CALL, CALLW 15 RETURN, RETLW RETURN, RETLW Interrupt, RETFIE Interrupt, RETFIE Stack Level 0 Stack Level 0 Stack Level 1 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h Interrupt Vector 0004h On-chip 0005h 0005h Program Page 0 Page 0 Memory 07FFh On-chip 07FFh Program 0800h 0800h Rollover to Page 0 Memory Wraps to Page 0 Page 1 0FFFh 1000h Rollover to Page 0 Wraps to Page 0 Wraps to Page 0 Rollover to Page 0 Rollover to Page 1 7FFFh 7FFFh  2012-2016 Microchip Technology Inc. DS40001624D-page 15

PIC16(L)F1512/3 3.1.1 READING PROGRAM MEMORY AS EXAMPLE 3-2: ACCESSING PROGRAM DATA MEMORY VIA FSR There are two methods of accessing constants in constants program memory. The first method is to use tables of DW DATA0 ;First constant DW DATA1 ;Second constant RETLW instructions. The second method is to set an DW DATA2 FSR to point to the program memory. DW DATA3 my_function 3.1.1.1 RETLW Instruction ;… LOTS OF CODE… The RETLW instruction can be used to provide access MOVLW DATA_INDEX to tables of constants. The recommended way to create ADDLW LOW constants such a table is shown in Example3-1. MOVWF FSR1L MOVLW HIGH constants; MSb is set automatically EXAMPLE 3-1: RETLW INSTRUCTION MOVWF FSR1H constants BTFSC STATUS, C ;carry from BRW ;Add Index in W to ADDLW? ;program counter to INCF FSR1H, f ;yes ;select data MOVIW 0[FSR1] RETLW DATA0 ;Index0 data ;THE PROGRAM MEMORY IS IN W RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;… LOTS OF CODE… MOVLW DATA_INDEX CALL constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If the code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example3-2 demonstrates accessing the program memory via an FSR. The High directive will set bit<7> if a label points to a location in program memory. DS40001624D-page 16  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 3.2 Data Memory Organization 3.2.1 CORE REGISTERS The data memory is partitioned in 32 memory banks The core registers contain the registers that directly with 128 bytes in a bank. Each bank consists of affect the basic operation. The core registers occupy (Figure3-3): the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These • 12 core registers registers are listed below in Table3-2. For detailed • 20 Special Function Registers (SFR) information, see Table3-8. • Up to 80 bytes of General Purpose RAM (GPR) • 16 bytes of common RAM TABLE 3-2: CORE REGISTERS The active bank is selected by writing the bank number Addresses BANKx into the Bank Select Register (BSR). Unimplemented x00h or x80h INDF0 memory will read as ‘0’. All data memory can be x01h or x81h INDF1 accessed either directly (via instructions that use the x02h or x82h PCL file registers) or indirectly via the two File Select x03h or x83h STATUS Registers (FSR). See Section3.5 “Indirect x04h or x84h FSR0L Addressing” for more information. x05h or x85h FSR0H Data memory uses a 12-bit address. The upper seven x06h or x86h FSR1L bits of the address define the Bank address and the x07h or x87h FSR1H lower five bits select the registers/RAM in that bank. x08h or x88h BSR x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON  2012-2016 Microchip Technology Inc. DS40001624D-page 17

PIC16(L)F1512/3 3.2.1.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register3-1, contains: as ‘000u u1uu’ (where u = unchanged). • the arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, • the Reset status SWAPF and MOVWF instructions are used to alter the The STATUS register can be the destination for any STATUS register, because these instructions do not instruction, like any other register. If the STATUS affect any Status bits. For other instructions not register is the destination for an instruction that affects affecting any Status bits (Refer to Section24.0 the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”). disabled. These bits are set or cleared according to the Note1: The C and DC bits operate as Borrow device logic. Furthermore, the TO and PD bits are not and Digit Borrow out bits, respectively, in writable. Therefore, the result of an instruction with the subtraction. STATUS register as destination may be different than intended. REGISTER 3-1: STATUS: STATUS REGISTER U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — — — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. DS40001624D-page 18  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 3.2.2 SPECIAL FUNCTION REGISTER FIGURE 3-3: BANKED MEMORY PARTITIONING The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function 7-bit Bank Offset Memory Region Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the 00h operation of the peripherals are described in the Core Registers appropriate peripheral chapter of this data sheet. (12 bytes) 0Bh 3.2.3 GENERAL PURPOSE RAM 0Ch There are up to 80bytes of GPR in each data memory Special Function Registers bank. The Special Function Registers occupy the 20 (20 bytes maximum) bytes after the core registers of every data memory 1Fh bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 20h 3.2.3.1 Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section3.5.2 “Linear Data Memory” for more information. General Purpose RAM (80 bytes maximum) 3.2.4 COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh 3.2.5 DEVICE MEMORY MAPS The memory maps for PIC16(L)F1512/3 are as shown in Table3-4 through Table3-7.  2012-2016 Microchip Technology Inc. DS40001624D-page 19

 TABLE 3-3: PIC16(L)F1512 MEMORY MAP (BANKS 0-7) 2 0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 1 2 -2 000h 080h 100h 180h 200h 280h 300h 380h 0 Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers 1 6 (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) M ic 00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh ro 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch — 28Ch — 30Ch — 38Ch — c h 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 30Dh — 38Dh — ip T 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh — 28Eh — 30Eh — 38Eh — e c 00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh — h n 010h PORTE 090h TRISE 110h — 190h — 210h WPUE 290h — 310h — 390h — o lo 011h PIR1 091h PIE1 111h — 191h PMADRL 211h SSPBUF 291h CCPR1L 311h — 391h — g y 012h PIR2 092h PIE2 112h — 192h PMADRH 212h SSPADD 292h CCPR1H 312h — 392h — Inc 013h — 093h — 113h — 193h PMDATL 213h SSPMSK 293h CCP1CON 313h — 393h — . 014h — 094h — 114h — 194h PMDATH 214h SSPSTAT 294h — 314h — 394h IOCBP 015h TMR0 095h OPTION_REG 115h — 195h PMCON1 215h SSPCON1 295h — 315h — 395h IOCBN 016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSPCON2 296h — 316h — 396h IOCBF 017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSPCON3 297h — 317h — 397h — 018h T1CON 098h — 118h — 198h — 218h — 298h CCPR2L 318h — 398h — 019h T1GCON 099h OSCCON 119h — 199h RCREG 219h — 299h CCPR2H 319h — 399h — 01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah — 39Ah — 01Bh PR2 09Bh ADRES0L 11Bh — 19Bh SPBRGL 21Bh — 29Bh — 31Bh — 39Bh — 01Ch T2CON 09Ch ADRES0H 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch — 01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh — 01Eh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh — 31Eh — 39Eh — 01Fh — 09Fh — 11Fh — 19Fh BAUDCON 21Fh — 29Fh — 31Fh — 39Fh — 020h 0A0h General Purpose 120h 1A0h 220h 2A0h 320h 3A0h General Register Purpose 0BFh 32 Bytes Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Register 0C0h Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 80 Bytes Unimplemented P Read as ‘0’ 06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh I 070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h C Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses 1 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh 6 Legend: = Unimplemented data memory locations, read as ‘0’. ( Note 1: PIC16F1512 only. L ) D S F 4 00 1 0 1 5 6 2 4 1 D -p 2 a ge / 2 3 0

D TABLE 3-4: PIC16(L)F1513 MEMORY MAP (BANKS 0-7) P S 40 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 I 0 C 0 000h 080h 100h 180h 200h 280h 300h 380h 1 62 Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers 1 4 (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) D 6 -p 00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh ag 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch — 28Ch — 30Ch — 38Ch — ( e L 2 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 30Dh — 38Dh — 1 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh — 28Eh — 30Eh — 38Eh — ) F 00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh — 010h PORTE 090h TRISE 110h — 190h — 210h WPUE 290h — 310h — 390h — 1 011h PIR1 091h PIE1 111h — 191h PMADRL 211h SSPBUF 291h CCPR1L 311h — 391h — 5 012h PIR2 092h PIE2 112h — 192h PMADRH 212h SSPADD 292h CCPR1H 312h — 392h — 1 013h — 093h — 113h — 193h PMDATL 213h SSPMSK 293h CCP1CON 313h — 393h — 2 014h — 094h — 114h — 194h PMDATH 214h SSPSTAT 294h — 314h — 394h IOCBP 015h TMR0 095h OPTION_REG 115h — 195h PMCON1 215h SSPCON1 295h — 315h — 395h IOCBN / 3 016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSPCON2 296h — 316h — 396h IOCBF 017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSPCON3 297h — 317h — 397h — 018h T1CON 098h — 118h — 198h — 218h — 298h CCPR2L 318h — 398h — 019h T1GCON 099h OSCCON 119h — 199h RCREG 219h — 299h CCPR2H 319h — 399h — 01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah — 39Ah — 01Bh PR2 09Bh ADRES0L 11Bh — 19Bh SPBRG 21Bh — 29Bh — 31Bh — 39Bh — 01Ch T2CON 09Ch ADRES0H 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch — 01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh — 01Eh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh — 31Eh — 39Eh — 01Fh — 09Fh — 11Fh — 19Fh BAUDCON 21Fh — 29Fh — 31Fh — 39Fh — 020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h General General General Purpose Purpose Purpose Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Register Register Register Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 80 Bytes 80 Bytes 80 Bytes 06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh 070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h  Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM 2 (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses 01 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 2 07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh -2 01 Legend: = Unimplemented data memory locations, read as ‘0’. 6 Note 1: PIC16F1513 only. M ic ro c h ip T e c h n o lo g y In c .

 TABLE 3-5: PIC16(L)F1512/3 MEMORY MAP (BANKS 8-30) 20 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 1 2 -2 400h 480h 500h 580h 600h 680h 700h 780h 0 Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers 1 6 (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) M ic 40Bh 48Bh 50Bh 58Bh 60Bh 68Bh 70Bh 78Bh ro 40Ch 48Ch 50Ch 58Ch 60Ch 68Ch 70Ch 78Ch c Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented h See Table3-6 ip Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ T 46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh e c 470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h h Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM n o (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses logy 47Fh 70h – 7Fh) 4FFh 70h – 7Fh) 57Fh 70h – 7Fh) 5FFh 70h – 7Fh) 67Fh 70h – 7Fh) 6FFh 70h – 7Fh) 77Fh 70h – 7Fh) 7FFh 70h – 7Fh) In c . BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23 800h 880h 900h 980h A00h A80h B00h B80h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) 80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh 80Ch 88Ch 90Ch 98Ch A0Ch A8Ch B0Ch B8Ch Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh 870h 8F0h 970h 9F0h A70h AF0h B70h BF0h Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31 C00h C80h D00h D80h E00h E80h F00h F80h P Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers I (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) C C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh F8Bh C0Ch C8Ch D0Ch D8Ch E0Ch E8Ch F0Ch F8Ch 1 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented See (Table3-7) 6 Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ ( C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh L C70h CF0h D70h DF0h E70h EF0h F70h FE0h Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM ) DS (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses F 4 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 00 C7Fh CFFh D7Fh DFFh E7Fh EFFh F7Fh FEFh 1 0 16 Legend: = Unimplemented data memory locations, read as ‘0’. 5 2 4 1 D -p 2 a ge / 2 3 2

PIC16(L)F1512/3 TABLE 3-6: PIC16(L)F1512/3 MEMORY TABLE 3-7: PIC16(L)F1512/3 MEMORY MAP (BANK 14) MAP (BANK 31) Bank 14 Bank 31 700h F80h Core Registers Core Registers (Table3-2) (Table3-2) 70Bh F8Bh 70Ch F8Ch Unimplemented Read as ‘0’ Unimplemented 710h Read as ‘0’ 711h AADCON0 712h AADCON1 FE3h 713h AADCON2 FE4h STATUS_SHAD 714h AADCON3 FE5h WREG_SHAD 715h AADSTAT FE6h BSR_SHAD 716h AADPRE FE7h PCLATH_SHAD 717h AADACQ FE8h FSR0L_SHAD 718h AADGRD FE9h FSR0H_SHAD 719h AADCAP FEAh FSR1L_SHAD 71Ah AADRES0L FEBh FSR1H_SHAD 71Bh AADRES0H FECh — 71Ch AADRES1L FEDh STKPTR 71Dh AADRES1H FEEh TOSL 71Eh — FEFh TOSH 71Fh — FF0h 720h Common RAM Unimplemented (Accesses Read as ‘0’ 70h – 7Fh) 76Fh FFFh 770h Common RAM (Accesses Legend: = Unimplemented data memory locations, 70h – 7Fh) 77Fh read as ‘0’. Legend: = Unimplemented data memory locations, read as ‘0’.  2012-2016 Microchip Technology Inc. DS40001624D-page 23

PIC16(L)F1512/3 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function Registers listed in Table3-8 can be addressed from any Bank. TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 0-31 x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory INDF0 xxxx xxxx uuuu uuuu x80h (not a physical register) x01h or Addressing this location uses contents of FSR1H/FSR1L to address data memory INDF1 xxxx xxxx uuuu uuuu x81h (not a physical register) x02h or PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x82h x03h or STATUS — — — TO PD Z DC C ---1 1000 ---q quuu x83h x04h or FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x84h x05h or FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x85h x06h or FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x86h x07h or FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x87h x08h or BSR — — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 x88h x09h or WREG Working Register 0000 0000 uuuu uuuu x89h x0Ah or PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 x8Ah x0Bh or INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 x8Bh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. DS40001624D-page 24  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 3.2.7 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Registers are listed in Table3-9. TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY Value on all Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 0 00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu 00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 00Fh — Unimplemented — — 010h PORTE — — — — RE3 — — — ---- x--- ---- u--- 011h PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 012h PIR2 OSFIF — — — BCLIF — — CCP2IF 0--- 0--0 0--- 0--0 013h — Unimplemented — — 014h — Unimplemented — — 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 0000 00-0 uuuu uu-u 019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu DONE 01Ah TMR2 Timer 2 Module Register 0000 0000 0000 0000 01Bh PR2 Timer 2 Period Register 1111 1111 1111 1111 01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000 01Dh — Unimplemented — — 01Eh — Unimplemented — — 01Fh — Unimplemented — — Bank 1 08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111 08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111 08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111 08Fh — Unimplemented — — 090h TRISE — — — — —(2) — — — ---- 1--- ---- 1--- 091h PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 092h PIE2 OSFIE — — — BCLIE — — CCP2IE 0--- 0--0 0--- 0--0 093h — Unimplemented — — 094h — Unimplemented — — 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111 096h PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu 097h WDTCON — — WDTPS<4:0> SWDTEN --01 0110 --01 0110 098h — Unimplemented — — 099h OSCCON — IRCF<3:0> — SCS<1:0> -011 1-00 -011 1-00 09Ah OSCSTAT SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS 0-q0 --00 q-qq --0q 09Bh ADRES0L(3) A/D Result Register Low xxxx xxxx uuuu uuuu 09Ch ADRES0H(3) A/D Result Register High xxxx xxxx uuuu uuuu 09Dh ADCON0(3) — CHS<4:0> GO/DONE ADON -000 0000 -000 0000 09Eh ADCON1(3) ADFM ADCS<2:0> — — ADPREF<1:0> 0000 --00 0000 --00 09Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16F1512/3 only. 2: Unimplemented, read as ‘1’. 3: This register is available in Bank 1 and Bank 14 under similar register names. See Table16-4.  2012-2016 Microchip Technology Inc. DS40001624D-page 25

PIC16(L)F1512/3 TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 2 10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu 10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu 10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu 10Fh to — Unimplemented — — 115h 116h BORCON SBOREN BORFS — — — — — BORRDY 10-- ---q uu-- ---u 117h FVRCON FVREN FVRRDY TSEN TSRNG — — ADFVR<1:0> 0q00 --00 0q00 --00 118h to — Unimplemented — — 11Ch 11Dh APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00 11Eh — Unimplemented — — 11Fh — Unimplemented — — Bank 3 18Ch ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 --1- 1111 18Dh ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111 18Eh ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 1111 1100 1111 1100 18Fh — Unimplemented — — 190h — Unimplemented — — 191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000 192h PMADRH — Program Memory Address Register High Byte 1000 0000 1000 0000 193h PMDATL Program Memory Data Register Low Byte xxxx xxxx uuuu uuuu 194h PMDATH — — Program Memory Data Register High Byte --xx xxxx --uu uuuu 195h PMCON1 —(2) CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000 196h PMCON2 Program Memory Control Register 2 0000 0000 0000 0000 197h VREGCON(1) — — — — — — VREGPM Reserved ---- --01 ---- --01 198h — Unimplemented — — 199h RCREG USART Receive Data Register 0000 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRGL BRG<7:0> 0000 0000 0000 0000 19Ch SPBRGH BRG<15:8> 0000 0000 0000 0000 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16F1512/3 only. 2: Unimplemented, read as ‘1’. 3: This register is available in Bank 1 and Bank 14 under similar register names. See Table16-4. DS40001624D-page 26  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 4 20Ch — Unimplemented — — 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 20Eh — Unimplemented — — 20Fh — Unimplemented — — 210h WPUE — — — — WPUE3 — — — ---- 1--- ---- 1--- 211h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 213h SSPMSK Synchronous Serial Port (I2C mode) Address Mask Register 1111 1111 1111 1111 214h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 215h SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000 216h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h to — Unimplemented — — 21Fh Bank 5 28Ch to — Unimplemented — — 290h 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 293h CCP1CON — — DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000 294h to — Unimplemented — — 297h 298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu 299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu 29Ah CCP2CON — — DC2B<1:0> CCP2M<3:0> --00 0000 --00 0000 29Bh to — Unimplemented — — 29Fh Bank 6 30Ch to — Unimplemented — — 31Fh Bank 7 38Ch to — Unimplemented — — 393h 394h IOCBP IOCBP<7:0> 0000 0000 0000 0000 395h IOCBN IOCBN<7:0> 0000 0000 0000 0000 396h IOCBF IOCBF<7:0> 0000 0000 0000 0000 397h to — Unimplemented — — 39Fh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16F1512/3 only. 2: Unimplemented, read as ‘1’. 3: This register is available in Bank 1 and Bank 14 under similar register names. See Table16-4.  2012-2016 Microchip Technology Inc. DS40001624D-page 27

PIC16(L)F1512/3 TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 8-13 x0Ch or x8Ch to — Unimplemented — — x1Fh or x9Fh Bank 14 70ch to — Unimplemented — — 710h 711h AADCON0(3) — CHS<4:0> GO/DONE ADON -000 0000 -000 0000 712h AADCON1(3) ADFM ADCS<2:0> — — ADPREF<1:0> 0000 --00 0000 --00 713h AADCON2 — TRIGSEL<2:0> — — — — -000 ---- -000 ---- 714h AADCON3 ADEPPOL ADIPPOL ADOLEN ADOEN ADOOEN — ADIPEN ADDSEN 0000 0-00 0000 0-00 715h AADSTAT — — — — — ADCONV ADSTG<1:0> ---- -000 ---- -000 716h AADPRE — ADPRE<6:0> -000 0000 -000 0000 717h AADACQ — ADACQ<6:0> -000 0000 -000 0000 718h AADGRD GRDBOE GRDAOE GRDPOL — — — — — 000- ---- 000- ---- 719h AADCAP — — — — — ADDCAP<2:0> ---- -000 ---- -000 71Ah AADRES0L(3) A/D Result 0 Register Low xxxx xxxx uuuu uuuu 71Bh AADRES0H(3) A/D Result 0 Register High xxxx xxxx uuuu uuuu 71Ch AADRES1L A/D Result 1 Register Low xxxx xxxx uuuu uuuu 71Dh AADRES1H A/D Result 1 Register High xxxx xxxx uuuu uuuu 71Eh — Unimplemented — — Bank 15-30 x0Ch or x8Ch to — Unimplemented — — x1Fh or x9Fh Bank 31 F8Ch to — Unimplemented — — FE3h FE4h STATUS_SHAD — — — — — Z DC C ---- -xxx ---- -uuu FE5h WREG_SHAD Working Register Shadow xxxx xxxx uuuu uuuu FE6h BSR_SHAD — — — Bank Select Register Shadow ---x xxxx ---u uuuu FE7h PCLATH_SHAD — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu FE9h FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu FEBh FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu FECh — Unimplemented — — FEDh STKPTR — — — Current Stack Pointer ---1 1111 ---1 1111 FEEh TOSL Top of Stack Low Byte xxxx xxxx uuuu uuuu FEFh TOSH — Top of Stack High Byte -xxx xxxx -uuu uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16F1512/3 only. 2: Unimplemented, read as ‘1’. 3: This register is available in Bank 1 and Bank 14 under similar register names. See Table16-4. DS40001624D-page 28  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 3.3 PCL and PCLATH 3.3.3 COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte A computed function CALL allows programs to maintain comes from the PCL register, which is a readable and tables of functions and provide another way to execute writable register. The high byte (PC<14:8>) is not directly state machines or look-up tables. When performing a readable or writable and comes from PCLATH. On any table read using a computed function CALL, care Reset, the PC is cleared. Figure3-4 shows the five should be exercised if the table location crosses a PCL situations for the loading of the PC. memory boundary (each 256-byte block). If using the CALL instruction, the PCH<2:0> and PCL FIGURE 3-4: LOADING OF PC IN registers are loaded with the operand of the CALL DIFFERENT SITUATIONS instruction. PCH<6:3> is loaded with PCLATH<6:3>. The CALLW instruction enables computed calls by 14 PCH PCL 0 Instruction with PC PCL as combining PCLATH and W to form the destination Destination address. A computed CALLW is accomplished by 6 7 0 8 loading the W register with the desired address and PCLATH ALU Result executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. 14 PCH PCL 0 3.3.4 BRANCHING PC GOTO, CALL The branching instructions add an offset to the PC. 6 4 0 11 This allows relocatable code and code that crosses PCLATH OPCODE <10:0> page boundaries. There are two forms of branching, 14 PCH PCL 0 BRW and BRA. The PC will have incremented to fetch PC CALLW the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be 6 7 0 8 crossed. PCLATH W If using BRW, load the W register with the desired 14 PCH PCL 0 unsigned address and execute BRW. The entire PC will PC BRW be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC+1+, 15 PC + W the signed value of the operand of the BRA instruction. 14 PCH PCL 0 PC BRA 15 PC + OPCODE <8:0> 3.3.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the PC to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the PC will change to the values contained in the PCLATH register and those being written to the PCL register. 3.3.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the PC (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, Implementing a Table Read (DS00556).  2012-2016 Microchip Technology Inc. DS40001624D-page 29

PIC16(L)F1512/3 3.4 Stack 3.4.1 ACCESSING THE STACK All devices have a 16-levelx15-bit wide hardware The stack is available through the TOSH, TOSL and stack (refer to Figures3-5 through3-8). The stack STKPTR registers. STKPTR is the current value of the space is not part of either program or data space. The Stack Pointer. TOSH:TOSL register pair points to the PC is PUSHed onto the stack when CALL or CALLW TOP of the stack. Both registers are read/writable. TOS instructions are executed or an interrupt causes a is split into TOSH and TOSL due to the 15-bit size of the branch. The stack is POPed in the event of a RETURN, PC. To access the stack, adjust the value of STKPTR, RETLW or a RETFIE instruction execution. PCLATH is which will position TOSH:TOSL, then read/write to not affected by a PUSH or POP operation. TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Word 2). This Note: Care should be taken when modifying the means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled. times, the seventeenth PUSH overwrites the value that During normal program operation, CALL, CALLW and was stored from the first PUSH. The eighteenth PUSH Interrupts will increment STKPTR while RETLW, overwrites the second PUSH (and so on). The RETURN, and RETFIE will decrement STKPTR. At any STKOVF and STKUNF flag bits will be set on an time STKPTR can be inspected to see how much stack Overflow/Underflow, regardless of whether the Reset is is left. The STKPTR always points at the currently used enabled. place on the stack. Therefore, a CALL or CALLW will Note1: There are no instructions/mnemonics increment the STKPTR and then write the PC, and a called PUSH or POP. These are actions return will unload the PC and then decrement STKPTR. that occur from the execution of the Reference Figure3-5 through3-8 for examples of CALL, CALLW, RETURN, RETLW and accessing the stack. RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1 Stack Reset Disabled TOSH:TOSL 0x0F STKPTR = 0x1F (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The 0x08 empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack 0x07 Overflow/Underflow Reset is enabled, the 0x06 TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is 0x05 disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x04 0x03 0x02 0x01 0x00 Stack Reset Enabled TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F (STVREN = 1) DS40001624D-page 30  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the return address will be placed in the 0x07 Program Counter and the Stack Pointer 0x06 decremented to the empty state (0x1F). 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL 0x00 Return Address STKPTR = 0x00 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an 0x0B interrupt, the stack looks like the figure on the left. A series of RETURN instructions 0x0A will repeatedly place the return addresses into the Program Counter and pop the stack. 0x09 0x08 0x07 TOSH:TOSL 0x06 Return Address STKPTR = 0x06 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address  2012-2016 Microchip Technology Inc. DS40001624D-page 31

PIC16(L)F1512/3 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address When the stack is full, the next CALL or 0x09 Return Address an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 0x08 Return Address so the stack will wrap and overwrite the return address at 0x00. If the Stack 0x07 Return Address Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will 0x06 Return Address not be overwritten. 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address TOSH:TOSL 0x00 Return Address STKPTR = 0x10 3.4.2 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Word 2 is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.5 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory DS40001624D-page 32  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 3-9: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Reserved 0x7FFF Address Range 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.  2012-2016 Microchip Technology Inc. DS40001624D-page 33

PIC16(L)F1512/3 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing Indirect Addressing 4 BSR 0 6 From Opcode 0 7 FSRxH 0 7 FSRxL 0 0 0 0 0 Bank Select Location Select Bank Select Location Select 00000 00001 00010 11111 0x00 0x7F Bank 0 Bank 1 Bank 2 Bank 31 DS40001624D-page 34  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 3.5.2 LINEAR DATA MEMORY 3.5.3 PROGRAM FLASH MEMORY The linear data memory is the region from FSR To make constant data access easier, the entire address 0x2000 to FSR address 0x29AF. This region is program Flash memory is mapped to the upper half of a virtual region that points back to the 80-byte blocks of the FSR address space. When the MSB of FSRnH is GPR memory in all the banks. set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the Unimplemented memory reads as 0x00. Use of the lower eight bits of each memory location is accessible linear data memory region allows buffers to be larger via INDF. Writing to the program Flash memory cannot than 80 bytes because incrementing the FSR beyond be accomplished via the FSR/INDF interface. All one bank will go directly to the GPR memory of the next instructions that access program Flash memory via the bank. FSR/INDF interface will require one additional The 16 bytes of common memory are not included in instruction cycle to complete. the linear data memory region. FIGURE 3-12: PROGRAM FLASH FIGURE 3-11: LINEAR DATA MEMORY MEMORY MAP MAP 7 FSRnH 0 7 FSRnL 0 7 FSRnH 0 7 FSRnL 0 1 0 0 1 Location Select 0x8000 0x0000 Location Select 0x2000 0x020 Bank 0 0x06F 0x0A0 Bank 1 Program 0x0EF Flash 0x120 Memory (low 8 Bank 2 bits) 0x16F 0xF20 Bank 30 0xFFFF 0x7FFF 0x29AF 0xF6F  2012-2016 Microchip Technology Inc. DS40001624D-page 35

PIC16(L)F1512/3 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. DS40001624D-page 36  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 FCMEN IESO CLKOUTEN BOREN<1:0> — bit 13 bit 8 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit If FOSC Configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin. All other FOSC modes: 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 Unimplemented: Read as ‘1’ bit 7 CP: Code Protection bit 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit. bit 5 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins  2012-2016 Microchip Technology Inc. DS40001624D-page 37

PIC16(L)F1512/3 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 LVP DEBUG LPBOR BORV STVREN — bit 13 bit 8 U-1 U-1 U-1 R/P-1 U-1 U-1 R/P-1 R/P-1 — — — VCAPEN(1) — — WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 LPBOR: Low-Power BOR bit 1 = Low-Power BOR is disabled 0 = Low-Power BOR is enabled bit 10 BORV: Brown-out Reset Voltage Selection bit(2) 1 = Brown-out Reset voltage (VBOR), low trip point selected 0 = Brown-out Reset voltage (VBOR), high trip point selected bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8-5 Unimplemented: Read as ‘1’ bit 4 VCAPEN: Voltage Regulator Capacitor Enable bits(1) If PIC16LF1512/3 (regulator disabled): These bits are ignored. All VCAP pin functions are disabled. If PIC16F1512/3 (regulator enabled): 0 = VCAP functionality is enabled on RA5 1 = All VCAP pin functions are disabled bit 3-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 2 kW Flash memory (PIC16(L)F1512 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by PMCON control 00 = 000h to 7FFh write-protected, no addresses may be modified by PMCON control 4 kW Flash memory (PIC16(L)F1513 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control 00 = 000h to FFFh write-protected, no addresses may be modified by PMCON control Note 1: PIC16F1512/3 only. 2: See VBOR parameter for specific trip point voltages. DS40001624D-page 38  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section4.3 “Write Protection” for more information. 4.3 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected. 4.4 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section11.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16(L)F151X/152X Memory Programming Specification” (DS41442).  2012-2016 Microchip Technology Inc. DS40001624D-page 39

PIC16(L)F1512/3 4.5 Device ID and Revision ID Development tools, such as device programmers and debuggers, may be used to read the Device ID and The memory location 8006h is where the Device ID and Revision ID. Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section11.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. REGISTER 4-3: DEVICEID: DEVICE ID REGISTER R R R R R R DEV<8:3> bit 13 bit 8 R R R R R R R R DEV<2:0> REV<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bit bit 13-5 DEV<8:0>: Device ID bits DEVICEID<13:0> Values Device DEV<8:0> REV<4:0> PIC16F1512 01 0111 000 x xxxx PIC16F1513 01 0110 010 x xxxx PIC16LF1512 01 0111 001 x xxxx PIC16LF1513 01 0111 010 x xxxx bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision (see Table under DEV<8:0> above). DS40001624D-page 40  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 5.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of eight FAIL-SAFE CLOCK MONITOR) clock modes. 1. ECL – External Clock Low-Power mode 5.1 Overview (0MHz to 0.5MHz) 2. ECM – External Clock Medium Power mode The oscillator module has a wide variety of clock (0.5MHz to 4MHz) sources and selection features that allow it to be used 3. ECH – External Clock High-Power mode in a wide range of applications while maximizing (4MHz to 20MHz) performance and minimizing power consumption. 4. LP – 32kHz Low-Power Crystal mode. Figure5-1 illustrates a block diagram of the oscillator module. 5. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz) Clock sources can be supplied from external oscillators, 6. HS – High Gain Crystal or Ceramic Resonator quartz crystal resonators, ceramic resonators and mode (4 MHz to 20 MHz) Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal 7. RC – External Resistor-Capacitor (RC). oscillators, with a choice of speeds selectable via 8. INTOSC – Internal oscillator (31kHz to 16 MHz). software. Additional clock features include: Clock Source modes are selected by the FOSC<2:0> • Selectable system clock source between external bits in the Configuration Words. The FOSC bits or internal sources via software. determine the type of oscillator that will be used when • Two-Speed Start-up mode, which minimizes the device is first powered. latency between external oscillator start-up and The EC clock mode relies on an external logic level code execution. signal as the device clock source. The LP, XT and HS • Fail-Safe Clock Monitor (FSCM) designed to clock modes require an external crystal or resonator to detect a failure of the external clock source (LP, be connected to the device. Each mode is optimized for XT, HS, EC or RC modes) and switch a different frequency range. The RC clock mode automatically to the internal oscillator. requires an external resistor and capacitor to set the • Oscillator Start-up Timer (OST) ensures stability oscillator frequency. of crystal oscillator sources The INTOSC internal oscillator block produces a low • Fast start-up oscillator allows internal circuits to and high frequency clock source, designated power up and stabilize before switching to the 16 LFINTOSC and HFINTOSC. (see Internal Oscillator MHz HFINTOSC Block, Figure5-1). A wide selection of device clock frequencies may be derived from these two clock sources.  2012-2016 Microchip Technology Inc. DS40001624D-page 41

PIC16(L)F1512/3 FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM Low-Power Mode Event Switch Primary Oscillator (SCS<1:0>) OSC2 Primary Oscillator (OSC) 2 OSC1 Primary Clock 00 C Secondary Oscillator lo c k SOSCO/ T1CKI Secondary Secondary Clock 01 S Oscillator w SOSCI (SOSC) itc h M U INTOSC X 1x Internal Oscillator IRCF<3:0> 4 4 Start-up /1 HF-16 MHz 1111 CLoongtircol //24 HHFF--48 MMHHzz 11111001Inte SPtrai1mr6t-a UMrypH OOz sscc Divide CircuitINTOSC /1///2136/86248 HHHFFFHH---FF521--05221005 MM kkkHHHHHzzzzz 1110101100101001110100101100///rnal Oscilla 0101t /256 HF-62.5 kHz 0100or M /512 HF-31.25 kHz 0011 0010u LF-INTOSC LF-31 kHz 0001x (31.25 kHz) 0000 DS40001624D-page 42  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 5.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully clock source to function. Examples are: oscillator static, stopping the external clock input will have the modules (EC mode), quartz crystal resonators or effect of halting the device while leaving all data intact. ceramic resonators (LP, XT and HS modes) and Upon restarting the external clock, the device will Resistor-Capacitor (RC) mode circuits. resume operation as if no time had elapsed. Internal clock sources are contained within the oscillator FIGURE 5-2: EXTERNAL CLOCK (EC) module. The internal oscillator block has two internal MODE OPERATION oscillators that are used to generate the internal system clock sources: the 16MHz High-Frequency Internal Oscillator and the 31kHz Low-Frequency Internal Clock from OSC1/CLKIN Oscillator (LFINTOSC). Ext. System The system clock can be selected between external or PIC® MCU internal clock sources via the System Clock Select OSC2/CLKOUT (SCS) bits in the OSCCON register. See Section5.3 FOSC/4 or I/O(1) “Clock Switching” for additional information. 5.2.1 EXTERNAL CLOCK SOURCES Note 1: Output depends upon the CLKOUTEN bit of the Configuration Words. An external clock source can be used as the device system clock by performing one of the following 5.2.1.2 LP, XT, HS Modes actions: The LP, XT and HS modes support the use of quartz • Program the FOSC<2:0> bits in the Configuration crystal resonators or ceramic resonators connected to Words to select an external clock source that will OSC1 and OSC2 (Figure5-3). The three modes select be used as the default system clock upon a a low, medium or high gain setting of the internal device Reset. inverter-amplifier to support various resonator types • Write the SCS<1:0> bits in the OSCCON register and speed. to switch the system clock source to: LP Oscillator mode selects the lowest gain setting of the - Secondary oscillator during run-time, or internal inverter-amplifier. LP mode current consumption - An external clock source determined by the is the least of the three modes. This mode is designed to value of the FOSC bits. drive only 32.768 kHz tuning-fork type crystals (watch See Section5.3 “Clock Switching”for more informa- crystals). tion. XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode 5.2.1.1 EC Mode current consumption is the medium of the three modes. The External Clock (EC) mode allows an externally This mode is best suited to drive resonators with a generated logic level signal to be the system clock medium drive level specification. source. When operating in this mode, an external clock HS Oscillator mode selects the highest gain setting of the source is connected to the OSC1 input. internal inverter-amplifier. HS mode current consumption OSC2/CLKOUT is available for general purpose I/O or is the highest of the three modes. This mode is best CLKOUT. Figure5-2 shows the pin connections for EC suited for resonators that require a high drive setting. mode. Figure5-3 and Figure5-4 show typical circuits for EC mode has three power modes to select from through quartz crystal and ceramic resonators, respectively. Configuration Words: • High power, 4-20MHz (FOSC = 111) • Medium power, 0.5-4MHz (FOSC = 110) • Low power, 0-0.5MHz (FOSC = 101)  2012-2016 Microchip Technology Inc. DS40001624D-page 43

PIC16(L)F1512/3 FIGURE 5-3: QUARTZ CRYSTAL FIGURE 5-4: CERAMIC RESONATOR OPERATION (LP, XT OR OPERATION HS MODE) (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN OSC1/CLKIN C1 To Internal C1 To Internal Logic Logic QCruyasrttazl RF(2) Sleep RP(3) RF(2) Sleep C2 RS(1) OSC2/CLKOUT C2 Ceramic RS(1) OSC2/CLKOUT Resonator Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 3: An additional parallel feedback resistor (RP) Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator according to type, package and operation. manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 5.2.1.3 Oscillator Start-up Timer (OST) 2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts expected for the application. 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer 3: For oscillator design assistance, reference (PWRT) has expired (if configured), or a wake-up from the following Microchip Applications Notes: Sleep. During this time, the program counter does not • AN826, Crystal Oscillator Basics and increment and program execution is suspended unless Crystal Selection for rfPIC® and PIC® either FSCM or Two-Speed Start-up are enabled, in Devices (DS00826) which case code will continue to execute while the OST • AN849, Basic PIC® Oscillator Design is counting. The OST ensures that the oscillator circuit, (DS00849) using a quartz crystal resonator or ceramic resonator, • AN943, Practical PIC® Oscillator has started and is providing a stable system clock to Analysis and Design (DS00943) the oscillator module. • AN949, Making Your Oscillator Work In order to minimize latency between external oscillator (DS00949) start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section5.4 “Two-Speed Clock Start-up Mode”). DS40001624D-page 44  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 5.2.1.4 Secondary Oscillator 5.2.1.5 External RC Mode The secondary oscillator is a separate crystal oscillator The external Resistor-Capacitor (RC) modes support that is associated with the Timer1 peripheral. It is the use of an external RC circuit. This allows the optimized for timekeeping operations with a 32.768 designer maximum flexibility in frequency choice while kHz crystal connected between the SOSCO and keeping costs to a minimum when clock accuracy is not SOSCI device pins. required. The secondary oscillator can be used as an alternate The RC circuit connects to OSC1. OSC2/CLKOUT is system clock source and can be selected during available for general purpose I/O or CLKOUT. The run-time using clock switching. Refer to Section5.3 function of the OSC2/CLKOUT pin is determined by the “Clock Switching” for more information. CLKOUTEN bit in Configuration Words. Figure5-6 shows the external RC mode connections. FIGURE 5-5: QUARTZ CRYSTAL OPERATION FIGURE 5-6: EXTERNAL RC MODES (SECONDARY OSCILLATOR) VDD PIC® MCU PIC® MCU REXT OSC1/CLKIN Internal Clock SOSCI CEXT C1 To Internal Logic VSS 32.768 kHz Quartz Crystal FOSC/4 or I/O(1) OSC2/CLKOUT C2 SOSCO Recommended values: 10 k  REXT  100 k, <3V 3 k  REXT  100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: Output depends upon the CLKOUTEN bit of Note 1: Quartz crystal characteristics vary the Configuration Words. according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications The RC oscillator frequency is a function of the supply and recommended application. voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting 2: Always verify oscillator performance over the oscillator frequency are: the VDD and temperature range that is • threshold voltage variation expected for the application. • component tolerances 3: For oscillator design assistance, reference • packaging variations in capacitance the following Microchip Applications Notes: The user also needs to take into account variation due • AN826, Crystal Oscillator Basics and to tolerance of the external RC components used. Crystal Selection for rfPIC® and PIC® Devices (DS00826) • AN849, Basic PIC® Oscillator Design (DS00849) • AN943, Practical PIC® Oscillator Analysis and Design (DS00943) • AN949, Making Your Oscillator Work (DS00949) • TB097, Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS (DS91097) • AN1288, Design Practices for Low-Power External Oscillators (DS01288)  2012-2016 Microchip Technology Inc. DS40001624D-page 45

PIC16(L)F1512/3 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.2 LFINTOSC The device may be configured to use the internal The Low-Frequency Internal Oscillator (LFINTOSC) is oscillator block as the system clock by performing one an uncalibrated 31kHz internal clock source. of the following actions: The output of the LFINTOSC connects to a postscaler • Program the FOSC<2:0> bits in Configuration and multiplexer (see Figure5-1). Select 31kHz, via Words to select the INTOSC clock source, which software, using the IRCF<3:0> bits of the OSCCON will be used as the default system clock upon a register. See Section5.2.2.4 “Internal Oscillator device Reset. Clock Switch Timing” for more information. The • Write the SCS<1:0> bits in the OSCCON register LFINTOSC is also the frequency for the Power-up Timer to switch the system clock source to the internal (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock oscillator during run-time. See Section5.3 Monitor (FSCM). “Clock Switching”for more information. The LFINTOSC is enabled by selecting 31kHz In INTOSC mode, OSC1/CLKIN is available for general (IRCF<3:0> bits of the OSCCON register=000) as the purpose I/O. OSC2/CLKOUT is available for general system clock source (SCS bits of the OSCCON purpose I/O or CLKOUT. register= 1x), or when any of the following are enabled: The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. • Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and The internal oscillator block has two independent • FOSC<2:0> = 100, or oscillators that provides the internal system clock source. • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ 1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at Peripherals that use the LFINTOSC are: 16MHz. • Power-up Timer (PWRT) 2. The LFINTOSC (Low-Frequency Internal • Watchdog Timer (WDT) Oscillator) is uncalibrated and operates at • Fail-Safe Clock Monitor (FSCM) 31kHz. The Low-Frequency Internal Oscillator Ready bit 5.2.2.1 HFINTOSC (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running. The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16MHz internal clock source. The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure5-1). The frequency derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section5.2.2.4 “Internal Oscillator Clock Switch Timing” for more information. The HFINTOSC is enabled by: • Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’. A fast start-up oscillator allows internal circuits to power up and stabilize before switching to HFINTOSC. The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running. The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. DS40001624D-page 46  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 5.2.2.3 Internal Oscillator Frequency 5.2.2.4 Internal Oscillator Clock Switch Selection Timing The system clock speed can be selected via software When switching between the HFINTOSC and the using the Internal Oscillator Frequency Select bits LFINTOSC, the new oscillator may already be shut IRCF<3:0> of the OSCCON register. down to save power (see Figure5-7). If this is the case, there is a delay after the IRCF<3:0> bits of the The output of the 16MHz HFINTOSC and 31kHz OSCCON register are modified before the frequency LFINTOSC connects to a postscaler and multiplexer selection takes place. The OSCSTAT register will (see Figure5-1). The Internal Oscillator Frequency reflect the current active status of the HFINTOSC and Select bits IRCF<3:0> of the OSCCON register select LFINTOSC oscillators. The sequence of a frequency the frequency output of the internal oscillators. One of selection is as follows: the following frequencies can be selected via software: 1. IRCF<3:0> bits of the OSCCON register are • HFINTOSC modified. - 16 MHz 2. If the new clock is shut down, a clock start-up - 8 MHz delay is started. - 4 MHz 3. Clock switch circuitry waits for a falling edge of - 2 MHz the current clock. - 1 MHz 4. The current clock is held low and the clock - 500 kHz (default after Reset) switch circuitry waits for a rising edge in the new - 250 kHz clock. - 125 kHz 5. The new clock is now active. - 62.5 kHz 6. The OSCSTAT register is updated as required. - 31.25 kHz 7. Clock switch is complete. • LFINTOSC See Figure5-7 for more details. • 31 kHz If the internal oscillator speed is switched between two Note: Following any Reset, the IRCF<3:0> bits clocks of the same source, there is no start-up delay of the OSCCON register are set to ‘0111’ before the new frequency is selected. Clock switching and the frequency selection is set to time delays are shown in Table5-1. 500kHz. The user can modify the IRCF Start-up delay specifications are located in the bits to select a different frequency. oscillator tables of Section25.0 “Electrical The IRCF<3:0> bits of the OSCCON register allow Specifications”. duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.  2012-2016 Microchip Technology Inc. DS40001624D-page 47

PIC16(L)F1512/3 FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC Oscillator Delay(1) 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC   IRCF <3:0> 0 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Oscillator Delay(1) 2-cycle Sync Running HFINTOSC IRCF <3:0> = 0  0 System Clock Note1: See Table5-1 for more information. DS40001624D-page 48  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 5.3 Clock Switching 5.3.3 SECONDARY OSCILLATOR The system clock source can be switched between The secondary oscillator is a separate crystal oscillator external and internal clock sources via software using associated with the Timer1 peripheral. It is optimized the System Clock Select (SCS) bits of the OSCCON for timekeeping operations with a 32.768 kHz crystal register. The following clock sources can be selected connected between the SOSCO and SOSCI device using the SCS bits: pins. • Default system oscillator determined by FOSC The secondary oscillator is enabled using the bits in Configuration Words T1OSCEN control bit in the T1CON register. See Section18.0 “Timer1 Module with Gate Control” for • Secondary oscillator 32 kHz crystal more information about the Timer1 peripheral. • Internal Oscillator Block (INTOSC) 5.3.4 SECONDARY OSCILLATOR READY 5.3.1 SYSTEM CLOCK SELECT (SCS) (SOSCR) BIT BITS The user must ensure that the secondary oscillator is The System Clock Select (SCS) bits of the OSCCON ready to be used before it is selected as a system clock register selects the system clock source that is used for source. The Secondary Oscillator Ready (SOSCR) bit the CPU and peripherals. of the OSCSTAT register indicates whether the • When the SCS bits of the OSCCON register = 00, secondary oscillator is ready to be used. After the the system clock source is determined by value of SOSCR bit is set, the SCS bits can be configured to the FOSC<2:0> bits in the Configuration Words. select the secondary oscillator. • When the SCS bits of the OSCCON register = 01, the system clock source is the secondary oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table5-1. 5.3.2 OSCILLATOR START-UP TIMER STATUS (OSTS) BIT The Oscillator Start-up Timer Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the secondary oscillator.  2012-2016 Microchip Technology Inc. DS40001624D-page 49

PIC16(L)F1512/3 5.4 Two-Speed Clock Start-up Mode 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode provides additional power savings by minimizing the latency between external Two-Speed Start-up mode is configured by the oscillator start-up and code execution. In applications following settings: that make heavy use of the Sleep mode, Two-Speed • IESO (of the Configuration Words) = 1; Start-up will remove the external oscillator start-up Internal/External Switchover bit (Two-Speed time from the time spent awake and can reduce the Start-up mode enabled). overall power consumption of the device. This mode • SCS (of the OSCCON register) = 00. allows the application to wake-up from Sleep, perform • FOSC<2:0> bits in the Configuration Words a few instructions using the INTOSC internal oscillator configured for LP, XT or HS mode. block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up mode is entered after: Two-Speed Start-up provides benefits when the • Power-on Reset (POR) and, if enabled, after oscillator module is configured for LP, XT or HS Power-up Timer (PWRT) has expired, or modes. The Oscillator Start-up Timer (OST) is enabled • Wake-up from Sleep. for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. Note: If FSCM is enabled, Two-Speed Start-up will automatically be enabled. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 5-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Oscillator Delay LFINTOSC 1 cycle of each clock source HFINTOSC 2s (approx.) Any clock source ECH, ECM, ECL, EXTRC 2 cycles LP, XT, HS 1024 Clock Cycles (OST) Secondary Oscillator 1024 Secondary Oscillator Cycles DS40001624D-page 50  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 5.4.2 TWO-SPEED START-UP 5.4.3 CHECKING TWO-SPEED CLOCK SEQUENCE STATUS 1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCSTAT 2. Instructions begin execution by the internal register will confirm if the microcontroller is running oscillator at the frequency set in the IRCF<3:0> from the external clock source, as defined by the bits of the OSCCON register. FOSC<2:0> bits in the Configuration Words, or the internal oscillator. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. 5. OSTS is set. 6. System clock held low until the next falling edge of new clock (LP, XT or HS mode). 7. System clock is switched to external clock source. FIGURE 5-8: TWO-SPEED START-UP INTOSC TTOST OSC1 0 1 1022 1023 OSC2 Program Counter P C - N PC PC + 1 System Clock  2012-2016 Microchip Technology Inc. DS40001624D-page 51

PIC16(L)F1512/3 5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset or to continue operating should the external oscillator fail. changing the SCS bits of the OSCCON register. When The FSCM can detect oscillator failure any time after the SCS bits are changed, the OST is restarted. While the Oscillator Start-up Timer (OST) has expired. The the OST is running, the device continues to operate FSCM is enabled by setting the FCMEN bit in the from the INTOSC selected in OSCCON. When the Configuration Words. The FSCM is applicable to all OST times out, the Fail-Safe condition is cleared and external Oscillator modes (LP, XT, HS, EC, RC and the device will be operating from the external clock secondary oscillator). source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. FIGURE 5-9: FSCM BLOCK DIAGRAM 5.5.4 RESET OR WAKE-UP FROM SLEEP Clock Monitor The FSCM is designed to detect an oscillator failure Latch after the Oscillator Start-up Timer (OST) has expired. External S Q The OST is used after waking up from Sleep and after Clock any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as LFINTOSC soon as the Reset or wake-up has completed. When Oscillator ÷ 64 R Q the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing 31 kHz 488 Hz code while the OST is operating. (~32 s) (~2 ms) Note: Due to the wide range of oscillator start-up Sample Clock Clock times, the Fail-Safe circuit is not active Failure during oscillator start-up (i.e., after exiting Detected Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to 5.5.1 FAIL-SAFE DETECTION verify the oscillator start-up and that the The FSCM module detects a failed oscillator by system clock switchover has successfully comparing the external oscillator to the FSCM sample completed. clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure5-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. DS40001624D-page 52  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.  2012-2016 Microchip Technology Inc. DS40001624D-page 53

PIC16(L)F1512/3 5.6 Oscillator Control Registers REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0 — IRCF<3:0> — SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 1111 = 16MHz 1110 = 8MHz 1101 = 4MHz 1100 = 2MHz 1011 = 1MHz 1010 = 500kHz(1) 1001 = 250kHz(1) 1000 = 125kHz(1) 0111 = 500kHz (default upon Reset) 0110 = 250kHz 0101 = 125kHz 0100 = 62.5kHz 001x = 31.25kHz 000x = 31kHz LF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Secondary oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words. Note 1: Duplicate frequency derived from HFINTOSC. DS40001624D-page 54  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/0 R-0/q SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 SOSCR: Secondary Oscillator Ready bit If T1OSCEN = 1: 1 = Secondary oscillator is ready 0 = Secondary oscillator is not ready If T1OSCEN = 0: 1 = Timer1 clock source is always ready bit 6 Unimplemented: Read as ‘0’ bit 5 OSTS: Oscillator Start-up Timer Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<2:0> = 100) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3-2 Unimplemented: Read as ‘0’ bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC 16 MHz oscillator is stable and is driving the INTOSC 0 = HFINTOSC 16 MHz is not stable, the start-up oscillator is driving INTOSC TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON — IRCF<3:0> — SCS<1:0> 54 OSCSTAT SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS 55 PIE2 OSFIE — — — BCLIE — — CCP2IE 71 PIR2 OSFIF — — — BCLIF — — CCP2IF 73 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 168 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 37 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.  2012-2016 Microchip Technology Inc. DS40001624D-page 55

PIC16(L)F1512/3 6.0 RESETS A simplified block diagram of the On-Chip Reset Circuit is shown in Figure6-1. There are multiple ways to reset this device: • Power-on Reset (POR) • Brown-out Reset (BOR) • Low-Power Brown-out Reset (LPBOR) • MCLR Reset • WDT Reset • RESET instruction • Stack Overflow • Stack Underflow • Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT ICSP™ Programming Mode Exit RESET Instruction Stack Pointer MCLRE Sleep WDT Time-out Device Reset Power-on Reset VDD Brown-out R PWRT Reset Done LPBOR Reset PWRTE LFINTOSC BOR Active(1) Note 1: See Table6-1 for BOR active conditions. DS40001624D-page 56  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 6.1 Power-on Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when VDD reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for performance may require greater than minimum VDD. execution protection can be implemented. The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in conditions have been met. Configuration Words. The four operating modes are: 6.1.1 POWER-UP TIMER (PWRT) • BOR is always on • BOR is off when in Sleep The Power-up Timer provides a nominal 64ms time- out on POR or Brown-out Reset. • BOR is controlled by software • BOR is always off The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to Refer to Table6-1 for more information. rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by enabled by clearing the PWRTE bit in Configuration configuring the BORV bit in Configuration Words. Words. A VDD noise rejection filter prevents the BOR from The Power-up Timer starts after the release of the POR triggering on small events. If VDD falls below VBOR for and BOR. a duration greater than parameter TBORDC, the device For additional information, refer to Application Note will reset. See Figure6-2 for more information. AN607, “Power-up Trouble Shooting” (DS00607). TABLE 6-1: BOR OPERATING MODES Instruction Execution upon: BOREN<1:0> SBOREN Device Mode BOR Mode Release of POR or Wake-up from Sleep 11 X X Active Waits for BOR ready(1) (BORRDY = 1) Awake Active 10 X Waits for BOR ready (BORRDY = 1) Sleep Disabled 1 X Active Waits for BOR ready(1) (BORRDY = 1) 01 0 X Disabled Begins immediately (BORRDY = x) 00 X X Disabled Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. 6.2.1 BOR IS ALWAYS ON 6.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Words are When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device programmed to ‘01’, the BOR is controlled by the start-up will be delayed until the BOR is ready and VDD SBOREN bit of the BORCON register. The device start- is higher than the BOR threshold. up is not delayed by the BOR ready condition or the BOR protection is active during Sleep. The BOR does VDD level. not delay wake-up from Sleep. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the 6.2.2 BOR IS OFF IN SLEEP BORRDY bit of the BORCON register. When the BOREN bits of Configuration Words are BOR protection is unchanged by Sleep. programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.  2012-2016 Microchip Technology Inc. DS40001624D-page 57

PIC16(L)F1512/3 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal < TPWRT Reset TPWRT(1) VDD VBOR Internal Reset TPWRT(1) Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’. REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Words  01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect. If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control): 1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Words. DS40001624D-page 58  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 6.3 Low-Power Brown-out Reset 6.5 Watchdog Timer (WDT) Reset (LPBOR) The Watchdog Timer generates a Reset if the firmware The Low-Power Brown-Out Reset (LPBOR) is an does not issue a CLRWDT instruction within the time-out essential part of the Reset subsystem. Refer to period. The TO and PD bits in the STATUS register are Figure6-1 to see how the BOR interacts with other changed to indicate the WDT Reset. See Section10.0 modules. “Watchdog Timer (WDT)” for more information. The LPBOR is used to monitor the external VDD pin. 6.6 RESET Instruction When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is A RESET instruction will cause a device Reset. The RI changed to indicate that a BOR Reset has occurred. bit in the PCON register will be set to ‘0’. See Table6-3 The same bit is set for both the BOR and the LPBOR. for default conditions after a RESET instruction has Refer to Register6-2. occurred. 6.3.1 ENABLING LPBOR 6.7 Stack Overflow/Underflow Reset The LPBOR is controlled by the LPBOREN bit of Configuration Words. When the device is erased, the The device can reset when the Stack Overflows or LPBOR module defaults to disabled. Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are 6.3.1.1 LPBOR Module Output enabled by setting the STVREN bit in Configuration Words. See Section3.4.2 “Overflow/Underflow The output of the LPBOR module is a signal indicating Reset” for more information. whether or not a Reset is to be asserted. This signal is to be OR’d together with the Reset signal of the BOR 6.8 Programming Mode Exit module to provide the generic BOR signal which goes to the PCON register and to the power control block. Upon exit of Programming mode, the device will behave as if a POR had just occurred. 6.4 MCLR 6.9 Power-Up Timer The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the The Power-up Timer optionally delays device execution MCLRE bit of Configuration Words and the LVP bit of after a BOR or POR event. This timer is typically used to Configuration Words (Register4-2). allow VDD to stabilize before allowing the device to start running. TABLE 6-2: MCLR CONFIGURATION The Power-up Timer is controlled by the PWRTE bit of Configuration Words. MCLRE LVP MCLR 0 0 Disabled 6.10 Start-up Sequence 1 0 Enabled Upon the release of a POR or BOR, the following must x 1 Enabled occur before the device will begin executing: 1. Power-up Timer runs to completion (if enabled). 6.4.1 MCLR ENABLED 2. Oscillator start-up timer runs to completion (if When MCLR is enabled and the pin is held low, the required for oscillator source). device is held in Reset. The MCLR pin is connected to 3. MCLR must be released (if enabled). VDD through an internal weak pull-up. The total time-out will vary based on oscillator configu- The device has a noise filter in the MCLR Reset path. ration and Power-up Timer configuration. See The filter will detect and ignore small pulses. Section5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for more information. Note: A Reset does not drive the MCLR pin low. The Power-up Timer and oscillator start-up timer run 6.4.2 MCLR DISABLED independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator start-up When MCLR is disabled, the pin functions as a general timer will expire. Upon bringing MCLR high, the device purpose input and the internal weak pull-up is under will begin execution immediately (see Figure6-3). This software control. See Section12.5 “PORTE Registers” is useful for testing purposes or to synchronize more for more information. than one device operating in parallel.  2012-2016 Microchip Technology Inc. DS40001624D-page 59

PIC16(L)F1512/3 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC DS40001624D-page 60  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table6-3 and Table6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during normal operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS(2) Program STATUS PCON Condition Counter Register Register Power-on Reset 0000h ---1 1000 00-1 110x MCLR Reset during normal operation 0000h ---u uuuu uu-u 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-u 0uuu WDT Reset 0000h ---0 uuuu uu-0 uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-u uuuu Brown-out Reset 0000h ---1 1uuu 00-1 11u0 Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-u uuuu RESET Instruction Executed 0000h ---u uuuu uu-u u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-u uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as ‘0’.  2012-2016 Microchip Technology Inc. DS40001624D-page 61

PIC16(L)F1512/3 6.12 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Reset Instruction Reset (RI) • MCLR Reset (RMCLR) • Watchdog Timer Reset (RWDT) • Stack Underflow Reset (STKUNF) • Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register6-2. REGISTER 6-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u STKOVF STKUNF — RWDT RMCLR RI POR BOR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware bit 5 Unimplemented: Read as ‘0’ bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) DS40001624D-page 62  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BORCON SBOREN BORFS — — — — — BORRDY 58 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 62 STATUS — — — TO PD Z DC C 18 WDTCON — — WDTPS<4:0> SWDTEN 82 Legend: — = unimplemented, reads as ‘0’. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.  2012-2016 Microchip Technology Inc. DS40001624D-page 63

PIC16(L)F1512/3 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • Operation • Interrupt Latency • Interrupts During Sleep • INT Pin • Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure7-1. FIGURE 7-1: INTERRUPT LOGIC TMR0IF Wake-up TMR0IE (If in Sleep mode) INTF Peripheral Interrupts INTE (TMR1IF) PIR1<0> IOCIF Interrupt (TMR1IE) PIE1<0> IOCIE to CPU PEIE PIRn<7> GIE PIEn<7> DS40001624D-page 64  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 7.1 Operation 7.2 Interrupt Latency Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the are enabled by setting the following bits: interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous • GIE bit of the INTCON register interrupts is three or four instruction cycles. For • Interrupt Enable bit(s) for the specific interrupt asynchronous interrupts, the latency is three to five event(s) instruction cycles, depending on when the interrupt • PEIE bit of the INTCON register (if the Interrupt occurs. See Figure7-2 and Figure7-3 for more details. Enable bit of the interrupt event is contained in the PIEx register) The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See Section7.5 “Automatic Context Saving”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.  2012-2016 Microchip Technology Inc. DS40001624D-page 65

PIC16(L)F1512/3 FIGURE 7-2: INTERRUPT LATENCY OSC1 Q1Q2Q3 Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC PC-1 PC PC+1 0004h 0005h Execute 1 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC+1/FSR New PC/ PC PC-1 PC ADDR PC+1 0004h 0005h Execute 2 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h) DS40001624D-page 66  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 (3) CLKOUT (4) INT pin (1) (1) (2) INTF (5) Interrupt Latency GIE INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section25.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.  2012-2016 Microchip Technology Inc. DS40001624D-page 67

PIC16(L)F1512/3 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section8.0 “Power- Down Mode (Sleep)” for more details. 7.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • W register • STATUS register (except for TO and PD) • BSR register • FSR registers • PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved. DS40001624D-page 68  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 7.6 Interrupt Control Registers Note: Interrupt flag bits are set when an interrupt 7.6.1 INTCON REGISTER condition occurs, regardless of the state of its corresponding enable bit or the Global The INTCON register is a readable and writable Enable bit, GIE, of the INTCON register. register that contains the various enable and flag bits User software should ensure the appropri- for TMR0 register overflow, interrupt-on-change and ate interrupt flag bits are clear prior to external INT pin interrupts. enabling an interrupt. REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Interrupt Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register have been cleared by software.  2012-2016 Microchip Technology Inc. DS40001624D-page 69

PIC16(L)F1512/3 7.6.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register7-2. set to enable any peripheral interrupt. REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 Gate Acquisition interrupt 0 = Disables the Timer1 Gate Acquisition interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt DS40001624D-page 70  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 7.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register7-3. set to enable any peripheral interrupt. REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 OSFIE — — — BCLIE — — CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt bit 6-4 Unimplemented: Read as ‘0’ bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP bus collision interrupt 0 = Disables the MSSP bus collision interrupt bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt  2012-2016 Microchip Technology Inc. DS40001624D-page 71

PIC16(L)F1512/3 7.6.4 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register7-4. condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 7-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending DS40001624D-page 72  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 7.6.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register7-5. condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 OSFIF — — — BCLIF — — CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6-4 Unimplemented: Read as ‘0’ bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending  2012-2016 Microchip Technology Inc. DS40001624D-page 73

PIC16(L)F1512/3 TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 159 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIE2 OSFIE — — — BCLIE — — CCP2IE 71 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 PIR2 OSFIF — — — BCLIF — — CCP2IF 73 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by interrupts. DS40001624D-page 74  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep The Power-Down mode is entered by executing a The device can wake-up from Sleep through one of the SLEEP instruction. following events: Upon entering Sleep mode, the following conditions 1. External Reset input on MCLR pin, if enabled exist: 2. BOR Reset, if enabled 1. WDT will be cleared but keeps running, if 3. POR Reset enabled for operation during Sleep. 4. Watchdog Timer, if enabled 2. PD bit of the STATUS register is cleared. 5. Any external interrupt 3. TO bit of the STATUS register is set. 6. Interrupts by peripherals capable of running 4. CPU clock is disabled. during Sleep (see individual peripheral for more 5. 31 kHz LFINTOSC is unaffected and peripherals information) that operate from it may continue operation in The first three events will cause a device Reset. The Sleep. last three events are considered a continuation of 6. Secondary oscillator is unaffected and peripherals program execution. To determine whether a device that operate from it may continue operation in Reset or wake-up event occurred, refer to Section6.11 Sleep. “Determining the Cause of a Reset”. 7. ADC is unaffected, if the dedicated FRC clock is When the SLEEP instruction is being executed, the next selected. instruction (PC + 1) is pre-fetched. For the device to 8. I/O ports maintain the status they had before wake-up through an interrupt event, the corresponding SLEEP was executed (driving high, low or high- interrupt enable bit must be enabled. Wake-up will impedance). occur regardless of the state of the GIE bit. If the GIE 9. Resets other than WDT are not affected by bit is disabled, the device continues execution at the Sleep mode. instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the Refer to individual chapters for more details on SLEEP instruction, the device will then call the Interrupt peripheral operation during Sleep. Service Routine. In cases where the execution of the To minimize current consumption, the following instruction following SLEEP is not desirable, the user conditions should be considered: should have a NOP after the SLEEP instruction. • I/O pins should not be floating The WDT is cleared when the device wakes up from • External circuitry sinking current from I/O pins Sleep, regardless of the source of wake-up. • Internal circuitry sourcing current from I/O pins • Current draw from pins with internal weak pull-ups • Modules using 31 kHz LFINTOSC • Modules using secondary oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include the FVR module. See Section14.0 “Fixed Voltage Reference (FVR)” for more information on this module.  2012-2016 Microchip Technology Inc. DS40001624D-page 75

PIC16(L)F1512/3 8.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the execution of a SLEEP instruction When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit - SLEEP instruction will be completely and interrupt flag bit set, one of the following will occur: executed - Device will immediately wake-up from Sleep • If the interrupt occurs before the execution of a SLEEP instruction - WDT and WDT prescaler will be cleared - SLEEP instruction will execute as a NOP - TO bit of the STATUS register will be set - WDT and WDT prescaler will not be cleared - PD bit of the STATUS register will be cleared - TO bit of the STATUS register will not be set Even if the flag bits were checked before executing a - PD bit of the STATUS register will not be SLEEP instruction, it may be possible for flag bits to cleared become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) CLKOUT(2) TOST(3) Interrupt flag Interrupt Latency(4) GIE bit Processor in (INTCON reg.) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC - 1) Sleep Inst(PC + 1) Forced NOP Forced NOP Inst(0004h) Note 1: External clock. High, Medium, Low mode assumed. 2: CLKOUT is shown here for timing reference. 3: TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section5.4 “Two-Speed Clock Start-up Mode”). 4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. DS40001624D-page 76  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 8.2 Low-Power Sleep Mode 8.2.2 PERIPHERAL USAGE IN SLEEP The PIC16F1512/3 device contains an internal Low Some peripherals that can operate in Sleep mode will Dropout (LDO) voltage regulator, which allows the not operate properly with the Low-Power Sleep mode device I/O pins to operate at voltages up to 5.5V while selected. The LDO will remain in the Normal Power the internal device logic operates at a lower voltage. mode when those peripherals are enabled. The Low- The LDO and its associated reference circuitry must Power Sleep mode is intended for use with these remain active when the device is in Sleep mode. The peripherals: PIC16F1512/3 allows the user to optimize the • Brown-Out Reset (BOR) operating current in Sleep, depending on the • Watchdog Timer (WDT) application requirements. • External interrupt pin/interrupt-on-change pins A Low-Power Sleep mode can be selected by setting • Timer1 (with external clock source) the VREGPM bit of the VREGCON register. With this • CCP (Capture mode) bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep. Note: The PIC16LF1512/3 does not have a 8.2.1 SLEEP CURRENT VS. WAKE-UP configurable Low-Power Sleep mode. TIME PIC16LF1512/3 is an unregulated device In the default operating mode, the LDO and reference and is always in the lowest power state circuitry remain in the normal configuration while in when in Sleep, with no wake-up time Sleep. The device is able to exit Sleep mode quickly penalty. This device has a lower maximum since all circuits remain active. In Low-Power Sleep VDD and I/O voltage than the mode, when waking up from Sleep, an extra delay time PIC16F1512/3. See Section25.0 is required for these circuits to return to the normal “Electrical Specifications” for more configuration and stabilize. information. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. 8.3 Power Control Registers REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 — — — — — — VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up 0 = Normal-Power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as ‘1’. Maintain this bit set. Note 1: PIC16F1512/3 only. 2: See Section25.0 “Electrical Specifications”.  2012-2016 Microchip Technology Inc. DS40001624D-page 77

PIC16(L)F1512/3 TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 117 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 117 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 117 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIE2 OSFIE — — — BCLIE — — CCP2IE 71 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 PIR2 OSFIF — — — BCLIF — — CCP2IF 73 STATUS — — — TO PD Z DC C 18 VREGCON(1) — — — — — — VREGPM Reserved 77 WDTCON — — WDTPS<4:0> SWDTEN 82 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode. Note 1: PIC16F1512/3 only. DS40001624D-page 78  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 9.0 LOW DROPOUT (LDO) On power-up, the external capacitor will load the LDO VOLTAGE REGULATOR voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source The PIC16F1512/3 has an internal Low Dropout charges the external capacitor. After the cap is fully Regulator (LDO) which provides operation above 3.6V. charged, the device is released from Reset. For more The LDO regulates a voltage for the internal device information on the constant current rate, refer to the logic while permitting the VDD and I/O pins to operate LDO Regulator Characteristics Table in Section25.0 at a higher voltage. There is no user enable/disable “Electrical Specifications”. control available for the LDO, it is always active. The PIC16LF1512/3 operates at a maximum VDD of 3.6V and does not incorporate an LDO. A device I/O pin may be configured as the LDO voltage output, identified as the VCAP pin. Although not required, an external low-ESR capacitor may be connected to the VCAP pin for additional regulator stability. The VCAPEN bit of Configuration Words determines which pin is assigned as the VCAP pin. Refer to Table9-1. TABLE 9-1: VCAPEN SELECT BIT VCAPEN Pin 0 RA5 TABLE 9-2: SUMMARY OF CONFIGURATION WORD WITH LDO Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 LVP DEBUG LPBOR BORV STVREN — CONFIG2 38 7:0 — — — VCAPEN — — WRT<1:0> Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO. Note 1: PIC16F1512/3 only.  2012-2016 Microchip Technology Inc. DS40001624D-page 79

PIC16(L)F1512/3 10.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (nominal) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0>=01 SWDTEN 23-bit Programmable WDTE<1:0>=11 LFINTOSC WDT Time-out Prescaler WDT WDTE<1:0>=10 Sleep WDTPS<4:0> DS40001624D-page 80  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 10.1 Independent Clock Source 10.3 Time-Out Period The WDT derives its time base from the 31kHz The WDTPS bits of the WDTCON register set the LFINTOSC internal oscillator. Time intervals in this time-out period from 1ms to 256 seconds (nominal). chapter are based on a nominal interval of 1ms. See After a Reset, the default time-out period is two Section25.0 “Electrical Specifications” for the seconds. LFINTOSC tolerances. 10.4 Clearing the WDT 10.2 WDT Operating Modes The WDT is cleared when any of the following The Watchdog Timer module has four operating modes conditions occur: controlled by the WDTE<1:0> bits in Configuration • Any Reset Words. See Table10-1. • CLRWDT instruction is executed 10.2.1 WDT IS ALWAYS ON • Device enters Sleep • Device wakes up from Sleep When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on. • Oscillator fail • WDT is disabled WDT protection is active during Sleep. • Oscillator Start-up Timer (OST) is running 10.2.2 WDT IS OFF IN SLEEP See Table10-2 for more information. When the WDTE bits of Configuration Words are set to ‘10’, the WDT is on, except in Sleep. 10.5 Operation During Sleep WDT protection is not active during Sleep. When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes 10.2.3 WDT CONTROLLED BY SOFTWARE counting. When the WDTE bits of Configuration Words are set to When the device exits Sleep, the WDT is cleared ‘01’, the WDT is controlled by the SWDTEN bit of the again. The WDT remains clear until the OST, if WDTCON register. enabled, completes. See Section5.0 “Oscillator WDT protection is unchanged by Sleep. See Module (With Fail-Safe Clock Monitor)” for more Table10-2 for more details. information on the OST. When a WDT time-out occurs while the device is in TABLE 10-1: WDT OPERATING MODES Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits Device WDT WDTE<1:0> SWDTEN in the STATUS register are changed to indicate the Mode Mode event. See Section3.0 “Memory Organization” and 11 X X Active The STATUS register (Register3-1) for more information. Awake Active 10 X Sleep Disabled 1 Active 01 X 0 Disabled 00 X X Disabled TABLE 10-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0>=00 WDTE<1:0>=01 and SWDTEN = 0 WDTE<1:0>=10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) Unaffected  2012-2016 Microchip Technology Inc. DS40001624D-page 81

PIC16(L)F1512/3 10.6 Watchdog Control Register REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 — — WDTPS<4:0> SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32) • • • 10011 = Reserved. Results in minimum interval (1:32) 10010 = 1:8388608 (223) (Interval 256s nominal) 10001 = 1:4194304 (222) (Interval 128s nominal) 10000 = 1:2097152 (221) (Interval 64s nominal) 01111 = 1:1048576 (220) (Interval 32s nominal) 01110 = 1:524288 (219) (Interval 16s nominal) 01101 = 1:262144 (218) (Interval 8s nominal) 01100 = 1:131072 (217) (Interval 4s nominal) 01011 = 1:65536 (Interval 2s nominal) (Reset value) 01010 = 1:32768 (Interval 1s nominal) 01001 = 1:16384 (Interval 512ms nominal) 01000 = 1:8192 (Interval 256ms nominal) 00111 = 1:4096 (Interval 128ms nominal) 00110 = 1:2048 (Interval 64ms nominal) 00101 = 1:1024 (Interval 32ms nominal) 00100 = 1:512 (Interval 16ms nominal) 00011 = 1:256 (Interval 8ms nominal) 00010 = 1:128 (Interval 4ms nominal) 00001 = 1:64 (Interval 2ms nominal) 00000 = 1:32 (Interval 1ms nominal) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. Note 1: Times are approximate. WDT time is based on 31kHz LFINTOSC. DS40001624D-page 82  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON — IRCF<3:0> — SCS<1:0> 54 STATUS — — — TO PD Z DC C 18 WDTCON — — WDTPS<4:0> SWDTEN 82 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer. TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 37 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.  2012-2016 Microchip Technology Inc. DS40001624D-page 83

PIC16(L)F1512/3 11.0 FLASH PROGRAM MEMORY 11.1.1 PMCON1 AND PMCON2 CONTROL REGISTERS PMCON1 is the control register for Flash program The Flash program memory is readable and writable memory accesses. during normal operation over the full VDD range. Program memory is indirectly addressed using Special Control bits RD and WR initiate read and write, Function Registers (SFRs). The SFRs used to access respectively. These bits cannot be cleared, only set, in program memory are: software. They are cleared by hardware at completion of the read or write operation. The inability to clear the • PMCON1 WR bit in software prevents the accidental, premature • PMCON2 termination of a write operation. • PMDATL The WREN bit, when set, will allow a write operation to • PMDATH occur. On power-up, the WREN bit is clear. The • PMADRL WRERR bit is set when a write operation is interrupted • PMADRH by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit When accessing the program memory, the and execute the appropriate error handling routine. PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the The PMCON2 register is a write-only register. Attempting PMADRH:PMADRL register pair forms a 2-byte word to read the PMCON2 register will return all ‘0’s. that holds the 15-bit address of the program memory To enable writes to the program memory, a specific location being read. pattern (the unlock sequence), must be written to the The write time is controlled by an on-chip timer. The write/ PMCON2 register. The required unlock sequence erase voltages are generated by an on-chip charge pump prevents inadvertent writes to the program memory rated to operate over the operating voltage range of the write latches and Flash program memory. device. 11.2 Flash Program Memory Overview The Flash program memory can be protected in two ways; by code protection (CP bit in Configuration Words) It is important to understand the Flash program memory and write protection (WRT<1:0> bits in Configuration structure for erase and programming operations. Flash Words). program memory is arranged in rows. A row consists of Code protection (CP = 0)(1), disables access, reading a fixed number of 14-bit program memory words. A row and writing, to the Flash program memory via external is the minimum size that can be erased by user software. device programmers. Code protection does not affect After a row has been erased, the user can reprogram the self-write and erase functionality. Code protection all or a portion of this row. Data to be written into the can only be reset by a device programmer performing program memory row is written to 14-bit wide data write a Bulk Erase to the device, clearing all Flash program latches. These write latches are not directly accessible memory, Configuration bits and User IDs. to the user, but may be loaded via sequential writes to Write protection prohibits self-write and erase to a the PMDATH:PMDATL register pair. portion or all of the Flash program memory as defined Note: If the user wants to modify only a portion by the bits WRT<1:0>. Write protection does not affect of a previously programmed row, then the a device programmers ability to read, write or erase the contents of the entire row must be read device. and saved in RAM prior to the erase. Note 1: Code protection of the entire Flash Then, new data and retained data can be program memory array is enabled by written into the write latches to reprogram clearing the CP bit of Configuration Words. the row of Flash program memory. However, any unprogrammed locations 11.1 PMADRL and PMADRH Registers can be written without first erasing the row. In this case, it is not necessary to save and The PMADRH:PMADRL register pair can address up rewrite the other previously programmed to a maximum of 32K words of program memory. When locations. selecting a program address value, the MSB of the See Table11-1 for Erase Row size and the number of address is written to the PMADRH register and the LSB write latches for Flash program memory. is written to the PMADRL register. DS40001624D-page 84  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 11-1: FLASH PROGRAM TABLE 11-1: FLASH MEMORY MEMORY READ ORGANIZATION BY DEVICE FLOWCHART Write Row Erase Device Latches (words) (words) Start Read Operation PIC16(L)F1512/3 32 32 11.2.1 READING THE FLASH PROGRAM Select MEMORY Program or Configuration Memory To read a program memory location, the user must: (CFGS) 1. Write the desired address to the PMADRH:PMADRL register pair. Select 2. Clear the CFGS bit of the PMCON1 register. Word Address 3. Then, set control bit RD of the PMCON1 register. (PMADRH:PMADRL) Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction Initiate Read operation immediately following the “BSF PMCON1,RD” instruction (RD = 1) to be ignored. The data is available in the very next cycle, in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions. Instruction Fetched ignored NOP execution forced PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user. Note: The two instructions following a program Instruction Fetched ignored memory read are required to be NOPs. NOP execution forced This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. Data read now in PMDATH:PMDATL End Read Operation  2012-2016 Microchip Technology Inc. DS40001624D-page 85

PIC16(L)F1512/3 FIGURE 11-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR PC PC + 1 PMADRH,PMADRL PPCC ++ 33 PC + 4 PC + 5 Flash Data INSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4) INSTR(PC + 1) INSTR(PC + 2) INSTR(PC - 1) BSF PMCON1,RD instruction ignored instruction ignored INSTR(PC + 3) INSTR(PC + 4) executed here executed here Forced NOP Forced NOP executed here executed here executed here executed here RD bit PMDATH PMDATL Register EXAMPLE 11-1: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL PMADRL ; Select Bank for PMCON registers MOVLW PROG_ADDR_LO ; MOVWF PMADRL ; Store LSB of address MOVLW PROG_ADDR_HI ; MOVWL PMADRH ; Store MSB of address BCF PMCON1,CFGS ; Do not select Configuration Space BSF PMCON1,RD ; Initiate read NOP ; Ignored (Figure 11-2) NOP ; Ignored (Figure 11-2) MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS40001624D-page 86  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 11.2.2 FLASH MEMORY UNLOCK FIGURE 11-3: FLASH PROGRAM SEQUENCE MEMORY UNLOCK SEQUENCE FLOWCHART The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing. The sequence must be Start executed and completed without interruption to Unlock Sequence successfully complete any of the following operations: • Row Erase • Load program memory write latches Write 055h to • Write of program memory write latches to PMCON2 program memory • Write of program memory write latches to User IDs Write 0AAh to PMCON2 The unlock sequence consists of the following steps: 1. Write 55h to PMCON2 Initiate 2. Write AAh to PMCON2 Write or Erase operation 3. Set the WR bit in PMCON1 (WR = 1) 4. NOP instruction 5. NOP instruction Instruction Fetched ignored Once the WR bit is set, the processor will always force NOP execution forced two NOP instructions. When an Erase Row or Program Row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is Instruction Fetched ignored complete and then resume with the next instruction. NOP execution forced When the operation is loading the program memory write latches, the processor will always force the two NOP instructions and continue uninterrupted with the next End instruction. Unlock Sequence Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed.  2012-2016 Microchip Technology Inc. DS40001624D-page 87

PIC16(L)F1512/3 11.2.3 ERASING FLASH PROGRAM FIGURE 11-4: FLASH PROGRAM MEMORY MEMORY ERASE FLOWCHART While executing code, program memory can only be erased by rows. To erase a row: 1. Load the PMADRH:PMADRL register pair with Start any address within the row to be erased. Erase Operation 2. Clear the CFGS bit of the PMCON1 register. 3. Set the FREE and WREN bits of the PMCON1 register. Disable Interrupts 4. Write 55h, then AAh, to PMCON2 (Flash (GIE = 0) programming unlock sequence). 5. Set control bit WR of the PMCON1 register to Select begin the erase operation. Program or Configuration Memory See Example11-2. (CFGS) After the “BSF PMCON1,WR” instruction, the processor requires two cycles to set up the erase operation. The Select Row Address user must place two NOP instructions immediately (PMADRH:PMADRL) following the WR bit set instruction. The processor will halt internal operations for the typical 2ms erase time. This is not Sleep mode as the clocks and peripherals Select Erase Operation will continue to run. After the erase cycle, the processor (FREE = 1) will resume operation with the third instruction after the PMCON1 write instruction. Enable Write/Erase Operation (WREN = 1) Unlock Sequence (FFIGigUurReE1 1x--3x) CPU stalls while Erase operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Erase Operation DS40001624D-page 88  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 EXAMPLE 11-2: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL PMADRL MOVF ADDRL,W ; Load lower 8 bits of erase address boundary MOVWF PMADRL MOVF ADDRH,W ; Load upper 6 bits of erase address boundary MOVWF PMADRH BCF PMCON1,CFGS ; Not configuration space BSF PMCON1,FREE ; Specify an erase operation BSF PMCON1,WREN ; Enable writes MOVLW 55h ; Start of required sequence to initiate erase MOVWF PMCON2 ; Write 55h RequiredSequence MMBOOSVVFLWWF 0PPAMMACChOO NN21 ,WR ;;; WSreitt eW RA Abhit to begin erase NOP ; NOP instructions are forced as processor starts NOP ; row erase of program memory. ; ; The processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction BCF PMCON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts  2012-2016 Microchip Technology Inc. DS40001624D-page 89

PIC16(L)F1512/3 11.2.4 WRITING TO FLASH PROGRAM The following steps should be completed to load the MEMORY write latches and program a row of program memory. These steps are divided into two parts. First, each write Program memory is programmed using the following latch is loaded with data from the PMDATH:PMDATL steps: using the unlock sequence with LWLO = 1. When the 1. Load the address in PMADRH:PMADRL of the last word to be loaded into the write latch is ready, the row to be programmed. LWLO bit is cleared and the unlock sequence 2. Load each write latch with data. executed. This initiates the programming operation, 3. Initiate a programming operation. writing all the latches into Flash program memory. 4. Repeat steps 1 through 3 until all data is written. Note: The special unlock sequence is required Before writing to program memory, the word(s) to be to load a write latch with data or initiate a written must be erased or previously unwritten. Flash programming operation. If the Program memory can only be erased one row at a time. unlock sequence is interrupted, writing to No automatic erase occurs upon the initiation of the the latches or program memory will not be write. initiated. Program memory can be written one or more words at 1. Set the WREN bit of the PMCON1 register. a time. The maximum number of words written at one 2. Clear the CFGS bit of the PMCON1 register. time is equal to the number of write latches. See 3. Set the LWLO bit of the PMCON1 register. Figure11-5 (row writes to program memory with 32 When the LWLO bit of the PMCON1 register is write latches) for more details. ‘1’, the write sequence will only load the write The write latches are aligned to the Flash row address latches and will not initiate the write to Flash boundary defined by the upper 10-bits of program memory. PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) 4. Load the PMADRH:PMADRL register pair with with the lower 5-bits of PMADRL, (PMADRL<4:0>) the address of the location to be written. determining the write latch being loaded. Write opera- 5. Load the PMDATH:PMDATL register pair with tions do not cross these boundaries. At the completion the program memory data to be written. of a program memory write operation, the data in the 6. Execute the unlock sequence (Section11.2.2 write latches is reset to contain 0x3FFF. “Flash Memory Unlock Sequence”). The write latch is now loaded. 7. Increment the PMADRH:PMADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is ‘0’, the write sequence will initiate the write to Flash program memory. 10. Load the PMDATH:PMDATL register pair with the program memory data to be written. 11. Execute the unlock sequence (Section11.2.2 “Flash Memory Unlock Sequence”). The entire program memory latch content is now written to Flash program memory. Note: The program memory write latches are reset to the blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example11-3. The initial address is loaded into the PMADRH:PMADRL register pair; the data is loaded using indirect addressing. DS40001624D-page 90  2012-2016 Microchip Technology Inc.

D FIGURE 11-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES P S 4 0 I 00 7 6 0 7 5 4 0 7 5 0 7 0 C 1 6 2 PMADRH PMADRL - - PMDATH PMDATL 1 4 D 6 -p - r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c4 c3 c2 c1 c0 6 8 ag ( e L 9 1 ) F 14 1 Program Memory Write Latches 5 10 5 1 14 14 14 14 2 / Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31 3 00h 01h 1Eh 1Fh PMADRL<4:0> 14 14 14 14 Row Addr Addr Addr Addr 000h 0000h 0001h 001Eh 001Fh 001h 0020h 0021h 003Eh 003Fh 002h 0040h 0041h 005Eh 005Fh CFGS = 0 3FEh 7FC0h 7FC1h 7FDEh 7FDFh  20 Row 3FFh 7FE0h 7FE1h 7FFEh 7FFFh 12-2 :PPMMAADDRRHL<<67::05>> ADdedcroedses Flash Program Memory 0 1 6 M ic ro 400h 8000h-8003h 8004h-8005h 8006h 8007h-8008h 8009h-801Fh c h ip T USER ID 0-3 reserved DEVICEID Configuration reserved ec CFGS = 1 REVID Words h n olo Configuration Memory g y In c .

PIC16(L)F1512/3 FIGURE 11-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine the number of Enable Write/Erase words to be written into the Program or Configuration Operation (WREN = 1) Memory. The number of words cannot exceed the number of words per row. Load the value to write (word_cnt) (PMDATH:PMDATL) Update the word counter Write Latches to Flash Disable Interrupts (word_cnt--) (LWLO = 0) (GIE = 0) Unlock Sequence Select Program or Config. Memory Last word to Yes F(Figiguurere1 1x--x3) (CFGS) write ? No CPU stalls while Write Select Row Address operation completes (PMADRH:PMADRL) (2ms typical) Unlock Sequence F(Figiguurere1 1x--x3) Select Write Operation (FREE = 0) Disable No delay when writing to Write/Erase Operation Program Memory Latches (WREN = 0) Load Write Latches Only (LWLO = 1) Re-enable Interrupts (GIE = 1) Increment Address (PMADRH:PMADRL++) End Write Operation DS40001624D-page 92  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 EXAMPLE 11-3: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL ; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) ; BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL PMADRH ; Bank 3 MOVF ADDRH,W ; Load initial address MOVWF PMADRH ; MOVF ADDRL,W ; MOVWF PMADRL ; MOVLW LOW DATA_ADDR ; Load initial data address MOVWF FSR0L ; MOVLW HIGH DATA_ADDR ; Load initial data address MOVWF FSR0H ; BCF PMCON1,CFGS ; Not configuration space BSF PMCON1,WREN ; Enable writes BSF PMCON1,LWLO ; Only Load Write Latches LOOP MOVIW FSR0++ ; Load first data byte into lower MOVWF PMDATL ; MOVIW FSR0++ ; Load second data byte into upper MOVWF PMDATH ; MOVF PMADRL,W ; Check if lower bits of address are '00000' XORLW 0x1F ; Check if we're on the last of 32 addresses ANDLW 0x1F ; BTFSC STATUS,Z ; Exit if last of 32 words, GOTO START_WRITE ; MOVLW 55h ; Start of required write sequence: MOVWF PMCON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0PPAMMACChOO NN21 ,WR ;;;; SWNerOtiP t WeiR n AsbAtihrtu cttoi obnesg ianr ew rfiotreced as processor ; loads program memory write latches NOP ; INCF PMADRL,F ; Still loading latches Increment address GOTO LOOP ; Write next latches START_WRITE BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program ; memory write MOVLW 55h ; Start of required write sequence: MOVWF PMCON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0PPAMMACChOO NN21 ,WR ;;;; SWNerOtiP t WeiR n AsbAtihrtu cttoi obnesg ianr ew rfiotreced as processor writes ; all the program memory write latches simultaneously NOP ; to program memory. ; After NOPs, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction BCF PMCON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts  2012-2016 Microchip Technology Inc. DS40001624D-page 93

PIC16(L)F1512/3 11.3 Modifying Flash Program Memory FIGURE 11-7: FLASH PROGRAM MEMORY MODIFY When modifying existing data in a program memory FLOWCHART row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: Start 1. Load the starting address of the row to be Modify Operation modified. 2. Read the existing data from the row into a RAM image. Read Operation 3. Modify the RAM image to contain the new data F(Figiguurere1 1x-.x2) to be written into program memory. 4. Load the starting address of the row to be rewritten. An image of the entire row read 5. Erase the program memory row. must be stored in RAM 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. Modify Image The words to be modified are changed in the RAM image Erase Operation F(Figiguurere1 1x-.x4) Write Operation use RAM image F(Figiugruere1 1x-.x5) End Modify Operation DS40001624D-page 94  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 11.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS=1 in the PMCON1 register. This is the region that would be pointed to by PC<15>=1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table11-1. When read access is initiated on an address outside the parameters listed in Table11-2, the PMDATH:PMDATL register pair is cleared, reading back ‘0’s. TABLE 11-1: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS=1) Address Function Read Access Write Access 8000h-8003h User IDs Yes Yes 8006h Device ID/Revision ID Yes No 8007h-8008h Configuration Words 1 and 2 Yes No EXAMPLE 11-4: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL PMADRL ; Select correct Bank MOVLW PROG_ADDR_LO ; MOVWF PMADRL ; Store LSB of address CLRF PMADRH ; Clear MSB of address BSF PMCON1,CFGS ; Select Configuration Space BCF INTCON,GIE ; Disable interrupts BSF PMCON1,RD ; Initiate read NOP ; Executed (See Figure 11-2) NOP ; Ignored (See Figure 11-2) BSF INTCON,GIE ; Restore interrupts MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2012-2016 Microchip Technology Inc. DS40001624D-page 95

PIC16(L)F1512/3 11.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 11-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation Fig(Fuirgeur1e1 x-2.x) PMDAT = No RAM image ? Yes Fail Verify Operation No Last Word ? Yes End Verify Operation DS40001624D-page 96  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 11.6 Flash Program Memory Control Registers REGISTER 11-2: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory REGISTER 11-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — PMDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory REGISTER 11-4: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address REGISTER 11-5: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — PMADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address  2012-2016 Microchip Technology Inc. DS40001624D-page 97

PIC16(L)F1512/3 REGISTER 11-6: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1(1) R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 — CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6 CFGS: Configuration Select bit 1 = Access Configuration, User ID and Device ID Registers 0 = Access Flash program memory bit 5 LWLO: Load Write Latches Only bit(3) 1 = Only the addressed program memory write latch is loaded/updated on the next WR command 0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches will be initiated on the next WR command bit 4 FREE: Program Flash Erase Enable bit 1 = Performs an erase operation on the next WR command (hardware cleared upon completion) 0 = Performs a write operation on the next WR command bit 3 WRERR: Program/Erase Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit). 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash bit 1 WR: Write Control bit 1 = Initiates a program Flash program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash read. Note 1: Unimplemented bit, read as ‘1’. 2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1). 3: The LWLO bit is ignored during a program memory erase operation (FREE = 1). DS40001624D-page 98  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 11-7: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PMCON1 — CFGS LWLO FREE WRERR WREN WR RD 98 PMCON2 Program Memory Control Register 2 99 PMADRL PMADRL<7:0> 97 PMADRH — PMADRH<6:0> 97 PMDATL PMDATL<7:0> 97 PMDATH — — PMDATH<5:0> 97 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module. TABLE 11-3: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 37 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> 13:8 — — LVP DEBUG LPBOR BORV STVREN — CONFIG2 38 7:0 — — — VCAPEN(1) — — WRT<1:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.  2012-2016 Microchip Technology Inc. DS40001624D-page 99

PIC16(L)F1512/3 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of Read LATx TRISx the device) • LATx registers (output latch) D Q Some ports may have one or more of the following Write LATx Write PORTx additional registers. These registers are: CK VDD • ANSELx (analog select) Data Register • WPUx (weak pull-up) Data Bus In general, when a peripheral is enabled on a port pin, I/O pin that pin cannot be used as a general purpose output. Read PORTx However, the pin can still be read. To peripherals VSS ANSELx TABLE 12-1: PORT AVAILABILITY PER DEVICE A B C E EXAMPLE 12-1: INITIALIZING PORTA T T T T Device R R R R ; This code example illustrates O O O O P P P P ; initializing the PORTA register. The ; other ports are initialized in the same PIC16(L)F1512 ● ● ● ● ; manner. PIC16(L)F1513 ● ● ● ● BANKSEL PORTA ; The Data Latch (LATx registers) is useful for CLRF PORTA ;Init PORTA read-modify-write operations on the value that the I/O BANKSEL LATA ;Data Latch pins are driving. CLRF LATA ; BANKSEL ANSELA ; A write operation to the LATx register has the same CLRF ANSELA ;digital I/O effect as a write to the corresponding PORTx register. BANKSEL TRISA ; A read of the LATx register reads of the values held in MOVLW B'00111000' ;Set RA<5:3> as inputs the I/O PORT latches, while a read of the PORTx MOVWF TRISA ;and set RA<2:0> as register reads the actual I/O pin value. ;outputs Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure12-1. DS40001624D-page 100  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register12-1. For this device family, the following functions can be moved between different pins. • SS (Slave Select) • CCP2 These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — SSSEL CCP2SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 SSSEL: Pin Selection bit 0 = SS function is on RA5 1 = SS function is on RA0 bit 0 CCP2SEL: Pin Selection bit 0 = CCP2 function is on RC1 1 = CCP2 function is on RB3  2012-2016 Microchip Technology Inc. DS40001624D-page 101

PIC16(L)F1512/3 12.2 PORTA Registers 12.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA Each PORTA pin is multiplexed with other functions. The (Register12-3). Setting a TRISA bit (= 1) will make the pins, their combined functions and their output priorities corresponding PORTA pin an input (i.e., disable the are shown in Table12-2. output driver). Clearing a TRISA bit (= 0) will make the When multiple outputs are enabled, the actual pin corresponding PORTA pin an output (i.e., enables control goes to the peripheral with the highest priority. output driver and puts the contents of the output latch Analog input functions, such as ADC, are not shown in on the selected pin). Example12-1 shows how to the priority lists. These inputs are active when the I/O initialize PORTA. pin is set for Analog mode using the ANSELx registers. Reading the PORTA register (Register12-2) reads the Digital output functions may control the pin when it is in status of the pins, whereas writing to it will write to the Analog mode with the priority shown in Table12-2. PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the TABLE 12-2: PORTA OUTPUT PRIORITY port pins are read, this value is modified and then written to the PORT data latch (LATA). Pin Name Function Priority(1) The TRISA register (Register12-3) controls the RA0 RA0 PORTA pin output drivers, even when they are being RA1 RA1 used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using RA2 RA2 them as analog inputs. I/O pins configured as analog RA3 RA3 input always read ‘0’. RA4 RA4 12.2.1 ANSELA REGISTER RA5 VCAP (PIC16F1512/3 only) The ANSELA register (Register12-5) is used to RA5 configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all RA6 CLKOUT OSC2 digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. RA6 RA7 RA7 The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set Note 1: Priority listed from highest to lowest. will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. DS40001624D-page 102  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 12-2: PORTA: PORTA REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RA<7:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-3: TRISA: PORTA TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISA<7:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output  2012-2016 Microchip Technology Inc. DS40001624D-page 103

PIC16(L)F1512/3 REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 LATA<7:0>: PORTA Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is the return of actual I/O pin values. REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 ANSA5: Analog Select between Analog or Digital Function on pins RA5, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 4 Unimplemented: Read as ‘0’ bit 3-0 ANSA<3:0>: Analog Select between Analog or Digital Function on pins RA<3:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS40001624D-page 104  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 104 APFCON — — — — — — SSSEL CCP2SEL 101 LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 104 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 159 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 103 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 103 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. TABLE 12-4: SUMMARY OF CONFIGURATION WORD WITH PORTA Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — FCMEN IESO CLKOUTEN BOREN<1:0.> — CONFIG1 37 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.  2012-2016 Microchip Technology Inc. DS40001624D-page 105

PIC16(L)F1512/3 12.3 PORTB Registers 12.3.2 PORTB FUNCTIONS AND OUTPUT PRIORITIES PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB Each PORTB pin is multiplexed with other functions. The (Register12-7). Setting a TRISB bit (= 1) will make the pins, their combined functions and their output priorities corresponding PORTB pin an input (i.e., put the are shown in Table12-5. corresponding output driver in a High-Impedance mode). When multiple outputs are enabled, the actual pin Clearing a TRISB bit (= 0) will make the corresponding control goes to the peripheral with the highest priority. PORTB pin an output (i.e., enable the output driver and Analog input and some digital input functions are not put the contents of the output latch on the selected pin). included in the list below. These input functions can Example12-1 shows how to initialize an I/O port. remain active when the pin is configured as an output. Certain digital input functions override other port Reading the PORTB register (Register12-6) reads the functions and are included in Table12-5. status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the TABLE 12-5: PORTB OUTPUT PRIORITY port pins are read, this value is modified and then written to the PORT data latch (LATB). Pin Name Function Priority(1) The TRISB register (Register12-7) controls the PORTB RB0 RB0 pin output drivers, even when they are being used as RB1 RB1 analog inputs. The user should ensure the bits in the RB2 RB2 TRISB register are maintained set when using them as RB3 CCP2 analog inputs. I/O pins configured as analog input always RB3 read ‘0’. RB4 RB4 12.3.1 ANSELB REGISTER RB5 RB5 The ANSELB register (Register12-9) is used to RB6 ICDCLK configure the Input mode of an I/O pin to analog. RB6 Setting the appropriate ANSELB bit high will cause all RB7 ICDDAT digital reads on the pin to be read as ‘0’ and allow RB7 analog functions on the pin to operate correctly. Note 1: Priority listed from highest to lowest. The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELB bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. DS40001624D-page 106  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 12-6: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RB<7:0>: PORTB General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is the return of actual I/O pin values. REGISTER 12-7: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output REGISTER 12-8: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 LATB<7:0>: PORTB Output Latch Value bits(1) Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is the return of actual I/O pin values.  2012-2016 Microchip Technology Inc. DS40001624D-page 107

PIC16(L)F1512/3 REGISTER 12-9: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Function on pins RB<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 12-10: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 108 APFCON — — — — — — SSSEL CCP2SEL 101 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 107 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 159 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 107 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 107 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 108 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. DS40001624D-page 108  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 12.4 PORTC Registers 12.4.2 PORTC FUNCTIONS AND OUTPUT PRIORITIES PORTC is an 8-bit wide bidirectional port. The corresponding data direction register is TRISC Each PORTC pin is multiplexed with other functions. The (Register12-12). Setting a TRISC bit (= 1) will make the pins, their combined functions and their output priorities corresponding PORTC pin an input (i.e., put the are shown in Table12-7. corresponding output driver in a High-Impedance mode). When multiple outputs are enabled, the actual pin Clearing a TRISC bit (= 0) will make the corresponding control goes to the peripheral with the highest priority. PORTC pin an output (i.e., enable the output driver and Analog input and some digital input functions are not put the contents of the output latch on the selected pin). included in the list below. These input functions can Example12-1 shows how to initialize an I/O port. remain active when the pin is configured as an output. Certain digital input functions override other port Reading the PORTC register (Register12-11) reads the functions and are included in Table12-7. status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the TABLE 12-7: PORTC OUTPUT PRIORITY port pins are read, this value is modified and then written to the PORT data latch (LATC). Pin Name Function Priority(1) The TRISC register (Register12-12) controls the RC0 SOSCO PORTC pin output drivers, even when they are being RC0 used as analog inputs. The user should ensure the bits in RC1 SOSCI the TRISC register are maintained set when using them CCP2 as analog inputs. I/O pins configured as analog input RC1 always read ‘0’. RC2 CCP1 RC2 12.4.1 ANSELC REGISTER RC3 SCL The ANSELC register (Register12-14) is used to SCK configure the Input mode of an I/O pin to analog. RC3(2) Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as ‘0’ and allow RC4 SDA analog functions on the pin to operate correctly. RC4(2) RC5 SDO The state of the ANSELC bits has no effect on digital RC5 output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode RC6 CK will be analog. This can cause unexpected behavior TX when executing read-modify-write instructions on the RC6 affected port. RC7 DT RC7 Note: The ANSELC bits default to the Analog mode after Reset. To use any pins as Note 1: Priority listed from highest to lowest. digital general purpose or peripheral 2: RC3 and RC4 read the I2C ST input when inputs, the corresponding ANSEL bits I2C mode is enabled. must be initialized to ‘0’ by user software.  2012-2016 Microchip Technology Inc. DS40001624D-page 109

PIC16(L)F1512/3 REGISTER 12-11: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is the return of actual I/O pin values. REGISTER 12-12: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output REGISTER 12-13: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits(1) Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is the return of actual I/O pin values. DS40001624D-page 110  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 12-14: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 ANSC7 ANSC6 ANSC3 ANSC3 ANSC3 ANSC2 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 ANSC<7:0>: Analog Select between Analog or Digital Function on pins RC<7:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 1-0 Unimplemented: Read as ‘0’ Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 108 APFCON — — — — — — SSSEL CCP2SEL 101 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 107 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 107 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 107 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.  2012-2016 Microchip Technology Inc. DS40001624D-page 111

PIC16(L)F1512/3 12.5 PORTE Registers 12.5.1 PORTE FUNCTIONS AND OUTPUT PRIORITIES PORTE is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a PORTE has no peripheral outputs, so the PORTE TRISE bit (= 1) will make the corresponding PORTE pin output has no priority function. an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The exception is RE3, which is input only and its TRIS bit will always read as ‘1’. Example12-1 shows how to initialize an I/O port. Reading the PORTE register (Register12-15) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATE). RE3 reads ‘0’ when MCLRE = 1. DS40001624D-page 112  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 12-15: PORTE: PORTE REGISTER U-0 U-0 U-0 U-0 R-x/x U-0 U-0 U-0 — — — — RE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 RE<3>: PORTE I/O Value bit (RE3 is read-only) bit 2-0 Unimplemented: Read as ‘0’ REGISTER 12-16: TRISE: PORTE TRI-STATE REGISTER U-0 U-0 U-0 U-0 U-1 U-0 U-0 U-0 — — — — —(1) — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 Unimplemented: Read as ‘1’ bit 2-0 Unimplemented: Read as ‘0’ Note 1: Unimplemented, read as ‘1’.  2012-2016 Microchip Technology Inc. DS40001624D-page 113

PIC16(L)F1512/3 REGISTER 12-17: WPUE: WEAK PULL-UP PORTE REGISTER(1,2) U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0 — — — — WPUE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 WPUE: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 2-0 Unimplemented: Read as ‘0’ Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page A(A)DCON0 — CHS<4:0> GO/DONE ADON 130, 147 CCPxCON — — DCxB<1:0> CCPxM<3:0> 236 PORTE — — — — RE3 — — — 113 TRISE — — — — —(1) — — — 113 WPUE — — — — WPUE3 — — — 114 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Note 1: Unimplemented, read as ‘1’. TABLE 12-10: SUMMARY OF CONFIGURATION WORD WITH PORTE Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 37 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTE. DS40001624D-page 114  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 13.0 INTERRUPT-ON-CHANGE 13.3 Interrupt Flags The PORTB pins can be configured to operate as The IOCBFx bits located in the IOCBF register are Interrupt-On-Change (IOC) pins. An interrupt can be status flags that correspond to the interrupt-on-change generated by detecting a signal that has either a rising pins of PORTB. If an expected edge is detected on an edge or a falling edge. Any individual PORTB pin, or appropriately enabled pin, then the status flag for that pin combination of PORTB pins, can be configured to will be set, and an interrupt will be generated if the IOCIE generate an interrupt. The interrupt-on-change module bit is set. The IOCIF bit of the INTCON register reflects has the following features: the status of all IOCBFx bits. • Interrupt-on-Change enable (Master Switch) 13.4 Clearing Interrupt Flags • Individual pin configuration • Rising and falling edge detection The individual status flags, (IOCBFx bits), can be • Individual pin interrupt flags cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated Figure13-1 is a block diagram of the IOC module. status flag will be set at the end of the sequence, regardless of the value actually being written. 13.1 Enabling the Module In order to ensure that no detected edge is lost while To allow individual PORTB pins to generate an interrupt, clearing flags, only AND operations masking out known the IOCIE bit of the INTCON register must be set. If the changed bits should be performed. The following IOCIE bit is disabled, the edge detection on the pin will sequence is an example of what should be performed. still occur, but an interrupt will not be generated. EXAMPLE 13-1: CLEARING INTERRUPT 13.2 Individual Pin Configuration FLAGS (PORTA EXAMPLE) For each PORTB pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a MOVLW 0xff rising edge, the associated IOCBPx bit of the IOCBP XORWF IOCAF, W register is set. To enable a pin to detect a falling edge, ANDWF IOCAF, F the associated IOCBNx bit of the IOCBN register is set. A pin can be configured to detect rising and falling 13.5 Operation in Sleep edges simultaneously by setting both the IOCBPx bit and the IOCBNx bit of the IOCBP and IOCBN registers, The interrupt-on-change interrupt sequence will wake respectively. the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCBF register will be updated prior to the first instruction executed out of Sleep.  2012-2016 Microchip Technology Inc. DS40001624D-page 115

PIC16(L)F1512/3 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q Q4Q1 CK edge detect R RBx data bus = S to data bus IOCBPx D Q 0 or 1 D Q IOCBFx CK write IOCBFx CK IOCIE R Q2 from all other IOCBFx individual IOC interrupt pin detectors to CPU core Q1 Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q3 Q4 Q4 Q4 Q4 Q4Q1 Q4Q1 Q4Q1 Q4Q1 DS40001624D-page 116  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 13.6 Interrupt-On-Change Registers REGISTER 13-1: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBP<7:0>: Interrupt-on-Change PORTB Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-2: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBN<7:0>: Interrupt-on-Change PORTB Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-3: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-0 IOCBF7:0>: Interrupt-on-Change PORTB Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx=1 and a rising edge was detected on RBx, or when IOCBNx=1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change.  2012-2016 Microchip Technology Inc. DS40001624D-page 117

PIC16(L)F1512/3 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 104 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 IOCBF IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 117 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 117 IOCBP IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 117 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 103 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. DS40001624D-page 118  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 14.0 FIXED VOLTAGE REFERENCE 14.1 Independent Gain Amplifiers (FVR) The output of the FVR supplied to the ADC module is routed through a programmable gain amplifier. The The Fixed Voltage Reference, or FVR, is a stable amplifier can be configured to amplify the reference voltage reference, independent of VDD, with 1.024V, voltage by 1x, 2x or 4x, to produce the three possible 2.048V or 4.096V selectable output levels. The output voltage levels. of the FVR can be configured to supply a reference voltage to the following: The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings • ADC input channel for the reference supplied to the ADC module. Refer- • ADC positive reference ence Section16.0 “Analog-to-Digital Converter • Comparator positive input (ADC) Module” for additional information. The FVR can be enabled by setting the FVREN bit of To minimize current consumption when the FVR is the FVRCON register. disabled, the FVR buffers should be turned off by clearing the Buffer Gain Selection bits. 14.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section25.0 “Electrical Specifications” for the minimum delay requirement. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 x1 FVR BUFFER1 x2 (To ADC Module) x4 1.024V Fixed Reference FVREN + FVRRDY - Any peripheral requiring the Fixed Reference (See Table14-1) TABLE 14-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral Conditions Description HFINTOSC FOSC<2:0> = 100 and INTOSC is active and device is not in Sleep IRCF<3:0> = 000x BOREN<1:0> = 11 BOR always enabled BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled LDO All PIC16F1512/3 devices, when The device runs off of the low-power regulator when in Sleep VREGPM = 1 and not in Sleep mode.  2012-2016 Microchip Technology Inc. DS40001624D-page 119

PIC16(L)F1512/3 14.3 FVR Control Registers REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 FVREN FVRRDY(1) TSEN TSRNG — — ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 0 = Fixed Voltage Reference output is not ready or not enabled 1 = Fixed Voltage Reference output is ready for use bit 5 TSEN: Temperature Indicator Enable bit 0 = Temperature Indicator is disabled 1 = Temperature Indicator is enabled bit 4 TSRNG: Temperature Indicator Range Selection bit 0 = VOUT = VDD - 2VT (Low Range) 1 = VOUT = VDD - 4VT (High Range) bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bits 00 =ADC Fixed Voltage Reference Peripheral output is off 01 =ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 =ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 =ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) Note 1: FVRRDY is always ‘1’ on PIC16F1512/3 only. 2: Fixed Voltage Reference output cannot exceed VDD. TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG — — ADFVR<1:0> 120 Legend: Shaded cells are unused by the Fixed Voltage Reference module. DS40001624D-page 120  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 15.0 TEMPERATURE INDICATOR FIGURE 15-1: TEMPERATURE CIRCUIT MODULE DIAGRAM This family of devices is equipped with a temperature VDD circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating TSEN temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is TSRNG internally connected to the device ADC. The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A one- point calibration allows the circuit to indicate a VOUT ADC temperature closely surrounding that point. A two-point MUX ADC calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, Use and Calibration of the Internal n Temperature Indicator (DS01333) for more details CHS bits regarding the calibration process. (ADCON0 register) 15.1 Circuit Operation Figure15-1 shows a simplified block diagram of the 15.2 Minimum Operating VDD temperature circuit. The proportional voltage output is When the temperature circuit is operated in low range, achieved by measuring the forward voltage drop across the device may be operated at any operating voltage multiple silicon junctions. that is within specifications. Equation15-1 describes the output characteristics of When the temperature circuit is operated in high range, the temperature indicator. the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is EQUATION 15-1: VOUT RANGES correctly biased. Table15-1 shows the recommended minimum VDD vs. High Range: VOUT = VDD - 4VT range setting. Low Range: VOUT = VDD - 2VT TABLE 15-1: RECOMMENDED VDD VS. RANGE The temperature sense circuit is integrated with the Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 Fixed Voltage Reference (FVR) module. See Section14.0 “Fixed Voltage Reference (FVR)” for 3.6V 1.8V more information. 15.3 Temperature Output The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no The output of the circuit is measured using the internal current. Analog-to-Digital Converter. A channel is reserved for The circuit operates in either high or low range. The high the temperature circuit output. Refer to Section16.0 range, selected by setting the TSRNG bit of the “Analog-to-Digital Converter (ADC) Module” for FVRCON register, provides a wider output voltage. This detailed information. provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.  2012-2016 Microchip Technology Inc. DS40001624D-page 121

PIC16(L)F1512/3 15.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200s between sequential conversions of the temperature indicator output. TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG — — ADFVR<1:0> 120 Legend: Shaded cells are unused by the temperature indicator module. DS40001624D-page 122  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 16.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE Note: This section of the ADC chapter discusses legacy operation. If new Capacitive Voltage Divider (CVD) features are needed, refer to Section16.5 “Hardware Capacitive Voltage Divider (CVD) Module” for more information. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure16-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake up the device from Sleep.  2012-2016 Microchip Technology Inc. DS40001624D-page 123

PIC16(L)F1512/3 FIGURE 16-1: ADC BLOCK DIAGRAM VDD ADPREF = 0x FVR ADPREF = 11 VREF+ ADPREF = 10 AN0 00000 AN1 00001 AN2 00010 VREF+/AN3 00011 AN4 00100 ADC Reserved 00101 GO/DONE 10 Reserved 00110 Reserved 00111 0 = Left Justify ADFM AN8 01000 1 = Right Justify AN9 01001 ADON(1) 16 AN10 01010 VSS ADRESxH(3) ADRESxL(4) AN11 01011 AN12 01100 AN13 01101 AN14 01110 AN15 01111 AN16 10000 AN17 10001 AN18 10010 AN19 10011 Reserved 10100 Reserved 11001 VREFH (ADC positive reference) 11010 VREFL (ADC negative reference) 11011 Reserved 11100 Temp Indicator 11101 Reserved 11110 FVR Buffer1 11111 CHS<4:0>(2) Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: See AADCON0 register (Register16-7) for detailed analog channel selection per device. 3: ADRES0H and AADRES0H are the same register in two locations, Bank 1 and Bank 14. See Table3-9. 4: ADRES0L and AADRES0L are the same register in two locations, Bank 1 and Bank 14. See Table3-9. DS40001624D-page 124  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 16.1 ADC Configuration 16.1.3 ADC VOLTAGE REFERENCE When configuring and using the ADC the following The ADPREF bits of the ADCON1 register provides functions must be considered: control of the positive voltage reference. The positive voltage reference can be: • Port configuration • VREF+ pin • Channel selection • VDD • ADC voltage reference selection • FVR (Fixed Voltage Reference) • ADC conversion clock source • Interrupt control See Section14.0 “Fixed Voltage Reference (FVR)” for more details on the fixed voltage reference. • Result formatting 16.1.4 CONVERSION CLOCK 16.1.1 PORT CONFIGURATION The source of the conversion clock is software The ADC can be used to convert both analog and selectable via the ADCS bits of the ADCON1 register. digital signals. When converting analog signals, the I/O There are seven possible clock options: pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to • FOSC/2 Section12.0 “I/O Ports” for more information. • FOSC/4 Note: Analog voltages on any pin that is defined • FOSC/8 as a digital input may cause the input • FOSC/16 buffer to conduct excess current. • FOSC/32 • FOSC/64 16.1.2 CHANNEL SELECTION • FRC (dedicated internal oscillator) There are up to 21 channel selections available: The time to complete one bit conversion is defined as - AN<19:8, 4:0> pins TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure16-2. - VREF+ (ADC positive reference) - VREF- (ADC negative reference) For correct conversion, the appropriate TAD specifica- tion must be met. Refer to the A/D conversion require- - Temperature Indicator ments in Section25.0 “Electrical Specifications” for - FVR (Fixed Voltage Reference) Output more information. Table gives examples of appropriate ADC clock selections. Refer to Section14.0 “Fixed Voltage Reference (FVR)” and Section15.0 “Temperature Indicator Note: Unless using the FRC, any changes in the Module” for more information on these channel system clock frequency will change the selections. ADC clock frequency, which may The CHS bits of the ADCON0 register determine which adversely affect the ADC result. channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section16.6 “Hardware CVD Operation” for more information. TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Clock Source Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s Fosc/8 001 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 1.6 s for VDD. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode.  2012-2016 Microchip Technology Inc. DS40001624D-page 125

PIC16(L)F1512/3 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (CONTINUED) ADC Clock Period (TAD) Device Frequency (FOSC) ADC ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Clock Source Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3) Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.0 s(3) Fosc/64 110 3.2 s 4.0 s 8.0 s(3) 16.0 s(3) 64.0 s(3) FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 1.6 s for VDD. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS40001624D-page 126  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 16.1.5 INTERRUPTS 16.1.6 RESULT FORMATTING The ADC module allows for the ability to generate an The 10-bit A/D conversion result can be supplied in two interrupt upon completion of an Analog-to-Digital formats, left justified or right justified. The ADFM bit of conversion. The ADC Interrupt Flag is the ADIF bit in the ADCON1 register controls the output format. the PIR1 register. The ADC Interrupt Enable is the Figure16-3 shows the two output formats. ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. FIGURE 16-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result  2012-2016 Microchip Technology Inc. DS40001624D-page 127

PIC16(L)F1512/3 16.2 ADC Operation 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This 16.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC To enable the ADC module, the ADON bit of the option. When the FRC clock source is selected, the ADCON0 register must be set to a ‘1’. Setting the ADC waits one additional instruction before starting the GO/DONE bit of the ADCON0 register to a ‘1’ will start conversion. This allows the SLEEP instruction to be the Analog-to-Digital conversion. executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device Note: The GO/DONE bit should not be set in the will wake-up from Sleep when the conversion same instruction that turns on the ADC. completes. If the ADC interrupt is disabled, the ADC Refer to Section16.2.6 “A/D Conver- module is turned off after the conversion completes, sion Procedure”. although the ADON bit remains set. 16.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than FRC, a SLEEP instruction causes the present When the conversion is complete, the ADC module will: conversion to be aborted and the ADC module is • Clear the GO/DONE bit turned off, although the ADON bit remains set. • Set the ADIF Interrupt Flag bit 16.2.5 SPECIAL EVENT TRIGGER • Update the ADRESH and ADRESL registers with new conversion result The Special Event Trigger allows periodic ADC measurements without software intervention, using the 16.2.3 TERMINATING A CONVERSION TRIGSEL bits of the AADCON2 register. When this trigger occurs, the GO/DONE bit is set by hardware If a conversion must be terminated before completion, from one of the following sources: the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with • CCP1 the partially complete Analog-to-Digital conversion • CCP2 sample. Incomplete bits will match the last bit • Timer0 Overflow converted. • Timer1 Overflow Note: A device Reset forces all registers to their • Timer2 Match to PR2 Reset state. Thus, the ADC module is turned off and any pending conversion is TABLE 16-2: SPECIAL EVENT TRIGGER terminated. Device Source PIC16(L)F1512/3 CCP1, CCP2, TMR0, TMR1, TMR2 Using the Special Event Trigger does not assure proper ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met. Refer to Section21.0 “Capture/Compare/PWM Modules”, Section17.0 “Timer0 Module”, Section18.0 “Timer1 Module with Gate Control”, and Section19.0 “Timer2 Module” for more information. DS40001624D-page 128  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 16.2.6 A/D CONVERSION PROCEDURE EXAMPLE 16-1: A/D CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. 1. Configure Port: ; • Disable pin output driver (refer to the TRIS ;Conversion start & polling for completion register) ; are included. • Configure pin as analog (refer to the ANSEL ; register) BANKSEL ADCON1 ; MOVLW B’11110000’ ;Right justify, Frc • Disable weak pull-ups either globally (refer to ;clock the OPTION_REG register) or individually MOVWF ADCON1 ;Vdd and Vss Vref (Refer to the appropriate WPUx register) BANKSEL TRISA ; 2. Configure the ADC module: BSF TRISA,0 ;Set RA0 to input • Select ADC conversion clock BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog • Configure voltage reference BANKSEL WPUA ; • Select ADC input channel BCF WPUA, 0 ;Disable weak • Turn on ADC module pull-up on RA0 BANKSEL ADCON0 ; 3. Configure ADC interrupt (optional): MOVLW B’00000001’ ;Select channel AN0 • Clear ADC interrupt flag MOVWF ADCON0 ;Turn ADC On • Enable ADC interrupt CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion • Enable peripheral interrupt BTFSC ADCON0,ADGO ;Is conversion done? • Enable global interrupt(1) GOTO $-1 ;No, test again 4. Wait the required acquisition time(2). BANKSEL ADRESH ; 5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space 6. Wait for ADC conversion to complete by one of BANKSEL ADRESL ; the following: MOVF ADRESL,W ;Read lower 8 bits • Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result in ADRES0H and ADRES0L. 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section16.4 “A/D Acquisition Requirements”.  2012-2016 Microchip Technology Inc. DS40001624D-page 129

PIC16(L)F1512/3 16.3 ADC Register Definitions The following registers are used to control the operation of the ADC. REGISTER 16-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CHS<4:0> GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(1) 11110 = Reserved. No channel connected. 11101 = Temperature Indicator(2). 11100 = Reserved. No channel connected. 11011 = VREFL (ADC Negative Reference) 11010 = VREFH (ADC Positive Reference)(3) 11001 = Reserved. No channel connected. • • • 10100 = Reserved. No channel connected. 10011 = AN19 10010 = AN18 10001 = AN17 10000 = AN16 01111 = AN15 01110 = AN14 01101 = AN13 01100 = AN12 01011 = AN11 01010 = AN10 01001 = AN9 01000 = AN8 00111 = Reserved. No channel connected. 00110 = Reserved. No channel connected. 00101 = Reserved. No channel connected. 00100 = AN4 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0 bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: See Section14.0 “Fixed Voltage Reference (FVR)” for more information. 2: See Section15.0 “Temperature Indicator Module” for more information. 3: Conversion results for the VREFH selection may contain errors due to noise. DS40001624D-page 130  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> — — ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right-justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded. 0 = Left-justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded. bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from a dedicated RC oscillator) bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits 00 = VREF is connected to VDD 01 = Reserved 10 = VREF is connected to external VREF+ pin(1) 11 = VREF is connected to internal Fixed Voltage Reference (FVR) module(1) Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section25.0 “Electrical Specifications” for details.  2012-2016 Microchip Technology Inc. DS40001624D-page 131

PIC16(L)F1512/3 REGISTER 16-3: ADRES0H: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 16-4: ADRES0L: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<1:0> — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. DS40001624D-page 132  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 16-5: ADRES0H: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 16-6: ADRES0L: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result  2012-2016 Microchip Technology Inc. DS40001624D-page 133

PIC16(L)F1512/3 16.4 A/D Acquisition Requirements source impedance is decreased, the acquisition time may be decreased. After the analog input channel is For the ADC to meet its specified accuracy, the charge selected (or changed), an A/D acquisition must be holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate charge to the input channel voltage level. The Analog the minimum acquisition time, Equation16-1 may be Input model is shown in Figure16-4. The source used. This equation assumes that 1/2 LSb error is used impedance (RS) and the internal sampling switch (RSS) (1,024 steps for the ADC). The 1/2 LSb error is the impedance directly affect the time required to charge maximum error allowed for the ADC to meet its the capacitor CHOLD. The sampling switch (RSS) specified resolution. impedance varies over the device voltage (VDD), refer to Figure16-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 16-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– ------n----+----1------------ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb 2 –1 –TC  ---------- RC VAPPLIED1–e  = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– ------n---+-----1------------ ;combining [1] and [2]   2  –1 Note: Where n = number of bits of the ADC. Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/2047) = –13.5pF1k+7k+10k ln(0.000488) = 1.85µs Therefore: TACQ = 2µs+1.85µs+50°C- 25°C0.05µs/°C 5.1µs Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification. DS40001624D-page 134  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Sampling Input Switch VT  0.6V Rs pin RIC  1k SS Rss VA C5 PpIFN VT  0.6V I LEAKAGE(1) CHOLD = 13.5 pF VSS/VREF- 6V 5V RSS Legend: CHOLD = Sample/Hold Capacitance VDD4V 3V CPIN = Input Capacitance 2V I LEAKAGE = Leakage current at the pin due to various junctions 5 6 7 891011 RIC = Interconnect Resistance Sampling Switch RSS = Resistance of Sampling Switch (k) SS = Sampling Switch VT = Threshold Voltage Note 1: Refer to Section25.0 “Electrical Specifications”. FIGURE 16-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh 3FCh e od 3FBh C ut p ut O C D 03h A 02h 01h 00h Analog Input Voltage 0.5 LSB 1.5 LSB Zero-Scale VREF- Transition Full-Scale Transition VREF+  2012-2016 Microchip Technology Inc. DS40001624D-page 135

PIC16(L)F1512/3 TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — CHS<4:0> GO/DONE ADON 130 ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 131 ADRES0H A/D Result Register High 132, 133 ADRES0L A/D Result Register Low 132, 133 ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 104 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 108 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 111 CCP1CON — — DC1B<1:0> CCP1M<3:0> 236 CCP2CON — — DC2B<1:0> CCP2M<3:0> 236 FVRCON FVREN FVRRDY TSEN TSRNG — — ADFVR<1:0> 120 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 103 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 107 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 110 Legend: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. DS40001624D-page 136  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 16.5 Hardware Capacitive Voltage levels for both the CHOLD and sensor nodes inverted. Divider (CVD) Module Figure16-6 shows the waveform for two inverted CVD measurements, which is also known is differential CVD The hardware Capacitive Voltage Divider (CVD) measurement. module is a peripheral which allows the user to perform In a typical application, an Analog-to-Digital Converter a relative capacitance measurement on any ADC (ADC) channel is attached to a pad on a Printed Circuit channel using the internal ADC sample and hold Board (PCB), which is electrically isolated from the end capacitance as a reference. This relative capacitance user. A capacitive change is detected on the ADC measurement can be used to implement capacitive channel using the CVD conversion method when the touch or proximity sensing applications. end user places a finger over the PCB pad, the The CVD operation begins with the ADC’s internal developer then can implement software to detect a sample and hold capacitor (CHOLD) being disconnected touch or proximity event or change. Key features of this from the path which connects it to the external module include: capacitive sensor node. While disconnected, CHOLD is • Automated double sample conversions pre-charged to VDD or VSS while the path to the sensor • Two result registers node is also discharged to VDD or VSS – typically this node is discharged to the level opposite that of CHOLD. • Inversion of second sample When the pre-charge phase is complete, the VDD/VSS • 7-bit pre-charge timer bias paths for the two nodes are shut off and CHOLD • 7-bit acquisition timer and the path to the external sensor node are • Two guard ring output drives re-connected, at which time the acquisition phase of • Adjustable sample and hold capacitor array the CVD operation begins. During acquisition, a capacitive voltage divider is formed between the pre-charged CHOLD and sensor nodes which results in Note: For more information on capacitive a final voltage level settling on CHOLD which is voltage divider sensing method refer to determined by the capacitances and pre-charge levels the Application Note AN1478, mTouchTM of the two nodes involved. After acquisition, the ADC Sensing Solution Acquisition Methods converts the voltage level held on CHOLD. This process Capacitive Voltage Divider (DS01478). is then usually repeated with the selected pre-charge FIGURE 16-6: DIFFERENTIAL CVD MEASUREMENT WAVEFORM Precharge Acquisition Conversion Precharge Acquisition Conversion V DD e g a Volt citor sor a n p e a S d C ve Hol aciti C p D Ca nternal A External I V SS First Sample Second Sample Time  2012-2016 Microchip Technology Inc. DS40001624D-page 137

PIC16(L)F1512/3 FIGURE 16-7: HARDWARE CAPACITIVE VOLTAGE DIVIDER BLOCK DIAGRAM ADOUT Pad ADOUT ADOEN or ADOLEN VDD ADIPPOL = 1 ANx ADC Conversion Bus ANx Pads ADIPPOL = 0 VGND ADDCAP<2:0> Additional Sample and Hold Cap VGND VGND VGND DS40001624D-page 138  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 16.6 Hardware CVD Operation At the start of the acquisition stage, the port pin logic of the selected analog channel is again overridden to turn Capacitive Voltage Divider is a charge averaging off the digital high/low output drivers so that they do not capacitive sensing method. The hardware CVD module affect the final result of charge averaging. Also, the will automate the process of charging, averaging selected ADC channel is connected to CHOLD. This between the external sensor capacitance and the allows charge averaging to proceed between the internal ADC sample and hold capacitor, and then pre-charged channel and the CHOLD capacitor. It is initiating the ADC conversions. The whole process can noted that the port pin logic override that occurs during be expanded into three stages: pre-charge, acquisition acquisition related to the selected sample channel and conversion. See Figure16-10 for basic information does not occur on the ADOUT pin. See Section16.6.9 on the timing of three stages. “Analog Bus Visibility” for more information. 16.6.1 PRE-CHARGE TIMER 16.6.3 STARTING A CONVERSION The pre-charge stage is an optional 1-127 instruction To enable the ADC module, the ADON bit of the cycle time delay used to put the external ADC channel AADCON0 register must be set. Setting the GO/DONE and the internal sample and hold capacitor (CHOLD) bit of the AADCON0 register or by the Special Event into pre-conditioned states. The pre-charge stage of Trigger inputs will start the Analog-to-Digital conversion. conversion is enabled by writing a non-zero value to Once a conversion begins, it proceeds until complete, the ADPRE<6:0> bits of the AADPRE register. This while the ADON bit is set. If the ADON bit is cleared, the stage is initiated when a conversion sequence is conversion is halted. The GO/DONE bit of the started by either the GO/DONE bit or a Special Event AADCON0 register indicates that a conversion is Trigger. When initiating an ADC conversion, if the occurring, regardless of the starting trigger. ADPRE bits are cleared, this stage is skipped. During the pre-charge time, CHOLD is disconnected Note: The GO/DONE bit should not be set in the from the outer portion of the sample path that leads to same instruction that turns on the ADC. the external capacitive sensor and is connected to Refer to Section Section16.6.10 “Hard- either VDD or VSS, depending on the value of the ware CVD Double Conversion Proce- ADIPPOL bit of the AADCON3 register. At the same dure”. time, the port pin logic of the selected analog channel is overridden to drive a digital high or low out in order to 16.6.4 COMPLETION OF A CONVERSION pre-charge the outer portion of the ADC’s sample path, When the conversion is complete, the ADC module will: which includes the external sensor. The output polarity • Clear the GO/DONE bit of the AADCON0 register. of this override is determined by the ADEPPOL bit of the AADCON3 register. • Set the ADIF Interrupt Flag bit of the PIR1 register. When the ADOOEN bit of the AADCON3 register is set, • Update the AADRESxH and AADRESxL registers the ADOUT pin is overridden during pre-charge. See with new conversion results. Section16.6.9 “Analog Bus Visibility” for more information. This override functions the same as the 16.6.5 TERMINATING A CONVERSION channel pin overrides, but the polarity is selected by the ADIPPOL bit of the AADCON3 register. See If a conversion must be terminated before completion, Figure16-7. clear the GO/DONE bit. The AADRESxH and AADRESxL registers will be updated with the partially 16.6.2 ACQUISITION TIMER complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. The acquisition timer controls the time allowed to acquire the signal to be sampled. The acquisition delay The AADSTAT register can be used to track the status time is from 1 to 127 instruction cycles and is used to of the hardware CVD module during a conversion. allow the voltage on the internal sample and hold Note: A device Reset forces all registers to their capacitor (CHOLD) to settle to a final value through Reset state. Thus, the ADC module is charge averaging. The acquisition time of conversion is turned off and any pending conversion is enabled by writing a non-zero value to the terminated. ADACQ<6:0> bits of the AADACQ register. When the acquisition time is enabled, the time starts immediately following the pre-charge stage. If the ADPRE<6:0> bits of the AADPRE register are set to zero, the acquisition time is initiated by either setting the GO/DONE bit or a Special Event Trigger.  2012-2016 Microchip Technology Inc. DS40001624D-page 139

PIC16(L)F1512/3 16.6.6 DOUBLE SAMPLE CONVERSION 16.6.7 GUARD RING OUTPUTS Double sampling can be enabled by setting the The guard ring outputs consist of a pair of digital ADDSEN bit of the AADCON3 register. When this bit is outputs from the hardware CVD module. This function set, two conversions are completed each time the is enabled by the GRDAOE and GRDBOE bits of the GO/DONE bit is set or a Special Event Trigger occurs. AADGRD register. Polarity of the output is controlled by The GO/DONE bit remains set for the duration of both the GRDPOL bit. conversions and is used to signal the end of the Once enabled and while ADON = 1, the guard ring conversion. outputs are active at all times. The outputs are Without setting the ADIPEN bit, the double conversion initialized at the start of the pre-charge stage to match will have identical charge/discharge on the internal and the polarity of the GRDPOL bit. The guard output external capacitor for these two conversions. Setting signal, ADGRDA, changes polarity at the start of the the ADIPEN bit prior to a double conversion will allow acquisition phase. The value stored by the GRDPOL bit the user to perform a pseudo-differential CVD mea- does not change. When in Double Sampling mode, the surement by subtracting the results from the double ring output levels are inverted during the second conversion. This is highly recommended for noise pre-charge and acquisition phases if ADDSEN = 1 and immunity purposes. ADIPEN = 1. For more information on the timing of the guard ring output, refer to Figures16-9,16-11 The result of the first conversion is written to the and16-12. AADRES0H and AADRES0L registers. The second conversion starts two clock cycles after the first has A typical guard ring circuit is displayed in Figure16-8. completed, while the GO/DONE bit remains set. When CGUARD represents the capacitance of the guard ring the ADIPEN bit of AADCON3 is set, the value used by trace placed on a PCB board. The user selects values the ADC for the ADEPPOL, ADIPPOL, and GRDPOL for RA and RB that will create a voltage profile on bits are inverted. The value stored in those bit locations CGUARD, which will match the selected channel during is unchanged. All other control signals remain acquisition. unchanged from the first conversion. The result of the The purpose of the guard ring is to generate a signal in second conversion is stored in the AADRES1H and phase with the CVD sensing signal to minimize the AADRES1L registers. See Figure16-11 and effects of the parasitic capacitance on sensing Figure16-12 for more information. electrodes. It also can be used as a mutual drive for mutual capacitive sensing. For more information about active guard and mutual drive, see Application Note AN1478, mTouchTM Sensing Solution Acquisition Methods Capacitive Voltage Divider (DS01478). FIGURE 16-8: GUARD RING CIRCUIT ADGRDA RA RB CGUARD ADGRDB DS40001624D-page 140  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 16-9: DIFFERENTIAL CVD WITH GUARD RING OUTPUT WAVEFORM V DD or s n e S e v citi a p a C age ernal Volt Ext Guard Ring Output V SS First Sample Second Sample Time 16.6.8 ADDITIONAL SAMPLE AND HOLD 16.6.9 ANALOG BUS VISIBILITY CAPACITOR The ADOEN bit or the ADOLEN bit of the AADCON3 Additional capacitance can be added in parallel with the register can be used to connect the ADC conversion bus sample and hold capacitor (CHOLD) by setting the (CHOLD) to the ADOUT pin. This connection can be used ADDCAP<2:0> bits of the AADCAP register. This bit to monitor the state and behavior of the internal analog connects a digitally programmable capacitance to the bus and it also can be used to improve the match ADC conversion bus, increasing the effective internal between internal and external capacitance by connecting capacitance of the sample and hold capacitor in the a external capacitor to increase the effective internal ADC module. This is used to improve the match capacitance. The ADOEN bit provides the connection via between internal and external capacitance for a better a standard channel passgate, while the ADOLEN bit sensing performance. The additional capacitance does enables a lower-impedance passgate. not affect analog performance of the ADC because it is The ADOUT pin function can be overridden during the not connected during conversion. See Figure16-6. pre-charge stage of conversion. This override function is controlled by the ADOOEN bit. The polarity of the override is set by the ADIPPOL bit. It should be noted that, outside of the pre-charge phase, no ADOUT override is in effect. Therefore, the user must manage the state of the ADOUT pin via the relevant TRIS bit in order to avoid unintended affects on conversion results. If the user wishes to have the ADOUT path be active during conversions, then the relevant TRIS bit should be set to ensure that the ADOUT pin logic is in the input mode during the acquisition phase of conversions.  2012-2016 Microchip Technology Inc. DS40001624D-page 141

PIC16(L)F1512/3 FIGURE 16-10: HARDWARE CVD SEQUENCE TIMING DIAGRAM Pre-Charge Acquisition/ Conversion Time Time Sharing Time (Traditional Timing of ADC Conversion) 1-127 TINST 1-127 TINST (TPRE) (TACQ) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 External and Internal External and Internal Conversion starts Channels are Channels share charged/discharged charge Holding capacitor CHOLD is disconnected from analog input (typically 100 ns) If ADPRE = 0 If ADACQ = 0 If ADPRE = 0 On the following cycle: If ADACQ = 0 AADRES0H:AADRES0L is loaded, (Traditional Operation Start) ADIF bit is set, GO/DONE bit is cleared Set GO/DONE bit DS40001624D-page 142  2012-2016 Microchip Technology Inc.

 FIGURE 16-11: DOUBLE SAMPLE CONVERSION SEQUENCE (ADDSEN = 1 AND ADIPEN = 0) 2 0 12 Pre-charge Acquisition Pre-charge Acquisition -2 AADPRE<6:0> AADACQ<6:0> AADPRE<6:0> AADACQ<6:0> 0 1 6 M Conversion Clock ic ro ch 1-127 TINST1-127 TINST TAD 2INST1-127 TINST1-127 TINST ip (1) (1) (1) (1) T (2) (3) e c h AADRESxL/H<9:0> 10'h000 10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st 10'h000 10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st n o lo gy TPRE TACQ TCONV First result written TPRE TACQ TCONV Second result written In to AADRES0L/H to AADRES1L/H c . ADGRDA (GRDPOL = 0) ADGRDB Internal CHOLD Charging (ADIPPOL = 1) External Channel Charging (ADEPPOL = 0) External Channel Connected P To Internal CHOLD I C 1 GO/DONE 6 ( L ADIF D ) S4 F 0 00 ADSTAT<2:0> 3'b001 3'b010 3'b011 3'b101 3'b110 3'b111 3'b000 1 1 6 5 2 4 D 1 -p Note 1: When the conversion clock is ADCRC, the pre-charge and acquisition timers are clocked by ADCRC. a 2 g 2: The AADRES0L/H registers are set to zero during this period. e 1 3: The AADRES1L/H registers are set to zero during this period. /3 4 3

D FIGURE 16-12: DOUBLE SAMPLE CONVERSION SEQUENCE (ADDSEN = 1 AND ADIPEN = 1) P S 4 0 I 0 Pre-charge Acquisition Pre-charge Acquisition C 0 1 AADPRE<6:0> AADACQ<6:0> AADPRE<6:0> AADACQ<6:0> 6 2 1 4 D Conversion Clock 6 -p ag ( e 1 1-12(71 )TINST1-127(1 T)INST TAD 2INST1-127(1 T)INST 1-127(1 T)INST L 44 (2) (3) ) F AADRESxL/H<9:0> 10'h000 10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st 10'h000 10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st 1 5 TPRE TACQ TCONV First result written TPRE TACQ TCONV Second result written 1 to AADRES0L/H to AADRES1L/H 2 ADGRDA / (GRDPOL = 0) 3 ADGRDB Internal CHOLD Charging (ADIPPOL = 1) External Channel Charging (ADEPPOL = 0) External Channel Connected To Internal CHOLD  2 0 1 GO/DONE 2 -2 0 1 6 M ADIF ic ro c hip ADSTAT<2:0> 3'b001 3'b010 3'b011 3'b101 3'b110 3'b111 3'b000 T e c h n o Note 1: When the conversion clock is ADCRC, the pre-charge and acquisition timers are clocked by ADCRC. log 2: The AADRES0L/H registers are set to zero during this period. y In 3: The AADRES1L/H registers are set to zero during this period. c .

PIC16(L)F1512/3 16.6.10 HARDWARE CVD DOUBLE EXAMPLE 16-2: HARDWARE CVD CONVERSION PROCEDURE DOUBLE CONVERSION This is an example procedure for using hardware CVD ;This code block configures the ADC to perform a double conversion for differential CVD ;for polling, Vdd and Vss references, Fosc/16 measurement with active guard drive. ;clock and AN0 input. ; 1. Configure Port: ; The Hardware CVD will perform an inverted • Enable pin output driver (Refer to the TRIS ; double conversion, Guard A and B drive are register). ; both enabled. ;Conversion start & polling for completion • Configure pin output low (Refer to the LAT are included. register). ; • Disable weak pull-up (Refer to the WPU BANKSEL TRISA register). BCF TRISA,0 ;Set RA0 to output BANKSEL LATA 2. Configure the ADC module: BCF LATA,0 ;RA0 output low • Select an appropriate ADC conversion clock BANKSEL ANSELA for your oscillator frequency. BCF ANSELA,0 ;Set RA0 to digital BANKSEL WPUA • Configure voltage reference. BCF WPUA,0 ;Disable pull-up on • Select ADC input channel. RA0 • Turn on the ADC module. ; Initialize ADC and Hardware CVD 3. Configure the hardware CVD module: BANKSEL AADCON0 • Configure charge polarity and double MOVLW B'00000001’ ;Select channel AN0 conversion. MOVWF AADCON0 BANKSEL AADCON1 • Configure pre-charge and acquisition timer. MOVLW B'11010000' ;Vdd and Vss Vref • Configure guard ring (optional). MOVWF AADCON1 • Select additional capacitance (optional). BANKSEL AADCON3 4. Configure ADC interrupt (optional): MOVLW B'01000011' ;Double and inverted • Clear ADC interrupt flag MOVWF AADCON3 ;ADOUT disabled • Enable ADC interrupt BANKSEL AADPRE MOVLW .10 • Enable peripheral interrupt MOVWF AADPRE ;Pre-charge Timer • Enable global interrupt(1) BANKSEL AADACQ MOVLW .10 5. Start conversion by setting the GO/DONE bit or MOVWF AADACQ ;Acquisition Timer by enabling the Special Event Trigger in the BANKSEL AADGRD ADDCON2 register. MOVLW B'11000000' ;Guard on A and B 6. Wait for the ADC conversion to complete by one MOVWF AADGRD of the following: BANKSEL AADCAP MOVLW B'00000000' • Polling the GO/DONE bit. MOVWF AADCAP ;No additional • Waiting for the ADC interrupt (interrupts ;Capacitor enabled). BANKSEL ADCON0 BSF ADCON0, GO 7. Read ADC result: BTFSC ADCON0, GO • Conversion 1 result in ADDRES0H and GOTO $-1 ;No, test again ADDRES0L ;RESULTS OF CONVERIONS 1. • Conversion 2 result in ADDRES1H and BANKSEL AADRES0H ; ADDRES1L MOVF AADRES0H,W ;Read upper 2 bits 8. Clear the ADC interrupt flag (required if interrupt MOVWF RESULT0H ;store in GPR space is enabled). MOVF AADRES0L,W ;Read lower 8 bits MOVWF RESULT0L ;Store in GPR space Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep ;RESULTS OF CONVERIONS 2. and resume in-line code execution. BANKSEL AADRES1H ; MOVF AADRES1H,W ;Read upper 2 bits MOVWF RESULT1H ;store in GPR space MOVF AADRES1L,W ;Read lower 8 bits MOVWF RESULT1L ;Store in GPR space  2012-2016 Microchip Technology Inc. DS40001624D-page 145

PIC16(L)F1512/3 16.6.11 HARDWARE CVD REGISTER MAPPING The hardware CVD module is an enhanced expansion of the standard ADC module as stated in Section16.0 “Analog-to-Digital Converter (ADC) Module” and is backward compatible with the other devices in this fam- ily. Control of the standard ADC module uses Bank 1 registers, see Table16-4. This set of registers is mapped into Bank 14 with the control registers for the hardware CVD module. Although this subset of regis- ters has different names, they are identical. Since the registers for the standard ADC are mapped into the Bank 14 address space, any changes to registers in Bank 1 will be reflected in Bank 14 and vice-versa. TABLE 16-4: HARDWARE CVD REGISTER MAPPING [Bank 14 Address] [Bank 1 Address] Hardware CVD ADC [711h] AADCON0(1) [09Dh] ADCON0(1) [712h] AADCON1(1) [09Eh] ADCON1(1) [713h] AADCON2 [714h] AADCON3 [715h] AADSTAT [716h] AADPRE [717h] AADACQ [718h] AADGRD [719h] AADCAP [71Ah] AADRES0L(1) [09Bh] ADRES0L(1) [71Bh] AADRES0H(1) [09Ch] ADRES0H(1) [71Ch] AADRES1L [71Dh] AADRES1H Note 1: Register is mapped in Bank 1 and Bank 14, using different names in each bank. DS40001624D-page 146  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 16.7 Register Definitions: Hardware CVD Control REGISTER 16-7: AADCON0: HARDWARE CVD CONTROL REGISTER 0(1) U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CHS<4:0> GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(2) 11110 = Reserved. No channel connected. 11101 = Temperature Indicator(3). 11100 = Reserved. No channel connected. 11011 = VREFL (ADC Negative Reference) 11010 = VREFH (ADC Positive Reference)(4) 11001 = Reserved. No channel connected. • • • 10100 = Reserved. No channel connected. 10011 = AN19 10010 = AN18 10001 = AN17 10000 = AN16 01111 = AN15 01110 = AN14 01101 = AN13 01100 = AN12 01011 = AN11 01010 = AN10 01001 = AN9 01000 = AN8 00111 = Reserved. No channel connected. 00110 = Reserved. No channel connected. 00101 = Reserved. No channel connected. 00100 = AN4 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0 bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: See Section16.6.11 “Hardware CVD Register Mapping” for more information. 2: See Section14.0 “Fixed Voltage Reference (FVR)” for more information. 3: See Section15.0 “Temperature Indicator Module” for more information. 4: Conversion results for the VREFH selection may contain errors due to noise.  2012-2016 Microchip Technology Inc. DS40001624D-page 147

PIC16(L)F1512/3 REGISTER 16-8: AADCON1: HARDWARE CVD CONTROL REGISTER 1(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> — — ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified. Six Most Significant bits of AADRESxH are set to ‘0’ when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of AADRESxL are set to ‘0’ when the conversion result is loaded. bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits 111 =FRC (clock supplied from a dedicated RC oscillator) 110 =FOSC/64 101 =FOSC/16 100 =FOSC/4 011 =FRC (clock supplied from a dedicated RC oscillator) 010 =FOSC/32 001 =FOSC/8 000 =FOSC/2 bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits 11 = VREF is connected to internal Fixed Voltage Reference (FVR) module(2) 10 = VREF is connected to external VREF+ pin 01 = Reserved 00 = VREF is connected to VDD Note 1: See Section16.6.11 “Hardware CVD Register Mapping” for more information. 2: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section25.0 “Electrical Specifications” for details. DS40001624D-page 148  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 16-9: AADCON2: HARDWARE CVD CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 — TRIGSEL<2:0>(1,2) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 TRIGSEL<2:0>: ADC Special Event Trigger Source Selection bits(1,2) 111 = Reserved. Auto-conversion Trigger disabled. 110 = Reserved. Auto-conversion Trigger disabled. 101 = TMR2 Match to PR2 100 = TMR1 Overflow 011 = TMR0 Overflow 010 = CCP2 001 = CCP1 000 = No Auto Conversion Trigger Selection bits bit 3-0 Unimplemented: Read as ‘0’ Note 1: This is a rising edge sensitive input for all sources. 2: Signal used to set the corresponding interrupt flag.  2012-2016 Microchip Technology Inc. DS40001624D-page 149

PIC16(L)F1512/3 REGISTER 16-10: AADCON3: HARDWARE CVD CONTROL REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ADEPPOL ADIPPOL ADOLEN ADOEN ADOOEN — ADIPEN ADDSEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADEPPOL: External Pre-charge Polarity bit(1) 1 = Selected channel is shorted to VDD during pre-charge time 0 = Selected channel is shorted to VSS during pre-charge time bit 6 ADIPPOL: Internal Pre-charge Polarity bit(1) 1 = CHOLD is shorted to VDD during pre-charge time 0 = CHOLD is shorted to VSS during pre-charge time bit 5 ADOLEN: ADOUT Low-Impedance Output Enable bit 1 = ADOUT pin low-impedance connection to ADC bus 0 = No external connection to ADC bus bit 4 ADOEN: ADOUT Output Enable bit 1 = ADOUT pin is connected to ADC bus (normal passgate) 0 = No external connection to ADC bus bit 3 ADOOEN: ADOUT Override Enable bit 1 = ADOUT pin is overridden during pre-charge with internal polarity value 0 = ADOUT pin is not overridden bit 2 Unimplemented: Read as ‘0’ bit 1 ADIPEN: A/D Invert Polarity Enable bit If ADDSEN = 1: 1 = The output value of the ADEPPOL, ADIPPOL, and GRDPOL bits used by the A/D are inverted for the second conversion 0 = The second A/D conversion proceeds like the first If ADDSEN = 0: This bit has no effect. bit 0 ADDSEN: A/D Double Sample Enable bit 1 = The A/D immediately starts a new conversion after completing a conversion. GO/DONE bit is not automatically clear at end of conversion 0 = A/D operates in the traditional, single conversion mode Note 1: When the ADDSEN= 1 and ADIPEN=1; the polarity of this output is inverted for the second conversion time. The stored bit value does not change. DS40001624D-page 150  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 16-11: AADSTAT: HARDWARE CVD STATUS REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — — ADCONV ADSTG<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 ADCONV: ADC Conversion Status bit 1 = Indicates ADC in Conversion Sequence for AADRES1H:AADRES1L 0 = Indicates ADC in Conversion Sequence for AADRES0H:AADRES0L (Also reads ‘0’ when GO/DONE = 0) bit 1-0 ADSTG<1:0>: ADC Stage Status bit 11 = ADC module is in conversion stage 10 = ADC module is in acquisition stage 01 = ADC module is in pre-charge stage 00 = ADC module is not converting (same as GO/DONE = 0) REGISTER 16-12: AADPRE: HARDWARE CVD PRE-CHARGE CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — ADPRE<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-0 ADPRE<6:0>: Pre-charge Time Select bits(1) 111 1111 = Pre-charge for 127 instruction cycles 111 1110 = Pre-charge for 126 instruction cycles • • • 000 0001 = Pre-charge for 1 instruction cycle (FOSC/4) 000 0000 = ADC pre-charge time is disabled Note 1: When the FRC clock is selected as the conversion clock source, it is also the clock used for the pre-charge and acquisition times.  2012-2016 Microchip Technology Inc. DS40001624D-page 151

PIC16(L)F1512/3 REGISTER 16-13: AADACQ: HARDWARE CVD ACQUISITION TIME CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — ADACQ<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-0 ADACQ<6:0>: Acquisition/Charge Share Time Select bits(1) 111 1111 = Acquisition/charge share for 127 instruction cycles 111 1110 = Acquisition/charge share for 126 instruction cycles • • • 000 0001 = Acquisition/charge share for one instruction cycle (FOSC/4) 000 0000 = ADC Acquisition/charge share time is disabled Note 1: When the FRC clock is selected as the conversion clock source, it is also the clock used for the pre-charge and acquisition times. REGISTER 16-14: AADGRD: HARDWARE CVD GUARD RING CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 U-0 GRDBOE(2) GRDAOE(2) GRDPOL(1,2) — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GRDBOE: Guard Ring B Output Enable bit(2) 1 = ADC guard ring output is enabled to ADGRDB pin. Its corresponding TRISx bit must be clear. 0 = No ADC guard ring function to this pin is enabled bit 6 GRDAOE: Guard Ring A Output Enable bit(2) 1 = ADC Guard Ring Output is enabled to ADGRDA pin. Its corresponding TRISx, x bit must be clear. 0 = No ADC Guard Ring function is enabled bit 5 GRDPOL: Guard Ring Polarity selection bit(1,2) 1 = ADC guard ring outputs start as digital high during pre-charge stage 0 = ADC guard ring outputs start as digital low during pre-charge stage bit 4-0 Unimplemented: Read as ‘0’ Note 1: When the ADDSEN=1 and ADIPEN=1; the polarity of this output is inverted for the second conversion time. The stored bit value does not change. 2: Guard Ring outputs are maintained while ADON=1. The ADGRDA output switches polarity at the start of the acquisition time. DS40001624D-page 152  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 16-15: AADCAP: HARDWARE CVD ADDITIONAL SAMPLE CAPACITOR SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — ADDCAP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ADDCAP: ADC Additional Sample Capacitor Selection bits 111 = Nominal additional sample capacitor of 28 pF 110 = Nominal additional sample capacitor of 24 pF 101 = Nominal additional sample capacitor of 20 pF 100 = Nominal additional sample capacitor of 16 pF 011 = Nominal additional sample capacitor of 12 pF 010 = Nominal additional sample capacitor of 8 pF 001 = Nominal additional sample capacitor of 4 pF 000 = Additional sample capacitor is disabled  2012-2016 Microchip Technology Inc. DS40001624D-page 153

PIC16(L)F1512/3 REGISTER 16-16: AADRESxH: HARDWARE CVD RESULT REGISTER MSB ADFM = 0(1) R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRESx<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 AD<9:2>: Most Significant ADC results Note 1: See Section16.6.11 “Hardware CVD Register Mapping” for more information. REGISTER 16-17: AADRESxL: HARDWARE CVD RESULT REGISTER LSL ADFM = 0(1) R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0 ADRESx<1:0> — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 AD<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. Note 1: See Section16.6.11 “Hardware CVD Register Mapping” for more information. DS40001624D-page 154  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 16-18: AADRESxH: HARDWARE CVD RESULT REGISTER MSB ADFM = 1(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u — — — — — — ADRESx<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 AD<9:8>: Most Significant ADC results Note 1: See Section16.6.11 “Hardware CVD Register Mapping” for more information. REGISTER 16-19: AADRESxL: HARDWARE CVD RESULT REGISTER LSB ADFM = 1(1) R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRESx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 AD<7:0>: ADC Result Register bits Lower two bits of 10-bit conversion result Note 1: See Section16.6.11 “Hardware CVD Register Mapping” for more information.  2012-2016 Microchip Technology Inc. DS40001624D-page 155

PIC16(L)F1512/3 TABLE 16-5: SUMMARY OF REGISTERS ASSOCIATED WITH HARDWARE CVD Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page AADCAP — — — — — ADDCAP<2:0> 152 AADCON0 — CHS<4:0> GO/DONE ADON 147 AADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 148 AADCON2 — TRIGSEL<2:0> — — — — 149 AADCON3 ADEPPOL ADIPPOL ADOLEN ADOEN ADOOEN — ADIPEN ADDSEN 150 AADGRD GRDBOE GRDAOE GRDPOL — — — — — 152 AADPRE — ADPRE<6:0> 151 AADRES0H A/D Result 0 Register High 154, 155 AADRES0L A/D Result 0 Register Low 154, 155 AADSTAT — — — — — ADCONV ADSTG<1:0> 151 AADACQ — ADACQ<6:0> 152 ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 104 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 108 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 111 CCP1CON — — DC1B<1:0> CCP1M<3:0> 236 CCP2CON — — DC2B<1:0> CCP2M<3:0> 236 FVRCON FVREN FVRRDY TSEN TSRNG — — ADFVR<1:0> 120 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 103 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 107 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 110 Legend: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. DS40001624D-page 156  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 17.0 TIMER0 MODULE 17.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment The Timer0 module is an 8-bit timer/counter with the on every rising or falling edge of the T0CKI pin. following features: 8-Bit Counter mode using the T0CKI pin is selected by • 8-bit timer/counter register (TMR0) setting the TMR0CS bit in the OPTION_REG register to • 8-bit prescaler (independent of Watchdog Timer) ‘1’. • Programmable internal or external clock source The rising or falling transition of the incrementing edge • Programmable external clock edge selection for either input source is determined by the TMR0SE bit • Interrupt on overflow in the OPTION_REG register. • TMR0 can be used to gate Timer1 Figure17-1 is a block diagram of the Timer0 module. 17.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 17.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 17-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 Sync 1 2 TCY TMR0 0 TMR0SE TMR0CS 8-bit Set Flag bit TMR0IF on Overflow Prescaler PSA Overflow to Timer1 8 PS<2:0>  2012-2016 Microchip Technology Inc. DS40001624D-page 157

PIC16(L)F1512/3 17.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 mod- ule ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 17.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 17.1.5 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section25.0 “Electrical Specifications”. 17.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS40001624D-page 158  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 17.2 Option and Timer0 Control Register REGISTER 17-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate 000 1 : 2 001 1 : 4 010 1 : 8 011 1 : 16 100 1 : 32 101 1 : 64 110 1 : 128 111 1 : 256 TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 159 TMR0 Timer0 Module Register 157* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 103 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information.  2012-2016 Microchip Technology Inc. DS40001624D-page 159

PIC16(L)F1512/3 18.0 TIMER1 MODULE WITH GATE • Gate Toggle mode CONTROL • Gate Single-pulse mode • Gate Value Status The Timer1 module is a 16-bit timer/counter with the • Gate Event Interrupt following features: Figure18-1 is a block diagram of the Timer1 module. • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 2-bit prescaler • 32 kHz secondary oscillator circuit • Optionally synchronized comparator out • Multiple Timer1 gate (count enable) sources • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with CCP) • Selectable Gate Source Polarity FIGURE 18-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1GSPM T1G 00 From Timer0 01 t1g_in 0 Data Bus Overflow 0 T1GVAL D Q Single Pulse RD FrMomat cThim PeRr22 10 D Q 1 Acq. Control 1 Q1 EN T1GCON Reserved 11 CK Q T1GGO/DONE Interrupt Set TMR1ON R det TMR1GIF T1GPOL T1GTM TMR1GE Set flag bit TMR1ON TMR1IF on Overflow TMR1(2) EN Synchronized TMR1H TMR1L T1CLK 0 clock input Q D 1 TMR1CS<1:0> T1SYNC SOSCO/T1CKI OUT Secondary LFINTOSC 11 Prescaler Synchronize(3) Oscillator 1 1, 2, 4, 8 det SOSCI EN 10 2 0 FOSC T1CKPS<1:0> Internal 01 T1OSCEN Clock IFnOteSrCn/a2l Sleep input FOSC/4 Clock Internal 00 (1) Clock To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. DS40001624D-page 160  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 18.1 Timer1 Operation 18.2 Clock Source Selection The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> and T1OSCEN bits of the T1CON which is accessed through the TMR1H:TMR1L register register are used to select the clock source for Timer1. pair. Writes to TMR1H or TMR1L directly update the Table18-2 displays the clock source selections. counter. 18.2.1 INTERNAL CLOCK SOURCE When used with an internal clock source, the module is a timer and increments on every instruction cycle. When the internal clock source is selected the When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples can be used as either a timer or counter and of FOSC as determined by the Timer1 prescaler. increments on every selected edge of the external When the FOSC internal clock source is selected, the source. Timer1 register value will increment by four counts every Timer1 is enabled by configuring the TMR1ON and instruction clock cycle. Due to this condition, a 2LSB TMR1GE bits in the T1CON and T1GCON registers, error in resolution will occur when reading the Timer1 respectively. Table18-1 displays the Timer1 enable value. To utilize the full resolution of Timer1, an selections. asynchronous input signal must be used to gate the Timer1 clock input. TABLE 18-1: TIMER1 ENABLE The following asynchronous source may be used: SELECTIONS • Asynchronous event on the T1G pin to Timer1 gate Timer1 TMR1ON TMR1GE Operation 18.2.2 EXTERNAL CLOCK SOURCE 0 0 Off When the external clock source is selected, the Timer1 0 1 Off module may work as a timer or a counter. 1 0 Always On When enabled to count, Timer1 is incremented on the 1 1 Count Enabled rising edge of the external clock input T1CKI. This external clock source can be synchronized to the microcontroller system clock and run asynchronously. When used as a timer with a clock oscillator, an external 32.768kHz crystal can be used in conjunction with the secondary oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • Timer1 enabled after POR • Write to TMR1H or TMR1L • Timer1 is disabled • Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON = 1) when T1CKI is low. TABLE 18-2: CLOCK SOURCE SELECTIONS TMR1CS1 TMR1CS0 T1OSCEN Clock Source 1 1 x LFINTOSC 1 0 1 Secondary Oscillator Circuit on SOSCI/SOSCO Pins 1 0 0 External Clocking on T1CKI Pin 0 1 x System Clock (FOSC) 0 0 x Instruction Clock (FOSC/4)  2012-2016 Microchip Technology Inc. DS40001624D-page 161

PIC16(L)F1512/3 18.3 Timer1 Prescaler should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the Timer1 has four prescaler options allowing 1, 2, 4 or 8 timer may overflow between the reads. divisions of the clock input. The T1CKPS bits of the For writes, it is recommended that the user simply stop T1CON register control the prescale counter. The the timer and write the desired values. A write prescale counter is not directly readable or writable; contention may occur by writing to the timer registers, however, the prescaler counter is cleared upon a write to while the register is incrementing. This may produce an TMR1H or TMR1L. unpredictable value in the TMR1H:TMR1L register pair. 18.4 Secondary Oscillator 18.6 Timer1 Gate Timer1 uses the low-power secondary oscillator circuit Timer1 can be configured to count freely or the count on pins SOSCI and SOSCO. The secondary oscillator can be enabled and disabled using Timer1 gate is designed to use an external 32.768kHz crystal. circuitry. This is also referred to as Timer1 Gate Enable. The secondary oscillator circuit is enabled by setting Timer1 gate can also be driven by multiple selectable the T1OSCEN bit of the T1CON register. The oscillator sources. will continue to run during Sleep. Note: The oscillator requires a start-up and 18.6.1 TIMER1 GATE ENABLE stabilization time before use. Thus, The Timer1 Gate Enable mode is enabled by setting T1OSCEN should be set and a suitable the TMR1GE bit of the T1GCON register. The polarity delay observed prior to using Timer1. A of the Timer1 Gate Enable mode is configured using suitable delay similar to the OST delay the T1GPOL bit of the T1GCON register. can be implemented in software by clearing the TMR1IF bit then presetting When Timer1 Gate Enable mode is enabled, Timer1 the TMR1H:TMR1L register pair to will increment on the rising edge of the Timer1 clock FC00h. The TMR1IF flag will be set when source. When Timer1 Gate Enable mode is disabled, 1024 clock cycles have elapsed, thereby no incrementing will occur and Timer1 will hold the indicating that the oscillator is running and current count. See Figure18-3 for timing details. reasonably stable. TABLE 18-3: TIMER1 GATE ENABLE 18.5 Timer1 Operation in SELECTIONS Asynchronous Counter Mode T1CLK T1GPOL T1G Timer1 Operation If control bit T1SYNC of the T1CON register is set, the  0 0 Counts external clock input is not synchronized. The timer  0 1 Holds Count increments asynchronously to the internal phase clocks. If the external clock source is selected then the  1 0 Holds Count timer will continue to run during Sleep and can  1 1 Counts generate an interrupt on overflow, which will wake-up the processor. However, special precautions in 18.6.2 TIMER1 GATE SOURCE software are needed to read/write the timer (see SELECTION Section18.5.1 “Reading and Writing Timer1 in The Timer1 gate source can be selected from one of Asynchronous Counter Mode”). four different sources. Source selection is controlled by Note: When switching from synchronous to the T1GSS bits of the T1GCON register. The polarity asynchronous operation, it is possible to for each available source is also selectable. Polarity skip an increment. When switching from selection is controlled by the T1GPOL bit of the asynchronous to synchronous operation, T1GCON register. it is possible to produce an additional increment. TABLE 18-4: TIMER1 GATE SOURCES T1GSS Timer1 Gate Source 18.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER 00 Timer1 Gate Pin MODE 01 Overflow of Timer0 (TMR0 increments from FFh to 00h) Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid 10 Timer2 match PR2 read (taken care of in hardware). However, the user 11 Reserved DS40001624D-page 162  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 18.6.2.1 T1G Pin Gate Operation 18.6.4 TIMER1 GATE SINGLE-PULSE MODE The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 When Timer1 Gate Single-Pulse mode is enabled, it is gate circuitry. possible to capture a single-pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the 18.6.2.2 Timer0 Overflow Gate Operation T1GSPM bit in the T1GCON register. Next, the When Timer0 increments from FFh to 00h, a T1GGO/DONE bit in the T1GCON register must be set. low-to-high pulse will automatically be generated and The Timer1 will be fully enabled on the next incrementing internally supplied to the Timer1 gate circuitry. edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other 18.6.2.3 Timer2 Match PR2 Operation gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. See When Timer2 increments and matches PR2, a Figure18-5 for timing details. low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. If the Single-Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE 18.6.3 TIMER1 GATE TOGGLE MODE bit should also be cleared. When Timer1 Gate Toggle mode is enabled, it is Enabling the Toggle mode and the Single-Pulse mode possible to measure the full-cycle length of a Timer1 simultaneously will permit both sections to work gate signal, as opposed to the duration of a single level together. This allows the cycle times on the Timer1 gate pulse. source to be measured. See Figure18-6 for timing details. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the 18.6.5 TIMER1 GATE VALUE STATUS signal. See Figure18-4 for timing details. When Timer1 gate value status is utilized, it is possible Timer1 Gate Toggle mode is enabled by setting the to read the most current level of the gate control value. T1GTM bit of the T1GCON register. When the T1GTM The value is stored in the T1GVAL bit in the T1GCON bit is cleared, the flip-flop is cleared and held clear. This register. The T1GVAL bit is valid even when the Timer1 is necessary in order to control which edge is gate is not enabled (TMR1GE bit is cleared). measured. Note: Enabling Toggle mode at the same time 18.6.6 TIMER1 GATE EVENT INTERRUPT as changing the gate polarity may result in When Timer1 gate event interrupt is enabled, it is indeterminate operation. possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared).  2012-2016 Microchip Technology Inc. DS40001624D-page 163

PIC16(L)F1512/3 18.7 Timer1 Interrupt 18.9 CCP Capture/Compare Time Base The Timer1 register pair (TMR1H:TMR1L) increments The CCP modules use the TMR1H:TMR1L register to FFFFh and rolls over to 0000h. When Timer1 rolls pair as the time base when operating in Capture or over, the Timer1 interrupt flag bit of the PIR1 register is Compare mode. set. To enable the interrupt on rollover, you must set In Capture mode, the value in the TMR1H:TMR1L these bits: register pair is copied into the CCPR1H:CCPR1L • TMR1ON bit of the T1CON register register pair on a configured event. • TMR1IE bit of the PIE1 register In Compare mode, an event is triggered when the value • PEIE bit of the INTCON register CCPR1H:CCPR1L register pair matches the value in • GIE bit of the INTCON register the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. For more information, see Section21.0 “Capture/Compare/PWM Modules”. Note: The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before 18.10 CCP Special Event Trigger enabling interrupts. When the CCP is configured to trigger a special event, 18.8 Timer1 Operation During Sleep the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. Timer1 can only operate during Sleep when setup in The CCP module may still be configured to generate a Asynchronous Counter mode. In this mode, an external CCP interrupt. crystal or clock source can be used to increment the In this mode of operation, the CCPR1H:CCPR1L counter. To set up the timer to wake the device: register pair becomes the period register for Timer1. • TMR1ON bit of the T1CON register must be set Timer1 should be synchronized and FOSC/4 should be • TMR1IE bit of the PIE1 register must be set selected as the clock source in order to utilize the • PEIE bit of the INTCON register must be set Special Event Trigger. Asynchronous operation of Tim- • T1SYNC bit of the T1CON register must be set er1 can cause a Special Event Trigger to be missed. • TMR1CS bits of the T1CON register must be In the event that a write to TMR1H or TMR1L coincides configured with a Special Event Trigger from the CCP, the write will • T1OSCEN bit of the T1CON register must be take precedence. configured For more information, see Section16.2.5 “Special The device will wake-up on an overflow and execute Event Trigger”. the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. Timer1 secondary oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 18-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. DS40001624D-page 164  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 18-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 FIGURE 18-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8  2012-2016 Microchip Technology Inc. DS40001624D-page 165

PIC16(L)F1512/3 FIGURE 18-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 Cleared by TMR1GIF Cleared by software Set by hardware on software falling edge of T1GVAL DS40001624D-page 166  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 18-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 Set by hardware on Cleared by TMR1GIF Cleared by software falling edge of T1GVAL software  2012-2016 Microchip Technology Inc. DS40001624D-page 167

PIC16(L)F1512/3 18.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register18-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 18-1: T1CON: TIMER1 CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 =Timer1 clock source is LFINTOSC 10 =Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on SOSCI/SOSCO pins 01 =Timer1 clock source is system clock (FOSC) 00 =Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Secondary oscillator circuit enabled for Timer1 0 = Secondary oscillator circuit disabled for Timer1 bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS<1:0> = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMR1CS<1:0> = 0X This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 0X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop DS40001624D-page 168  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 18.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register18-2, is used to control Timer1 gate. REGISTER 18-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> DONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 gate pin 01 = Timer0 overflow output 10 = Timer2 Match PR2 11 = Reserved  2012-2016 Microchip Technology Inc. DS40001624D-page 169

PIC16(L)F1512/3 TABLE 18-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 108 CCP1CON — — DC1B<1:0> CCP1M<3:0> 236 CCP2CON — — DC2B<1:0> CCP2M<3:0> 236 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count 164* TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count 164* TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 108 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 111 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 168 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 169 DONE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. DS40001624D-page 170  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 19.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP modules See Figure19-1 for a block diagram of Timer2. FIGURE 19-1: TIMER2 BLOCK DIAGRAM Prescaler Reset FOSC/4 TMR2 TMR2 Output 1:1, 1:4, 1:16, 1:64 2 Comparator Postscaler Sets Flagbit TMR2IF EQ 1:1 to 1:16 T2CKPS<1:0> PR2 4 T2OUTPS<3:0>  2012-2016 Microchip Technology Inc. DS40001624D-page 171

PIC16(L)F1512/3 19.1 Timer2 Operation 19.3 Timer2 Output The clock input to the Timer2 modules is the system The unscaled output of TMR2 is available primarily to instruction clock (FOSC/4). the CCP module, where it is used as a time base for operations in PWM mode. TMR2 increments from 00h on each clock edge. Timer2 can be optionally used as the shift clock source A 4-bit counter/prescaler on the clock input allows direct for the MSSP module operating in SPI mode. input, divide-by-4 and divide-by-16 prescale options. Additional information is provided in Section20.0 These options are selected by the prescaler control bits, “Master Synchronous Serial Port (MSSP) Module” T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on 19.4 Timer2 Operation During Sleep each clock cycle. When the two values match, the comparator generates a match signal as the timer Timer2 cannot be operated while the processor is in output. This signal also resets the value of TMR2 to 00h Sleep mode. The contents of the TMR2 and PR2 on the next cycle and drives the output registers will remain unchanged while the processor is counter/postscaler (see Section19.2 “Timer2 in Sleep mode. Interrupt”). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • a write to the TMR2 register • a write to the T2CON register • Power-on Reset (POR) • Brown-out Reset (BOR) • MCLR Reset • Watchdog Timer (WDT) Reset • Stack Overflow Reset • Stack Underflow Reset • RESET Instruction Note: TMR2 is not cleared when T2CON is written. 19.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register. DS40001624D-page 172  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 19.5 Timer2 Control Register REGISTER 19-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits 1111 =1:16 Postscaler 1110 =1:15 Postscaler 1101 =1:14 Postscaler 1100 =1:13 Postscaler 1011 =1:12 Postscaler 1010 =1:11 Postscaler 1001 =1:10 Postscaler 1000 =1:9 Postscaler 0111 =1:8 Postscaler 0110 =1:7 Postscaler 0101 =1:6 Postscaler 0100 =1:5 Postscaler 0011 =1:4 Postscaler 0010 =1:3 Postscaler 0001 =1:2 Postscaler 0000 =1:1 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 11 =Prescaler is 64 10 =Prescaler is 16 01 =Prescaler is 4 00 =Prescaler is 1  2012-2016 Microchip Technology Inc. DS40001624D-page 173

PIC16(L)F1512/3 TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCP1CON — — DC1B<1:0> CCP1M<3:0> 236 CCP2CON — — DC2B<1:0> CCP2M<3:0> 236 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 PR2 Timer2 Module Period Register 171* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 173 TMR2 Holding Register for the 8-bit TMR2 Register 171* Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information. DS40001624D-page 174  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 20.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 20.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) The SPI interface supports the following modes and features: • Master mode • Slave mode • Clock Parity • Slave Select Synchronization (Slave mode only) • Daisy-chain connection of slave devices Figure20-1 is a block diagram of the SPI interface module. FIGURE 20-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPBUF Reg SDI SSPSR Reg SDO bit 0 Shift Clock SS SS Control 2 (CKP, CKE) Enable Clock Select Edge Select SSPM<3:0> 4 ( T M R 2 O u tp u t ) 2 SCK Edge Prescaler TOSC Select 4, 16, 64 Baud Rate Generator TRIS bit (SSPADD)  2012-2016 Microchip Technology Inc. DS40001624D-page 175

PIC16(L)F1512/3 The I2C interface supports the following modes and features: • Master mode • Slave mode • Byte NACKing (Slave mode) • Limited Multi-master support • 7-bit and 10-bit addressing • Start and Stop interrupts • Interrupt masking • Clock stretching • Bus collision detection • General call address matching • Address masking • Address Hold and Data Hold modes • Selectable SDA hold times Figure20-2 is a block diagram of the I2C interface module in Master mode. Figure20-3 is a diagram of the I2C interface module in Slave mode. FIGURE 20-2: MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal data bus [SSPM 3:0] Read Write SSPBUF Baud Rate Generator (SSPADD) SDA Shift SDA in Clock SSPSR ct e Enable (RCEN) MGSeSbnteAarrcatk tbeni ot(,wS SSletoPdpCg ebOitNL,S2b) Clock Cntl arbitrate/BCOL det d off clock source) SCL ceive Clock (Hol e R Start bit detect, Stop bit detect SCL in Write collision detect Set/Reset: S, P, SSPSTAT, WCOL, SSPOV Clock arbitration Reset SEN, PEN (SSPCON2) Bus Collision State counter for Set SSPIF, BCLIF end of XMIT/RCV Address Match detect DS40001624D-page 176  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-3: MSSP BLOCK DIAGRAM (I2C SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT Reg)  2012-2016 Microchip Technology Inc. DS40001624D-page 177

PIC16(L)F1512/3 20.2 SPI Mode Overview During each SPI clock cycle, a full duplex data transmission occurs. This means that while the master The Serial Peripheral Interface (SPI) bus is a device is sending out the MSb from its shift register (on synchronous serial data communication bus that its SDO pin) and the slave device is reading this bit and operates in Full Duplex mode. Devices communicate in saving it as the LSb of its shift register, that the slave a master/slave environment where the master device device is also sending out the MSb from its shift register initiates the communication. A slave device is (on its SDO pin) and the master device is reading this controlled through a Chip Select known as Slave bit and saving it as the LSb of its shift register. Select. After eight bits have been shifted out, the master and The SPI bus specifies four signal connections: slave have exchanged register values. • Serial Clock (SCK) If there is more data to exchange, the shift registers are • Serial Data Out (SDO) loaded with new data and the process repeats itself. • Serial Data In (SDI) Whether the data is meaningful or not (dummy data), • Slave Select (SS) depends on the application software. This leads to Figure20-1 shows the block diagram of the MSSP three scenarios for data transmission: module when operating in SPI Mode. • Master sends useful data and slave sends dummy The SPI bus operates with a single master device and data. one or more slave devices. When multiple slave • Master sends useful data and slave sends useful devices are used, an independent Slave Select data. connection is required from the master device to each • Master sends dummy data and slave sends useful slave device. data. Figure20-4 shows a typical connection between a Transmissions may involve any number of clock master device and multiple slave devices. cycles. When there is no more data to be transmitted, The master selects only one slave at a time. Most slave the master stops sending the clock signal and it devices have tri-state outputs so their output signal deselects the slave. appears disconnected from the bus when they are not Every slave device connected to the bus that has not selected. been selected through its slave select line must Transmissions involve two shift registers, eight bits in disregard the clock and transmission signals and must size, one in the master and one in the slave. With either not transmit out any data of its own. the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure20-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. DS40001624D-page 178  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SCK SCK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS General I/O General I/O SCK SDI SPI Slave SDO #2 SS SCK SDI SPI Slave SDO #3 SS 20.2.1 SPI MODE REGISTERS 20.2.2 SPI MODE OPERATION The MSSP module has five registers for SPI mode When initializing the SPI, several options need to be operation. These are: specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). • MSSP STATUS register (SSPSTAT) These control bits allow the following to be specified: • MSSP Control Register 1 (SSPCON1) • Master mode (SCK is the clock output) • MSSP Control Register 3 (SSPCON3) • Slave mode (SCK is the clock input) • MSSP Data Buffer register (SSPBUF) • Clock Polarity (Idle state of SCK) • MSSP Address register (SSPADD) • Data Input Sample Phase (middle or end of data • MSSP Shift Register (SSPSR) output time) (Not directly accessible) • Clock Edge (output data on rising/falling edge of SSPCON1 and SSPSTAT are the control and STATUS SCK) registers in SPI mode operation. The SSPCON1 • Clock Rate (Master mode only) register is readable and writable. The lower six bits of the SSPSTAT are read-only. The upper two bits of the • Slave Select mode (Slave mode only) SSPSTAT are read/write. To enable the serial port, SSP Enable bit, SSPEN of the In SPI master mode, SSPADD can be loaded with a SSPCON1 register, must be set. To reset or reconfig- value used in the Baud Rate Generator. More ure SPI mode, clear the SSPEN bit, re-initialize the information on the Baud Rate Generator is available in SSPCON registers and then set the SSPEN bit. This Section20.7 “Baud Rate Generator”. configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port SSPSR is the shift register used for shifting data in and function, some must have their data direction bits (in out. SSPBUF provides indirect access to the SSPSR the TRIS register) appropriately programmed as register. SSPBUF is the buffer register to which data follows: bytes are written, and from which data bytes are read. • SDI must have corresponding TRIS bit set In receive operations, SSPSR and SSPBUF together • SDO must have corresponding TRIS bit cleared create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the • SCK (Master mode) must have corresponding SSPIF interrupt is set. TRIS bit cleared • SCK (Slave mode) must have corresponding During transmission, the SSPBUF is not buffered. A TRIS bit set write to SSPBUF will write to both SSPBUF and SSPSR. • SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value.  2012-2016 Microchip Technology Inc. DS40001624D-page 179

PIC16(L)F1512/3 The MSSP consists of a transmit/receive shift register When the application software is expecting to receive (SSPSR) and a buffer register (SSPBUF). The SSPSR valid data, the SSPBUF should be read before the next shifts the data in and out of the device, MSb first. The byte of data to transfer is written to the SSPBUF. The SSPBUF holds the data that was written to the SSPSR Buffer Full bit, BF of the SSPSTAT register, indicates until the received data is ready. Once the eight bits of when SSPBUF has been loaded with the received data data have been received, that byte is moved to the (transmission is complete). When the SSPBUF is read, SSPBUF register. Then, the Buffer Full Detect bit, BF the BF bit is cleared. This data may be irrelevant if the of the SSPSTAT register, and the interrupt flag bit, SPI is only a transmitter. Generally, the MSSP interrupt SSPIF, are set. This double-buffering of the received is used to determine when the transmission/reception data (SSPBUF) allows the next byte to start reception has completed. If the interrupt method is not going to before reading the data that was just received. Any be used, then software polling can be done to ensure write to the SSPBUF register during that a write collision does not occur. transmission/reception of data will be ignored and the The SSPSR is not directly readable or writable and can write collision detect bit WCOL of the SSPCON1 only be accessed by addressing the SSPBUF register. register, will be set. User software must clear the Additionally, the SSPSTAT register indicates the WCOL bit to allow the following write(s) to the SSPBUF various Status conditions. register to complete successfully. FIGURE 20-5: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x = 1010 SDO SDI Serial Input Buffer Serial Input Buffer (BUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK Slave Select General I/O SS Processor 1 (optional) Processor 2 DS40001624D-page 180  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 20.2.3 SPI MASTER MODE The clock polarity is selected by appropriately programming the CKP bit of the SSPCON1 register The master can initiate the data transfer at any time and the CKE bit of the SSPSTAT register. This then, because it controls the SCK line. The master would give waveforms for SPI communication as determines when the slave (Processor 2, Figure20-5) shown in Figure20-6, Figure20-9 and Figure20-10, is to broadcast data by the software protocol. where the MSb is transmitted first. In Master mode, the In Master mode, the data is transmitted/received as SPI clock rate (bit rate) is user programmable to be one soon as the SSPBUF register is written to. If the SPI is of the following: only going to receive, the SDO output could be • FOSC/4 (or TCY) disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the • FOSC/16 (or 4 * TCY) SDI pin at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY) received, it will be loaded into the SSPBUF register as • Timer2 output/2 if a normal received byte (interrupts and Status bits • Fosc/(4 * (SSPADD + 1)) appropriately set). Figure20-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 20-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF  2012-2016 Microchip Technology Inc. DS40001624D-page 181

PIC16(L)F1512/3 20.2.4 SPI SLAVE MODE 20.2.5 SLAVE SELECT SYNCHRONIZATION In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last The Slave Select can also be used to synchronize bit is latched, the SSPIF interrupt flag bit is set. communication. The Slave Select line is held high until the master device is ready to communicate. When the Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a be observed by reading the SCK pin. The Idle state is new transmission is starting. determined by the CKP bit of the SSPCON1 register. If the slave fails to receive the communication properly, While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the the external clock source on the SCK pin. This external Slave Select line returns to a high state. The slave is clock must meet the minimum high and low times as then ready to receive a new transmission when the specified in the electrical specifications. Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will While in Sleep mode, the slave can transmit/receive eventually become out of sync with the master. If the data. The shift register is clocked from the SCK pin slave misses a bit, it will always be one bit off in future input and when a byte is received, the device will transmissions. Use of the Slave Select line allows the generate an interrupt. If enabled, the device will slave and master to align themselves at the beginning wake-up from Sleep. of each transmission. 20.2.4.1 Daisy-Chain Configuration The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled The SPI bus can sometimes be connected in a (SSPCON1<3:0> = 0100). daisy-chain configuration. The first slave output is connected to the second slave input, the second slave When the SS pin is low, transmission and reception are output is connected to the third slave input, and so on. enabled and the SDO pin is driven. The final slave output is connected to the master input. When the SS pin goes high, the SDO pin is no longer Each slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down first group of clock pulses. The whole chain acts as resistors may be desirable depending on the one large communication shift register. The application. daisy-chain feature only requires a single Slave Select line from the master device. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON1<3:0> = Figure20-7 shows the block diagram of a typical 0100), the SPI module will reset if the SS daisy-chain connection when operating in SPI mode. pin is set to VDD. In a daisy-chain configuration, only the most recent 2: When the SPI is used in Slave mode with byte on the bus is required by the slave. Setting the CKE set; the user must enable SS pin BOEN bit of the SSPCON3 register will enable writes control. to the SSPBUF register, even if the previous byte has 3: While operated in SPI Slave mode the not been read. This allows the software to ignore data SMP bit of the SSPSTAT register must that may not apply to it. remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. DS40001624D-page 182  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-7: SPI DAISY-CHAIN CONNECTION SCK SCK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS SCK SDI SPI Slave SDO #2 SS SCK SDI SPI Slave SDO #3 SS FIGURE 20-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Shift register SSPSR and bit count are reset SSPBUF to SSPSR SDO bit 7 bit 6 bit 7 bit 6 bit 0 SDI bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF  2012-2016 Microchip Technology Inc. DS40001624D-page 183

PIC16(L)F1512/3 FIGURE 20-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE=0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active FIGURE 20-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active DS40001624D-page 184  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 20.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmis- In SPI Master mode, module clocks may be operating sion/reception will remain in that state until the device at a different speed than when in Full-Power mode; in wakes. After the device returns to Run mode, the the case of the Sleep mode, all clocks are halted. module will resume transmitting and receiving data. Special care must be taken by the user when the MSSP In SPI Slave mode, the SPI Transmit/Receive Shift clock is much faster than the system clock. register operates asynchronously to the device. This In Slave mode, when MSSP interrupts are enabled, allows the device to be placed in Sleep mode and data after the master completes sending data, an MSSP to be shifted into the SPI Transmit/Receive Shift interrupt will wake the controller from Sleep. register. When all eight bits have been received, the If an exit from Sleep mode is not desired, MSSP MSSP interrupt flag bit will be set and if enabled, will interrupts should be disabled. wake the device. TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 104 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 111 APFCON — — — — — — SSSEL CCP2SEL 101 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 179* SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 224 SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 226 SSPSTAT SMP CKE D/A P S R/W UA BF 224 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 103 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 110 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. * Page provides register information.  2012-2016 Microchip Technology Inc. DS40001624D-page 185

PIC16(L)F1512/3 20.3 I2C MODE OVERVIEW FIGURE 20-11: I2C MASTER/ SLAVE CONNECTION The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master VDD devices initiate the communication. A slave device is controlled through addressing. SCL SCL The I2C bus specifies two signal connections: VDD • Serial Clock (SCL) Master Slave • Serial Data (SDA) SDA SDA Figure20-2 and Figure20-3 show the block diagrams of the MSSP module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal, supply voltage. Pulling the line to ground is considered which holds the SDA line low to indicate to the a logical zero and letting the line float is considered a transmitter that the slave device has received the logical one. transmitted data and is ready to receive more. Figure20-11 shows a typical connection between two The transition of a data bit is always performed while processors configured as master and slave devices. the SCL line is held low. Transitions that occur while the The I2C bus can operate with one or more master SCL line is held high are used to indicate Start and Stop devices and one or more slave devices. bits. There are four potential modes of operation for a given If the master intends to write to the slave, then it device: repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this • Master Transmit mode example, the master device is in Master Transmit mode (master is transmitting data to a slave) and the slave is in Slave Receive mode. • Master Receive mode If the master intends to read from the slave, then it (master is receiving data from a slave) repeatedly receives a byte of data from the slave, and • Slave Transmit mode responds after each byte with an ACK bit. In this (slave is transmitting data to a master) example, the master device is in Master Receive mode • Slave Receive mode and the slave is Slave Transmit mode. (slave is receiving data from the master) On the last byte of data communicated, the master To begin communication, a master device starts out in device may end the transmission by sending a Stop bit. Master Transmit mode. The master device sends out a If the master device is in Receive mode, it sends the Start bit followed by the address byte of the slave it Stop bit in place of the last ACK bit. A Stop bit is intends to communicate with. This is followed by a sin- indicated by a low-to-high transition of the SDA line gle Read/Write bit, which determines whether the mas- while the SCL line is held high. ter intends to transmit to or receive data from the slave In some cases, the master may want to maintain device. control of the bus and re-initiate another transmission. If the requested slave exists on the bus, it will respond If so, the master device may send another Start bit in with an Acknowledge bit, otherwise known as an ACK. place of the Stop bit or last ACK bit when it is in receive The master then continues in either Transmit mode or mode. Receive mode and the slave continues in the The I2C bus specifies three message protocols; complement, either in Receive mode or Transmit mode, respectively. • Single message where a master writes data to a slave. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and • Single message where a master reads data from data bytes are sent out, Most Significant bit (MSb) first. a slave. The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a out as a logical zero when it intends to write data to the combination of writes and reads, to one or more slave. slaves. DS40001624D-page 186  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 When one device is transmitting a logical one, or letting 20.3.2 ARBITRATION the line float, and a second device is transmitting a Each master device must monitor the bus for Start and logical zero, or holding the line low, the first device can Stop bits. If the device detects that the bus is busy, it detect that the line is not a logical one. This detection, cannot begin a new message until the bus returns to an when used on the SCL line, is called clock stretching. Idle state. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on However, two master devices may try to initiate a trans- the SDA line, it is called arbitration. Arbitration ensures mission on or about the same time. When this occurs, that there is only one master device communicating at the process of arbitration begins. Each transmitter any single time. checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to 20.3.1 CLOCK STRETCHING observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. When a slave device has not completed processing data, it can delay the transfer of more data through the For example, if one transmitter holds the SDA line to a process of clock stretching. An addressed slave device logical one (lets it float) and a second transmitter holds may hold the SCL clock line low after receiving or send- it to a logical zero (pulls it low), the result is that the ing a bit, indicating that it is not yet ready to continue. SDA line will be low. The first transmitter then observes The master that is communicating with the slave will that the level of the line is different than expected and attempt to raise the SCL line in order to transfer the concludes that another transmitter is communicating. next bit, but will detect that the clock line has not yet The first transmitter to notice this difference is the one been released. Because the SCL connection is that loses arbitration and must stop driving the SDA open-drain, the slave has the ability to hold that line low line. If this transmitter is also a master device, it also until it is ready to continue communicating. must stop driving the SCL line. It then can monitor the Clock stretching allows receivers that cannot keep up lines for a Stop condition before trying to reissue its with a transmitter to control the flow of incoming data. transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration pro- cess must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.  2012-2016 Microchip Technology Inc. DS40001624D-page 187

PIC16(L)F1512/3 20.4 I2C MODE OPERATION TABLE 20-2: I2C BUS TERMS All MSSP I2C communication is byte-oriented and TERM Description shifted out MSb first. Six SFR registers and two Transmitter The device which shifts data out interrupt flags interface the module with the PIC® onto the bus. microcontroller and user software. Two pins, SDA and Receiver The device which shifts data in SCL, are exercised by the module to communicate from the bus. with other external I2C devices. Master The device that initiates a transfer, generates clock signals and 20.4.1 BYTE FORMAT terminates a transfer. All communication in I2C is done in 9-bit segments. A Slave The device addressed by the byte is sent from a master to a slave or vice-versa, master. followed by an Acknowledge bit sent back. After the Multi-master A bus with more than one device 8th falling edge of the SCL line, the device outputting that can initiate data transfers. data on the SDA changes that pin to an input and Arbitration Procedure to ensure that only one reads in an Acknowledge value on the next clock master at a time controls the bus. pulse. Winning arbitration ensures that The clock signal, SCL, is provided by the master. Data the message is not corrupted. is valid to change while the SCL signal is low, and Synchronization Procedure to synchronize the sampled on the rising edge of the clock. Changes on clocks of two or more devices on the SDA line while the SCL line is high define special the bus. conditions on the bus, explained below. Idle No master is controlling the bus, 20.4.2 DEFINITION OF I2C TERMINOLOGY and both SDA and SCL lines are high. There is language and terminology in the description Active Any time one or more master of I2C communication that have definitions specific to devices are controlling the bus. I2C. That word usage is defined below and may be Addressed Slave device that has received a used in the rest of this document without explanation. This table was adapted from the Philips I2C Slave matching address and is actively being clocked by a master. specification. Matching Address byte that is clocked into a 20.4.3 SDA AND SCL PINS Address slave that matches the value Selection of any I2C mode with the SSPEN bit set, stored in SSPADD. forces the SCL and SDA pins to be open-drain. These Write Request Slave receives a matching pins should be set by the user to inputs by setting the address with R/W bit clear, and is appropriate TRIS bits. ready to clock in data. Read Request Master sends an address byte with Note: Data is tied to output zero when an I2C the R/W bit set, indicating that it mode is enabled. wishes to clock data out of the Slave. This data is the next and all 20.4.4 SDA HOLD TIME following bytes until a Restart or The hold time of the SDA pin is selected by the SDAHT Stop. bit of the SSPCON3 register. Hold time is the time SDA Clock Stretching When a device on the bus hold is held valid after the falling edge of SCL. Setting the SCL low to stall communication. SDAHT bit selects a longer 300ns minimum hold time Bus Collision Any time the SDA line is sampled and may help on buses with large capacitance. low by the module while it is outputting and expected high state. DS40001624D-page 188  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 20.4.5 START CONDITION 20.4.7 RESTART CONDITION The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid. transition of SDA from a high to a low state while SCL A master can issue a Restart if it wishes to hold the line is high. A Start condition is always generated by bus after terminating the current transfer. A Restart the master and signifies the transition of the bus from has the same effect on the slave that a Start would, an Idle to an Active state. Figure20-12 shows wave resetting all slave logic and preparing it to clock in an forms for Start and Stop conditions. address. The master may want to address the same or another slave. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it In 10-bit Addressing Slave mode a Restart is required low. This does not conform to the I2C Specification that for the master to clock data out of the addressed states no bus collision can occur on a Start. slave. Once a slave has been fully addressed, matching both high and low address bytes, the master 20.4.6 STOP CONDITION can issue a Restart and the high address byte with the A Stop condition is a transition of the SDA line from R/W bit set. The slave logic will then hold the clock low-to-high state while the SCL line is high. and prepare to clock out data. After a full match with R/W clear in 10-bit mode, a prior Note: At least one SCL low time must appear match flag is set and maintained. Until a Stop before a Stop is valid, therefore, if the SDA condition, a high address with R/W clear, or high line goes low then high again while the SCL address match fails. line stays high, only the Start condition is detected. 20.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 20-12: I2C START AND STOP CONDITIONS SDA SCL S P Change of Change of Data Allowed Data Allowed Start Stop Condition Condition FIGURE 20-13: I2C RESTART CONDITION Sr Change of Change of Data Allowed Data Allowed Restart Condition  2012-2016 Microchip Technology Inc. DS40001624D-page 189

PIC16(L)F1512/3 20.4.9 ACKNOWLEDGE SEQUENCE 20.5 I2C SLAVE MODE OPERATION The 9th SCL pulse for any transferred byte in I2C is The MSSP Slave mode operates in one of four modes dedicated as an Acknowledge. It allows receiving selected in the SSPM bits of SSPCON1 register. The devices to respond back to the transmitter by pulling modes can be divided into 7-bit and 10-bit Addressing the SDA line low. The transmitter must release control mode. 10-bit Addressing modes operate the same as of the line during this time to shift in the response. The 7-bit with some additional overhead for handling the Acknowledge (ACK) is an active-low signal, pulling the larger addresses. SDA line low indicated to the transmitter that the device has received the transmitted data and is ready Modes with Start and Stop bit interrupts operate the to receive more. same as the other modes with SSPIF additionally getting set upon detection of a Start, Restart, or Stop The result of an ACK is placed in the ACKSTAT bit of condition. the SSPCON2 register. Slave software, when the AHEN and DHEN bits are 20.5.1 SLAVE MODE ADDRESSES set, allow the user to set the ACK value sent back to The SSPADD register (Register20-7) contains the the transmitter. The ACKDT bit of the SSPCON2 Slave mode address. The first byte received after a register is set/cleared to determine the response. Start or Restart condition is compared against the Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the AHEN and DHEN bits of the SSPCON3 register are value is loaded into the SSPBUF register and an clear. interrupt is generated. If the value does not match, the module goes Idle and no indication is given to the There are certain conditions where an ACK will not be software that anything happened. sent by the slave. If the BF bit of the SSPSTAT register or the SSPOV bit of the SSPCON1 register are set The SSP Mask register (Register20-6) affects the when a byte is received. address matching process. See Section20.5.9 “SSP Mask Register” for more information. When the module is addressed, after the 8th falling edge of SCL on the bus, the ACKTIM bit of the 20.5.1.1 I2C Slave 7-bit Addressing Mode SSPCON3 register is set. The ACKTIM bit indicates the Acknowledge time of the active bus. The ACKTIM In 7-bit Addressing mode, the LSb of the received data Status bit is only active when the AHEN bit or DHEN byte is ignored when determining if there is an address bit is enabled. match. 20.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPADD. Even if there is not an address match; SSPIF and UA are set, and SCL is held low until SSPADD is updated to receive a high byte again. When SSPADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communi- cation. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS40001624D-page 190  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 20.5.2 SLAVE RECEPTION 20.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPSTAT register is cleared. Slave device reception with AHEN and DHEN set The received address is loaded into the SSPBUF operate the same as without these options with extra register and Acknowledged. interrupts and clock stretching added after the 8th When the overflow condition exists for a received falling edge of SCL. These additional interrupts allow address, then not Acknowledge is given. An overflow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the condition is defined as either bit BF bit of the SSPSTAT register is set, or bit SSPOV bit of the SSPCON1 hardware. This functionality adds support for PMBus™ register is set. The BOEN bit of the SSPCON3 register that was not present on previous versions of this modifies this operation. For more information see module. Register20-5. This list describes the steps that need to be taken by slave software to use these options for I2C communi- An MSSP interrupt is generated for each transferred cation. Figure20-16 displays a module using both data byte. Flag bit, SSPIF, must be cleared by software. address and data holding. Figure20-17 includes the When the SEN bit of the SSPCON2 register is set, SCL operation with the SEN bit of the SSPCON2 register will be held low (clock stretch) following each received set. byte. The clock must be released by setting the CKP 1. S bit of SSPSTAT is set; SSPIF is set if interrupt bit of the SSPCON1 register, except sometimes in 10-bit mode. See Section20.2.3 “SPI Master Mode” on Start detect is enabled. for more detail. 2. Matching address with R/W bit clear is clocked in. SSPIF is set and CKP cleared after the 8th 20.5.2.1 7-bit Addressing Reception falling edge of SCL. This section describes a standard sequence of events 3. Slave clears the SSPIF. for the MSSP module configured as an I2C Slave in 4. Slave can look at the ACKTIM bit of the SSP- 7-bit Addressing mode. Figure20-14 and Figure20-15 CON3 register to determine if the SSPIF was are used as visual references for this description. after or before the ACK. This is a step by step process of what typically must 5. Slave reads the address value from SSPBUF, be done to accomplish I2C communication. clearing the BF flag. 6. Slave sets ACK value clocked out to the master 1. Start bit detected. by setting ACKDT. 2. S bit of SSPSTAT is set; SSPIF is set if interrupt 7. Slave releases the clock by setting CKP. on Start detect is enabled. 8. SSPIF is set after an ACK, not after a NACK. 3. Matching address with R/W bit clear is received. 9. If SEN=1 the slave hardware will stretch the 4. The slave pulls SDA low sending an ACK to the clock after the ACK. master, and sets SSPIF bit. 10. Slave clears SSPIF. 5. Software clears the SSPIF bit. 6. Software reads received address from SSPBUF Note: SSPIF is still set after the 9th falling edge of clearing the BF flag. SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent 7. If SEN=1; Slave software sets CKP bit to to master is SSPIF not set release the SCL line. 8. The master clocks out a data byte. 11. SSPIF set and CKP cleared after 8th falling 9. Slave drives SDA low sending an ACK to the edge of SCL for a received data byte. master, and sets SSPIF bit. 12. Slave looks at ACKTIM bit of SSPCON3 to 10. Software clears SSPIF. determine the source of the interrupt. 11. Software reads the received byte from SSPBUF 13. Slave reads the received data from SSPBUF clearing BF. clearing BF. 12. Steps 8-12 are repeated for all received bytes 14. Steps 7-14 are the same for each received data from the master. byte. 13. Master sends Stop condition, setting P bit of 15. Communication is ended by either the slave SSPSTAT, and the bus goes Idle. sending an ACK=1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSPSTAT register.  2012-2016 Microchip Technology Inc. DS40001624D-page 191

PIC16(L)F1512/3 FIGURE 20-14: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=0, DHEN=0) s d Bus Master senStop condition 1 P SSPIF set on 9thfalling edge of SCL = K 9 C A D0 8 e Master eceiving Data D4D3D2D1 4567 eared by software SSPOV set becausSSPBUF is still full. ACK is not sent. e to R D5 3 Cl v From Sla D7D6K 12 First byte of data is available in SSPBUF C 9 A D0 8 D1 7 d a Receiving Data D5D4D3D2 3456 Cleared by software SSPBUF is re D6 2 D7 1 K 9 C A 8 A1 7 2 6 A s s dre A3 5 d A ng A4 4 vi ecei A5 3 R A6 2 A7 1 S V F O A L PI P D C S F S S S S B S DS40001624D-page 192  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-15: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) Bus Master sends Stop condition P SSPIF set on 9thfalling edge of SCL SCL is not heldlow becauseACK=1 K C 9 A D0 8 e Receive Data D7D6D5D4D3D2D1 1234567 Cleared by software First byte of data is available in SSPBUF SSPOV set becausSSPBUF is still full. ACK is not sent. CKP is written to ‘’ in software, 1releasing SCL N E S K AC 9 D0 8 ’1 o ‘ Data D2D1 67 KP is set t oftware, Receive D7D6D5D4D3 12345 Clock is held low until C Cleared by software SSPBUF is read CKP is written to ‘’ in s1releasing SCL N E S K C A 9 0 = W R/ 8 A1 7 2 6 A s s dre A3 5 d e A A4 4 v ei ec A5 3 R 6 2 A A7 1 S V P SDA SCL SSPIF BF SSPO CK  2012-2016 Microchip Technology Inc. DS40001624D-page 193

PIC16(L)F1512/3 FIGURE 20-16: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=1) Master sendsStop condition =1 P No interruptafter not ACKfrom Slave CK 9 A are T to Received DataCKD7D6D5D4D3D2D1D0 912345678 Cleared by software a is read from SSPBUF Slave softwsets ACKDnot ACK CKP set by software, SCL is released ACKTIM set by hardwareon 8th falling edge of SCL A at D D0 8 g Receiving Data D6D5D4D3D2D1 234567 SPIF is set on h falling edge of CL, after ACK When DHEN=:1CKP is cleared byhardware on 8th fallinedge of SCL KTIM cleared bydware in 9th ng edge of SCL D7 1 S9tS ACharrisi K 9 ce C n A e Aqu De es SCK s sA Master Releato slave for Receiving Address A7A6A5A4A3A2A1 12345678 If AHEN=:1SSPIF is set Address isread from SSBUF Slave softwareclears ACKDT to ACK the receivedbyte When AHEN=:1CKP is cleared by hardwareand SCL is stretched ACKTIM set by hardwareon 8th falling edge of SCL S M SDA SCL SSPIF BF ACKDT CKP ACKTI S P DS40001624D-page 194  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-17: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN= 1, AHEN=1, DHEN=1) Master sendsStop condition P No interrupt afterif not ACKfrom Slave CKP is not clearedif not ACK K 9 C A D0 8 s d D1 7 enK Receive Data D6D5D4D3D2 23456 SSPBUF can beread any time beforenext byte is loaded Slave snot AC Set by software,release SCL D7 1 K C 9 A D0 8 e K sequence Receive Data D7D6D5D4D3D2D1 1245673 Cleared by software Received data isavailable on SSPBUF When DHEN = ;1on the 8th falling edgeof SCL of a receiveddata byte, CKP is cleared ACKTIM is cleared by hardwaron 9th rising edge of SCL C A ster releasesA to slave for ACK 9 aD MS 8 s R/W = 0 Receiving Address A6A5A4A3A2A1 342567 Received address is loaded into SSPBUF Slave software clearACKDT to ACKthe received byte When AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared KTIM is set by hardware8th falling edge of SCL A7 1 ACon S M TI SDA SCL SSPIF BF ACKDT CKP ACK S P  2012-2016 Microchip Technology Inc. DS40001624D-page 195

PIC16(L)F1512/3 20.5.3 SLAVE TRANSMISSION 20.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set A master device can transmit a read request to a and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list SSPSTAT register is set. The received address is below outlines what software for a slave will need to loaded into the SSPBUF register, and an ACK pulse is do to accomplish a standard transmission. sent by the slave on the ninth bit. Figure20-17 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and and the SCL pin is held low (see Section20.5.6 SCL. “Clock Stretching” for more detail). By stretching the 2. S bit of SSPSTAT is set; SSPIF is set if interrupt clock, the master will be unable to assert another clock on Start detect is enabled. pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by data. the Slave setting SSPIF bit. The transmit data must be loaded into the SSPBUF 4. Slave hardware generates an ACK and sets register which also loads the SSPSR register. Then the SSPIF. SCL pin should be released by setting the CKP bit of 5. SSPIF bit is cleared by user. the SSPCON1 register. The eight data bits are shifted 6. Software reads the received address from SSP- out on the falling edge of the SCL input. This ensures BUF, clearing BF. that the SDA signal is valid during the SCL high time. 7. R/W is set so CKP was automatically cleared The ACK pulse from the master-receiver is latched on after the ACK. the rising edge of the ninth SCL input pulse. This ACK 8. The slave software loads the transmit data into value is copied to the ACKSTAT bit of the SSPCON2 SSPBUF. register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is 9. CKP bit is set releasing SCL, allowing the latched by the slave, the slave goes Idle and waits for master to clock the data out of the slave. another occurrence of the Start bit. If the SDA line was 10. SSPIF is set after the ACK response from the low (ACK), the next transmit data must be loaded into master is loaded into the ACKSTAT register. the SSPBUF register. Again, the SCL pin must be 11. SSPIF bit is cleared. released by setting bit CKP. 12. The slave software checks the ACKSTAT bit to An MSSP interrupt is generated for each data transfer see if the master wants to clock out more data. byte. The SSPIF bit must be cleared by software and Note 1: If the master ACKs the clock will be the SSPSTAT register is used to determine the status stretched. of the byte. The SSPIF bit is set on the falling edge of 2: ACKSTAT is the only bit updated on the the ninth clock pulse. rising edge of SCL (9th) rather than the 20.5.3.1 Slave Mode Bus Collision falling. A slave receives a Read request and begins shifting 13. Steps 9-13 are repeated for each transmitted data out on the SDA line. If a bus collision is detected byte. and the SBCDE bit of the SSPCON3 register is set, the 14. If the master sends a not ACK; the clock is not BCLIF bit of the PIR register is set. Once a bus collision held, but SSPIF is still set. is detected, the slave goes Idle and waits to be 15. The master sends a Restart condition or a Stop. addressed again. User software can use the BCLIF bit 16. The slave is no longer addressed. to handle a slave bus collision. DS40001624D-page 196  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-18: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=0) sn do enditi er scon P stp ao MSt K C 9 A Transmitting Data D7D6D5D4D3D2D1D0 12345678 BF is automatically cleared after 8th fallingedge of SCL CKP is not held for not ACK Masters not ACKis copied to ACKSTAT c ati m o ut A K AC 9 D0 8 1 D 7 a Dat D2 6 Transmitting D7D6D5D4D3 12345 Cleared by software Data to transmit isloaded into SSPBUF Set by software c ati m o ut A 1CK =A 9 W eceiving AddressR/A5A4A3A2A1 345678 Received addressis read from SSPBUF When R/W is setSCL is alwaysheld low after 9th SCLfalling edge R/W is copied from the matching address byte Indicates an address has been received R 6 A 2 7 A 1 S T A SDA SCL SSPIF BF CKP ACKST R/W D/A S P  2012-2016 Microchip Technology Inc. DS40001624D-page 197

PIC16(L)F1512/3 20.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure20-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. Bus starts Idle. 2. Master sends Start condition; the S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCL line the CKP bit is cleared and SSPIF interrupt is generated. 4. Slave software clears SSPIF. 5. Slave software reads ACKTIM bit of SSPCON3 register, and R/W and D/A of the SSPSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSPCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPIF after the ACK if the R/W bit is set. 11. Slave software clears SSPIF. 12. Slave loads value to transmit to the master into SSPBUF setting the BF bit. Note: SSPBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS40001624D-page 198  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-19: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=1) endsdition sn aster op co P MSt K C A 9 0 D 8 Transmitting Data D5D4D3D2D1 34567 F is automatically eared after 8th fallingge of SCL Master’s ACKresponse is copiedto SSPSTAT CKP not cleared after not ACK D6 2 Bcled 7 D 1 c ati m o AutK C A 9 D0 8 1 a D 7 at D 2 ence omaticTransmitting D7D6D5D4D3D 123456 Cleared by software Data to transmit isloaded into SSPBUF Set by software,releases SCL KTIM is cleared9th rising edge of SCL DAequ Aut ACon Ss K Master releases to slave for ACK W=1AC 9 When R/W = ;1CKP is alwayscleared after ACK R/ 8 F U K Receiving Address A7A6A5A4A3A2A1 1234567 Received addressis read from SSPB Slave clearsACKDT to ACaddress When AHEN = ;1CKP is cleared by hardwareafter receiving matchingaddress. ACKTIM is set on 8th fallingedge of SCL S SDA SCL SPIF BF CKDT STAT CKP KTIM R/W D/A S A K C C A A  2012-2016 Microchip Technology Inc. DS40001624D-page 199

PIC16(L)F1512/3 20.5.4 SLAVE MODE 10-BIT ADDRESS 20.5.5 10-BIT ADDRESSING WITH RECEPTION ADDRESS OR DATA HOLD This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or for the MSSP module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only 10-bit Addressing mode. difference is the need to update the SSPADD register using the UA bit. All functionality, specifically when the Figure20-19 is used as a visual reference for this CKP bit is cleared and SCL line is held low are the description. same. Figure20-20 can be used as a reference of a This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set. slave software to accomplish I2C communication. Figure20-21 shows a standard waveform for a slave 1. Bus starts Idle. transmitter in 10-bit Addressing mode. 2. Master sends Start condition; S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Master sends matching high address with R/W bit clear; UA bit of the SSPSTAT register is set. 4. Slave sends ACK and SSPIF is set. 5. Software clears the SSPIF bit. 6. Software reads received address from SSPBUF clearing the BF flag. 7. Slave loads low address into SSPADD, releasing SCL. 8. Master sends matching low address byte to the slave; UA bit is set. Note: Updates to the SSPADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPIF is set. Note: If the low address does not match, SSPIF and UA are still set so that the slave software can set SSPADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPIF. 11. Slave reads the received matching address from SSPBUF clearing BF. 12. Slave loads high address into SSPADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCL pulse; SSPIF is set. 14. If SEN bit of SSPCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPIF. 16. Slave reads the received byte from SSPBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS40001624D-page 200  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-20: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) endsdition er scon P stp ao MSt K C 9 A 0 8 D a D1 7 F at dU D 2 6 aB Receive D6D5D4D3D 2345 SCL is held lowwhile CKP = 0 Data is refrom SSP Set by software,releasing SCLyte D7 1 d b e v K cei Receive Data D6D5D4D3D2D1D0AC 92345678 Cleared by software Receive address isread from SSPBUF When SEN = ;1CKP is cleared after9th falling edge of re D7 1 K C e A 9 ess Byt A1A0 78 PADD Receive Second Addr A6A5A4A3A2 23456 Software updates SSand releases SCL A7 1 K C 9 A ve First Address Byte 0A9A811 345678 Set by hardwareon 9th falling edge If address matchesSSPADD it is loaded into SSPBUF When UA = ;1SCL is held low ei 1 2 c e R 1 1 S SDA SCL SPIF BF UA CKP S  2012-2016 Microchip Technology Inc. DS40001624D-page 201

PIC16(L)F1512/3 FIGURE 20-21: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=0) a Receive Data D7D6D5 12 Received datis read from SSPBUF K C 9 A D0 8 D1 7 s e Receive Data D6D5D4D3D2 23456 eared by software Update of SSPADD,clears UA and releasSCL CKP with software ases SCL D7 1 Cl Set rele A U K C 9 A 0 A 8 Receive Second Address Byte A6A5A4A3A2A1 345672 ed by software SSPBUF can beread anytime beforethe next received byte ate to SSPADD isallowed until 9thng edge of SCL A7 1 Clear Updnot falli A U K C 9 A 0 = W 8 R/ e eive First Address Byte A9A8110 34567 Set by hardwareon 9th falling edge Slave software clearsACKDT to ACKthe received byte If when AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared ACKTIM is set by hardwaron 8th falling edge of SCL ec 1 2 R 1 1 S T M SDA SCL SSPIF BF ACKD UA CKP ACKTI DS40001624D-page 202  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN=0, AHEN=0, DHEN=0) ends dition er scon P MastStop K = 1 ds AC 9 en D0 8 K Master snot ACK Transmitting Data Byte D7D6D5D4D3D2D1 1723456 Data to transmit isloaded into SSPBUF Set by softwarereleases SCL Masters not ACis copied K C A 9 e 8 aster sends estart event Receive First Address Byt A9A811110 1672345Sr Set by hardware Received address isread from SSPBUF High address is loadedback into SSPADD When R/W = ;1CKP is cleared on9th falling edge of SCL R/W is copied from thematching address byte MR K yte AC 9 s B A0 8 ed eiving Second Addres A6A5A4A3A2A1 672345 Cleared by software After SSPADD isupdated, UA is clearand SCL is released c Re A7 1 K = 0 AC 9 W 8 Receiving AddressR/ A9A811110 1672345 Set by hardware SSPBUF loadedwith received address UA indicates SSPADDmust be updated Indicates an addresshas been received S AT T S SDA SCL SPIF BF UA CKP ACK R/W D/A S  2012-2016 Microchip Technology Inc. DS40001624D-page 203

PIC16(L)F1512/3 20.5.6 CLOCK STRETCHING 20.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus holds In 10-bit Addressing mode, when the UA bit is set the the SCL line low effectively pausing communication. clock is always stretched. This is the only time, the The slave may stretch the clock to allow more time to SCL is stretched without CKP being cleared. SCL is handle data or prepare a response for the master released immediately after a write to SSPADD. device. A master device is not concerned with Note: Previous versions of the module did not stretching as anytime it is active on the bus and not stretch the clock if the second address byte transferring data it is stretching. Any stretching done by did not match. a slave is invisible to the master software and handled by the hardware that generates SCL. 20.5.6.3 Byte NACKing The CKP bit of the SSPCON1 register is used to When AHEN bit of SSPCON3 is set; CKP is cleared by control stretching in software. Any time the CKP bit is hardware after the 8th falling edge of SCL for a cleared, the module will wait for the SCL line to go low received matching address byte. When DHEN bit of and then hold it. Setting CKP will release SCL and SSPCON3 is set; CKP is cleared after the 8th falling allow more communication. edge of SCL for received data. 20.5.6.1 Normal Clock Stretching Stretching after the 8th falling edge of SCL allows the Following an ACK if the R/W bit of SSPSTAT is set, a slave to look at the received address or data and read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data. allows the slave time to update SSPBUF with data to 20.5.7 CLOCK SYNCHRONIZATION AND transfer to the master. If the SEN bit of SSPCON2 is THE CKP BIT set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait is set by software and communication resumes. for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low Note 1: The BF bit has no effect on if the clock will until the SCL output is already sampled low. There- be stretched or not. This is different than fore, the CKP bit will not assert the SCL line until an previous versions of the module that external I2C master device has already asserted the would not stretch the clock, clear CKP, if SCL line. The SCL output will remain low until the CKP SSPBUF was read before the 9th falling bit is set and all other devices on the I2C bus have edge of SCL. released SCL. This ensures that a write to the CKP bit 2: Previous versions of the module did not will not violate the minimum high time requirement for stretch the clock for a transmission if SCL (see Figure20-22). SSPBUF was loaded before the 9th falling edge of SCL. It is now always cleared for read requests. FIGURE 20-23: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX ‚ – 1 SCL Master device CKP asserts clock Master device releases clock WR SSPCON1 DS40001624D-page 204  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 20.5.8 GENERAL CALL ADDRESS software can read SSPBUF and respond. SUPPORT Figure20-23 shows a general call reception sequence. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually In 10-bit Address mode, the UA bit will not be set on determines which device will be the slave addressed the reception of the general call address. The slave by the master device. The exception is the general call will prepare to receive the second byte as data, just as address which can address all devices. When this it would in 7-Bit mode. address is used, all devices should, in theory, respond If the AHEN bit of the SSPCON3 register is set, just as with an Acknowledge. with any other address reception, the slave hardware The general call address is a reserved address in the will stretch the clock after the 8th falling edge of SCL. I2C protocol, defined as address 0x00. When the The slave must then set its ACKDT value and release GCEN bit of the SSPCON2 register is set, the slave the clock with communication progressing as it would module will automatically ACK the reception of this normally. address regardless of the value stored in SSPADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave FIGURE 20-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared by software SSPBUF is read GCEN (SSPCON2<7>) ’1’ 20.5.9 SSP MASK REGISTER An SSP Mask (SSPMSK) register (Register20-6) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the reception of the first (high) byte of the address.  2012-2016 Microchip Technology Inc. DS40001624D-page 205

PIC16(L)F1512/3 20.6 I2C MASTER MODE 20.6.1 I2C MASTER MODE OPERATION The master device generates all of the serial clock Master mode is enabled by setting and clearing the pulses and the Start and Stop conditions. A transfer is appropriate SSPM bits in the SSPCON1 register and ended with a Stop condition or with a Repeated Start by setting the SSPEN bit. In Master mode, the SDA and condition. Since the Repeated Start condition is also SCK pins must be configured as inputs. The MSSP the beginning of the next serial transfer, the I2C bus will peripheral hardware will override the output driver TRIS not be released. controls when necessary to drive the pins low. In Master Transmitter mode, serial data is output Master mode of operation is supported by interrupt through SDA, while SCL outputs the serial clock. The generation on the detection of the Start and Stop first byte transmitted contains the slave address of the conditions. The Stop (P) and Start (S) bits are cleared receiving device (7 bits) and the Read/Write (R/W) bit. from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is set, or the bus is Idle. transmitted, an Acknowledge bit is received. Start and In Firmware Controlled Master mode, user code Stop conditions are output to indicate the beginning conducts all I2C bus operations based on Start and and the end of a serial transfer. Stop bit condition detection. Start and Stop condition In Master Receive mode, the first byte transmitted detection is the only active circuitry in this mode. All contains the slave address of the transmitting device other communication is done by the user software (7bits) and the R/W bit. In this case, the R/W bit will be directly manipulating the SDA and SCL lines. logic ‘1’. Thus, the first byte transmitted is a 7-bit slave The following events will cause the SSP Interrupt Flag address followed by a ‘1’ to indicate the receive bit. bit, SSPIF, to be set (SSP interrupt, if enabled): Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. • Start condition detected After each byte is received, an Acknowledge bit is • Stop condition detected transmitted. Start and Stop conditions indicate the • Data transfer byte transmitted/received beginning and end of transmission. • Acknowledge transmitted/received A Baud Rate Generator is used to set the clock • Repeated Start generated frequency output on SCL. See Section20.7 “Baud Note 1: The MSSP module, when configured in Rate Generator” for more detail. I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start con- dition is complete. In this case, the SSP- BUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur 2: Master mode suspends Start/Stop detection when sending the Start/Stop condition by means of the SEN/PEN control bits. The SSPxIF bit is set at the end of the Start/Stop generation when hardware clears the control bit. DS40001624D-page 206  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 20.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure20-25). FIGURE 20-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX ‚ – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload 20.6.3 WCOL STATUS FLAG If the user writes the SSPBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPBUF was attempted while the module was not Idle. Note: Because queuing of events is not allowed, writing to the lower five bits of SSPCON2 is disabled until the Start condition is complete.  2012-2016 Microchip Technology Inc. DS40001624D-page 207

PIC16(L)F1512/3 20.6.4 I2C MASTER MODE START CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSPSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPCON2 register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start. FIGURE 20-26: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPSTAT<3>) At completion of Start bit, SDA = 1, hardware clears SEN bit SCL = 1 and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here SDA 1st bit 2nd bit TBRG SCL S TBRG DS40001624D-page 208  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 20.6.5 I2C MASTER MODE REPEATED SSPCON2 register will be automatically cleared and START CONDITION TIMING the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is A Repeated Start condition occurs when the RSEN bit detected on the SDA and SCL pins, the S bit of the of the SSPCON2 register is programmed high and the SSPSTAT register will be set. The SSPIF bit will not be Master state machine is no longer active. When the set until the Baud Rate Generator has timed out. RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is Note1: If RSEN is programmed while any other loaded and begins counting. The SDA pin is released event is in progress, it will not take effect. (brought high) for one Baud Rate Generator count 2: A bus collision during the Repeated Start (TBRG). When the Baud Rate Generator times out, if condition occurs if: SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud • SDA is sampled low when SCL Rate Generator is reloaded and begins counting. SDA goes from low-to-high. and SCL must be sampled high for one TBRG. This • SCL goes low before SDA is action is then followed by assertion of the SDA pin asserted low. This may indicate (SDA=0) for one TBRG while SCL is high. SCL is that another master is attempting to asserted low. Following this, the RSEN bit of the transmit a data ‘1’. FIGURE 20-27: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPCON2 occurs here At completion of Start bit, SDA = 1, SDA = 1, hardware clears RSEN bit SCL (no change) SCL = 1 and sets SSPIF TBRG TBRG TBRG SDA 1st bit Write to SSPBUF occurs here TBRG SCL Sr TBRG Repeated Start 20.6.6 I2C MASTER MODE on the rising edge of the ninth clock. If the master TRANSMISSION receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth Transmission of a data byte, a 7-bit address or the clock, the SSPIF bit is set and the master clock (Baud other half of a 10-bit address is accomplished by simply Rate Generator) is suspended until the next data byte writing a value to the SSPBUF register. This action will is loaded into the SSPBUF, leaving SCL low and SDA set the Buffer Full flag bit, BF and allow the Baud Rate unchanged (Figure20-27). Generator to begin counting and start the next trans- mission. Each bit of address/data will be shifted out After the write to the SSPBUF, each bit of the address onto the SDA pin after the falling edge of SCL is will be shifted out on the falling edge of SCL until all asserted. SCL is held low for one Baud Rate Generator seven address bits and the R/W bit are completed. On rollover count (TBRG). Data should be valid before SCL the falling edge of the eighth clock, the master will is released high. When the SCL pin is released high, it release the SDA pin, allowing the slave to respond with is held that way for TBRG. The data on the SDA pin an Acknowledge. On the falling edge of the ninth clock, must remain stable for that duration and some hold the master will sample the SDA pin to see if the address time after the next falling edge of SCL. After the eighth was recognized by a slave. The status of the ACK bit is bit is shifted out (the falling edge of the eighth clock), loaded into the ACKSTAT Status bit of the SSPCON2 the BF flag is cleared and the master releases SDA. register. Following the falling edge of the ninth clock This allows the slave device being addressed to transmission of the address, the SSPIF is set, the BF respond with an ACK bit during the ninth bit time if an flag is cleared and the Baud Rate Generator is turned address match occurred, or if data was received prop- off until another write to the SSPBUF takes place, erly. The status of ACK is written into the ACKSTAT bit holding SCL low and allowing SDA to float.  2012-2016 Microchip Technology Inc. DS40001624D-page 209

PIC16(L)F1512/3 20.6.6.1 BF Status Flag In Transmit mode, the BF bit of the SSPSTAT register is set when the CPU writes to SSPBUF and is cleared when all eight bits are shifted out. 20.6.6.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. 20.6.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPCON2 register is cleared when the slave has sent an Acknowledge (ACK=0) and is set when the slave does not Acknowledge (ACK=1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 20.6.6.4 Typical Transmit Sequence: 1. The user generates a Start condition by setting the SEN bit of the SSPCON2 register. 2. SSPIF is set by hardware on completion of the Start. 3. SSPIF is cleared by software. 4. The MSSP module will wait the required start time before any other operation takes place. 5. The user loads the SSPBUF with the slave address to transmit. 6. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPBUF is written to. 7. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. 8. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 9. The user loads the SSPBUF with eight bits of data. 10. Data is shifted out the SDA pin until all eight bits are transmitted. 11. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. 12. Steps 8-11 are repeated for all transmitted data bytes. 13. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPCON2 register. Interrupt is generated once the Stop/Restart condition is complete. DS40001624D-page 210  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-28: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) ACKSTAT in SSPCON2 = 1 P ared by software K e C 9 Cl A > <6 D0 8 e 2 n slave, clear ACKSTAT bit SSPCON Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared by software service routifrom SSP interrupt SSPBUF is written by software From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to CK re R/W = 0 A1A ss and R/W 789 d by hardware ave A2 ddre 6 eare PCON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPBUF written with 7-bit astart transmit 12345 Cleared by software SSPBUF written After Start condition, SEN cl Sn Write SStart co S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W  2012-2016 Microchip Technology Inc. DS40001624D-page 211

PIC16(L)F1512/3 20.6.7 I2C MASTER MODE RECEPTION 20.6.7.4 Typical Receive Sequence: Master mode reception is enabled by programming the 1. The user generates a Start condition by setting Receive Enable bit, RCEN bit of the SSPCON2 the SEN bit of the SSPCON2 register. register. 2. SSPIF is set by hardware on completion of the Start. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the 3. SSPIF is cleared by software. RCEN bit will be disregarded. 4. User writes SSPBUF with the slave address to transmit and the R/W bit set. The Baud Rate Generator begins counting and on each 5. Address is shifted out the SDA pin until all eight rollover, the state of the SCL pin changes bits are transmitted. Transmission begins as (high-to-low/low-to-high) and data is shifted into the soon as SSPBUF is written to. SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the 6. The MSSP module shifts in the ACK bit from the contents of the SSPSR are loaded into the SSPBUF, slave device and writes its value into the the BF flag bit is set, the SSPIF flag bit is set and the ACKSTAT bit of the SSPCON2 register. Baud Rate Generator is suspended from counting, 7. The MSSP module generates an interrupt at the holding SCL low. The MSSP is now in Idle state end of the ninth clock cycle by setting the SSPIF awaiting the next command. When the buffer is read by bit. the CPU, the BF flag bit is automatically cleared. The 8. User sets the RCEN bit of the SSPCON2 register user can then send an Acknowledge bit at the end of and the master clocks in a byte from the slave. reception by setting the Acknowledge Sequence 9. After the 8th falling edge of SCL, SSPIF and BF Enable, ACKEN bit of the SSPCON2 register. are set. 20.6.7.1 BF Status Flag 10. Master clears SSPIF and reads the received byte from SSPUF, clears BF. In receive operation, the BF bit is set when an address 11. Master sets ACK value sent to slave in ACKDT or data byte is loaded into SSPBUF from SSPSR. It is bit of the SSPCON2 register and initiates the cleared when the SSPBUF register is read. ACK by setting the ACKEN bit. 20.6.7.2 SSPOV Status Flag 12. Masters ACK is clocked out to the slave and SSPIF is set. In receive operation, the SSPOV bit is set when eight 13. User clears SSPIF. bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 14. Steps 8-13 are repeated for each received byte from the slave. 20.6.7.3 WCOL Status Flag 15. Master sends a not ACK or Stop to end If the user writes the SSPBUF when a receive is communication. already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). DS40001624D-page 212  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-29: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from MasterMaster configured as a receiverSDA = ACKDT = SDA = ACKDT = 10by programming SSPCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten hereom Slavenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1ACKD0WACK Bus masterACK is not sentterminatestransfer9967895876512343124PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared by softwareCleared by softwareCleared by software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Master configured as a receiverRCEN clearedACK from MasterRCEN clearedSDA = ACKDT = automatically0by programming SSPCON2<3> (RCEN = )automatically1 K fr R/ 8 AC A1 7 Write to SSPCON2<0>(SEN = ),1begin Start condition SEN = 0Write to SSPBUF occurs here,start XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 631245SCLS SSPIF Cleared by softwareSDA = , SCL = 01while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN RCEN  2012-2016 Microchip Technology Inc. DS40001624D-page 213

PIC16(L)F1512/3 20.6.8 ACKNOWLEDGE SEQUENCE 20.6.9 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPCON2 register. At the end of a SSPCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDA pin. If the user wishes to the master will assert the SDA line low. When the SDA generate an Acknowledge, then the ACKDT bit should line is sampled low, the Baud Rate Generator is be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate before starting an Acknowledge sequence. The Baud Generator times out, the SCL pin will be brought high Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count) (TBRG) and the SCL pin is deasserted (pulled high). later, the SDA pin will be deasserted. When the SDA When the SCL pin is sampled high (clock arbitration), pin is sampled high while SCL is high, the P bit of the the Baud Rate Generator counts for TBRG. The SCL pin SSPSTAT register is set. A TBRG later, the PEN bit is is then pulled low. Following this, the ACKEN bit is cleared and the SSPIF bit is set (Figure20-30). automatically cleared, the Baud Rate Generator is 20.6.9.1 WCOL Status Flag turned off and the MSSP module then goes into Idle mode (Figure20-29). If the user writes the SSPBUF when a Stop sequence is in progress, then the WCOL bit is set and the 20.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does If the user writes the SSPBUF when an Acknowledge not occur). sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 20-30: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in SSPIF set at Cleared in software the end of receive software SSPIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. DS40001624D-page 214  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 20-31: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 20.6.10 SLEEP OPERATION 20.6.13 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C slave module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 20.6.11 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, 20.6.12 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure20-31). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit of the SSPSTAT register is set, SSPBUF can be written to. When the user services the or the bus is Idle, with both the S and P bits clear. When bus collision Interrupt Service Routine and if the I2C the bus is busy, enabling the SSP interrupt will gener- bus is free, the user can resume communication by ate the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge monitored for arbitration to see if the signal level is the condition was in progress when the bus collision expected output level. This check is performed by occurred, the condition is aborted, the SDA and SCL hardware with the result placed in the BCLIF bit. lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user The states where arbitration can be lost are: services the bus collision Interrupt Service Routine and • Address Transfer if the I2C bus is free, the user can resume • Data Transfer communication by asserting a Start condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared.  2012-2016 Microchip Technology Inc. DS40001624D-page 215

PIC16(L)F1512/3 FIGURE 20-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data does not match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF DS40001624D-page 216  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 20.6.13.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure20-34). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure20-32). counts down to zero; if the SCL pin is sampled as ‘0’ b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the (Figure20-33). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a pins are monitored. factor during a Start condition is that no two bus masters can assert a Start If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: condition at the exact same time. Therefore, one master will always assert • the Start condition is aborted, SDA before the other. This condition does • the BCLIF flag is set and not cause a bus collision because the two • the MSSP module is reset to its Idle state masters must be allowed to arbitrate the (Figure20-32). first address following the Start condition. The Start condition begins with the SDA and SCL pins If the address is the same, arbitration deasserted. When the SDA pin is sampled high, the must be allowed to continue into the data Baud Rate Generator is loaded and counts down. If the portion, Repeated Start or Stop SCL pin is sampled low while SDA is high, a bus conditions. collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 20-33: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared by software S SSPIF SSPIF and BCLIF are cleared by software  2012-2016 Microchip Technology Inc. DS40001624D-page 217

PIC16(L)F1512/3 FIGURE 20-34: BUS COLLISION DURING START CONDITION (SCL=0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared by software S ’0’ ’0’ SSPIF ’0’ ’0’ FIGURE 20-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCLIF ’0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF by software DS40001624D-page 218  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 20.6.13.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure20-35). If SDA is sampled high, the BRG is reloaded and begins During a Repeated Start condition, a bus collision counting. If SDA goes from high-to-low before the BRG occurs if: times out, no bus collision occurs because no two a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time. from low level to high level. If SCL goes from high-to-low before the BRG times out b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision indicating that another master is attempting to occurs. In this case, another master is attempting to transmit a data ‘1’. transmit a data ‘1’ during the Repeated Start condition, When the user releases SDA and the pin is allowed to see Figure20-36. float high, the BRG is loaded with SSPADD and counts If, at the end of the BRG time-out, both SCL and SDA down to zero. The SCL pin is then deasserted and are still high, the SDA pin is driven low and the BRG is when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 20-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared by software S ’0’ SSPIF ’0’ FIGURE 20-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared by software RSEN ’0’ S SSPIF  2012-2016 Microchip Technology Inc. DS40001624D-page 219

PIC16(L)F1512/3 20.6.13.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD and a) After the SDA pin has been deasserted and counts down to zero. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure20-37). If the SCL pin is sampled low before SDA goes high. low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure20-38). FIGURE 20-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ’0’ SSPIF ’0’ FIGURE 20-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ’0’ SSPIF ’0’ DS40001624D-page 220  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIE2 OSFIE — — — BCLIE — — CCP2IE 71 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 PIR2 OSFIF — — — BCLIF — — CCP2IF 73 SSPADD ADD<7:0> 227 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 179* SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 224 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 225 SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 226 SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 227 SSPSTAT SMP CKE D/A P S R/W UA BF 223 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 103 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode. * Page provides register information.  2012-2016 Microchip Technology Inc. DS40001624D-page 221

PIC16(L)F1512/3 20.7 BAUD RATE GENERATOR An internal signal “Reload” in Figure20-39 triggers the value from SSPADD to be loaded into the BRG counter. The MSSP module has a Baud Rate Generator This occurs twice for each oscillation of the module available for clock generation in both I2C and SPI clock line. The logic dictating when the reload signal is Master modes. The Baud Rate Generator (BRG) asserted depends on the mode the MSSP is being reload value is placed in the SSPADD register operated in. (Register20-7). When a write occurs to SSPBUF, the Table20-1 demonstrates clock rates based on Baud Rate Generator will automatically begin counting instruction cycles and the BRG value loaded into down. SSPADD. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will EQUATION 20-1: BRG CLOCK FREQUENCY remain in its last state. FOSC FCLOCK = ---------------------------------------------- SSPADD+14 FIGURE 20-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPADD<7:0> SSPM<3:0> Reload Reload SCL Control SSPCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 20-1: MSSP CLOCK RATE W/BRG FCLOCK FOSC FCY BRG Value (2 Rollovers of BRG) 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. DS40001624D-page 222  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 20.8 MSSP Control Registers REGISTER 20-2: SSPSTAT: SSP STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I 2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I 2 C mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I 2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty  2012-2016 Microchip Technology Inc. DS40001624D-page 223

PIC16(L)F1512/3 REGISTER 20-3: SSPCON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register (must be cleared in software). 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I 2 C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C Master mode: Unused in this mode bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5) 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: When enabled, the SDA and SCL pins must be configured as inputs. 4: SSPADD values of 0, 1 or 2 are not supported for I2C mode. 5: SSPADD value of ‘0’ is not supported. Use SSPM = 0000 instead. DS40001624D-page 224  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 20-4: SSPCON2: SSP CONTROL REGISTER 2(1) R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKMSSP Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).  2012-2016 Microchip Technology Inc. DS40001624D-page 225

PIC16(L)F1512/3 REGISTER 20-5: SSPCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the SSPCON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPBUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF bit of the PIR2 register is set, and bus goes Idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSPCON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSPCON1 register and SCL is held low. 0 = Data holding is disabled Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF=1, but hardware continues to write the most recent byte to SSPBUF. 2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. 3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. DS40001624D-page 226  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 20-6: SSPMSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address: The bit is ignored. REGISTER 20-7: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit pat- tern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode — Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.  2012-2016 Microchip Technology Inc. DS40001624D-page 227

PIC16(L)F1512/3 21.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains two standard Capture/ Compare/PWM modules (CCP1 and CCP2). The Capture and Compare functions are identical for all CCP modules. Note1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required. DS40001624D-page 228  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 21.1 Capture Mode 21.1.2 TIMER1 MODE RESOURCE The Capture mode function described in this section is Timer1 must be running in Timer mode or Synchronized available and identical for all CCP modules. Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture Capture mode makes use of the 16-bit Timer1 operation may not work. resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and See Section18.0 “Timer1 Module with Gate stores the 16-bit value of the TMR1H:TMR1L register Control” for more information on configuring Timer1. pair, respectively. An event is defined as one of the 21.1.3 SOFTWARE INTERRUPT MODE following and is configured by the CCPxM<3:0> bits of the CCPxCON register: When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the • Every falling edge CCPxIE interrupt enable bit of the PIEx register clear to • Every rising edge avoid false interrupts. Additionally, the user should • Every 4th rising edge clear the CCPxIF interrupt flag bit of the PIRx register • Every 16th rising edge following any change in Operating mode. When a capture is made, the Interrupt Request Flag bit 21.1.4 CCP PRESCALER CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs There are four prescaler settings specified by the before the value in the CCPRxH, CCPRxL register pair CCPxM<3:0> bits of the CCPxCON register. Whenever is read, the old captured value is overwritten by the new the CCP module is turned off, or the CCP module is not captured value. in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Figure21-1 shows a simplified diagram of the Capture operation. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To 21.1.1 CCP PIN CONFIGURATION avoid this unexpected operation, turn the module off by In Capture mode, the CCPx pin should be configured clearing the CCPxCON register before changing the as an input by setting the associated TRIS control bit. prescaler. Equation21-1 demonstrates the code to perform this function. Also, the CCP2 pin function can be moved to alternative pins using the APFCON register. Refer to EXAMPLE 21-1: CHANGING BETWEEN SectionRegister 12-1: “APFCON: Alternate Pin CAPTURE PRESCALERS Function Control Register” for more details. BANKSELCCPxCON ;Set Bank bits to point Note: If the CCPx pin is configured as an output, ;to CCPxCON a write to the port can cause a capture CLRF CCPxCON ;Turn CCP module off condition. MOVLW NEW_CAPT_PS;Load the W reg with ;the new prescaler FIGURE 21-1: CAPTURE MODE ;move value and CCP ON OPERATION BLOCK MOVWF CCPxCON ;Load CCPxCON with this ;value DIAGRAM Set Flag bit CCPxIF (PIRx register) Prescaler  1, 4, 16 CCPx CCPRxH CCPRxL pin and Capture Edge Detect Enable TMR1H TMR1L CCPxM<3:0> System Clock (FOSC)  2012-2016 Microchip Technology Inc. DS40001624D-page 229

PIC16(L)F1512/3 21.1.5 CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 21.1.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section12.1 “Alternate Pin Function” for more information. DS40001624D-page 230  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 21.2 Compare Mode 21.2.2 TIMER1 MODE RESOURCE The Compare mode function described in this section In Compare mode, Timer1 must be running in either is available and identical for al CCP modules. Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Compare mode makes use of the 16-bit Timer1 Counter mode. resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit See Section18.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: Note: Clocking Timer1 from the system clock • Toggle the CCPx output (FOSC) should not be used in Compare mode. In order for Compare mode to • Set the CCPx output recognize the trigger event on the CCPx • Clear the CCPx output pin, TImer1 must be clocked from the • Generate a Special Event Trigger instruction clock (FOSC/4) or from an • Generate a Software Interrupt external clock source. The action on the pin is based on the value of the CCPxM<3:0> control bits of the CCPxCON register. At 21.2.3 SOFTWARE INTERRUPT MODE the same time, the interrupt flag CCPxIF bit is set. When Generate Software Interrupt mode is chosen All Compare modes can generate an interrupt. (CCPxM<3:0>=1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON Figure21-2 shows a simplified diagram of the register). Compare operation. 21.2.4 SPECIAL EVENT TRIGGER FIGURE 21-2: COMPARE MODE When Special Event Trigger mode is chosen OPERATION BLOCK (CCPxM<3:0>=1011), the CCPx module does the DIAGRAM following: CCPxM<3:0> • Resets Timer1 Mode Select CCPx • Starts an ADC conversion if ADC is enabled Set CCPxIF Interrupt Flag The CCPx module does not assert control of the CCPx (PIRx) CCPx 4 pin in this mode. Pin CCPRxH CCPRxL The Special Event Trigger output of the CCP occurs Q S Output Comparator immediately upon a match between the TMR1H, R Logic Match TMR1L register pair and the CCPRxH, CCPRxL register pair. The TMR1H, TMR1L register pair is not TMR1H TMR1L TRIS reset until the next rising edge of the Timer1 clock. The Output Enable Special Event Trigger output starts an A/D conversion Special Event Trigger (if the A/D module is enabled). This allows the CCPRxH, CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1. 21.2.1 CCPX PIN CONFIGURATION Refer to Section16.2.5 “Special Event Trigger” for The user must configure the CCPx pin as an output by more information. clearing the associated TRIS bit. Note1: The Special Event Trigger from the CCPx The CCP2 pin function can be moved to alternate pins module does not set interrupt flag bit using the APFCON register (Register12-1). Refer to TMR1IF of the PIR1 register. Section12.1 “Alternate Pin Function” for more details. 2: Removing the match condition by changing the contents of the CCPRxH Note: Clearing the CCPxCON register will force and CCPRxL register pair, between the the CCPx compare output latch to the clock edge that generates the Special default low level. This is not the PORT I/O Event Trigger and the clock edge that data latch. generates the Timer1 Reset, will preclude the Reset from occurring.  2012-2016 Microchip Technology Inc. DS40001624D-page 231

PIC16(L)F1512/3 21.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system Note1: The corresponding TRIS bit must be clock (FOSC) for proper operation. Since FOSC is shut cleared to enable the PWM output on the down during Sleep mode, the Compare mode will not CCPx pin. function properly during Sleep. 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. 21.2.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON. To determine which pins can be FIGURE 21-3: CCP PWM OUTPUT SIGNAL moved and what their default locations are upon a Reset, see Section12.1 “Alternate Pin Function”for Period more information. Pulse Width TMR2 = PR2 21.3 PWM Overview TMR2 = CCPRxH:CCPxCON<5:4> Pulse-Width Modulation (PWM) is a scheme that TMR2 = 0 provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is FIGURE 21-4: SIMPLIFIED PWM BLOCK considered the on state and the low portion of the signal DIAGRAM is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in CCPxCON<5:4> steps. A larger number of steps applied, which Duty Cycle Registers lengthens the pulse width, also supplies more power to CCPRxL the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete CCPx cycle or the total amount of on and off time combined. CCPRxH(2) (Slave) PWM resolution defines the maximum number of steps CCPx that can be present in a single PWM period. A higher Comparator R Q resolution allows for more precise control of the pulse width time and in turn the power that is applied to the S TMR2 (1) load. TRIS The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, Comparator Clear Timer, where 0% is fully off and 100% is fully on. A lower duty toggle CCPx pin and cycle corresponds to less power applied and a higher latch duty cycle PR2 duty cycle corresponds to more power applied. Note 1: The 8-bit timer TMR2 register is concatenated Figure21-3 shows a typical waveform of the PWM with the 2-bit internal system clock (FOSC), or signal. 2 bits of the prescaler, to create the 10-bit time base. 21.3.1 STANDARD PWM OPERATION 2: In PWM mode, CCPRxH is a read-only register. The standard PWM function described in this section is available and identical for all CCP modules. The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • PR2 registers • T2CON registers • CCPRxL registers • CCPxCON registers Figure21-4 shows a simplified block diagram of PWM operation. DS40001624D-page 232  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 21.3.2 SETUP FOR PWM OPERATION When TMR2 is equal to PR2, the following three events occur on the next increment cycle: The following steps should be taken when configuring the CCP module for standard PWM operation: • TMR2 is cleared • The CCPx pin is set. (Exception: If the PWM duty 1. Disable the CCPx pin output driver by setting the cycle=0%, the pin will not be set.) associated TRIS bit. 2. Load the PR2 register with the PWM period • The PWM duty cycle is latched from CCPRxL into value. CCPRxH. 3. Configure the CCP module for the PWM mode by loading the CCPxCON register with the Note: The Timer postscaler (see Section19.1 “Timer2 Operation”) is not used in the appropriate values. determination of the PWM frequency. 4. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty 21.3.5 PWM DUTY CYCLE cycle value. The PWM duty cycle is specified by writing a 10-bit 5. Configure and start Timer2: value to multiple registers: CCPRxL register and • Clear the TMR2IF interrupt flag bit of the DCxB<1:0> bits of the CCPxCON register. The PIRx register. See Note below. CCPRxL contains the eight MSbs and the DCxB<1:0> • Configure the T2CKPS bits of the T2CON bits of the CCPxCON register contain the two LSbs. register with the Timer prescale value. CCPRxL and DCxB<1:0> bits of the CCPxCON • Enable the Timer by setting the TMR2ON register can be written to at any time. The duty cycle bit of the T2CON register. value is not latched into CCPRxH until after the period 6. Enable PWM output pin: completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPRxH • Wait until the Timer overflows and the register is read-only. TMR2IF bit of the PIR1 register is set. See Note below. Equation21-2 is used to calculate the PWM pulse • Enable the CCPx pin output driver by width. clearing the associated TRIS bit. Equation21-3 is used to calculate the PWM duty cycle Note: In order to send a complete duty cycle and ratio. period on the first PWM output, the above steps must be included in the setup EQUATION 21-2: PULSE WIDTH sequence. If it is not critical to start with a complete PWM signal on the first output, Pulse Width = CCPRxL:CCPxCON<5:4>  then step 6 may be ignored. TOSC  (TMR2 Prescale Value) 21.3.3 TIMER2 TIMER RESOURCE The PWM standard mode makes use of the 8-bit EQUATION 21-3: DUTY CYCLE RATIO Timer2 timer resources to specify the PWM period. 21.3.4 PWM PERIOD CCPRxL:CCPxCON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------- 4PR2+1 The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation21-1. The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double EQUATION 21-1: PWM PERIOD buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with PWM Period = PR2+14TOSC either the 2-bit internal system clock (FOSC), or two bits (TMR2 Prescale Value) of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. Note 1: TOSC = 1/FOSC When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure21-4).  2012-2016 Microchip Technology Inc. DS40001624D-page 233

PIC16(L)F1512/3 21.3.6 PWM RESOLUTION EQUATION 21-4: PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution log4PR2+1 Resolution = ------------------------------------------ bits will result in 1024 discrete duty cycles, whereas an 8-bit log2 resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is Note: If the pulse-width value is greater than the 255. The resolution is a function of the PR2 register period, the assigned PWM pin(s) will value as shown by Equation21-4. remain unchanged. TABLE 21-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 21-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 DS40001624D-page 234  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 21.3.7 OPERATION IN SLEEP MODE 21.3.10 ALTERNATE PIN LOCATIONS In Sleep mode, the TMR2register will not increment This module incorporates I/O pins that can be moved to and the state of the module will not change. If the CCPx other locations with the use of the alternate pin function pin is driving a value, it will continue to drive that value. register APFCON. To determine which pins can be When the device wakes up, TMR2 will continue from its moved and what their default locations are upon a previous state. Reset, see Section12.1 “Alternate Pin Function” for more information. 21.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. 21.3.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON — — — — — — SSSEL CCP2SEL 101 CCP1CON — — DC1B<1:0> CCP1M<3:0> 236 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIE2 OSFIE — — — BCLIE — — CCP2IE 71 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 PIR2 OSFIF — — — BCLIF — — CCP2IF 73 PR2 Timer2 Period Register 171* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 173 TMR2 Timer2 Module Register 171 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 103 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information.  2012-2016 Microchip Technology Inc. DS40001624D-page 235

PIC16(L)F1512/3 21.4 CCP Control Registers REGISTER 21-3: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — DCxB<1:0> CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCPx module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: set output on compare match (set CCPxIF) 1001 = Compare mode: clear output on compare match (set CCPxIF) 1010 = Compare mode: generate software interrupt only 1011 = Compare mode: Special Event Trigger (sets CCPxIF bit, starts A/D conversion if A/D module is enabled) 11xx = PWM mode DS40001624D-page 236  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 22.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer • Half-duplex synchronous master independent of device program execution. The • Half-duplex synchronous slave EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous Interface (SCI), can be configured as a full-duplex modes asynchronous system or half-duplex synchronous • Sleep operation system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT The EUSART module implements the following terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems: with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate circuits, serial EEPROMs or other microcontrollers. • Wake-up on Break reception These devices typically do not have internal clocks for • 13-bit Break character transmit baud rate generation and require the external clock signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and receiver are shown in Figure22-1 and Figure22-2. FIGURE 22-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREG Register TXIF 8 MSb LSb TX/CK pin (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT SPEN Baud Rate Generator FOSC ÷ n TX9 BRG16 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 X 0 0 0 SPBRGH SPBRGL BRGH X 1 1 0 0 BRG16 X 1 0 1 0  2012-2016 Microchip Technology Inc. DS40001624D-page 237

PIC16(L)F1512/3 FIGURE 22-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN OERR RCIDL RX/DT pin MSb RSR Register LSb Panind BCuoffnetrrol DReactaovery Stop (8) 7 • • • 1 0 Start Baud Rate Generator FOSC RX9 ÷ n BRG16 n + 1 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 FIFO SPBRGH SPBRGL BRGH X 1 1 0 0 FERR RX9D RCREG Register BRG16 X 1 0 1 0 8 Data Bus RCIF Interrupt RCIE The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These registers are detailed in Register22-1, Register22-2 and Register22-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output. DS40001624D-page 238  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 22.1 EUSART Asynchronous Mode 22.1.1.2 Transmitting Data The EUSART transmits and receives data using the A transmission is initiated by writing a character to the standard non-return-to-zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the implemented with two levels: a VOH mark state which previous character has been completely flushed from represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXREG is immediately represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains consecutively transmitted data bits of the same value all or part of a previous character, the new character stay at the output level of that bit without returning to a data is held in the TXREG until the Stop bit of the neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending transmission port idles in the mark state. Each character character in the TXREG is then transferred to the TSR transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits or nine data bits and is always terminated by one or and Stop bit sequence commences immediately more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data following the transfer of the data to the TSR from the format is eight bits. Each transmitted bit persists for a TXREG. period of 1/(Baud Rate). An on-chip dedicated 22.1.1.3 Transmit Data Polarity 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system The polarity of the transmit data can be controlled with oscillator. See Table22-4 for examples of baud rate the SCKP bit of the BAUDCON register. The default configurations. state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the SCKP bit to ‘1’ will invert the The EUSART transmits and receives the LSb first. The transmit data resulting in low true idle and data bits. The EUSART’s transmitter and receiver are functionally SCKP bit controls transmit data polarity in independent, but share the same data format and baud Asynchronous mode only. In Synchronous mode, the rate. Parity is not supported by the hardware, but can SCKP bit has a different function. See Section22.5.1.2 be implemented in software and stored as the ninth “Clock Polarity”. data bit. 22.1.1.4 Transmit Interrupt Flag 22.1.1 EUSART ASYNCHRONOUS TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no The EUSART transmitter block diagram is shown in character is being held for transmission in the TXREG. Figure22-1. The heart of the transmitter is the serial In other words, the TXIF bit is only clear when the TSR Transmit Shift Register (TSR), which is not directly is busy with a character and a new character has been accessible by software. The TSR obtains its data from queued for transmission in the TXREG. The TXIF flag bit the transmit buffer, which is the TXREG register. is not cleared immediately upon writing TXREG. TXIF 22.1.1.1 Enabling the Transmitter becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following The EUSART transmitter is enabled for asynchronous the TXREG write will return invalid results. The TXIF bit operations by configuring the following three control is read-only, it cannot be set or cleared by software. bits: The TXIF interrupt can be enabled by setting the TXIE • TXEN = 1 interrupt enable bit of the PIE1 register. However, the • SYNC = 0 TXIF flag bit will be set whenever the TXREG is empty, • SPEN = 1 regardless of the state of TXIE enable bit. All other EUSART control bits are assumed to be in To use interrupts when transmitting data, set the TXIE their default state. bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character Setting the TXEN bit of the TXSTA register enables the of the transmission to the TXREG. transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note1: The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set.  2012-2016 Microchip Technology Inc. DS40001624D-page 239

PIC16(L)F1512/3 22.1.1.5 TSR Status 22.1.1.7 Asynchronous Transmission Set-up: The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRGL register pair and status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired TRMT bit is set when the TSR register is empty and is baud rate (see Section22.4 “EUSART Baud cleared when a character is transferred to the TSR Rate Generator (BRG)”). register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit. No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 poll this bit to determine the TSR status. control bit. A set ninth data bit will indicate that Note: The TSR register is not mapped in data the eight Least Significant data bits are an memory, so it is not available to the user. address when the receiver is set for address detection. 22.1.1.6 Transmitting 9-Bit Characters 4. Set SCKP bit if inverted transmit is desired. The EUSART supports 9-bit character transmissions. 5. Enable the transmission by setting the TXEN When the TX9 bit of the TXSTA register is set, the control bit. This will cause the TXIF interrupt bit EUSART will shift nine bits out for each character to be set. transmitted. The TX9D bit of the TXSTA register is the 6. If interrupts are desired, set the TXIE interrupt ninth, and Most Significant, data bit. When transmitting enable bit of the PIE1 register. An interrupt will 9-bit data, the TX9D data bit must be written before occur immediately provided that the GIE and writing the eight Least Significant bits into the TXREG. PEIE bits of the INTCON register are also set. All nine bits of data will be transferred to the TSR shift 7. If 9-bit transmission is selected, the ninth bit register immediately after the TXREG is written. should be loaded into the TX9D data bit. A special 9-bit Address mode is available for use with 8. Load 8-bit data into the TXREG register. This multiple receivers. See Section22.1.2.7 “Address will start the transmission. Detection” for more information on the address mode. FIGURE 22-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) DS40001624D-page 240  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 22-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Transmit Buffer Reg. Empty Flag) 1 TCY TRMT bit Word 1 Word 2 (Transmit Shift Transmit Shift Reg. Transmit Shift Reg. Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248 SPBRGL BRG<7:0> 250* SPBRGH BRG<15:8> 250* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 110 TXREG EUSART Transmit Data Register 239* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for asynchronous transmission. * Page provides register information.  2012-2016 Microchip Technology Inc. DS40001624D-page 241

PIC16(L)F1512/3 22.1.2 EUSART ASYNCHRONOUS 22.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit, systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data Figure22-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts the baud rate, whereas the serial Receive Shift character reception, without generating an error, and Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data are immediately transferred to a two character recovery circuit counts a full bit time to the center of the First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. start of a third character before software must start This repeats until all data bits have been sampled and servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always Access to the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this 22.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this character. See Section22.1.2.4 “Receive Framing The EUSART receiver is enabled for asynchronous Error” for more information on framing errors. operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have • CREN = 1 been received, the character in the RSR is transferred • SYNC = 0 to the EUSART receive FIFO and the RCIF interrupt • SPEN = 1 flag bit of the PIR1 register is set. The top character in All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the their default state. RCREG register. Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun of the TXSTA register configures the EUSART for condition is cleared. See Section22.1.2.5 asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more RCSTA register enables the EUSART. The programmer information on overrun errors. must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. 22.1.2.3 Receive Interrupts Note1: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is cleared for the receiver to function. an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: • RCIE, Interrupt Enable bit of the PIE1 register • PEIE, Peripheral Interrupt Enable bit of the INTCON register • GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS40001624D-page 242  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 22.1.2.4 Receive Framing Error 22.1.2.7 Address Detection Each character in the receive FIFO buffer has a A special Address Detection mode is available for use corresponding framing error Status bit. A framing error when multiple receivers share the same transmission indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA FERR bit of the RCSTA register. The FERR bit register. represents the status of the top unread character in the Address detection requires 9-bit character reception. receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters before reading the RCREG. with the ninth data bit set will be transferred to the The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt unread character in the receive FIFO. A framing error bit. All other characters will be ignored. (FERR = 1) does not preclude reception of additional Upon receiving an address character, user software characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon Reading the next character from the FIFO buffer will address match, user software must disable address advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next corresponding framing error. Stop bit occurs. When user software detects the end of The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit. affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. 22.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 22.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG.  2012-2016 Microchip Technology Inc. DS40001624D-page 243

PIC16(L)F1512/3 22.1.2.8 Asynchronous Reception Set-up: 22.1.2.9 9-bit Address Detection Mode Set-up 1. Initialize the SPBRGH, SPBRGL register pair This mode would typically be used in RS-485 systems. and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section22.4 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRGL register pair 2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the 3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section22.4 “EUSART The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”). operation. 2. Clear the ANSEL bit for the RX pin (if applicable). 4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit. PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous INTCON register. operation. 5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the 6. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the 7. The RCIF interrupt flag bit will be set when a INTCON register. character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit. receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN the RCIE interrupt enable bit was also set. bit. 8. Read the RCSTA register to get the error flags 7. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit register. was also set. 10. If an overrun occurred, clear the OERR flag by 9. Read the RCSTA register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. FIGURE 22-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg. Word 1 Word 2 RCREG RCREG RCIDL Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS40001624D-page 244  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 RCREG EUSART Receive Data Register 242* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248 SPBRGL BRG<7:0> 250* SPBRGH BRG<15:8> 250* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 110 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for asynchronous reception. * Page provides register information.  2012-2016 Microchip Technology Inc. DS40001624D-page 245

PIC16(L)F1512/3 22.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. The Auto-Baud Detect feature (see 22.4.1 “Auto-Baud Detect”) can be used to compensate for changes in the INTOSC frequency. There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. DS40001624D-page 246  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 22.3 EUSART Control Registers REGISTER 22-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2012-2016 Microchip Technology Inc. DS40001624D-page 247

PIC16(L)F1512/3 REGISTER 22-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001624D-page 248  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 REGISTER 22-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2012-2016 Microchip Technology Inc. DS40001624D-page 249

PIC16(L)F1512/3 22.4 EUSART Baud Rate Generator EXAMPLE 22-1: CALCULATING BAUD (BRG) RATE ERROR The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. FOSC Desired Baud Rate = ------------------------------------------------------------------------ By default, the BRG operates in 8-bit mode. Setting the 64[SPBRGH:SPBRGL]+1 BRG16 bit of the BAUDCON register selects 16-bit Solving for SPBRGH:SPBRGL: mode. FOSC The SPBRGH, SPBRGL register pair determines the --------------------------------------------- Desired Baud Rate period of the free running baud rate timer. In X = ---------------------------------------------–1 64 Asynchronous mode the multiplier of the baud rate 16000000 period is determined by both the BRGH bit of the TXSTA ------------------------ 9600 register and the BRG16 bit of the BAUDCON register. In = ------------------------–1 64 Synchronous mode, the BRGH bit is ignored. = 25.042 = 25 Table contains the formulas for determining the baud rate. Example22-1 provides a sample calculation for 16000000 Calculated Baud Rate = --------------------------- determining the baud rate and baud rate error. 6425+1 Typical baud rates and error values for various = 9615 Asynchronous modes have been computed for your convenience and are shown in Table. It may be Calc. Baud Rate–Desired Baud Rate Error = -------------------------------------------------------------------------------------------- advantageous to use the high baud rate (BRGH = 1), Desired Baud Rate or the 16-bit BRG (BRG16 = 1) to reduce the baud rate 9615–9600 error. The 16-bit BRG mode is used to achieve slow = ---------------------------------- = 0.16% 9600 baud rates for fast oscillator frequencies. Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock. DS40001624D-page 250  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 22-4: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair. TABLE 22-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248 SPBRGL BRG<7:0> 250* SPBRGH BRG<15:8> 250* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Baud Rate Generator. * Page provides register information.  2012-2016 Microchip Technology Inc. DS40001624D-page 251

PIC16(L)F1512/3 TABLE 22-4: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k — — — 57.60k 0.00 7 — — — 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5 DS40001624D-page 252  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 22-4: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — —  2012-2016 Microchip Technology Inc. DS40001624D-page 253

PIC16(L)F1512/3 TABLE 22-4: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264 19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — — DS40001624D-page 254  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 22.4.1 AUTO-BAUD DETECT and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. Note1: If the WUE bit is set with the ABDEN bit, In the Auto-Baud Detect (ABD) mode, the clock to the auto-baud detection will occur on the byte BRG is reversed. Rather than the BRG clocking the following the Break character (see incoming RX signal, the RX signal is timing the BRG. Section22.4.3 “Auto-Wake-up on The Baud Rate Generator is used to time the period of Break”). a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the that it has five rising edges including the Stop bit edge. incoming character baud rate is within the range of the selected BRG clock source. Setting the ABDEN bit of the BAUDCON register starts Some combinations of oscillator frequency the auto-baud calibration sequence (Figure22-6). and EUSART baud rates are not possible. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of 3: During the auto-baud process, the the receive line, after the Start bit, the SPBRG begins auto-baud counter starts counting at 1. counting up using the BRG counter clock as shown in Upon completion of the auto-baud Table22-5. The fifth rising edge will occur on the RX pin sequence, to achieve maximum accuracy, at the end of the eighth bit period. At that time, an subtract 1 from the SPBRGH:SPBRGL accumulated value totaling the proper BRG period is register pair. left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag TABLE 22-5: BRG COUNTER CLOCK RATES is set. The value in the RCREG needs to be read to BRG Base BRG ABD clear the RCIF interrupt. RCREG content should be BRG16 BRGH Clock Clock discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the 0 0 FOSC/64 FOSC/512 SPBRGL register did not overflow by checking for 00h 0 1 FOSC/16 FOSC/128 in the SPBRGH register. 1 0 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table22-5. During ABD, 1 1 FOSC/4 FOSC/32 both the SPBRGH and SPBRGL registers are used as Note: During the ABD sequence, SPBRGL and a 16-bit counter, independent of the BRG16 bit setting. SPBRGH registers are both used as a While calibrating the baud rate period, the SPBRGH 16-bit counter, independent of BRG16 setting. FIGURE 22-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL XXh 1Ch SPBRGH XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.  2012-2016 Microchip Technology Inc. DS40001624D-page 255

PIC16(L)F1512/3 22.4.2 AUTO-BAUD OVERFLOW 22.4.3.1 Special Considerations During the course of automatic baud detection, the Break Character ABDOVF bit of the BAUDxCON register will be set if To avoid character errors or character fragments during the baud rate counter overflows before the fifth rising a wake-up event, the wake-up character must be all edge is detected on the RX pin. The ABDOVF bit indi- zeros. cates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPx- When the wake-up is enabled the function works BRGL register pair. The overflow condition will set the independent of the low time on the data stream. If the RCIF flag. The counter continues to count until the fifth WUE bit is set and a valid non-zero character is rising edge is detected on the RX pin. The RCIDL bit received, the low time from the Start bit to the first rising will remain false ('0') until the fifth rising edge at which edge will be interpreted as the wake-up event. The time the RCIDL bit will be set. If the RCREG is read remaining bits in the character will be received as a after the overflow occurs but before the fifth rising edge fragmented character and subsequent characters can then the fifth rising edge will set the RCIF again. result in framing or overrun errors. Terminating the auto-baud process early to clear an Therefore, the initial character in the transmission must overflow condition will prevent proper detection of the be all ‘0’s. This must be 10 or more bit times, 13-bit sync character fifth rising edge. If any falling edges of times recommended for LIN bus, or any number of bit the sync character have not yet occurred when the times for standard RS-232 devices. ABDEN bit is cleared then those will be falsely detected Oscillator Start-up Time as start bits. The following steps are recommended to Oscillator start-up time must be considered, especially clear the overflow condition: in applications using oscillators with longer start-up 1. Read RCREG to clear RCIF. intervals (i.e., LP, XT or HS mode). The Sync Break (or wake-up signal) character must be of sufficient length, 2. If RCIDL is zero then wait for RCIF and repeat step 1. and be followed by a sufficient interval, to allow enough 3. Clear the ABDOVF bit. time for the selected oscillator to start and provide proper initialization of the EUSART. 22.4.3 AUTO-WAKE-UP ON BREAK WUE Bit During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator The wake-up event causes a receive interrupt by is inactive and a proper character reception cannot be setting the RCIF bit. The WUE bit is cleared in performed. The Auto-Wake-up feature allows the hardware by a rising edge on RX/DT. The interrupt controller to wake-up due to activity on the RX/DT line. condition is then cleared in software by reading the This feature is available only in Asynchronous mode. RCREG register and discarding its contents. The Auto-Wake-up feature is enabled by setting the To ensure that no actual data is lost, check the RCIDL WUE bit of the BAUDCON register. Once set, the normal bit to verify that a receive operation is not in process receive sequence on RX/DT is disabled, and the before setting the WUE bit. If a receive operation is not EUSART remains in an Idle state, monitoring for a occurring, the WUE bit may then be set just prior to wake-up event independent of the CPU mode. A entering the Sleep mode. wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure22-7), and asynchronously if the device is in Sleep mode (Figure22-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. DS40001624D-page 256  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 22-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 22-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RX/DT Line Note 1 RCIF Cleared due to User Read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set.  2012-2016 Microchip Technology Inc. DS40001624D-page 257

PIC16(L)F1512/3 22.4.4 BREAK CHARACTER SEQUENCE 22.4.5 RECEIVING A BREAK CHARACTER The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break special Break character sequences that are required by character in two ways. the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the Received data To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is bits of the TXSTA register. The Break character assumed to have been initialized to the expected baud transmission is then initiated by a write to the TXREG. rate. The value of data written to TXREG will be ignored and A Break character has been received when; all ‘0’s will be transmitted. • RCIF bit is set The SENDB bit is automatically reset by hardware after • FERR bit is set the corresponding Stop bit is sent. This allows the user • RCREG = 00h to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature character in the LIN specification). described in Section22.4.3 “Auto-Wake-up on Break”. By enabling this feature, the EUSART will The TRMT bit of the TXSTA register indicates when the sample the next two transitions on RX/DT, cause an transmit operation is active or idle, just as it does during RCIF interrupt, and receive the next data byte followed normal transmission. See Figure22-9 for the timing of by another interrupt. the Break character sequence. Note that following a Break character, the user will 22.4.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature. The following sequence will start a message frame For both methods, the user can set the ABDEN bit of header made up of a Break, followed by an auto-baud the BAUDCON register before placing the EUSART in Sync byte. This sequence is typical of a LIN bus Sleep mode. master. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to enable the Break sequence. 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. FIGURE 22-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit) DS40001624D-page 258  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 22.5 EUSART Synchronous Mode 22.5.1.2 Clock Polarity Synchronous serial communications are typically used A clock polarity option is provided for Microwire in systems with a single master and one or more compatibility. Clock polarity is selected with the SCKP slaves. The master device contains the necessary bit of the BAUDCON register. Setting the SCKP bit sets circuitry for baud rate generation and supplies the clock the clock Idle state as high. When the SCKP bit is set, for all devices in the system. Slave devices can take the data changes on the falling edge of each clock. advantage of the master clock by eliminating the Clearing the SCKP bit sets the Idle state as low. When internal clock generation circuitry. the SCKP bit is cleared, the data changes on the rising edge of each clock. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the 22.5.1.3 Synchronous Master Transmission external clock supplied by the master to shift the serial Data is transferred out of the device on the RX/DT pin. data into and out of their respective receive and trans- The RX/DT and TX/CK pin output drivers are automat- mit shift registers. Since the data line is bidirectional, ically enabled when the EUSART is configured for synchronous operation is half-duplex only. Half-duplex synchronous master transmit operation. refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. A transmission is initiated by writing a character to the The EUSART can operate as either a master or slave TXREG register. If the TSR still contains all or part of a device. previous character the new character data is held in the TXREG until the last bit of the previous character has Start and Stop bits are not used in synchronous been transmitted. If this is the first character, or the transmissions. previous character has been completely flushed from 22.5.1 SYNCHRONOUS MASTER MODE the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the The following bits are used to configure the EUSART character commences immediately following the for Synchronous Master operation: transfer of the data to the TSR from the TXREG. • SYNC = 1 Each data bit changes on the leading edge of the • CSRC = 1 master clock and remains valid until the subsequent • SREN = 0 (for transmit); SREN = 1 (for receive) leading clock edge. • CREN = 0 (for transmit); CREN = 1 (for receive) Note: The TSR register is not mapped in data • SPEN = 1 memory, so it is not available to the user. Setting the SYNC bit of the TXSTA register configures 22.5.1.4 Synchronous Master Transmission the device for synchronous operation. Setting the CSRC Set-up: bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA 1. Initialize the SPBRGH, SPBRGL register pair register ensures that the device is in the Transmit mode, and the BRGH and BRG16 bits to achieve the otherwise the device will be configured to receive. Setting desired baud rate (see Section22.4 “EUSART the SPEN bit of the RCSTA register enables the Baud Rate Generator (BRG)”). EUSART. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 22.5.1.1 Master Clock 3. Disable Receive mode by clearing bits SREN Synchronous data transfers use a separate clock line, and CREN. which is synchronous with the data. A device config- 4. Enable Transmit mode by setting the TXEN bit. ured as a master transmits the clock on the TX/CK line. 5. If 9-bit transmission is desired, set the TX9 bit. The TX/CK pin output driver is automatically enabled 6. If interrupts are desired, set the TXIE bit of the when the EUSART is configured for synchronous PIE1 register and the GIE and PEIE bits of the transmit or receive operation. Serial data bits change INTCON register. on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is 7. If 9-bit transmission is selected, the ninth bit generated for each data bit. Only as many clock cycles should be loaded in the TX9D bit. are generated as there are data bits. 8. Start transmission by loading data to the TXREG register.  2012-2016 Microchip Technology Inc. DS40001624D-page 259

PIC16(L)F1512/3 FIGURE 22-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 22-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 22-6: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248 SPBRGL BRG<7:0> 250* SPBRGH BRG<15:8> 250* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 110 TXREG EUSART Transmit Data Register 239* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. * Page provides register information. DS40001624D-page 260  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 22.5.1.5 Synchronous Master Reception 22.5.1.7 Receive Overrun Error Data is received at the RX/DT pin. The RX/DT pin The receive FIFO buffer can hold two characters. An output driver is automatically disabled when the overrun error will be generated if a third character, in its EUSART is configured for synchronous master receive entirety, is received before RCREG is read to access operation. the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will In Synchronous mode, reception is enabled by setting not be overwritten. The two characters in the FIFO either the Single Receive Enable bit (SREN of the buffer can be read, however, no additional characters RCSTA register) or the Continuous Receive Enable bit will be received until the error is cleared. The OERR bit (CREN of the RCSTA register). can only be cleared by clearing the overrun condition. When SREN is set and CREN is clear, only as many If the overrun error occurred when the SREN bit is set clock cycles are generated as there are data bits in a and CREN is clear then the error is cleared by reading single character. The SREN bit is automatically cleared RCREG. If the overrun occurred when the CREN bit is at the completion of one character. When CREN is set, set then the error condition is cleared by either clearing clocks are continuously generated until CREN is the CREN bit of the RCSTA register or by clearing the cleared. If CREN is cleared in the middle of a character SPEN bit which resets the EUSART. the CK clock stops immediately and the partial charac- ter is discarded. If SREN and CREN are both set, then 22.5.1.8 Receiving 9-bit Characters SREN is cleared at the completion of the first character The EUSART supports 9-bit character reception. When and CREN takes precedence. the RX9 bit of the RCSTA register is set the EUSART To initiate reception, set either SREN or CREN. Data is will shift 9-bits into the RSR for each character sampled at the RX/DT pin on the trailing edge of the received. The RX9D bit of the RCSTA register is the TX/CK clock pin and is shifted into the Receive Shift ninth, and Most Significant, data bit of the top unread Register (RSR). When a complete character is character in the receive FIFO. When reading 9-bit data received into the RSR, the RCIF bit is set and the from the receive FIFO buffer, the RX9D data bit must character is automatically transferred to the two be read before reading the eight Least Significant bits character receive FIFO. The Least Significant eight bits from the RCREG. of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are 22.5.1.9 Synchronous Master Reception unread characters in the receive FIFO. Set-up: Note: If the RX/DT function is on an analog pin, 1. Initialize the SPBRGH, SPBRGL register pair for the corresponding ANSEL bit must be the appropriate baud rate. Set or clear the cleared for the receiver to function. BRGH and BRG16 bits, as required, to achieve the desired baud rate. 22.5.1.6 Slave Clock 2. Clear the ANSEL bit for the RX pin (if applicable). Synchronous data transfers use a separate clock line, 3. Enable the synchronous master serial port by which is synchronous with the data. A device configured setting bits SYNC, SPEN and CSRC. as a slave receives the clock on the TX/CK line. The 4. Ensure bits CREN and SREN are clear. TX/CK pin output driver is automatically disabled when 5. If interrupts are desired, set the RCIE bit of the the device is configured for synchronous slave transmit PIE1 register and the GIE and PEIE bits of the or receive operation. Serial data bits change on the INTCON register. leading edge to ensure they are valid at the trailing edge 6. If 9-bit reception is desired, set bit RX9. of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as 7. Start reception by setting the SREN bit or for there are data bits. continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF will be set when reception Note: If the device is configured as a slave and of a character is complete. An interrupt will be the TX/CK function is on an analog pin, the generated if the enable bit RCIE was set. corresponding ANSEL bit must be 9. Read the RCSTA register to get the ninth bit (if cleared. enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART.  2012-2016 Microchip Technology Inc. DS40001624D-page 261

PIC16(L)F1512/3 FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 22-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 RCREG EUSART Receive Data Register 242* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248 SPBRGL BRG<7:0> 250* SPBRGH BRG<15:8> 250* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 110 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. * Page provides register information. DS40001624D-page 262  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 22.5.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the EUSART for synchronous slave operation: 1. The first character will immediately transfer to the TSR register and transmit. • SYNC = 1 2. The second word will remain in the TXREG • CSRC = 0 register. • SREN = 0 (for transmit); SREN = 1 (for receive) 3. The TXIF bit will not be set. • CREN = 0 (for transmit); CREN = 1 (for receive) 4. After the first character has been shifted out of • SPEN = 1 TSR, the TXREG register will transfer the second Setting the SYNC bit of the TXSTA register configures the character to the TSR and the TXIF bit will now be device for synchronous operation. Clearing the CSRC bit set. of the TXSTA register configures the device as a slave. 5. If the PEIE and TXIE bits are set, the interrupt Clearing the SREN and CREN bits of the RCSTA register will wake the device from Sleep and execute the ensures that the device is in the Transmit mode, next instruction. If the GIE bit is also set, the otherwise the device will be configured to receive. Setting program will call the Interrupt Service Routine. the SPEN bit of the RCSTA register enables the EUSART. 22.5.2.2 Synchronous Slave Transmission Set-up: 22.5.2.1 EUSART Synchronous Slave 1. Set the SYNC and SPEN bits and clear the Transmit CSRC bit. The operation of the Synchronous Master and Slave 2. Clear the ANSEL bit for the CK pin (if applicable). modes are identical (see Section22.5.1.3 3. Clear the CREN and SREN bits. “Synchronous Master Transmission”), except in the case of the Sleep mode. 4. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit transmission is desired, set the TX9 bit. 6. Enable transmission by setting the TXEN bit. 7. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 8. Start transmission by writing the Least Significant eight bits to the TXREG register. TABLE 22-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 110 TXREG EUSART Transmit Data Register 239* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. * Page provides register information.  2012-2016 Microchip Technology Inc. DS40001624D-page 263

PIC16(L)F1512/3 22.5.2.3 EUSART Synchronous Slave 22.5.2.4 Synchronous Slave Reception Reception Set-up: The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the modes is identical (Section22.5.1.5 “Synchronous CSRC bit. Master Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins • Sleep (if applicable). • CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RCIE bit of the never Idle PIE1 register and the GIE and PEIE bits of the INTCON register. • SREN bit, which is a “don’t care” in Slave mode 4. If 9-bit reception is desired, set the RX9 bit. A character may be received while in Sleep mode by 5. Set the CREN bit to enable reception. setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data 6. The RCIF bit will be set when reception is to the RCREG register. If the RCIE enable bit is set, the complete. An interrupt will be generated if the interrupt generated will wake the device from Sleep RCIE bit was set. and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTA register. 8. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 22-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 69 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 70 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72 RCREG EUSART Receive Data Register 242* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 110 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. * Page provides register information. DS40001624D-page 264  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 22.6 EUSART Operation During Sleep 22.6.2 SYNCHRONOUS TRANSMIT DURING SLEEP The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the To transmit during Sleep, all the following conditions system clock and therefore cannot generate the must be met before entering Sleep mode: necessary signals to run the Transmit or Receive Shift • RCSTA and TXSTA Control registers must be registers during Sleep. configured for Synchronous Slave Transmission Synchronous Slave mode uses an externally generated (see Section22.5.2.2 “Synchronous Slave clock to run the Transmit and Receive Shift registers. Transmission Set-up:”). • The TXIF interrupt flag must be cleared by writing 22.6.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the SLEEP TSR and transmit buffer. To receive during Sleep, all the following conditions • If interrupts are desired, set the TXIE bit of the must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON register. • RCSTA and TXSTA Control registers must be • Interrupt enable bits TXIE of the PIE1 register and configured for Synchronous Slave Reception (see PEIE of the INTCON register must set. Section22.5.2.4 “Synchronous Slave Reception Set-up:”). Upon entering Sleep mode, the device will be ready to • If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the PIE1 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been INTCON register. completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and • The RCIF interrupt flag must be cleared by read- the TXIF flag will be set. Thereby, waking the processor ing RCREG to unload any pending characters in from Sleep. At this point, the TXREG is available to the receive buffer. accept another character for transmission, which will Upon entering Sleep mode, the device will be ready to clear the TXIF flag. accept data and clocks on the RX/DT and TX/CK pins, Upon waking from Sleep, the instruction following the respectively. When the data word has been completely SLEEP instruction will be executed. If the Global clocked in by the external device, the RCIF interrupt Interrupt Enable (GIE) bit is also set then the Interrupt flag bit of the PIR1 register will be set. Thereby, waking Service Routine at address 0004h will be called. the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called.  2012-2016 Microchip Technology Inc. DS40001624D-page 265

PIC16(L)F1512/3 23.0 IN-CIRCUIT SERIAL 23.2 Low-Voltage Programming Entry PROGRAMMING™ (ICSP™) Mode ICSP™ programming allows customers to manufacture The Low-Voltage Programming Entry mode allows the circuit boards with unprogrammed devices. Programming PIC16(L)F1512/3 devices to be programmed using can be done after the assembly process allowing the VDD only, without high voltage. When the LVP bit of device to be programmed with the most recent firmware Configuration Words is set to ‘1’, the low-voltage ICSP or a custom firmware. Five pins are needed for ICSP™ programming entry is enabled. To disable the programming: Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. • ICSPCLK • ICSPDAT Entry into the Low-Voltage Programming Entry mode requires the following steps: • MCLR/VPP • VDD 1. MCLR is brought to VIL. • VSS 2. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through Once the key sequence is complete, MCLR must be serial communications. The ICSPDAT pin is a held at VIL for as long as Program/Verify mode is to be bidirectional I/O used for transferring the serial data and maintained. the ICSPCLK pin is the clock input. For more information If low-voltage programming is enabled (LVP = 1), the on ICSP™ refer to the “PIC16(L)F151X/152X Memory MCLR Reset function is automatically enabled and Programming Specification” (DS41442). cannot be disabled. See Section6.3 “Low-Power Brown-out Reset (LPBOR)” for more information. 23.1 High-Voltage Programming Entry The LVP bit can only be reprogrammed to ‘0’ by using Mode the High-Voltage Programming mode. The device is placed into High-Voltage Programming 23.3 Common Programming Interfaces Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6 connector) configuration. See Figure23-1. FIGURE 23-1: ICD RJ-11 STYLE CONNECTOR INTERFACE ICSPDAT 2 4 6 NC VDD ICSPCLK 1 3 5 Target VPP/MCLR VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect DS40001624D-page 266  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1inch spacing. Refer to Figure23-2. FIGURE 23-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 1 = VPP/MCLR 2 2 = VDD Target 3 4 3 = VSS (ground) 5 4 = ICSPDAT 6 5 = ICSPCLK 6 = No Connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins. For additional interface recommendations, refer to your It is recommended that isolation devices be used to specific device programmer manual prior to PCB separate the programming pins from other circuitry. design. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure23-3 for more information. FIGURE 23-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming VDD Device to be Signals Programmed VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required).  2012-2016 Microchip Technology Inc. DS40001624D-page 267

PIC16(L)F1512/3 24.0 INSTRUCTION SET SUMMARY 24.1 Read-Modify-Write Operations Each instruction is a 14-bit word containing the Any instruction that specifies a file register as part of operation code (opcode) and all required operands. the instruction performs a Read-Modify-Write (R-M-W) The opcodes are broken into three broad categories. operation. The register is read, the data is modified, and the result is stored according to either the instruc- • Byte Oriented tion, or the destination designator ‘d’. A read operation • Bit Oriented is performed on a register even if the instruction writes • Literal and Control to that register. The literal and control category contains the most var- ied instruction word format. TABLE 24-1: OPCODE FIELD Table24-1 lists the instructions recognized by the DESCRIPTIONS MPASMTM assembler. Field Description All instructions are executed within a single instruction cycle, with the following exceptions, which may take f Register file address (0x00 to 0x7F) two or three cycles: W Working register (accumulator) • Subroutine takes two cycles (CALL, CALLW) b Bit address within an 8-bit file register • Returns from interrupts or subroutines take two k Literal field, constant data or label cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1). • Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0. BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for • One additional instruction cycle will be used when compatibility with all Microchip software tools. any instruction references an indirect file register and the file select register is pointing to program d Destination select; d = 0: store result in W, memory. d = 1: store result in file register f. Default is d = 1. One instruction cycle consists of four oscillator cycles; n FSR or INDF number. (0-1) for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. mm Pre-post increment-decrement mode selection All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. TABLE 24-2: ABBREVIATION DESCRIPTIONS Field Description PC Program Counter TO Time-out bit C Carry bit DC Digit carry bit Z Zero bit PD Power-down bit DS40001624D-page 268  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value MOVLP instruction only 13 7 6 0 OPCODE k (literal) k = 7-bit immediate value MOVLB instruction only 13 5 4 0 OPCODE k (literal) k = 5-bit immediate value BRA instruction only 13 9 8 0 OPCODE k (literal) k = 9-bit immediate value FSR Offset instructions 13 7 6 5 0 OPCODE n k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 3 2 1 0 OPCODE n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE  2012-2016 Microchip Technology Inc. DS40001624D-page 269

PIC16(L)F1512/3 TABLE 24-3: PIC16(L)F1512/3 INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2 ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2 ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2 LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2 LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0000 00xx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 2 INCF f, d Increment f 1 00 1010 dfff ffff Z 2 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 2 MOVWF f Move W to f 1 00 0000 1fff ffff 2 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2 SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 2 BIT-ORIENTED SKIP OPERATIONS BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2 LITERAL OPERATIONS ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLB k Move literal to BSR 1 00 0000 001k kkkk MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk MOVLW k Move literal to W 1 11 0000 kkkk kkkk SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. DS40001624D-page 270  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 24-4: PIC16(L)F1512/3 INSTRUCTION SET (CONTINUED) 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb CONTROL OPERATIONS BRA k Relative Branch 2 11 001k kkkk kkkk BRW – Relative Branch with W 2 00 0000 0000 1011 CALL k Call Subroutine 2 10 0kkk kkkk kkkk CALLW – Call Subroutine with W 2 00 0000 0000 1010 GOTO k Go to address 2 10 1kkk kkkk kkkk RETFIE k Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 0100 kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 INHERENT OPERATIONS CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD NOP – No Operation 1 00 0000 0000 0000 OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010 RESET – Software device Reset 1 00 0000 0000 0001 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD TRIS f Load TRIS register with W 1 00 0000 0110 0fff C-COMPILER OPTIMIZED ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3 modifier, mm k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2 MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3 modifier, mm k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2 Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions.  2012-2016 Microchip Technology Inc. DS40001624D-page 271

PIC16(L)F1512/3 24.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k Operands: -32  k  31 Operands: 0  k  255 n  [ 0, 1] Operation: (W) .AND. (k)  (W) Operation: FSR(n) + k  FSR(n) Status Affected: Z Status Affected: None Description: The contents of W register are Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The the contents of the FSRnH:FSRnL result is placed in the W register. register pair. FSRn is limited to the range 0000h - FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W ANDWF AND W with f Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d Operands: 0  k  255 Operands: 0  f  127 d 0,1 Operation: (W) + k  (W) Operation: (W) .AND. (f)  (destination) Status Affected: C, DC, Z Status Affected: Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the Description: AND the W register with register ‘f’. If result is placed in the W register. ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWF Add W and f ASRF Arithmetic Right Shift Syntax: [ label ] ADDWF f,d Syntax: [ label ] ASRF f {,d} Operands: 0  f  127 Operands: 0  f  127 d 0,1 d [0,1] Operation: (W) + (f)  (destination) Operation: (f<7>) dest<7> (f<7:1>)  dest<6:0>, Status Affected: C, DC, Z (f<0>)  C, Description: Add the contents of the W register Status Affected: C, Z with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the Description: The contents of register ‘f’ are shifted result is stored back in register ‘f’. one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWFC ADD W and CARRY bit to f register f C Syntax: [ label ] ADDWFC f {,d} Operands: 0  f  127 d [0,1] Operation: (W) + (f) + (C)  dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data mem- ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. DS40001624D-page 272  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 0  b  7 0  b  7 Operation: 0  (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b [ label ] BRA $+k Operands: 0  f  127 Operands: -256label-PC+1255 0  b < 7 -256  k  255 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k  PC Status Affected: None Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Description: Add the signed 9-bit literal ‘k’ to the instruction is executed. PC. Since the PC will have incre- If bit ‘b’ is ‘1’, then the next mented to fetch the next instruction, instruction is discarded and a NOP is the new address will be PC+1+k. executed instead, making this a This instruction is a 2-cycle instruc- 2-cycle instruction. tion. This branch has a limited range. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W)  PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incre- mented to fetch the next instruction, the new address will be PC+1+(W). This instruction is a 2-cycle instruc- tion. BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0  f  127 0  b  7 Operation: 1  (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set.  2012-2016 Microchip Technology Inc. DS40001624D-page 273

PIC16(L)F1512/3 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<6:3>)  PC<14:11> 1  TO Status Affected: None 1  PD Description: Call Subroutine. First, return address Status Affected: TO, PD (PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch- The 11-bit immediate address is dog Timer. It also resets the prescaler loaded into PC bits <10:0>. The upper of the WDT. Status bits TO and PD bits of the PC are loaded from are set. PCLATH. CALL is a 2-cycle instruc- tion. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: (PC) +1  TOS, (W)  PC<7:0>, Operation: (f)  (destination) (PCLATH<6:0>) PC<14:8> Status Affected: Z Description: The contents of register ‘f’ are Status Affected: None complemented. If ‘d’ is ‘0’, the result is Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is return address (PC + 1) is pushed stored back in register ‘f’. onto the return stack. Then, the con- tents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a 2-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the and the Z bit is set. result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h  (W) 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS40001624D-page 274  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre- mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. is placed back in register ‘f’. If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is NOP is executed instead, making it a executed instead, making it a 2-cycle 2-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<6:3>  PC<14:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. The OR’ed with the 8-bit literal ‘k’. The 11-bit immediate value is loaded into result is placed in the W register. PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with mented. If ‘d’ is ‘0’, the result is placed register ‘f’. If ‘d’ is ‘0’, the result is in the W register. If ‘d’ is ‘1’, the result placed in the W register. If ‘d’ is ‘1’, the is placed back in register ‘f’. result is placed back in register ‘f’.  2012-2016 Microchip Technology Inc. DS40001624D-page 275

PIC16(L)F1512/3 LSLF Logical Left Shift MOVF Move f Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d Operands: 0  f  127 Operands: 0  f  127 d [0,1] d  [0,1] Operation: (f<7>)  C Operation: (f)  (dest) (f<6:0>)  dest<7:1> Status Affected: Z 0  dest<0> Description: The contents of register f is moved to Status Affected: C, Z a destination dependent upon the Description: The contents of register ‘f’ are shifted status of d. If d = 0, destination is W one bit to the left through the Carry flag. register. If d = 1, the destination is file A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, register f itself. d = 1 is useful to test a the result is placed in W. If ‘d’ is ‘1’, the file register since status flag Z is result is stored back in register ‘f’. affected. Words: 1 C register f 0 Cycles: 1 Example: MOVF FSR, 0 After Instruction LSRF Logical Right Shift W = value in FSR register Syntax: [ label ] LSRF f {,d} Z = 1 Operands: 0  f  127 d [0,1] Operation: 0  dest<7> (f<7:1>)  dest<6:0>, (f<0>)  C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘0’ is shifted into the MSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 0 register f C DS40001624D-page 276  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 MOVIW Move INDFn to W MOVLP Move literal to PCLATH Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k [ label ] MOVIW --FSRn Operands: 0  k  127 [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-- Operation: k  PCLATH [ label ] MOVIW k[FSRn] Status Affected: None Operands: n  [0,1] Description: The 7-bit literal ‘k’ is loaded into the mm  [00,01, 10, 11] PCLATH register. -32  k  31 Operation: INDFn  W Effective address is determined by MOVLW Move literal to W • FSR + 1 (preincrement) Syntax: [ label ] MOVLW k • FSR - 1 (predecrement) • FSR + k (relative offset) Operands: 0  k  255 After the Move, the FSR value will be Operation: k  (W) either: • FSR + 1 (all increments) Status Affected: None • FSR - 1 (all decrements) Description: The 8-bit literal ‘k’ is loaded into W • Unchanged register. The “don’t cares” will Status Affected: Z assemble as ‘0’s. Words: 1 Mode Syntax mm Cycles: 1 Preincrement ++FSRn 00 Example: MOVLW 0x5A Predecrement --FSRn 01 After Instruction W = 0x5A Postincrement FSRn++ 10 Postdecrement FSRn-- 11 MOVWF Move W to f Syntax: [ label ] MOVWF f Description: This instruction is used to move data between W and one of the indirect Operands: 0  f  127 registers (INDFn). Before/after this Operation: (W)  (f) move, the pointer (FSRn) is updated by Status Affected: None pre/post incrementing/decrementing it. Description: Move data from W register to register Note: The INDFn registers are not ‘f’. physical registers. Any instruction that Words: 1 accesses an INDFn register actually accesses the register at the address Cycles: 1 specified by the FSRn. Example: MOVWF OPTION_REG Before Instruction FSRn is limited to the range 0000h - OPTION_REG = 0xFF FFFFh. Incrementing/decrementing it W = 0x4F beyond these bounds will cause it to After Instruction wrap-around. OPTION_REG = 0x4F W = 0x4F MOVLB Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0  k  15 Operation: k  BSR Status Affected: None Description: The 5-bit literal ‘k’ is loaded into the Bank Select Register (BSR).  2012-2016 Microchip Technology Inc. DS40001624D-page 277

PIC16(L)F1512/3 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] NOP Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn Operands: None [ label ] MOVWI FSRn++ Operation: No operation [ label ] MOVWI FSRn-- [ label ] MOVWI k[FSRn] Status Affected: None Operands: n  [0,1] Description: No operation. mm  [00,01, 10, 11] Words: 1 -32  k  31 Cycles: 1 Operation: W  INDFn Example: NOP Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be Load OPTION_REG Register either: OPTION with W • FSR + 1 (all increments) • FSR - 1 (all decrements) Syntax: [ label ] OPTION Unchanged Operands: None Status Affected: None Operation: (W)  OPTION_REG Status Affected: None Mode Syntax mm Description: Move data from W register to Preincrement ++FSRn 00 OPTION_REG register. Predecrement --FSRn 01 Postincrement FSRn++ 10 Words: 1 Postdecrement FSRn-- 11 Cycles: 1 Example: OPTION Description: This instruction is used to move data Before Instruction between W and one of the indirect OPTION_REG = 0xFF registers (INDFn). Before/after this W = 0x4F move, the pointer (FSRn) is updated by After Instruction pre/post incrementing/decrementing it. OPTION_REG = 0x4F W = 0x4F Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually RESET Software Reset accesses the register at the address specified by the FSRn. Syntax: [ label ] RESET Operands: None FSRn is limited to the range 0000h - FFFFh. Incrementing/decrementing it Operation: Execute a device Reset. Resets the beyond these bounds will cause it to nRI flag of the PCON register. wrap-around. Status Affected: None The increment/decrement operation on Description: This instruction provides a way to FSRn WILL NOT affect any Status bits. execute a hardware Reset by software. DS40001624D-page 278  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] RETFIE k Syntax: [ label ] RETURN Operands: None Operands: None Operation: TOS  PC, Operation: TOS  PC 1  GIE Status Affected: None Status Affected: None Description: Return from subroutine. The stack is Description: Return from Interrupt. Stack is POPed POPed and the top of the stack (TOS) and Top-of-Stack (TOS) is loaded in is loaded into the program counter. the PC. Interrupts are enabled by This is a 2-cycle instruction. setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 RETLW Return with literal in W RLF Rotate Left f through Carry Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d Operands: 0  k  255 Operands: 0  f  127 Operation: k  (W); d  [0,1] TOS  PC Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the 8-bit literal ‘k’. The program counter is Description: The contents of register ‘f’ are rotated loaded from the top of the stack (the one bit to the left through the Carry return address). This is a 2-cycle flag. If ‘d’ is ‘0’, the result is placed in instruction. the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Words: 1 C Register f Cycles: 2 Example: CALL TABLE;W contains table Words: 1 ;offset value Cycles: 1 • ;W now has table value TABLE • Example: RLF REG1,0 • Before Instruction ADDWF PC ;W = offset REG1 = 1110 0110 RETLW k1 ;Begin table C = 0 RETLW k2 ; After Instruction • REG1 = 1110 0110 • W = 1100 1100 • C = 1 RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8  2012-2016 Microchip Technology Inc. DS40001624D-page 279

PIC16(L)F1512/3 SUBLW Subtract W from literal RRF Rotate Right f through Carry Syntax: [ label ] SUBLW k Syntax: [ label ] RRF f,d Operands: 0 k 255 Operands: 0  f  127 d  [0,1] Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s complement method) from the 8-bit Description: The contents of register ‘f’ are rotated literal ‘k’. The result is placed in the W one bit to the right through the Carry register. flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is C = 0 W  k placed back in register ‘f’. C = 1 W  k C Register f DC = 0 W<3:0>  k<3:0> DC = 1 W<3:0>  k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] SLEEP Syntax: [ label ] SUBWF f,d Operands: None Operands: 0 f 127 d  [0,1] Operation: 00h  WDT, 0  WDT prescaler, Operation: (f) - (W) destination) 1  TO, Status Affected: C, DC, Z 0  PD Description: Subtract (2’s complement method) W Status Affected: TO, PD register from register ‘f’. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is result is stored in the W register. If ‘d’ is cleared. Time-out Status bit, TO is ‘1’, the result is stored back in register set. Watchdog Timer and its pres- ‘f. caler are cleared. The processor is put into Sleep mode C = 0 W  f with the oscillator stopped. C = 1 W  f DC = 0 W<3:0>  f<3:0> DC = 1 W<3:0>  f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB f {,d} Operands: 0  f  127 d  [0,1] Operation: (f) – (W) – (B) dest Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s comple- ment method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001624D-page 280  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k Operands: 0  f  127 Operands: 0 k 255 d  [0,1] Operation: (W) .XOR. k W) Operation: (f<3:0>)  (destination<7:4>), Status Affected: Z (f<7:4>)  (destination<3:0>) Description: The contents of the W register are Status Affected: None XOR’ed with the 8-bit literal ‘k’. The Description: The upper and lower nibbles of regis- result is placed in the W register. ter ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. XORWF Exclusive OR W with f TRIS Load TRIS Register with W Syntax: [ label ] XORWF f,d Syntax: [ label ] TRIS f Operands: 0  f  127 Operands: 5  f  7 d  [0,1] Operation: (W)  TRIS register ‘f’ Operation: (W) .XOR. (f) destination) Status Affected: None Status Affected: Z Description: Move data from W register to TRIS Description: Exclusive OR the contents of the W register. register with register ‘f’. If ‘d’ is ‘0’, the When ‘f’ = 5, TRISA is loaded. result is stored in the W register. If ‘d’ When ‘f’ = 6, TRISB is loaded. is ‘1’, the result is stored back in When ‘f’ = 7, TRISC is loaded. register ‘f’.  2012-2016 Microchip Technology Inc. DS40001624D-page 281

PIC16(L)F1512/3 25.0 ELECTRICAL SPECIFICATIONS 25.1 Absolute Maximum Ratings(†) Ambient temperature under bias...................................................................................................... -40°C to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on pins with respect to VSS on VDD pin PIC16F1512/3 ........................................................................................................... -0.3V to +6.5V PIC16LF1512/3 ......................................................................................................... -0.3V to +4.0V on MCLR pin ........................................................................................................................... -0.3V to +9.0V on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V) Maximum current on VSS pin(1) -40°C  TA  +85°C .............................................................................................................. 340 mA -40°C  TA  +125°C ............................................................................................................ 140 mA on VDD pin(1) -40°C  TA  +85°C .............................................................................................................. 255 mA -40°C  TA  +125°C ............................................................................................................ 105 mA on any I/O pin ..................................................................................................................................... 25 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Section25.4 “Thermal Considerations” to calculate device specifications. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001624D-page 282  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 25.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: VDDMIN VDD VDDMAX Operating Temperature: TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC16LF1512/3 VDDMIN (Fosc  16 MHz)......................................................................................................... +1.8V VDDMIN (16 MHz < Fosc  20 MHz)......................................................................................... +2.5V VDDMAX.................................................................................................................................... +3.6V PIC16F1512/3 VDDMIN (Fosc  16 MHz)......................................................................................................... +2.3V VDDMIN (16 MHz < Fosc  20 MHz)......................................................................................... +2.5V VDDMAX.................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN...................................................................................................................................... -40°C TA_MAX.................................................................................................................................... +85°C Extended Temperature TA_MIN...................................................................................................................................... -40°C TA_MAX.................................................................................................................................. +125°C Note 1: See Parameter D001, DC Characteristics: Supply Voltage.  2012-2016 Microchip Technology Inc. DS40001624D-page 283

PIC16(L)F1512/3 FIGURE 25-1: PIC16F1512/3 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C 5.5 ) V ( D D V 2.5 2.3 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table25-6 for each Oscillator mode’s supported frequencies. FIGURE 25-2: PIC16LF1512/3 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C V) 3.6 ( D D V 2.5 1.8 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table25-6 for each Oscillator mode’s supported frequencies. DS40001624D-page 284  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 25.3 DC Characteristics TABLE 25-1: SUPPLY VOLTAGE PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) PIC16F1512/3 Param Sym. Characteristic Min. Typ† Max. Units Conditions . No. D001 VDD Supply Voltage VDDMIN — VDDMAX 1.8 — 3.6 V FOSC  16MHz: 2.5 3.6 V FOSC  20MHz D001 2.3 — 5.5 V FOSC  16MHz: 2.5 — 5.5 V FOSC  20MHz D002* VDR RAM Data Retention Voltage(1) 1.5 — — V Device in Sleep mode D002* 1.7 — — V Device in Sleep mode VPOR* Power-on Reset Release Volt- — 1.6 — V age VPORR* Power-on Reset Rearm Voltage — 1.0 — V — 1.4 — V D003 VADFVR Fixed Voltage Reference Volt- -8 6 % 1.024V, VDD  2.5V age for ADC, Initial Accuracy — — 2.048V, VDD  2.5V 4.096V, VDD  4.75V D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See Section 6.1 “Power-on Reset Power-on Reset signal (POR)” for details. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.  2012-2016 Microchip Technology Inc. DS40001624D-page 285

PIC16(L)F1512/3 FIGURE 25-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(3) TPOR(2) Note 1: When NPOR is low, the device is held in Reset. 2: TPOR 1s typical. 3: TVLOW 2.7s typical. DS40001624D-page 286  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 25-2: SUPPLY VOLTAGE (IDD)(1,2) PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) PIC16F1512/3 Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note D010 — 8.0 16 A 1.8 FOSC = 32kHz — 12.0 25 A 3.0 LP Oscillator mode, -40°C  TA  +85°C D010 — 17 28 A 2.3 FOSC = 32kHz — 20 35 A 3.0 LP Oscillator mode, -40°C  TA  +85°C — 23 45 A 5.0 D010A — 8.0 23 A 1.8 FOSC = 32kHz — 12.0 35 A 3.0 LP Oscillator mode, -40°C  TA  +125°C D010A — 17 35 A 2.3 FOSC = 32kHz — 20 42 A 3.0 LP Oscillator mode, -40°C  TA  +125°C — 23 52 A 5.0 D011 — 70 105 A 1.8 FOSC = 1MHz XT Oscillator mode — 125 190 A 3.0 D011 — .125 170 A 2.3 FOSC = 1MHz XT Oscillator mode — 160 230 A 3.0 — 205 350 A 5.0 D012 — 155 240 A 1.8 FOSC = 4MHz XT Oscillator mode — 280 430 A 3.0 D012 — 230 450 A 2.3 FOSC = 4MHz XT Oscillator mode — 320 500 A 3.0 — 390 650 A 5.0 D013 — 16 31 A 1.8 FOSC = 500kHz EC Oscillator — 33 50 A 3.0 Low Power mode D013 — 32 47 A 2.3 FOSC = 500kHz EC Oscillator — 45 65 A 3.0 Low-Power mode — 50 70 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k  2012-2016 Microchip Technology Inc. DS40001624D-page 287

PIC16(L)F1512/3 TABLE 25-2: SUPPLY VOLTAGE (IDD)(1,2) (CONTINUED) PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) PIC16F1512/3 Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note D014 — 120 210 A 1.8 FOSC = 4MHz EC Oscillator, Medium-Power mode — 210 380 A 3.0 D014 — 190 280 A 2.3 FOSC = 4MHz EC Oscillator, Medium-Power mode — 260 380 A 3.0 — 330 480 A 5.0 D015 — 1.1 1.5 mA 3.0 FOSC = 20MHz EC Oscillator, High-Power mode — 1.3 2.0 mA 3.6 D015 — 1.2 1.5 mA 3.0 FOSC = 20MHz EC Oscillator, High-Power mode — 1.4 2 mA 5.0 D016 — 5.0 12 A 1.8 FOSC = 31kHz LFINTOSC mode — 10 31 A 3.0 D016 — 16 25 A 2.3 FOSC = 31kHz LFINTOSC mode — 22 35 A 3.0 — 23 40 A 5.0 D017 — 230 380 A 1.8 FOSC = 500kHz HFINTOSC mode — 275 450 A 3.0 D017 — 290 400 A 2.3 FOSC = 500kHz HFINTOSC mode — 335 480 A 3.0 — 365 530 A 5.0 D018 — 440 750 A 1.8 FOSC = 8MHz HFINTOSC mode — 700 1000 A 3.0 D018 — 580 750 A 2.3 FOSC = 8MHz HFINTOSC mode — 780 1000 A 3.0 — 810 1100 A 5.0 D019 — 0.65 1.3 mA 1.8 FOSC = 16MHz HFINTOSC mode — 1.1 1.5 mA 3.0 D019 — 0.80 1.3 mA 2.3 FOSC = 16MHz HFINTOSC mode — 1.1 1.5 mA 3.0 — 1.2 1.7 mA 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k DS40001624D-page 288  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 25-2: SUPPLY VOLTAGE (IDD)(1,2) (CONTINUED) PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) PIC16F1512/3 Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note D020 — 1.2 1.8 mA 3.0 FOSC = 20MHz HS Oscillator mode — 1.5 2.1 mA 3.6 D020 — 1.4 1.7 mA 3.0 FOSC = 20MHz HS Oscillator mode — 1.7 2.3 mA 5.0 D021 — 150 220 A 1.8 FOSC = 4MHz EXTRC mode (Note 3) — 250 380 A 3.0 D021 — 200 330 A 2.3 FOSC = 4MHz EXTRC mode (Note 3) — 280 420 A 3.0 — 350 500 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k  2012-2016 Microchip Technology Inc. DS40001624D-page 289

PIC16(L)F1512/3 TABLE 25-3: POWER-DOWN CURRENTS (IPD)(1,2,4) PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) PIC16F1512/3 Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note D022 — 0.02 1.0 8.0 A 1.8 WDT, BOR, FVR, and SOSC — 0.03 2.0 9.0 A 3.0 disabled, all Peripherals Inactive D022 — 0.20 3.0 11 A 2.3 WDT, BOR, FVR, and SOSC — 0.30 4.0 12 A 3.0 disabled, all Peripherals Inactive — 0.40 6 15 A 5.0 D023 — 0.30 6 14 A 1.8 LPWDT Current — 0.60 7 17 A 3.0 D023 — 0.50 6 15 A 2.3 LPWDT Current — 0.77 7 20 A 3.0 — 0.85 8 22 A 5.0 D023A — 10 28 30 A 1.8 FVR current — 12 30 33 A 3.0 D023A — 18 33 35 A 2.3 FVR current — 19 36 37 A 3.0 — 20 37 45 A 5.0 D024 — 8.0 17 20 A 3.0 BOR Current D024 — 8 17 30 A 3.0 BOR Current — 9 20 40 A 5.0 D024A — 0.80 4 8 A 3.0 LPBOR Current D024A — 0.30 4 14 A 3.0 LPBOR Current — 0.45 8 17 A 5.0 D025 — 0.6 5 9 A 1.8 SOSC Current — 2.5 8.5 12 A 3.0 D025 — 1 6 10 A 2.3 SOSC Current — 2.2 8.5 20 A 3.0 — 5.5 15 25 A 5.0 D026 — 0.1 1.5 9 A 1.8 A/D Current (Note 3), — 0.2 2.7 10 A 3.0 no conversion in progress D026 — 0.3 4 11 A 2.3 A/D Current (Note 3), — 0.35 5 13 A 3.0 no conversion in progress — 0.45 8 16 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: A/D oscillator source is FRC. 4: Specification for PIC16F1512/3 devices assumes that Low-Power Sleep mode is selected, when available, via the VREGCON register (see Section8.2.2 “Peripheral Usage in Sleep” and Register8-1). DS40001624D-page 290  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 25-3: POWER-DOWN CURRENTS (IPD)(1,2,4) (CONTINUED) PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) PIC16F1512/3 Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note D026A* — 250 400 410 A 1.8 A/D Current (Note 3), — 260 420 430 A 3.0 conversion in progress D026A* — 280 430 440 A 2.3 A/D Current (Note 3), — 300 450 460 A 3.0 conversion in progress — 320 470 480 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: A/D oscillator source is FRC. 4: Specification for PIC16F1512/3 devices assumes that Low-Power Sleep mode is selected, when available, via the VREGCON register (see Section8.2.2 “Peripheral Usage in Sleep” and Register8-1).  2012-2016 Microchip Technology Inc. DS40001624D-page 291

PIC16(L)F1512/3 TABLE 25-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage I/O PORT: D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V D030A — — 0.15VDD V 1.8V  VDD  4.5V D031 with Schmitt Trigger buffer — — 0.2VDD V 2.0V  VDD  5.5V with I2C levels — — 0.3VDD V with SMBus levels — — 0.8 V 2.7V  VDD  5.5V D032 MCLR, OSC1 (RC mode)(1) — — 0.2VDD V D033 OSC1 (HS mode) — — 0.3VDD V VIH Input High Voltage I/O ports: — — D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V D040A 0.25VDD + — — V 1.8V  VDD  4.5V 0.8 D041 with Schmitt Trigger buffer 0.8VDD — — V 2.0V  VDD  5.5V with I2C levels 0.7VDD — — V with SMBus levels 2.1 — — V 2.7V  VDD  5.5V D042 MCLR 0.8VDD — — V D043A OSC1 (HS mode) 0.7VDD — — V D043B OSC1 (RC mode) 0.9VDD — — V VDD  2.0V (Note 1) IIL Input Leakage Current(2) D060 I/O ports — ± 5 ± 125 nA VSS  VPIN  VDD, Pin at high- impedance at 85°C ± 5 ± 1000 nA 125°C D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD at 85°C IPUR Weak Pull-up Current D070* 25 100 200 VDD = 3.3V, VPIN = VSS 25 140 300 A VDD = 5.0V, VPIN = VSS VOL Output Low Voltage(4) D080 I/O ports IOL = 8 mA, VDD = 5V — — 0.6 V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V VOH Output High Voltage(4) D090 I/O ports IOH = 3.5 mA, VDD = 5V VDD - 0.7 — — V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode. DS40001624D-page 292  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 25-4: I/O PORTS (CONTINUED) Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode.  2012-2016 Microchip Technology Inc. DS40001624D-page 293

PIC16(L)F1512/3 TABLE 25-5: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP/RA5 pin 8.0 — 9.0 V (Note 2, Note 3) D111 IDDP Supply Current during Programming — — 10 mA D112 VBE VDD for Bulk Erase 2.7 — VDD V max. D113 VPEW VDD for Write or Row Erase VDD — VDD V min. max. D114 IPPPGM Current on MCLR/VPP during Erase/ — — 1.0 mA Write D115 IDDPGM Current on VDD during Erase/Write — 5.0 mA Program Flash Memory D121 EP Cell Endurance 10K — — E/W -40C to +85C (Note 1) D122 VPRW VDD for Read/Write VDD — VDD V min. max. D123 TIW Self-timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D125 EHEFC High-Endurance Flash Cell 100K — — E/W 0C  TA  +60°C, lower byte last 128 addresses † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Required only if single-supply programming is disabled. 3: The MPLAB® ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP voltage must be placed between the MPLAB ICD 2 and target system when programming or debugging with the MPLAB ICD 2. DS40001624D-page 294  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 25.4 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance Junction to Ambient 80 C/W 28-pin SOIC package 60 C/W 28-pin SPDIP package 90 C/W 28-pin SSOP package 27.5 C/W 28-pin UQFN package TH02 JC Thermal Resistance Junction to Case 24 C/W 28-pin SOIC package 31.4 C/W 28-pin SPDIP package 24 C/W 28-pin SSOP package 24 C/W 28-pin UQFN package TH03 TJMAX Maximum Junction Temperature 150 C TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Legend: TBD = To Be Determined Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature; TJ = Junction Temperature.  2012-2016 Microchip Technology Inc. DS40001624D-page 295

PIC16(L)F1512/3 25.5 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDIx sc SCKx do SDO ss SS dt Data in t0 T0CKI io I/O PORT t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 25-4: LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins DS40001624D-page 296  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 25-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS modes) OSC2/CLKOUT (CLKOUT mode) TABLE 25-6: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz EC Oscillator mode (low) DC — 4 MHz EC Oscillator mode (medium) DC — 20 MHz EC Oscillator mode (high) Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 4 MHz HS Oscillator mode 1 — 20 MHz HS Oscillator mode, VDD  2.7V DC — 4 MHz RC Oscillator mode, VDD  2.0V OS02 TOSC External CLKIN Period(1) 27 —  s LP Oscillator mode 250 —  ns XT Oscillator mode 50 —  ns HS Oscillator mode 50 —  ns EC Oscillator mode Oscillator Period(1) — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 125 — DC ns TCY = FOSC/4 OS04* TosH, External CLKIN High, 2 — — s LP oscillator TosL External CLKIN Low 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TosR, External CLKIN Rise, 0 —  ns LP oscillator TosF External CLKIN Fall 0 —  ns XT oscillator 0 —  ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.  2012-2016 Microchip Technology Inc. DS40001624D-page 297

PIC16(L)F1512/3 TABLE 25-7: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param Freq. Sym. Characteristic Min. Typ† Max. Units Conditions No. Tolerance OS08 HFOSC Internal Calibrated HFINTOSC ±2% — 16.0 — MHz VDD = 3.0V, TA = 25°C, Frequency(1) (Note 2) OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz (Note 3) OS10* TIOSC ST HFINTOSC — — 5 15 s Wake-up from Sleep Start-up Time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. 2: See Figure26-58: “HFINTOSC Accuracy Over Temperature, VDD = 1.8V, PIC16LF1512/3 Only”, and Figure26-59: “HFINTOSC Accuracy Over Temperature, 2.3V  VDD 5.5V”. 3: See Figure26-56: “LFINTOSC Frequency over VDD and Temperature, PIC16LF1512/3 Only”, and Figure26-57: “LFINTOSC Frequency over VDD and Temperature, PIC16F1512/3”. FIGURE 25-6: HFINTOSC FREQUENCY ACCURACY OVER VDD AND TEMPERATURE Rev.10-000135A 7/30/2013 125 ±12% 85 -4.5%to+7% C) (° 60 e ur at mper 25 ±4.5% e T 0 ±12% -40 1.8 2.3 5.5 VDD(V) Note: See Figure26-58: “HFINTOSC Accuracy Over Temperature, VDD = 1.8V, PIC16LF1512/3 Only”, and Figure26-59: “HFINTOSC Accuracy Over Temperature, 2.3V VDD  5.5V”. DS40001624D-page 298  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 25-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19 TABLE 25-8: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS11 TosH2ckL FOSC to CLKOUT (1) — — 70 ns VDD = 3.3-5.0V OS12 TosH2ckH FOSC to CLKOUT (1) — — 72 ns VDD = 3.3-5.0V OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3-5.0V OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns VDD = 3.3-5.0V (I/O in hold time) OS17 TioV2osH Port input valid to Fosc(Q2 cycle) 20 — — ns (I/O in setup time) OS18 TioR Port output rise time — 40 72 ns VDD = 1.8V — 15 32 VDD = 3.3-5.0V OS19 TioF Port output fall time — 28 55 ns VDD = 1.8V — 15 30 VDD = 3.3-5.0V OS20* Tinp INT pin input high or low time 25 — — ns OS21* Tioc Interrupt-on-change new input level time 25 — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.  2012-2016 Microchip Technology Inc. DS40001624D-page 299

PIC16(L)F1512/3 FIGURE 25-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 25-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’. 2ms delay if PWRTE = 0 and VREGEN=1. DS40001624D-page 300  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 25-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDTLP Low-Power Watchdog Timer 10 16 27 ms VDD = 3.3V-5V, Time-out Period 1:512 Prescaler used 32 TOST Oscillator Start-up Timer Period(1), (2) — 1024 — Tosc (Note 3) 33* TPWRT Power-up Timer Period, PWRTE=0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low or — — 2.0 s Watchdog Timer Reset 35 VBOR Brown-out Reset Voltage(4) 2.58 2.70 2.85 V BORV = 2.7V 2.35 2.45 2.57 V BORV = 2.45V for F devices only 1.80 1.9 2.11 V BORV = 1.9V for LF devices only 35A VLPBOR Low-Power Brown-out 1.8 2.1 2.5 V LPBOR = 1 36* VHYST Brown-out Reset Hysteresis 0 25 60 mV -40°C to +85°C 37* TBORDC Brown-out Reset DC Response Time 1 3 35 s VDD  VBOR * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended.  2012-2016 Microchip Technology Inc. DS40001624D-page 301

PIC16(L)F1512/3 FIGURE 25-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 TABLE 25-10: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Pres- 10 — — ns caler 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Pres- 10 — — ns caler 42* TT0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value Period 30 or TCY + 40 (1, 2, 4, 8) N Asynchronous 60 — — ns 48 FT1 Secondary Oscillator Input Frequency 32.4 32.76 33.1 kHz Range 8 (oscillator enabled by setting bit T1OSCEN) 49* TCKEZT- Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync MR1 Increment mode * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001624D-page 302  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 25-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP (Capture mode) CC01 CC02 CC03 Note: Refer to Figure25-4 for load conditions. TABLE 25-11: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. CC01* TccL CCP Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCP Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCP Input Period 3TCY + 40 — — ns N = prescale value (1, 4 or 16) N * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 25-12: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3) Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param Unit Sym. Characteristic Min. Typ† Max. Conditions No. s AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — — ±1.25 LSb VREF = 3.0V AD03 EDL Differential Error — — ±1 LSb No missing codes VREF = 3.0V AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V AD05 EGN Gain Error — — ±2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage(4) 1.8 — VDD V AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended Impedance of — — 10 k Analog Voltage Source * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input. 4: FVR voltage selected must be 2.048V or 4.096V.  2012-2016 Microchip Technology Inc. DS40001624D-page 303

PIC16(L)F1512/3 TABLE 25-13: A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD130* TAD A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal RC Oscillator 1.0 1.6 6.0 s ADCS<1:0> = 11 (ADRC mode) Period AD131 TCNV Conversion Time (not including — 11 — TAD Set GO/DONE bit to conversion Acquisition Time)(1) complete AD132* TACQ Acquisition Time — 5.0 — s * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. FIGURE 25-12: A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 (TOSC/2(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 7 6 5 4 3 2 1 0 ADRESx OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. DS40001624D-page 304  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 25-13: A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 7 6 5 4 3 2 1 0 ADRESx OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 25-14: LOW DROPOUT (LDO) REGULATOR CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. LD001 LDO Regulation Voltage — 3.4 — V LD002 LDO External Capacitor 0.1 — 1 F * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 25-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US120 US122 Note: Refer to Figure25-4 for load conditions.  2012-2016 Microchip Technology Inc. DS40001624D-page 305

PIC16(L)F1512/3 TABLE 25-15: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Max. Units Conditions No. US120* TCKH2DTV SYNC XMIT (Master and Slave) 3.0-5.5V — 80 ns Clock high to data-out valid 1.8-5.5V — 100 ns US121* TCKRF Clock out rise time and fall time 3.0-5.5V — 45 ns (Master mode) 1.8-5.5V — 50 ns US122* TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns FIGURE 25-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure25-4 for load conditions. TABLE 25-16: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Max. Units Conditions No. US125* TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK  (DT hold time) 10 — ns US126* TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns DS40001624D-page 306  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 25-16: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SCKx (CKP = 1) SP79 SP78 SP80 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure25-4 for load conditions. FIGURE 25-17: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SSx SP81 SCKx (CKP = 0) SP71 SP72 SP79 SP73 SCKx (CKP = 1) SP80 SP78 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure25-4 for load conditions.  2012-2016 Microchip Technology Inc. DS40001624D-page 307

PIC16(L)F1512/3 FIGURE 25-18: SPI SLAVE MODE TIMING (CKE=0) SSx SP70 SCKx SP83 (CKP = 0) SP71 SP72 SP78 SP79 SCKx (CKP = 1) SP79 SP78 SP80 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SP77 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure25-4 for load conditions. FIGURE 25-19: SPI SLAVE MODE TIMING (CKE=1) SP82 SSx SP70 SCKx SP83 (CKP = 0) SP71 SP72 SCKx (CKP = 1) SP80 SDOx MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure25-4 for load conditions. DS40001624D-page 308  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 25-17: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Symbol Characteristic Min. Typ† Max. Units Conditions No. SP70* TSSL2SCH, SSx to SCKx or SCKx input 2.25 — — TCY TSSL2SCL SP71* TSCH SCKx input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCKx input low time (Slave mode) TCY + 20 — — ns SP73* TDIV2SCH, Setup time of SDIx data input to SCKx edge 100 — — ns TDIV2SCL SP74* TSCH2DIL, Hold time of SDIx data input to SCKx edge 100 — — ns TSCL2DIL SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns 1.8-5.5V — 25 50 ns SP76* TDOF SDOx data output fall time — 10 25 ns SP77* TSSH2DOZ SSx to SDOx output high-impedance 10 — 50 ns SP78* TSCR SCKx output rise time 3.0-5.5V — 10 25 ns (Master mode) 1.8-5.5V — 25 50 ns SP79* TSCF SCKx output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, SDOx data output valid after SCKx 3.0-5.5V — — 50 ns TSCL2DOV edge 1.8-5.5V — — 145 ns SP81* TDOV2SCH, SDOx data output setup to SCKx edge Tcy — — ns TDOV2SCL SP82* TSSL2DOV SDOx data output valid after SS edge — — 50 ns SP83* TSCH2SSH, SSx after SCKx edge 1.5TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 25-20: I2C BUS START/STOP BITS TIMING SCLx SP91 SP93 SP90 SP92 SDAx Start Stop Condition Condition Note: Refer to Figure25-4 for load conditions.  2012-2016 Microchip Technology Inc. DS40001624D-page 309

PIC16(L)F1512/3 FIGURE 25-21: I2C BUS DATA TIMING SP103 SP100 SP102 SP101 SCLx SP90 SP106 SP107 SP91 SP92 SDAx In SP110 SP109 SP109 SDAx Out Note: Refer to Figure25-4 for load conditions. TABLE 25-18: I2C BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Unit Symbol Characteristic Min. Typ Max. Conditions No. s SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — Start condition SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first Hold time 400 kHz mode 600 — — clock pulse is generated SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. DS40001624D-page 310  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 TABLE 25-19: I2C BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Max. Units Conditions No. SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP module 1.5TCY — — SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP module 1.5TCY — — SP102* TR SDAx and SCLx rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF SP103* TF SDAx and SCLx fall 100 kHz mode — 250 ns time 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from 10-400 pF SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s SP107* TSU:DAT Data input setup time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start SP111 CB Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx signal, it must output the next data bit to the SDAx line TR max. + TSU:DAT=1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released.  2012-2016 Microchip Technology Inc. DS40001624D-page 311

PIC16(L)F1512/3 26.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.” represents (mean+3) or (mean-3) respectively, where  is a standard deviation, over each temperature range. DS40001624D-page 312  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-1: IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16LF1512/3 ONLY 30 25 Max: 85°C + 3(cid:305) Typical: 25°C 20 Max. A) (µ 15 DD Typical I 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 26-2: IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16F1512/3 ONLY 40 Max. Max: 85°C + 3(cid:305) 35 Typical: 25°C 30 Typical 25 A) (µ 20 D D I 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 313

PIC16(L)F1512/3 FIGURE 26-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1512/3 ONLY 400 350 Typical: 25°C 4 MHz XT 300 250 A) (µ 200 D D I 150 1 MHz XT 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 26-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1512/3 ONLY 450 400 Max: 85°C + 3(cid:305) 4 MHz XT 350 300 A) 250 µ ( D D 200 I 1 MHz XT 150 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) DS40001624D-page 314  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1512/3 ONLY 450 4 MHz XT 400 Typical: 25°C 350 4 MHz EXTRC 300 A) 250 1 MHz XT µ ( D 200 D I 150 100 1 MHz EXTRC 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 26-6: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1512/3 ONLY 500 4 MHz XT 450 Max: 85°C + 3(cid:305) 400 350 4 MHz EXTRC 300 1 MHz XT A) 250 µ ( D D 200 I 150 1 MHz EXTRC 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 315

PIC16(L)F1512/3 FIGURE 26-7: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC16LF1512/3 ONLY 25 Max. Max: 85°C + 3(cid:305) 20 Typical: 25°C 15 A) Typical µ ( D D I 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 26-8: IDD EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC16F1512/3 ONLY 35 Max. 30 Max: 85°C + 3(cid:305) Typical: 25°C 25 Typical A) 20 µ ( D D I 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001624D-page 316  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-9: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC16LF1512/3 ONLY 60 Max. Max: 85°C + 3(cid:305) 50 Typical: 25°C 40 A) Typical µ 30 ( D D I 20 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 26-10: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC16F1512/3 ONLY 70 Max. Max: 85°C + 3(cid:305) 60 Typical: 25°C Typical 50 A) 40 µ ( D D I 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 317

PIC16(L)F1512/3 FIGURE 26-11: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1512/3 ONLY 300 4 MHz 250 Typical: 25°C 200 A) µ 150 ( D D I 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 26-12: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1512/3 ONLY 350 300 Max: 85°C + 3(cid:305) 4 MHz 250 A) 200 µ ( D D 150 I 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) DS40001624D-page 318  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-13: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1512/3 ONLY 350 300 Typical: 25°C 4 MHz 250 A) 200 µ ( D D I 150 1 MHz 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 26-14: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1512/3 ONLY 400 350 Max: 85°C + 3(cid:305) 4 MHz 300 250 A) µ ( 200 D D 1 MHz I 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 319

PIC16(L)F1512/3 FIGURE 26-15: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16LF1512/3 ONLY 1.6 1.4 Typical: 25°C 20 MHz 1.2 1.0 16 MHz A) m 0.8 ( D D I 0.6 8 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 26-16: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16LF1512/3 ONLY 1.8 1.6 Max: 85°C + 3(cid:305) 20 MHz 1.4 1.2 16 MHz A) 1.0 m ( D 0.8 D I 0.6 8 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) DS40001624D-page 320  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-17: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16F1512/3 ONLY 1.6 20 MHz 1.4 Typical: 25°C 1.2 16 MHz 1.0 A) m 0.8 ( D 8 MHz D I 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 26-18: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16F1512/3 ONLY 1.8 1.6 Max: 85°C + 3(cid:305) 20 MHz 1.4 16 MHz 1.2 A) 1.0 m ( D 0.8 8 MHz D I 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 321

PIC16(L)F1512/3 FIGURE 26-19: IDD, LFINTOSC MODE, FOSC = 31 kHz, PIC16LF1512/3 ONLY 30 Max: 85°C + 3(cid:305) 25 Typical: 25°C Max. 20 A) µ ( D 15 Typical D I 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 26-20: IDD, LFINTOSC MODE, FOSC = 31 kHz, PIC16F1512/3 ONLY 35 Max. 30 25 Typical A) 20 µ ( D D I 15 10 Max: 85°C + 3(cid:305) 5 Typical: 25°C 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001624D-page 322  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-21: IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16LF1512/3 ONLY 350 Max. Max: 85°C + 3(cid:305) 300 Typical: 25°C Typical 250 A) µ ( D D I 200 150 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 26-22: IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16F1512/3 ONLY 450 Max. Max: 85°C + 3(cid:305) 400 Typical: 25°C Typical 350 A) 300 µ ( D D 250 I 200 150 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 323

PIC16(L)F1512/3 FIGURE 26-23: IDD TYPICAL, HFINTOSC MODE, PIC16LF1512/3 ONLY 1.4 16 MHz 1.2 Typical: 25°C 1.0 8 MHz A) 0.8 m ( D D 0.6 4 MHz I 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 26-24: IDD MAXIMUM, HFINTOSC MODE, PIC16LF1512/3 ONLY 1.6 16 MHz 1.4 Max: 85°C + 3(cid:305) 1.2 1.0 A) 8 MHz m ( 0.8 D D I 4 MHz 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) DS40001624D-page 324  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-25: IDD TYPICAL, HFINTOSC MODE, PIC16F1512/3 ONLY 1.4 16 MHz 1.2 Typical: 25°C 1.0 8 MHz 0.8 A) m ( 4 MHz D 0.6 D I 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 26-26: IDD MAXIMUM, HFINTOSC MODE, PIC16F1512/3 ONLY 1.6 16 MHz 1.4 Max: 85°C + 3(cid:305) 1.2 1.0 8 MHz A) m 0.8 (D 4 MHz D I 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 325

PIC16(L)F1512/3 FIGURE 26-27: IDD TYPICAL, HS OSCILLATOR, PIC16LF1512/3 ONLY 1.8 1.6 Typical: 25°C 20 MHz 1.4 1.2 A) 1 m ( 0.8 D ID 8 MHz 0.6 0.4 4 MHz 0.2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 26-28: IDD MAXIMUM, HS OSCILLATOR, PIC16LF1512/3 ONLY 2.0 1.8 Max: 85°C + 3(cid:305) 20 MHz 1.6 1.4 1.2 A) 1.0 m dd ( 0.8 8 MHz I 0.6 4 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) DS40001624D-page 326  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-29: IDD TYPICAL, HS OSCILLATOR, PIC16F1512/3 ONLY 2 1.8 Typical: 25°C 20 MHz 1.6 1.4 1.2 A) 1 m d ( 0.8 8 MHz d I 0.6 4 MHz 0.4 0.2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 26-30: IDD MAXIMUM, HS OSCILLATOR, PIC16F1512/3 ONLY 2.5 20 MHz 2.0 Max: 85°C + 3(cid:305) 1.5 A) m d ( 8 MHz d 1.0 I 4 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 327

PIC16(L)F1512/3 FIGURE 26-31: IPD BASE, LOW-POWER SLEEP MODE, PIC16LF1512/3 ONLY 445500 MMax: 8855°°CC + 33(cid:305) Max. 400 Typical: 25°C 350 300 A)A) 225500 nn (( DD P 200 I 150 100 Typical 50 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 26-32: IPD BASE, LOW-POWER SLEEP MODE, PIC16F1512/3 ONLY 660000 MMaaxx.. Max: 85°C + 3(cid:305) 500 Typical: 25°C 400 A)A) TTyyppiiccaall nn (( 330000 DD PP I 200 100 00 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001624D-page 328  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-33: IPD, WATCHDOG TIMER (WDT), PIC16LF1512/3 ONLY 11..44 Max: 85°C + 3(cid:305) 1.2 Typical: 25°C Max. 1.0 00.88 A)A TTyyppiiccaall µµ (( PDPD 00..66 II 0.4 0.2 00..00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 26-34: IPD, WATCHDOG TIMER (WDT), PIC16F1512/3 ONLY 11..44 1.2 Max: 85°C + 3(cid:305) Max. Typical: 25°C 1.0 A)A 0.8 Typical µµ (( DD IIPP 00..66 0.4 0.2 00..00 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 329

PIC16(L)F1512/3 FIGURE 26-35: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1512/3 ONLY 2255 MMaaxx.. 20 15 A)A µµ TTyyppiiccaall (( DD PP II 1100 Max: 85°C + 3(cid:305) 5 Typical: 25°C 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 26-36: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1512/3 ONLY 3300 25 Max. 20 A) Typical µµ (( 1155 DD PP II 10 5 Max: 85°C + 3(cid:305) Typical: 25°C 00 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001624D-page 330  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-37: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16LF1512/3 ONLY 1122 Max. Max: 85°C + 3(cid:305) 10 Typical: 25°C 8 Typical A)A) 66 µµ (( DD P I 4 2 00 11.66 11.88 22.00 22.22 22.44 22.66 22.88 33.00 33.22 33.44 33.66 33.88 VDD(V) FIGURE 26-38: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16F1512/3 ONLY 1144 MMaaxx. MMaax: 8855°°CC ++ 33(cid:305)(cid:305) 12 Typical: 25°C 10 Typical 8 A)A) µµ (( DD 66 PP II 4 2 00 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 331

PIC16(L)F1512/3 FIGURE 26-39: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16LF1512/3 ONLY 66..00 Max: 85°C + 3(cid:305) 5.0 Typical: 25°C Max. 4.0 A)A µµ 33..00 (( DD PP II TTyyppiiccaall 2.0 1.0 00..00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 26-40: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16F1512/3 ONLY 1122 Max: 85°C + 3(cid:305) 10 Typical: 25°C Max. 8 A) ((µµ 66 TTyyppiiccaall DD PP II 4 2 00 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001624D-page 332  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-41: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V, PIC16F1512/3 ONLY 6 5 4 V) (H 3 O V 125°C Typical 2 -40°C Graph represents 1 3(cid:305)Limits 0 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 IOH(mA) FIGURE 26-42: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V, PIC16F1512/3 ONLY 5 125°C Graph represents 4 3(cid:305)Limits 3 V) ( L O Typical V 2 -40°C 1 0 0 10 20 30 40 50 60 70 80 90 100 IOL(mA)  2012-2016 Microchip Technology Inc. DS40001624D-page 333

PIC16(L)F1512/3 FIGURE 26-43: VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V 3.5 Graph represents 3.0 3(cid:305)Limits 2.5 V) 2.0 ( H O 125°C V 1.5 Typical 1.0 -40°C 0.5 0.0 -15 -13 -11 -9 -7 -5 -3 -1 IOH(mA) FIGURE 26-44: VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V 3.0 125°C Graph represents 2.5 3(cid:305)Limits Typical 2.0 -40°C V) ( 1.5 L O V 1.0 0.5 0.0 0 5 10 15 20 25 30 35 40 IOL(mA) DS40001624D-page 334  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-45: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V, PIC16LF1512/3 ONLY 2.0 Graph represents 1.8 3(cid:305)Limits 1.6 1.4 125°C 1.2 V) (H 1.0 O Typical V 0.8 0.6 -40°C 0.4 0.2 0.0 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 IOH(mA) FIGURE 26-46: VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V, PIC16LF1512/3 ONLY 1.8 Graph represents 1.6 3(cid:305)Limits 1.4 125°C 1.2 Typical V) 1.0 ( L -40°C VO 0.8 0.6 0.4 0.2 0.0 0 1 2 3 4 5 6 7 8 9 10 IOL(mA)  2012-2016 Microchip Technology Inc. DS40001624D-page 335

PIC16(L)F1512/3 FIGURE 26-47: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 1.64 Typical ) 1.62 V ge ( 1.60 Min. a t ol 1.58 V 1.56 1.54 Max: Typical + 3(cid:305) Typical: 25°C 1.52 Min: Typical -3(cid:305) 1.50 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 26-48: POR REARM VOLTAGE, PIC16F1512/3 ONLY 1.54 1.52 Max: Typical + 3(cid:305) Typical: 25°C 1.50 Min: Typical -3(cid:305) Max. 1.48 ) 1.46 V e ( g 1.44 a Typical t ol 1.42 V 1.40 Min. 1.38 1.36 1.34 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) DS40001624D-page 336  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-49: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16LF1512/3 ONLY 2.00 Max. 1.95 ) V ge ( 1.90 Typical a t ol V 1.85 Min. Max: Typical + 3(cid:305) Min: Typical -3(cid:305) 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 26-50: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16F1512/3 ONLY 2.60 2.55 Max. 2.50 ) Typical V ge ( 2.45 a t ol V Min. 2.40 Max: Typical + 3(cid:305) 2.35 Min: Typical -3(cid:305) 2.30 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C)  2012-2016 Microchip Technology Inc. DS40001624D-page 337

PIC16(L)F1512/3 FIGURE 26-51: BROWN-OUT RESET VOLTAGE, BORV = 0 2.80 2.75 Max. ) 2.70 V e ( Typical g a t ol 2.65 V Min. Max: Typical + 3(cid:305) 2.60 Min: Typical -3(cid:305) 2.55 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 26-52: LOW-POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0 2.50 Max. Max: Typical + 3(cid:305) 2.40 Min: Typical -3(cid:305) 2.30 Typical ) V 2.20 e ( g a olt 2.10 V 2.00 Min. 1.90 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) DS40001624D-page 338  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-53: WDT TIME-OUT PERIOD 24 22 Max. 20 ) s 18 m Typical e ( m 16 Ti Min. 14 Max: Typical + 3(cid:305)(-40°C to +125°C) 12 Typical: statistical mean @ 25°C Min: Typical -3(cid:305)(-40°C to +125°C) 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 26-54: PWRT PERIOD 100 Max: Typical + 3(cid:305)(-40°C to +125°C) Typical: statistical mean @ 25°C 90 Min: Typical -3(cid:305)(-40°C to +125°C) Max. 80 ) s m e ( 70 Typical m Ti 60 Min. 50 40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 339

PIC16(L)F1512/3 FIGURE 26-55: FVR STABILIZATION PERIOD, PIC16LF1512/3 ONLY 40 Max: Typical + 3(cid:305) 35 Max. Typical: statistical mean @ 25°C 30 Typical 25 ) s u e ( 20 m Ti 15 Note: 10 The FVR Stabiliztion Period applies when coming out of RESET or exiting sleep mode. 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) DS40001624D-page 340  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 FIGURE 26-56: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16LF1512/3 ONLY 36 34 Max. 32 30 ) Typical z H (k 28 y c n e 26 Min. u q e Fr 24 Max: Typical + 3(cid:305)(-40°C to +125°C) 22 Typical: statistical mean @ 25°C Min: Typical -3(cid:305)(-40°C to +125°C) 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 26-57: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16F1512/3 ONLY 36 34 Max. 32 30 z) Typical H k ( 28 y c n ue 26 Min. q e r F 24 Max: Typical + 3(cid:305)(-40°C to +125°C) 22 Typical: statistical mean @ 25°C Min: Typical -3(cid:305)(-40°C to +125°C) 20 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD(V)  2012-2016 Microchip Technology Inc. DS40001624D-page 341

PIC16(L)F1512/3 FIGURE 26-58: HFINTOSC ACCURACY OVER TEMPERATURE, VDD = 1.8V, PIC16LF1512/3 ONLY 8% 6% Max: Typical + 3(cid:305) Typical: statistical mean Max. 4% Min: Typical -3(cid:305) 2% %) ( cy 0% Typical a r u -2% c c A -4% -6% Min. -8% -10% -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 26-59: HFINTOSC ACCURACY OVER TEMPERATURE, 2.3V  VDD 5.5V 8% 6% Max: Typical + 3(cid:305) Typical: statistical mean 4% Min: Typical -3(cid:305) Max. %) 2% ( Typical y c 0% a r u c -2% Min. c A -4% -6% -8% -10% -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) DS40001624D-page 342  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 27.0 DEVELOPMENT SUPPORT 27.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2012-2016 Microchip Technology Inc. DS40001624D-page 343

PIC16(L)F1512/3 27.2 MPLAB XC Compilers 27.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 27.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 27.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001624D-page 344  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 27.6 MPLAB X SIM Software Simulator 27.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 27.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 27.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 27.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2012-2016 Microchip Technology Inc. DS40001624D-page 345

PIC16(L)F1512/3 27.11 Demonstration/Development 27.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001624D-page 346  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX PIC16F1512-E/SO XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 1110017 28-Lead SPDIP (.300”) Example PIC16F1512-E/SP 1110017 28-Lead SSOP (5.30 mm) Example PIC16F1512-E/SS e3 1110017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2012-2016 Microchip Technology Inc. DS40001624D-page 347

PIC16(L)F1512/3 Package Marking Information (Continued) 28-Lead UQFN (4x4x0.5 mm) Example PIC16 PIN 1 PIN 1 F1513 I/ML e3 110017 DS40001624D-page 348  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 28.2 Package Details The following sections give the technical details of the packages. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2016 Microchip Technology Inc. DS40001624D-page 349

PIC16(L)F1512/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001624D-page 350  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2016 Microchip Technology Inc. DS40001624D-page 351

PIC16(L)F1512/3 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)(cid:26)(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 5(cid:11)(cid:10)(cid:3)((cid:12)(cid:15)(cid:3))(cid:11)#((cid:3)(cid:9)$(cid:10)(cid:10)(cid:15)(cid:16)((cid:3)(cid:13)(cid:29)(cid:9)6(cid:29)(cid:18)(cid:15)(cid:3)%(cid:10)(cid:29),(cid:8)(cid:16)(cid:18)#*(cid:3)(cid:13)(cid:17)(cid:15)(cid:29)#(cid:15)(cid:3)#(cid:15)(cid:15)(cid:3)((cid:12)(cid:15)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:3)!(cid:29)(cid:9)6(cid:29)(cid:18)(cid:8)(cid:16)(cid:18)(cid:3)(cid:23)(cid:13)(cid:15)(cid:9)(cid:8)’(cid:8)(cid:9)(cid:29)((cid:8)(cid:11)(cid:16)(cid:3)(cid:17)(cid:11)(cid:9)(cid:29)((cid:15)%(cid:3)(cid:29)((cid:3) (cid:12)(((cid:13)477,,,(cid:21))(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:21)(cid:9)(cid:11))7(cid:13)(cid:29)(cid:9)6(cid:29)(cid:18)(cid:8)(cid:16)(cid:18) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 8(cid:16)(cid:8)(# (cid:20)9.:0(cid:23) (cid:22)(cid:8))(cid:15)(cid:16)#(cid:8)(cid:11)(cid:16)(cid:3);(cid:8))(cid:8)(# (cid:7)(cid:20)9 9<(cid:7) (cid:7)(cid:26)= 9$)+(cid:15)(cid:10)(cid:3)(cid:11)’(cid:3)!(cid:8)(cid:16)# 9 (cid:4)> !(cid:8)((cid:9)(cid:12) (cid:15) (cid:21)(cid:31)(cid:5)(cid:5)(cid:3)3(cid:23). (cid:14)(cid:11)(cid:13)(cid:3)((cid:11)(cid:3)(cid:23)(cid:15)(cid:29)((cid:8)(cid:16)(cid:18)(cid:3)!(cid:17)(cid:29)(cid:16)(cid:15) (cid:26) ? ? (cid:21)(cid:4)(cid:5)(cid:5) (cid:7)(cid:11)(cid:17)%(cid:15)%(cid:3)!(cid:29)(cid:9)6(cid:29)(cid:18)(cid:15)(cid:3)(cid:14)(cid:12)(cid:8)(cid:9)6(cid:16)(cid:15)## (cid:26)(cid:4) (cid:21)(cid:31)(cid:4)(cid:5) (cid:21)(cid:31)/(cid:30) (cid:21)(cid:31)(cid:30)(cid:5) 3(cid:29)#(cid:15)(cid:3)((cid:11)(cid:3)(cid:23)(cid:15)(cid:29)((cid:8)(cid:16)(cid:18)(cid:3)!(cid:17)(cid:29)(cid:16)(cid:15) (cid:26)(cid:31) (cid:21)(cid:5)(cid:31)(cid:30) ? ? (cid:23)(cid:12)(cid:11)$(cid:17)%(cid:15)(cid:10)(cid:3)((cid:11)(cid:3)(cid:23)(cid:12)(cid:11)$(cid:17)%(cid:15)(cid:10)(cid:3)@(cid:8)%((cid:12) 0 (cid:21)(cid:4)(cid:25)(cid:5) (cid:21)/(cid:31)(cid:5) (cid:21)//(cid:30) (cid:7)(cid:11)(cid:17)%(cid:15)%(cid:3)!(cid:29)(cid:9)6(cid:29)(cid:18)(cid:15)(cid:3)@(cid:8)%((cid:12) 0(cid:31) (cid:21)(cid:4)(cid:24)(cid:5) (cid:21)(cid:4)>(cid:30) (cid:21)(cid:4)(cid:25)(cid:30) <"(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3);(cid:15)(cid:16)(cid:18)((cid:12) (cid:22) (cid:31)(cid:21)/(cid:24)(cid:30) (cid:31)(cid:21)/B(cid:30) (cid:31)(cid:21)(cid:24)(cid:5)(cid:5) (cid:14)(cid:8)(cid:13)(cid:3)((cid:11)(cid:3)(cid:23)(cid:15)(cid:29)((cid:8)(cid:16)(cid:18)(cid:3)!(cid:17)(cid:29)(cid:16)(cid:15) ; (cid:21)(cid:31)(cid:31)(cid:5) (cid:21)(cid:31)/(cid:5) (cid:21)(cid:31)(cid:30)(cid:5) ;(cid:15)(cid:29)%(cid:3)(cid:14)(cid:12)(cid:8)(cid:9)6(cid:16)(cid:15)## (cid:9) (cid:21)(cid:5)(cid:5)> (cid:21)(cid:5)(cid:31)(cid:5) (cid:21)(cid:5)(cid:31)(cid:30) 8(cid:13)(cid:13)(cid:15)(cid:10)(cid:3);(cid:15)(cid:29)%(cid:3)@(cid:8)%((cid:12) +(cid:31) (cid:21)(cid:5)(cid:24)(cid:5) (cid:21)(cid:5)(cid:30)(cid:5) (cid:21)(cid:5)(cid:6)(cid:5) ;(cid:11),(cid:15)(cid:10)(cid:3);(cid:15)(cid:29)%(cid:3)@(cid:8)%((cid:12) + (cid:21)(cid:5)(cid:31)(cid:24) (cid:21)(cid:5)(cid:31)> (cid:21)(cid:5)(cid:4)(cid:4) <"(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3)(cid:27)(cid:11),(cid:3)(cid:23)(cid:13)(cid:29)(cid:9)(cid:8)(cid:16)(cid:18)(cid:3)(cid:3)- (cid:15)3 ? ? (cid:21)(cid:24)/(cid:5) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:31)(cid:21) !(cid:8)(cid:16)(cid:3)(cid:31)(cid:3)"(cid:8)#$(cid:29)(cid:17)(cid:3)(cid:8)(cid:16)%(cid:15)&(cid:3)’(cid:15)(cid:29)($(cid:10)(cid:15)(cid:3))(cid:29)(cid:19)(cid:3)"(cid:29)(cid:10)(cid:19)*(cid:3)+$((cid:3))$#((cid:3)+(cid:15)(cid:3)(cid:17)(cid:11)(cid:9)(cid:29)((cid:15)%(cid:3),(cid:8)((cid:12)(cid:8)(cid:16)(cid:3)((cid:12)(cid:15)(cid:3)(cid:12)(cid:29)((cid:9)(cid:12)(cid:15)%(cid:3)(cid:29)(cid:10)(cid:15)(cid:29)(cid:21) (cid:4)(cid:21) -(cid:3)(cid:23)(cid:8)(cid:18)(cid:16)(cid:8)’(cid:8)(cid:9)(cid:29)(cid:16)((cid:3).(cid:12)(cid:29)(cid:10)(cid:29)(cid:9)((cid:15)(cid:10)(cid:8)#((cid:8)(cid:9)(cid:21) /(cid:21) (cid:22)(cid:8))(cid:15)(cid:16)#(cid:8)(cid:11)(cid:16)#(cid:3)(cid:22)(cid:3)(cid:29)(cid:16)%(cid:3)0(cid:31)(cid:3)%(cid:11)(cid:3)(cid:16)(cid:11)((cid:3)(cid:8)(cid:16)(cid:9)(cid:17)$%(cid:15)(cid:3))(cid:11)(cid:17)%(cid:3)’(cid:17)(cid:29)#(cid:12)(cid:3)(cid:11)(cid:10)(cid:3)(cid:13)(cid:10)(cid:11)((cid:10)$#(cid:8)(cid:11)(cid:16)#(cid:21)(cid:3)(cid:7)(cid:11)(cid:17)%(cid:3)’(cid:17)(cid:29)#(cid:12)(cid:3)(cid:11)(cid:10)(cid:3)(cid:13)(cid:10)(cid:11)((cid:10)$#(cid:8)(cid:11)(cid:16)#(cid:3)#(cid:12)(cid:29)(cid:17)(cid:17)(cid:3)(cid:16)(cid:11)((cid:3)(cid:15)&(cid:9)(cid:15)(cid:15)%(cid:3)(cid:21)(cid:5)(cid:31)(cid:5)1(cid:3)(cid:13)(cid:15)(cid:10)(cid:3)#(cid:8)%(cid:15)(cid:21) (cid:24)(cid:21) (cid:22)(cid:8))(cid:15)(cid:16)#(cid:8)(cid:11)(cid:16)(cid:8)(cid:16)(cid:18)(cid:3)(cid:29)(cid:16)%(cid:3)((cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:8)(cid:16)(cid:18)(cid:3)(cid:13)(cid:15)(cid:10)(cid:3)(cid:26)(cid:23)(cid:7)0(cid:3)2(cid:31)(cid:24)(cid:21)(cid:30)(cid:7)(cid:21) 3(cid:23).4 3(cid:29)#(cid:8)(cid:9)(cid:3)(cid:22)(cid:8))(cid:15)(cid:16)#(cid:8)(cid:11)(cid:16)(cid:21)(cid:3)(cid:14)(cid:12)(cid:15)(cid:11)(cid:10)(cid:15)((cid:8)(cid:9)(cid:29)(cid:17)(cid:17)(cid:19)(cid:3)(cid:15)&(cid:29)(cid:9)((cid:3)"(cid:29)(cid:17)$(cid:15)(cid:3)#(cid:12)(cid:11),(cid:16)(cid:3),(cid:8)((cid:12)(cid:11)$((cid:3)((cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:15)#(cid:21) (cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:14)(cid:15)(cid:9)(cid:12)(cid:16)(cid:11)(cid:17)(cid:11)(cid:18)(cid:19)(cid:22)(cid:10)(cid:29),(cid:8)(cid:16)(cid:18).(cid:5)(cid:24)(cid:28)(cid:5)(cid:6)(cid:5)3 DS40001624D-page 352  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)#$(cid:12)(cid:13)(cid:11)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)%(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:10)(cid:24)(cid:9)(cid:25)(cid:9)&’(cid:26)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:10)%(cid:15) !(cid:30)(cid:18)(cid:6)" 5(cid:11)(cid:10)(cid:3)((cid:12)(cid:15)(cid:3))(cid:11)#((cid:3)(cid:9)$(cid:10)(cid:10)(cid:15)(cid:16)((cid:3)(cid:13)(cid:29)(cid:9)6(cid:29)(cid:18)(cid:15)(cid:3)%(cid:10)(cid:29),(cid:8)(cid:16)(cid:18)#*(cid:3)(cid:13)(cid:17)(cid:15)(cid:29)#(cid:15)(cid:3)#(cid:15)(cid:15)(cid:3)((cid:12)(cid:15)(cid:3)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:3)!(cid:29)(cid:9)6(cid:29)(cid:18)(cid:8)(cid:16)(cid:18)(cid:3)(cid:23)(cid:13)(cid:15)(cid:9)(cid:8)’(cid:8)(cid:9)(cid:29)((cid:8)(cid:11)(cid:16)(cid:3)(cid:17)(cid:11)(cid:9)(cid:29)((cid:15)%(cid:3)(cid:29)((cid:3) (cid:12)(((cid:13)477,,,(cid:21))(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:21)(cid:9)(cid:11))7(cid:13)(cid:29)(cid:9)6(cid:29)(cid:18)(cid:8)(cid:16)(cid:18) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 8(cid:16)(cid:8)(# (cid:7)(cid:20);;(cid:20)(cid:7)0(cid:14)0(cid:27)(cid:23) (cid:22)(cid:8))(cid:15)(cid:16)#(cid:8)(cid:11)(cid:16)(cid:3);(cid:8))(cid:8)(# (cid:7)(cid:20)9 9<(cid:7) (cid:7)(cid:26)= 9$)+(cid:15)(cid:10)(cid:3)(cid:11)’(cid:3)!(cid:8)(cid:16)# 9 (cid:4)> !(cid:8)((cid:9)(cid:12) (cid:15) (cid:5)(cid:21)B(cid:30)(cid:3)3(cid:23). <"(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3):(cid:15)(cid:8)(cid:18)(cid:12)( (cid:26) ? ? (cid:4)(cid:21)(cid:5)(cid:5) (cid:7)(cid:11)(cid:17)%(cid:15)%(cid:3)!(cid:29)(cid:9)6(cid:29)(cid:18)(cid:15)(cid:3)(cid:14)(cid:12)(cid:8)(cid:9)6(cid:16)(cid:15)## (cid:26)(cid:4) (cid:31)(cid:21)B(cid:30) (cid:31)(cid:21)(cid:6)(cid:30) (cid:31)(cid:21)>(cid:30) (cid:23)((cid:29)(cid:16)%(cid:11)’’(cid:3) (cid:26)(cid:31) (cid:5)(cid:21)(cid:5)(cid:30) ? ? <"(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3)@(cid:8)%((cid:12) 0 (cid:6)(cid:21)(cid:24)(cid:5) (cid:6)(cid:21)>(cid:5) >(cid:21)(cid:4)(cid:5) (cid:7)(cid:11)(cid:17)%(cid:15)%(cid:3)!(cid:29)(cid:9)6(cid:29)(cid:18)(cid:15)(cid:3)@(cid:8)%((cid:12) 0(cid:31) (cid:30)(cid:21)(cid:5)(cid:5) (cid:30)(cid:21)/(cid:5) (cid:30)(cid:21)B(cid:5) <"(cid:15)(cid:10)(cid:29)(cid:17)(cid:17)(cid:3);(cid:15)(cid:16)(cid:18)((cid:12) (cid:22) (cid:25)(cid:21)(cid:25)(cid:5) (cid:31)(cid:5)(cid:21)(cid:4)(cid:5) (cid:31)(cid:5)(cid:21)(cid:30)(cid:5) 5(cid:11)(cid:11)((cid:3);(cid:15)(cid:16)(cid:18)((cid:12) ; (cid:5)(cid:21)(cid:30)(cid:30) (cid:5)(cid:21)(cid:6)(cid:30) (cid:5)(cid:21)(cid:25)(cid:30) 5(cid:11)(cid:11)((cid:13)(cid:10)(cid:8)(cid:16)( ;(cid:31) (cid:31)(cid:21)(cid:4)(cid:30)(cid:3)(cid:27)05 ;(cid:15)(cid:29)%(cid:3)(cid:14)(cid:12)(cid:8)(cid:9)6(cid:16)(cid:15)## (cid:9) (cid:5)(cid:21)(cid:5)(cid:25) ? (cid:5)(cid:21)(cid:4)(cid:30) 5(cid:11)(cid:11)((cid:3)(cid:26)(cid:16)(cid:18)(cid:17)(cid:15) (cid:3) (cid:5)D (cid:24)D >D ;(cid:15)(cid:29)%(cid:3)@(cid:8)%((cid:12) + (cid:5)(cid:21)(cid:4)(cid:4) ? (cid:5)(cid:21)/> !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:31)(cid:21) !(cid:8)(cid:16)(cid:3)(cid:31)(cid:3)"(cid:8)#$(cid:29)(cid:17)(cid:3)(cid:8)(cid:16)%(cid:15)&(cid:3)’(cid:15)(cid:29)($(cid:10)(cid:15)(cid:3))(cid:29)(cid:19)(cid:3)"(cid:29)(cid:10)(cid:19)*(cid:3)+$((cid:3))$#((cid:3)+(cid:15)(cid:3)(cid:17)(cid:11)(cid:9)(cid:29)((cid:15)%(cid:3),(cid:8)((cid:12)(cid:8)(cid:16)(cid:3)((cid:12)(cid:15)(cid:3)(cid:12)(cid:29)((cid:9)(cid:12)(cid:15)%(cid:3)(cid:29)(cid:10)(cid:15)(cid:29)(cid:21) (cid:4)(cid:21) (cid:22)(cid:8))(cid:15)(cid:16)#(cid:8)(cid:11)(cid:16)#(cid:3)(cid:22)(cid:3)(cid:29)(cid:16)%(cid:3)0(cid:31)(cid:3)%(cid:11)(cid:3)(cid:16)(cid:11)((cid:3)(cid:8)(cid:16)(cid:9)(cid:17)$%(cid:15)(cid:3))(cid:11)(cid:17)%(cid:3)’(cid:17)(cid:29)#(cid:12)(cid:3)(cid:11)(cid:10)(cid:3)(cid:13)(cid:10)(cid:11)((cid:10)$#(cid:8)(cid:11)(cid:16)#(cid:21)(cid:3)(cid:7)(cid:11)(cid:17)%(cid:3)’(cid:17)(cid:29)#(cid:12)(cid:3)(cid:11)(cid:10)(cid:3)(cid:13)(cid:10)(cid:11)((cid:10)$#(cid:8)(cid:11)(cid:16)#(cid:3)#(cid:12)(cid:29)(cid:17)(cid:17)(cid:3)(cid:16)(cid:11)((cid:3)(cid:15)&(cid:9)(cid:15)(cid:15)%(cid:3)(cid:5)(cid:21)(cid:4)(cid:5)(cid:3)))(cid:3)(cid:13)(cid:15)(cid:10)(cid:3)#(cid:8)%(cid:15)(cid:21) /(cid:21) (cid:22)(cid:8))(cid:15)(cid:16)#(cid:8)(cid:11)(cid:16)(cid:8)(cid:16)(cid:18)(cid:3)(cid:29)(cid:16)%(cid:3)((cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:8)(cid:16)(cid:18)(cid:3)(cid:13)(cid:15)(cid:10)(cid:3)(cid:26)(cid:23)(cid:7)0(cid:3)2(cid:31)(cid:24)(cid:21)(cid:30)(cid:7)(cid:21) 3(cid:23).4 3(cid:29)#(cid:8)(cid:9)(cid:3)(cid:22)(cid:8))(cid:15)(cid:16)#(cid:8)(cid:11)(cid:16)(cid:21)(cid:3)(cid:14)(cid:12)(cid:15)(cid:11)(cid:10)(cid:15)((cid:8)(cid:9)(cid:29)(cid:17)(cid:17)(cid:19)(cid:3)(cid:15)&(cid:29)(cid:9)((cid:3)"(cid:29)(cid:17)$(cid:15)(cid:3)#(cid:12)(cid:11),(cid:16)(cid:3),(cid:8)((cid:12)(cid:11)$((cid:3)((cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:15)#(cid:21) (cid:27)054 (cid:27)(cid:15)’(cid:15)(cid:10)(cid:15)(cid:16)(cid:9)(cid:15)(cid:3)(cid:22)(cid:8))(cid:15)(cid:16)#(cid:8)(cid:11)(cid:16)*(cid:3)$#$(cid:29)(cid:17)(cid:17)(cid:19)(cid:3),(cid:8)((cid:12)(cid:11)$((cid:3)((cid:11)(cid:17)(cid:15)(cid:10)(cid:29)(cid:16)(cid:9)(cid:15)*(cid:3)’(cid:11)(cid:10)(cid:3)(cid:8)(cid:16)’(cid:11)(cid:10))(cid:29)((cid:8)(cid:11)(cid:16)(cid:3)(cid:13)$(cid:10)(cid:13)(cid:11)#(cid:15)#(cid:3)(cid:11)(cid:16)(cid:17)(cid:19)(cid:21) (cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:9)(cid:12)(cid:8)(cid:13)(cid:14)(cid:15)(cid:9)(cid:12)(cid:16)(cid:11)(cid:17)(cid:11)(cid:18)(cid:19)(cid:22)(cid:10)(cid:29),(cid:8)(cid:16)(cid:18).(cid:5)(cid:24)(cid:28)(cid:5)(cid:6)/3  2012-2016 Microchip Technology Inc. DS40001624D-page 353

PIC16(L)F1512/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001624D-page 354  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2016 Microchip Technology Inc. DS40001624D-page 355

PIC16(L)F1512/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001624D-page 356  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3  2012-2016 Microchip Technology Inc. DS40001624D-page 357

PIC16(L)F1512/3 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (02/2012) Original release (02/2012) Revision B (06/2012) Updated Figure 16-1; Removed Figure 16-8; Added new Figure 16-8; Replaced Figures 16-9 and 16-10; Added Note 1 to Figure 16-12; Added Note 3 to Register 16-1; Added Note 4 to Register 16-7; Updated the Electrical Specifications section; Other minor corrections. Revision C (03/2014) Updated Table 3-1; Updated Table 5-1; Updated Table 11-1; Added paragraph to Section 14.1; Updated Equation 16-1; Updated Section 16.5 Hardware Capacitive Voltage Divider (CVD) Module; Updated Section 22.2; Updated the Electrical Specifications section; Added Characterization Graphs; Other minor corrections. Revision D (07/2016) Updated the Family Type Table and added the Memory Section; Other minor corrections. DS40001624D-page 358  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Product Support – Data sheets and errata, • Technical Support application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or Field Application Engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the website program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2012-2016 Microchip Technology Inc. DS40001624D-page 359

PIC16(L)F1512/3 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) - X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC16F1512T - I/SO 301 Option Range Tape and Reel, Industrial temperature, SOIC package b) PIC16F1512 - I/P Device: PIC16F1512, PIC16LF1512 Industrial temperature PIC16F1513, PIC16LF1513 PDIP package c) PIC16F1513 - E/SS Extended temperature, Tape and Reel Blank = Standard packaging (tube or tray) SSOP package Option: T = Tape and Reel(1) Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Package: MV = Micro Lead Frame (UQFN) 4x4 P = Plastic DIP (PDIP) Note1: Tape and Reel identifier only appears in the SO = SOIC catalog part number description. This SP = Skinny Plastic DIP (SPDIP) identifier is used for ordering purposes and is SS = SSOP not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) DS40001624D-page 360  2012-2016 Microchip Technology Inc.

PIC16(L)F1512/3 NOTES:  2012-2016 Microchip Technology Inc. DS40001624D-page 361

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, and may be superseded by updates. It is your responsibility to dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, ensure that your application meets with your specifications. KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MICROCHIP MAKES NO REPRESENTATIONS OR MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, WARRANTIES OF ANY KIND WHETHER EXPRESS OR RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O IMPLIED, WRITTEN OR ORAL, STATUTORY OR are registered trademarks of Microchip Technology OTHERWISE, RELATED TO THE INFORMATION, Incorporated in the U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR ClockWorks, The Embedded Control Solutions Company, FITNESS FOR PURPOSE. Microchip disclaims all liability ETHERSYNCH, Hyper Speed Control, HyperLight Load, arising from this information and its use. Use of Microchip IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are devices in life support and/or safety applications is entirely at registered trademarks of Microchip Technology Incorporated the buyer’s risk, and the buyer agrees to defend, indemnify and in the U.S.A. hold harmless Microchip from any and all damages, claims, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, suits, or expenses resulting from such use. No licenses are BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, conveyed, implicitly or otherwise, under any Microchip dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, intellectual property rights unless otherwise stated. EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of Tempe, Arizona; Gresham, Oregon and design centers in California Microchip Technology Inc. in other countries. and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademark of Microchip Technology devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. QUALITY MANAGEMENT SYSTEM © 2012-2016, Microchip Technology Incorporated, Printed in CERTIFIED BY DNV the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0763-8 == ISO/TS 16949 == DS40001624D-page 362  2012-2016 Microchip Technology Inc.

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16F1512T-I/SO PIC16F1513T-I/SO PIC16LF1512T-I/SO PIC16LF1513T-I/SO PIC16F1512-I/SO PIC16F1513- E/SO PIC16F1513-I/SO PIC16LF1512-E/SO PIC16LF1512-I/SO PIC16LF1513-E/SO PIC16LF1513-I/SO PIC16F1512-E/SP PIC16F1512-I/SP PIC16F1513-E/SP PIC16F1513-I/SP PIC16LF1512-E/SP PIC16LF1512-I/SP PIC16LF1513-E/SP PIC16LF1513-I/SP PIC16F1512T-I/SS PIC16F1513T-I/SS PIC16LF1512T-I/SS PIC16LF1513T- I/SS PIC16F1512-E/SS PIC16F1512-I/SS PIC16F1513-E/SS PIC16F1513-I/SS PIC16LF1512-E/SS PIC16LF1512- I/SS PIC16LF1513-E/SS PIC16LF1513-I/SS PIC16F1512T-I/MV PIC16F1513T-I/MV PIC16LF1512T-I/MV PIC16LF1513T-I/MV PIC16F1512-I/MV PIC16F1513-E/MV PIC16F1513-I/MV PIC16LF1512-E/MV PIC16LF1512- I/MV PIC16LF1513-E/MV PIC16LF1513-I/MV PIC16F1512-E/SO PIC16F1512-E/MV