PIC16C7X 8-Bit CMOS Microcontrollers with A/D Converter Devices included in this data sheet: • Wide operating voltage range: 2.5V to 6.0V • High Sink/Source Current 25/25 mA • PIC16C72 • PIC16C74A • Commercial, Industrial and Extended temperature • PIC16C73 • PIC16C76 ranges • PIC16C73A • PIC16C77 • Low-power consumption: • PIC16C74 • < 2 mA @ 5V, 4 MHz • 15 m A typical @ 3V, 32 kHz PIC16C7X Microcontroller Core Features: • < 1 m A typical standby current • High-performance RISC CPU PIC16C7X Peripheral Features: • Only 35 single word instructions to learn • Timer0: 8-bit timer/counter with 8-bit prescaler • All single cycle instructions except for program • Timer1: 16-bit timer/counter with prescaler, branches which are two cycle can be incremented during sleep via external • Operating speed: DC - 20 MHz clock input crystal/clock DC - 200 ns instruction cycle • Timer2: 8-bit timer/counter with 8-bit period • Up to 8K x 14 words of Program Memory, register, prescaler and postscaler up to 368 x 8 bytes of Data Memory (RAM) • Capture, Compare, PWM module(s) • Interrupt capability • Capture is 16-bit, max. resolution is 12.5 ns, • Eight level deep hardware stack Compare is 16-bit, max. resolution is 200 ns, • Direct, indirect, and relative addressing modes PWM max. resolution is 10-bit • Power-on Reset (POR) • 8-bit multichannel analog-to-digital converter • Power-up Timer (PWRT) and • Synchronous Serial Port (SSP) with Oscillator Start-up Timer (OST) SPI(cid:228) and I2C(cid:228) • Watchdog Timer (WDT) with its own on-chip RC • Universal Synchronous Asynchronous Receiver oscillator for reliable operation Transmitter (USART/SCI) • Programmable code-protection • Parallel Slave Port (PSP) 8-bits wide, with • Power saving SLEEP mode external RD, WR and CS controls • Selectable oscillator options • Brown-out detection circuitry for • Low-power, high-speed CMOS EPROM Brown-out Reset (BOR) technology • Fully static design PIC16C7X Features 72 73 73A 74 74A 76 77 Program Memory (EPROM) x 14 2K 4K 4K 4K 4K 8K 8K Data Memory (Bytes) x 8 128 192 192 192 192 368 368 I/O Pins 22 22 22 33 33 22 33 Parallel Slave Port — — — Yes Yes — Yes Capture/Compare/PWM Modules 1 2 2 2 2 2 2 Timer Modules 3 3 3 3 3 3 3 A/D Channels 5 5 5 8 8 5 8 Serial Communication SPI/I2C SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C, USART USART USART USART USART USART In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Yes Brown-out Reset Yes — Yes — Yes Yes Yes Interrupt Sources 8 11 11 12 12 11 12 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 1

PIC16C7X Pin Diagrams SDIP, SOIC, Windowed Side Brazed Ceramic SSOP MCLR/VPP • 1 28 RB7 MCLR/VPP • 1 28 RB7 RA0/AN0 2 27 RB6 RA0/AN0 2 27 RB6 RA1/AN1 3 26 RB5 RA1/AN1 3 26 RB5 RA2/AN2 4 25 RB4 RA2/AN2 4 25 RB4 RA3/AN3/VREF 5 24 RB3 RA3/AN3/VREF 5 24 RB3 RA4/T0CKI 6 23 RB2 RA4/T0CKI 6 23 RB2 RA5/SS/AN4 7 22 RB1 RA5/SS/AN4 7 22 RB1 VSS 8 21 RB0/INT VSS 8 21 RB0/INT OSC1/CLKIN 9 20 VDD OSC1/CLKIN 9 20 VDD OSC2/CLKOUT 10 19 VSS OSC2/CLKOUT 10 19 VSS RC0/T1OSO/T1CKI 11 18 RC7 RC0/T1OSO/T1CKI 11 18 RC7 RC1/T1OSI 12 17 RC6 RC1/T1OSI 12 17 RC6 RC2/CCP1 13 16 RC5/SDO RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA RC3/SCK/SCL 14 15 RC4/SDI/SDA PIC16C72 PIC16C72 SDIP, SOIC, Windowed Side Brazed Ceramic PDIP, Windowed CERDIP MCLR/VPP • 1 28 RB7 MCLR/VPP 1 40 RB7 RA0/AN0 2 27 RB6 RA0/AN0 2 39 RB6 RA1/AN1 3 26 RB5 RA1/AN1 3 38 RB5 RA2/AN2 4 25 RB4 RA2/AN2 4 37 RB4 RA3/AN3/VREF 5 24 RB3 RA3/AN3/VREF 5 36 RB3 RA4/T0CKI 6 35 RB2 RA4/T0CKI 6 23 RB2 RA5/SS/AN4 7 34 RB1 RA5/SS/AN4 7 22 RB1 RE0/RD/AN5 8 33 RB0/INT VSS 8 21 RB0/INT RE1/WR/AN6 9 32 VDD OSC1/CLKIN 9 20 VDD RE2/CS/AN7 10 31 VSS OSC2/CLKOUT 10 19 VSS VVDSDS 1112 3209 RRDD76//PPSSPP76 RC0/T1OSO/T1CKI 11 18 RC7/RX/DT OSC1/CLKIN 13 28 RD5/PSP5 RC1/T1OSI/CCP2 12 17 RC6/TX/CK OSC2/CLKOUT 14 27 RD4/PSP4 RC2/CCP1 13 16 RC5/SDO RC0/T1OSO/T1CKI 15 26 RC7/RX/DT RC3/SCK/SCL 14 15 RC4/SDI/SDA RC1/T1OSI/CCP2 16 25 RC6/TX/CK RC2/CCP1 17 24 RC5/SDO PIC16C73 RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0/PSP0 19 22 RD3/PSP3 PIC16C73A RD1/PSP1 20 21 RD2/PSP2 PIC16C76 PIC16C74 PIC16C74A PIC16C77 DS30390E-page 2 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Pin Diagrams (Cont.’d) MQFP RC6/TX/CKRC5/SDORC4/SDI/SDARD3/PSP3RD2/PSP2RD1/PSP1RD0/PSP0RC3/SCK/SCLRC2/CCP1RC1/T1OSI/CCP2NC RC7/RX/DT 1444342414039383736353433 NC RD4/PSP4 2 32 RC0/T1OSO/T1CKI RD5/PSP5 3 31 OSC2/CLKOUT RD6/PSP6 4 30 OSC1/CLKIN RD7/PSP7 5 29 VSS VSS 6 PIC16C74 28 VDD VDD 7 27 RE2/CS/AN7 RB0/INT 8 26 RE1/WR/AN6 RB1 9 25 RE0/RD/AN5 RB2 10 24 RA5/SS/AN4 RB3 11 23 RA4/T0CKI 1213141516171819202122 NCNCRB4RB5RB6RB7/VMCLRPPRA0/AN0RA1/AN1RA2/AN2A3/AN3/VREF R PLCC RA3/AN3/VREFRA2/AN2RA1/AN1RA0/AN0/VMCLRPPNCRB7RB6RB5RB4NC MTQQFFPP RC6/TX/CKRC5/SDORC4/SDI/SDARD3/PSP3RD2/PSP2RD1/PSP1RD0/PSP0RC3/SCK/SCLRC2/CCP1RC1/T1OSI/CCP2NC 6543214443424140 RRA5A/4S/ST0/ACNK4I 78 3398 RRBB32 RC7/RX/DT 1444342414039383736353433 NC RE0/RD/AN5 9 37 RB1 RD4/PSP4 2 32 RC0/T1OSO/T1CKI OSRORCESE21C2//C/W1CL/CRSK//LOAAVVKUNNDSINTD76S 111111012345 PPPICIICC111666CCC777447A 333333654321 RVVRRRDSBDDDSD0765////IPPPNSSSTPPP765 RRRDDDR567B///PPP0/SSSVVINPPPDSTD567S 345678 PPICIC1166CC7747A 332222109876 OORRVVSSSEEDSDCC12//21WC//CCSR/LL/AAKKNONIN76UT RC0/T1OSO/T1CKI 16 30 RD4/PSP4 RB1 9 25 RE0/RD/AN5 NC 17 29 RC7/RX/DT RB2 10 24 RA5/SS/AN4 RB3 11 23 RA4/T0CKI 1819202122232425262728 1213141516171819202122 C1/T1OSI/CCP2RC2/CCP1RC3/SCK/SCLRD0/PSP0RD1/PSP1RD2/PSP2RD3/PSP3RC4/SDI/SDARC5/SDORC6/TX/CKNC NCNCRB4RB5RB6RB7/VMCLRPPRA0/AN0RA1/AN1RA2/AN2RA3/AN3/VREF R (cid:211) 1997 Microchip Technology Inc. DS30390E-page 3

PIC16C7X Table of Contents 1.0 General Description.......................................................................................................................................................................5 2.0 PIC16C7X Device Varieties...........................................................................................................................................................7 3.0 Architectural Overview...................................................................................................................................................................9 4.0 Memory Organization...................................................................................................................................................................19 5.0 I/O Ports.......................................................................................................................................................................................43 6.0 Overview of Timer Modules.........................................................................................................................................................57 7.0 Timer0 Module.............................................................................................................................................................................59 8.0 Timer1 Module.............................................................................................................................................................................65 9.0 Timer2 Module.............................................................................................................................................................................69 10.0Capture/Compare/PWM Module(s)..............................................................................................................................................71 11.0Synchronous Serial Port (SSP) Module.......................................................................................................................................77 12.0Universal Synchronous Asynchronous Receiver Transmitter (USART)......................................................................................99 13.0Analog-to-Digital Converter (A/D) Module.................................................................................................................................117 14.0Special Features of the CPU.....................................................................................................................................................129 15.0Instruction Set Summary............................................................................................................................................................147 16.0Development Support................................................................................................................................................................163 17.0Electrical Characteristics for PIC16C72.....................................................................................................................................167 18.0Electrical Characteristics for PIC16C73/74................................................................................................................................183 19.0Electrical Characteristics for PIC16C73A/74A...........................................................................................................................201 20.0Electrical Characteristics for PIC16C76/77................................................................................................................................219 21.0DC and AC Characteristics Graphs and Tables........................................................................................................................241 22.0Packaging Information...............................................................................................................................................................251 Appendix A: ...................................................................................................................................................................................263 Appendix B: Compatibility.............................................................................................................................................................263 Appendix C: What’s New...............................................................................................................................................................264 Appendix D: What’s Changed.......................................................................................................................................................264 Appendix E: PIC16/17 Microcontrollers.......................................................................................................................................265 Pin Compatibility................................................................................................................................................................................271 Index..................................................................................................................................................................................................273 List of Examples.................................................................................................................................................................................279 List of Figures.....................................................................................................................................................................................280 List of Tables......................................................................................................................................................................................283 Reader Response..............................................................................................................................................................................286 PIC16C7X Product Identification System...........................................................................................................................................287 For register and module descriptions in this data sheet, device legends show which devices apply to those sections. As an example, the legend below would mean that the following section applies only to the PIC16C72, PIC16C73A and PIC16C74A devices. Applicable Devices 727373A7474A7677 To Our Valued Customers We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. DS30390E-page 4 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 1.0 GENERAL DESCRIPTION 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog inter- The PIC16C7X is a family of low-cost, high-perfor- face, e.g. thermostat control, pressure sensing, etc. mance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converters, in the The PIC16C7X family has special features to reduce PIC16CXX mid-range family. external components, thus reducing cost, enhancing system reliability and reducing power consumption. All PIC16/17 microcontrollers employ an advanced There are four oscillator options, of which the single pin RISC architecture. The PIC16CXX microcontroller fam- RC oscillator provides a low-cost solution, the LP oscil- ily has enhanced core features, eight-level deep stack, lator minimizes power consumption, XT is a standard and multiple internal and external interrupt sources. crystal, and the HS is for High Speed crystals. The The separate instruction and data buses of the Harvard SLEEP (power-down) feature provides a power saving architecture allow a 14-bit wide instruction word with mode. The user can wake up the chip from SLEEP the separate 8-bit wide data. The two stage instruction through several external and internal interrupts and pipeline allows all instructions to execute in a single resets. cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction A highly reliable Watchdog Timer with its own on-chip set) are available. Additionally, a large register set gives RC oscillator provides protection against software lock- some of the architectural innovations used to achieve a up. very high performance. A UV erasable CERDIP packaged version is ideal for PIC16CXX microcontrollers typically achieve a 2:1 code development while the cost-effective One-Time- code compression and a 4:1 speed improvement over Programmable (OTP) version is suitable for production other 8-bit microcontrollers in their class. in any volume. The PIC16C72 has 128 bytes of RAM and 22 I/O pins. The PIC16C7X family fits perfectly in applications rang- In addition several peripheral features are available ing from security and remote sensors to appliance con- including: three timer/counters, one Capture/Compare/ trol and automotive. The EPROM technology makes PWM module and one serial port. The Synchronous customization of application programs (transmitter Serial Port can be configured as either a 3-wire Serial codes, motor speeds, receiver frequencies, etc.) Peripheral Interface (SPI) or the two-wire Inter-Inte- extremely fast and convenient. The small footprint grated Circuit (I2C) bus. Also a 5-channel high-speed packages make this microcontroller series perfect for all applications with space limitations. Low cost, low 8-bit A/D is provided. The 8-bit resolution is ideally power, high performance, ease of use and I/O flexibility suited for applications requiring low-cost analog inter- make the PIC16C7X very versatile even in areas where face, e.g. thermostat control, pressure sensing, etc. no microcontroller use has been considered before The PIC16C73/73A devices have 192 bytes of RAM, (e.g. timer functions, serial communication, capture while the PIC16C76 has 368 byes of RAM. Each device and compare, PWM functions and coprocessor appli- has 22 I/O pins. In addition, several peripheral features cations). are available including: three timer/counters, two Cap- ture/Compare/PWM modules and two serial ports. The 1.1 Family and Upward Compatibility Synchronous Serial Port can be configured as either a Users familiar with the PIC16C5X microcontroller fam- 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus. The Universal Syn- ily will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for chronous Asynchronous Receiver Transmitter a detailed list of enhancements. Code written for the (USART) is also known as the Serial Communications PIC16C5X can be easily ported to the PIC16CXX fam- Interface or SCI. Also a 5-channel high-speed 8-bit A/ ily of devices (Appendix B). D is provided.The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. 1.2 Development Support thermostat control, pressure sensing, etc. PIC16C7X devices are supported by the complete line The PIC16C74/74A devices have 192 bytes of RAM, of Microchip Development tools. while the PIC16C77 has 368 bytes of RAM. Each device has 33 I/O pins. In addition several peripheral Please refer to Section 16.0 for more details about features are available including: three timer/counters, Microchip’s development tools. two Capture/Compare/PWM modules and two serial ports. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus. The Uni- versal Synchronous Asynchronous Receiver Transmit- ter (USART) is also known as the Serial Communications Interface or SCI. An 8-bit Parallel Slave Port is provided. Also an 8-channel high-speed (cid:211) 1997 Microchip Technology Inc. DS30390E-page 5

PIC16C7X TABLE 1-1: PIC16C7XX FAMILY OF DEVCES PIC16C710 PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72(1) Maximum Frequency 20 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 512 1K 1K 2K 2K — (x14 words) Memory ROM Program Memory — — — — — 2K (14K words) Data Memory (bytes) 36 36 68 128 128 128 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0, TMR0, TMR1, TMR1, TMR2 TMR2 Capture/Compare/ — — — — 1 1 Peripherals PWM Module(s) Serial Port(s) — — — — SPI/I2C SPI/I2C (SPI/I2C, USART) Parallel Slave Port — — — — — — A/D Converter (8-bit) Channels 4 4 4 4 5 5 Interrupt Sources 4 4 4 4 8 8 I/O Pins 13 13 13 13 22 22 Voltage Range (Volts) 3.0-6.0 3.0-6.0 3.0-6.0 3.0-5.5 2.5-6.0 3.0-5.5 In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Features Brown-out Reset Yes — Yes Yes Yes Yes Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP, SOIC; SOIC SOIC; SOIC; SOIC, SSOP SOIC, SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP PIC16C73A PIC16C74A PIC16C76 PIC16C77 Maximum Frequency of Oper- 20 20 20 20 Clock ation (MHz) EPROM Program Memory 4K 4K 8K 8K Memory (x14 words) Data Memory (bytes) 192 192 368 368 Timer Module(s) TMR0, TMR0, TMR0, TMR0, TMR1, TMR1, TMR1, TMR1, TMR2 TMR2 TMR2 TMR2 Capture/Compare/PWM Mod- 2 2 2 2 Peripherals ule(s) Serial Port(s) (SPI/I2C, US- SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART ART) Parallel Slave Port — Yes — Yes A/D Converter (8-bit) Channels 5 8 5 8 Interrupt Sources 11 12 11 12 I/O Pins 22 33 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Features Brown-out Reset Yes Yes Yes Yes Packages 28-pin SDIP, 40-pin DIP; 28-pin SDIP, 40-pin DIP; SOIC 44-pin PLCC, SOIC 44-pin PLCC, MQFP, TQFP MQFP, TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capabil- ity. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales office for availability of these devices. DS30390E-page 6 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 2.0 PIC16C7X DEVICE VARIETIES 2.3 Quick-Turnaround-Production (QTP) Devices A variety of frequency ranges and packaging options are available. Depending on application and production Microchip offers a QTP Programming Service for fac- requirements, the proper device option can be selected tory production orders. This service is made available using the information in the PIC16C7X Product Identifi- for users who choose not to program a medium to high cation System section at the end of this data sheet. quantity of units and whose code patterns have stabi- When placing orders, please use that page of the data lized. The devices are identical to the OTP devices but sheet to specify the correct part number. with all EPROM locations and configuration options For the PIC16C7X family, there are two device “types” already programmed by the factory. Certain code and as indicated in the device number: prototype verification procedures apply before produc- tion shipments are available. Please contact your local 1. C, as in PIC16C74. These devices have Microchip Technology sales office for more details. EPROM type memory and operate over the standard voltage range. 2.4 Serialized Quick-Turnaround 2. LC, as in PIC16LC74. These devices have Production (SQTPSM) Devices EPROM type memory and operate over an extended voltage range. Microchip offers a unique programming service where a few user-defined locations in each device are pro- 2.1 UV Erasable Devices grammed with different serial numbers. The serial num- bers may be random, pseudo-random, or sequential. The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot Serial programming allows each device to have a programs. This version can be erased and unique number which can serve as an entry-code, reprogrammed to any of the oscillator modes. password, or ID number. (cid:210) (cid:210) Microchip's PICSTART Plus and PRO MATE II programmers both support programming of the PIC16C7X. 2.2 One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, per- mit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 7

PIC16C7X NOTES: DS30390E-page 8 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 3.0 ARCHITECTURAL OVERVIEW PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. The high performance of the PIC16CXX family can be It performs arithmetic and Boolean functions between attributed to a number of architectural features com- the data in the working register and any register file. monly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, The ALU is 8-bits wide and capable of addition, sub- program and data are accessed from separate memo- traction, shift and logical operations. Unless otherwise ries using separate buses. This improves bandwidth mentioned, arithmetic operations are two's comple- over traditional von Neumann architecture in which pro- ment in nature. In two-operand instructions, typically gram and data are fetched from the same memory one operand is the working register (W register). The using the same bus. Separating program and data other operand is a file register or an immediate con- buses further allows instructions to be sized differently stant. In single operand instructions, the operand is than the 8-bit wide data word. Instruction opcodes are either the W register or a file register. 14-bits wide making it possible to have all single word The W register is an 8-bit working register used for ALU instructions. A 14-bit wide program memory access operations. It is not an addressable register. bus fetches a 14-bit instruction in a single cycle. A two- Depending on the instruction executed, the ALU may stage pipeline overlaps fetch and execution of instruc- affect the values of the Carry (C), Digit Carry (DC), and tions (Example 3-1). Consequently, all instructions (35) Zero (Z) bits in the STATUS register. The C and DC bits execute in a single cycle (200 ns @ 20 MHz) except for operate as a borrow bit and a digit borrow out bit, program branches. respectively, in subtraction. See the SUBLW and SUBWF The table below lists program memory (EPROM) and instructions for examples. data memory (RAM) for each PIC16C7X device. Program Device Data Memory Memory PIC16C72 2K x 14 128 x 8 PIC16C73 4K x 14 192 x 8 PIC16C73A 4K x 14 192 x 8 PIC16C74 4K x 14 192 x 8 PIC16C74A 4K x 14 192 x 8 PIC16C76 8K x 14 368 x 8 PIC16C77 8K x 14 386 x 8 The PIC16CXX can directly or indirectly address its register files or data memory. All special function regis- ters, including the program counter, are mapped in the data memory. The PIC16CXX has an orthogonal (sym- metrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 9

PIC16C7X FIGURE 3-1: PIC16C72 BLOCK DIAGRAM 13 8 PORTA Data Bus Program Counter EPROM RA0/AN0 Program RA1/AN1 Memory RAM RA2/AN2 2K x 14 8 L(e1v3e-lb Sitt)ack RegFiisleters RRAA43//TA0NC3K/VIREF 128 x 8 RA5/SS/AN4 Program Bus 14 RAM Addr(1) 9 PORTB Addr MUX Instruction reg RB0/INT Direct Addr 7 8 InAddirderct RB7:RB1 FSR reg STATUS reg PORTC 8 RC0/T1OSO/T1CKI RC1/T1OSI 3 RC2/CCP1 Power-up MUX RC3/SCK/SCL Timer RC4/SDI/SDA Instruction Oscillator RC5/SDO Decode & Start-up Timer ALU RC6 Control Power-on RC7 Reset 8 Timing Watchdog Generation Timer W reg OSC1/CLKIN Brown-out OSC2/CLKOUT Reset MCLR VDD, VSS Timer0 Timer1 Timer2 Synchronous A/D Serial Port CCP1 Note 1: Higher order bits are from the STATUS register. DS30390E-page 10 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X FIGURE 3-2: PIC16C73/73A/76 BLOCK DIAGRAM Device Program Memory Data Memory (RAM) PIC16C73 4K x 14 192 x 8 PIC16C73A 4K x 14 192 x 8 PIC16C76 8K x 14 368 x 8 13 Data Bus 8 PORTA Program Counter RA0/AN0 EPROM RA1/AN1 Program RA2/AN2 Memory 8 Level Stack RAM RA3/AN3/VREF (13-bit) File RA4/T0CKI Registers RA5/SS/AN4 Program Bus 14 RAM Addr(1) 9 PORTB Addr MUX Instruction reg RB0/INT Direct Addr 7 Indirect 8 Addr FSR reg RB7:RB1 STATUS reg PORTC 8 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 3 RC2/CCP1 Power-up MUX RC3/SCK/SCL Timer RC4/SDI/SDA Instruction Oscillator RC5/SDO Decode & Start-up Timer ALU RC6/TX/CK Control Power-on RC7/RX/DT Reset 8 Timing Watchdog Generation Timer W reg OSC1/CLKIN Brown-out OSC2/CLKOUT Reset(2) MCLR VDD, VSS Timer0 Timer1 Timer2 A/D Synchronous CCP1 CCP2 USART Serial Port Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C73. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 11

PIC16C7X FIGURE 3-3: PIC16C74/74A/77 BLOCK DIAGRAM Device Program Memory Data Memory (RAM) PIC16C74 4K x 14 192 x 8 PIC16C74A 4K x 14 192 x 8 PIC16C77 8K x 14 368 x 8 13 Data Bus 8 PORTA Program Counter RA0/AN0 EPROM RA1/AN1 Program RA2/AN2 Memory 8 Level Stack RAM RA3/AN3/VREF (13-bit) File RA4/T0CKI Registers RA5/SS/AN4 Program Bus 14 RAM Addr (1) 9 PORTB Addr MUX Instruction reg RB0/INT Direct Addr 7 Indirect 8 Addr FSR reg RB7:RB1 STATUS reg PORTC 8 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 Power-up 3 MUX RRCC23//CSCCKP/1SCL Timer RC4/SDI/SDA Instruction Oscillator RC5/SDO Decode & Start-up Timer ALU RC6/TX/CK Control Power-on RC7/RX/DT Reset 8 PORTD Timing Watchdog Generation Timer W reg OSC1/CLKIN Brown-out OSC2/CLKOUT Reset(2) RD7/PSP7:RD0/PSP0 PORTE Parallel Slave Port MCLR VDD, VSS RE0/RD/AN5 RE1/WR/AN6 Timer0 Timer1 Timer2 A/D RE2/CS/AN7 Synchronous CCP1 CCP2 USART Serial Port Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C74. DS30390E-page 12 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 3-1: PIC16C72 PINOUT DESCRIPTION DIP SSOP SOIC I/O/P Buffer Pin Name Description Pin# Pin# Pin# Type Type OSC1/CLKIN 9 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input. OSC2/CLKOUT 10 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 1 1 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0/AN0 2 2 2 I/O TTL RA0 can also be analog input0 RA1/AN1 3 3 3 I/O TTL RA1 can also be analog input1 RA2/AN2 4 4 4 I/O TTL RA2 can also be analog input2 RA3/AN3/VREF 5 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage RA4/T0CKI 6 6 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5/SS/AN4 7 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 21 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 22 22 22 I/O TTL RB2 23 23 23 I/O TTL RB3 24 24 24 I/O TTL RB4 25 25 25 I/O TTL Interrupt on change pin. RB5 26 26 26 I/O TTL Interrupt on change pin. RB6 27 27 27 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock. RB7 28 28 28 I/O TTL/ST(2) Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI 12 12 12 I/O ST RC1 can also be the Timer1 oscillator input. RC2/CCP1 13 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 14 14 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6 17 17 17 I/O ST RC7 18 18 18 I/O ST VSS 8, 19 8, 19 8, 19 P — Ground reference for logic and I/O pins. VDD 20 20 20 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 13

PIC16C7X TABLE 3-2: PIC16C73/73A/76 PINOUT DESCRIPTION DIP SOIC I/O/P Buffer Pin Name Description Pin# Pin# Type Type OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input. OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 1 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0/AN0 2 2 I/O TTL RA0 can also be analog input0 RA1/AN1 3 3 I/O TTL RA1 can also be analog input1 RA2/AN2 4 4 I/O TTL RA2 can also be analog input2 RA3/AN3/VREF 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5/SS/AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 22 22 I/O TTL RB2 23 23 I/O TTL RB3 24 24 I/O TTL RB4 25 25 I/O TTL Interrupt on change pin. RB5 26 26 I/O TTL Interrupt on change pin. RB6 27 27 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock. RB7 28 28 I/O TTL/ST(2) Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins. VDD 20 20 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. DS30390E-page 14 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION DIP PLCC QFP I/O/P Buffer Pin Name Description Pin# Pin# Pin# Type Type OSC1/CLKIN 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input. OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 18 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0 RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1 RA2/AN2 4 5 21 I/O TTL RA2 can also be analog input2 RA3/AN3/VREF 5 6 22 I/O TTL RA3 can also be analog input3 or analog reference voltage RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5/SS/AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 34 37 9 I/O TTL RB2 35 38 10 I/O TTL RB3 36 39 11 I/O TTL RB4 37 41 14 I/O TTL Interrupt on change pin. RB5 38 42 15 I/O TTL Interrupt on change pin. RB6 39 43 16 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock. RB7 40 44 17 I/O TTL/ST(2) Interrupt on change pin. Serial programming data. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 15

PIC16C7X TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION (Cont.’d) DIP PLCC QFP I/O/P Buffer Pin Name Description Pin# Pin# Pin# Type Type PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/ output for both SPI and I2C modes. RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus. RD0/PSP0 19 21 38 I/O ST/TTL(3) RD1/PSP1 20 22 39 I/O ST/TTL(3) RD2/PSP2 21 23 40 I/O ST/TTL(3) RD3/PSP3 22 24 41 I/O ST/TTL(3) RD4/PSP4 27 30 2 I/O ST/TTL(3) RD5/PSP5 28 31 3 I/O ST/TTL(3) RD6/PSP6 29 32 4 I/O ST/TTL(3) RD7/PSP7 30 33 5 I/O ST/TTL(3) PORTE is a bi-directional I/O port. RE0/RD/AN5 8 9 25 I/O ST/TTL(3) RE0 can also be read control for the parallel slave port, or analog input5. RE1/WR/AN6 9 10 26 I/O ST/TTL(3) RE1 can also be write control for the parallel slave port, or analog input6. RE2/CS/AN7 10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave port, or analog input7. VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins. VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins. NC — 1,17,28, 12,13, — These pins are not internally connected. These pins should 40 33,34 be left unconnected. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. DS30390E-page 16 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining The clock input (from OSC1) is internally divided by An “Instruction Cycle” consists of four Q cycles (Q1, four to generate four non-overlapping quadrature Q2, Q3 and Q4). The instruction fetch and execute are clocks namely Q1, Q2, Q3 and Q4. Internally, the pro- pipelined such that fetch takes one instruction cycle gram counter (PC) is incremented every Q1, the while decode and execute takes another instruction instruction is fetched from the program memory and cycle. However, due to the pipelining, each instruction latched into the instruction register in Q4. The instruc- effectively executes in one cycle. If an instruction tion is decoded and executed during the following Q1 causes the program counter to change (e.g. GOTO) through Q4. The clocks and instruction execution flow then two cycles are required to complete the instruction is shown in Figure 3-4. (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Q3 phase clock Q4 PC PC PC+1 PC+2 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 17

PIC16C7X NOTES: DS30390E-page 18 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 4.0 MEMORY ORGANIZATION FIGURE 4-2: PIC16C73/73A/74/74A Applicable Devices PROGRAM MEMORY MAP AND STACK 727373A7474A7677 4.1 Program Memory Organization PC<12:0> The PIC16C7X family has a 13-bit program counter CALL, RETURN 13 RETFIE, RETLW capable of addressing an 8K x 14 program memory space. The amount of program memory available to each device is listed below: Stack Level 1 Program Device Address Range Memory Stack Level 8 PIC16C72 2K x 14 0000h-07FFh PIC16C73 4K x 14 0000h-0FFFh Reset Vector 0000h PIC16C73A 4K x 14 0000h-0FFFh PIC16C74 4K x 14 0000h-0FFFh PIC16C74A 4K x 14 0000h-0FFFh y Interrupt Vector 0004h PIC16C76 8K x 14 0000h-1FFFh or me On-chip Program 0005h PIC16C77 8K x 14 0000h-1FFFh Meac Memory (Page 0) p For those devices with less than 8K program memory, er S 07FFh s U accessing a location above the physically implemented On-chip Program 0800h address will cause a wraparound. Memory (Page 1) The reset vector is at 0000h and the interrupt vector is 0FFFh at 0004h. 1000h FIGURE 4-1: PIC16C72 PROGRAM MEMORY MAP AND STACK 1FFFh PC<12:0> CALL, RETURN 13 RETFIE, RETLW Stack Level 1 Stack Level 8 Reset Vector 0000h y Interrupt Vector 0004h or me 0005h ec Ma p er S s On-chip Program U Memory 07FFh 0800h 1FFFh (cid:211) 1997 Microchip Technology Inc. DS30390E-page 19

PIC16C7X FIGURE 4-3: PIC16C76/77 PROGRAM 4.2 Data Memory Organization MEMORY MAP AND STACK Applicable Devices 727373A7474A7677 PC<12:0> The data memory is partitioned into multiple banks CALL, RETURN 13 which contain the General Purpose Registers and the RETFIE, RETLW Special Function Registers. Bits RP1 and RP0 are the bank select bits. Stack Level 1 RP1:RP0 (STATUS<6:5>) Stack Level 2 = 00 fi Bank0 = 01 fi Bank1 = 10 fi Bank2 Stack Level 8 = 11 fi Bank3 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Reset Vector 0000h Function Registers. Above the Special Function Regis- ters are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some “high use” special function Interrupt Vector 0004h registers from one bank may be mirrored in another 0005h bank for code reduction and quicker access. y On-Chip Page 0 more 07FFh 4.2.1 GENERAL PURPOSE REGISTER FILE er MeSpac On-Chip Page 1 0800h Trehcetl yre gitshtreoru figleh catnh eb e aFciclee ssSede leeictht erR deirgeicsttley,r or FinSdRi- s 0FFFh U (Section 4.5). 1000h On-Chip Page 2 17FFh 1800h On-Chip Page 3 1FFFh DS30390E-page 20 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X FIGURE 4-4: PIC16C72 REGISTER FILE FIGURE 4-5: PIC16C73/73A/74/74A MAP REGISTER FILE MAP File File File File Address Address Address Address 00h INDF(1) INDF(1) 80h 00h INDF(1) INDF(1) 80h 01h TMR0 OPTION 81h 01h TMR0 OPTION 81h 02h PCL PCL 82h 02h PCL PCL 82h 03h STATUS STATUS 83h 03h STATUS STATUS 83h 04h FSR FSR 84h 04h FSR FSR 84h 05h PORTA TRISA 85h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 06h PORTB TRISB 86h 07h PORTC TRISC 87h 07h PORTC TRISC 87h 08h PORTD(2) TRISD(2) 88h 08h 88h 09h PORTE(2) TRISE(2) 89h 09h 89h 0Ah PCLATH PCLATH 8Ah 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Ch PIR1 PIE1 8Ch 0Dh PIR2 PIE2 8Dh 0Dh 8Dh 0Eh TMR1L PCON 8Eh 0Eh TMR1L PCON 8Eh 0Fh TMR1H 8Fh 0Fh TMR1H 8Fh 10h T1CON 90h 10h T1CON 90h 11h TMR2 91h 11h TMR2 91h 12h T2CON PR2 92h 12h T2CON PR2 92h 13h SSPBUF SSPADD 93h 13h SSPBUF SSPADD 93h 14h SSPCON SSPSTAT 94h 14h SSPCON SSPSTAT 94h 15h CCPR1L 95h 15h CCPR1L 95h 16h CCPR1H 96h 16h CCPR1H 96h 17h CCP1CON 97h 17h CCP1CON 97h 18h RCSTA TXSTA 98h 18h 98h 19h TXREG SPBRG 99h 19h 99h 1Ah RCREG 9Ah 1Ah 9Ah 1Bh CCPR2L 9Bh 1Bh 9Bh 1Ch CCPR2H 9Ch 1Ch 9Ch 1Dh CCP2CON 9Dh 1Dh 9Dh 1Eh ADRES 9Eh 1Eh ADRES 9Eh 1Fh ADCON0 ADCON1 9Fh 1Fh ADCON0 ADCON1 9Fh 20h A0h 20h A0h General General Purpose Purpose General General Register Register Purpose Purpose BFh Register Register C0h 7Fh FFh Bank 0 Bank 1 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. Unimplemented data memory locations, read as Note 1: Not a physical register. '0'. 2: These registers are not physically imple- Note 1: Not a physical register. mented on the PIC16C73/73A, read as '0'. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 21

PIC16C7X FIGURE 4-6: PIC16C76/77 REGISTER FILE MAP File Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION 81h TMR0 101h OPTION 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h 107h 187h PORTD(1) 08h TRISD(1) 88h 108h 188h PORTE(1) 09h TRISE(1) 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch 10Ch 18Ch PIR2 0Dh PIE2 8Dh 10Dh 18Dh TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh 8Fh 10Fh 18Fh T1CON 10h 90h 110h 190h TMR2 11h 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPR1L 15h 95h 115h 195h CCPR1H 16h 96h 116h 196h CCP1CON 17h 97h General 117h General 197h Purpose Purpose RCSTA 18h TXSTA 98h Register 118h Register 198h TXREG 19h SPBRG 99h 16 Bytes 119h 16 Bytes 199h RCREG 1Ah 9Ah 11Ah 19Ah CCPR2L 1Bh 9Bh 11Bh 19Bh CCPR2H 1Ch 9Ch 11Ch 19Ch CCP2CON 1Dh 9Dh 11Dh 19Dh ADRES 1Eh 9Eh 11Eh 19Eh ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh 20h A0h 120h 1A0h General General General General Purpose Purpose Purpose Purpose Register Register Register Register 80 Bytes 80 Bytes 80 Bytes 96 Bytes EFh 16Fh 1EFh accesses F0h accesses 170h accesses 1F0h 70h-7Fh 70h-7Fh 70h - 7Fh 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: PORTD, PORTE, TRISD, and TRISE are unimplemented on the PIC16C76, read as '0'. Note: The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require relocation of data memory usage in the user application code if upgrading to the PIC16C76/77. DS30390E-page 22 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 4.2.2 SPECIAL FUNCTION REGISTERS The special function registers can be classified into two sets (core and peripheral). Those registers associated The Special Function Registers are registers used by with the “core” functions are described in this section, the CPU and Peripheral Modules for controlling the and those related to the operation of the peripheral fea- desired operation of the device. These registers are tures are described in the section of that peripheral fea- implemented as static RAM. ture. TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR (3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h — Unimplemented — — 09h — Unimplemented — — 0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 0Dh — Unimplemented — — 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h — Unimplemented — — 19h — Unimplemented — — 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 23

PIC16C7X TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d) Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR (3) Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h — Unimplemented — — 89h — Unimplemented — — 8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear. DS30390E-page 24 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR (2) Bank 0 00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(4) STATUS IRP(7) RP1(7) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 09h(5) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con- tents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear. 4: These registers can be addressed from either bank. 5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’. 6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'. 7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 25

PIC16C7X TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d) Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR (2) Bank 1 80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(4) STATUS IRP(7) RP1(7) RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h(5) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR(6) ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con- tents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear. 4: These registers can be addressed from either bank. 5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’. 6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'. 7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear. DS30390E-page 26 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR (2) Bank 0 00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 09h(5) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con- tents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 27

PIC16C7X TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d) Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR (2) Bank 1 80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h(5) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con- tents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’. DS30390E-page 28 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d) Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR (2) Bank 2 100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 102h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 103h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 104h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 105h — Unimplemented — — 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 10Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Ch- — Unimplemented — — 10Fh Bank 3 180h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 182h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 183h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 184h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 18Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 18Ch- — Unimplemented — — 18Fh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con- tents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 29

PIC16C7X 4.2.2.1 STATUS REGISTER For example, CLRF STATUS will clear the upper-three Applicable Devices bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). 727373A7474A7677 It is recommended, therefore, that only BCF, BSF, The STATUS register, shown in Figure 4-7, contains the SWAPF and MOVWF instructions are used to alter the arithmetic status of the ALU, the RESET status and the STATUS register because these instructions do not bank select bits for data memory. affect the Z, C or DC bits from the STATUS register. For The STATUS register can be the destination for any other instructions, not affecting any status bits, see the instruction, as with any other register. If the STATUS "Instruction Set Summary." register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is Note 1: For those devices that do not use bits IRP disabled. These bits are set or cleared according to the and RP1 (STATUS<7:6>), maintain these device logic. Furthermore, the TO and PD bits are not bits clear to ensure upward compatibility writable. Therefore, the result of an instruction with the with future products. STATUS register as destination may be different than Note 2: The C and DC bits operate as a borrow intended. and digit borrow bit, respectively, in sub- traction. See the SUBLW and SUBWF instructions for examples. FIGURE 4-7: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. DS30390E-page 30 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 4.2.2.2 OPTION REGISTER Applicable Devices Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to 727373A7474A7677 the Watchdog Timer. The OPTION register is a readable and writable regis- ter which contains various control bits to configure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 4-8: OPTION REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 31

PIC16C7X 4.2.2.3 INTCON REGISTER Applicable Devices Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of 727373A7474A7677 its corresponding enable bit or the global The INTCON Register is a readable and writable regis- enable bit, GIE (INTCON<7>). ter which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. FIGURE 4-9: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: GIE:(1) Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note1: For the PIC16C73 and PIC16C74, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may be unintentionally re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. Refer to Section 14.5 for a detailed description. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30390E-page 32 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 4.2.2.4 PIE1 REGISTER Applicable Devices Note: Bit PEIE (INTCON<6>) must be set to 727373A7474A7677 enable any peripheral interrupt. This register contains the individual enable bits for the peripheral interrupts. FIGURE 4-10: PIE1 REGISTER PIC16C72 (ADDRESS 8Ch) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: Unimplemented: Read as '0' bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt (cid:211) 1997 Microchip Technology Inc. DS30390E-page 33

PIC16C7X FIGURE 4-11: PIE1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5: RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4: TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note1: PIC16C73/73A/76 devices do not have a Parallel Slave Port implemented, this bit location is reserved on these devices, always maintain this bit clear. DS30390E-page 34 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 4.2.2.5 PIR1 REGISTER Note: Interrupt flag bits get set when an interrupt Applicable Devices condition occurs regardless of the state of 727373A7474A7677 its corresponding enable bit or the global This register contains the individual flag bits for the enable bit, GIE (INTCON<7>). User soft- Peripheral interrupts. ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. FIGURE 4-12: PIR1 REGISTER PIC16C72 (ADDRESS 0Ch) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: Unimplemented: Read as '0' bit 6: ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 35

PIC16C7X FIGURE 4-13: PIR1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6: ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5: RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is empty bit 4: TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note1: PIC16C73/73A/76 devices do not have a Parallel Slave Port implemented, this bit location is reserved on these devices, always maintain this bit clear. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30390E-page 36 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 4.2.2.6 PIE2 REGISTER Applicable Devices 727373A7474A7677 This register contains the individual enable bit for the CCP2 peripheral interrupt. FIGURE 4-14: PIE2 REGISTER (ADDRESS 8Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IE R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt (cid:211) 1997 Microchip Technology Inc. DS30390E-page 37

PIC16C7X 4.2.2.7 PIR2 REGISTER . Applicable Devices Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of 727373A7474A7677 its corresponding enable bit or the global This register contains the CCP2 interrupt flag bit. enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. FIGURE 4-15: PIR2 REGISTER (ADDRESS 0Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IF: CCP2 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30390E-page 38 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 4.2.2.8 PCON REGISTER Note: BOR is unknown on Power-on Reset. It Applicable Devices must then be set by the user and checked 727373A7474A7677 on subsequent resets to see if BOR is clear, indicating a brown-out has occurred. The Power Control (PCON) register contains a flag bit The BOR status bit is a don't care and is to allow differentiation between a Power-on Reset not necessarily predictable if the brown-out (POR) to an external MCLR Reset or WDT Reset. circuit is disabled (by clearing the BODEN Those devices with brown-out detection circuitry con- bit in the Configuration word). tain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. FIGURE 4-16: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q — — — — — — POR BOR(1) R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR(1): Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note1: Brown-out Reset is not implemented on the PIC16C73/74. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 39

PIC16C7X 4.3 PCL and PCLATH Note 1: There are no status bits to indicate stack Applicable Devices overflow or stack underflow conditions. 727373A7474A7677 Note 2: There are no instructions/mnemonics The program counter (PC) is 13-bits wide. The low byte called PUSH or POP. These are actions comes from the PCL register, which is a readable and that occur from the execution of the writable register. The upper bits (PC<12:8>) are not CALL, RETURN, RETLW, and RETFIE readable, but are indirectly writable through the instructions, or the vectoring to an inter- PCLATH register. On any reset, the upper bits of the rupt address. PC will be cleared. Figure 4-17 shows the two situa- 4.4 Program Memory Paging tions for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to Applicable Devices PCL (PCLATH<4:0> fi PCH). The lower example in 727373A7474A7677 the figure shows how the PC is loaded during a CALL PIC16C7X devices are capable of addressing a contin- or GOTO instruction (PCLATH<4:3> fi PCH). uous 8K word block of program memory. The CALL and FIGURE 4-17: LOADING OF PC IN GOTO instructions provide only 11 bits of address to DIFFERENT SITUATIONS allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper 2 bits of the address are provided by PCLATH<4:3>. When PCH PCL doing a CALL or GOTO instruction, the user must ensure 12 8 7 0 Instruction with that the page select bits are programmed so that the PC PCL as desired program memory page is addressed. If a return Destination PCLATH<4:0> 8 from a CALL instruction (or interrupt) is executed, the 5 ALU entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required PCLATH for the return instructions (which POPs the address from the stack). PCH PCL Note: PIC16C7X devices with 4K or less of pro- 12 11 10 8 7 0 gram memory ignore paging bit PC GOTO, CALL PCLATH<4>. The use of PCLATH<4> as a 2 PCLATH<4:3> 11 general purpose read/write bit is not rec- Opcode <10:0> ommended since this may affect upward compatibility with future products. PCLATH 4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an off- set to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note “Implementing a Table Read" (AN556). 4.3.2 STACK The PIC16CXX family has an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). DS30390E-page 40 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Example 4-1 shows the calling of a subroutine in 4.5 Indirect Addressing, INDF and FSR page 1 of the program memory. This example assumes Registers that PCLATH is saved and restored by the interrupt ser- Applicable Devices vice routine (if interrupts are used). 727373A7474A7677 EXAMPLE 4-1: CALL OF A SUBROUTINE IN The INDF register is not a physical register. Addressing PAGE 1 FROM PAGE 0 the INDF register will cause indirect addressing. ORG 0x500 Indirect addressing is possible by using the INDF reg- BSF PCLATH,3 ;Select page 1 (800h-FFFh) ister. Any instruction using the INDF register actually BCF PCLATH,4 ;Only on >4K devices accesses the register pointed to by the File Select Reg- CALL SUB1_P1 ;Call subroutine in ister, FSR. Reading the INDF register itself indirectly : ;page 1 (800h-FFFh) (FSR = '0') will read 00h. Writing to the INDF register : indirectly results in a no-operation (although status bits : may be affected). An effective 9-bit address is obtained ORG 0x900 by concatenating the 8-bit FSR register and the IRP bit SUB1_P1: ;called subroutine : ;page 1 (800h-FFFh) (STATUS<7>), as shown in Figure 4-18. : A simple program to clear RAM locations 20h-2Fh RETURN ;return to Call subroutine using indirect addressing is shown in Example 4-2. ;in page 0 (000h-7FFh) EXAMPLE 4-2: INDIRECT ADDRESSING movlw 0x20 ;initialize pointer movwf FSR ;to RAM NEXT clrf INDF ;clear INDF register incf FSR,F ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next CONTINUE : ;yes continue FIGURE 4-18: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1:RP0 6 from opcode 0 IRP 7 FSR register 0 bank select location select bank select location select 00 01 10 11 00h 80h 100h 180h not used Data Memory 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For register file map detail see Figure 4-4, and Figure 4-5. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 41

PIC16C7X NOTES: DS30390E-page 42 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 5.0 I/O PORTS FIGURE 5-1: BLOCK DIAGRAM OF Applicable Devices RA3:RA0 AND RA5 PINS 727373A7474A7677 Data bus Some pins for these I/O ports are multiplexed with an D Q alternate function for the peripheral features on the VDD device. In general, when a peripheral is enabled, that WR Port pin may not be used as a general purpose I/O pin. CK Q P 5.1 PORTA and TRISA Registers Data Latch Applicable Devices D Q N I/O pin(1) 727373A7474A7677 WR PORTA is a 6-bit latch. TRIS CK Q VSS The RA4/T0CKI pin is a Schmitt Trigger input and an Analog open drain output. All other RA port pins have TTL input input TRIS Latch mode levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as output or input. RD TRIS TTL Setting a TRISA register bit puts the corresponding out- input buffer put driver in a hi-impedance mode. Clearing a bit in the Q D TRISA register puts the contents of the output latch on the selected pin(s). Reading the PORTA register reads the status of the EN pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. RD PORT Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. To A/D Converter Pin RA4 is multiplexed with the Timer0 module clock Note 1: I/O pins have protection diodes to VDD and input to become the RA4/T0CKI pin. VSS. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the FIGURE 5-2: BLOCK DIAGRAM OF RA4/ ADCON1 register (A/D Control Register1). T0CKI PIN Note: On a Power-on Reset, these pins are con- Data figured as analog inputs and read as '0'. bus D Q The TRISA register controls the direction of the RA WR PORT pins, even when they are being used as analog inputs. CK Q I/O pin(1) The user must ensure the bits in the TRISA register are N Data Latch maintained set when using them as analog inputs. D Q VSS EXAMPLE 5-1: INITIALIZING PORTA WR TRIS CK Q Schmitt BCF STATUS, RP0 ; Trigger input BCF STATUS, RP1 ; PIC16C76/77 only TRIS Latch buffer CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches RD TRIS BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to Q D ; initialize data ; direction ENEN MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs RD PORT ; TRISA<7:6> are always ; read as '0'. TMR0 clock input Note 1: I/O pin has protection diodes to VSS only. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 43

PIC16C7X TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input RA1/AN1 bit1 TTL Input/output or analog input RA2/AN2 bit2 TTL Input/output or analog input RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF RA4/T0CKI bit4 ST Input/output or external clock input for Timer0 Output is open drain type RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. DS30390E-page 44 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 5.2 PORTB and TRISB Registers Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can Applicable Devices cause this interrupt to occur (i.e. any RB7:RB4 pin con- 727373A7474A7677 figured as an output is excluded from the interrupt on PORTB is an 8-bit wide bi-directional port. The corre- change comparison). The input pins (of RB7:RB4) are sponding data direction register is TRISB. Setting a bit compared with the old value latched on the last read of in the TRISB register puts the corresponding output PORTB. The “mismatch” outputs of RB7:RB4 are driver in a hi-impedance input mode. Clearing a bit in OR’ed together to generate the RB Port Change Inter- the TRISB register puts the contents of the output latch rupt with flag bit RBIF (INTCON<0>). on the selected pin(s). This interrupt can wake the device from SLEEP. The EXAMPLE 5-2: INITIALIZING PORTB user, in the interrupt service routine, can clear the inter- rupt in the following manner: BCF STATUS, RP0 ; CLRF PORTB ; Initialize PORTB by a) Any read or write of PORTB. This will end the ; clearing output mismatch condition. ; data latches b) Clear flag bit RBIF. BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to A mismatch condition will continue to set flag bit RBIF. ; initialize data Reading PORTB will end the mismatch condition, and ; direction allow flag bit RBIF to be cleared. MOVWF TRISB ; Set RB<3:0> as inputs This interrupt on mismatch feature, together with soft- ; RB<5:4> as outputs ware configurable pull-ups on these four pins allow ; RB<7:6> as inputs easy interface to a keypad and make it possible for Each of the PORTB pins has a weak internal pull-up. A wake-up on key-depression. Refer to the Embedded single control bit can turn on all the pull-ups. This is Control Handbook, "Implementing Wake-Up on Key performed by clearing bit RBPU (OPTION<7>). The Stroke" (AN552). weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are dis- Note: For the PIC16C73/74, if a change on the abled on a Power-on Reset. I/O pin should occur when the read opera- tion is being executed (start of the Q2 FIGURE 5-3: BLOCK DIAGRAM OF cycle), then interrupt flag bit RBIF may not RB3:RB0 PINS get set. VDD RBPU(2) weak The interrupt on change feature is recommended for P pull-up wake-up on key depression operation and operations Data Latch where PORTB is only used for the interrupt on change Data bus D Q feature. Polling of PORTB is not recommended while WR Port I/O using the interrupt on change feature. CK pin(1) TRIS Latch D Q TTL Input WR TRIS CK Buffer RD TRIS Q D RD Port EN RB0/INT Schmitt Trigger RD Port Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). (cid:211) 1997 Microchip Technology Inc. DS30390E-page 45

PIC16C7X FIGURE 5-4: BLOCK DIAGRAM OF FIGURE 5-5: BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C73/74) RB7:RB4 PINS (PIC16C72/ VDD 73A/74A/76/77) RBPU(2) weak VDD P pull-up RBPU(2) weak Data bus Data Latch P pull-up D Q Data Latch Data bus I/O D Q WR Port CK pin(1) I/O WR Port TRIS Latch CK pin(1) D Q TRIS Latch D Q WR TRIS TTL CK Input Buffer ST WR TRIS CK TTL Input Buffer Buffer ST Buffer RD TRIS Latch Q D RD TRIS Latch Q D RD Port EN Set RBIF RD Port EN Q1 Set RBIF From other Q D RB7:RB4 pins From other Q D EN RB7:RB4 pins RD Port RD Port EN RB7:RB6 in serial programming mode Q3 Note 1: I/O pins have diode protection to VDD and VSS. RB7:RB6 in serial programming mode 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. DS30390E-page 46 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 47

PIC16C7X 5.3 PORTC and TRISC Registers FIGURE 5-6: PORTC BLOCK DIAGRAM Applicable Devices (PERIPHERAL OUTPUT OVERRIDE) 727373A7474A7677 PORTC is an 8-bit bi-directional port. Each pin is indi- PORT/PERIPHERAL Select(2) vidually configurable as an input or output through the TRISC register. PORTC is multiplexed with several Peripheral Data Out 0 VDD peripheral functions (Table 5-5). PORTC pins have Data bus Schmitt Trigger input buffers. WR D Q 1 P PORT When enabling peripheral functions, care should be CK Q taken in defining TRIS bits for each PORTC pin. Some Data Latch peripherals override the TRIS bit to make a pin an out- D Q I/O put, while other peripherals override the TRIS bit to WR pin(1) TRIS make a pin an input. Since the TRIS bit override is in CK Q N effect while the peripheral is enabled, read-modify- TRIS Latch write instructions (BSF, BCF, XORWF) with TRISC as VSS destination should be avoided. The user should refer to Schmitt the corresponding peripheral section for the correct RD TRIS Trigger TRIS bit settings. Peripheral OE(3) Q D EXAMPLE 5-3: INITIALIZING PORTC RD EN BCF STATUS, RP0 ; Select Bank 0 PORT BCF STATUS, RP1 ; PIC16C76/77 only Peripheral input CLRF PORTC ; Initialize PORTC by Note 1: I/O pins have diode protection to VDD and VSS. ; clearing output 2: Port/Peripheral select signal selects between port ; data latches data and peripheral output. BSF STATUS, RP0 ; Select Bank 1 3: Peripheral OE (output enable) is only activated if MOVLW 0xCF ; Value used to peripheral select is active. ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs TABLE 5-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input RC1/T1OSI/CCP2(1) bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output RC6/TX/CK(2) bit6 ST Input/output port pin or USART Asynchronous Transmit, or USART Synchronous Clock RC7/RX/DT(2) bit7 ST Input/output port pin or USART Asynchronous Receive, or USART Synchronous Data Legend: ST = Schmitt Trigger input Note1: The CCP2 multiplexed function is not enabled on the PIC16C72. 2: The TX/CK and RX/DT multiplexed functions are not enabled on the PIC16C72. DS30390E-page 48 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 49

PIC16C7X 5.4 PORTD and TRISD Registers FIGURE 5-7: PORTD BLOCK DIAGRAM (IN Applicable Devices I/O PORT MODE) 727373A7474A7677 Data bus PORTD is an 8-bit port with Schmitt Trigger input buff- D Q ers. Each pin is individually configurable as an input or WR output. PORT CK I/O pin(1) PORTD can be configured as an 8-bit wide micropro- Data Latch cessor port (parallel slave port) by setting control bit D Q PSPMODE (TRISE<4>). In this mode, the input buffers WR are TTL. TRIS Schmitt CK Trigger input TRIS Latch buffer RD TRIS Q D ENEN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS. TABLE 5-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0 RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1 RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2 RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3 RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4 RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5 RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6 RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7 Legend: ST = Schmitt Trigger input TTL = TTL input Note1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode. TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD. DS30390E-page 50 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 5.5 PORTE and TRISE Register Note: On a Power-on Reset these pins are con- Applicable Devices figured as analog inputs. 727373A7474A7677 FIGURE 5-8: PORTE BLOCK DIAGRAM (IN PORTE has three pins RE0/RD/AN5, RE1/WR/AN6 I/O PORT MODE) and RE2/CS/AN7, which are individually configurable Data as inputs or outputs. These pins have Schmitt Trigger bus D Q input buffers. WR PORT I/O pin(1) I/O PORTE becomes control inputs for the micropro- CK cessor port when bit PSPMODE (TRISE<4>) is set. In Data Latch this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital D Q inputs) and that register ADCON1 is configured for dig- WR ital I/O. In this mode the input buffers are TTL. TRIS CK Schmitt Trigger Figure 5-9 shows the TRISE register, which also con- TRIS Latch input buffer trols the parallel slave port operation. PORTE pins are multiplexed with analog inputs. The operation of these pins is selected by control bits in the RD TRIS ADCON1 register. When selected as an analog input, these pins will read as '0's. Q D TRISE controls the direction of the RE pins, even when ENEN they are being used as analog inputs. The user must RD PORT make sure to keep the pins configured as inputs when using them as analog inputs. Note 1: I/O pins have protection diodes to VDD and VSS. FIGURE 5-9: TRISE REGISTER (ADDRESS 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — bit2 bit1 bit0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7 : IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6: OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5: IBOV: Input Buffer Overflow Detect bit (in microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4: PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel slave port mode 0 = General purpose I/O mode bit 3: Unimplemented: Read as '0' PORTE Data Direction Bits bit 2: Bit2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output bit 1: Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0: Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output (cid:211) 1997 Microchip Technology Inc. DS30390E-page 51

PIC16C7X TABLE 5-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/RD/AN5 bit0 ST/TTL(1) Input/output port pin or read control input in parallel slave port mode or analog input: RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected) RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in parallel slave port mode or analog input: WR 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected) RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in parallel slave port mode or analog input: CS 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input TTL = TTL input Note1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode. TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE. DS30390E-page 52 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 5.6 I/O Programming Considerations EXAMPLE 5-4: READ-MODIFY-WRITE Applicable Devices INSTRUCTIONS ON AN I/O PORT 727373A7474A7677 ;Initial PORT settings: PORTB<7:4> Inputs 5.6.1 BI-DIRECTIONAL I/O PORTS ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are Any instruction which writes, operates internally as a ;not connected to other circuitry read followed by a write operation. The BCF and BSF ; instructions, for example, read the register into the ; PORT latch PORT pins CPU, execute the bit operation and write the result back ; ---------- --------- to the register. Caution must be used when these BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp instructions are applied to a port with both inputs and BSF STATUS, RP0 ; outputs defined. For example, a BSF operation on bit5 BCF TRISB, 7 ; 10pp pppp 11pp pppp of PORTB will cause all eight bits of PORTB to be read BCF TRISB, 6 ; 10pp pppp 10pp pppp into the CPU. Then the BSF operation takes place on ; bit5 and PORTB is written to the output latches. If ;Note that the user may have expected the another bit of PORTB is used as a bi-directional I/O pin ;pin values to be 00pp ppp. The 2nd BCF (e.g., bit0) and it is defined as an input at this time, the ;caused RB7 to be latched as the pin value input signal present on the pin itself would be read into ;(high). the CPU and rewritten to the data latch of this particular A pin actively outputting a Low or High should not be pin, overwriting the previous content. As long as the pin driven from external devices at the same time in order stays in the input mode, no problem occurs. However, if to change the level on this pin (“wired-or”, “wired-and”). bit0 is switched to an output, the content of the data The resulting high output currents may damage the latch may now be unknown. chip. Reading the port register, reads the values of the port 5.6.2 SUCCESSIVE OPERATIONS ON I/O PORTS pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions The actual write to an I/O port happens at the end of an (ex. BCF, BSF, etc.) on a port, the value of the port pins instruction cycle, whereas for reading, the data must be is read, the desired operation is done to this value, and valid at the beginning of the instruction cycle (Figure 5- this value is then written to the port latch. 10). Therefore, care must be exercised if a write fol- Example 5-4 shows the effect of two sequential read- lowed by a read operation is carried out on the same I/ modify-write instructions on an I/O port. O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-10: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Note: PC PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB Instruction followed by a read from PORTB. fetched MOVWF PORTB MOVF PORTB,W write to NOP NOP Note that: PORTB RB7:RB0 data setup time = (0.25TCY - TPD) where TCY = instruction cycle Port pin sampled here TPD = propagation delay Instruction TPD Therefore, at higher clock frequencies, executed NOP a write followed by a read may be prob- MOVWF PORTB MOVF PORTB,W lematic. write to PORTB (cid:211) 1997 Microchip Technology Inc. DS30390E-page 53

PIC16C7X 5.7 Parallel Slave Port FIGURE 5-11: PORTD AND PORTE BLOCK Applicable Devices DIAGRAM (PARALLEL SLAVE PORT) 727373A7474A7677 PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE Data bus (TRISE<4>) is set. In slave mode it is asynchronously D Q readable and writable by the external world through RD WR RDx PORT control input pin RE0/RD/AN5 and WR control input pin CK pin RE1/WR/AN6. TTL It can directly interface to an 8-bit microprocessor data Q D bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE RD ENEN enables port pin RE0/RD/AN5 to be the RD input, RE1/ PORT WR/AN6 to be the WR input and RE2/CS/AN7 to be the CS (chip select) input. For this functionality, the corre- One bit of PORTD sponding data direction bits of the TRISE register Set interrupt flag (TRISE<2:0>) must be configured as inputs (set) and PSPIF (PIR1<7>) the A/D port configuration bits PCFG2:PCFG0 (ADCON1<2:0>) must be set, which will configure pins RE2:RE0 as digital I/O. There are actually two 8-bit latches, one for data-out Read (from the PIC16/17) and one for data input. The user TTL RD writes 8-bit data to PORTD data latch and reads data Chip Select from the port pin latch (note that they have the same TTL CS address). In this mode, the TRISD register is ignored, Write since the microprocessor is controlling the direction of TTL WR data flow. A write to the PSP occurs when both the CS and WR Note: I/O pin has protection diodes to VDD and VSS. lines are first detected low. When either the CS or WR lines become high (level triggered), then the Input Buffer Full status flag bit IBF (TRISE<7>) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is complete (Figure 5-12). The interrupt flag bit PSPIF (PIR1<7>) is also set on the same Q4 clock cycle. IBF can only be cleared by reading the PORTD input latch. The input Buffer Overflow status flag bit IBOV (TRISE<5>) is set if a second write to the Parallel Slave Port is attempted when the previous byte has not been read out of the buffer. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full sta- tus flag bit OBF (TRISE<6>) is cleared immediately (Figure 5-13) indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware. When not in Parallel Slave Port mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previ- ously set, it must be cleared in firmware. An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>). DS30390E-page 54 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X FIGURE 5-12: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 5-13: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 08h PORTD Port data latch when written: Port pins when read xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 0Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 55

PIC16C7X NOTES: DS30390E-page 56 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 6.0 OVERVIEW OF TIMER CCP module, Timer1 is the time-base for 16-bit Cap- MODULES ture or the 16-bit Compare and must be synchronized to the device. Applicable Devices 727373A7474A7677 6.3 Timer2 Overview Applicable Devices The PIC16C72, PIC16C73/73A, PIC16C74/74A, PIC16C76/77 each have three timer modules. 727373A7474A7677 Each module can generate an interrupt to indicate that Timer2 is an 8-bit timer with a programmable prescaler an event has occurred (i.e. timer overflow). Each of and postscaler, as well as an 8-bit period register these modules is explained in full detail in the following (PR2). Timer2 can be used with the CCP1 module (in sections. The timer modules are: PWM mode) as well as the Baud Rate Generator for the Synchronous Serial Port (SSP). The prescaler • Timer0 Module (Section 7.0) option allows Timer2 to increment at the following • Timer1 Module (Section 8.0) rates: 1:1, 1:4, 1:16. • Timer2 Module (Section 9.0) The postscaler allows the TMR2 register to match the 6.1 Timer0 Overview period register (PR2) a programmable number of times before generating an interrupt. The postscaler can be Applicable Devices programmed from 1:1 to 1:16 (inclusive). 727373A7474A7677 6.4 CCP Overview The Timer0 module is a simple 8-bit overflow counter. The clock source can be either the internal system Applicable Devices clock (Fosc/4) or an external clock. When the clock 727373A7474A7677 source is an external clock, the Timer0 module can be The CCP module(s) can operate in one of these three selected to increment on either the rising or falling modes: 16-bit capture, 16-bit compare, or up to 10-bit edge. Pulse Width Modulation (PWM). The Timer0 module also has a programmable pres- Capture mode captures the 16-bit value of TMR1 into caler option. This prescaler can be assigned to either the CCPRxH:CCPRxL register pair. The capture event the Timer0 module or the Watchdog Timer. Bit PSA can be programmed for either the falling edge, rising (OPTION<3>) assigns the prescaler, and bits PS2:PS0 edge, fourth rising edge, or the sixteenth rising edge of (OPTION<2:0>) determine the prescaler value. Timer0 the CCPx pin. can increment at the following rates: 1:1 (when pres- caler assigned to Watchdog timer), 1:2, 1:4, 1:8, 1:16, Compare mode compares the TMR1H:TMR1L register 1:32, 1:64, 1:128, and 1:256 (Timer0 only). pair to the CCPRxH:CCPRxL register pair. When a match occurs an interrupt can be generated, and the Synchronization of the external clock occurs after the output pin CCPx can be forced to given state (High or prescaler. When the prescaler is used, the external Low), TMR1 can be reset (CCP1), or TMR1 reset and clock frequency may be higher then the device’s fre- start A/D conversion (CCP2). This depends on the con- quency. The maximum frequency is 50 MHz, given the trol bits CCPxM3:CCPxM0. high and low time requirements of the clock. PWM mode compares the TMR2 register to a 10-bit 6.2 Timer1 Overview duty cycle register (CCPRxH:CCPRxL<5:4>) as well as Applicable Devices to an 8-bit period register (PR2). When the TMR2 reg- ister = Duty Cycle register, the CCPx pin will be forced 727373A7474A7677 low. When TMR2 = PR2, TMR2 is cleared to 00h, an Timer1 is a 16-bit timer/counter. The clock source can interrupt can be generated, and the CCPx pin (if an out- be either the internal system clock (Fosc/4), an external put) will be forced high. clock, or an external crystal. Timer1 can operate as either a timer or a counter. When operating as a counter (external clock source), the counter can either operate synchronized to the device or asynchronously to the device. Asynchronous operation allows Timer1 to operate during sleep, which is useful for applications that require a real-time clock as well as the power sav- ings of SLEEP mode. Timer1 also has a prescaler option which allows Timer1 to increment at the following rates: 1:1, 1:2, 1:4, and 1:8. Timer1 can be used in conjunction with the Capture/Compare/PWM module. When used with a (cid:211) 1997 Microchip Technology Inc. DS30390E-page 57

PIC16C7X NOTES: DS30390E-page 58 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 7.0 TIMER0 MODULE Source Edge Select bit T0SE (OPTION<4>). Clearing Applicable Devices bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in 727373A7474A7677 Section 7.2. The Timer0 module timer/counter has the following fea- The prescaler is mutually exclusively shared between tures: the Timer0 module and the Watchdog Timer. The pres- • 8-bit timer/counter caler assignment is controlled in software by control bit • Readable and writable PSA (OPTION<3>). Clearing bit PSA will assign the • 8-bit software programmable prescaler prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to • Internal or external clock select the Timer0 module, prescale values of 1:2, 1:4, ..., • Interrupt on overflow from FFh to 00h 1:256 are selectable. Section 7.3 details the operation • Edge select for external clock of the prescaler. Figure 7-1 is a simplified block diagram of the Timer0 7.1 Timer0 Interrupt module. Applicable Devices Timer mode is selected by clearing bit T0CS (OPTION<5>). In timer mode, the Timer0 module will 727373A7474A7677 increment every instruction cycle (without prescaler). If The TMR0 interrupt is generated when the TMR0 reg- the TMR0 register is written, the increment is inhibited ister overflows from FFh to 00h. This overflow sets bit for the following two instruction cycles (Figure 7-2 and T0IF (INTCON<2>). The interrupt can be masked by Figure 7-3). The user can work around this by writing clearing bit T0IE (INTCON<5>). Bit T0IF must be an adjusted value to the TMR0 register. cleared in software by the Timer0 module interrupt ser- Counter mode is selected by setting bit T0CS vice routine before re-enabling this interrupt. The (OPTION<5>). In counter mode, Timer0 will increment TMR0 interrupt cannot awaken the processor from either on every rising or falling edge of pin RA4/T0CKI. SLEEP since the timer is shut off during SLEEP. See The incrementing edge is determined by the Timer0 Figure 7-4 for Timer0 interrupt timing. FIGURE 7-1: TIMER0 BLOCK DIAGRAM Data bus FOSC/4 0 PSout 8 1 Sync with 1 Internal TMR0 clocks RA4/T0CKI Programmable 0 PSout pin Prescaler T0SE (2 cycle delay) 3 Set interrupt PS2, PS1, PS0 PSA flag bit T0IF T0CS on overflow Note1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram). FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch TMR0 T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T0 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 59

PIC16C7X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch TMR0 T0 T0+1 NT0 NT0+1 PC+6 Instruction Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 FIGURE 7-4: TIMER0 INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) Timer0 FEh FFh 00h 01h 02h 1 1 T0IF bit (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC +1 PC +1 0004h 0005h Instruction fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h) Instruction executed Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h) Note 1: Interrupt flag bit T0IF is sampled here (every Q1). 2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. DS30390E-page 60 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 7.2 Using Timer0 with an External Clock When a prescaler is used, the external clock input is Applicable Devices divided by the asynchronous ripple-counter type pres- caler so that the prescaler output is symmetrical. For 727373A7474A7677 the external clock to meet the sampling requirement, When an external clock input is used for Timer0, it must the ripple-counter must be taken into account. There- meet certain requirements. The requirements ensure fore, it is necessary for T0CKI to have a period of at the external clock can be synchronized with the internal least 4Tosc (and a small RC delay of 40 ns) divided by phase clock (TOSC). Also, there is a delay in the actual the prescaler value. The only requirement on T0CKI incrementing of Timer0 after synchronization. high and low time is that they do not violate the mini- mum pulse width requirement of 10 ns. Refer to param- 7.2.1 EXTERNAL CLOCK SYNCHRONIZATION eters 40, 41 and 42 in the electrical specification of the desired device. When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization 7.2.2 TMR0 INCREMENT DELAY of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and Since the prescaler output is synchronized with the Q4 cycles of the internal phase clocks (Figure 7-5). internal clocks, there is a small delay from the time the Therefore, it is necessary for T0CKI to be high for at external clock edge occurs to the time the Timer0 mod- least 2Tosc (and a small RC delay of 20 ns) and low for ule is actually incremented. Figure 7-5 shows the delay at least 2Tosc (and a small RC delay of 20 ns). Refer to from the external clock edge to the timer incrementing. the electrical specification of the desired device. FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse External Clock Input or Prescaler output (2) misses sampling (1) (3) External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = – 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 61

PIC16C7X 7.3 Prescaler The PSA and PS2:PS0 bits (OPTION<3:0>) determine Applicable Devices the prescaler assignment and prescale ratio. 727373A7474A7677 When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, An 8-bit counter is available as a prescaler for the BSF 1,x....etc.) will clear the prescaler. When Timer0 module, or as a postscaler for the Watchdog assigned to WDT, a CLRWDT instruction will clear the Timer, respectively (Figure 7-6). For simplicity, this prescaler along with the Watchdog Timer. The pres- counter is being referred to as “prescaler” throughout caler is not readable or writable. this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between Note: Writing to TMR0 when the prescaler is the Timer0 module and the Watchdog Timer. Thus, a assigned to Timer0 will clear the prescaler prescaler assignment for the Timer0 module means count, but will not change the prescaler that there is no prescaler for the Watchdog Timer, and assignment. vice-versa. FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKOUT (=Fosc/4) Data Bus 8 M 0 1 RA4/T0CKI U M SYNC pin 1 X 0 U 2 TMR0 reg X Cycles T0SE T0CS PSA Set flag bit T0IF on Overflow 0 8-bit Prescaler M U Watchdog 1 X 8 Timer 8 - to - 1MUX PS2:PS0 PSA 0 1 WDT Enable bit M U X PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>). DS30390E-page 62 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 7.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol, i.e., it can be changed “on the fly” during program execution. Note: To avoid an unintended device RESET, the following instruction sequence (shown in Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. EXAMPLE 7-1: CHANGING PRESCALER (TIMER0fi WDT) 1) BSF STATUS, RP0 ;Bank 1 Lines 2 and 3 do NOT have to 2) MOVLW b'xx0x0xxx' ;Select clock source and prescale value of be included if the final desired 3) MOVWF OPTION_REG ;other than 1:1 prescale value is other than 1:1. 4) BCF STATUS, RP0 ;Bank 0 If 1:1 is final desired value, then 5) CLRF TMR0 ;Clear TMR0 and prescaler a temporary prescale value is set in lines 2 and 3 and the final 6) BSF STATUS, RP1 ;Bank 1 prescale value will be set in lines 7) MOVLW b'xxxx1xxx' ;Select WDT, do not change prescale value 10 and 11. 8) MOVWF OPTION_REG ; 9) CLRWDT ;Clears WDT and prescaler 10) MOVLW b'xxxx1xxx' ;Select new prescale value and WDT 11) MOVWF OPTION_REG ; 12) BCF STATUS, RP0 ;Bank 0 To change prescaler from the WDT to the Timer0 mod- ule use the sequence shown in Example 7-2. EXAMPLE 7-2: CHANGING PRESCALER (WDTfi TIMER0) CLRWDT ;Clear WDT and prescaler BSF STATUS, RP0 ;Bank 1 MOVLW b'xxxx0xxx' ;Select TMR0, new prescale value and MOVWF OPTION_REG ;clock source BCF STATUS, RP0 ;Bank 0 TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0 Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 01h,101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 81h,181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 63

PIC16C7X NOTES: DS30390E-page 64 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 8.0 TIMER1 MODULE In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising Applicable Devices edge of the external clock input. 727373A7474A7677 Timer1 can be enabled/disabled by setting/clearing The Timer1 module is a 16-bit timer/counter consisting control bit TMR1ON (T1CON<0>). of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 Register pair Timer1 also has an internal “reset input”. This reset can (TMR1H:TMR1L) increments from 0000h to FFFFh be generated by either of the two CCP modules and rolls over to 0000h. The TMR1 Interrupt, if enabled, (Section 10.0). Figure 8-1 shows the Timer1 control is generated on overflow which is latched in interrupt register. flag bit TMR1IF (PIR1<0>). This interrupt can be For the PIC16C72/73A/74A/76/77, when the Timer1 enabled/disabled by setting/clearing TMR1 interrupt oscillator is enabled (T1OSCEN is set), the RC1/ enable bit TMR1IE (PIE1<0>). T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become Timer1 can operate in one of two modes: inputs. That is, the TRISC<1:0> value is ignored. • As a timer For the PIC16C73/74, when the Timer1 oscillator is enabled (T1OSCEN is set), RC1/T1OSI/CCP2 pin • As a counter becomes an input, however the RC0/T1OSO/T1CKI The operating mode is determined by the clock select pin will have to be configured as an input by setting the bit, TMR1CS (T1CON<1>). TRISC<0> bit. FIGURE 8-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1CKPS1 T1CKPS0T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit W = Writable bit bit7 bit0 U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 65

PIC16C7X 8.1 Timer1 Operation in Timer Mode 8.2.1 EXTERNAL CLOCK INPUT TIMING FOR Applicable Devices SYNCHRONIZED COUNTER MODE 727373A7474A7677 When an external clock input is used for Timer1 in syn- Timer mode is selected by clearing the TMR1CS chronized counter mode, it must meet certain require- (T1CON<1>) bit. In this mode, the input clock to the ments. The external clock requirement is due to timer is FOSC/4. The synchronize control bit T1SYNC internal phase clock (Tosc) synchronization. Also, there (T1CON<2>) has no effect since the internal clock is is a delay in the actual incrementing of TMR1 after syn- always in sync. chronization. When the prescaler is 1:1, the external clock input is 8.2 Timer1 Operation in Synchronized the same as the prescaler output. The synchronization Counter Mode of T1CKI with the internal phase clocks is accom- Applicable Devices plished by sampling the prescaler output on the Q2 and 727373A7474A7677 Q4 cycles of the internal phase clocks. Therefore, it is necessary for T1CKI to be high for at least 2Tosc (and Counter mode is selected by setting bit TMR1CS. In a small RC delay of 20 ns) and low for at least 2Tosc this mode the timer increments on every rising edge of (and a small RC delay of 20 ns). Refer to the appropri- clock input on pin RC1/T1OSI/CCP2 when bit ate electrical specifications, parameters 45, 46, and 47. T1OSCEN is set or pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared. When a prescaler other than 1:1 is used, the external clock input is divided by the asynchronous ripple- If T1SYNC is cleared, then the external clock input is counter type prescaler so that the prescaler output is synchronized with internal phase clocks. The synchro- symmetrical. In order for the external clock to meet the nization is done after the prescaler stage. The pres- sampling requirement, the ripple-counter must be caler stage is an asynchronous ripple-counter. taken into account. Therefore, it is necessary for T1CKI In this configuration, during SLEEP mode, Timer1 will to have a period of at least 4Tosc (and a small RC delay not increment even if the external clock is present, of 40 ns) divided by the prescaler value. The only since the synchronization circuit is shut off. The pres- requirement on T1CKI high and low time is that they do caler however will continue to increment. not violate the minimum pulse width requirements of 10 ns). Refer to the appropriate electrical specifica- tions, parameters 40, 42, 45, 46, and 47. FIGURE 8-2: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow Synchronized TMR1 0 clock input TMR1H TMR1L 1 TMR1ON on/off T1SYNC T1OSC (3) RC0/T1OSO/T1CKI 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 RC1/T1OSI/CCP2(2) Oscillator(1) Clock 2 SLEEP input T1CKPS1:T1CKPS0 TMR1CS Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 2: The CCP2 module is not implemented in the PIC16C72. 3: For the PIC16C73 and PIC16C74, the Schmitt Trigger is not implemented in external clock mode. DS30390E-page 66 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 8.3 Timer1 Operation in Asynchronous EXAMPLE 8-1: READING A 16-BIT FREE- Counter Mode RUNNING TIMER Applicable Devices ; All interrupts are disabled 727373A7474A7677 MOVF TMR1H, W ;Read high byte If control bit T1SYNC (T1CON<2>) is set, the external MOVWF TMPH ; clock input is not synchronized. The timer continues to MOVF TMR1L, W ;Read low byte increment asynchronous to the internal phase clocks. MOVWF TMPL ; The timer will continue to run during SLEEP and can MOVF TMR1H, W ;Read high byte SUBWF TMPH, W ;Sub 1st read generate an interrupt on overflow which will wake-up ; with 2nd read the processor. However, special precautions in soft- BTFSC STATUS,Z ;Is result = 0 ware are needed to read/write the timer (Section 8.3.2). GOTO CONTINUE ;Good 16-bit read In asynchronous counter mode, Timer1 can not be ; used as a time-base for capture or compare operations. ; TMR1L may have rolled over between the read ; of the high and low bytes. Reading the high 8.3.1 EXTERNAL CLOCK INPUT TIMING WITH ; and low bytes now will read a good value. UNSYNCHRONIZED CLOCK ; MOVF TMR1H, W ;Read high byte If control bit T1SYNC is set, the timer will increment MOVWF TMPH ; completely asynchronously. The input clock must meet MOVF TMR1L, W ;Read low byte certain minimum high time and low time requirements. MOVWF TMPL ; ; Re-enable the Interrupt (if required) Refer to the appropriate Electrical Specifications Sec- CONTINUE ;Continue with your code tion, timing parameters 45, 46, and 47. 8.3.2 READING AND WRITING TIMER1 IN 8.4 Timer1 Oscillator ASYNCHRONOUS COUNTER MODE Applicable Devices 727373A7474A7677 Reading TMR1H or TMR1L while the timer is running, from an external asynchronous clock, will guarantee a A crystal oscillator circuit is built in between pins T1OSI valid read (taken care of in hardware). However, the (input) and T1OSO (amplifier output). It is enabled by user should keep in mind that reading the 16-bit timer setting control bit T1OSCEN (T1CON<3>). The oscilla- in two 8-bit values itself poses certain problems since tor is a low power oscillator rated up to 200 kHz. It will the timer may overflow between the reads. continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 8-1 shows the capacitor For writes, it is recommended that the user simply stop selection for the Timer1 oscillator. the timer and write the desired values. A write conten- tion may occur by writing to the timer registers while the The Timer1 oscillator is identical to the LP oscillator. register is incrementing. This may produce an unpre- The user must provide a software time delay to ensure dictable value in the timer register. proper oscillator start-up. Reading the 16-bit value requires some care. TABLE 8-1: CAPACITOR SELECTION Example 8-1 is an example routine to read the 16-bit FOR THE TIMER1 timer value. This is useful if the timer cannot be OSCILLATOR stopped. Osc Type Freq C1 C2 LP 32 kHz 33 pF 33 pF 100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF These values are for design guidance only. Crystals Tested: 32.768 kHz Epson C-001R32.768K-A – 20 PPM 100 kHz Epson C-2 100.00 KC-P – 20 PPM 200 kHz STD XTL 200.000 kHz – 20 PPM Note1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 67

PIC16C7X 8.5 Resetting Timer1 using a CCP Trigger 8.6 Resetting of Timer1 Register Pair Output (TMR1H, TMR1L) Applicable Devices Applicable Devices 727373A7474A7677 727373A7474A7677 The CCP2 module is not implemented on the TMR1H and TMR1L registers are not reset to 00h on a PIC16C72 device. POR or any other reset except by the CCP1 and CCP2 special event triggers. If the CCP1 or CCP2 module is configured in compare mode to generate a “special event trigger" T1CON register is reset to 00h on a Power-on Reset or (CCP1M3:CCP1M0 = 1011), this signal will reset a Brown-out Reset, which shuts off the timer and Timer1. leaves a 1:1 prescale. In all other resets, the register is unaffected. Note: The special event triggers from the CCP1 and CCP2 modules will not set interrupt 8.7 Timer1 Prescaler flag bit TMR1IF (PIR1<0>). Applicable Devices Timer1 must be configured for either timer or synchro- 727373A7474A7677 nized counter mode to take advantage of this feature. The prescaler counter is cleared on writes to the If Timer1 is running in asynchronous counter mode, this TMR1H or TMR1L registers. reset operation may not work. In the event that a write to Timer1 coincides with a spe- cial event trigger from CCP1 or CCP2, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL regis- ters pair effectively becomes the period register for Timer1. TABLE 8-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'. DS30390E-page 68 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 9.0 TIMER2 MODULE 9.1 Timer2 Prescaler and Postscaler Applicable Devices Applicable Devices 727373A7474A7677 727373A7474A7677 Timer2 is an 8-bit timer with a prescaler and a The prescaler and postscaler counters are cleared postscaler. It can be used as the PWM time-base for when any of the following occurs: PWM mode of the CCP module(s). The TMR2 register • a write to the TMR2 register is readable and writable, and is cleared on any device • a write to the T2CON register reset. • any device reset (Power-on Reset, MCLR reset, The input clock (FOSC/4) has a prescale option of 1:1, Watchdog Timer reset, or Brown-out Reset) 1:4 or 1:16, selected by control bits TMR2 is not cleared when T2CON is written. T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register PR2. 9.2 Output of TMR2 Timer2 increments from 00h until it matches PR2 and Applicable Devices then resets to 00h on the next increment cycle. PR2 is 727373A7474A7677 a readable and writable register. The PR2 register is ini- tialized to FFh upon reset. The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module which optionally uses The match output of TMR2 goes through a 4-bit it to generate shift clock. postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit FIGURE 9-1: TIMER2 BLOCK DIAGRAM TMR2IF, (PIR1<1>)). Sets flag Timer2 can be shut off by clearing control bit TMR2ON bit TMR2IF ToMutRpu2t (1) (T2CON<2>) to minimize power consumption. Figure 9-2 shows the Timer2 control register. Reset Prescaler TMR2 reg FOSC/4 1:1, 1:4, 1:16 Postscaler Comparator 2 1:1 to 1:16 EQ 4 PR2 reg Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 69

PIC16C7X FIGURE 9-2: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3TOUTPS2TOUTPS1TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2: TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'. DS30390E-page 70 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 10.0 CAPTURE/COMPARE/PWM CCP1 module: MODULE(s) Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and Applicable Devices CCPR1H (high byte). The CCP1CON register controls 7273 73A 74 74A 7677 CCP1 the operation of CCP1. All are readable and writable. 7273 73A 74 74A 7677 CCP2 CCP2 module: Each CCP (Capture/Compare/PWM) module contains Capture/Compare/PWM Register2 (CCPR2) is com- a 16-bit register which can operate as a 16-bit capture prised of two 8-bit registers: CCPR2L (low byte) and register, as a 16-bit compare register or as a PWM CCPR2H (high byte). The CCP2CON register controls master/slave Duty Cycle register. Both the CCP1 and the operation of CCP2. All are readable and writable. CCP2 modules are identical in operation, with the exception of the operation of the special event trigger. For use of the CCP modules, refer to the Embedded Table 10-1 and Table 10-2 show the resources and Control Handbook, "Using the CCP Modules" (AN594). interactions of the CCP module(s). In the following sec- TABLE 10-1: CCP MODE - TIMER tions, the operation of a CCP module is described with RESOURCE respect to CCP1. CCP2 operates the same as CCP1, except where noted. CCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2 TABLE 10-2: INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture Same TMR1 time-base. Capture Compare The compare should be configured for the special event trigger, which clears TMR1. Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1. PWM PWM The PWMs will have the same frequency, and update rate (TMR2 interrupt). PWM Capture None PWM Compare None (cid:211) 1997 Microchip Technology Inc. DS30390E-page 71

PIC16C7X FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h)/CCP2CON REGISTER (ADDRESS 1Dh) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 R = Readable bit bit7 bit0 W =Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: CCPxX:CCPxY: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode 10.1 Capture Mode FIGURE 10-2: CAPTURE MODE Applicable Devices OPERATION BLOCK DIAGRAM 727373A7474A7677 In Capture mode, CCPR1H:CCPR1L captures the Set flag bit CCP1IF 16-bit value of the TMR1 register when an event occurs Prescaler (PIR1<2>) on pin RC2/CCP1. An event is defined as: ‚ 1, 4, 16 RC2/CCP1 CCPR1H CCPR1L • Every falling edge Pin • Every rising edge and Capture • Every 4th rising edge edge detect Enable • Every 16th rising edge TMR1H TMR1L CCP1CON<3:0> An event is selected by control bits CCP1M3:CCP1M0 Q’s (CCP1CON<3:0>). When a capture is made, the inter- rupt request flag bit CCP1IF (PIR1<2>) is set. It must 10.1.2 TIMER1 MODE SELECTION be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured Timer1 must be running in timer mode or synchronized value will be lost. counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture 10.1.1 CCP PIN CONFIGURATION operation may not work. In Capture mode, the RC2/CCP1 pin should be config- 10.1.3 SOFTWARE INTERRUPT ured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 is configured as an out- When the Capture mode is changed, a false capture put, a write to the port can cause a capture interrupt may be generated. The user should keep bit condition. CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode. DS30390E-page 72 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 10.1.4 CCP PRESCALER 10.2.1 CCP PIN CONFIGURATION There are four prescaler settings, specified by bits The user must configure the RC2/CCP1 pin as an out- CCP1M3:CCP1M0. Whenever the CCP module is put by clearing the TRISC<2> bit. turned off, or the CCP module is not in capture mode, Note: Clearing the CCP1CON register will force the prescaler counter is cleared. This means that any the RC2/CCP1 compare output latch to the reset will clear the prescaler counter. default low level. This is not the data latch. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will 10.2.2 TIMER1 MODE SELECTION not be cleared, therefore the first capture may be from Timer1 must be running in Timer mode or Synchro- a non-zero prescaler. Example 10-1 shows the recom- nized Counter mode if the CCP module is using the mended method for switching between capture pres- compare feature. In Asynchronous Counter mode, the calers. This example also clears the prescaler counter compare operation may not work. and will not generate the “false” interrupt. 10.2.3 SOFTWARE INTERRUPT MODE EXAMPLE 10-1: CHANGING BETWEEN CAPTURE PRESCALERS When generate software interrupt is chosen the CCP1 pin is not affected. Only a CCP interrupt is generated (if CLRF CCP1CON ;Turn CCP module off enabled). MOVLW NEW_CAPT_PS ;Load the W reg with ; the new prescaler 10.2.4 SPECIAL EVENT TRIGGER ; mode value and CCP ON MOVWF CCP1CON ;Load CCP1CON with this In this mode, an internal hardware trigger is generated ; value which may be used to initiate an action. 10.2 Compare Mode The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to Applicable Devices effectively be a 16-bit programmable period register for 727373A7474A7677 Timer1. In Compare mode, the 16-bit CCPR1 register value is The special trigger output of CCP2 resets the TMR1 constantly compared against the TMR1 register pair register pair, and starts an A/D conversion (if the A/D value. When a match occurs, the RC2/CCP1 pin is: module is enabled). • Driven High For the PIC16C72 only, the special event trigger output • Driven Low of CCP1 resets the TMR1 register pair, and starts an • Remains Unchanged A/D conversion (if the A/D module is enabled). The action on the pin is based on the value of control Note: The special event trigger from the bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the CCP1and CCP2 modules will not set inter- same time, interrupt flag bit CCP1IF is set. rupt flag bit TMR1IF (PIR1<0>). FIGURE 10-3: COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion (CCP1 only for PIC16C72, CCP2 only for PIC16C73/73A/74/74A/76/77). Special Event Trigger Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Q S Output RC2/CCP1 R Logic match Comparator Pin TRISC<2> TMR1H TMR1L Output Enable CCP1CON<3:0> Mode Select (cid:211) 1997 Microchip Technology Inc. DS30390E-page 73

PIC16C7X 10.3 PWM Mode 10.3.1 PWM PERIOD Applicable Devices The PWM period is specified by writing to the PR2 reg- 727373A7474A7677 ister. The PWM period can be calculated using the fol- In Pulse Width Modulation (PWM) mode, the CCPx pin lowing formula: produces up to a 10-bit resolution PWM output. Since PWM period = [(PR2) + 1] • 4 • TOSC • the CCP1 pin is multiplexed with the PORTC data latch, (TMR2 prescale value) the TRISC<2> bit must be cleared to make the CCP1 PWM frequency is defined as 1 / [PWM period]. pin an output. When TMR2 is equal to PR2, the following three events Note: Clearing the CCP1CON register will force occur on the next increment cycle: the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data • TMR2 is cleared latch. • The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) Figure 10-4 shows a simplified block diagram of the CCP module in PWM mode. • The PWM duty cycle is latched from CCPR1L into CCPR1H For a step by step procedure on how to set up the CCP module for PWM operation, see Section 10.3.3. Note: The Timer2 postscaler (see Section 9.1) is FIGURE 10-4: SIMPLIFIED PWM BLOCK not used in the determination of the PWM DIAGRAM frequency. The postscaler could be used to have a servo update rate at a different fre- Duty cycle registers CCP1CON<5:4> quency than the PWM output. CCPR1L 10.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains CCPR1H (Slave) the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by Comparator R Q CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: RC2/CCP1 TMR2 (Note 1) PWM duty cycle = (CCPR1L:CCP1CON<5:4>) • S Tosc • (TMR2 prescale value) Comparator TRISC<2> CCPR1L and CCP1CON<5:4> can be written to at any Clear Timer, time, but the duty cycle value is not latched into CCP1 pin and latch D.C. CCPR1H until after a match between PR2 and TMR2 PR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double A PWM output (Figure 10-5) has a time base (period) buffering is essential for glitchless PWM operation. and a time that the output stays high (duty cycle). The When the CCPR1H and 2-bit latch match TMR2 con- frequency of the PWM is the inverse of the period catenated with an internal 2-bit Q clock or 2 bits of the (1/period). TMR2 prescaler, the CCP1 pin is cleared. FIGURE 10-5: PWM OUTPUT Maximum PWM resolution (bits) for a given PWM frequency: Period ( FOSC ) log FPWM = bits log(2) Duty Cycle TMR2 = PR2 Note: If the PWM duty cycle value is longer than TMR2 = Duty Cycle the PWM period the CCP1 pin will not be cleared. TMR2 = PR2 DS30390E-page 74 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X EXAMPLE 10-2: PWM PERIOD AND DUTY In order to achieve higher resolution, the PWM fre- CYCLE CALCULATION quency must be decreased. In order to achieve higher PWM frequency, the resolution must be decreased. Desired PWM frequency is 78.125 kHz, Fosc = 20 MHz Table 10-3 lists example PWM frequencies and resolu- TMR2 prescale = 1 tions for Fosc = 20 MHz. The TMR2 prescaler and PR2 values are also shown. 1/78.125 kHz= [(PR2) + 1] • 4 • 1/20 MHz • 1 12.8 m s = [(PR2) + 1] • 4 • 50 ns • 1 10.3.3 SET-UP FOR PWM OPERATION PR2 = 63 The following steps should be taken when configuring Find the maximum resolution of the duty cycle that can the CCP module for PWM operation: be used with a 78.125 kHz frequency and 20 MHz 1. Set the PWM period by writing to the PR2 regis- oscillator: ter. 1/78.125 kHz= 2PWM RESOLUTION • 1/20 MHz • 1 2. Set the PWM duty cycle by writing to the 12.8 m s = 2PWM RESOLUTION • 50 ns • 1 CCPR1L register and CCP1CON<5:4> bits. 3. Make the CCP1 pin an output by clearing the 256 = 2PWM RESOLUTION TRISC<2> bit. log(256) = (PWM Resolution) • log(2) 4. Set the TMR2 prescale value and enable Timer2 8.0 = PWM Resolution by writing to T2CON. 5. Configure the CCP1 module for PWM operation. At most, an 8-bit resolution duty cycle can be obtained from a 78.125 kHz frequency and a 20 MHz oscillator, i.e., 0 £ CCPR1L:CCP1CON<5:4> £ 255. Any value greater than 255 will result in a 100% duty cycle. TABLE 10-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 5.5 TABLE 10-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh(2) PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh(2) PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh(2) CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu 1Ch(2) CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu 1Dh(2) CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 75

PIC16C7X TABLE 10-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh(2) PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh(2) PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 92h PR2 Timer2 module’s period register 1111 1111 1111 1111 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh(2) CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu 1Ch(2) CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu 1Dh(2) CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'. DS30390E-page 76 (cid:211) 1997 Microchip Technology Inc.

Applicable Devices PIC16C7X 727373A7474A7677 11.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE 11.1 SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc. The SSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) The SSP module in I2C mode works the same in all PIC16C7X devices that have an SSP module. However the SSP Module in SPI mode has differences between the PIC16C76/77 and the other PIC16C7X devices. The register definitions and operational description of SPI mode has been split into two sections because of the differences between the PIC16C76/77 and the other PIC16C7X devices. The default reset values of both the SPI modules is the same regardless of the device: 11.2 SPI Mode for PIC16C72/73/73A/74/74A..........78 11.3 SPI Mode for PIC16C76/77..............................83 11.4 I2C™ Overview................................................89 11.5 SSP I2C Operation...........................................93 Refer to Application Note AN578, “Use of the SSP Module in the I2C Multi-Master Environment.” (cid:211) 1997 Microchip Technology Inc. DS30390E-page 77

PIC16C7X Applicable Devices 727373A7474A7677 11.2 SPI Mode for PIC16C72/73/73A/74/74A This section contains register definitions and opera- tional characteristics of the SPI module for the PIC16C72, PIC16C73, PIC16C73A, PIC16C74, PIC16C74A. FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — D/A P S R/W UA BF R = Readable bit bit7 bit0 W =Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty DS30390E-page 78 (cid:211) 1997 Microchip Technology Inc.

Applicable Devices PIC16C7X 727373A7474A7677 FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit bit7 bit0 W =Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Detect bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR register is lost. Overflow can only occur in slave mode. The user must read the SSP- BUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge. 0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge. In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master mode, clock = Fosc/4 0001 = SPI master mode, clock = Fosc/16 0010 = SPI master mode, clock = Fosc/64 0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled Master Mode (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled (cid:211) 1997 Microchip Technology Inc. DS30390E-page 79

PIC16C7X Applicable Devices 727373A7474A7677 11.2.1 OPERATION OF SSP MODULE IN SPI EXAMPLE 11-1: LOADING THE SSPBUF MODE (SSPSR) REGISTER Applicable Devices BSF STATUS, RP0 ;Specify Bank 1 727373A7474A7677 LOOP BTFSS SSPSTAT, BF ;Has data been ;received The SPI mode allows 8-bits of data to be synchro- ;(transmit nously transmitted and received simultaneously. To ;complete)? accomplish communication, typically three pins are GOTO LOOP ;No used: BCF STATUS, RP0 ;Specify Bank 0 • Serial Data Out (SDO) MOVF SSPBUF, W ;W reg = contents • Serial Data In (SDI) ;of SSPBUF • Serial Clock (SCK) MOVWF RXDATA ;Save in user RAM MOVF TXDATA, W ;W reg = contents Additionally a fourth pin may be used when in a slave ; of TXDATA mode of operation: MOVWF SSPBUF ;New data to xmit • Slave Select (SS) The block diagram of the SSP module, when in SPI When initializing the SPI, several options need to be mode (Figure 11-3), shows that the SSPSR register is specified. This is done by programming the appropriate not directly readable or writable, and can only be control bits in the SSPCON register (SSPCON<5:0>). accessed from addressing the SSPBUF register. Addi- These control bits allow the following to be specified: tionally, the SSP status register (SSPSTAT) indicates • Master Mode (SCK is the clock output) the various status conditions. • Slave Mode (SCK is the clock input) FIGURE 11-3: SSP BLOCK DIAGRAM • Clock Polarity (Output/Input data on the Rising/ (SPI MODE) Falling edge of SCK) • Clock Rate (Master mode only) • Slave Select Mode (Slave mode only) Internal data bus The SSP consists of a transmit/receive Shift Register (SSPSR) and a Buffer register (SSPBUF). The SSPSR Read Write shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, SSPBUF reg until the received data is ready. Once the 8-bits of data have been received, that byte is moved to the SSPBUF register. Then the Buffer Full bit, BF (SSPSTAT<0>) and flag bit SSPIF are set. This double buffering of the SSPSR reg received data (SSPBUF) allows the next byte to start RC4/SDI/SDA bit0 shift reception before reading the data that was just clock received. Any write to the SSPBUF register during transmission/reception of data will be ignored, and the RC5/SDO write collision detect bit, WCOL (SSPCON<7>) will be set. User software must clear bit WCOL so that it can be determined if the following write(s) to the SSPBUF SS Control Enable completed successfully. When the application software is expecting to receive valid data, the SSPBUF register RA5/SS/AN4 Edge should be read before the next byte of data to transfer Select is written to the SSPBUF register. The Buffer Full bit BF (SSPSTAT<0>) indicates when the SSPBUF register 2 Clock Select has been loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is SSPM3:SSPM0 cleared. This data may be irrelevant if the SPI is only a TMR2 output transmitter. Generally the SSP Interrupt is used to 4 2 determine when the transmission/reception has com- Edge pleted. The SSPBUF register must be read and/or writ- Select Prescaler TCY ten. If the interrupt method is not going to be used, then RC3/SCK/ 4, 16, 64 software polling can be done to ensure that a write col- SCL lision does not occur. Example 11-1 shows the loading TRISC<3> of the SSPBUF (SSPSR) register for data transmission. The shaded instruction is only required if the received data is meaningful. DS30390E-page 80 (cid:211) 1997 Microchip Technology Inc.

Applicable Devices PIC16C7X 727373A7474A7677 To enable the serial port, SSP enable bit SSPEN The master can initiate the data transfer at any time (SSPCON<5>) must be set. To reset or reconfigure SPI because it controls the SCK. The master determines mode, clear enable bit SSPEN, re-initialize SSPCON when the slave (Processor 2) is to broadcast data by register, and then set enable bit SSPEN. This config- the software protocol. ures the SDI, SDO, SCK, and SS pins as serial port In master mode the data is transmitted/received as pins. For the pins to behave as the serial port function, soon as the SSPBUF register is written to. If the SPI is they must have their data direction bits (in the TRIS reg- only going to receive, the SCK output could be disabled ister) appropriately programmed. That is: (programmed as an input). The SSPSR register will • SDI must have TRISC<4> set continue to shift in the signal present on the SDI pin at • SDO must have TRISC<5> cleared the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal • SCK (Master mode) must have TRISC<3> received byte (interrupts and status bits appropriately cleared set). This could be useful in receiver applications as a • SCK (Slave mode) must have TRISC<3> set “line activity monitor” mode. • SS must have TRISA<5> set (if implemented) In slave mode, the data is transmitted and received as Any serial port function that is not desired may be over- the external clock pulses appear on SCK. When the ridden by programming the corresponding data direc- last bit is latched interrupt flag bit SSPIF (PIR1<3>) is tion (TRIS) register to the opposite value. An example set. would be in master mode where you are only sending The clock polarity is selected by appropriately program- data (to a display driver), then both SDI and SS could ming bit CKP (SSPCON<4>). This then would give be used as general purpose outputs by clearing their waveforms for SPI communication as shown in corresponding TRIS register bits. Figure 11-5 and Figure 11-6 where the MSB is trans- Figure 11-4 shows a typical connection between two mitted first. In master mode, the SPI clock rate (bit rate) microcontrollers. The master controller (Processor 1) is user programmable to be one of the following: initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- • Fosc/4 (or TCY) grammed clock edge, and latched on the opposite edge • Fosc/16 (or 4 • TCY) of the clock. Both processors should be programmed to • Fosc/64 (or 16 • TCY) the same Clock Polarity (CKP), then both controllers • Timer2 output/2 would send and receive data at the same time. This allows a maximum bit clock frequency (at 20 MHz) Whether the data is meaningful (or dummy data) of 5 MHz. When in slave mode the external clock must depends on the application software. This leads to meet the minimum high and low times. three scenarios for data transmission: In sleep mode, the slave can transmit and receive data • Master sends data — Slave sends dummy data and wake the device from sleep. • Master sends data — Slave sends data • Master sends dummy data — Slave sends data FIGURE 11-4: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF register) (SSPBUF register) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 81

PIC16C7X Applicable Devices 727373A7474A7677 The SS pin allows a synchronous slave mode. The point at which it was taken high. External pull-up/ SPI must be in slave mode (SSPCON<3:0> = 04h) pull-down resistors may be desirable, depending on the and the TRISA<5> bit must be set the for synchro- application. nous slave mode to be enabled. When the SS pin is To emulate two-wire communication, the SDO pin can low, transmission and reception are enabled and be connected to the SDI pin. When the SPI needs to the SDO pin is driven. When the SS pin goes high, operate as a receiver the SDO pin can be configured as the SDO pin is no longer driven, even if in the mid- an input. This disables transmissions from the SDO. dle of a transmitted byte, and becomes a floating The SDI can always be left as an input (SDI function) output. If the SS pin is taken low without resetting since it cannot create a bus conflict. SPI mode, the transmission will continue from the FIGURE 11-5: SPI MODE TIMING, MASTER MODE OR SLAVE MODE W/O SS CONTROL SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI bit7 bit0 SSPIF FIGURE 11-6: SPI MODE TIMING, SLAVE MODE WITH SS CONTROL SS SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI bit7 bit0 SSPIF TABLE 11-1: REGISTERS ASSOCIATED WITH SPI OPERATION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port or USART, these bits are unimplemented, read as '0'. DS30390E-page 82 (cid:211) 1997 Microchip Technology Inc.

Applicable Devices PIC16C7X 727373A7474A7677 11.3 SPI Mode for PIC16C76/77 This section contains register definitions and opera- tional characteristics of the SPI module on the PIC16C76 and PIC16C77 only. FIGURE 11-7: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)(PIC16C76/77) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF R = Readable bit W =Writable bit bit7 bit0 U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: SMP: SPI data input sample phase SPI Master Mode 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode bit 6: CKE: SPI Clock Edge Select (Figure 11-11, Figure 11-12, and Figure 11-13) CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is detected last, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty (cid:211) 1997 Microchip Technology Inc. DS30390E-page 83

PIC16C7X Applicable Devices 727373A7474A7677 FIGURE 11-8: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)(PIC16C76/77) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit W =Writable bit bit7 bit0 U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Indicator bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master mode, clock = FOSC/4 0001 = SPI master mode, clock = FOSC/16 0010 = SPI master mode, clock = FOSC/64 0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled master mode (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled DS30390E-page 84 (cid:211) 1997 Microchip Technology Inc.

Applicable Devices PIC16C7X 727373A7474A7677 11.3.1 SPI MODE FOR PIC16C76/77 EXAMPLE 11-2: LOADING THE SSPBUF (SSPSR) REGISTER The SPI mode allows 8-bits of data to be synchro- (PIC16C76/77) nously transmitted and received simultaneously. To accomplish communication, typically three pins are BCF STATUS, RP1 ;Specify Bank 1 used: BSF STATUS, RP0 ; • Serial Data Out (SDO) RC5/SDO LOOP BTFSS SSPSTAT, BF ;Has data been ;received • Serial Data In (SDI) RC4/SDI/SDA ;(transmit • Serial Clock (SCK) RC3/SCK/SCL ;complete)? Additionally a fourth pin may be used when in a slave GOTO LOOP ;No mode of operation: BCF STATUS, RP0 ;Specify Bank 0 MOVF SSPBUF, W ;W reg = contents • Slave Select (SS) RA5/SS/AN4 ; of SSPBUF MOVWF RXDATA ;Save in user RAM When initializing the SPI, several options need to be specified. This is done by programming the appropriate MOVF TXDATA, W ;W reg = contents control bits in the SSPCON register (SSPCON<5:0>) ; of TXDATA MOVWF SSPBUF ;New data to xmit and SSPSTAT<7:6>. These control bits allow the fol- lowing to be specified: The block diagram of the SSP module, when in SPI • Master Mode (SCK is the clock output) mode (Figure 11-9), shows that the SSPSR is not • Slave Mode (SCK is the clock input) directly readable or writable, and can only be accessed from addressing the SSPBUF register. Additionally, the • Clock Polarity (Idle state of SCK) SSP status register (SSPSTAT) indicates the various • Clock edge (output data on rising/falling edge of status conditions. SCK) • Clock Rate (Master mode only) FIGURE 11-9: SSP BLOCK DIAGRAM • Slave Select Mode (Slave mode only) (SPI MODE)(PIC16C76/77) The SSP consists of a transmit/receive Shift Register Internal (SSPSR) and a buffer register (SSPBUF). The SSPSR data bus shifts the data in and out of the device, MSb first. The Read Write SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the 8-bits of data SSPBUF reg have been received, that byte is moved to the SSPBUF register. Then the buffer full detect bit BF (SSPSTAT<0>) and interrupt flag bit SSPIF (PIR1<3>) are set. This double buffering of the received data SSPSR reg (SSPBUF) allows the next byte to start reception before RC4/SDI/SDA bit0 shift reading the data that was just received. Any write to the clock SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit WCOL RC5/SDO (SSPCON<7>) will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed success- SS Control fully. When the application software is expecting to Enable receive valid data, the SSPBUF should be read before RA5/SS/AN4 Edge the next byte of data to transfer is written to the Select SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates when SSPBUF has been loaded with the received data 2 (transmission is complete). When the SSPBUF is read, Clock Select bit BF is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally the SSP Interrupt is SSPM3:SSPM0 TMR2 output used to determine when the transmission/reception 4 2 has completed. The SSPBUF must be read and/or writ- Edge ten. If the interrupt method is not going to be used, then software polling can be done to ensure that a write col- Select Prescaler TCY RC3/SCK/ 4, 16, 64 lision does not occur. Example 11-2 shows the loading SCL of the SSPBUF (SSPSR) for data transmission. The TRISC<3> shaded instruction is only required if the received data is meaningful. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 85

PIC16C7X Applicable Devices 727373A7474A7677 To enable the serial port, SSP Enable bit, SSPEN The master can initiate the data transfer at any time (SSPCON<5>) must be set. To reset or reconfigure SPI because it controls the SCK. The master determines mode, clear bit SSPEN, re-initialize the SSPCON reg- when the slave (Processor 2) is to broadcast data by ister, and then set bit SSPEN. This configures the SDI, the firmware protocol. SDO, SCK, and SS pins as serial port pins. For the pins In master mode the data is transmitted/received as to behave as the serial port function, they must have soon as the SSPBUF register is written to. If the SPI is their data direction bits (in the TRISC register) appro- only going to receive, the SCK output could be disabled priately programmed. That is: (programmed as an input). The SSPSR register will • SDI must have TRISC<4> set continue to shift in the signal present on the SDI pin at • SDO must have TRISC<5> cleared the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal • SCK (Master mode) must have TRISC<3> received byte (interrupts and status bits appropriately cleared set). This could be useful in receiver applications as a • SCK (Slave mode) must have TRISC<3> set “line activity monitor” mode. • SS must have TRISA<5> set In slave mode, the data is transmitted and received as Any serial port function that is not desired may be over- the external clock pulses appear on SCK. When the ridden by programming the corresponding data direc- last bit is latched the interrupt flag bit SSPIF (PIR1<3>) tion (TRIS) register to the opposite value. An example is set. would be in master mode where you are only sending The clock polarity is selected by appropriately program- data (to a display driver), then both SDI and SS could ming bit CKP (SSPCON<4>). This then would give be used as general purpose outputs by clearing their waveforms for SPI communication as shown in corresponding TRIS register bits. Figure 11-11, Figure 11-12, and Figure 11-13 where Figure 11-10 shows a typical connection between two the MSB is transmitted first. In master mode, the SPI microcontrollers. The master controller (Processor 1) clock rate (bit rate) is user programmable to be one of initiates the data transfer by sending the SCK signal. the following: Data is shifted out of both shift registers on their pro- grammed clock edge, and latched on the opposite edge • FOSC/4 (or TCY) of the clock. Both processors should be programmed to • FOSC/16 (or 4 • TCY) same Clock Polarity (CKP), then both controllers would • FOSC/64 (or 16 • TCY) send and receive data at the same time. Whether the • Timer2 output/2 data is meaningful (or dummy data) depends on the This allows a maximum bit clock frequency (at 20 MHz) application firmware. This leads to three scenarios for of 5 MHz. When in slave mode the external clock must data transmission: meet the minimum high and low times. • Master sends data — Slave sends dummy data In sleep mode, the slave can transmit and receive data • Master sends data — Slave sends data and wake the device from sleep. • Master sends dummy data — Slave sends data FIGURE 11-10:SPI MASTER/SLAVE CONNECTION (PIC16C76/77) SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2 DS30390E-page 86 (cid:211) 1997 Microchip Technology Inc.

Applicable Devices PIC16C7X 727373A7474A7677 The SS pin allows a synchronous slave mode. The . SPI must be in slave mode (SSPCON<3:0> = 04h) Note: When the SPI is in Slave Mode with SS pin and the TRISA<5> bit must be set for the synchro- control enabled, (SSPCON<3:0> = 0100) nous slave mode to be enabled. When the SS pin is the SPI module will reset if the SS pin is set low, transmission and reception are enabled and to VDD. the SDO pin is driven. When the SS pin goes high, Note: If the SPI is used in Slave Mode with the SDO pin is no longer driven, even if in the mid- CKE = '1', then the SS pin control must be dle of a transmitted byte, and becomes a floating enabled. output. If the SS pin is taken low without resetting SPI mode, the transmission will continue from the To emulate two-wire communication, the SDO pin can point at which it was taken high. External pull-up/ be connected to the SDI pin. When the SPI needs to pull-down resistors may be desirable, depending on the operate as a receiver the SDO pin can be configured as application. an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. FIGURE 11-11:SPI MODE TIMING, MASTER MODE (PIC16C76/77) SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF FIGURE 11-12:SPI MODE TIMING (SLAVE MODE WITH CKE = 0) (PIC16C76/77) SS (optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF (cid:211) 1997 Microchip Technology Inc. DS30390E-page 87

PIC16C7X Applicable Devices 727373A7474A7677 FIGURE 11-13:SPI MODE TIMING (SLAVE MODE WITH CKE = 1) (PIC16C76/77) SS (not optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 11-2: REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16C76/77) Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh. INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. DS30390E-page 88 (cid:211) 1997 Microchip Technology Inc.

Applicable Devices PIC16C7X 727373A7474A7677 11.4 I2C™ Overview In both cases the master generates the clock signal. The output stages of the clock (SCL) and data (SDA) This section provides an overview of the Inter-Inte- grated Circuit (I2C) bus, with Section 11.5 discussing lines must have an open-drain or open-collector in the operation of the SSP module in I2C mode. order to perform the wired-AND function of the bus. External pull-up resistors are used to ensure a high The I2C bus is a two-wire serial interface developed by level when no device is pulling the line down. The num- the Philips Corporation. The original specification, or ber of devices that may be attached to the I2C bus is standard mode, was for data transfers of up to 100 limited only by the maximum bus loading specification Kbps. The enhanced specification (fast mode) is also of 400 pF. supported. This device will communicate with both standard and fast mode devices if attached to the same 11.4.1 INITIATING AND TERMINATING DATA bus. The clock will determine the data rate. TRANSFER The I2C interface employs a comprehensive protocol to During times of no data transfer (idle time), both the ensure reliable transmission and reception of data. clock line (SCL) and the data line (SDA) are pulled high When transmitting data, one device is the “master” through the external pull-up resistors. The START and which initiates transfer on the bus and generates the STOP conditions determine the start and stop of data clock signals to permit that transfer, while the other transmission. The START condition is defined as a high device(s) acts as the “slave.” All portions of the slave to low transition of the SDA when the SCL is high. The protocol are implemented in the SSP module’s hard- STOP condition is defined as a low to high transition of ware, except general call support, while portions of the the SDA when the SCL is high. Figure 11-14 shows the master protocol need to be addressed in the START and STOP conditions. The master generates PIC16CXX software. Table 11-3 defines some of the these conditions for starting and terminating data trans- I2C bus terminology. For additional information on the fer. Due to the definition of the START and STOP con- I2C interface specification, refer to the Philips docu- ditions, when data is being transmitted, the SDA line ment “The I2C bus and how to use it.” #939839340011, can only change state when the SCL line is low. which can be obtained from the Philips Corporation. In the I2C interface protocol each device has an FIGURE 11-14:START AND STOP address. When a master wishes to initiate a data trans- CONDITIONS fer, it first transmits the address of the device that it wishes to “talk” to. All devices “listen” to see if this is their address. Within this address, a bit specifies if the master wishes to read-from/write-to the slave device. SDA The master and slave are always in opposite modes (transmitter/receiver) of operation during a data trans- SCL S P fer. That is they can be thought of as operating in either of these two relations: Start Change Change Stop Condition of Data of Data Condition • Master-transmitter and Slave-receiver Allowed Allowed • Slave-transmitter and Master-receiver TABLE 11-3: I2C BUS TERMINOLOGY Term Description Transmitter The device that sends the data to the bus. Receiver The device that receives the data from the bus. Master The device which initiates the transfer, generates the clock and terminates the transfer. Slave The device addressed by a master. Multi-master More than one master device in a system. These masters can attempt to control the bus at the same time without corrupting the message. Arbitration Procedure that ensures that only one of the master devices will control the bus. This ensure that the transfer data does not get corrupted. Synchronization Procedure where the clock signals of two or more devices are synchronized. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 89

PIC16C7X Applicable Devices 727373A7474A7677 11.4.2 ADDRESSING I2C DEVICES FIGURE 11-17:SLAVE-RECEIVER ACKNOWLEDGE There are two address formats. The simplest is the 7-bit address format with a R/W bit (Figure 11-15). The Data more complex is the 10-bit address with a R/W bit Output by Transmitter (Figure 11-16). For 10-bit address format, two bytes Data not acknowledge must be transmitted with the first five bits specifying this Output by to be a 10-bit address. Receiver acknowledge SCL from FIGURE 11-15:7-BIT ADDRESS FORMAT Master 1 2 8 9 S MSb LSb Start Clock Pulse for Condition Acknowledgment S R/W ACK slave address Sent by If the master is receiving the data (master-receiver), it Slave generates an acknowledge signal for each received S Start Condition byte of data, except for the last byte. To signal the end R/W Read/Write pulse of data to the slave-transmitter, the master does not ACK Acknowledge generate an acknowledge (not acknowledge). The slave then releases the SDA line so the master can generate the STOP condition. The master can also FIGURE 11-16:I2C 10-BIT ADDRESS FORMAT generate the STOP condition during the acknowledge pulse for valid termination of data transfer. S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK If the slave needs to delay the transmission of the next sent by slave byte, holding the SCL line low will force the master into = 0 for write a wait state. Data transfer continues when the slave S - Start Condition releases the SCL line. This allows the slave to move the R/W - Read/Write Pulse ACK - Acknowledge received data or fetch the data it needs to transfer before allowing the clock to start. This wait state tech- nique can also be implemented at the bit level, 11.4.3 TRANSFER ACKNOWLEDGE Figure 11-18. The slave will inherently stretch the clock, when it is a transmitter, but will not when it is a receiver. All data must be transmitted per byte, with no limit to the The slave will have to clear the SSPCON<4> bit to number of bytes transmitted per data transfer. After enable clock stretching when it is a receiver. each byte, the slave-receiver generates an acknowl- edge bit (ACK) (Figure 11-17). When a slave-receiver doesn’t acknowledge the slave address or received data, the master must abort the transfer. The slave must leave SDA high so that the master can generate the STOP condition (Figure 11-14). FIGURE 11-18:DATA TRANSFER WAIT STATE SDA MSB acknowledgment acknowledgment signal from receiver byte complete signal from receiver interrupt with receiver clock line held low while interrupts are serviced SCL S 1 2 7 8 9 1 2 3 • 8 9 P Start Stop Condition Address R/W ACK Wait Data ACK Condition State DS30390E-page 90 (cid:211) 1997 Microchip Technology Inc.

Applicable Devices PIC16C7X 727373A7474A7677 Figure 11-19 and Figure 11-20 show Master-transmit- SCL is high), but occurs after a data transfer acknowl- ter and Master-receiver data transfer sequences. edge pulse (not the bus-free state). This allows a mas- ter to send “commands” to the slave and then receive When a master does not wish to relinquish the bus (by the requested information or to address a different generating a STOP condition), a repeated START con- slave device. This sequence is shown in Figure 11-21. dition (Sr) must be generated. This condition is identi- cal to the start condition (SDA goes high-to-low while FIGURE 11-19:MASTER-TRANSMITTER SEQUENCE For 7-bit address: For 10-bit address: SSlave AddressR/WA Data A Data A/A P SSlave AddressR/W A1Slave AddressA2 First 7 bits Second byte '0' (write) data transferred (write) (n bytes - acknowledge) A master transmitter addresses a slave receiver with a 7-bit address. The transfer direction is not changed. Data A DataA/AP A = acknowledge (SDA low) From master to slave A = not acknowledge (SDA high) S = Start Condition A master transmitter addresses a slave receiver From slave to master P = Stop Condition with a 10-bit address. FIGURE 11-20:MASTER-RECEIVER SEQUENCE For 7-bit address: For 10-bit address: S Slave AddressR/WA Data A Data A P SSlave AddressR/W A1Slave AddressA2 First 7 bits Second byte '1' (read) data transferred (write) (n bytes - acknowledge) A master reads a slave immediately after the first byte. SrSlave AddressR/W A3DataA DataA P First 7 bits A = acknowledge (SDA low) From master to slave A = not acknowledge (SDA high) (read) S = Start Condition A master transmitter addresses a slave receiver From slave to master P = Stop Condition with a 10-bit address. FIGURE 11-21:COMBINED FORMAT (read or write) (n bytes + acknowledge) SSlave AddressR/WA Data A/A Sr Slave Address R/W A Data A/A P (read) Sr = repeated (write) Direction of transfer Start Condition may change at this point Transfer direction of data and acknowledgment bits depends on R/W bits. Combined format: SrSlave AddressR/W A Slave AddressA Data A Data A/A Sr Slave AddressR/W ADataA DataAP First 7 bits Second byte First 7 bits (write) (read) Combined format - A master addresses a slave with a 10-bit address, then transmits data to this slave and reads data from this slave. A = acknowledge (SDA low) From master to slave A = not acknowledge (SDA high) S = Start Condition From slave to master P = Stop Condition (cid:211) 1997 Microchip Technology Inc. DS30390E-page 91

PIC16C7X Applicable Devices 727373A7474A7677 11.4.4 MULTI-MASTER 11.2.4.2 Clock Synchronization The I2C protocol allows a system to have more than Clock synchronization occurs after the devices have started arbitration. This is performed using a one master. This is called multi-master. When two or wired-AND connection to the SCL line. A high to low more masters try to transfer data at the same time, arbi- transition on the SCL line causes the concerned tration and synchronization occur. devices to start counting off their low period. Once a 11.4.4.1 ARBITRATION device clock has gone low, it will hold the SCL line low until its SCL high state is reached. The low to high tran- Arbitration takes place on the SDA line, while the SCL sition of this clock may not change the state of the SCL line is high. The master which transmits a high when line, if another device clock is still within its low period. the other master transmits a low loses arbitration The SCL line is held low by the device with the longest (Figure 11-22), and turns off its data output stage. A low period. Devices with shorter low periods enter a master which lost arbitration can generate clock pulses high wait-state, until the SCL line comes high. When until the end of the data byte where it lost arbitration. the SCL line comes high, all devices start counting off When the master devices are addressing the same their high periods. The first device to complete its high device, arbitration continues into the data. period will pull the SCL line low. The SCL line high time is determined by the device with the shortest high FIGURE 11-22:MULTI-MASTER period, Figure 11-23. ARBITRATION (TWO MASTERS) FIGURE 11-23:CLOCK SYNCHRONIZATION transmitter 1 loses arbitration DATA 1 SDA wait start counting state HIGH period DATA 1 DATA 2 CLK 1 SDA counter CLK reset 2 SCL SCL Masters that also incorporate the slave function, and have lost arbitration must immediately switch over to slave-receiver mode. This is because the winning mas- ter-transmitter may be addressing it. Arbitration is not allowed between: • A repeated START condition • A STOP condition and a data bit • A repeated START condition and a STOP condi- tion Care needs to be taken to ensure that these conditions do not occur. DS30390E-page 92 (cid:211) 1997 Microchip Technology Inc.

Applicable Devices PIC16C7X 727373A7474A7677 11.5 SSP I2C Operation The SSPCON register allows control of the I2C opera- tion. Four mode selection bits (SSPCON<3:0>) allow The SSP module in I2C mode fully implements all slave one of the following I2C modes to be selected: functions, except general call support, and provides • I2C Slave mode (7-bit address) interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. The • I2C Slave mode (10-bit address) SSP module implements the standard mode specifica- • I2C Slave mode (7-bit address), with start and tions as well as 7-bit and 10-bit addressing. Two pins stop bit interrupts enabled are used for data transfer. These are the • I2C Slave mode (10-bit address), with start and RC3/SCK/SCL pin, which is the clock (SCL), and the stop bit interrupts enabled RC4/SDI/SDA pin, which is the data (SDA). The user • I2C Firmware controlled Master Mode, slave is must configure these pins as inputs or outputs through idle the TRISC<4:3> bits. The SSP module functions are Selection of any I2C mode, with the SSPEN bit set, enabled by setting SSP Enable bit SSPEN (SSP- forces the SCL and SDA pins to be open drain, pro- CON<5>). vided these pins are programmed to inputs by setting the appropriate TRISC bits. FIGURE 11-24:SSP BLOCK DIAGRAM (I2C MODE) The SSPSTAT register gives the status of the data transfer. This information includes detection of a START or STOP bit, specifies if the received byte was Internal data or address if the next byte is the completion of data bus 10-bit address, and if this will be a read or write data Read Write transfer. The SSPSTAT register is read only. The SSPBUF is the register to which transfer data is SSPBUF reg written to or read from. The SSPSR register shifts the RC3/SCK/SCL data in or out of the device. In receive operations, the shift SSPBUF and SSPSR create a doubled buffered clock receiver. This allows reception of the next byte to begin SSPSR reg before reading the last byte of received data. When the RC4/ MSb LSb complete byte is received, it is transferred to the SDI/ SSPBUF register and flag bit SSPIF is set. If another SDA complete byte is received before the SSPBUF register Match detect Addr Match is read, a receiver overflow has occurred and bit SSPOV (SSPCON<6>) is set and the byte in the SSPSR is lost. SSPADD reg The SSPADD register holds the slave address. In 10-bit Start and Set, Reset mode, the user first needs to write the high byte of the Stop bit detect S, P bits address (1111 0 A9 A8 0). Following the high byte (SSPSTAT reg) address match, the low byte of the address needs to be loaded (A7:A0). The SSP module has five registers for I2C operation. These are the: • SSP Control Register (SSPCON) • SSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) - Not directly acces- sible • SSP Address Register (SSPADD) (cid:211) 1997 Microchip Technology Inc. DS30390E-page 93

PIC16C7X Applicable Devices 727373A7474A7677 11.5.1 SLAVE MODE address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF In slave mode, the SCL and SDA pins must be config- and SSPOV bits are clear, the following events occur: ured as inputs (TRISC<4:3> set). The SSP module will a) The SSPSR register value is loaded into the override the input state with the output data when SSPBUF register. required (slave-transmitter). b) The buffer full bit, BF is set. When an address is matched or the data transfer after c) An ACK pulse is generated. an address match is received, the hardware automati- cally will generate the acknowledge (ACK) pulse, and d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set then load the SSPBUF register with the received value (interrupt is generated if enabled) - on the falling currently in the SSPSR register. edge of the ninth SCL pulse. There are certain conditions that will cause the SSP In 10-bit address mode, two address bytes need to be module not to give this ACK pulse. These are if either received by the slave (Figure 11-16). The five Most Sig- (or both): nificant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must a) The buffer full bit BF (SSPSTAT<0>) was set specify a write so the slave device will receive the sec- before the transfer was received. ond address byte. For a 10-bit address the first byte b) The overflow bit SSPOV (SSPCON<6>) was set would equal ‘1111 0 A9 A8 0’, where A9 and A8 are before the transfer was received. the two MSbs of the address. The sequence of events In this case, the SSPSR register value is not loaded for 10-bit address is as follows, with steps 7- 9 for into the SSPBUF, but bit SSPIF (PIR1<3>) is set. slave-transmitter: Table 11-4 shows what happens when a data transfer 1. Receive first (high) byte of Address (bits SSPIF, byte is received, given the status of bits BF and SSPOV. BF, and bit UA (SSPSTAT<1>) are set). The shaded cells show the condition where user soft- 2. Update the SSPADD register with second (low) ware did not properly clear the overflow condition. Flag byte of Address (clears bit UA and releases the bit BF is cleared by reading the SSPBUF register while SCL line). bit SSPOV is cleared through software. 3. Read the SSPBUF register (clears bit BF) and The SCL clock input must have a minimum high and clear flag bit SSPIF. low for proper operation. The high and low times of the 4. Receive second (low) byte of Address (bits I2C specification as well as the requirement of the SSP SSPIF, BF, and UA are set). module is shown in timing parameter #100 and param- 5. Update the SSPADD register with the first (high) eter #101. byte of Address, if match releases SCL line, this 11.5.1.1 ADDRESSING will clear bit UA. 6. Read the SSPBUF register (clears bit BF) and Once the SSP module has been enabled, it waits for a clear flag bit SSPIF. START condition to occur. Following the START condi- 7. Receive repeated START condition. tion, the 8-bits are shifted into the SSPSR register. All 8. Receive first (high) byte of Address (bits SSPIF incoming bits are sampled with the rising edge of the and BF are set). clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. TABLE 11-4: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received Set bit SSPIF Generate ACK (SSP Interrupt occurs BF SSPOV SSPSR fi SSPBUF Pulse if enabled) 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes DS30390E-page 94 (cid:211) 1997 Microchip Technology Inc.

Applicable Devices PIC16C7X 727373A7474A7677 11.5.1.2 RECEPTION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- When the R/W bit of the address byte is clear and an ware. The SSPSTAT register is used to determine the address match occurs, the R/W bit of the SSPSTAT reg- status of the byte. ister is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow con- dition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. FIGURE 11-25: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address R/W=0 Receiving Data ACK Receiving Data ACK ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF (PIR1<3>) Cleared in software Bus Master terminates transfer BF (SSPSTAT<0>) SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 95

PIC16C7X Applicable Devices 727373A7474A7677 11.5.1.3 TRANSMISSION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and When the R/W bit of the incoming address byte is set the SSPSTAT register is used to determine the status and an address match occurs, the R/W bit of the of the byte. Flag bit SSPIF is set on the falling edge of SSPSTAT register is set. The received address is the ninth clock pulse. loaded into the SSPBUF register. The ACK pulse will As a slave-transmitter, the ACK pulse from the mas- be sent on the ninth bit, and pin RC3/SCK/SCL is held ter-receiver is latched on the rising edge of the ninth low. The transmit data must be loaded into the SSP- SCL input pulse. If the SDA line was high (not ACK), BUF register, which also loads the SSPSR register. then the data transfer is complete. When the ACK is Then pin RC3/SCK/SCL should be enabled by setting latched by the slave, the slave logic is reset (resets bit CKP (SSPCON<4>). The master must monitor the SSPSTAT register) and the slave then monitors for SCL pin prior to asserting another clock pulse. The another occurrence of the START bit. If the SDA line slave devices may be holding off the master by stretch- was low (ACK), the transmit data must be loaded into ing the clock. The eight data bits are shifted out on the the SSPBUF register, which also loads the SSPSR reg- falling edge of the SCL input. This ensures that the SDA ister. Then pin RC3/SCK/SCL should be enabled by signal is valid during the SCL high time (Figure 11-26). setting bit CKP. FIGURE 11-26:I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address R/W = 1 Transmitting Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Data in SCL held low sampled while CPU responds to SSPIF SSPIF (PIR1<3>) cleared in software BF (SSPSTAT<0>) From SSP interrupt SSPBUF is written in software service routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) DS30390E-page 96 (cid:211) 1997 Microchip Technology Inc.

Applicable Devices PIC16C7X 727373A7474A7677 11.5.2 MASTER MODE 11.5.3 MULTI-MASTER MODE Master mode of operation is supported in firmware In multi-master mode, the interrupt generation on the using interrupt generation on the detection of the detection of the START and STOP conditions allows START and STOP conditions. The STOP (P) and the determination of when the bus is free. The STOP START (S) bits are cleared from a reset or when the (P) and START (S) bits are cleared from a reset or SSP module is disabled. The STOP (P) and START (S) when the SSP module is disabled. The STOP (P) and bits will toggle based on the START and STOP condi- START (S) bits will toggle based on the START and tions. Control of the I2C bus may be taken when the P STOP conditions. Control of the I2C bus may be taken bit is set, or the bus is idle and both the S and P bits are when bit P (SSPSTAT<4>) is set, or the bus is idle and clear. both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt In master mode the SCL and SDA lines are manipu- when the STOP condition occurs. lated by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the In multi-master operation, the SDA line must be moni- value(s) in PORTC<4:3>. So when transmitting data, a tored to see if the signal level is the expected output '1' data bit must have the TRISC<4> bit set (input) and level. This check only needs to be done when a high a '0' data bit must have the TRISC<4> bit cleared (out- level is output. If a high level is expected and a low level put). The same scenario is true for the SCL line with the is present, the device needs to release the SDA and TRISC<3> bit. SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are: The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): • Address Transfer • START condition • Data Transfer • STOP condition When the slave logic is enabled, the slave continues to • Data transfer byte transmitted/received receive. If arbitration was lost during the address trans- fer stage, communication to the device may be in Master mode of operation can be done with either the progress. If addressed an ACK pulse will be generated. slave mode idle (SSPM3:SSPM0 = 1011) or with the If arbitration was lost during the data transfer stage, the slave active. When both master and slave modes are device will need to re-transfer the data at a later time. enabled, the software needs to differentiate the source(s) of the interrupt. TABLE 11-5: REGISTERS ASSOCIATED WITH I2C OPERATION Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 94h SSPSTAT SMP(2) CKE(2) D/A P S R/W UA BF 0000 0000 0000 0000 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI mode. Note 1: PSPIF and PSPIE are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The SMP and CKE bits are implemented on the PIC16C76/77 only. All other PIC16C7X devices have these two bits unim- plemented, read as '0'. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 97

PIC16C7X Applicable Devices 727373A7474A7677 FIGURE 11-27:OPERATION OF THE I2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE IDLE_MODE (7-bit): if (Addr_match) { Set interrupt; if (R/W = 1) { Send ACK = 0; set XMIT_MODE; } else if (R/W = 0) set RCV_MODE; } RCV_MODE: if ((SSPBUF=Full) OR (SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { transfer SSPSR fi SSPBUF; send ACK = 0; } Receive 8-bits in SSPSR; Set interrupt; XMIT_MODE: While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low; Send byte; Set interrupt; if ( ACK Received = 1) { End of transmission; Go back to IDLE_MODE; } else if ( ACK Received = 0) Go back to XMIT_MODE; IDLE_MODE (10-Bit): If (High_byte_addr_match AND (R/W = 0)) { PRIOR_ADDR_MATCH = FALSE; Set interrupt; if ((SSPBUF = Full) OR ((SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { Set UA = 1; Send ACK = 0; While (SSPADD not updated) Hold SCL low; Clear UA = 0; Receive Low_addr_byte; Set interrupt; Set UA = 1; If (Low_byte_addr_match) { PRIOR_ADDR_MATCH = TRUE; Send ACK = 0; while (SSPADD not updated) Hold SCL low; Clear UA = 0; Set RCV_MODE; } } } else if (High_byte_addr_match AND (R/W = 1) { if (PRIOR_ADDR_MATCH) { send ACK = 0; set XMIT_MODE; } else PRIOR_ADDR_MATCH = FALSE; } DS30390E-page 98 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 12.0 UNIVERSAL SYNCHRONOUS as a half duplex synchronous system that can commu- ASYNCHRONOUS RECEIVER nicate with peripheral devices such as A/D or D/A inte- grated circuits, Serial EEPROMs etc. TRANSMITTER (USART) The USART can be configured in the following modes: Applicable Devices • Asynchronous (full duplex) 727373A7474A7677 • Synchronous - Master (half duplex) The Universal Synchronous Asynchronous Receiver • Synchronous - Slave (half duplex) Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Com- Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to munications Interface or SCI). The USART can be con- be set in order to configure pins RC6/TX/CK and RC7/ figured as a full duplex asynchronous system that can RX/DT as the Universal Synchronous Asynchronous communicate with peripheral devices such as CRT ter- Receiver Transmitter. minals and personal computers, or it can be configured FIGURE 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D R = Readable bit bit7 bit0 W =Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: CSRC: Clock Source Select bit Asynchronous mode Don’t care Synchronous mode 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) bit 6: TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5: TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. bit 4: SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3: Unimplemented: Read as '0' bit 2: BRGH: High Baud Rate Select bit Asynchronous mode 1 = High speed Note: For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may expe- rience a high rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77. 0 = Low speed Synchronous mode Unused in this mode bit 1: TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data. Can be parity bit. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 99

PIC16C7X FIGURE 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x SPEN RX9 SREN CREN — FERR OERR RX9D R = Readable bit bit7 bit0 W =Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6: RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5: SREN: Single Receive Enable bit Asynchronous mode Don’t care Synchronous mode - master 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - slave Unused in this mode bit 4: CREN: Continuous Receive Enable bit Asynchronous mode 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3: Unimplemented: Read as '0' bit 2: FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1: OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit) DS30390E-page 100 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 12.1 USART Baud Rate Generator (BRG) EXAMPLE 12-1: CALCULATING BAUD Applicable Devices RATE ERROR 727373A7474A7677 Desired Baud rate = Fosc / (64 (X + 1)) The BRG supports both the Asynchronous and Syn- 9600 = 16000000 /(64 (X + 1)) chronous modes of the USART. It is a dedicated 8-bit X = º 25.042ß = 25 baud rate generator. The SPBRG register controls the Calculated Baud Rate=16000000 / (64 (25 + 1)) period of a free running 8-bit timer. In asynchronous mode bit BRGH (TXSTA<2>) also controls the baud = 9615 rate. In synchronous mode bit BRGH is ignored. Error = (Calculated Baud Rate - Desired Baud Rate) Table 12-1 shows the formula for computation of the Desired Baud Rate baud rate for different USART modes which only apply = (9615 - 9600) / 9600 in master mode (internal clock). = 0.16% Given the desired baud rate and Fosc, the nearest inte- ger value for the SPBRG register can be calculated using the formula in Table 12-1. From this, the error in It may be advantageous to use the high baud rate baud rate can be determined. (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the Example 12-1 shows the calculation of the baud rate baud rate error in some cases. error for the following conditions: FOSC = 16 MHz Note: For the PIC16C73/73A/74/74A, the asyn- Desired Baud Rate = 9600 chronous high speed mode (BRGH = 1) BRGH = 0 may experience a high rate of receive SYNC = 0 errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77. Writing a new value to the SPBRG register, causes the BRG timer to be reset (or cleared), this ensures the BRG does not wait for a timer overflow before output- ting the new baud rate. TABLE 12-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate= FOSC/(16(X+1)) 1 (Synchronous) Baud Rate = FOSC/(4(X+1)) NA X = value in SPBRG (0 to 255) TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 101

PIC16C7X TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE FOSC = 20 MHz 16 MHz 10 MHz 7.15909 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value KBAUD KBAUD KBAUD KBAUD (K) ERROR (decimal) ERROR (decimal) ERROR (decimal) ERROR (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - 9.766 +1.73 255 9.622 +0.23 185 19.2 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 76.8 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 96 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 300 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 298.3 -0.57 5 500 500 0 9 500 0 7 500 0 4 NA - - HIGH 5000 - 0 4000 - 0 2500 - 0 1789.8 - 0 LOW 19.53 - 255 15.625 - 255 9.766 - 255 6.991 - 255 FOSC = 5.0688 MHz 4 MHz 3.579545 MHz 1 MHz 32.768 kHz BAUD SPBRG SPBRG SPBRG SPBRG SPBRG RATE KBAUD % value KBAUD % value KBAUD % value KBAUD % value KBAUD % value (K) ERROR (decimal) ERROR (decimal) ERROR (decimal) ERROR (decimal) ERROR (decimal) 0.3 NA - - NA - - NA - - NA - - 0.303 +1.14 26 1.2 NA - - NA - - NA - - 1.202 +0.16 207 1.170 -2.48 6 2.4 NA - - NA - - NA - - 2.404 +0.16 103 NA - - 9.6 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92 9.615 +0.16 25 NA - - 19.2 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46 19.24 +0.16 12 NA - - 76.8 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11 83.34 +8.51 2 NA - - 96 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8 NA - - NA - - 300 316.8 +5.60 3 NA - - 298.3 -0.57 2 NA - - NA - - 500 NA - - NA - - NA - - NA - - NA - - HIGH 1267 - 0 100 - 0 894.9 - 0 250 - 0 8.192 - 0 LOW 4.950 - 255 3.906 - 255 3.496 - 255 0.9766 - 255 0.032 - 255 TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz 16 MHz 10 MHz 7.15909 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value (K) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 1.203 +0.23 92 2.4 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 2.380 -0.83 46 9.6 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 9.322 -2.90 11 19.2 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 76.8 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 NA - - 96 104.2 +8.51 2 NA - - NA - - NA - - 300 312.5 +4.17 0 NA - - NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 312.5 - 0 250 - 0 156.3 - 0 111.9 - 0 LOW 1.221 - 255 0.977 - 255 0.6104 - 255 0.437 - 255 FOSC = 5.0688 MHz 4 MHz 3.579545 MHz 1 MHz 32.768 kHz BAUD SPBRG SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value % value (K) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1 1.2 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46 1.202 +0.16 12 NA - - 2.4 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22 2.232 -6.99 6 NA - - 9.6 9.9 +3.13 7 NA - - 9.322 -2.90 5 NA - - NA - - 19.2 19.8 +3.13 3 NA - - 18.64 -2.90 2 NA - - NA - - 76.8 79.2 +3.13 0 NA - - NA - - NA - - NA - - 96 NA - - NA - - NA - - NA - - NA - - 300 NA - - NA - - NA - - NA - - NA - - 500 NA - - NA - - NA - - NA - - NA - - HIGH 79.2 - 0 62.500 - 0 55.93 - 0 15.63 - 0 0.512 - 0 LOW 0.3094 - 255 3.906 - 255 0.2185 - 255 0.0610 - 255 0.0020 - 255 DS30390E-page 102 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz 16 MHz 10 MHz 7.16 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value (K) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 9.520 -0.83 46 19.2 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 19.454 +1.32 22 38.4 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 37.286 -2.90 11 57.6 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 55.930 -2.90 7 115.2 113.636 -1.36 10 111.111 -3.55 8 125 +8.51 4 111.860 -2.90 3 250 250 0 4 250 0 3 NA - - NA - - 625 625 0 1 NA - - 625 0 0 NA - - 1250 1250 0 0 NA - - NA - - NA - - FOSC = 5.068 MHz 4 MHz 3.579 MHz 1 MHz 32.768 kHz BAUD SPBRG SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value % value (K) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 9.6 9.6 0 32 NA - - 9.727 +1.32 22 8.928 -6.99 6 NA - - 19.2 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11 20.833 +8.51 2 NA - - 38.4 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5 31.25 -18.61 1 NA - - 57.6 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3 62.5 +8.51 0 NA - - 115.2 105.6 -8.33 2 19.231 +0.16 12 111.860 -2.90 1 NA - - NA - - 250 NA - - NA - - 223.721 -10.51 0 NA - - NA - - 625 NA - - NA - - NA - - NA - - NA - - 1250 NA - - NA - - NA - - NA - - NA - - Note: For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may experience a high rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 103

PIC16C7X 12.1.1 SAMPLING set (i.e., at the high baud rates), the sampling is done on the 3 clock edges preceding the second rising edge The data on the RC7/RX/DT pin is sampled three times after the first falling edge of a x4 clock (Figure 12-4 and by a majority detect circuit to determine if a high or a Figure 12-5). low level is present at the RX pin. If bit BRGH (TXSTA<2>) is clear (i.e., at the low baud rates), the sampling is done on the seventh, eighth and ninth fall- ing edges of a x16 clock (Figure 12-3). If bit BRGH is FIGURE 12-3: RX PIN SAMPLING SCHEME. BRGH = 0 (PIC16C73/73A/74/74A) Start bit RX Bit0 (RC7/RX/DT pin) Baud CLK for all but start bit baud CLK x16 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Samples FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 1 (PIC16C73/73A/74/74A) RX pin Start Bit bit0 bit1 baud clk First falling edge after RX pin goes low Second rising edge x4 clk 1 2 3 4 1 2 3 4 1 2 Q2, Q4 clk Samples Samples Samples FIGURE 12-5: RX PIN SAMPLING SCHEME, BRGH = 1 (PIC16C73/73A/74/74A) RX pin Start Bit bit0 Baud clk for all but start bit baud clk First falling edge after RX pin goes low Second rising edge x4 clk 1 2 3 4 Q2, Q4 clk Samples DS30390E-page 104 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X FIGURE 12-6: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1 (PIC16C76/77) Start bit RX Bit0 (RC7/RX/DT pin) Baud CLK for all but start bit baud CLK x16 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Samples (cid:211) 1997 Microchip Technology Inc. DS30390E-page 105

PIC16C7X 12.2 USART Asynchronous Mode flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE Applicable Devices ( PIE1<4>). Flag bit TXIF will be set regardless of the 727373A7474A7677 state of enable bit TXIE and cannot be cleared in soft- In this mode, the USART uses standard nonreturn-to- ware. It will reset only when new data is loaded into the zero (NRZ) format (one start bit, eight or nine data bits TXREG register. While flag bit TXIF indicated the sta- and one stop bit). The most common data format is tus of the TXREG register, another bit TRMT 8-bits. An on-chip dedicated 8-bit baud rate generator (TXSTA<1>) shows the status of the TSR register. Sta- can be used to derive standard baud rate frequencies tus bit TRMT is a read only bit which is set when the from the oscillator. The USART transmits and receives TSR register is empty. No interrupt logic is tied to this the LSb first. The USART’s transmitter and receiver are bit, so the user has to poll this bit in order to determine functionally independent but use the same data format if the TSR register is empty. and baud rate. The baud rate generator produces a clock either x16 or x64 of the bit shift rate, depending Note 1: The TSR register is not mapped in data on bit BRGH (TXSTA<2>). Parity is not supported by memory so it is not available to the user. the hardware, but can be implemented in software (and Note 2: Flag bit TXIF is set when enable bit TXEN stored as the ninth data bit). Asynchronous mode is is set. stopped during SLEEP. Transmission is enabled by setting enable bit TXEN Asynchronous mode is selected by clearing bit SYNC (TXSTA<5>). The actual transmission will not occur (TXSTA<4>). until the TXREG register has been loaded with data and the baud rate generator (BRG) has produced a The USART Asynchronous module consists of the fol- shift clock (Figure 12-7). The transmission can also be lowing important elements: started by first loading the TXREG register and then • Baud Rate Generator setting enable bit TXEN. Normally when transmission • Sampling Circuit is first started, the TSR register is empty, so a transfer • Asynchronous Transmitter to the TXREG register will result in an immediate trans- • Asynchronous Receiver fer to TSR resulting in an empty TXREG. A back-to- back transfer is thus possible (Figure 12-9). Clearing 12.2.1 USART ASYNCHRONOUS TRANSMITTER enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmit- The USART transmitter block diagram is shown in ter. As a result the RC6/TX/CK pin will revert to hi- Figure 12-7. The heart of the transmitter is the transmit impedance. (serial) shift register (TSR). The shift register obtains its In order to select 9-bit transmission, transmit bit TX9 data from the read/write transmit buffer, TXREG. The (TXSTA<6>) should be set and the ninth bit should be TXREG register is loaded with data in software. The written to TX9D (TXSTA<0>). The ninth bit must be TSR register is not loaded until the STOP bit has been written before writing the 8-bit data to the TXREG reg- transmitted from the previous load. As soon as the ister. This is because a data write to the TXREG regis- STOP bit is transmitted, the TSR is loaded with new ter can result in an immediate transfer of the data to the data from the TXREG register (if available). Once the TSR register (if the TSR is empty). In such a case, an TXREG register transfers the data to the TSR register incorrect ninth data bit maybe loaded in the TSR regis- (occurs in one TCY), the TXREG register is empty and ter. FIGURE 12-7: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register TXIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D DS30390E-page 106 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Steps to follow when setting up an Asynchronous 4. If 9-bit transmission is desired, then set transmit Transmission: bit TX9. 1. Initialize the SPBRG register for the appropriate 5. Enable the transmission by setting bit TXEN, baud rate. If a high speed baud rate is desired, which will also set bit TXIF. set bit BRGH. (Section 12.1) 6. If 9-bit transmission is selected, the ninth bit 2. Enable the asynchronous serial port by clearing should be loaded in bit TX9D. bit SYNC and setting bit SPEN. 7. Load data to the TXREG register (starts trans- 3. If interrupts are desired, then set enable bit mission). TXIE. FIGURE 12-8: ASYNCHRONOUS MASTER TRANSMISSION Write to TXREG Word 1 BRG output (shift clock) RC6/TX/CK (pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit WORD 1 TXIF bit (Transmit buffer reg. empty flag) WORD 1 TRMT bit Transmit Shift Reg (Transmit shift reg. empty flag) FIGURE 12-9: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG output (shift clock) RC6/TX/CK (pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit Start Bit Bit 0 TXIF bit (interrupt reg. flag) WORD 1 WORD 2 TRMT bit WORD 1 WORD 2 (rTerga. nesmmpitt ys hfliaftg) Transmit Shift Reg. Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 107

PIC16C7X 12.2.2 USART ASYNCHRONOUS RECEIVER double buffered register, i.e. it is a two deep FIFO. It is possible for two bytes of data to be received and trans- The receiver block diagram is shown in Figure 12-10. ferred to the RCREG FIFO and a third byte begin shift- The data is received on the RC7/RX/DT pin and drives ing to the RSR register. On the detection of the STOP the data recovery block. The data recovery block is bit of the third byte, if the RCREG register is still full actually a high speed shifter operating at x16 times the then overrun error bit OERR (RCSTA<1>) will be set. baud rate, whereas the main receive serial shifter oper- The word in the RSR will be lost. The RCREG register ates at the bit rate or at FOSC. can be read twice to retrieve the two bytes in the FIFO. Once Asynchronous mode is selected, reception is Overrun bit OERR has to be cleared in software. This enabled by setting bit CREN (RCSTA<4>). is done by resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the The heart of the receiver is the receive (serial) shift reg- RSR register to the RCREG register are inhibited, so it ister (RSR). After sampling the STOP bit, the received is essential to clear error bit OERR if it is set. Framing data in the RSR is transferred to the RCREG register (if error bit FERR (RCSTA<2>) is set if a stop bit is it is empty). If the transfer is complete, flag bit RCIF detected as clear. Bit FERR and the 9th receive bit are (PIR1<5>) is set. The actual interrupt can be enabled/ buffered the same way as the receive data. Reading disabled by setting/clearing enable bit RCIE the RCREG, will load bits RX9D and FERR with new (PIE1<5>). Flag bit RCIF is a read only bit which is values, therefore it is essential for the user to read the cleared by the hardware. It is cleared when the RCREG RCSTA register before reading RCREG register in register has been read and is empty. The RCREG is a order not to lose the old FERR and RX9D information. FIGURE 12-10:USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN SPBRG ‚ 64 MSb RSR register LSb or Baud Rate Generator ‚ 16 Stop (8) 7 • • • 1 0 Start RC7/RX/DT Pin Buffer Data and Control Recovery RX9 SPEN RX9D RCREG register FIFO 8 Interrupt RCIF Data Bus RCIE FIGURE 12-11:ASYNCHRONOUS RECEPTION RX (pin) Start Start Start bit bit0 bit1 bit7/8 Stop bit bit0 bit7/8 Stop bit bit7/8 Stop bit bit bit Rcv shift reg Rcv buffer reg WORD 1 WORD 2 RCREG RCREG Read Rcv buffer reg RCREG RCIF (interrupt flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS30390E-page 108 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Steps to follow when setting up an Asynchronous 6. Flag bit RCIF will be set when reception is com- Reception: plete and an interrupt will be generated if enable bit RCIE was set. 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, 7. Read the RCSTA register to get the ninth bit (if set bit BRGH. (Section 12.1). enabled) and determine if any error occurred during reception. 2. Enable the asynchronous serial port by clearing bit SYNC, and setting bit SPEN. 8. Read the 8-bit received data by reading the RCREG register. 3. If interrupts are desired, then set enable bit RCIE. 9. If any error occurred, clear the error by clearing enable bit CREN. 4. If 9-bit reception is desired, then set bit RX9. 5. Enable the reception by setting bit CREN. TABLE 12-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 109

PIC16C7X 12.3 USART Synchronous Master Mode Clearing enable bit TXEN, during a transmission, will Applicable Devices cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to hi-imped- 727373A7474A7677 ance. If either bit CREN or bit SREN is set, during a In Synchronous Master mode, the data is transmitted in transmission, the transmission is aborted and the DT a half-duplex manner i.e. transmission and reception pin reverts to a hi-impedance state (for a reception). do not occur at the same time. When transmitting data, The CK pin will remain an output if bit CSRC is set the reception is inhibited and vice versa. Synchronous (internal clock). The transmitter logic however is not mode is entered by setting bit SYNC (TXSTA<4>). In reset although it is disconnected from the pins. In order addition enable bit SPEN (RCSTA<7>) is set in order to to reset the transmitter, the user has to clear bit TXEN. configure the RC6/TX/CK and RC7/RX/DT I/O pins to If bit SREN is set (to interrupt an on-going transmission CK (clock) and DT (data) lines respectively. The Master and receive a single word), then after the single word is mode indicates that the processor transmits the master received, bit SREN will be cleared and the serial port clock on the CK line. The Master mode is entered by will revert back to transmitting since bit TXEN is still set. setting bit CSRC (TXSTA<7>). The DT line will immediately switch from hi-impedance receive mode to transmit and start driving. To avoid 12.3.1 USART SYNCHRONOUS MASTER this, bit TXEN should be cleared. TRANSMISSION In order to select 9-bit transmission, the TX9 The USART transmitter block diagram is shown in (TXSTA<6>) bit should be set and the ninth bit should Figure 12-7. The heart of the transmitter is the transmit be written to bit TX9D (TXSTA<0>). The ninth bit must (serial) shift register (TSR). The shift register obtains its be written before writing the 8-bit data to the TXREG data from the read/write transmit buffer register register. This is because a data write to the TXREG can TXREG. The TXREG register is loaded with data in result in an immediate transfer of the data to the TSR software. The TSR register is not loaded until the last register (if the TSR is empty). If the TSR was empty and bit has been transmitted from the previous load. As the TXREG was written before writing the “new” TX9D, soon as the last bit is transmitted, the TSR is loaded the “present” value of bit TX9D is loaded. with new data from the TXREG (if available). Once the Steps to follow when setting up a Synchronous Master TXREG register transfers the data to the TSR register Transmission: (occurs in one Tcycle), the TXREG is empty and inter- rupt bit, TXIF (PIR1<4>) is set. The interrupt can be 1. Initialize the SPBRG register for the appropriate enabled/disabled by setting/clearing enable bit TXIE baud rate (Section 12.1). (PIE1<4>). Flag bit TXIF will be set regardless of the 2. Enable the synchronous master serial port by state of enable bit TXIE and cannot be cleared in soft- setting bits SYNC, SPEN, and CSRC. ware. It will reset only when new data is loaded into the 3. If interrupts are desired, then set enable bit TXREG register. While flag bit TXIF indicates the status TXIE. of the TXREG register, another bit TRMT (TXSTA<1>) 4. If 9-bit transmission is desired, then set bit TX9. shows the status of the TSR register. TRMT is a read 5. Enable the transmission by setting bit TXEN. only bit which is set when the TSR is empty. No inter- 6. If 9-bit transmission is selected, the ninth bit rupt logic is tied to this bit, so the user has to poll this should be loaded in bit TX9D. bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not 7. Start transmission by loading data to the available to the user. TXREG register. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is sta- ble around the falling edge of the synchronous clock (Figure 12-12). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure 12-13). This is advantageous when slow baud rates are selected, since the BRG is kept in reset when bits TXEN, CREN, and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. Back-to-back trans- fers are possible. DS30390E-page 110 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets BOR 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. FIGURE 12-12:SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin Bit 0 Bit 1 Bit 2 Bit 7 Bit 0 Bit 1 Bit 7 WORD 1 WORD 2 RC6/TX/CK pin Write to TXREG reg Write word1 Write word2 TXIF bit (Interrupt flag) TRMT bTiRtMT '1' '1' TXEN bit Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words FIGURE 12-13:SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit0 bit1 bit2 bit6 bit7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit (cid:211) 1997 Microchip Technology Inc. DS30390E-page 111

PIC16C7X 12.3.2 USART SYNCHRONOUS MASTER Steps to follow when setting up a Synchronous Master RECEPTION Reception: 1. Initialize the SPBRG register for the appropriate Once Synchronous mode is selected, reception is baud rate. (Section 12.1) enabled by setting either enable bit SREN (RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is 2. Enable the synchronous master serial port by sampled on the RC7/RX/DT pin on the falling edge of setting bits SYNC, SPEN, and CSRC. the clock. If enable bit SREN is set, then only a single 3. Ensure bits CREN and SREN are clear. word is received. If enable bit CREN is set, the recep- 4. If interrupts are desired, then set enable bit tion is continuous until CREN is cleared. If both bits are RCIE. set then CREN takes precedence. After clocking the 5. If 9-bit reception is desired, then set bit RX9. last bit, the received data in the Receive Shift Register 6. If a single reception is required, set bit SREN. (RSR) is transferred to the RCREG register (if it is For continuous reception set bit CREN. empty). When the transfer is complete, interrupt flag bit 7. Interrupt flag bit RCIF will be set when reception RCIF (PIR1<5>) is set. The actual interrupt can be is complete and an interrupt will be generated if enabled/disabled by setting/clearing enable bit RCIE enable bit RCIE was set. (PIE1<5>). Flag bit RCIF is a read only bit which is reset by the hardware. In this case it is reset when the 8. Read the RCSTA register to get the ninth bit (if RCREG register has been read and is empty. The enabled) and determine if any error occurred RCREG is a double buffered register, i.e. it is a two during reception. deep FIFO. It is possible for two bytes of data to be 9. Read the 8-bit received data by reading the received and transferred to the RCREG FIFO and a RCREG register. third byte to begin shifting into the RSR register. On the 10. If any error occurred, clear the error by clearing clocking of the last bit of the third byte, if the RCREG bit CREN. register is still full then overrun error bit OERR (RCSTA<1>) is set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, so it is essential to clear bit OERR if it is set. The 9th receive bit is buffered the same way as the receive data. Reading the RCREG register, will load bit RX9D with a new value, therefore it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets BOR 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. DS30390E-page 112 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X FIGURE 12-14:SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 113

PIC16C7X 12.4 USART Synchronous Slave Mode 12.4.2 USART SYNCHRONOUS SLAVE Applicable Devices RECEPTION 727373A7474A7677 The operation of the synchronous master and slave Synchronous slave mode differs from the Master mode modes is identical except in the case of the SLEEP in the fact that the shift clock is supplied externally at mode. Also, bit SREN is a don't care in slave mode. the RC6/TX/CK pin (instead of being supplied internally If receive is enabled, by setting bit CREN, prior to the in master mode). This allows the device to transfer or SLEEP instruction, then a word may be received during receive data while in SLEEP mode. Slave mode is SLEEP. On completely receiving the word, the RSR entered by clearing bit CSRC (TXSTA<7>). register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated 12.4.1 USART SYNCHRONOUS SLAVE will wake the chip from SLEEP. If the global interrupt is TRANSMIT enabled, the program will branch to the interrupt vector The operation of the synchronous master and slave (0004h). modes are identical except in the case of the SLEEP Steps to follow when setting up a Synchronous Slave mode. Reception: If two words are written to the TXREG and then the 1. Enable the synchronous master serial port by SLEEP instruction is executed, the following will occur: setting bits SYNC and SPEN and clearing bit a) The first word will immediately transfer to the CSRC. TSR register and transmit. 2. If interrupts are desired, then set enable bit b) The second word will remain in TXREG register. RCIE. c) Flag bit TXIF will not be set. 3. If 9-bit reception is desired, then set bit RX9. d) When the first word has been shifted out of TSR, 4. To enable reception, set enable bit CREN. the TXREG register will transfer the second 5. Flag bit RCIF will be set when reception is com- word to the TSR and flag bit TXIF will now be plete and an interrupt will be generated, if set. enable bit RCIE was set. e) If enable bit TXIE is set, the interrupt will wake 6. Read the RCSTA register to get the ninth bit (if the chip from SLEEP and if the global interrupt enabled) and determine if any error occurred is enabled, the program will branch to the inter- during reception. rupt vector (0004h). 7. Read the 8-bit received data by reading the Steps to follow when setting up a Synchronous Slave RCREG register. Transmission: 8. If any error occurred, clear the error by clearing 1. Enable the synchronous slave serial port by set- bit CREN. ting bits SYNC and SPEN and clearing bit CSRC. 2. Clear bits CREN and SREN. 3. If interrupts are desired, then set enable bit TXIE. 4. If 9-bit transmission is desired, then set bit TX9. 5. Enable the transmission by setting enable bit TXEN. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. DS30390E-page 114 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets BOR 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets BOR 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 115

PIC16C7X NOTES: DS30390E-page 116 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 13.0 ANALOG-TO-DIGITAL The A/D converter has a unique feature of being able to CONVERTER (A/D) MODULE operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from Applicable Devices the A/D’s internal RC oscillator. 727373A7474A7677 The A/D module has three registers. These registers The analog-to-digital (A/D) converter module has five are: inputs for the PIC16C72/73/73A/76, and eight for the • A/D Result Register (ADRES) PIC16C74/74A/77. • A/D Control Register 0 (ADCON0) The A/D allows conversion of an analog input signal to • A/D Control Register 1 (ADCON1) a corresponding 8-bit digital number (refer to Applica- tion Note AN546 for use of A/D Converter). The output The ADCON0 register, shown in Figure 13-1, controls of the sample and hold is the input into the converter, the operation of the A/D module. The ADCON1 regis- which generates the result via successive approxima- ter, shown in Figure 13-2, configures the functions of tion. The analog reference voltage is software select- the port pins. The port pins can be configured as ana- able to either the device’s positive supply voltage (VDD) log inputs (RA3 can also be a voltage reference) or as or the voltage level on the RA3/AN3/VREF pin. digital I/O. FIGURE 13-1: ADCON0 REGISTER (ADDRESS 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON R =Readable bit bit7 bit0 W =Writable bit U =Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an internal RC oscillator) bit 5-3: CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) 101 = channel 5, (RE0/AN5)(1) 110 = channel 6, (RE1/AN6)(1) 111 = channel 7, (RE2/AN7)(1) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: Unimplemented: Read as '0' bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current Note 1: A/D channels 5, 6, and 7 are implemented on the PIC16C74/74A/77 only. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 117

PIC16C7X FIGURE 13-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCFG2 PCFG1 PCFG0 R =Readable bit bit7 bit0 W =Writable bit U =Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0(1) RE1(1) RE2(1) VREF 000 A A A A A A A A VDD 001 A A A A VREF A A A RA3 010 A A A A A D D D VDD 011 A A A A VREF D D D RA3 100 A A D D A D D D VDD 101 A A D D VREF D D D RA3 11x D D D D D D D D — A = Analog input D = Digital I/O Note 1: RE0, RE1, and RE2 are implemented on the PIC16C74/74A/77 only. DS30390E-page 118 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X The ADRES register contains the result of the A/D con- 3. Wait the required acquisition time. version. When the A/D conversion is complete, the 4. Start conversion: result is loaded into the ADRES register, the GO/DONE • Set GO/DONE bit (ADCON0) bit (ADCON0<2>) is cleared, and A/D interrupt flag bit 5. Wait for A/D conversion to complete, by either: ADIF is set. The block diagrams of the A/D module are shown in Figure 13-3. • Polling for the GO/DONE bit to be cleared After the A/D module has been configured as desired, OR the selected channel must be acquired before the con- • Waiting for the A/D interrupt version is started. The analog input channels must 6. Read A/D Result register (ADRES), clear bit have their corresponding TRIS bits selected as an ADIF if required. input. To determine acquisition time, see Section 13.1. 7. For next conversion, go to step 1 or step 2 as After this acquisition time has elapsed the A/D conver- required. The A/D conversion time per bit is sion can be started. The following steps should be fol- defined as TAD. A minimum wait of 2TAD is lowed for doing an A/D conversion: required before next acquisition starts. 1. Configure the A/D module: • Configure analog pins / voltage reference / and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set GIE bit FIGURE 13-3: A/D BLOCK DIAGRAM CHS2:CHS0 111 RE2/AN7(1) 110 RE1/AN6(1) 101 RE0/AN5(1) 100 RA5/AN4 VIN 011 (Input voltage) RA3/AN3/VREF 010 A/D RA2/AN2 Converter 001 RA1/AN1 000 VDD RA0/AN0 000 or VREF 010 or 100 (Reference voltage) 001 or 011 or 101 PCFG2:PCFG0 Note 1: Not available on PIC16C72/73/73A/76. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 119

PIC16C7X 13.1 A/D Acquisition Requirements VDD = 5V fi Rss = 7 kW Applicable Devices Temp (application system max.) = 50(cid:176) C 727373A7474A7677 VHOLD = 0 @ t = 0 For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed Note 1: The reference voltage (VREF) has no to fully charge to the input channel voltage level. The effect on the equation, since it cancels analog input model is shown in Figure 13-4. The source itself out. impedance (RS) and the internal sampling switch (RSS) Note 2: The charge holding capacitor (CHOLD) is impedance directly affect the time required to charge not discharged after each conversion. the capacitor CHOLD. The sampling switch (RSS) imped- Note 3: The maximum recommended impedance ance varies over the device voltage (VDD), Figure 13-4. for analog sources is 10 kW . This is The source impedance affects the offset voltage at the required to meet the pin leakage specifi- analog input (due to pin leakage current). The maxi- cation. mum recommended impedance for analog sources is 10 kW . After the analog input channel is selected Note 4: After a conversion has completed, a (changed) this acquisition must be done before the con- 2.0TAD delay must complete before acqui- version can be started. sition can begin again. During this time the holding capacitor is not connected to To calculate the minimum acquisition time, the selected A/D input channel. Equation 13-1 may be used. This equation calculates the acquisition time to within 1/2 LSb error is used (512 EXAMPLE 13-1: CALCULATING THE steps for the A/D). The 1/2 LSb error is the maximum MINIMUM REQUIRED error allowed for the A/D to meet its specified accuracy. ACQUISITION TIME EQUATION 13-1: A/D MINIMUM CHARGING TACQ = Amplifier Settling Time + TIME Holding Capacitor Charging Time + VHOLD = (VREF - (VREF/512)) • (1 - e(-TCAP/CHOLD(RIC + RSS + RS))) Temperature Coefficient Given: VHOLD = (VREF/512), for 1/2 LSb resolution TACQ = 5 m s + TCAP + [(Temp - 25(cid:176) C)(0.05 m s/(cid:176) C)] The above equation reduces to: TCAP = -CHOLD (RIC + RSS + RS) ln(1/511) TCAP = -(51.2 pF)(1 kW + RSS + RS) ln(1/511) -51.2 pF (1 kW + 7 kW + 10 kW ) ln(0.0020) Example 13-1 shows the calculation of the minimum -51.2 pF (18 kW ) ln(0.0020) required acquisition time TACQ. This calculation is based on the following system assumptions. -0.921 m s (-6.2364) 5.747 m s CHOLD = 51.2 pF TACQ = 5 m s + 5.747 m s + [(50(cid:176) C - 25(cid:176) C)(0.05 m s/(cid:176) C)] Rs = 10 kW 10.747 m s + 1.25 m s 1/2 LSb error 11.997 m s FIGURE 13-4: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC £ 1k SS RSS CHOLD VA CPIN I leakage = DAC capacitance 5 pF VT = 0.6V – 500 nA = 51.2 pF VSS Legend CPIN = input capacitance 6V VT = threshold voltage 5V I leakage = leakage current at the pin due to VDD 4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5 6 7 891011 Sampling Switch ( kW ) DS30390E-page 120 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 13.2 Selecting the A/D Conversion Clock 13.3 Configuring Analog Port Pins Applicable Devices Applicable Devices 727373A7474A7677 727373A7474A7677 The A/D conversion time per bit is defined as TAD. The The ADCON1, TRISA, and TRISE registers control the A/D conversion requires 9.5TAD per 8-bit conversion. operation of the A/D port pins. The port pins that are The source of the A/D conversion clock is software desired as analog inputs must have their correspond- selectable. The four possible options for TAD are: ing TRIS bits set (input). If the TRIS bit is cleared (out- • 2TOSC put), the digital output level (VOH or VOL) will be converted. • 8TOSC The A/D operation is independent of the state of the • 32TOSC CHS2:CHS0 bits and the TRIS bits. • Internal RC oscillator Note 1: When reading the port register, all pins For correct A/D conversions, the A/D conversion clock configured as analog input channels will (TAD) must be selected to ensure a minimum TAD time of 1.6 m s. read as cleared (a low level). Pins config- ured as digital inputs, will convert an ana- Table 13-1 shows the resultant TAD times derived from log input. Analog levels on a digitally the device operating frequencies and the A/D clock configured input will not affect the conver- source selected. sion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the AN7:AN0 pins), may cause the input buffer to con- sume current that is out of the devices specification. TABLE 13-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Device Frequency Operation ADCS1:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz 2TOSC 00 100 ns(2) 400 ns(2) 1.6 m s 6 m s 8TOSC 01 400 ns(2) 1.6 m s 6.4 m s 24 m s(3) 32TOSC 10 1.6 m s 6.4 m s 25.6 m s(3) 96 m s(3) RC(5) 11 2 - 6 m s(1,4) 2 - 6 m s(1,4) 2 - 6 m s(1,4) 2 - 6 m s(1) Legend: Shaded cells are outside of recommended range. Note1: The RC source has a typical TAD time of 4 m s. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 121

PIC16C7X 13.4 A/D Conversions Applicable Devices Note: The GO/DONE bit should NOT be set in 727373A7474A7677 the same instruction that turns on the A/D. Example 13-2 shows how to perform an A/D conver- Clearing the GO/DONE bit during a conversion will sion. The RA pins are configured as analog inputs. The abort the current conversion. The ADRES register will analog reference (VREF) is the device VDD. The A/D NOT be updated with the partially completed A/D con- interrupt is enabled, and the A/D conversion clock is version sample. That is, the ADRES register will con- FRC. The conversion is performed on the RA0 pin tinue to contain the value of the last completed (channel 0). conversion (or the last value written to the ADRES reg- ister). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, an acquisition is automatically started on the selected channel. EXAMPLE 13-2: A/D CONVERSION BSF STATUS, RP0 ; Select Bank 1 BCF STATUS, RP1 ; PIC16C76/77 only CLRF ADCON1 ; Configure A/D inputs BSF PIE1, ADIE ; Enable A/D interrupts BCF STATUS, RP0 ; Select Bank 0 MOVLW 0xC1 ; RC Clock, A/D is on, Channel 0 is selected MOVWF ADCON0 ; BCF PIR1, ADIF ; Clear A/D interrupt flag bit BSF INTCON, PEIE ; Enable peripheral interrupts BSF INTCON, GIE ; Enable all interrupts ; ; Ensure that the required sampling time for the selected input channel has elapsed. ; Then the conversion may be started. ; BSF ADCON0, GO ; Start A/D Conversion : ; The ADIF bit will be set and the GO/DONE bit : ; is cleared upon completion of the A/D Conversion. DS30390E-page 122 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 13.4.1 FASTER CONVERSION - LOWER Since the TAD is based from the device oscillator, the RESOLUTION TRADE-OFF user must use some method (a timer, software loop, etc.) to determine when the A/D oscillator may be Not all applications require a result with 8-bits of reso- changed. Example 13-3 shows a comparison of time lution, but may instead require a faster conversion time. required for a conversion with 4-bits of resolution, ver- The A/D module allows users to make the trade-off of sus the 8-bit resolution conversion. The example is for conversion speed to resolution. Regardless of the res- devices operating at 20 MHz and 16 MHz (The A/D olution required, the acquisition time is the same. To clock is programmed for 32TOSC), and assumes that speed up the conversion, the clock source of the A/D immediately after 6TAD, the A/D clock is programmed module may be switched so that the TAD time violates for 2TOSC. the minimum specified time (see the applicable electri- cal specification). Once the TAD time violates the mini- The 2TOSC violates the minimum TAD time since the last 4-bits will not be converted to correct values. mum specified time, all the following A/D result bits are not valid (see A/D Conversion Timing in the Electrical Specifications section.) The clock sources may only be switched between the three oscillator versions (cannot be switched from/to RC). The equation to determine the time before the oscillator can be switched is as fol- lows: Conversion time = 2TAD + N • TAD + (8 - N)(2TOSC) Where: N = number of bits of resolution required. EXAMPLE 13-3: 4-BIT vs. 8-BIT CONVERSION TIMES Resolution Freq. (MHz)(1) 4-bit 8-bit TAD 20 1.6 m s 1.6 m s 16 2.0 m s 2.0 m s TOSC 20 50 ns 50 ns 16 62.5 ns 62.5 ns 2TAD + N • TAD + (8 - N)(2TOSC) 20 10 m s 16 m s 16 12.5 m s 20 m s Note1: PIC16C7X devices have a minimum TAD time of 1.6 m s. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 123

PIC16C7X 13.5 A/D Operation During Sleep Gain error measures the maximum deviation of the last Applicable Devices actual transition and the last ideal transition adjusted for offset error. This error appears as a change in slope 727373A7474A7677 of the transfer function. The difference in gain error to The A/D module can operate during SLEEP mode. This full scale error is that full scale does not take offset error requires that the A/D clock source be set to RC into account. Gain error can be calibrated out in soft- (ADCS1:ADCS0 = 11). When the RC clock source is ware. selected, the A/D module waits one instruction cycle Linearity error refers to the uniformity of the code before starting the conversion. This allows the SLEEP changes. Linearity errors cannot be calibrated out of instruction to be executed, which eliminates all digital the system. Integral non-linearity error measures the switching noise from the conversion. When the conver- actual code transition versus the ideal code transition sion is completed the GO/DONE bit will be cleared, and adjusted by the gain error for each code. the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from Differential non-linearity measures the maximum actual SLEEP. If the A/D interrupt is not enabled, the A/D mod- code width versus the ideal code width. This measure ule will then be turned off, although the ADON bit will is unadjusted. remain set. The maximum pin leakage current is – 1 m A. When the A/D clock source is another clock option (not In systems where the device frequency is low, use of RC), a SLEEP instruction will cause the present conver- the A/D RC clock is preferred. At moderate to high fre- sion to be aborted and the A/D module to be turned off, quencies, TAD should be derived from the device oscil- though the ADON bit will remain set. lator. TAD must not violate the minimum and should be Turning off the A/D places the A/D module in its lowest £ 8 m s for preferred operation. This is because TAD, current consumption state. when derived from TOSC, is kept away from on-chip phase clock transitions. This reduces, to a large extent, Note: For the A/D module to operate in SLEEP, the effects of digital switching noise. This is not possi- the A/D clock source must be set to RC ble with the RC derived clock. The loss of accuracy due (ADCS1:ADCS0 = 11). To perform an A/D to digital switching noise can be significant if many I/O conversion in SLEEP, ensure the SLEEP pins are active. instruction immediately follows the instruc- tion that sets the GO/DONE bit. In systems where the device will enter SLEEP mode after the start of the A/D conversion, the RC clock 13.6 A/D Accuracy/Error source selection is required. In this mode, the digital noise from the modules in SLEEP are stopped. This Applicable Devices method gives high accuracy. 727373A7474A7677 The absolute accuracy specified for the A/D converter 13.7 Effects of a RESET includes the sum of all contributions for quantization Applicable Devices error, integral error, differential error, full scale error, off- 727373A7474A7677 set error, and monotonicity. It is defined as the maxi- mum deviation from an actual transition versus an ideal A device reset forces all registers to their reset state. transition for any code. The absolute error of the A/D This forces the A/D module to be turned off, and any converter is specified at < – 1 LSb for VDD = VREF (over conversion is aborted. the device’s specified operating range). However, the The value that is in the ADRES register is not modified accuracy of the A/D converter will degrade as VDD for a Power-on Reset. The ADRES register will contain diverges from VREF. unknown data after a Power-on Reset. For a given range of analog inputs, the output digital code will be the same. This is due to the quantization of the analog input to a digital code. Quantization error is typically – 1/2 LSb and is inherent in the analog to dig- ital conversion process. The only way to reduce quan- tization error is to increase the resolution of the A/D converter. Offset error measures the first actual transition of a code versus the first ideal transition of a code. Offset error shifts the entire transfer function. Offset error can be calibrated out of a system or introduced into a sys- tem through the interaction of the total leakage current and source impedance at the analog input. DS30390E-page 124 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 13.8 Use of the CCP Trigger FIGURE 13-5: A/D TRANSFER FUNCTION Applicable Devices 727373A7474A7677 Note: In the PIC16C72, the "special event trig- FFh ger" is implemented in the CCP1 module. put FEh ut An A/D conversion can be started by the “special event e o trigger” of the CCP2 module (CCP1 on the PIC16C72 od c only). This requires that the CCP2M3:CCP2M0 bits al (CCP2CON<3:0>) be programmed as 1011 and that Digit 04h the A/D module is enabled (ADON bit is set). When the 03h trigger occurs, the GO/DONE bit will be set, starting the 02h A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D 01h acquisition period with minimal software overhead 00h (moving the ADRES to the desired location). The bb b b b b be) SS S S S S Sal appropriate analog input channel must be selected and LL L L L L Lc the minimum acquisition done before the “special event 0.5 1 2 3 4 255 256 ull s trigger” sets the GO/DONE bit (starts a conversion). (f Analog input voltage If the A/D module is not enabled (ADON is cleared), then the “special event trigger” will be ignored by the A/D module, but will still reset the Timer1 counter. 13.11 References 13.9 Connection Considerations A very good reference for understanding A/D convert- Applicable Devices ers is the "Analog-Digital Conversion Handbook" third 727373A7474A7677 edition, published by Prentice Hall (ISBN If the input voltage exceeds the rail values (VSS or VDD) 0-13-03-2848-0). by greater than 0.2V, then the accuracy of the conver- sion is out of specification. An external RC filter is sometimes added for anti-alias- ing of the input signal. The R component should be selected to ensure that the total source impedance is kept under the 10 kW recommended specification. Any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. 13.10 Transfer Function Applicable Devices 727373A7474A7677 The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input voltage (VAIN) is Analog VREF/256 (Figure 13-5). (cid:211) 1997 Microchip Technology Inc. DS30390E-page 125

PIC16C7X FIGURE 13-6: FLOWCHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Acquire Selected Channel Yes GO = 0? No A/=D R CClo?ck Yes C1o InnvSsettrrasuricto toniof DnA eC/Dlayyceled InsStLruEcEtiPon?Yes FinisAhG DCOIoF =n =v 0 e1rsion No No DSLeEviEceP ?in Yes AborAtG DCOIoF n= =v 0e 0rsion FinisAhG DCOIoF =n =v 0 e1rsion FrWoma kSel-euepp?Yes Wait 2 TAD No No FinishG COo =nv 0ersion PoweSrL-dEoEwPn A/D Wait 2 TAD PoSwtaeyr -idno Swlne eAp/D ADIF = 1 Wait 2 TAD TABLE 13-2: REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C72 Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets BOR 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. DS30390E-page 126 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 13-3: SUMMARY OF A/D REGISTERS, PIC16C73/73A/74/74A/76/77 Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets BOR 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C73/73A/76, always maintain these bits clear. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 127

PIC16C7X NOTES: DS30390E-page 128 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 14.0 SPECIAL FEATURES OF THE the chip in reset until the crystal oscillator is stable. The CPU other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, Applicable Devices designed to keep the part in reset while the power sup- 727373A7474A7677 ply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. What sets a microcontroller apart from other proces- sors are special circuits to deal with the needs of real- SLEEP mode is designed to offer a very low current time applications. The PIC16CXX family has a host of power-down mode. The user can wake-up from SLEEP such features intended to maximize system reliability, through external reset, Watchdog Timer Wake-up, or minimize cost through elimination of external compo- through an interrupt. Several oscillator options are also nents, provide power saving operating modes and offer made available to allow the part to fit the application. code protection. These are: The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration • Oscillator selection bits are used to select various options. • Reset - Power-on Reset (POR) 14.1 Configuration Bits - Power-up Timer (PWRT) Applicable Devices - Oscillator Start-up Timer (OST) 727373A7474A7677 - Brown-out Reset (BOR) The configuration bits can be programmed (read as '0') • Interrupts or left unprogrammed (read as '1') to select various • Watchdog Timer (WDT) device configurations. These bits are mapped in pro- • SLEEP gram memory location 2007h. • Code protection The user will note that address 2007h is beyond the • ID locations user program memory space. In fact, it belongs to the special test/configuration memory space (2000h - • In-circuit serial programming 3FFFh), which can be accessed only during program- The PIC16CXX has a Watchdog Timer which can be ming. shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep FIGURE 14-1: CONFIGURATION WORD FOR PIC16C73/74 — — — — — — — — CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG Address 2007h bit13 bit0 bit 13-5: Unimplemented: Read as '1' bit 4: CP1:CP0: Code protection bits 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 3: PWRTE: Power-up Timer Enable bit 1 = Power-up Timer enabled 0 = Power-up Timer disabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator (cid:211) 1997 Microchip Technology Inc. DS30390E-page 129

PIC16C7X FIGURE 14-2: CONFIGURATION WORD FOR PIC16C72/73A/74A/76/77 CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG Address 2007h bit13 bit0 bit 13-8 CP1:CP0: Code Protection bits (2) 5-4: 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 7: Unimplemented: Read as '1' bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. DS30390E-page 130 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 14.2 Oscillator Configurations TABLE 14-1: CERAMIC RESONATORS Applicable Devices Ranges Tested: 727373A7474A7677 Mode Freq OSC1 OSC2 14.2.1 OSCILLATOR TYPES XT 455 kHz 68 - 100 pF 68 - 100 pF The PIC16CXX can be operated in four different oscil- 2.0 MHz 15 - 68 pF 15 - 68 pF lator modes. The user can program two configuration 4.0 MHz 15 - 68 pF 15 - 68 pF bits (FOSC1 and FOSC0) to select one of these four HS 8.0 MHz 10 - 68 pF 10 - 68 pF modes: 16.0 MHz 10 - 22 pF 10 - 22 pF • LP Low Power Crystal These values are for design guidance only. See • XT Crystal/Resonator notes at bottom of page. • HS High Speed Crystal/Resonator Resonators Used: • RC Resistor/Capacitor 455 kHz Panasonic EFO-A455K04B – 0.3% 2.0 MHz Murata Erie CSA2.00MG – 0.5% 14.2.2 CRYSTAL OSCILLATOR/CERAMIC 4.0 MHz Murata Erie CSA4.00MG – 0.5% RESONATORS 8.0 MHz Murata Erie CSA8.00MT – 0.5% In XT, LP or HS modes a crystal or ceramic resonator 16.0 MHz Murata Erie CSA16.00MX – 0.5% is connected to the OSC1/CLKIN and OSC2/CLKOUT All resonators used did not have built-in capacitors. pins to establish oscillation (Figure 14-3). The PIC16CXX Oscillator design requires the use of a par- TABLE 14-2: CAPACITOR SELECTION allel cut crystal. Use of a series cut crystal may give a FOR CRYSTAL OSCILLATOR frequency out of the crystal manufacturers specifica- tions. When in XT, LP or HS modes, the device can Crystal Cap. Range Cap. Range have an external clock source to drive the OSC1/ Osc Type Freq C1 C2 CLKIN pin (Figure 14-4). LP 32 kHz 33 pF 33 pF FIGURE 14-3: CRYSTAL/CERAMIC 200 kHz 15 pF 15 pF RESONATOR OPERATION XT 200 kHz 47-68 pF 47-68 pF (HS, XT OR LP 1 MHz 15 pF 15 pF OSC CONFIGURATION) 4 MHz 15 pF 15 pF OSC1 HS 4 MHz 15 pF 15 pF To internal logic 8 MHz 15-33 pF 15-33 pF C1 20 MHz 15-33 pF 15-33 pF XTAL SLEEP RF These values are for design guidance only. See PIC16CXX OSC2 notes at bottom of page. RS Crystals Used C2 Note1 32 kHz Epson C-001R32.768K-A – 20 PPM See Table 14-1 and Table 14-2 for recommended values 200 kHz STD XTL 200.000KHz – 20 PPM of C1 and C2. 1 MHz ECS ECS-10-13-1 – 50 PPM Note 1: A series resistor may be required for AT strip 4 MHz ECS ECS-40-20-1 – 50 PPM cut crystals. 8 MHz EPSON CA-301 8.000M-C – 30 PPM 20 MHz EPSON CA-301 20.000M-C – 30 PPM FIGURE 14-4: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Note1: Recommended values of C1 and C2 are identical to the ranges tested (Table 14-1). 2: Higher capacitance increases the stability Clock from OSC1 of oscillator but also increases the start-up ext. system PIC16CXX time. 3: Since each resonator/crystal has its own Open OSC2 characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. 4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 131

PIC16C7X 14.2.3 EXTERNAL CRYSTAL OSCILLATOR 14.2.4 RC OSCILLATOR CIRCUIT For timing insensitive applications the “RC” device Either a prepackaged oscillator can be used or a simple option offers additional cost savings. The RC oscillator oscillator circuit with TTL gates can be built. Prepack- frequency is a function of the supply voltage, the resis- aged oscillators provide a wide operating range and tor (Rext) and capacitor (Cext) values, and the operat- better stability. A well-designed crystal oscillator will ing temperature. In addition to this, the oscillator provide good performance with TTL gates. Two types frequency will vary from unit to unit due to normal pro- of crystal oscillator circuits can be used; one with series cess parameter variation. Furthermore, the difference resonance, or one with parallel resonance. in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Figure 14-5 shows implementation of a parallel reso- Cext values. The user also needs to take into account nant oscillator circuit. The circuit is designed to use the variation due to tolerance of external R and C compo- fundamental frequency of the crystal. The 74AS04 nents used. Figure 14-7 shows how the R/C combina- inverter performs the 180-degree phase shift that a par- allel oscillator requires. The 4.7 kW resistor provides tion is connected to the PIC16CXX. For Rext values the negative feedback for stability. The 10 kW potenti- below 2.2 kW , the oscillator operation may become unstable, or stop completely. For very high Rext values ometer biases the 74AS04 in the linear region. This (e.g. 1 MW ), the oscillator becomes sensitive to noise, could be used for external oscillator designs. humidity and leakage. Thus, we recommend to keep FIGURE 14-5: EXTERNAL PARALLEL Rext between 3 kW and 100 kW . RESONANT CRYSTAL Although the oscillator will operate with no external OSCILLATOR CIRCUIT capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or +5V To Other small external capacitance, the oscillation frequency Devices can vary dramatically due to changes in external 10k capacitances, such as PCB trace capacitance or pack- 4.7k 74AS04 PIC16CXX age lead frame capacitance. 74AS04 CLKIN See characterization data for desired device for RC fre- quency variation from part to part due to normal pro- cess variation. The variation is larger for larger R (since 10k leakage current variation will affect RC frequency more XTAL for large R) and for smaller C (since variation of input 10k capacitance will affect RC frequency more). See characterization data for desired device for varia- 20 pF 20 pF tion of oscillator frequency due to VDD for given Rext/ Cext values as well as frequency variation due to oper- Figure 14-6 shows a series resonant oscillator circuit. ating temperature for given R, C, and VDD values. This circuit is also designed to use the fundamental fre- The oscillator frequency, divided by 4, is available on quency of the crystal. The inverter performs a 180- the OSC2/CLKOUT pin, and can be used for test pur- degree phase shift in a series resonant oscillator cir- poses or to synchronize other logic (see Figure 3-4 for cuit. The 330 kW resistors provide the negative feed- waveform). back to bias the inverters in their linear region. FIGURE 14-7: RC OSCILLATOR MODE FIGURE 14-6: EXTERNAL SERIES RESONANT CRYSTAL VDD OSCILLATOR CIRCUIT Rext Internal To Other OSC1 330 kW 330 kW Devices clock 74AS04 74AS04 74AS04 PIC16CXX Cext PIC16CXX CLKIN VSS 0.1 m F OSC2/CLKOUT Fosc/4 XTAL DS30390E-page 132 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 14.3 Reset A simplified block diagram of the on-chip reset circuit is Applicable Devices shown in Figure 14-8. 727373A7474A7677 The PIC16C72/73A/74A/76/77 have a MCLR noise fil- ter in the MCLR reset path. The filter will detect and The PIC16CXX differentiates between various kinds of ignore small pulses. reset: It should be noted that a WDT Reset does not drive • Power-on Reset (POR) MCLR pin low. • MCLR reset during normal operation • MCLR reset during SLEEP • WDT Reset (normal operation) • Brown-out Reset (BOR) (PIC16C72/73A/74A/76/ 77) Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset state” on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR reset during SLEEP, and Brown- out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differ- ently in different reset situations as indicated in Table 14-5 and Table 14-6. These bits are used in soft- ware to determine the nature of the reset. See Table 14-8 for a full description of reset states of all reg- isters. FIGURE 14-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR SLEEP WDT WDT Module Time-out Reset VDD rise detect Power-on Reset VDD (2) Brown-out Reset BODEN S OST/PWRT OST Chip_Reset 10-bit Ripple counter R Q OSC1 (1) PWRT On-chip RC OSC 10-bit Ripple counter Enable PWRT (3) Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: Brown-out Reset is implemented on the PIC16C72/73A/74A/76/77. 3: See Table 14-3 and Table 14-4 for time-out situations. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 133

PIC16C7X 14.4 Power-on Reset (POR), Power-up The power-up time delay will vary from chip to chip due Timer (PWRT) and Oscillator Start-up to VDD, temperature, and process variation. See DC Timer (OST), and Brown-out Reset parameters for details. (BOR) 14.4.3 OSCILLATOR START-UP TIMER (OST) Applicable Devices 727373A7474A7677 The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the 14.4.1 POWER-ON RESET (POR) PWRT delay is over. This ensures that the crystal oscil- lator or resonator has started and stabilized. A Power-on Reset pulse is generated on-chip when The OST time-out is invoked only for XT, LP and HS VDD rise is detected (in the range of 1.5V - 2.1V). To modes and only on Power-on Reset or wake-up from take advantage of the POR, just tie the MCLR pin SLEEP. directly (or through a resistor) to VDD. This will elimi- nate external RC components usually needed to create 14.4.4 BROWN-OUT RESET (BOR) a Power-on Reset. A maximum rise time for VDD is Applicable Devices specified. See Electrical Specifications for details. 727373A7474A7677 When the device starts normal operation (exits the A configuration bit, BODEN, can disable (if clear/pro- reset condition), device operating parameters (voltage, grammed) or enable (if set) the Brown-out Reset cir- frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device cuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for must be held in reset until the operating conditions are greater than parameter #35, the brown-out situation will met. Brown-out Reset may be used to meet the startup reset the chip. A reset may not occur if VDD falls below conditions. 4.0V for less than parameter #35. The chip will remain in Brown-out Reset until VDD rises above BVDD. The For additional information, refer to Application Note Power-up Timer will now be invoked and will keep the AN607, "Power-up Trouble Shooting." chip in RESET an additional 72 ms. If VDD drops below 14.4.2 POWER-UP TIMER (PWRT) BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up The Power-up Timer provides a fixed 72 ms nominal Timer will be initialized. Once VDD rises above BVDD, time-out on power-up only, from the POR. The Power- the Power-up Timer will execute a 72 ms time delay. up Timer operates on an internal RC oscillator. The The Power-up Timer should always be enabled when chip is kept in reset as long as the PWRT is active. The Brown-out Reset is enabled. Figure 14-9 shows typi- PWRT’s time delay allows VDD to rise to an acceptable cal brown-out situations. level. A configuration bit is provided to enable/disable the PWRT. FIGURE 14-9: BROWN-OUT SITUATIONS VDD BVDD Max. BVDD Min. Internal 72 ms Reset VDD BVDD Max. BVDD Min. Internal <72 ms 72 ms Reset VDD BVDD Max. BVDD Min. Internal 72 ms Reset DS30390E-page 134 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 14.4.5 TIME-OUT SEQUENCE 14.4.6 POWER CONTROL/STATUS REGISTER (PCON) On power-up the time-out sequence is as follows: First Applicable Devices PWRT time-out is invoked after the POR time delay has 727373A7474A7677 expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of The Power Control/Status Register, PCON has up to the PWRT. For example, in RC mode with the PWRT two bits, depending upon the device. Bit0 is not imple- disabled, there will be no time-out at all. Figure 14-10, mented on the PIC16C73 or PIC16C74. Figure 14-11, and Figure 14-12 depict time-out Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is sequences on power-up. unknown on a Power-on Reset. It must then be set by Since the time-outs occur from the POR pulse, if MCLR the user and checked on subsequent resets to see if bit is kept low long enough, the time-outs will expire. Then BOR cleared, indicating a BOR occurred. The BOR bit bringing MCLR high will begin execution immediately is a "Don’t Care" bit and is not necessarily predictable (Figure 14-11). This is useful for testing purposes or to if the Brown-out Reset circuitry is disabled (by clearing synchronize more than one PIC16CXX device operat- bit BODEN in the Configuration Word). ing in parallel. Bit1 is POR (Power-on Reset Status bit). It is cleared Table 14-7 shows the reset conditions for some special on a Power-on Reset and unaffected otherwise. The function registers, while Table 14-8 shows the reset user must set this bit following a Power-on Reset. conditions for all the registers. TABLE 14-3: TIME-OUT IN VARIOUS SITUATIONS, PIC16C73/74 Oscillator Configuration Power-up Wake-up from SLEEP PWRTE = 1 PWRTE = 0 XT, HS, LP 72 ms + 1024TOSC 1024TOSC 1024 TOSC RC 72 ms — — TABLE 14-4: TIME-OUT IN VARIOUS SITUATIONS, PIC16C72/73A/74A/76/77 Oscillator Configuration Power-up Wake-up from SLEEP Brown-out PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC RC 72 ms — 72 ms — TABLE 14-5: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C73/74 POR TO PD 0 1 1 Power-on Reset 0 0 x Illegal, TO is set on POR 0 x 0 Illegal, PD is set on POR 1 0 1 WDT Reset 1 0 0 WDT Wake-up 1 u u MCLR Reset during normal operation 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP Legend: u = unchanged, x = unknown (cid:211) 1997 Microchip Technology Inc. DS30390E-page 135

PIC16C7X TABLE 14-6: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C72/73A/74A/76/77 POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 x x Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP TABLE 14-7: RESET CONDITION FOR SPECIAL REGISTERS Program STATUS PCON PCON Condition Counter Register Register Register PIC16C73/74 PIC16C72/73A/74A/76/77 Power-on Reset 000h 0001 1xxx ---- --0- ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --u- ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --u- ---- --uu WDT Reset 000h 0000 1uuu ---- --u- ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --u- ---- --uu Brown-out Reset 000h 0001 1uuu N/A ---- --u0 Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --u- ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). TABLE 14-8: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, MCLR Resets Wake-up via WDT Brown-out Reset WDT Reset or Interrupt W 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu INDF 72 73 73A 74 74A 76 77 N/A N/A N/A TMR0 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PCL 72 73 73A 74 74A 76 77 0000h 0000h PC + 1(2) STATUS 72 73 73A 74 74A 76 77 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTA 72 73 73A 74 74A 76 77 --0x 0000 --0u 0000 --uu uuuu PORTB 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTD 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTE 72 73 73A 74 74A 76 77 ---- -xxx ---- -uuu ---- -uuu PCLATH 72 73 73A 74 74A 76 77 ---0 0000 ---0 0000 ---u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-7 for reset value for specific condition. DS30390E-page 136 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X TABLE 14-8: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d) Register Applicable Devices Power-on Reset, MCLR Resets Wake-up via WDT Brown-out Reset WDT Reset or Interrupt INTCON 72 73 73A 74 74A 76 77 0000 000x 0000 000u uuuu uuuu(1) 72 73 73A 74 74A 76 77 -0-- 0000 -0-- 0000 -u-- uuuu(1) PIR1 72 73 73A 74 74A 76 77 -000 0000 -000 0000 -uuu uuuu(1) 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu(1) PIR2 72 73 73A 74 74A 76 77 ---- ---0 ---- ---0 ---- ---u(1) TMR1L 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 72 73 73A 74 74A 76 77 --00 0000 --uu uuuu --uu uuuu TMR2 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu T2CON 72 73 73A 74 74A 76 77 -000 0000 -000 0000 -uuu uuuu SSPBUF 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu CCPR1L 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 72 73 73A 74 74A 76 77 --00 0000 --00 0000 --uu uuuu RCSTA 72 73 73A 74 74A 76 77 0000 -00x 0000 -00x uuuu -uuu TXREG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu RCREG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu CCPR2L 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu ADRES 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 72 73 73A 74 74A 76 77 0000 00-0 0000 00-0 uuuu uu-u OPTION 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu TRISA 72 73 73A 74 74A 76 77 --11 1111 --11 1111 --uu uuuu TRISB 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu TRISC 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu TRISD 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu TRISE 72 73 73A 74 74A 76 77 0000 -111 0000 -111 uuuu -uuu 72 73 73A 74 74A 76 77 -0-- 0000 -0-- 0000 -u-- uuuu PIE1 72 73 73A 74 74A 76 77 -000 0000 -000 0000 -uuu uuuu 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu PIE2 72 73 73A 74 74A 76 77 ---- ---0 ---- ---0 ---- ---u 72 73 73A 74 74A 76 77 ---- --0- ---- --u- ---- --u- PCON 72 73 73A 74 74A 76 77 ---- --0u ---- --uu ---- --uu PR2 72 73 73A 74 74A 76 77 1111 1111 1111 1111 1111 1111 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-7 for reset value for specific condition. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 137

PIC16C7X TABLE 14-8: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d) Register Applicable Devices Power-on Reset, MCLR Resets Wake-up via WDT Brown-out Reset WDT Reset or Interrupt SSPADD 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu SSPSTAT 72 73 73A 74 74A 76 77 --00 0000 --00 0000 --uu uuuu TXSTA 72 73 73A 74 74A 76 77 0000 -010 0000 -010 uuuu -uuu SPBRG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu ADCON1 72 73 73A 74 74A 76 77 ---- -000 ---- -000 ---- -uuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-7 for reset value for specific condition. DS30390E-page 138 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X FIGURE 14-10:TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 14-11:TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 14-12:TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET (cid:211) 1997 Microchip Technology Inc. DS30390E-page 139

PIC16C7X FIGURE 14-13:EXTERNAL POWER-ON FIGURE 14-14:EXTERNAL BROWN-OUT RESET CIRCUIT (FOR SLOW PROTECTION CIRCUIT 1 VDD POWER-UP) VDD VDD 33k VDD 10k D R MCLR R1 40k MCLR PIC16CXX C PIC16CXX Note1: This circuit will activate reset when VDD Note1: External Power-on Reset circuit is required goes below (Vz + 0.7V) where Vz = Zener only if VDD power-up slope is too slow. The voltage. diode D helps discharge the capacitor 2: Internal brown-out detection on the quickly when VDD powers down. PIC16C72/73A/74A/76/77 should be dis- 2: R < 40 kW is recommended to make sure abled when using this circuit. that voltage drop across R does not violate 3: Resistors should be adjusted for the char- the device’s electrical specification. acteristics of the transistor. 3: R1 = 100W to 1 kW will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin break- FIGURE 14-15:EXTERNAL BROWN-OUT down due to Electrostatic Discharge PROTECTION CIRCUIT 2 (ESD) or Electrical Overstress (EOS). VDD VDD R1 Q1 MCLR R2 40k PIC16CXX Note1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that: R1 VDD • = 0.7V R1 + R2 2: Internal brown-out detection on the PIC16C72/73A/74A/76/77 should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. DS30390E-page 140 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 14.5 Interrupts instructions. Individual interrupt flag bits are set regard- Applicable Devices less of the status of their corresponding mask bit or the GIE bit. 727373A7474A7677 The PIC16C7X family has up to 12 sources of interrupt. Note: For the PIC16C73/74, if an interrupt occurs The interrupt control register (INTCON) records individ- while the Global Interrupt Enable (GIE) bit ual interrupt requests in flag bits. It also has individual is being cleared, the GIE bit may uninten- and global interrupt enable bits. tionally be re-enabled by the user’s Inter- rupt Service Routine (the RETFIE Note: Individual interrupt flag bits are set regard- instruction). The events that would cause less of the status of their corresponding this to occur are: mask bit or the GIE bit. 1. An instruction clears the GIE bit while A global interrupt enable bit, GIE (INTCON<7>) an interrupt is acknowledged. enables (if set) all un-masked interrupts or disables (if 2. The program branches to the Interrupt cleared) all interrupts. When bit GIE is enabled, and an vector and executes the Interrupt Ser- interrupt’s flag bit and mask bit are set, the interrupt will vice Routine. vector immediately. Individual interrupts can be dis- abled through their corresponding enable bits in vari- 3. The Interrupt Service Routine com- ous registers. Individual interrupt bits are set pletes with the execution of the RET- regardless of the status of the GIE bit. The GIE bit is FIE instruction. This causes the GIE cleared on reset. bit to be set (enables interrupts), and the program returns to the instruction The “return from interrupt” instruction, RETFIE, exits after the one which was meant to dis- the interrupt routine as well as sets the GIE bit, which able interrupts. re-enables interrupts. Perform the following to ensure that inter- The RB0/INT pin interrupt, the RB port change interrupt rupts are globally disabled: and the TMR0 overflow interrupt flags are contained in the INTCON register. LOOP BCF INTCON, GIE ; Disable global ; interrupt bit The peripheral interrupt flags are contained in the spe- BTFSC INTCON, GIE ; Global interrupt cial function registers PIR1 and PIR2. The correspond- ; disabled? ing interrupt enable bits are contained in special GOTO LOOP ; NO, try again function registers PIE1 and PIE2, and the peripheral : ; Yes, continue interrupt enable bit is contained in special function reg- ; with program ister INTCON. ; flow When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 14- 17). The latency is the same for one or two cycle (cid:211) 1997 Microchip Technology Inc. DS30390E-page 141

PIC16C7X FIGURE 14-16:INTERRUPT LOGIC PSPIF PSPIE ADIF T0IF Wake-up (If in SLEEP mode) ADIE T0IE RCIF INTF RCIE INTE Interrupt to CPU TXIF RBIF TXIE RBIE SSPIF SSPIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE The following table shows which devices have which interrupts. Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF PIC16C72 Yes Yes Yes - Yes - - Yes Yes Yes Yes - PIC16C73 Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes Yes PIC16C73A Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes Yes PIC16C74 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PIC16C74A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PIC16C76 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PIC16C77 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes FIGURE 14-17:INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 4 INT pin 1 1 INTF flag 5 Interrupt Latency 2 (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 PC+1 0004h 0005h Instruction fetched Inst (PC) Inst (PC+1) — Inst (0004h) Inst (0005h) Instruction Inst (PC-1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) executed Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles. DS30390E-page 142 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 14.5.1 INT INTERRUPT 14.6 Context Saving During Interrupts Applicable Devices External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set, or fall- 727373A7474A7677 ing, if the INTEDG bit is clear. When a valid edge During an interrupt, only the return PC value is saved appears on the RB0/INT pin, flag bit INTF on the stack. Typically, users may wish to save key reg- (INTCON<1>) is set. This interrupt can be disabled by isters during an interrupt i.e., W register and STATUS clearing enable bit INTE (INTCON<4>). Flag bit INTF register. This will have to be implemented in software. must be cleared in software in the interrupt service rou- Example 14-1 stores and restores the STATUS, W, and tine before re-enabling this interrupt. The INT interrupt PCLATH registers. The register, W_TEMP, must be can wake-up the processor from SLEEP, if bit INTE was defined in each bank and must be defined at the same set prior to going into SLEEP. The status of global inter- offset from the bank base address (i.e., if W_TEMP is rupt enable bit GIE decides whether or not the proces- defined at 0x20 in bank 0, it must also be defined at sor branches to the interrupt vector following wake-up. 0xA0 in bank 1). See Section 14.8 for details on SLEEP mode. The example: 14.5.2 TMR0 INTERRUPT a) Stores the W register. An overflow (FFh fi 00h) in the TMR0 register will set b) Stores the STATUS register in bank 0. flag bit T0IF (INTCON<2>). The interrupt can be c) Stores the PCLATH register. enabled/disabled by setting/clearing enable bit T0IE d) Executes the ISR code. (INTCON<5>). (Section 7.0) e) Restores the STATUS register (and bank select 14.5.3 PORTB INTCON CHANGE bit). f) Restores the W and PCLATH registers. An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 5.2) Note: For the PIC16C73/74, if a change on the I/O pin should occur when the read opera- tion is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. EXAMPLE 14-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ;Save PCLATH into W CLRF PCLATH ;Page zero, regardless of current page BCF STATUS, IRP ;Return to Bank 0 MOVF FSR, W ;Copy FSR to W MOVWF FSR_TEMP ;Copy FSR from W to FSR_TEMP : :(ISR) : MOVF PCLATH_TEMP, W ;Restore PCLATH MOVWF PCLATH ;Move W into PCLATH SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W (cid:211) 1997 Microchip Technology Inc. DS30390E-page 143

PIC16C7X 14.7 Watchdog Timer (WDT) prescaler with a division ratio of up to 1:128 can be Applicable Devices assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 727373A7474A7677 2.3 seconds can be realized. The Watchdog Timer is as a free running on-chip RC The CLRWDT and SLEEP instructions clear the WDT oscillator which does not require any external compo- and the postscaler, if assigned to the WDT, and prevent nents. This RC oscillator is separate from the RC oscil- it from timing out and generating a device RESET con- lator of the OSC1/CLKIN pin. That means that the WDT dition. will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, The TO bit in the STATUS register will be cleared upon for example, by execution of a SLEEP instruction. Dur- a Watchdog Timer time-out. ing normal operation, a WDT time-out generates a 14.7.2 WDT PROGRAMMING CONSIDERATIONS device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to It should also be taken into account that under worst wake-up and continue with normal operation (Watch- case conditions (VDD = Min., Temperature = Max., and dog Timer Wake-up). The WDT can be permanently max. WDT prescaler) it may take several seconds disabled by clearing configuration bit WDTE before a WDT time-out occurs. (Section 14.1). Note: When a CLRWDT instruction is executed 14.7.1 WDT PERIOD and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the The WDT has a nominal time-out period of 18 ms, (with prescaler assignment is not changed. no prescaler). The time-out periods vary with tempera- ture, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a FIGURE 14-18:WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 7-6) 0 M Postscaler 1 WDT Timer U X 8 8 - to - 1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure 7-6) 0 1 MUX PSA WDT Note: PSA and PS2:PS0 are bits in the OPTION register. Time-out FIGURE 14-19:SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 81h,181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note1: See Figure 14-1, and Figure 14-2 for operation of these bits. DS30390E-page 144 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 14.8 Power-down Mode (SLEEP) Other peripherals cannot generate interrupts since dur- Applicable Devices ing SLEEP, no on-chip Q clocks are present. 727373A7474A7677 When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to Power-down mode is entered by executing a SLEEP wake-up through an interrupt event, the corresponding instruction. interrupt enable bit must be set (enabled). Wake-up is If enabled, the Watchdog Timer will be cleared but regardless of the state of the GIE bit. If the GIE bit is keeps running, the PD bit (STATUS<3>) is cleared, the clear (disabled), the device continues execution at the TO (STATUS<4>) bit is set, and the oscillator driver is instruction after the SLEEP instruction. If the GIE bit is turned off. The I/O ports maintain the status they had, set (enabled), the device executes the instruction after before the SLEEP instruction was executed (driving the SLEEP instruction and then branches to the inter- high, low, or hi-impedance). rupt address (0004h). In cases where the execution of For lowest current consumption in this mode, place all the instruction following SLEEP is not desirable, the I/O pins at either VDD, or VSS, ensure no external cir- user should have a NOP after the SLEEP instruction. cuitry is drawing current from the I/O pin, power-down 14.8.2 WAKE-UP USING INTERRUPTS the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to avoid When global interrupts are disabled (GIE cleared) and switching currents caused by floating inputs. The any interrupt source has both its interrupt enable bit T0CKI input should also be at VDD or VSS for lowest and interrupt flag bit set, one of the following will occur: current consumption. The contribution from on-chip • If the interrupt occurs before the execution of a pull-ups on PORTB should be considered. SLEEP instruction, the SLEEP instruction will com- The MCLR pin must be at a logic high level (VIHMC). plete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not 14.8.1 WAKE-UP FROM SLEEP be set and PD bits will not be cleared. The device can wake up from SLEEP through one of • If the interrupt occurs during or after the execu- the following events: tion of a SLEEP instruction, the device will imme- diately wake up from sleep. The SLEEP instruction 1. External reset input on MCLR pin. will be completely executed before the wake-up. 2. Watchdog Timer Wake-up (if WDT was Therefore, the WDT and WDT postscaler will be enabled). cleared, the TO bit will be set and the PD bit will 3. Interrupt from INT pin, RB port change, or some be cleared. Peripheral Interrupts. Even if the flag bits were checked before executing a External MCLR Reset will cause a device reset. All SLEEP instruction, it may be possible for flag bits to other events are considered a continuation of program become set before the SLEEP instruction completes. To execution and cause a "wake-up". The TO and PD bits determine whether a SLEEP instruction executed, test in the STATUS register can be used to determine the the PD bit. If the PD bit is set, the SLEEP instruction cause of device reset. The PD bit, which is set on was executed as a NOP. power-up, is cleared when SLEEP is invoked. The TO To ensure that the WDT is cleared, a CLRWDT instruc- bit is cleared if a WDT time-out occurred (and caused tion should be executed before a SLEEP instruction. wake-up). The following peripheral interrupts can wake the device from SLEEP: 1. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 2. SSP (Start/Stop) bit detect interrupt. 3. SSP transmit or receive in slave mode (SPI/I2C). 4. CCP capture mode interrupt. 5. Parallel Slave Port read or write. 6. A/D conversion (when A/D clock source is RC). 7. Special event trigger (Timer1 in asynchronous mode using an external clock). 8. USART TX or RX (synchronous slave mode). (cid:211) 1997 Microchip Technology Inc. DS30390E-page 145

PIC16C7X FIGURE 14-20:WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit Processor in (INTCON<7>) SLEEP INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h Instruction fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) Ienxsetcruuctetidon Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. 3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 14.9 Program Verification/Code Protection The device is placed into a program/verify mode by Applicable Devices holding the RB6 and RB7 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming 727373A7474A7677 specification). RB6 becomes the programming clock If the code protection bit(s) have not been pro- and RB7 becomes the programming data. Both RB6 grammed, the on-chip program memory can be read and RB7 are Schmitt Trigger inputs in this mode. out for verification purposes. After reset, to place the device into programming/verify Note: Microchip does not recommend code pro- mode, the program counter (PC) is at location 00h. A 6- tecting windowed devices. bit command is then supplied to the device. Depending on the command, 14-bits of program data are then sup- 14.10 ID Locations plied to or from the device, depending if the command Applicable Devices was a load or a read. For complete details of serial pro- 727373A7474A7677 gramming, please refer to the PIC16C6X/7X Program- ming Specifications (Literature #DS30228). Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or FIGURE 14-21:TYPICAL IN-CIRCUIT SERIAL other code-identification numbers. These locations are PROGRAMMING not accessible during normal execution but are read- CONNECTION able and writable during program/verify. It is recom- mended that only the 4 least significant bits of the ID location are used. To Normal Connections External 14.11 In-Circuit Serial Programming Connector PIC16CXX Signals Applicable Devices 727373A7474A7677 +5V VDD 0V VSS PIC16CXX microcontrollers can be serially pro- VPP MCLR/VPP grammed while in the end application circuit. This is simply done with two lines for clock and data, and three CLK RB6 other lines for power, ground, and the programming voltage. This allows customers to manufacture boards Data I/O RB7 with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firm- VDD ware to be programmed. To Normal Connections DS30390E-page 146 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 15.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped into three basic categories: Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type • Byte-oriented operations and one or more operands which further specify the • Bit-oriented operations operation of the instruction. The PIC16CXX instruction • Literal and control operations set summary in Table 15-2 lists byte-oriented, bit-ori- All instructions are executed within one single instruc- ented, and literal and control operations. Table 15-1 tion cycle, unless a conditional test is true or the pro- shows the opcode field descriptions. gram counter is changed as a result of an instruction. For byte-oriented instructions, 'f' represents a file reg- In this case, the execution takes two instruction cycles ister designator and 'd' represents a destination desig- with the second cycle executed as a NOP. One instruc- nator. The file register designator specifies which file tion cycle consists of four oscillator periods. Thus, for register is to be used by the instruction. an oscillator frequency of 4 MHz, the normal instruction execution time is 1 m s. If a conditional test is true or the The destination designator specifies where the result of program counter is changed as a result of an instruc- the operation is to be placed. If 'd' is zero, the result is tion, the instruction execution time is 2 m s. placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. Table 15-2 lists the instructions recognized by the MPASM assembler. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected Figure 15-1 shows the general formats that the instruc- by the operation, while 'f' represents the number of the tions can have. file in which the bit is located. Note: To maintain upward compatibility with For literal and control operations, 'k' represents an future PIC16CXX products, do not use the eight or eleven bit constant or literal value. OPTION and TRIS instructions. TABLE 15-1: OPCODE FIELD All examples use the following format to represent a DESCRIPTIONS hexadecimal number: 0xhh Field Description where h signifies a hexadecimal digit. f Register file address (0x00 to 0x7F) W Working register (accumulator) FIGURE 15-1: GENERAL FORMAT FOR b Bit address within an 8-bit file register INSTRUCTIONS k Literal field, constant data or label Byte-oriented file register operations x Don't care location (= 0 or 1) 13 8 7 6 0 The assembler will generate code with x = 0. It is the OPCODE d f (FILE #) recommended form of use for compatibility with all Microchip software tools. d = 0 for destination W d = 1 for destination f d Destination select; d = 0: store result in W, f = 7-bit file register address d = 1: store result in file register f. Default is d = 1 label Label name Bit-oriented file register operations 13 10 9 7 6 0 TOS Top of Stack OPCODE b (BIT #) f (FILE #) PC Program Counter PCLATH Program Counter High Latch b = 3-bit bit address GIE Global Interrupt Enable bit f = 7-bit file register address WDT Watchdog Timer/Counter TO Time-out bit Literal and control operations PD Power-down bit General dest Destination either the W register or the specified register file location 13 8 7 0 [ ] Options OPCODE k (literal) ( ) Contents k = 8-bit immediate value fi Assigned to < > Register bit field CALL and GOTO instructions only ˛ In the set of 13 11 10 0 italics User defined term (font is courier) OPCODE k (literal) k = 11-bit immediate value (cid:211) 1997 Microchip Technology Inc. DS30390E-page 147

PIC16C7X TABLE 15-2: PIC16CXX INSTRUCTION SET Mnemonic, Description Cycles 14-Bit Opcode Status Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS30390E-page 148 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 15.1 Instruction Descriptions ADDLW Add Literal and W ANDLW AND Literal with W Syntax: [label] ADDLW k Syntax: [label] ANDLW k Operands: 0 £ k £ 255 Operands: 0 £ k £ 255 Operation: (W) + k fi (W) Operation: (W) .AND. (k) fi (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 111x kkkk kkkk Encoding: 11 1001 kkkk kkkk Description: The contents of the W register are Description: The contents of W register are added to the eight bit literal 'k' and the AND’ed with the eight bit literal 'k'. The result is placed in the W register. result is placed in the W register. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to literal 'k' data W literal "k" data W Example: ADDLW 0x15 Example ANDLW 0x5F Before Instruction Before Instruction W = 0x10 W = 0xA3 After Instruction After Instruction W = 0x25 W = 0x03 ADDWF Add W and f ANDWF AND W with f Syntax: [label] ADDWF f,d Syntax: [label] ANDWF f,d Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 d ˛ [0,1] d ˛ [0,1] Operation: (W) + (f) fi (destination) Operation: (W) .AND. (f) fi (destination) Status Affected: C, DC, Z Status Affected: Z Encoding: 00 0111 dfff ffff Encoding: 00 0101 dfff ffff Description: Add the contents of the W register with Description: AND the W register with register 'f'. If 'd' register 'f'. If 'd' is 0 the result is stored is 0 the result is stored in the W regis- in the W register. If 'd' is 1 the result is ter. If 'd' is 1 the result is stored back in stored back in register 'f'. register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register data destination register data destination 'f' 'f' Example ADDWF FSR, 0 Example ANDWF FSR, 1 Before Instruction Before Instruction W = 0x17 W = 0x17 FSR= 0xC2 FSR= 0xC2 After Instruction After Instruction W = 0xD9 W = 0x17 FSR= 0xC2 FSR= 0x02 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 149

PIC16C7X BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [label] BCF f,b Syntax: [label] BTFSC f,b Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 0 £ b £ 7 0 £ b £ 7 Operation: 0 fi (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Encoding: 01 00bb bfff ffff Encoding: 01 10bb bfff ffff Description: Bit 'b' in register 'f' is cleared. Description: If bit 'b' in register 'f' is '1' then the next instruction is executed. Words: 1 If bit 'b', in register 'f', is '0' then the next Cycles: 1 instruction is discarded, and a NOP is executed instead, making this a 2TCY Q Cycle Activity: Q1 Q2 Q3 Q4 instruction. Decode Read Process Write Words: 1 register data register 'f' 'f' Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Example BCF FLAG_REG, 7 Decode Read Process No- Before Instruction register 'f' data Operation FLAG_REG = 0xC7 After Instruction If Skip: (2nd Cycle) FLAG_REG = 0x47 Q1 Q2 Q3 Q4 No- No- No- No- Operation Operation Operation Operation Example HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE • • • Before Instruction PC = address HERE After Instruction if FLAG<1> = 0, BSF Bit Set f PC = address TRUE Syntax: [label] BSF f,b if FLAG<1>=1, PC = address FALSE Operands: 0 £ f £ 127 0 £ b £ 7 Operation: 1 fi (f<b>) Status Affected: None Encoding: 01 01bb bfff ffff Description: Bit 'b' in register 'f' is set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register data register 'f' 'f' Example BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A DS30390E-page 150 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 £ f £ 127 Operands: 0 £ k £ 2047 0 £ b < 7 Operation: (PC)+ 1fi TOS, Operation: skip if (f<b>) = 1 k fi PC<10:0>, (PCLATH<4:3>) fi PC<12:11> Status Affected: None Status Affected: None Encoding: 01 11bb bfff ffff Description: If bit 'b' in register 'f' is '0' then the next Encoding: 10 0kkk kkkk kkkk instruction is executed. Description: Call Subroutine. First, return address If bit 'b' is '1', then the next instruction is (PC+1) is pushed onto the stack. The discarded and a NOP is executed eleven bit immediate address is loaded instead, making this a 2TCY instruction. into PC bits <10:0>. The upper bits of Words: 1 the PC are loaded from PCLATH. CALL is a two cycle instruction. Cycles: 1(2) Words: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Cycles: 2 Decode Read Process No- Q Cycle Activity: Q1 Q2 Q3 Q4 register 'f' data Operation 1st Cycle Decode Read Process Write to If Skip: (2nd Cycle) literal 'k', data PC Q1 Q2 Q3 Q4 Push PC to Stack No- No- No- No- 2nd Cycle No- No- No- No- Operation Operation Operation Operation Operation Operation Operation Operation Example HERE BTFSC FLAG,1 Example HERE CALL THERE FALSE GOTO PROCESS_CODE TRUE • Before Instruction • PC = Address HERE • After Instruction Before Instruction PC = Address THERE TOS= Address HERE+1 PC = address HERE After Instruction if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE (cid:211) 1997 Microchip Technology Inc. DS30390E-page 151

PIC16C7X CLRF Clear f CLRW Clear W Syntax: [label] CLRF f Syntax: [ label ] CLRW Operands: 0 £ f £ 127 Operands: None Operation: 00h fi (f) Operation: 00h fi (W) 1 fi Z 1 fi Z Status Affected: Z Status Affected: Z Encoding: 00 0001 1fff ffff Encoding: 00 0001 0xxx xxxx Description: The contents of register 'f' are cleared Description: W register is cleared. Zero bit (Z) is and the Z bit is set. set. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write Decode No- Process Write to register data register 'f' Operation data W 'f' Example CLRW Example CLRF FLAG_REG Before Instruction Before Instruction W = 0x5A FLAG_REG = 0x5A After Instruction After Instruction W = 0x00 FLAG_REG = 0x00 Z = 1 Z = 1 CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h fi WDT 0 fi WDT prescaler, 1 fi TO 1 fi PD Status Affected: TO, PD Encoding: 00 0000 0110 0100 Description: CLRWDT instruction resets the Watch- dog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No- Process Clear Operation data WDT Counter Example CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = 0x00 WDT prescaler= 0 TO = 1 PD = 1 DS30390E-page 152 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF f,d Syntax: [ label ] DECFSZ f,d Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 d ˛ [0,1] d ˛ [0,1] Operation: (f) fi (destination) Operation: (f) - 1 fi (destination); Status Affected: Z skip if result = 0 Encoding: 00 1001 dfff ffff Status Affected: None Description: The contents of register 'f' are comple- Encoding: 00 1011 dfff ffff mented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in Description: The contents of register 'f' are decre- register 'f'. mented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed Words: 1 back in register 'f'. If the result is 1, the next instruction, is Cycles: 1 executed. If the result is 0, then a NOP is executed instead making it a 2TCY instruc- Q Cycle Activity: Q1 Q2 Q3 Q4 tion. Decode Read Process Write to Words: 1 register data destination 'f' Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Example COMF REG1,0 Decode Read Process Write to Before Instruction register 'f' data destination REG1 = 0x13 If Skip: (2nd Cycle) After Instruction Q1 Q2 Q3 Q4 REG1 = 0x13 W = 0xEC No- No- No- No- Operation Operation Operation Operation DECF Decrement f Example HERE DECFSZ CNT, 1 Syntax: [label] DECF f,d GOTO LOOP Operands: 0 £ f £ 127 CONTINUE • d ˛ [0,1] • • Operation: (f) - 1 fi (destination) Before Instruction Status Affected: Z PC = address HERE After Instruction Encoding: 00 0011 dfff ffff CNT = CNT - 1 Description: Decrement register 'f'. If 'd' is 0 the if CNT= 0, result is stored in the W register. If 'd' is PC = address CONTINUE 1 the result is stored back in register 'f'. if CNT„ 0, Words: 1 PC = address HERE+1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register data destination 'f' Example DECF CNT, 1 Before Instruction CNT = 0x01 Z = 0 After Instruction CNT = 0x00 Z = 1 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 153

PIC16C7X GOTO Unconditional Branch INCF Increment f Syntax: [ label ] GOTO k Syntax: [ label ] INCF f,d Operands: 0 £ k £ 2047 Operands: 0 £ f £ 127 Operation: k fi PC<10:0> d ˛ [0,1] PCLATH<4:3> fi PC<12:11> Operation: (f) + 1 fi (destination) Status Affected: None Status Affected: Z Encoding: 10 1kkk kkkk kkkk Encoding: 00 1010 dfff ffff Description: GOTO is an unconditional branch. The Description: The contents of register 'f' are incre- eleven bit immediate value is loaded mented. If 'd' is 0 the result is placed in into PC bits <10:0>. The upper bits of the W register. If 'd' is 1 the result is PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction. placed back in register 'f'. Words: 1 Words: 1 Cycles: 2 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 1st Cycle Decode Read Process Write to Decode Read Process Write to literal 'k' data PC register data destination 'f' 2nd Cycle No- No- No- No- Operation Operation Operation Operation Example INCF CNT, 1 Example GOTO THERE Before Instruction CNT = 0xFF After Instruction Z = 0 PC = Address THERE After Instruction CNT = 0x00 Z = 1 DS30390E-page 154 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X INCFSZ Increment f, Skip if 0 IORLW Inclusive OR Literal with W Syntax: [ label ] INCFSZ f,d Syntax: [ label ] IORLW k Operands: 0 £ f £ 127 Operands: 0 £ k £ 255 d ˛ [0,1] Operation: (W) .OR. k fi (W) Operation: (f) + 1 fi (destination), Status Affected: Z skip if result = 0 Encoding: 11 1000 kkkk kkkk Status Affected: None Description: The contents of the W register is Encoding: 00 1111 dfff ffff OR’ed with the eight bit literal 'k'. The Description: The contents of register 'f' are incre- result is placed in the W register. mented. If 'd' is 0 the result is placed in Words: 1 the W register. If 'd' is 1 the result is placed back in register 'f'. Cycles: 1 If the result is 1, the next instruction is executed. If the result is 0, a NOP is Q Cycle Activity: Q1 Q2 Q3 Q4 executed instead making it a 2TCY instruction. Decode Read Process Write to Words: 1 literal 'k' data W Cycles: 1(2) Example IORLW 0x35 Q Cycle Activity: Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write to W = 0x9A register 'f' data destination After Instruction If Skip: (2nd Cycle) W = 0xBF Z = 1 Q1 Q2 Q3 Q4 No- No- No- No- Operation Operation Operation Operation Example HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE • • • Before Instruction PC = address HERE After Instruction CNT = CNT + 1 if CNT= 0, PC = address CONTINUE if CNT„ 0, PC = address HERE +1 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 155

PIC16C7X IORWF Inclusive OR W with f MOVLW Move Literal to W Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVLW k Operands: 0 £ f £ 127 Operands: 0 £ k £ 255 d ˛ [0,1] Operation: k fi (W) Operation: (W) .OR. (f) fi (destination) Status Affected: None Status Affected: Z Encoding: 11 00xx kkkk kkkk Encoding: 00 0100 dfff ffff Description: The eight bit literal 'k' is loaded into W Description: Inclusive OR the W register with regis- register. The don’t cares will assemble ter 'f'. If 'd' is 0 the result is placed in the as 0’s. W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to literal 'k' data W Decode Read Process Write to register data destination 'f' Example MOVLW 0x5A After Instruction Example IORWF RESULT, 0 W = 0x5A Before Instruction RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93 Z = 1 MOVF Move f MOVWF Move W to f Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (W) fi (f) Operation: (f) fi (destination) Status Affected: None Status Affected: Z Encoding: 00 0000 1fff ffff Encoding: 00 1000 dfff ffff Description: Move data from W register to register Description: The contents of register f is moved to a 'f'. destination dependant upon the status Words: 1 of d. If d = 0, destination is W register. If d = 1, the destination is file register f Cycles: 1 itself. d = 1 is useful to test a file regis- Q Cycle Activity: Q1 Q2 Q3 Q4 ter since status flag Z is affected. Decode Read Process Write Words: 1 register data register 'f' 'f' Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Example MOVWF OPTION_REG Decode Read Process Write to Before Instruction register data destination 'f' OPTION = 0xFF W = 0x4F After Instruction Example MOVF FSR, 0 OPTION = 0x4F After Instruction W = 0x4F W = value in FSR register Z = 1 DS30390E-page 156 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] NOP Syntax: [ label ] RETFIE Operands: None Operands: None Operation: No operation Operation: TOS fi PC, 1 fi GIE Status Affected: None Status Affected: None Encoding: 00 0000 0xx0 0000 Encoding: 00 0000 0000 1001 Description: No operation. Description: Return from Interrupt. Stack is POPed Words: 1 and Top of Stack (TOS) is loaded in the Cycles: 1 PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE Q Cycle Activity: Q1 Q2 Q3 Q4 (INTCON<7>). This is a two cycle Decode No- No- No- instruction. Operation Operation Operation Words: 1 Example NOP Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 1st Cycle Decode No- Set the Pop from Operation GIE bit the Stack 2nd Cycle No- No- No- No- Operation Operation Operation Operation Example RETFIE After Interrupt PC = TOS GIE = 1 OPTION Load Option Register Syntax: [ label ] OPTION Operands: None Operation: (W) fi OPTION Status Affected: None Encoding: 00 0000 0110 0010 Description: The contents of the W register are loaded in the OPTION register. This instruction is supported for code com- patibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. Words: 1 Cycles: 1 Example To maintain upward compatibility with future PIC16CXX products, do not use this instruction. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 157

PIC16C7X RETLW Return with Literal in W RETURN Return from Subroutine Syntax: [ label ] RETLW k Syntax: [ label ] RETURN Operands: 0 £ k £ 255 Operands: None Operation: k fi (W); Operation: TOS fi PC TOS fi PC Status Affected: None Status Affected: None Encoding: 00 0000 0000 1000 Encoding: 11 01xx kkkk kkkk Description: Return from subroutine. The stack is Description: The W register is loaded with the eight POPed and the top of the stack (TOS) bit literal 'k'. The program counter is is loaded into the program counter. This loaded from the top of the stack (the is a two cycle instruction. return address). This is a two cycle Words: 1 instruction. Cycles: 2 Words: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Cycles: 2 1st Cycle Decode No- No- Pop from Q Cycle Activity: Q1 Q2 Q3 Q4 Operation Operation the Stack 1st Cycle Decode Read No- Write to W, 2nd Cycle No- No- No- No- literal 'k' Operation Pop from Operation Operation Operation Operation the Stack 2nd Cycle No- No- No- No- Example RETURN Operation Operation Operation Operation After Interrupt Example CALL TABLE ;W contains table PC = TOS ;offset value • ;W now has table value • • TABLE ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 DS30390E-page 158 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] RLF f,d Syntax: [ label ] RRF f,d Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 d ˛ [0,1] d ˛ [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: 00 1101 dfff ffff Encoding: 00 1100 dfff ffff Description: The contents of register 'f' are rotated Description: The contents of register 'f' are rotated one bit to the left through the Carry one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored W register. If 'd' is 1 the result is placed back in register 'f'. back in register 'f'. C Register f C Register f Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register data destination register data destination 'f' 'f' Example RLF REG1,0 Example RRF REG1,0 Before Instruction Before Instruction REG1 = 1110 0110 REG1 = 1110 0110 C = 0 C = 0 After Instruction After Instruction REG1 = 1110 0110 REG1 = 1110 0110 W = 1100 1100 W = 0111 0011 C = 1 C = 0 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 159

PIC16C7X SLEEP SUBLW Subtract W from Literal Syntax: [ label ] SLEEP Syntax: [ label ] SUBLW k Operands: None Operands: 0 £ k £ 255 Operation: 00h fi WDT, Operation: k - (W) fi ( W) 0 fi WDT prescaler, Status Affected: C, DC, Z 1 fi TO, Encoding: 11 110x kkkk kkkk 0 fi PD Description: The W register is subtracted (2’s comple- Status Affected: TO, PD ment method) from the eight bit literal 'k'. Encoding: 00 0000 0110 0011 The result is placed in the W register. Description: The power-down status bit, PD is Words: 1 cleared. Time-out status bit, TO is Cycles: 1 set. Watchdog Timer and its pres- caler are cleared. Q Cycle Activity: Q1 Q2 Q3 Q4 The processor is put into SLEEP Decode Read Process Write to W mode with the oscillator stopped. See literal 'k' data Section 14.8 for more details. Words: 1 Example 1: SUBLW 0x02 Cycles: 1 Before Instruction Q Cycle Activity: Q1 Q2 Q3 Q4 W = 1 C = ? Decode No- No- Go to Operation Operation Sleep Z = ? After Instruction Example: SLEEP W = 1 C = 1; result is positive Z = 0 Example 2: Before Instruction W = 2 C = ? Z = ? After Instruction W = 0 C = 1; result is zero Z = 1 Example 3: Before Instruction W = 3 C = ? Z = ? After Instruction W = 0xFF C = 0; result is negative Z = 0 DS30390E-page 160 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] SUBWF f,d Syntax: [ label ] SWAPF f,d Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 d ˛ [0,1] d ˛ [0,1] Operation: (f) - (W) fi ( destination) Operation: (f<3:0>) fi (destination<7:4>), (f<7:4>) fi (destination<3:0>) Status Affected: C, DC, Z Status Affected: None Encoding: 00 0010 dfff ffff Encoding: 00 1110 dfff ffff Description: Subtract (2’s complement method) W reg- ister from register 'f'. If 'd' is 0 the result is Description: The upper and lower nibbles of register stored in the W register. If 'd' is 1 the 'f' are exchanged. If 'd' is 0 the result is result is stored back in register 'f'. placed in W register. If 'd' is 1 the result is placed in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register 'f' data destination Decode Read Process Write to register 'f' data destination Example 1: SUBWF REG1,1 Example SWAPF REG, 0 Before Instruction Before Instruction REG1 = 3 W = 2 REG1 = 0xA5 C = ? After Instruction Z = ? REG1 = 0xA5 After Instruction W = 0x5A REG1 = 1 W = 2 C = 1; result is positive Z = 0 Example 2: Before Instruction TRIS Load TRIS Register REG1 = 2 Syntax: [label] TRIS f W = 2 Operands: 5 £ f £ 7 C = ? Z = ? Operation: (W) fi TRIS register f; After Instruction Status Affected: None Encoding: 00 0000 0110 0fff REG1 = 0 W = 2 Description: The instruction is supported for code C = 1; result is zero compatibility with the PIC16C5X prod- Z = 1 ucts. Since TRIS registers are read- Example 3: Before Instruction able and writable, the user can directly address them. REG1 = 1 Words: 1 W = 2 C = ? Cycles: 1 Z = ? Example After Instruction To maintain upward compatibility REG1 = 0xFF with future PIC16CXX products, do W = 2 not use this instruction. C = 0; result is negative Z = 0 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 161

PIC16C7X XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [label] XORLW k Syntax: [label] XORWF f,d Operands: 0 £ k £ 255 Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (W) .XOR. k fi ( W) Operation: (W) .XOR. (f) fi ( destination) Status Affected: Z Status Affected: Z Encoding: 11 1010 kkkk kkkk Encoding: 00 0110 dfff ffff Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. Description: Exclusive OR the contents of the W The result is placed in the W regis- register with register 'f'. If 'd' is 0 the ter. result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to literal 'k' data W Decode Read Process Write to register data destination 'f' Example: XORLW 0xAF Before Instruction Example XORWF REG 1 W = 0xB5 Before Instruction After Instruction REG = 0xAF W = 0xB5 W = 0x1A After Instruction REG = 0x1A W = 0xB5 DS30390E-page 162 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 16.0 DEVELOPMENT SUPPORT 16.3 ICEPIC: Low-cost PIC16CXXX In-Circuit Emulator 16.1 Development Tools ICEPIC is a low-cost in-circuit emulator solution for the The PIC16/17 microcontrollers are supported with a full Microchip PIC16C5X and PIC16CXXX families of 8-bit range of hardware and software development tools: OTP microcontrollers. • PICMASTER/PICMASTER CE Real-Time ICEPIC is designed to operate on PC-compatible In-Circuit Emulator machines ranging from 286-AT(cid:226) through Pentium(cid:228) • ICEPIC Low-Cost PIC16C5X and PIC16CXXX based machines under Windows 3.x environment. In-Circuit Emulator ICEPIC features real time, non-intrusive emulation. (cid:226) • PRO MATE II Universal Programmer 16.4 PRO MATE II: Universal Programmer (cid:226) • PICSTART Plus Entry-Level Prototype Programmer The PRO MATE II Universal Programmer is a full-fea- • PICDEM-1 Low-Cost Demonstration Board tured programmer capable of operating in stand-alone • PICDEM-2 Low-Cost Demonstration Board mode as well as PC-hosted mode. • PICDEM-3 Low-Cost Demonstration Board The PRO MATE II has programmable VDD and VPP • MPASM Assembler supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has • MPLAB-SIM Software Simulator an LCD display for displaying error messages, keys to • MPLAB-C (C Compiler) enter commands and a modular detachable socket • Fuzzy logic development system (fuzzyTECH(cid:226) - MP) assembly to support various package types. In stand- alone mode the PRO MATE II can read, verify or pro- 16.2 PICMASTER: High Performance gram PIC16C5X, PIC16CXXX, PIC17CXX and Universal In-Circuit Emulator with PIC14000 devices. It can also set configuration and MPLAB IDE code-protect bits in this mode. The PICMASTER Universal In-Circuit Emulator is 16.5 PICSTART Plus Entry Level intended to provide the product development engineer Development System with a complete microcontroller design tool set for all microcontrollers in the PIC12C5XX, PIC14C000, The PICSTART programmer is an easy-to-use, low- PIC16C5X, PIC16CXXX and PIC17CXX families. cost prototype programmer. It connects to the PC via PICMASTER is supplied with the MPLAB(cid:228) Integrated one of the COM (RS-232) ports. MPLAB Integrated Development Environment (IDE), which allows editing, Development Environment software makes using the “make” and download, and source debugging from a programmer simple and efficient. PICSTART Plus is single environment. not recommended for production programming. Interchangeable target probes allow the system to be PICSTART Plus supports all PIC12C5XX, PIC14000, easily reconfigured for emulation of different proces- PIC16C5X, PIC16CXXX and PIC17CXX devices with sors. The universal architecture of the PICMASTER up to 40 pins. Larger pin count devices such as the allows expansion to support all new Microchip micro- PIC16C923 and PIC16C924 may be supported with an controllers. adapter socket. The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (cid:226) (and higher) machine platform and Microsoft Windows 3.x environment were chosen to best make these fea- tures available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 163

PIC16C7X 16.6 PICDEM-1 Low-Cost PIC16/17 an RS-232 interface, push-button switches, a potenti- Demonstration Board ometer for simulated analog input, a thermistor and separate headers for connection to an external LCD The PICDEM-1 is a simple board which demonstrates module and a keypad. Also provided on the PICDEM-3 the capabilities of several of Microchip’s microcontrol- board is an LCD panel, with 4 commons and 12 seg- lers. The microcontrollers supported are: PIC16C5X ments, that is capable of displaying time, temperature (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, and day of the week. The PICDEM-3 provides an addi- PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and tional RS-232 interface and Windows 3.1 software for PIC17C44. All necessary hardware and software is showing the demultiplexed LCD signals on a PC. A sim- included to run basic demo programs. The users can ple serial interface allows the user to construct a hard- program the sample microcontrollers provided with ware demultiplexer for the LCD signals. the PICDEM-1 board, on a PRO MATE II or PICSTART-16B programmer, and easily test firm- 16.9 MPLAB Integrated Development ware. The user can also connect the PICDEM-1 Environment Software board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional pro- The MPLAB IDE Software brings an ease of software totype area is available for the user to build some addi- development previously unseen in the 8-bit microcon- tional hardware and connect it to the microcontroller troller market. MPLAB is a windows based application socket(s). Some of the features include an RS-232 which contains: interface, a potentiometer for simulated analog input, • A full featured editor push-button switches and eight LEDs connected to • Three operating modes PORTB. - editor - emulator 16.7 PICDEM-2 Low-Cost PIC16CXX - simulator Demonstration Board • A project manager • Customizable tool bar and key mapping The PICDEM-2 is a simple demonstration board that • A status bar with project information supports the PIC16C62, PIC16C64, PIC16C65, • Extensive on-line help PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to MPLAB allows you to: run the basic demonstration programs. The user • Edit your source files (either assembly or ‘C’) can program the sample microcontrollers provided • One touch assemble (or compile) and download with the PICDEM-2 board, on a PRO MATE II pro- to PIC16/17 tools (automatically updates all grammer or PICSTART-16C, and easily test firmware. project information) The PICMASTER emulator may also be used with the • Debug using: PICDEM-2 board to test firmware. Additional prototype - source files area has been provided to the user for adding addi- - absolute listing file tional hardware and connecting it to the microcontroller • Transfer data dynamically via DDE (soon to be socket(s). Some of the features include a RS-232 inter- replaced by OLE) face, push-button switches, a potentiometer for simu- • Run up to four emulators on the same PC lated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connec- The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily tion to an LCD module and a keypad. switch from the low cost simulator to the full featured 16.8 PICDEM-3 Low-Cost PIC16CXXX emulator with minimal retraining due to development Demonstration Board tools. 16.10 Assembler (MPASM) The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC The MPASM Universal Macro Assembler is a PC- package. It will also support future 44-pin PLCC hosted symbolic assembler. It supports all microcon- microcontrollers with a LCD Module. All the neces- troller series including the PIC12C5XX, PIC14000, sary hardware and software is included to run the PIC16C5X, PIC16CXXX, and PIC17CXX families. basic demonstration programs. The user can pro- gram the sample microcontrollers provided with MPASM offers full featured Macro capabilities, condi- the PICDEM-3 board, on a PRO MATE II program- tional assembly, and several source and listing formats. mer or PICSTART Plus with an adapter socket, and It generates various object code formats to support easily test firmware. The PICMASTER emulator may Microchip's development tools as well as third party also be used with the PICDEM-3 board to test firm- programmers. ware. Additional prototype area has been provided to MPASM allows full symbolic debugging from the user for adding hardware and connecting it to the PICMASTER, Microchip’s Universal Emulator microcontroller socket(s). Some of the features include System. DS30390E-page 164 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X MPASM has the following features to assist in develop- 16.14 MP-DriveWay(cid:228) – Application Code ing software for specific use applications. Generator • Provides translation of Assembler source code to MP-DriveWay is an easy-to-use Windows-based Appli- object code for all Microchip microcontrollers. cation Code Generator. With MP-DriveWay you can • Macro assembly capability. visually configure all the peripherals in a PIC16/17 • Produces all the files (Object, Listing, Symbol, device and, with a click of the mouse, generate all the and special) required for symbolic debug with initialization and many functional code modules in C Microchip’s emulator systems. language. The output is fully compatible with Micro- • Supports Hex (default), Decimal and Octal source chip’s MPLAB-C C compiler. The code produced is and listing formats. highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain MPASM provides a rich directive language to support your code through subsequent code generation. programming of the PIC16/17. Directives are helpful in making the development of your assemble source code 16.15 SEEVAL(cid:226) Evaluation and shorter and more maintainable. Programming System 16.11 Software Simulator (MPLAB-SIM) The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit The MPLAB-SIM Software Simulator allows code includes everything necessary to read, write, erase or development in a PC host environment. It allows the program special features of any Microchip SEEPROM user to simulate the PIC16/17 series microcontrollers product including Smart Serials(cid:212) and secure serials. on an instruction level. On any given instruction, the The Total Endurance(cid:212) Disk is included to aid in trade- user may examine or modify any of the data areas or off analysis and reliability calculations. The total kit can provide external stimulus to any of the pins. The input/ significantly reduce time-to-market and result in an output radix can be set by the user and the execution optimized system. can be performed in; single step, execute until break, or in a trace mode. 16.16 TrueGauge(cid:226) Intelligent Battery MPLAB-SIM fully supports symbolic debugging using Management MPLAB-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code out- The TrueGauge development tool supports system side of the laboratory environment making it an excel- development with the MTA11200B TrueGauge Intelli- lent multi-project software development tool. gent Battery Management IC. System design verifica- tion can be accomplished before hardware prototypes 16.12 C Compiler (MPLAB-C) are built. User interface is graphically-oriented and measured data can be saved in a file for exporting to The MPLAB-C Code Development System is a Microsoft Excel. complete ‘C’ compiler and integrated development environment for Microchip’s PIC16/17 family of micro- 16.17 KEELOQ(cid:226) Evaluation and controllers. The compiler provides powerful integration Programming Tools capabilities and ease of use not found with other compilers. KEELOQ evaluation and programming tools support For easier source level debugging, the compiler pro- Microchips HCS Secure Data Products. The HCS eval- vides symbol information that is compatible with the uation kit includes an LCD display to show changing MPLAB IDE memory display (PICMASTER emulator codes, a decoder to decode transmissions, and a pro- software versions 1.13 and later). gramming interface to program test transmitters. 16.13 Fuzzy Logic Development System (fuzzyTECH-MP) fuzzyTECH-MP fuzzy logic development tool is avail- able in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, edition for imple- menting more complex systems. Both versions include Microchip’s fuzzyLAB(cid:228) demon- stration board for hands-on experience with fuzzy logic systems implementation. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 165

PIC16C7X TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP 001 000 S2S3S3 4 4 CCC 4 HHH XXX CXCXCX 4 4 453 4 229 X 5 e C7 abl97 C17 Avail3Q 4 4 4 4 PI X 4 C 17 4 4 4 4 4 4 4 4 C PI X X 9 C 4 6 4 4 4 4 4 4 1 C PI X 8 C 16 4 4 4 4 4 4 4 4 4 4 C PI X X 7 6C 4 4 4 4 4 4 4 4 4 4 1 C PI X 6 C 16 4 4 4 4 4 4 4 4 4 4 C PI X X X 6C 4 4 4 4 4 4 4 4 4 1 C PI X 5 C 6 4 4 4 4 4 4 4 4 4 4 1 C PI 0 0 0 4 4 4 4 4 4 4 1 C PI X X 5 C 4 4 4 4 4 4 4 2 1 C PI (cid:226)PICMASTER/PICMASTER-CEIn-Circuit Emulator ICEPIC Low-CostIn-Circuit Emulator (cid:228)MPLABIntegratedDevelopmentEnvironment(cid:228)MPLAB CCompiler(cid:226)fuzzyTECH-MPExplorer/EditionFuzzy LogicDev. Tool(cid:228)MP-DriveWayApplicationsCode Generator(cid:228)Total EnduranceSoftware Model(cid:226)PICSTARTLite Ultra Low-CostDev. Kit(cid:226)PICSTARTPlus Low-CostUniversal Dev. Kit(cid:226)PRO MATE IIUniversalProgrammer(cid:226)KEELOQProgrammer(cid:226)SEEVALDesigners Kit PICDEM-1 PICDEM-2 PICDEM-3 (cid:226)KEELOQEvaluation Kit stcudorP rotalumE slooT erawtfoS sremmargorP sdraoB omeD DS30390E-page 166 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.0 ELECTRICAL CHARACTERISTICS FOR PIC16C72 Absolute Maximum Ratings † Ambient temperature under bias..................................................................................................................-55 to +125˚C Storage temperature............................................................................................................................... -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +14V Voltage on RA4 with respect to Vss...................................................................................................................0 to +14V Total power dissipation (Note 1).................................................................................................................................1.0W Maximum current out of VSS pin............................................................................................................................300 mA Maximum current into VDD pin...............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................– 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................– 20 mA Maximum output current sunk by any I/O pin...........................................................................................................25 mA Maximum output current sourced by any I/O pin.....................................................................................................25 mA Maximum current sunk by PORTA and PORTB (combined)..................................................................................200 mA Maximum current sourced by PORTA and PORTB (combined).............................................................................200 mA Maximum current sunk by PORTC........................................................................................................................200 mA Maximum current sourced by PORTC...................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - (cid:229) IOH} + (cid:229) {(VDD - VOH) x IOH} + (cid:229) (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100W should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 17-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) OSC PIC16C72-04 PIC16C72-10 PIC16C72-20 PIC16LC72-04 JW Devices VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V RC IIDPDD:: 51 6m mAA m maaxx. .a at t5 4.5VV IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 35..80 mmAA mmaaxx. . aatt 33V.0V IIDPDD:: 51 6m mAA m maaxx. .a at t5 4.5VV Freq:4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq:4 MHz max. VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V XT IIDPDD:: 51 6m mAA m maaxx. .a at t5 4.5VV IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 35..80 mmAA mmaaxx. . aatt 33V.0V IIDPDD:: 51 6m mAA m maaxx. .a at t5 4.5VV Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V Not recommended for use IDD: 20 mA max. at 5.5V HS IPD: 1.5 m A typ. at 4.5V IPD: 1.5 m A typ. at 4.5V IPD: 1.5 m A typ. at 4.5V in HS mode IPD: 1.5 m A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq:20 MHz max. Freq: 20 MHz max. VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 52.5 m A typ. at Not recommended for use Not recommended for use IDD: 48 m A max. at IDD: 48 m A max. at LP 32 kHz, 4.0V 32 kHz, 3.0V 32 kHz, 3.0V IPD: 0.9 m A typ. at 4.0V in LP mode in LP mode IPD: 5.0 m A max. at 3.0V IPD: 5.0 m A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 167

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.1 DC Characteristics: PIC16C72-04 (Commercial, Industrial, Extended) PIC16C72-10 (Commercial, Industrial, Extended) PIC16C72-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +125˚C for extended, DC CHARACTERISTICS -40˚C £ TA £ +85˚C for industrial and 0˚C £ TA £ +70˚C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power- on Reset Signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset Signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled 3.7 4.0 4.4 V Extended Only D010 Supply Current IDD - 2.7 5.0 mA XT, RC osc configuration (Note 2,5) FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 10 20 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V D015 Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) D020 Power-down Current IPD - 10.5 42 m A VDD = 4.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3,5) - 1.5 16 m A VDD = 4.0V, WDT disabled, -0(cid:176) C to +70(cid:176) C D021A - 1.5 19 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C D021B - 2.5 19 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +125(cid:176) C D023 Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 m A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30390E-page 168 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.2 DC Characteristics: PIC16LC72-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +85˚C for industrial and DC CHARACTERISTICS 0˚C £ TA £ +70˚C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 2.5 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention Volt- VDR - 1.5 - V age (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled D010 Supply Current IDD - 2.0 3.8 mA XT, RC osc configuration (Note 2,5) FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 m A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D015* Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) D020 Power-down Current IPD - 7.5 30 m A VDD = 3.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3,5) - 0.9 5 m A VDD = 3.0V, WDT disabled, 0(cid:176) C to +70(cid:176) C D021A - 0.9 5 m A VDD = 3.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C D023* Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 m A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 169

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.3 DC Characteristics: PIC16C72-04 (Commercial, Industrial, Extended) PIC16C72-10 (Commercial, Industrial, Extended) PIC16C72-20 (Commercial, Industrial, Extended) PIC16LC72-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +125˚C for extended, -40˚C £ TA £ +85˚C for industrial and DC CHARACTERISTICS 0˚C £ TA £ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 17.1 and Section 17.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5 £ VDD £ 5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5 £ VDD £ 5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 †400 m A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - – 1 m A Vss £ VPIN £ VDD, Pin at hi- impedance D061 MCLR, RA4/T0CKI - - – 5 m A Vss £ VPIN £ VDD D063 OSC1 - - – 5 m A Vss £ VPIN £ VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. DS30390E-page 170 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +125˚C for extended, -40˚C £ TA £ +85˚C for industrial and DC CHARACTERISTICS 0˚C £ TA £ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 17.1 and Section 17.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Output High Voltage D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D092A VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D150* Open-Drain High Voltage VOD - - 14 V RA4 pin Capacitive Loading Specs on Out- put Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC mode) CIO - - 50 pF D102 SCL, SDA in I2C mode CB - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 171

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 17-1: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464W CL = 50 pF for all pins except OSC2 15 pF for OSC2 output DS30390E-page 172 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.5 Timing Diagrams and Specifications FIGURE 17-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 17-2: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — m s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — m s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — m s LP oscillator 15 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 173

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 18 12 14 19 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure 17-1 for load conditions. TABLE 17-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1› to CLKOUTfl — 75 200 ns Note 1 11* TosH2ckH OSC1› to CLKOUT› — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT fl to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT › TOSC + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT › 0 — — ns Note 1 17* TosH2ioV OSC1› (Q1 cycle) to — 50 150 ns Port out valid 18* TosH2ioI OSC1› (Q2 cycle) to PIC16C72 100 — — ns Port input invalid (I/O in PIC16LC72 200 — — ns hold time) 19* TioV2osH Port input valid to OSC1› (I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C72 — 10 40 ns PIC16LC72 — — 80 ns 21* TioF Port output fall time PIC16C72 — 10 40 ns PIC16LC72 — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. †Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30390E-page 174 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 17-1 for load conditions. FIGURE 17-5: BROWN-OUT RESET TIMING VDD BVDD 35 TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — m s VDD = 5V, -40˚C to +125˚C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40˚C to +125˚C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C 34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 m s or Watchdog Timer Reset 35 TBOR Brown-out Reset pulse width 100 — — m s VDD £ BVDD (D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 175

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure 17-1 for load conditions. TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet parameter 42 With Prescaler 10 — — ns 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C7X 15 — — ns parameter 47 Prescaler = PIC16LC7X 25 — — ns 2,4,8 Asynchronous PIC16C7X 30 — — ns PIC16LC7X 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C7X 15 — — ns parameter 47 Prescaler = PIC16LC7X 25 — — ns 2,4,8 Asynchronous PIC16C7X 30 — — ns PIC16LC7X 50 — — ns 47* Tt1P T1CKI input period Synchronous PIC16C7X Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8) N PIC16LC7X Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous PIC16C7X 60 — — ns PIC16LC7X 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 176 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 17-1 for load conditions. TABLE 17-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Param Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 input low time No Prescaler 0.5TCY + 20 — — ns With Prescaler PIC16C72 10 — — ns PIC16LC72 20 — — ns 51* TccH CCP1 input high time No Prescaler 0.5TCY + 20 — — ns With Prescaler PIC16C72 10 — — ns PIC16LC72 20 — — ns 52* TccP CCP1 input period 3TCY + 40 — — ns N = prescale N value (1,4 or 16) 53* TccR CCP1 output rise time PIC16C72 — 10 25 ns PIC16LC72 — 25 45 ns 54* TccF CCP1 output fall time PIC16C72 — 10 25 ns PIC16LC72 — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 177

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO 75, 76 77 SDI 74 73 Note: Refer to Figure 17-1 for load conditions TABLE 17-7: SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 70 TssL2scH, SSfl to SCKfl or SCK› input TCY — — ns TssL2scL 71 TscH SCK input high time (slave mode) TCY + 20 — — ns 72 TscL SCK input low time (slave mode) TCY + 20 — — ns 73 TdiV2scH, Setup time of SDI data input to SCK 50 — — ns TdiV2scL edge 74 TscH2diL, Hold time of SDI data input to SCK 50 — — ns TscL2diL edge 75 TdoR SDO data output rise time — 10 25 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS› to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time (master mode) — 10 25 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, SDO data output valid after SCK — — 50 ns TscL2doV edge † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 178 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-9: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure 17-1 for load conditions TABLE 17-8: I2C BUS START/STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No. 90 TSU:STA START condition 100 kHz mode 4700 — — Only relevant for repeated START ns Setup time 400 kHz mode 600 — — condition 91 THD:STA START condition 100 kHz mode 4000 — — After this period the first clock ns Hold time 400 kHz mode 600 — — pulse is generated 92 TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — (cid:211) 1997 Microchip Technology Inc. DS30390E-page 179

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-10:I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 17-1 for load conditions TABLE 17-9: I2C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100 kHz mode 4.0 — m s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — m s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101 TLOW Clock low time 100 kHz mode 4.7 — m s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — m s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102 TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 103 TF SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 90 TSU:STA START condition 100 kHz mode 4.7 — m s Only relevant for repeated setup time 400 kHz mode 0.6 — m s START condition 91 THD:STA START condition hold 100 kHz mode 4.0 — m s After this period the first clock time 400 kHz mode 0.6 — m s pulse is generated 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 m s 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92 TSU:STO STOP condition setup 100 kHz mode 4.7 — m s time 400 kHz mode 0.6 — m s 109 TAA Output valid from 100 kHz mode — 3500 ns Note 1 clock 400 kHz mode — — ns 110 TBUF Bus free time 100 kHz mode 4.7 — m s Time the bus must be free 400 kHz mode 1.3 — m s before a new transmission can start Cb Bus capacitive loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz)S I2C-bus system, but the requirement tsu;DAT ‡ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. DS30390E-page 180 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 17-10: A/D CONVERTER CHARACTERISTICS: PIC16C72-04 (Commercial, Industrial, Extended) PIC16C72-10 (Commercial, Industrial, Extended) PIC16C72-20 (Commercial, Industrial, Extended) PIC16LC72-04 (Commercial, Industrial) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 8-bits bit VREF = VDD = 5.12V, VSS £ VAIN £ VREF A02 EABS Total Absolute error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A03 EIL Integral linearity error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A04 EDL Differential linearity error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A05 EFS Full scale error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A06 EOFF Offset error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A10 — Monotonicity — guaranteed — — VSS £ VAIN £ VREF A20 VREF Reference voltage 3.0V — VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V A30 ZAIN Recommended impedance of — — 10.0 kW analog voltage source A40 IAD A/D conversion current (VDD) PIC16C72 — 180 — m A Average current consump- PIC16LC72 — 90 — m A tion when A/D is on. (Note 1) A50 IREF VREF input current (Note 2) 10 — 1000 m A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 13.1. — — 10 m A During A/D Conversion cycle * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 181

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-11:A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY 134 (TOSC/2) (1) 131 Q4 130 A/D CLK 132 A/D DATA 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 17-11: A/D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D clock period PIC16C72 1.6 — — m s TOSC based, VREF ‡ 3.0V PIC16LC72 2.0 — — m s TOSC based, VREF full range PIC16C72 2.0 4.0 6.0 m s A/D RC Mode PIC16LC72 3.0 6.0 9.0 m s A/D RC Mode 131 TCNV Conversion time (not including S/H — 9.5 — TAD time) (Note 1) 132 TACQ Acquisition time Note 2 20 — m s 5* — — m s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 135 TSWC Switching from convert fi sample time 1.5 § — — TAD * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 13.1 for min conditions. DS30390E-page 182 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.0 ELECTRICAL CHARACTERISTICS FOR PIC16C73/74 Absolute Maximum Ratings † Ambient temperature under bias..................................................................................................................-55 to +125˚C Storage temperature............................................................................................................................... -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4)...........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +14V Voltage on RA4 with respect to Vss...................................................................................................................0 to +14V Total power dissipation (Note 1).................................................................................................................................1.0W Maximum current out of VSS pin............................................................................................................................300 mA Maximum current into VDD pin...............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................– 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................– 20 mA Maximum output current sunk by any I/O pin...........................................................................................................25 mA Maximum output current sourced by any I/O pin.....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3).....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)...............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3)...................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3)..............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - (cid:229) IOH} + (cid:229) {(VDD - VOH) x IOH} + (cid:229) (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100W should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE are not implemented on the PIC16C73. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 18-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C73-04 PIC16C73-10 PIC16C73-20 PIC16LC73-04 OSC JW Devices PIC16C74-04 PIC16C74-10 PIC16C74-20 PIC16LC74-04 VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 3.0V to 6.0V VDD: 4.0V to 6.0V RC IIDPDD:: 52 1m mAA m maaxx. .a at t5 4.5VV IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 31.38. 5m mAA m maaxx. .a at t3 3.0VV IIDPDD:: 52 1m mAA m maaxx. .a at t5 4.5VV Freq:4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq:4 MHz max. VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 3.0V to 6.0V VDD: 4.0V to 6.0V XT IIDPDD:: 52 1m mAA m maaxx. .a at t5 4.5VV IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 31.38. 5m mAA m maaxx. .a at t3 3.0VV IIDPDD:: 52 1m mAA m maaxx. .a at t5 4.5VV Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 15 mA max. at 5.5V IDD: 30 mA max. at 5.5V Not recommended for IDD: 30 mA max. at 5.5V HS IPD: 1.5 m A typ. at 4.5V IPD: 1.5 m A typ. at 4.5V IPD: 1.5 m A typ. at 4.5V use in HS mode IPD: 1.5 m A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq:20 MHz max. Freq: 20 MHz max. VDD: 4.0V to 6.0V VDD: 3.0V to 6.0V VDD: 3.0V to 6.0V IDD: 52.5 m A typ. at Not recommended for Not recommended for IDD: 48 m A max. at IDD: 48 m A max. at LP 32 kHz, 4.0V 32 kHz, 3.0V 32 kHz, 3.0V IPD: 0.9 m A typ. at 4.0V use in LP mode use in LP mode IPD: 13.5 m A max. at 3.0V IPD: 13.5 m A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 183

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.1 DC Characteristics: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40˚C £ TA £ +85˚C for industrial and 0˚C £ TA £ +70˚C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D010 Supply Current (Note 2,5) IDD - 2.7 5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 13.5 30 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V D020 Power-down Current IPD - 10.5 42 m A VDD = 4.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3,5) - 1.5 21 m A VDD = 4.0V, WDT disabled, -0(cid:176) C to +70(cid:176) C D021A - 1.5 24 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 m A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. DS30390E-page 184 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.2 DC Characteristics: PIC16LC73/74-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40˚C £ TA £ +85˚C for industrial and 0˚C £ TA £ +70˚C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 3.0 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D010 Supply Current (Note 2,5) IDD - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 m A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D020 Power-down Current IPD - 7.5 30 m A VDD = 3.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3,5) - 0.9 13.5 m A VDD = 3.0V, WDT disabled, 0(cid:176) C to +70(cid:176) C D021A - 0.9 18 m A VDD = 3.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 m A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 185

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.3 DC Characteristics: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) PIC16LC73/74-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +85˚C for industrial and DC CHARACTERISTICS 0˚C £ TA £ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 18.1 and Section 18.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5V £ VDD £ 5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5V £ VDD £ 5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 400 m A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - – 1 m A Vss £ VPIN £ VDD, Pin at hi-imped- ance D061 MCLR, RA4/T0CKI - - – 5 m A Vss £ VPIN £ VDD D063 OSC1 - - – 5 m A Vss £ VPIN £ VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C Output High Voltage D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D150* Open-Drain High Voltage VOD - - 14 V RA4 pin * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30390E-page 186 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +85˚C for industrial and DC CHARACTERISTICS 0˚C £ TA £ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 18.1 and Section 18.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when exter- nal clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC CIO - - 50 pF D102 mode) SCL, SDA in I2C mode CB - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 187

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 18-1: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464W CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports 15 pF for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16C73. DS30390E-page 188 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.5 Timing Diagrams and Specifications FIGURE 18-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 18-2: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — m s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — m s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) High or 50 — — ns XT oscillator TosH Low Time 2.5 — — m s LP oscillator 15 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 189

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 18 12 14 19 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure 18-1 for load conditions. TABLE 18-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1› to CLKOUTfl — 75 200 ns Note 1 11* TosH2ckH OSC1› to CLKOUT› — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT fl to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT › 0.25TCY + 25 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT › 0 — — ns Note 1 17* TosH2ioV OSC1› (Q1 cycle) to — 50 150 ns Port out valid 18* TosH2ioI OSC1› (Q2 cycle) to PIC16C73/74 100 — — ns Port input invalid (I/O in PIC16LC73/74 200 — — ns hold time) 19* TioV2osH Port input valid to OSC1› (I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C73/74 — 10 25 ns PIC16LC73/74 — — 60 ns 21* TioF Port output fall time PIC16C73/74 — 10 25 ns PIC16LC73/74 — — 60 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. †Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30390E-page 190 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 18-1 for load conditions. TABLE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 100 — — ns VDD = 5V, -40˚C to +85˚C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40˚C to +85˚C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +85˚C 34 TIOZ I/O Hi-impedance from MCLR Low — — 100 ns or Watchdog Timer Reset * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 191

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure 18-1 for load conditions. TABLE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet parameter 42 With Prescaler 10 — — ns 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C7X 15 — — ns parameter 47 Prescaler = PIC16LC7X 25 — — ns 2,4,8 Asynchronous PIC16C7X 30 — — ns PIC16LC7X 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C7X 15 — — ns parameter 47 Prescaler = PIC16LC7X 25 — — ns 2,4,8 Asynchronous PIC16C7X 30 — — ns PIC16LC7X 50 — — ns 47* Tt1P T1CKI input period Synchronous PIC16C7X Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8) N PIC16LC7X Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous PIC16C7X 60 — — ns PIC16LC7X 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 192 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 18-1 for load conditions. TABLE 18-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input low time PIC16C73/74 10 — — ns With Prescaler PIC16LC73/74 20 — — ns 51* TccH CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input high time PIC16C73/74 10 — — ns With Prescaler PIC16LC73/74 20 — — ns 52* TccP CCP1 and CCP2 input period 3TCY + 40 — — ns N = prescale value N (1,4 or 16) 53* TccR CCP1 and CCP2 output fall time PIC16C73/74 — 10 25 ns PIC16LC73/74 — 25 45 ns 54* TccF CCP1 and CCP2 output fall time PIC16C73/74 — 10 25 ns PIC16LC73/74 — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 193

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-7: PARALLEL SLAVE PORT TIMING (PIC16C74) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 18-1 for load conditions TABLE 18-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C74) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 62 TdtV2wrH Data in valid before WR› or CS› (setup time) 20 — — ns 63* TwrH2dtI WR› or CS› to data–in invalid (hold time) PIC16C74 20 — — ns PIC16LC74 35 — — ns 64 TrdL2dtV RDfl and CSfl to data–out valid — — 80 ns 65 TrdH2dtI RD› or CSfl to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 194 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO 75, 76 77 SDI 74 73 Note: Refer to Figure 18-1 for load conditions TABLE 18-8: SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 70 TssL2scH, SSfl to SCKfl or SCK› input TCY — — ns TssL2scL 71 TscH SCK input high time (slave mode) TCY + 20 — — ns 72 TscL SCK input low time (slave mode) TCY + 20 — — ns 73 TdiV2scH, Setup time of SDI data input to SCK 50 — — ns TdiV2scL edge 74 TscH2diL, Hold time of SDI data input to SCK 50 — — ns TscL2diL edge 75 TdoR SDO data output rise time — 10 25 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS› to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time (master mode) — 10 25 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, SDO data output valid after SCK — — 50 ns TscL2doV edge † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 195

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-9: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure 18-1 for load conditions TABLE 18-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No. 90 TSU:STA START condition 100 kHz mode 4700 — — Only relevant for repeated START ns Setup time 400 kHz mode 600 — — condition 91 THD:STA START condition 100 kHz mode 4000 — — After this period the first clock ns Hold time 400 kHz mode 600 — — pulse is generated 92 TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — DS30390E-page 196 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-10:I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 18-1 for load conditions TABLE 18-10: I2C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100 kHz mode 4.0 — m s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — m s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101 TLOW Clock low time 100 kHz mode 4.7 — m s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — m s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102 TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 103 TF SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 90 TSU:STA START condition 100 kHz mode 4.7 — m s Only relevant for repeated setup time 400 kHz mode 0.6 — m s START condition 91 THD:STA START condition hold 100 kHz mode 4.0 — m s After this period the first clock time 400 kHz mode 0.6 — m s pulse is generated 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 m s 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92 TSU:STO STOP condition setup 100 kHz mode 4.7 — m s time 400 kHz mode 0.6 — m s 109 TAA Output valid from 100 kHz mode — 3500 ns Note 1 clock 400 kHz mode — — ns 110 TBUF Bus free time 100 kHz mode 4.7 — m s Time the bus must be free 400 kHz mode 1.3 — m s before a new transmission can start Cb Bus capacitive loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT ‡ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 197

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-11:USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK 121 pin 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 18-1 for load conditions TABLE 18-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) PIC16C73/74 — — 80 ns Clock high to data out valid PIC16LC73/74 — — 100 ns 121 Tckrf Clock out rise time and fall time PIC16C73/74 — — 45 ns (Master Mode) PIC16LC73/74 — — 50 ns 122 Tdtrf Data out rise time and fall time PIC16C73/74 — — 45 ns PIC16LC73/74 — — 50 ns †: Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 18-12:USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure 18-1 for load conditions TABLE 18-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 125 TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK fl (DT setup time) 15 — — ns 126 TckL2dtl Data hold after CK fl (DT hold time) 15 — — ns †: Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 198 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 18-13: A/D CONVERTER CHARACTERISTICS: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) PIC16LC73/74-04 (Commercial, Industrial) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 8-bits bit VREF = VDD = 5.12V, VSS £ VAIN £ VREF A02 EABS Total Absolute error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A03 EIL Integral linearity error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A04 EDL Differential linearity error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A05 EFS Full scale error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A06 EOFF Offset error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A10 — Monotonicity — guaranteed — — VSS £ VAIN £ VREF A20 VREF Reference voltage 3.0V — VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V A30 ZAIN Recommended impedance of — — 10.0 kW analog voltage source A40 IAD A/D conversion current PIC16C73/74 — 180 — m A Average current consump- (VDD) PIC16LC73/74 — 90 — m A tion when A/D is on. (Note 1) A50 IREF VREF input current (Note 2) 10 — 1000 m A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 13.1. — — 10 m A During A/D Conversion cycle * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 199

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-13:A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY 134 (TOSC/2) (1) 131 Q4 130 A/D CLK 132 A/D DATA 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 18-14: A/D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D clock period PIC16C73/74 1.6 — — m s TOSC based, VREF ‡ 3.0V PIC16LC73/74 2.0 — — m s TOSC based, VREF full range PIC16C73/74 2.0 4.0 6.0 m s A/D RC Mode PIC16LC73/74 3.0 6.0 9.0 m s A/D RC Mode 131 TCNV Conversion time (not including S/H time) — 9.5 — TAD (Note 1) 132 TACQ Acquisition time Note 2 20 — m s 5* — — m s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 135 TSWC Switching from convert fi sample time 1.5 § — — TAD * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 13.1 for min conditions. DS30390E-page 200 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.0 ELECTRICAL CHARACTERISTICS FOR PIC16C73A/74A Absolute Maximum Ratings † Ambient temperature under bias..................................................................................................................-55 to +125˚C Storage temperature............................................................................................................................... -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4)...........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +14V Voltage on RA4 with respect to Vss...................................................................................................................0 to +14V Total power dissipation (Note 1).................................................................................................................................1.0W Maximum current out of VSS pin............................................................................................................................300 mA Maximum current into VDD pin...............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................– 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................– 20 mA Maximum output current sunk by any I/O pin...........................................................................................................25 mA Maximum output current sourced by any I/O pin.....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3).....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)...............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3)...................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3)..............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - (cid:229) IOH} + (cid:229) {(VDD - VOH) x IOH} + (cid:229) (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100W should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE are not implemented on the PIC16C73A. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 19-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C73A-04 PIC16C73A-10 PIC16C73A-20 PIC16LC73A-04 OSC JW Devices PIC16C74A-04 PIC16C74A-10 PIC16C74A-20 PIC16LC74A-04 VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V RC IIDPDD:: 51 6m mAA m maaxx. .a at t5 4.5VV IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 35. m8 Am mA amx.a axt. a3tV 3.0V IIDPDD:: 51 6m mAA m maaxx. .a at t5 4.5VV Freq:4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq:4 MHz max. VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V XT IIDPDD:: 51 6m mAA m maaxx. .a at t5 4.5VV IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 21..75 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 35. m8 Am mA amx.a axt. a3tV 3.0V IIDPDD:: 51 6m mAA m maaxx. .a at t5 4.5VV Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V Not recommended for IDD: 20 mA max. at 5.5V HS IPD: 1.5 m A typ. at 4.5V IPD: 1.5 m A typ. at 4.5V IPD: 1.5 m A typ. at 4.5V use in HS mode IPD: 1.5 m A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq:20 MHz max. Freq: 20 MHz max. VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 52.5 m A typ. at Not recommended for Not recommended for IDD: 48 m A max. at IDD: 48 m A max. at LP 32 kHz, 4.0V 32 kHz, 3.0V 32 kHz, 3.0V IPD: 0.9 m A typ. at 4.0V use in LP mode use in LP mode IPD: 5.0 m A max. at 3.0V IPD: 5.0 m A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 201

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.1 DC Characteristics: PIC16C73A/74A-04 (Commercial, Industrial, Extended) PIC16C73A/74A-10 (Commercial, Industrial, Extended) PIC16C73A/74A-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +125˚C for extended, DC CHARACTERISTICS -40˚C £ TA £ +85˚C for industrial and 0˚C £ TA £ +70˚C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled 3.7 4.0 4.4 V Extended Range Only D010 Supply Current (Note 2,5) IDD - 2.7 5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 10 20 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V D015* Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) D020 Power-down Current IPD - 10.5 42 m A VDD = 4.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3,5) - 1.5 16 m A VDD = 4.0V, WDT disabled, -0(cid:176) C to +70(cid:176) C D021A - 1.5 19 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C D021B - 2.5 19 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +125(cid:176) C D023* Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 m A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30390E-page 202 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.2 DC Characteristics: PIC16LC73A/74A-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40˚C £ TA £ +85˚C for industrial and 0˚C £ TA £ +70˚C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 2.5 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled D010 Supply Current (Note 2,5) IDD - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 m A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D015* Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) D020 Power-down Current IPD - 7.5 30 m A VDD = 3.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3,5) - 0.9 5 m A VDD = 3.0V, WDT disabled, 0(cid:176) C to +70(cid:176) C D021A - 0.9 5 m A VDD = 3.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C D023* Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 m A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 203

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.3 DC Characteristics: PIC16C73A/74A-04 (Commercial, Industrial, Extended) PIC16C73A/74A-10 (Commercial, Industrial, Extended) PIC16C73A/74A-20 (Commercial, Industrial, Extended) PIC16LC73A/74A-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +125˚C for extended, -40˚C £ TA £ +85˚C for industrial and DC CHARACTERISTICS 0˚C £ TA £ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 19.1 and Section 19.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V 4.5V £ VDD £ 5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5V £ VDD £ 5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 400 m A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - – 1 m A Vss £ VPIN £ VDD, Pin at hi-imped- ance D061 MCLR, RA4/T0CKI - - – 5 m A Vss £ VPIN £ VDD D063 OSC1 - - – 5 m A Vss £ VPIN £ VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30390E-page 204 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +125˚C for extended, -40˚C £ TA £ +85˚C for industrial and DC CHARACTERISTICS 0˚C £ TA £ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 19.1 and Section 19.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Output High Voltage D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D092A VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D150* Open-Drain High Voltage VOD - - 14 V RA4 pin Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when exter- nal clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC CIO - - 50 pF D102 mode) SCL, SDA in I2C mode CB - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 205

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 19-1: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464W CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports 15 pF for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16C73A. DS30390E-page 206 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.5 Timing Diagrams and Specifications FIGURE 19-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 19-2: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — m s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — m s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — m s LP oscillator 15 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 207

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 18 12 14 19 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure 19-1 for load conditions. TABLE 19-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1› to CLKOUTfl — 75 200 ns Note 1 11* TosH2ckH OSC1› to CLKOUT› — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT fl to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT › TOSC + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT › 0 — — ns Note 1 17* TosH2ioV OSC1› (Q1 cycle) to — 50 150 ns Port out valid 18* TosH2ioI OSC1› (Q2 cycle) to PIC16C73A/74A 100 — — ns Port input invalid (I/O in PIC16LC73A/74A 200 — — ns hold time) 19* TioV2osH Port input valid to OSC1› (I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C73A/74A — 10 40 ns PIC16LC73A/74A — — 80 ns 21* TioF Port output fall time PIC16C73A/74A — 10 40 ns PIC16LC73A/74A — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. †Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30390E-page 208 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 19-1 for load conditions. FIGURE 19-5: BROWN-OUT RESET TIMING VDD BVDD 35 TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — m s VDD = 5V, -40˚C to +125˚C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40˚C to +125˚C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C 34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 m s or Watchdog Timer Reset 35 TBOR Brown-out Reset pulse width 100 — — m s VDD £ BVDD (D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 209

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure 19-1 for load conditions. TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet parameter 42 With Prescaler 10 — — ns 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C7X 15 — — ns parameter 47 Prescaler = PIC16LC7X 25 — — ns 2,4,8 Asynchronous PIC16C7X 30 — — ns PIC16LC7X 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C7X 15 — — ns parameter 47 Prescaler = PIC16LC7X 25 — — ns 2,4,8 Asynchronous PIC16C7X 30 — — ns PIC16LC7X 50 — — ns 47* Tt1P T1CKI input period Synchronous PIC16C7X Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8) N PIC16LC7X Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous PIC16C7X 60 — — ns PIC16LC7X 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 210 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 19-1 for load conditions. TABLE 19-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input low time PIC16C73A/74A 10 — — ns With Prescaler PIC16LC73A/74A 20 — — ns 51* TccH CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input high time PIC16C73A/74A 10 — — ns With Prescaler PIC16LC73A/74A 20 — — ns 52* TccP CCP1 and CCP2 input period 3TCY + 40 — — ns N = prescale N value (1,4 or 16) 53* TccR CCP1 and CCP2 output rise time PIC16C73A/74A — 10 25 ns PIC16LC73A/74A — 25 45 ns 54* TccF CCP1 and CCP2 output fall time PIC16C73A/74A — 10 25 ns PIC16LC73A/74A — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 211

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-8: PARALLEL SLAVE PORT TIMING (PIC16C74A) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 19-1 for load conditions TABLE 19-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C74A) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 62 TdtV2wrH Data in valid before WR› or CS› (setup time) 20 — — ns 25 — — ns Extended Range Only 63* TwrH2dtI WR› or CS› to data–in invalid (hold time) PIC16C74A 20 — — ns PIC16LC74A 35 — — ns 64 TrdL2dtV RDfl and CSfl to data–out valid — — 80 ns — — 90 ns Extended Range Only 65 TrdH2dtI RD› or CSfl to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 212 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO 75, 76 77 SDI 74 73 Note: Refer to Figure 19-1 for load conditions TABLE 19-8: SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 70 TssL2scH, SSfl to SCKfl or SCK› input TCY — — ns TssL2scL 71 TscH SCK input high time (slave mode) TCY + 20 — — ns 72 TscL SCK input low time (slave mode) TCY + 20 — — ns 73 TdiV2scH, Setup time of SDI data input to SCK 100 — — ns TdiV2scL edge 74 TscH2diL, Hold time of SDI data input to SCK 100 — — ns TscL2diL edge 75 TdoR SDO data output rise time — 10 25 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS› to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time (master mode) — 10 25 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, SDO data output valid after SCK — — 50 ns TscL2doV edge † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 213

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-10:I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure 19-1 for load conditions TABLE 19-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No. 90 TSU:STA START condition 100 kHz mode 4700 — — Only relevant for repeated START ns Setup time 400 kHz mode 600 — — condition 91 THD:STA START condition 100 kHz mode 4000 — — After this period the first clock ns Hold time 400 kHz mode 600 — — pulse is generated 92 TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — DS30390E-page 214 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-11:I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 19-1 for load conditions TABLE 19-10: I2C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100 kHz mode 4.0 — m s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — m s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101 TLOW Clock low time 100 kHz mode 4.7 — m s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — m s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102 TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 103 TF SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 90 TSU:STA START condition 100 kHz mode 4.7 — m s Only relevant for repeated setup time 400 kHz mode 0.6 — m s START condition 91 THD:STA START condition hold 100 kHz mode 4.0 — m s After this period the first clock time 400 kHz mode 0.6 — m s pulse is generated 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 m s 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92 TSU:STO STOP condition setup 100 kHz mode 4.7 — m s time 400 kHz mode 0.6 — m s 109 TAA Output valid from 100 kHz mode — 3500 ns Note 1 clock 400 kHz mode — — ns 110 TBUF Bus free time 100 kHz mode 4.7 — m s Time the bus must be free 400 kHz mode 1.3 — m s before a new transmission can start Cb Bus capacitive loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT ‡ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 215

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-12:USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK 121 pin 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 19-1 for load conditions TABLE 19-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) PIC16C73A/74A — — 80 ns Clock high to data out valid PIC16LC73A/74A — — 100 ns 121 Tckrf Clock out rise time and fall time PIC16C73A/74A — — 45 ns (Master Mode) PIC16LC73A/74A — — 50 ns 122 Tdtrf Data out rise time and fall time PIC16C73A/74A — — 45 ns PIC16LC73A/74A — — 50 ns †: Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 19-13:USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure 19-1 for load conditions TABLE 19-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 125 TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK fl (DT setup time) 15 — — ns 126 TckL2dtl Data hold after CK fl (DT hold time) 15 — — ns †: Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 216 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 19-13: A/D CONVERTER CHARACTERISTICS: PIC16C73A/74A-04 (Commercial, Industrial, Extended) PIC16C73A/74A-10 (Commercial, Industrial, Extended) PIC16C73A/74A-20 (Commercial, Industrial, Extended) PIC16LC73A/74A-04 (Commercial, Industrial) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 8-bits bit VREF = VDD = 5.12V, VSS £ VAIN £ VREF A02 EABS Total Absolute error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A03 EIL Integral linearity error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A04 EDL Differential linearity error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A05 EFS Full scale error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A06 EOFF Offset error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A10 — Monotonicity — guaranteed — — VSS £ VAIN £ VREF A20 VREF Reference voltage 3.0V — VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V A30 ZAIN Recommended impedance of — — 10.0 kW analog voltage source A40 IAD A/D conversion current PIC16C73A/74A — 180 — m A Average current consump- (VDD) PIC16LC73A/74A — 90 — m A tion when A/D is on. (Note 1) A50 IREF VREF input current (Note 2) 10 — 1000 m A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 13.1. — — 10 m A During A/D Conversion cycle * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 217

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-14:A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY 134 (TOSC/2) (1) 131 Q4 130 A/D CLK 132 A/D DATA 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 19-14: A/D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D clock period PIC16C73A/74A 1.6 — — m s TOSC based, VREF ‡ 3.0V PIC16LC73A/74A 2.0 — — m s TOSC based, VREF full range PIC16C73A/74A 2.0 4.0 6.0 m s A/D RC Mode PIC16LC73A/74A 3.0 6.0 9.0 m s A/D RC Mode 131 TCNV Conversion time (not including S/H time) — 9.5 — TAD (Note 1) 132 TACQ Acquisition time Note 2 20 — m s 5* — — m s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 135 TSWC Switching from convert fi sample time 1.5 § — — TAD * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 13.1 for min conditions. DS30390E-page 218 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.0 ELECTRICAL CHARACTERISTICS FOR PIC16C76/77 Absolute Maximum Ratings † Ambient temperature under bias..................................................................................................................-55 to +125˚C Storage temperature............................................................................................................................... -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4)...........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +14V Voltage on RA4 with respect to Vss...................................................................................................................0 to +14V Total power dissipation (Note 1).................................................................................................................................1.0W Maximum current out of VSS pin............................................................................................................................300 mA Maximum current into VDD pin...............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................– 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................– 20 mA Maximum output current sunk by any I/O pin...........................................................................................................25 mA Maximum output current sourced by any I/O pin.....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3).....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)...............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3)...................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3)..............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - (cid:229) IOH} + (cid:229) {(VDD - VOH) x IOH} + (cid:229) (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100W should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE are not implemented on the PIC16C76. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 219

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 20-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C76-04 PIC16C76-10 PIC16C76-20 PIC16LC76-04 OSC JW Devices PIC16C77-04 PIC16C77-10 PIC16C77-20 PIC16LC77-04 VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V IDD: 5 mA max. IDD: 2.7 mA typ. IDD: 2.7 mA typ. IDD: 5 mA max. IDD: 3.8 mA max. at 5.5V at 5.5V at 5.5V at 5.5V RC at 3.0V IPD: 16 m A max. IPD: 1.5 m A typ. IPD: 1.5 m A typ. IPD: 5 m A max. at 3V IPD: 16 m A max. at 4V at 4V at 4V at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V IDD: 5 mA max. IDD: 2.7 mA typ. IDD: 2.7 mA typ. IDD: 5 mA max. IDD: 3.8 mA max. at 5.5V at 5.5V at 5.5V at 5.5V XT at 3.0V IPD: 16 m A max. IPD: 1.5 m A typ. IPD: 1.5 m A typ. IPD: 5 m A max. at 3V IPD: 16 m A max. at 4V at 4V at 4V at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. IDD: 10 mA max. IDD: 20 mA max. IDD: 20 mA max. at 5.5V at 5.5V at 5.5V Not recommended for at 5.5V HS IPD: 1.5 m A typ. IPD: 1.5 m A typ. IPD: 1.5 m A typ. use in HS mode IPD: 1.5 m A typ. at 4.5V at 4.5V at 4.5V at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max. VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 52.5 m A typ. IDD: 48 m A max. IDD: 48 m A max. at 32 kHz, 4.0V Not recommended for Not recommended for at 32 kHz, 3.0V at 32 kHz, 3.0V LP IPD: 0.9 m A typ. use in LP mode use in LP mode IPD: 5.0 m A max. IPD: 5.0 m A max. at 4.0V at 3.0V at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. DS30390E-page 220 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.1 DC Characteristics: PIC16C76/77-04 (Commercial, Industrial, Extended) PIC16C76/77-10 (Commercial, Industrial, Extended) PIC16C76/77-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +125˚C for extended, DC CHARACTERISTICS -40˚C £ TA £ +85˚C for industrial and 0˚C £ TA £ +70˚C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled 3.7 4.0 4.4 V Extended Range Only D010 Supply Current (Note 2,5) IDD - 2.7 5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 10 20 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V D015* Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) D020 Power-down Current IPD - 10.5 42 m A VDD = 4.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3,5) - 1.5 16 m A VDD = 4.0V, WDT disabled, -0(cid:176) C to +70(cid:176) C D021A - 1.5 19 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C D021B - 2.5 19 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +125(cid:176) C D023* Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 m A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 221

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.2 DC Characteristics: PIC16LC76/77-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40˚C £ TA £ +85˚C for industrial and 0˚C £ TA £ +70˚C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 2.5 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled D010 Supply Current (Note 2,5) IDD - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 m A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D015* Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) D020 Power-down Current IPD - 7.5 30 m A VDD = 3.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3,5) - 0.9 5 m A VDD = 3.0V, WDT disabled, 0(cid:176) C to +70(cid:176) C D021A - 0.9 5 m A VDD = 3.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C D023* Brown-out Reset Current D IBOR - 350 425 m A BOR enabled VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 m A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30390E-page 222 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.3 DC Characteristics: PIC16C76/77-04 (Commercial, Industrial, Extended) PIC16C76/77-10 (Commercial, Industrial, Extended) PIC16C76/77-20 (Commercial, Industrial, Extended) PIC16LC76/77-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +125˚C for extended, -40˚C £ TA £ +85˚C for industrial and DC CHARACTERISTICS 0˚C £ TA £ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 20.1 and Section 20.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5V £ VDD £ 5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5V £ VDD £ 5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 400 m A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - – 1 m A Vss £ VPIN £ VDD, Pin at hi-imped- ance D061 MCLR, RA4/T0CKI - - – 5 m A Vss £ VPIN £ VDD D063 OSC1 - - – 5 m A Vss £ VPIN £ VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 223

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C £ TA £ +125˚C for extended, -40˚C £ TA £ +85˚C for industrial and DC CHARACTERISTICS 0˚C £ TA £ +70˚C for commercial Operating voltage VDD range as described in DC spec Section 20.1 and Section 20.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Output High Voltage D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D092A VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D150* Open-Drain High Voltage VOD - - 14 V RA4 pin Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when exter- nal clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC CIO - - 50 pF D102 mode) SCL, SDA in I2C mode CB - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30390E-page 224 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 20-1: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464W CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports 15 pF for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16C76. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 225

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.5 Timing Diagrams and Specifications FIGURE 20-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 20-2: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — m s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) HS osc mode (-20) 50 — 250 ns 5 — — m s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — m s LP oscillator 15 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. DS30390E-page 226 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 18 12 14 19 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure 20-1 for load conditions. TABLE 20-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1› to CLKOUTfl — 75 200 ns Note 1 11* TosH2ckH OSC1› to CLKOUT› — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT fl to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT › TOSC + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT › 0 — — ns Note 1 17* TosH2ioV OSC1› (Q1 cycle) to — 50 150 ns Port out valid 18* TosH2ioI OSC1› (Q2 cycle) to PIC16C76/77 100 — — ns Port input invalid (I/O in PIC16LC76/77 200 — — ns hold time) 19* TioV2osH Port input valid to OSC1› (I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C76/77 — 10 40 ns PIC16LC76/77 — — 80 ns 21* TioF Port output fall time PIC16C76/77 — 10 40 ns PIC16LC76/77 — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 227

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 20-1 for load conditions. FIGURE 20-5: BROWN-OUT RESET TIMING VDD BVDD 35 TABLE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — m s VDD = 5V, -40˚C to +125˚C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40˚C to +125˚C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C 34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 m s or Watchdog Timer Reset 35 TBOR Brown-out Reset pulse width 100 — — m s VDD £ BVDD (D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 228 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure 20-1 for load conditions. TABLE 20-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet parameter 42 With Prescaler 10 — — ns 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C7X 15 — — ns parameter 47 Prescaler = PIC16LC7X 25 — — ns 2,4,8 Asynchronous PIC16C7X 30 — — ns PIC16LC7X 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C7X 15 — — ns parameter 47 Prescaler = PIC16LC7X 25 — — ns 2,4,8 Asynchronous PIC16C7X 30 — — ns PIC16LC7X 50 — — ns 47* Tt1P T1CKI input period Synchronous PIC16C7X Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8) N PIC16LC7X Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous PIC16C7X 60 — — ns PIC16LC7X 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 229

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 20-1 for load conditions. TABLE 20-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input low time PIC16C76/77 10 — — ns With Prescaler PIC16LC76/77 20 — — ns 51* TccH CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input high time PIC16C76/77 10 — — ns With Prescaler PIC16LC76/77 20 — — ns 52* TccP CCP1 and CCP2 input period 3TCY + 40 — — ns N = prescale N value (1,4 or 16) 53* TccR CCP1 and CCP2 output rise time PIC16C76/77 — 10 25 ns PIC16LC76/77 — 25 45 ns 54* TccF CCP1 and CCP2 output fall time PIC16C76/77 — 10 25 ns PIC16LC76/77 — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 230 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-8: PARALLEL SLAVE PORT TIMING (PIC16C77) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 20-1 for load conditions TABLE 20-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C77) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 62 TdtV2wrH Data in valid before WR› or CS› (setup time) 20 — — ns 25 — — ns Extended Range Only 63* TwrH2dtI WR› or CS› to data–in invalid (hold time) PIC16C77 20 — — ns PIC16LC77 35 — — ns 64 TrdL2dtV RDfl and CSfl to data–out valid — — 80 ns — — 90 ns Extended Range Only 65 TrdH2dtI RD› or CSfl to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 231

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-9: SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSB BIT6 - - - - - -1 LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 20-1 for load conditions. FIGURE 20-10:SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSB BIT6 - - - - - -1 LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 Refer to Figure 20-1 for load conditions. DS30390E-page 232 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-11:SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSB BIT6 - - - - - -1 LSB 75, 76 77 SSDDII MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 20-1 for load conditions. FIGURE 20-12:SPI SLAVE MODE TIMING (CKE = 1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSB BIT6 - - - - - -1 LSB 75, 76 77 SSDDII MSB IN BIT6 - - - -1 LSB IN 74 Refer to Figure 20-1 for load conditions. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 233

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 20-8: SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 70* TssL2scH, SSfl to SCKfl or SCK› input TCY — — ns TssL2scL 71* TscH SCK input high time (slave mode) TCY + 20 — — ns 72* TscL SCK input low time (slave mode) TCY + 20 — — ns 73* TdiV2scH, Setup time of SDI data input to SCK 100 — — ns TdiV2scL edge 74* TscH2diL, Hold time of SDI data input to SCK 100 — — ns TscL2diL edge 75* TdoR SDO data output rise time — 10 25 ns 76* TdoF SDO data output fall time — 10 25 ns 77* TssH2doZ SS› to SDO output hi-impedance 10 — 50 ns 78* TscR SCK output rise time (master mode) — 10 25 ns 79* TscF SCK output fall time (master mode) — 10 25 ns 80* TscH2doV, SDO data output valid after SCK — — 50 ns TscL2doV edge 81* TdoV2scH, SDO data output setup to SCK TCY — — ns TdoV2scL edge 82* TssL2doV SDO data output valid after SSfl — — 50 ns edge 83* TscH2ssH, SS › after SCK edge 1.5TCY + 40 — — ns TscL2ssH * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 234 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-13:I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure 20-1 for load conditions TABLE 20-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No. 90 TSU:STA START condition 100 kHz mode 4700 — — Only relevant for repeated START ns Setup time 400 kHz mode 600 — — condition 91 THD:STA START condition 100 kHz mode 4000 — — After this period the first clock ns Hold time 400 kHz mode 600 — — pulse is generated 92 TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — (cid:211) 1997 Microchip Technology Inc. DS30390E-page 235

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-14:I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 20-1 for load conditions TABLE 20-10: I2C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100 kHz mode 4.0 — m s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — m s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101 TLOW Clock low time 100 kHz mode 4.7 — m s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — m s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102 TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 103 TF SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 90 TSU:STA START condition 100 kHz mode 4.7 — m s Only relevant for repeated setup time 400 kHz mode 0.6 — m s START condition 91 THD:STA START condition hold 100 kHz mode 4.0 — m s After this period the first clock time 400 kHz mode 0.6 — m s pulse is generated 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 m s 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92 TSU:STO STOP condition setup 100 kHz mode 4.7 — m s time 400 kHz mode 0.6 — m s 109 TAA Output valid from 100 kHz mode — 3500 ns Note 1 clock 400 kHz mode — — ns 110 TBUF Bus free time 100 kHz mode 4.7 — m s Time the bus must be free 400 kHz mode 1.3 — m s before a new transmission can start Cb Bus capacitive loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT ‡ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. DS30390E-page 236 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-15:USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK 121 pin 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 20-1 for load conditions TABLE 20-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) PIC16C76/77 — — 80 ns Clock high to data out valid PIC16LC76/77 — — 100 ns 121 Tckrf Clock out rise time and fall time PIC16C76/77 — — 45 ns (Master Mode) PIC16LC76/77 — — 50 ns 122 Tdtrf Data out rise time and fall time PIC16C76/77 — — 45 ns PIC16LC76/77 — — 50 ns †: Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 20-16:USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure 20-1 for load conditions TABLE 20-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 125 TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK fl (DT setup time) 15 — — ns 126 TckL2dtl Data hold after CK fl (DT hold time) 15 — — ns †: Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 237

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 20-13: A/D CONVERTER CHARACTERISTICS: PIC16C76/77-04 (Commercial, Industrial, Extended) PIC16C76/77-10 (Commercial, Industrial, Extended) PIC16C76/77-20 (Commercial, Industrial, Extended) PIC16LC76/77-04 (Commercial, Industrial) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 8-bits bit VREF = VDD = 5.12V, VSS £ VAIN £ VREF A02 EABS Total Absolute error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A03 EIL Integral linearity error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A04 EDL Differential linearity error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A05 EFS Full scale error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A06 EOFF Offset error — — < – 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A10 — Monotonicity — guaranteed — — VSS £ VAIN £ VREF A20 VREF Reference voltage 3.0V — VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V A30 ZAIN Recommended impedance of — — 10.0 kW analog voltage source A40 IAD A/D conversion current PIC16C76/77 — 180 — m A Average current consump- (VDD) PIC16LC76/77 — 90 — m A tion when A/D is on. (Note 1) A50 IREF VREF input current (Note 2) 10 — 1000 m A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 13.1. — — 10 m A During A/D Conversion cycle * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. DS30390E-page 238 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-17:A/D CONVERSION TIMING BSF ADCON0, GO 1 Tcy 134 (TOSC/2) (1) 131 Q4 130 A/D CLK 132 A/D DATA 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 20-14: A/D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D clock period PIC16C76/77 1.6 — — m s TOSC based, VREF ‡ 3.0V PIC16LC76/77 2.0 — — m s TOSC based, VREF full range PIC16C76/77 2.0 4.0 6.0 m s A/D RC Mode PIC16LC76/77 3.0 6.0 9.0 m s A/D RC Mode 131 TCNV Conversion time (not including S/H time) — 9.5 — TAD (Note 1) 132 TACQ Acquisition time Note 2 20 — m s 5* — — m s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 135 TSWC Switching from convert fi sample time 1.5 § — — TAD * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 13.1 for min conditions. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 239

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 NOTES: DS30390E-page 240 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 21.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at, 25(cid:176) C, while 'max' or 'min' represents (mean +3s ) and (mean -3s ) respectively where s is standard deviation. FIGURE 21-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE) 35 30 25 20 A) n (D P I 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 21-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE) 10.000 85(cid:176) C 70(cid:176) C 1.000 A) 25(cid:176) C 0.100 m(D P I 0(cid:176) C -40(cid:176) C 0.010 0.001 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) (cid:211) 1997 Microchip Technology Inc. DS30390E-page 241

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-3: TYPICAL IPD vs. VDD @ 25(cid:176) C FIGURE 21-5: TYPICAL RC OSCILLATOR (WDT ENABLED, RC MODE) FREQUENCY vs. VDD Cext = 22 pF, T = 25(cid:176)C 6.0 25 5.5 5.0 20 4.5 R = 5k 4.0 A) 15 MHz) 3.5 mI(PD 10 osc( 3.0 R = 10k F 2.5 2.0 5 1.5 1.0 0 R = 100k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5 VDD(Volts) 0.02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 21-4: MAXIMUM IPD vs. VDD (WDT Shaded area is beyond recommended range. ENABLED, RC MODE) FIGURE 21-6: TYPICAL RC OSCILLATOR 35 FREQUENCY vs. VDD -40(cid:176)C 30 0(cid:176)C 2.4 Cext = 100 pF, T = 25(cid:176)C 25 2.2 R = 3.3k 2.0 A) 20 1.8 m(D 70(cid:176)C 1.6 IP 15 z) R = 5k H 1.4 M 10 85(cid:176)C sc( 1.2 o F 1.0 R = 10k 5 0.8 0.6 s. 0 etail 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 00..42 R = 100k d VDD(Volts) or 0.0 n f 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 o VDD(Volts) cti e s s FIGURE 21-7: TYPICAL RC OSCILLATOR of thi FREQUENCY vs. VDD e g a Cext = 300 pF, T = 25(cid:176)C p st 1000 fir 900 ee 800 R = 3.3k S s. z) 700 mple sc(kH 650000 R = 5k sa Fo 400 x R = 10k atri 300 m 200 n 100 R = 100k o d 0 se 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 a b VDD(Volts) a at D DS30390E-page 242 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-8: TYPICAL IPD vs. VDD BROWN- FIGURE 21-10:TYPICAL IPD vs. TIMER1 OUT DETECT ENABLED (RC ENABLED (32 kHz, RC0/RC1 = MODE) 33 pF/33 pF, RC MODE) 1400 1200 30 1000 25 A) 800 Device NOT in m(D Brown-out Reset 20 IP 600 A) 400 BDreovwicne-o iunt m(PD15 200 Reset I10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5 VDD(Volts) 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 The shaded region represents the built-in hysteresis of the VDD(Volts) brown-out reset circuitry. FIGURE 21-9: MAXIMUM IPD vs. VDD BROWN-OUT DETECT FIGURE 21-11:MAXIMUM IPD vs. TIMER1 ENABLED ENABLED (85(cid:176) C TO -40(cid:176) C, RC MODE) (32 kHz, RC0/RC1 = 33 pF/33 pF, 85(cid:176) C TO -40(cid:176) C, RC MODE) 1600 1400 1200 45 1000 40 A) Device NOT in 35 m(PD 800 Brown-out Reset 30 I 600 Device in Brown-out A)25 400 Reset m(D20 P 200 I15 s. 4.3 10 ail 0 et 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5 d VDD(Volts) or The shaded region represents the built-in hysteresis of the 02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 n f brown-out reset circuitry. VDD(Volts) ctio e s s hi of t e g a p st fir e e S s. e pl m a s x atri m n o d e s a b a at D (cid:211) 1997 Microchip Technology Inc. DS30390E-page 243

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-12:TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25(cid:176) C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V 1400 4.0V A) 1200 3.5V m(D ID 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Frequency(MHz) Shaded area is beyond recommended range FIGURE 21-13:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40(cid:176) C TO 85(cid:176) C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V 1400 4.0V ails. A) 1200 3.5V or det mI(DD 1000 3.0V n f 800 o 2.5V ecti 600 s s hi 400 of t e 200 g a p st 0 fir 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 See Frequency(MHz) Shaded area is s. beyond recommended range e pl m a s x atri m n o d e s a b a at D DS30390E-page 244 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-14:TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25(cid:176) C) 1600 6.0V 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 3.5V A) 3.0V m(D 800 D I 2.5V 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 Shaded area is Frequency(kHz) beyond recommended range FIGURE 21-15:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40(cid:176) C TO 85(cid:176) C) 1600 6.0V 1400 5.5V 5.0V s. 1200 4.5V etail d 1000 4.0V n for o 3.5V cti A) e m(DD 800 3.0V his s I 600 2.5V ge of t a p st 400 fir e e S 200 es. pl m a s 0 x 0 200 400 600 800 1000 1200 1400 1600 1800 atri Shaded area is Frequency(kHz) m beyond recommended range n o d e s a b a at D (cid:211) 1997 Microchip Technology Inc. DS30390E-page 245

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-16:TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25(cid:176) C) 1200 6.0V 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V 3.0V A) 600 m(D 2.5V D I 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) FIGURE 21-17:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40(cid:176) C TO 85(cid:176) C) 1200 6.0V 5.5V 1000 5.0V s. ail 4.5V et d or 800 4.0V n f 3.5V o cti e 3.0V s s A) 600 of thi mI(DD 2.5V e g a 400 p st fir e e S 200 s. e pl m a s 0 x atri 0 100 200 300 400 500 600 700 m Frequency(kHz) n o d e s a b a at D DS30390E-page 246 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-18:TYPICAL IDD vs. CAPACITANCE @ 500 kHz FIGURE 21-19:TRANSCONDUCTANCE(gm) (RC MODE) OF HS OSCILLATOR vs. VDD 600 4.0 Max -40(cid:176)C 5.0V 3.5 500 3.0 4.0V 400 A) 3.0V V) 2.5 Typ 25(cid:176)C m(D 300 mA/ 2.0 ID m( g 1.5 Min 85(cid:176)C 200 1.0 100 0.5 0 0.0 20 pF 100 pF 300 pF 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Capacitance(pF) Shaded area is VDD(Volts) beyond recommended range TABLE 21-1: RC OSCILLATOR FIGURE 21-20:TRANSCONDUCTANCE(gm) FREQUENCIES OF LP OSCILLATOR vs. VDD Average Cext Rext 110 Fosc @ 5V, 25(cid:176) C 100 Max -40(cid:176)C 90 22 pF 5k 4.12 MHz – 1.4% 80 10k 2.35 MHz – 1.4% 70 100k 268 kHz – 1.1% A/V) 60 Typ 25(cid:176)C 100 pF 3.3k 1.80 MHz – 1.0% mm( 50 g 40 5k 1.27 MHz – 1.0% 30 10k 688 kHz – 1.2% 20 Min 85(cid:176)C 100k 77.2 kHz – 1.0% 10 0 300 pF 3.3k 707 kHz – 1.4% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 150kk 520619 kkHHzz –– 11..26%% Sbehyaodnedd raerceoams mareen ded range VDD(Volts) details. 100k 28.3 kHz – 1.1% FIGURE 21-21:TRANSCONDUCTANCE(gm) or OF XT OSCILLATOR vs. VDD n f The percentage variation indicated here is part to o part variation due to normal process distribution. The ecti variation indicated is – 3 standard deviation from 1000 s s average value for VDD = 5V. 980000 Max -40(cid:176)C of thi 700 e g V) 600 Typ 25(cid:176)C a mgm(A/ 543000000 Min 85(cid:176)C ee first p S 200 s. 100 e pl 0 m 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 a s Shaded areas are VDD(Volts) x beyond recommended range atri m n o d e s a b a at D (cid:211) 1997 Microchip Technology Inc. DS30390E-page 247

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-22:TYPICAL XTAL STARTUP FIGURE 21-24:TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25(cid:176) C) TIME vs. VDD (XT MODE, 25(cid:176) C) 3.5 70 3.0 60 2.5 s) 50 d con 2.0 ms) 40 me(Se 1.5 32 kHz, 33 pF/33 pF Time( 30 200 kHz, 68 pF/68 pF up Ti artup 20 200 kHz, 47 pF/47 pF art 1.0 St 1 MHz, 15 pF/15 pF St 10 4 MHz, 15 pF/15 pF 0.5 200 kHz, 15 pF/15 pF 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.0 VDD(Volts) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 21-23:TYPICAL XTAL STARTUP TABLE 21-2: CAPACITOR SELECTION TIME vs. VDD (HS MODE, 25(cid:176) C) FOR CRYSTAL OSCILLATORS 7 Crystal Cap. Range Cap. Range Osc Type Freq C1 C2 6 LP 32 kHz 33 pF 33 pF ms) 5 20 MHz, 33 pF/33 pF 200 kHz 15 pF 15 pF me( XT 200 kHz 47-68 pF 47-68 pF p Ti 4 1 MHz 15 pF 15 pF u 8 MHz, 33 pF/33 pF etails. Start 32 280 MMHHzz,, 1155 ppFF//1155 ppFF HS 484 MMMHHHzzz 1511-553 3pp FFpF 1511-553 3pp FFpF d or 1 20 MHz 15-33 pF 15-33 pF n f 4.0 4.5 5.0 5.5 6.0 o cti VDD(Volts) Crystals e s Used s hi 32 kHz Epson C-001R32.768K-A – 20 PPM of t 200 kHz STD XTL 200.000KHz – 20 PPM e g 1 MHz ECS ECS-10-13-1 – 50 PPM a st p 4 MHz ECS ECS-40-20-1 – 50 PPM fir 8 MHz EPSON CA-301 8.000M-C – 30 PPM e e 20 MHz EPSON CA-301 20.000M-C – 30 PPM S s. e pl m a s x atri m n o d e s a b a at D DS30390E-page 248 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-25:TYPICAL IDD vs. FREQUENCY FIGURE 21-27:TYPICAL IDD vs. FREQUENCY (LP MODE, 25(cid:176) C) (XT MODE, 25(cid:176) C) 1800 1600 6.0V 120 1400 5.5V 100 5.0V 1200 80 4.5V A) 1000 4.0V 60 m(DD 6.0V 800 3.5V I40 55..50VV A) 3.0V 4.5V m(D600 20 43..05VV ID 2.5V 3.0V 400 2.5V 0 0 50 100 150 200 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) FIGURE 21-26:MAXIMUM IDD vs. FIGURE 21-28:MAXIMUM IDD vs. FREQUENCY FREQUENCY (LP MODE, 85(cid:176) C TO -40(cid:176) C) (XT MODE, -40(cid:176) C TO 85(cid:176) C) 1800 6.0V 140 1600 5.5V 120 1400 5.0V 100 1200 4.5V 80 1000 4.0V A) m(D60 6.0V 800 3.5V ID40 554...505VVV m(A)DD600 32..05VV ails. 4.0V I et 200 332...505VVV 420000 n for d o 0 50 100 150 200 cti Frequency(kHz) 0 e 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 s s Frequency(MHz) hi of t e g a p st fir e e S s. e pl m a s x atri m n o d e s a b a at D (cid:211) 1997 Microchip Technology Inc. DS30390E-page 249

PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-29:TYPICAL IDD vs. FREQUENCY FIGURE 21-30:MAXIMUM IDD vs. (HS MODE, 25(cid:176) C) FREQUENCY (HS MODE, -40(cid:176) C TO 85(cid:176) C) 7.0 7.0 6.0 6.0 5.0 5.0 A)4.0 (mDD3.0 mA)4.0 I (DD3.0 2.0 6.0V I 5.5V 5.0V 2.0 6.0V 1.0 4.5V 5.5V 4.0V 5.0V 1.0 4.5V 0.0 4.0V 1 2 4 6 8 10 12 14 16 18 20 0.0 Frequency(MHz) 1 2 4 6 8 10 12 14 16 18 20 Frequency(MHz) s. ail et d or n f o cti e s s hi of t e g a p st fir e e S s. e pl m a s x atri m n o d e s a b a at D DS30390E-page 250 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 22.0 PACKAGING INFORMATION 22.1 28-Lead Ceramic Side Brazed Dual In-Line with Window (300 mil)(JW) N C E1 E eA Pin #1 a eB Indicator Area D S1 S Base Plane Seating A3 A2 Plane L A1 A B1 e1 B D1 Package Group: Ceramic Side Brazed Dual In-Line (CER) Millimeters Inches Symbol Min Max Notes Min Max Notes a 0(cid:176) 10(cid:176) 0(cid:176) 10(cid:176) A 3.937 5.030 0.155 0.198 A1 1.016 1.524 0.040 0.060 A2 2.921 3.506 0.115 0.138 A3 1.930 2.388 0.076 0.094 B 0.406 0.508 0.016 0.020 B1 1.219 1.321 Typical 0.048 0.052 C 0.228 0.305 Typical 0.009 0.012 D 35.204 35.916 1.386 1.414 D1 32.893 33.147 Reference 1.295 1.305 E 7.620 8.128 0.300 0.320 E1 7.366 7.620 0.290 0.300 e1 2.413 2.667 Typical 0.095 0.105 eA 7.366 7.874 Reference 0.290 0.310 eB 7.594 8.179 0.299 0.322 L 3.302 4.064 0.130 0.160 N 28 28 28 28 S 1.143 1.397 0.045 0.055 S1 0.533 0.737 0.021 0.029 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 251

PIC16C7X 22.2 40-Lead Ceramic CERDIP Dual In-line with Window (600 mil) (JW) N E1 E a C Pin No. 1 Indicator eA Area eB D S S1 Base Plane Seating Plane L B1 e1 A1 A3 A A2 B D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Inches Symbol Min Max Notes Min Max Notes a 0(cid:176) 10(cid:176) 0(cid:176) 10(cid:176) A 4.318 5.715 0.170 0.225 A1 0.381 1.778 0.015 0.070 A2 3.810 4.699 0.150 0.185 A3 3.810 4.445 0.150 0.175 B 0.355 0.585 0.014 0.023 B1 1.270 1.651 Typical 0.050 0.065 Typical C 0.203 0.381 Typical 0.008 0.015 Typical D 51.435 52.705 2.025 2.075 D1 48.260 48.260 Reference 1.900 1.900 Reference E 15.240 15.875 0.600 0.625 E1 12.954 15.240 0.510 0.600 e1 2.540 2.540 Reference 0.100 0.100 Reference eA 14.986 16.002 Typical 0.590 0.630 Typical eB 15.240 18.034 0.600 0.710 L 3.175 3.810 0.125 0.150 N 40 40 40 40 S 1.016 2.286 0.040 0.090 S1 0.381 1.778 0.015 0.070 DS30390E-page 252 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 22.3 28-Lead Plastic Dual In-line (300 mil) (SP) N a E1 E C Pin No. 1 eA Indicator eB Area B2 B1 D S Base Plane Seating Plane L Detail A e1 A1 A2 A B3 B D1 Detail A Package Group: Plastic Dual In-Line (PLA) Millimeters Inches Symbol Min Max Notes Min Max Notes a 0(cid:176) 10(cid:176) 0(cid:176) 10(cid:176) A 3.632 4.572 0.143 0.180 A1 0.381 – 0.015 – A2 3.175 3.556 0.125 0.140 B 0.406 0.559 0.016 0.022 B1 1.016 1.651 Typical 0.040 0.065 Typical B2 0.762 1.016 4 places 0.030 0.040 4 places B3 0.203 0.508 4 places 0.008 0.020 4 places C 0.203 0.331 Typical 0.008 0.013 Typical D 34.163 35.179 1.385 1.395 D1 33.020 33.020 Reference 1.300 1.300 Reference E 7.874 8.382 0.310 0.330 E1 7.112 7.493 0.280 0.295 e1 2.540 2.540 Typical 0.100 0.100 Typical eA 7.874 7.874 Reference 0.310 0.310 Reference eB 8.128 9.652 0.320 0.380 L 3.175 3.683 0.125 0.145 N 28 - 28 - S 0.584 1.220 0.023 0.048 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 253

PIC16C7X 22.4 40-Lead Plastic Dual In-line (600 mil) (P) N a E1 E C Pin No. 1 eA Indicator eB Area D S S1 Base Plane Seating Plane L B1 e1 A1 A2 A B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Inches Symbol Min Max Notes Min Max Notes a 0(cid:176) 10(cid:176) 0(cid:176) 10(cid:176) A – 5.080 – 0.200 A1 0.381 – 0.015 – A2 3.175 4.064 0.125 0.160 B 0.355 0.559 0.014 0.022 B1 1.270 1.778 Typical 0.050 0.070 Typical C 0.203 0.381 Typical 0.008 0.015 Typical D 51.181 52.197 2.015 2.055 D1 48.260 48.260 Reference 1.900 1.900 Reference E 15.240 15.875 0.600 0.625 E1 13.462 13.970 0.530 0.550 e1 2.489 2.591 Typical 0.098 0.102 Typical eA 15.240 15.240 Reference 0.600 0.600 Reference eB 15.240 17.272 0.600 0.680 L 2.921 3.683 0.115 0.145 N 40 40 40 40 S 1.270 – 0.050 – S1 0.508 – 0.020 – DS30390E-page 254 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 22.5 28-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO) e B h x 45(cid:176) N Index Area E H a C Chamfer L h x 45(cid:176) 1 2 3 D Base CP Seating Plane Plane A1 A Package Group: Plastic SOIC (SO) Millimeters Inches Symbol Min Max Notes Min Max Notes a 0(cid:176) 8(cid:176) 0(cid:176) 8(cid:176) A 2.362 2.642 0.093 0.104 A1 0.101 0.300 0.004 0.012 B 0.355 0.483 0.014 0.019 C 0.241 0.318 0.009 0.013 D 17.703 18.085 0.697 0.712 E 7.416 7.595 0.292 0.299 e 1.270 1.270 Typical 0.050 0.050 Typical H 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 L 0.406 1.143 0.016 0.045 N 28 28 28 28 CP – 0.102 – 0.004 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 255

PIC16C7X 22.6 28-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS) N Index area E H a C L 1 2 3 e B A Base plane CP Seating plane D A1 Package Group: Plastic SSOP Millimeters Inches Symbol Min Max Notes Min Max Notes a 0(cid:176) 8(cid:176) 0(cid:176) 8(cid:176) A 1.730 1.990 0.068 0.078 A1 0.050 0.210 0.002 0.008 B 0.250 0.380 0.010 0.015 C 0.130 0.220 0.005 0.009 D 10.070 10.330 0.396 0.407 E 5.200 5.380 0.205 0.212 e 0.650 0.650 Reference 0.026 0.026 Reference H 7.650 7.900 0.301 0.311 L 0.550 0.950 0.022 0.037 N 28 28 28 28 CP - 0.102 - 0.004 DS30390E-page 256 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 22.7 44-Lead Plastic Leaded Chip Carrier (Square)(PLCC) D 0.812/0.661 N Pics 0.177 1.27 .032/.026 .007 S B D-E S .050 0.177 -A- 2 Sides -H- .007 S B A S D1 A A1 2 Sides -D- 3 DD32/E3 D 0..010041 SPelaanteing 9 0.38 3 .015 F-G S 4 -C- 3 -F- 8 -G- E2 E1 E 0.38 F-G S .015 4 -B- 3 -E- 0.177 .007 S A F-G S 10 0.812/0.661 0.254 0.254 .032/.026 3 .010 Max 11 .010 Max 11 1.524 2 -H- 0..052008 0..052008 -H- 2 .060 Min 6 6 -C- 5 1.651 1.651 0.64 Min 0.533/0.331 .065 .065 .025 .021/.013 R 1.14/0.64 R 1.14/0.64 .045/.025 .045/.025 0.0.10777M A F-G S,D-E S Package Group: Plastic Leaded Chip Carrier (PLCC) Millimeters Inches Symbol Min Max Notes Min Max Notes A 4.191 4.572 0.165 0.180 A1 2.413 2.921 0.095 0.115 D 17.399 17.653 0.685 0.695 D1 16.510 16.663 0.650 0.656 D2 15.494 16.002 0.610 0.630 D3 12.700 12.700 Reference 0.500 0.500 Reference E 17.399 17.653 0.685 0.695 E1 16.510 16.663 0.650 0.656 E2 15.494 16.002 0.610 0.630 E3 12.700 12.700 Reference 0.500 0.500 Reference N 44 44 44 44 CP – 0.102 – 0.004 LT 0.203 0.381 0.008 0.015 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 257

PIC16C7X 22.8 44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form) (PQ) 0.20 M CA-B S D S 4 D 0.20 M HA-B S D S D1 5 7 0.05 mm/mm A-B 0.20 min. D3 0.13 R min. Index area 6 PARTING LINE 0.13/0.30 R b a 9 L C E3 E1 E 1.60 Ref. 0.20 M CA-B S D S 4 TYP 4x 10 0.20 M HA-B S D S e B 5 7 0.05 mm/mm D A2 A Base Plane Seating Plane A1 Package Group: Plastic MQFP Millimeters Inches Symbol Min Max Notes Min Max Notes a 0(cid:176) 7(cid:176) 0(cid:176) 7(cid:176) A 2.000 2.350 0.078 0.093 A1 0.050 0.250 0.002 0.010 A2 1.950 2.100 0.768 0.083 b 0.300 0.450 Typical 0.011 0.018 Typical C 0.150 0.180 0.006 0.007 D 12.950 13.450 0.510 0.530 D1 9.900 10.100 0.390 0.398 D3 8.000 8.000 Reference 0.315 0.315 Reference E 12.950 13.450 0.510 0.530 E1 9.900 10.100 0.390 0.398 E3 8.000 8.000 Reference 0.315 0.315 Reference e 0.800 0.800 0.031 0.032 L 0.730 1.030 0.028 0.041 N 44 44 44 44 CP 0.102 – 0.004 – DS30390E-page 258 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X 22.9 44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form) (TQ) D D1 1.0ø (0.039ø) Ref. 11(cid:176) /13(cid:176) (4x) Pin#1 Pin#1 2 2 0(cid:176) Min E E1 Q 11(cid:176) /13(cid:176) (4x) Detail B e 3.0ø (0.118ø) Ref. R1 0.08 Min Option 1 (TOP side) R 0.08/0.20 Option 2 (TOP side) Gage Plane A1 0.250 Base Metal Lead Finish A2 A b S L 0.20 Detail A L c c1 L1 Min Detail B 1.00 Ref 1.00 Ref. b1 Detail B Detail A Package Group: Plastic TQFP Millimeters Inches Symbol Min Max Notes Min Max Notes A 1.00 1.20 0.039 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 D 11.75 12.25 0.463 0.482 D1 9.90 10.10 0.390 0.398 E 11.75 12.25 0.463 0.482 E1 9.90 10.10 0.390 0.398 L 0.45 0.75 0.018 0.030 e 0.80 BSC 0.031 BSC b 0.30 0.45 0.012 0.018 b1 0.30 0.40 0.012 0.016 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 N 44 44 44 44 Q 0(cid:176) 7(cid:176) 0(cid:176) 7(cid:176) Note1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010”) per side. D1 and E1 dimensions including mold mismatch. 2: Dimension “b” does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m (0.003”)max. 3: This outline conforms to JEDEC MS-026. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 259

PIC16C7X 22.10 Package Marking Information 28-Lead SSOP Example XXXXXXXXXXXX PIC16C72 XXXXXXXXXXXX 20I/SS025 AABBCAE 9517SBP 28-Lead PDIP (Skinny DIP) Example MMMMMMMMMMMM PIC16C73-10/SP XXXXXXXXXXXXXXX AABBCDE AABBCDE 28-Lead Side Brazed Skinny Windowed Example XXXXXXXXXXX PIC16C73/JW XXXXXXXXXXX AABBCDE 9517CAT 28-Lead SOIC Example MMMMMMMMMMMMMMMM PIC16C73-10/SO XXXXXXXXXXXXXXXXXXXX AABBCDE 945/CAA Legend: MM...M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calender year) BB Week code (week of January 1 is week '01’) C Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. D1 Mask revision number for microcontroller E Assembly code of the plant or country of origin in which part was assembled. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS30390E-page 260 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Package Marking Information (Cont’d) 40-Lead PDIP Example MMMMMMMMMMMMMM PIC16C74-04/P XXXXXXXXXXXXXXXXXX AABBCDE 9512CAA 40-Lead CERDIP Windowed Example MMMMMMMMM PIC16C74/JW XXXXXXXXXXX XXXXXXXXXXX AABBCDE AABBCDE 44-Lead PLCC Example MMMMMMMM PIC16C74 XXXXXXXXXX -10/L XXXXXXXXXX AABBCDE AABBCDE 44-Lead MQFP Example MMMMMMMM PIC16C74 XXXXXXXXXX -10/PQ XXXXXXXXXX AABBCDE AABBCDE Legend: MM...M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calender year) BB Week code (week of January 1 is week '01’) C Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. D1 Mask revision number for microcontroller E Assembly code of the plant or country of origin in which part was assembled. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 261

PIC16C7X Package Marking Information (Cont’d) 44-Lead TQFP Example MMMMMMMM PIC16C74A XXXXXXXXXX -10/TQ XXXXXXXXXX AABBCDE AABBCDE Legend: MM...M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calender year) BB Week code (week of January 1 is week '01’) C Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. D1 Mask revision number for microcontroller E Assembly code of the plant or country of origin in which part was assembled. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS30390E-page 262 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X APPENDIX A: APPENDIX B: COMPATIBILITY The following are the list of modifications over the To convert code written for PIC16C5X to PIC16CXX, PIC16C5X microcontroller family: the user should take the following steps: 1. Instruction word length is increased to 14-bits. 1. Remove any program memory page select This allows larger page sizes both in program operations (PA2, PA1, PA0 bits) for CALL, GOTO. memory (2K now as opposed to 512 before) and 2. Revisit any computed jump operations (write to register file (128 bytes now versus 32 bytes PC or add to PC, etc.) to make sure page bits before). are set properly under the new scheme. 2. A PC high latch register (PCLATH) is added to 3. Eliminate any data memory page switching. handle program memory paging. Bits PA2, PA1, Redefine data variables to reallocate them. PA0 are removed from STATUS register. 4. Verify all writes to STATUS, OPTION, and FSR 3. Data memory paging is redefined slightly. registers since these have changed. STATUS register is modified. 5. Change reset vector to 0000h. 4. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compati- bility with PIC16C5X. 5. OPTION and TRIS registers are made address- able. 6. Interrupt capability is added. Interrupt vector is at 0004h. 7. Stack size is increased to 8 deep. 8. Reset vector is changed to 0000h. 9. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Reg- isters are reset differently. 10. Wake up from SLEEP through interrupt is added. 11. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These tim- ers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. PORTB has weak pull-ups and interrupt on change feature. 13. T0CKI pin is also a port pin (RA4) now. 14. FSR is made a full eight bit register. 15. “In-circuit serial programming” is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, MCLR/VPP, RB6 (clock) and RB7 (data in/out). 16. PCON status register is added with a Power-on Reset status bit (POR). 17. Code protection scheme is enhanced such that portions of the program memory can be pro- tected, while the remainder is unprotected. 18. Brown-out protection circuitry has been added. Controlled by configuration word bit BODEN. Brown-out reset ensures the device is placed in a reset condition if VDD dips below a fixed set- point. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 263

PIC16C7X APPENDIX C: WHAT’S NEW APPENDIX D: WHAT’S CHANGED Added the following devices: Minor changes, spelling and grammatical changes. • PIC16C76 Added the following note to the USART section. This • PIC16C77 note applies to all devices except the PIC16C76 and PIC16C77. Removed the PIC16C710, PIC16C71, PIC16C711 from this datasheet. For the PIC16C73/73A/74/74A the asynchronous high speed mode (BRGH = 1) may experience a high rate of Added PIC16C76 and PIC16C77 devices. The receive errors. It is recommended that BRGH = 0. If you PIC16C76/77 devices have 368 bytes of data memory desire a higher baud rate than BRGH = 0 can support, distributed in 4 banks and 8K of program memory in 4 refer to the device errata for additional information or pages. These two devices have an enhanced SPI that use the PIC16C76/77. supports both clock phase and polarity. The USART has been enhanced. When upgrading to the PIC16C76/77 please note that Divided SPI section into SPI for the PIC16C76/77 and the upper 16 bytes of data memory in banks 1,2, and 3 SPI for all other devices. are mapped into bank 0. This may require relocation of data memory usage in the user application code. Added Q-cycle definitions to the Instruction Set Sum- mary section. DS30390E-page 264 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X APPENDIX E: PIC16/17 MICROCONTROLLERS E.1 PIC12CXXX Family of Devices PIC12C508 PIC12C509 PIC12C671 PIC12C672 Maximum Frequency 4 4 4 4 Clock of Operation (MHz) EPROM Program Memory 512 x 12 1024 x 12 1024 x 14 2048 x 14 Memory Data Memory (bytes) 25 41 128 128 Timer Module(s) TMR0 TMR0 TMR0 TMR0 Peripherals A/D Converter (8-bit) Channels — — 4 4 Wake-up from SLEEP on Yes Yes Yes Yes pin change I/O Pins 5 5 5 5 Input Pins 1 1 1 1 Features Internal Pull-ups Yes Yes Yes Yes Voltage Range (Volts) 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 In-Circuit Serial Programming Yes Yes Yes Yes Number of Instructions 33 33 35 35 Packages 8-pin DIP, SOIC 8-pin DIP, SOIC 8-pin DIP, SOIC 8-pin DIP, SOIC All PIC12C5XX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12C5XX devices use serial programming with data pin GP1 and clock pin GP0. E.2 PIC14C000 Family of Devices PIC14C000 Clock Maximum Frequency of Operation (MHz) 20 EPROM Program Memory (x14 words) 4K Data Memory (bytes) 192 Memory Timer Module(s) TMR0 ADTMR Serial Port(s) I2C with SMBus Peripherals (SPI/I2C, USART) Support Slope A/D Converter Channels 8 External; 6 Internal Interrupt Sources 11 I/O Pins 22 Voltage Range (Volts) 2.7-6.0 Features In-Circuit Serial Programming Yes Additional On-chip Features Internal 4MHz Oscillator, Bandgap Reference,Temperature Sensor, Calibration Factors, Low Voltage Detector, SLEEP, HIBERNATE, Comparators with Programmable References (2) Packages 28-pin DIP (.300 mil), SOIC, SSOP (cid:211) 1997 Microchip Technology Inc. DS30390E-page 265

PIC16C7X E.3 PIC16C15X Family of Devices PIC16C154 PIC16CR154 PIC16C156 PIC16CR156 PIC16C158 PIC16CR158 Maximum Frequency 20 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 512 — 1K — 2K — (x12 words) Memory ROM Program Memory — 512 — 1K — 2K (x12 words) RAM Data Memory (bytes) 25 25 25 25 73 73 Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 I/O Pins 12 12 12 12 12 12 Voltage Range (Volts) 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 Number of Instructions 33 33 33 33 33 33 Features Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC; SOIC; SOIC; SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. E.4 PIC16C5X Family of Devices PIC16C52 PIC16C54 PIC16C54A PIC16CR54A PIC16C55 PIC16C56 Maximum Frequency 4 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 384 512 512 — 512 1K (x12 words) Memory ROM Program Memory — — — 512 — — (x12 words) RAM Data Memory (bytes) 25 25 25 25 24 25 Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 I/O Pins 12 12 12 12 20 12 Voltage Range (Volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.0-6.25 2.5-6.25 2.5-6.25 Number of Instructions 33 33 33 33 33 33 Features Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin DIP, 18-pin DIP, SOIC SOIC; SOIC; SOIC; SOIC, SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP SSOP 20-pin SSOP PIC16C57 PIC16CR57B PIC16C58A PIC16CR58A Maximum Frequency 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 2K — 2K — (x12 words) Memory ROM Program Memory — 2K — 2K (x12 words) RAM Data Memory (bytes) 72 72 73 73 Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 I/O Pins 20 20 12 12 Voltage Range (Volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.5-6.25 Number of Instructions 33 33 33 33 Features Packages 28-pin DIP, 28-pin DIP, SOIC, 18-pin DIP, SOIC; 18-pin DIP, SOIC; SOIC, SSOP 20-pin SSOP 20-pin SSOP SSOP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code protect and high I/O current capability. DS30390E-page 266 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X E.5 PIC16C55X Family of Devices PIC16C554 PIC16C556(1) PIC16C558 Clock Maximum Frequency of Operation (MHz) 20 20 20 EPROM Program Memory (x14 words) 512 1K 2K Memory Data Memory (bytes) 80 80 128 Timer Module(s) TMR0 TMR0 TMR0 Peripherals Comparators(s) — — — Internal Reference Voltage — — — Interrupt Sources 3 3 3 I/O Pins 13 13 13 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 Features Brown-out Reset — — — Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C5XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales office for availability of these devices. E.6 PIC16C62X and PIC16C64X Family of Devices PIC16C620 PIC16C621 PIC16C622 PIC16C642 PIC16C662 Maximum Frequency 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 512 1K 2K 4K 4K Memory (x14 words) Data Memory (bytes) 80 80 128 176 176 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 Peripherals Comparators(s) 2 2 2 2 2 Internal Reference Voltage Yes Yes Yes Yes Yes Interrupt Sources 4 4 4 4 5 I/O Pins 13 13 13 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 3.0-6.0 3.0-6.0 Brown-out Reset Yes Yes Yes Yes Yes Features Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin PDIP, 40-pin PDIP, SOIC; SOIC; SOIC; SOIC, Windowed 20-pin SSOP 20-pin SSOP 20-pin SSOP Windowed CDIP; CDIP 44-pin PLCC, MQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C62X and PIC16C64X Family devices use serial programming with clock pin RB6 and data pin RB7. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 267

PIC16C7X E.7 PIC16C6X Family of Devices PIC16C61 PIC16C62A PIC16CR62 PIC16C63 PIC16CR63 Maximum Frequency 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 1K 2K — 4K — (x14 words) Memory ROM Program Memory — — 2K — 4K (x14 words) Data Memory (bytes) 36 128 128 192 192 Timer Module(s) TMR0 TMR0, TMR0, TMR0, TMR0, TMR1, TMR1, TMR1, TMR1, TMR2 TMR2 TMR2 TMR2 Capture/Compare/ — 1 1 2 2 Peripherals PWM Module(s) Serial Port(s) — SPI/I2C SPI/I2C SPI/I2C, SPI/I2C (SPI/I2C, USART) USART USART Parallel Slave Port — — — — — Interrupt Sources 3 7 7 10 10 I/O Pins 13 22 22 22 22 Voltage Range (Volts) 3.0-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 Features In-Circuit Serial Programming Yes Yes Yes Yes Yes Brown-out Reset — Yes Yes Yes Yes Packages 18-pin DIP, SO28-pin SDIP, 28-pin SDIP, 28-pin SDIP, 28-pin SDIP, SOIC, SSOP SOIC, SSOP SOIC SOIC PIC16C64A PIC16CR64 PIC16C65A PIC16CR65 PIC16C66 PIC16C67 Maximum Frequency 20 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 2K — 4K — 8K 8K (x14 words) Memory ROM Program Memory (x14 — 2K — 4K — — words) Data Memory (bytes) 128 128 192 192 368 368 Timer Module(s) TMR0, TMR0, TMR0, TMR0, TMR0, TMR0, TMR1, TMR1, TMR1, TMR1, TMR1, TMR1, TMR2 TMR2 TMR2 TMR2 TMR2 TMR2 Capture/Compare/PWM Mod- 1 1 2 2 2 2 Peripherals ule(s) Serial Port(s) (SPI/I2C, USART) SPI/I2C SPI/I2C SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C, USART USART USART USART Parallel Slave Port Yes Yes Yes Yes — Yes Interrupt Sources 8 8 11 11 10 11 I/O Pins 33 33 33 33 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Features Brown-out Reset Yes Yes Yes Yes Yes Yes Packages 40-pin DIP; 40-pin DIP; 40-pin DIP; 40-pin DIP; 28-pin SDIP, 40-pin DIP; 44-pin PLCC,44-pin PLCC, 44-pin PLCC, 44-pin SOIC 44-pin MQFP, TQFPMQFP, TQFP MQFP, TQFP PLCC, PLCC, MQFP, MQFP, TQFP TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C6X Family devices use serial programming with clock pin RB6 and data pin RB7. DS30390E-page 268 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X E.8 PIC16C8X Family of Devices PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 Maximum Frequency 10 10 10 10 Clock of Operation (MHz) Flash Program Memory 512 — 1K — EEPROM Program Memory — — — — Memory ROM Program Memory — 512 — 1K Data Memory (bytes) 36 36 68 68 Data EEPROM (bytes) 64 64 64 64 Peripher- Timer Module(s) TMR0 TMR0 TMR0 TMR0 als Interrupt Sources 4 4 4 4 I/O Pins 13 13 13 13 Features Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0 Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC SOIC SOIC SOIC All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capabil- ity. All PIC16C8X Family devices use serial programming with clock pin RB6 and data pin RB7. E.9 PIC16C9XX Family Of Devices PIC16C923 PIC16C924 Clock Maximum Frequency of Operation (MHz) 8 8 EPROM Program Memory 4K 4K Memory Data Memory (bytes) 176 176 Timer Module(s) TMR0, TMR0, TMR1, TMR1, TMR2 TMR2 Capture/Compare/PWM Module(s) 1 1 Serial Port(s) SPI/I2C SPI/I2C Peripherals (SPI/I2C, USART) Parallel Slave Port — — A/D Converter (8-bit) Channels — 5 LCD Module 4 Com, 4 Com, 32 Seg 32 Seg Interrupt Sources 8 9 I/O Pins 25 25 Input Pins 27 27 Voltage Range (Volts) 3.0-6.0 3.0-6.0 Features In-Circuit Serial Programming Yes Yes Brown-out Reset — — Packages 64-pin SDIP(1), 64-pin SDIP(1), TQFP; TQFP; 68-pin PLCC, 68-pin PLCC, Die Die All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capa- bility. All PIC16C9XX Family devices use serial programming with clock pin RB6 and data pin RB7. (cid:211) 1997 Microchip Technology Inc. DS30390E-page 269

PIC16C7X E.10 PIC17CXXX Family of Devices PIC17C42A PIC17CR42 PIC17C43 PIC17CR43 PIC17C44 Maximum Frequency 33 33 33 33 33 Clock of Operation (MHz) EPROM Program Memory 2K — 4K — 8K (words) Memory ROM Program Memory — 2K — 4K — (words) RAM Data Memory (bytes) 232 232 454 454 454 Timer Module(s) TMR0, TMR0, TMR0, TMR0, TMR0, TMR1, TMR1, TMR1, TMR1, TMR1, TMR2, TMR2, TMR2, TMR2, TMR2, Peripherals TMR3 TMR3 TMR3 TMR3 TMR3 Captures/PWM Module(s) 2 2 2 2 2 Serial Port(s) (USART) Yes Yes Yes Yes Yes Hardware Multiply Yes Yes Yes Yes Yes External Interrupts Yes Yes Yes Yes Yes Interrupt Sources 11 11 11 11 11 I/O Pins 33 33 33 33 33 Features Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 Number of Instructions 58 58 58 58 58 Packages 40-pin DIP; 40-pin DIP; 40-pin DIP; 40-pin DIP; 40-pin DIP; 44-pin PLCC, 44-pin PLCC, 44-pin PLCC, 44-pin PLCC, 44-pin PLCC, MQFP, TQFP MQFP, TQFP MQFP, TQFP MQFP, TQFP MQFP, TQFP PIC17C752 PIC17C756 Maximum Frequency 33 33 Clock of Operation (MHz) EPROM Program Memory 8K 16K (words) Memory ROM Program Memory — — (words) RAM Data Memory (bytes) 454 902 Timer Module(s) TMR0, TMR0, TMR1, TMR1, TMR2, TMR2, Peripherals TMR3 TMR3 Captures/PWM Module(s) 4/3 4/3 Serial Port(s) (USART) 2 2 Hardware Multiply Yes Yes External Interrupts Yes Yes Interrupt Sources 18 18 I/O Pins 50 50 Features Voltage Range (Volts) 3.0-6.0 3.0-6.0 Number of Instructions 58 58 Packages 64-pin DIP; 64-pin DIP; 68-pin LCC, 68-pin LCC, 68-pin TQFP 68-pin TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. DS30390E-page 270 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X PIN COMPATIBILITY Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modification to allow proper operation in the application socket (ex., PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55. Pin compatibility does not mean that the devices offer the same features. As an example, the PIC16C54 is pin compatible with the PIC16C71, but does not have an A/D converter, weak pull-ups on PORTB, or interrupts. TABLE E-1: PIN COMPATIBLE DEVICES Pin Compatible Devices Package PIC12C508, PIC12C509, PIC12C671, PIC12C672 8-pin PIC16C154, PIC16CR154, PIC16C156, 18-pin, PIC16CR156, PIC16C158, PIC16CR158, 20-pin PIC16C52, PIC16C54, PIC16C54A, PIC16CR54A, PIC16C56, PIC16C58A, PIC16CR58A, PIC16C61, PIC16C554, PIC16C556, PIC16C558 PIC16C620, PIC16C621, PIC16C622 PIC16C641, PIC16C642, PIC16C661, PIC16C662 PIC16C710, PIC16C71, PIC16C711, PIC16C715 PIC16F83, PIC16CR83, PIC16F84A, PIC16CR84 PIC16C55, PIC16C57, PIC16CR57B 28-pin PIC16CR62, PIC16C62A, PIC16C63, PIC16CR63, 28-pin PIC16C66, PIC16C72, PIC16C73A, PIC16C76 PIC16CR64, PIC16C64A, PIC16C65A, 40-pin PIC16CR65, PIC16C67, PIC16C74A, PIC16C77 PIC17CR42, PIC17C42A, 40-pin PIC17C43, PIC17CR43, PIC17C44 PIC16C923, PIC16C924 64/68-pin PIC17C756, PIC17C752 64/68-pin (cid:211) 1997 Microchip Technology Inc. DS30390E-page 271

PIC16C7X NOTES: DS30390E-page 272 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X INDEX Compare .....................................................................73 I2C Mode ....................................................................93 A On-Chip Reset Circuit ...............................................133 PIC16C72 ...................................................................10 A/D PIC16C73 ...................................................................11 Accuracy/Error .........................................................124 PIC16C73A .................................................................11 ADCON0 Register ....................................................117 PIC16C74 ...................................................................12 ADCON1 Register ....................................................118 PIC16C74A .................................................................12 ADIF bit ....................................................................119 PIC16C76 ...................................................................11 Analog Input Model Block Diagram ..........................120 PIC16C77 ...................................................................12 Analog-to-Digital Converter ......................................117 PORTC .......................................................................48 Block Diagram ..........................................................119 PORTD (In I/O Port Mode) .........................................50 Configuring Analog Port Pins ...................................121 PORTD and PORTE as a Parallel Slave Port ............54 Configuring the Interrupt ..........................................119 PORTE (In I/O Port Mode) .........................................51 Configuring the Module ............................................119 PWM ...........................................................................74 Connection Considerations ......................................125 RA3:RA0 and RA5 Port Pins ......................................43 Conversion Clock .....................................................121 RA4/T0CKI Pin ...........................................................43 Conversion Time ......................................................123 RB3:RB0 Port Pins .....................................................45 Conversions .............................................................122 RB7:RB4 Port Pins .....................................................46 Converter Characteristics ................181, 199, 217, 238 SPI Master/Slave Connection .....................................81 Delays ......................................................................120 SSP in I2C Mode ........................................................93 Effects of a Reset .....................................................124 SSP in SPI Mode ..................................................80, 85 Equations .................................................................120 Timer0 ........................................................................59 Faster Conversion - Lower Resolution Tradeoff ......123 Timer0/WDT Prescaler ...............................................62 Flowchart of A/D Operation ......................................126 Timer1 ........................................................................66 GO/DONE bit ...........................................................119 Timer2 ........................................................................69 Internal Sampling Switch (Rss) Impedance .............120 USART Receive .......................................................108 Operation During Sleep ...........................................124 USART Transmit ......................................................106 Sampling Requirements ...........................................120 Watchdog Timer .......................................................144 Sampling Time .........................................................120 BOR bit .......................................................................39, 135 Source Impedance ...................................................120 BRGH bit ..........................................................................101 Time Delays .............................................................120 Buffer Full Status bit, BF ...............................................78, 83 Transfer Function .....................................................125 Using the CCP Trigger .............................................125 C Absolute Maximum Ratings .....................167, 183, 201, 219 C bit ....................................................................................30 ACK ........................................................................90, 94, 95 C Compiler ........................................................................165 ADIE bit ..............................................................................33 Capture/Compare/PWM ADIF bit ..............................................................................35 Capture ADRES Register ....................................23, 25, 27, 117, 119 Block Diagram ....................................................72 ALU ......................................................................................9 CCP1CON Register ...........................................72 Application Notes CCP1IF ...............................................................72 AN546 (Using the Analog-to-Digital Converter) .......117 CCPR1 ...............................................................72 AN552 (Implementing Wake-up on Key Strokes Using CCPR1H:CCPR1L .............................................72 PIC16CXXX) ..............................................................45 Mode ..................................................................72 AN556 (Table Reading Using PIC16CXX ..................40 Prescaler ............................................................73 AN578 (Use of the SSP Module in the I2C Multi-Master CCP Timer Resources ................................................71 Environment) ..............................................................77 Compare AN594 (Using the CCP Modules) ..............................71 Block Diagram ....................................................73 AN607, Power-up Trouble Shooting ........................134 Mode ..................................................................73 Architecture Software Interrupt Mode .....................................73 Harvard ........................................................................9 Special Event Trigger .........................................73 Overview ......................................................................9 Special Trigger Output of CCP1 .........................73 von Neumann ...............................................................9 Special Trigger Output of CCP2 .........................73 Assembler Interaction of Two CCP Modules ................................71 MPASM Assembler ..................................................164 Section ........................................................................71 B Special Event Trigger and A/D Conversions ..............73 Capture/Compare/PWM (CCP) Baud Rate Error ...............................................................101 PWM Block Diagram ..................................................74 Baud Rate Formula ..........................................................101 PWM Mode .................................................................74 Baud Rates PWM, Example Frequencies/Resolutions ..................75 Asynchronous Mode ................................................102 Carry bit ................................................................................9 Synchronous Mode ..................................................102 CCP1CON ..........................................................................29 BF ..........................................................................78, 83, 94 CCP1IE bit ..........................................................................33 Block Diagrams CCP1IF bit ....................................................................35, 36 A/D ...........................................................................119 CCP2CON ..........................................................................29 Analog Input Model ..................................................120 CCP2IE bit ..........................................................................37 Capture ......................................................................72 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 273

PIC16C7X CCP2IF bit ..........................................................................38 F CCPR1H Register ............................................25, 27, 29, 71 Family of Devices CCPR1L Register .........................................................29, 71 PIC12CXXX .............................................................265 CCPR2H Register ............................................25, 27, 29, 71 PIC14C000 ..............................................................265 CCPR2L Register .............................................25, 27, 29, 71 PIC16C15X ..............................................................266 CCPxM0 bit ........................................................................72 PIC16C55X ..............................................................267 CCPxM1 bit ........................................................................72 PIC16C5X ................................................................266 CCPxM2 bit ........................................................................72 PIC16C62X and PIC16C64X ...................................267 CCPxM3 bit ........................................................................72 PIC16C6X ................................................................268 CCPxX bit ...........................................................................72 PIC16C7XX .................................................................6 CCPxY bit ...........................................................................72 PIC16C8X ................................................................269 CKE ....................................................................................83 PIC16C9XX .............................................................269 CKP ..............................................................................79, 84 PIC17CXX ...............................................................270 Clock Polarity Select bit, CKP ......................................79, 84 FERR bit ..........................................................................100 Clock Polarity, SPI Mode ...................................................81 FSR Register ...........................23, 24, 25, 26, 27, 28, 29, 41 Clocking Scheme ...............................................................17 Fuzzy Logic Dev. System (fuzzyTECH(cid:210) -MP) .........163, 165 Code Examples Call of a Subroutine in Page 1 from Page 0 ...............41 G Changing Between Capture Prescalers .....................73 General Description .............................................................5 Changing Prescaler (Timer0 to WDT) ........................63 GIE bit ..............................................................................141 Changing Prescaler (WDT to Timer0) ........................63 I/O Programming ........................................................53 I Indirect Addressing ....................................................41 I/O Ports Initializing PORTA ......................................................43 PORTA ......................................................................43 Initializing PORTB ......................................................45 PORTB ......................................................................45 Initializing PORTC ......................................................48 PORTC ......................................................................48 Loading the SSPBUF Register ............................80, 85 PORTD ................................................................50, 54 Code Protection .......................................................129, 146 PORTE ......................................................................51 Computed GOTO ...............................................................40 Section .......................................................................43 Configuration Bits .............................................................129 I/O Programming Considerations ......................................53 Configuration Word ..........................................................129 I2C Connecting Two Microcontrollers .......................................81 Addressing .................................................................94 CREN bit ..........................................................................100 Addressing I2C Devices .............................................90 CS pin ................................................................................54 Arbitration ..................................................................92 D Block Diagram ...........................................................93 Clock Synchronization ...............................................92 D/A ...............................................................................78, 83 Combined Format ......................................................91 Data/Address bit, D/A ...................................................78, 83 I2C Operation .............................................................93 DC bit .................................................................................30 I2C Overview .............................................................89 DC Characteristics Initiating and Terminating Data Transfer ...................89 PIC16C72 ................................................................168 Master Mode ..............................................................97 PIC16C73 ................................................................184 Master-Receiver Sequence .......................................91 PIC16C73A ..............................................................202 Master-Transmitter Sequence ...................................91 PIC16C74 ................................................................184 Mode ..........................................................................93 PIC16C74A ..............................................................202 Mode Selection ..........................................................93 PIC16C76 ................................................................221 Multi-master ...............................................................92 PIC16C77 ................................................................221 Multi-Master Mode .....................................................97 Development Support ..................................................5, 163 Reception ..................................................................95 Development Tools ..........................................................163 Reception Timing Diagram ........................................95 Digit Carry bit .......................................................................9 SCL and SDA pins .....................................................94 Direct Addressing ...............................................................41 Slave Mode ................................................................94 E START .......................................................................89 STOP ...................................................................89, 90 Electrical Characteristics Transfer Acknowledge ...............................................90 PIC16C72 ................................................................167 Transmission .............................................................96 PIC16C73 ................................................................183 IDLE_MODE ......................................................................98 PIC16C73A ..............................................................201 In-Circuit Serial Programming ..................................129, 146 PIC16C74 ................................................................183 INDF ..................................................................................29 PIC16C74A ..............................................................201 INDF Register ......................................24, 25, 26, 27, 28, 41 PIC16C76 ................................................................219 Indirect Addressing ............................................................41 PIC16C77 ................................................................219 Initialization Condition for all Register ..............................136 External Brown-out Protection Circuit ..............................140 Instruction Cycle ................................................................17 External Power-on Reset Circuit ......................................140 Instruction Flow/Pipelining .................................................17 Instruction Format ............................................................147 DS30390E-page 274 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Instruction Set M ADDLW ....................................................................149 MCLR .......................................................................133, 136 ADDWF ....................................................................149 Memory ANDLW ....................................................................149 Data Memory ..............................................................20 ANDWF ....................................................................149 Program Memory ........................................................19 BCF ..........................................................................150 Program Memory Maps BSF ..........................................................................150 PIC16C72 ...........................................................19 BTFSC .....................................................................150 PIC16C73 ...........................................................19 BTFSS .....................................................................151 PIC16C73A ........................................................19 CALL ........................................................................151 PIC16C74 ...........................................................19 CLRF ........................................................................152 PIC16C74A ........................................................19 CLRW ......................................................................152 PIC16C76 ...........................................................20 CLRWDT ..................................................................152 PIC16C77 ...........................................................20 COMF ......................................................................153 Register File Maps DECF .......................................................................153 PIC16C72 ...........................................................21 DECFSZ ...................................................................153 PIC16C73 ...........................................................21 GOTO ......................................................................154 PIC16C73A ........................................................21 INCF .........................................................................154 PIC16C74 ...........................................................21 INCFSZ ....................................................................155 PIC16C74A ........................................................21 IORLW .....................................................................155 PIC16C76 ...........................................................21 IORWF .....................................................................156 PIC16C77 ...........................................................21 MOVF .......................................................................156 MPASM Assembler ..........................................................163 MOVLW ...................................................................156 MPLAB-C ..........................................................................165 MOVWF ...................................................................156 MPSIM Software Simulator ......................................163, 165 NOP .........................................................................157 OPTION ...................................................................157 O RETFIE ....................................................................157 OERR bit ..........................................................................100 RETLW ....................................................................158 OPCODE ..........................................................................147 RETURN ..................................................................158 OPTION ..............................................................................29 RLF ..........................................................................159 OPTION Register ...............................................................31 RRF ..........................................................................159 Orthogonal ............................................................................9 SLEEP .....................................................................160 OSC selection ...................................................................129 SUBLW ....................................................................160 Oscillator SUBWF ....................................................................161 HS .....................................................................131, 135 SWAPF ....................................................................161 LP .....................................................................131, 135 TRIS .........................................................................161 RC ............................................................................131 XORLW ....................................................................162 XT .....................................................................131, 135 XORWF ....................................................................162 Oscillator Configurations ..................................................131 Section .....................................................................147 Output of TMR2 ..................................................................69 Summary Table ........................................................148 INT Interrupt .....................................................................143 P INTCON .............................................................................29 P ...................................................................................78, 83 INTCON Register ...............................................................32 Packaging INTEDG bit .................................................................31, 143 28-Lead Ceramic w/Window .....................................251 Internal Sampling Switch (Rss) Impedance .....................120 28-Lead PDIP ...........................................................253 Interrupts ..........................................................................129 28-Lead SOIC ...........................................................255 PortB Change ..........................................................143 28-Lead SSOP .........................................................256 RB7:RB4 Port Change ...............................................45 40-Lead CERDIP w/Window ....................................252 Section .....................................................................141 40-Lead PDIP ...........................................................254 TMR0 .......................................................................143 44-Lead MQFP .........................................................258 IRP bit ................................................................................30 44-Lead PLCC ..........................................................257 L 44-Lead TQFP ..........................................................259 Paging, Program Memory ...................................................40 Loading of PC ....................................................................40 Parallel Slave Port ........................................................50, 54 PCFG0 bit .........................................................................118 PCFG1 bit .........................................................................118 PCFG2 bit .........................................................................118 PCL Register ............................23, 24, 25, 26, 27, 28, 29, 40 PCLATH ...........................................................................136 PCLATH Register .....................23, 24, 25, 26, 27, 28, 29, 40 PCON Register .....................................................29, 39, 135 PD bit ..................................................................30, 133, 135 PICDEM-1 Low-Cost PIC16/17 Demo Board ...........163, 164 PICDEM-2 Low-Cost PIC16CXX Demo Board .........163, 164 PICDEM-3 Low-Cost PIC16C9XXX Demo Board ............164 PICMASTER In-Circuit Emulator ......................................163 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 275

PIC16C7X PICSTART Low-Cost Development System ....................163 POR .........................................................................134, 135 PIE1 Register ...............................................................29, 33 Oscillator Start-up Timer (OST) .......................129, 134 PIE2 Register ...............................................................29, 37 Power Control Register (PCON) ..............................135 Pin Compatible Devices ...................................................271 Power-on Reset (POR) ............................129, 134, 136 Pin Functions Power-up Timer (PWRT) .................................129, 134 MCLR/VPP ......................................................13, 14, 15 Power-Up-Timer (PWRT) ........................................134 OSC1/CLKIN ..................................................13, 14, 15 Time-out Sequence .................................................135 OSC2/CLKOUT ..............................................13, 14, 15 Time-out Sequence on Power-up ............................139 RA0/AN0 ........................................................13, 14, 15 TO ....................................................................133, 135 RA1/AN1 ........................................................13, 14, 15 POR bit ......................................................................39, 135 RA2/AN2 ........................................................13, 14, 15 Port RB Interrupt ..............................................................143 RA3/AN3/VREF ...............................................13, 14, 15 PORTA ......................................................................29, 136 RA4/T0CKI .....................................................13, 14, 15 PORTA Register ..............................................23, 25, 27, 43 RA5/AN4/SS ..................................................13, 14, 15 PORTB ......................................................................29, 136 RB0/INT .........................................................13, 14, 15 PORTB Register ..............................................23, 25, 27, 45 RB1 ................................................................13, 14, 15 PORTC ......................................................................29, 136 RB2 ................................................................13, 14, 15 PORTC Register ..............................................23, 25, 27, 48 RB3 ................................................................13, 14, 15 PORTD ......................................................................29, 136 RB4 ................................................................13, 14, 15 PORTD Register ....................................................25, 27, 50 RB5 ................................................................13, 14, 15 PORTE ......................................................................29, 136 RB6 ................................................................13, 14, 15 PORTE Register ....................................................25, 27, 51 RB7 ................................................................13, 14, 15 Power-down Mode (SLEEP) ............................................145 RC0/T1OSO/T1CKI .......................................13, 14, 16 PR2 ....................................................................................29 RC1/T1OSI ................................................................13 PR2 Register .........................................................26, 28, 69 RC1/T1OSI/CCP2 ................................................14, 16 Prescaler, Switching Between Timer0 and WDT ...............63 RC2/CCP1 .....................................................13, 14, 16 PRO MATE Universal Programmer .................................163 RC3/SCK/SCL ...............................................13, 14, 16 Program Branches ...............................................................9 RC4/SDI/SDA ................................................13, 14, 16 Program Memory RC5/SDO .......................................................13, 14, 16 Paging .......................................................................40 RC6 ............................................................................13 Program Memory Maps RC6/TX/CK ............................................14, 16, 99–114 PIC16C72 ..................................................................19 RC7 ............................................................................13 PIC16C73 ..................................................................19 RC7/RX/DT ............................................14, 16, 99–114 PIC16C73A ................................................................19 RD0/PSP0 ..................................................................16 PIC16C74 ..................................................................19 RD1/PSP1 ..................................................................16 PIC16C74A ................................................................19 RD2/PSP2 ..................................................................16 Program Verification ........................................................146 RD3/PSP3 ..................................................................16 PS0 bit ...............................................................................31 RD4/PSP4 ..................................................................16 PS1 bit ...............................................................................31 RD5/PSP5 ..................................................................16 PS2 bit ...............................................................................31 RD6/PSP6 ..................................................................16 PSA bit ...............................................................................31 RD7/PSP7 ..................................................................16 PSPIE bit ...........................................................................34 RE0/RD/AN5 ..............................................................16 PSPIF bit ............................................................................36 RE1/WR/AN6 .............................................................16 PSPMODE bit ........................................................50, 51, 54 RE2/CS/AN7 ..............................................................16 PUSH .................................................................................40 SCK ......................................................................80–82 R SDI .......................................................................80–82 SDO .....................................................................80–82 R/W ..............................................................................78, 83 SS ........................................................................80–82 R/W bit .............................................................90, 94, 95, 96 VDD ................................................................13, 14, 16 RBIF bit ......................................................................45, 143 VSS .................................................................13, 14, 16 RBPU bit ............................................................................31 Pinout Descriptions RC Oscillator ............................................................132, 135 PIC16C72 ..................................................................13 RCIE bit .............................................................................34 PIC16C73 ..................................................................14 RCIF bit ..............................................................................36 PIC16C73A ................................................................14 RCREG ..............................................................................29 PIC16C74 ..................................................................15 RCSTA Register ........................................................29, 100 PIC16C74A ................................................................15 RCV_MODE ......................................................................98 PIC16C76 ..................................................................14 RD pin ................................................................................54 PIC16C77 ..................................................................15 Read/Write bit Information, R/W ..................................78, 83 PIR1 Register .....................................................................35 Read-Modify-Write .............................................................53 PIR2 Register .....................................................................38 Receive Overflow Detect bit, SSPOV ................................79 POP ....................................................................................40 Receive Overflow Indicator bit, SSPOV .............................84 Register File .......................................................................20 DS30390E-page 276 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Registers SPBRG Register ...........................................................26, 28 FSR Special Event Trigger .......................................................125 Summary ...........................................................29 Special Features of the CPU ............................................129 INDF Special Function Registers Summary ...........................................................29 PIC16C72 ...................................................................23 Initialization Conditions ............................................136 PIC16C73 .............................................................25, 27 INTCON PIC16C73A ...........................................................25, 27 Summary ...........................................................29 PIC16C74 .............................................................25, 27 Maps PIC16C74A ...........................................................25, 27 PIC16C72 ..........................................................21 PIC16C76 ...................................................................27 PIC16C73 ..........................................................21 PIC16C77 ...................................................................27 PIC16C73A ........................................................21 Special Function Registers, Section ...................................23 PIC16C74 ..........................................................21 SPEN bit ...........................................................................100 PIC16C74A ........................................................21 SPI PIC16C76 ..........................................................22 Block Diagram ......................................................80, 85 PIC16C77 ..........................................................22 Master Mode ...............................................................86 OPTION Master Mode Timing ...................................................87 Summary ...........................................................29 Mode ...........................................................................80 PCL Serial Clock ................................................................85 Summary ...........................................................29 Serial Data In ..............................................................85 PCLATH Serial Data Out ...........................................................85 Summary ...........................................................29 Slave Mode Timing .....................................................88 PORTB Slave Mode Timing Diagram ......................................87 Summary ...........................................................29 Slave Select ................................................................85 Reset Conditions ......................................................136 SPI clock .....................................................................86 SSPBUF SPI Mode ....................................................................85 Section ...............................................................80 SSPCON ....................................................................84 SSPCON SSPSTAT ...................................................................83 Diagram .............................................................79 SPI Clock Edge Select bit, CKE .........................................83 SSPSR SPI Data Input Sample Phase Select bit, SMP ..................83 Section ...............................................................80 SPI Mode ............................................................................80 SSPSTAT ...................................................................83 SREN bit ...........................................................................100 Diagram .............................................................78 SS .......................................................................................80 Section ...............................................................78 SSP STATUS Module Overview ........................................................77 Summary ...........................................................29 Section ........................................................................77 Summary ..............................................................25, 27 SSPBUF .....................................................................86 TMR0 SSPCON ....................................................................84 Summary ...........................................................29 SSPSR .......................................................................86 TRISB SSPSTAT ...................................................................83 Summary ...........................................................29 SSP in I2C Mode - See I2C Reset ........................................................................129, 133 SSPADD .............................................................................93 Reset Conditions for Special Registers ...........................136 SSPADD Register ............................................24, 26, 28, 29 RP0 bit .........................................................................20, 30 SSPBUF .......................................................................29, 93 RP1 bit ...............................................................................30 SSPBUF Register .........................................................25, 27 RX9 bit .............................................................................100 SSPCON ......................................................................79, 84 RX9D bit ...........................................................................100 SSPCON Register ........................................................25, 27 SSPEN .........................................................................79, 84 S SSPIE bit ............................................................................33 S ...................................................................................78, 83 SSPIF bit ......................................................................35, 36 SCK ....................................................................................80 SSPM3:SSPM0 ............................................................79, 84 SCL ....................................................................................94 SSPOV ...................................................................79, 84, 94 SDI .....................................................................................80 SSPSTAT .....................................................................78, 93 SDO ...................................................................................80 SSPSTAT Register .....................................24, 26, 28, 29, 83 Serial Communication Interface (SCI) Module, See USART Stack ...................................................................................40 Services Overflows ....................................................................40 One-Time-Programmable (OTP) .................................7 Underflow ...................................................................40 Quick-Turnaround-Production (QTP) ...........................7 Start bit, S .....................................................................78, 83 Serialized Quick-Turnaround Production (SQTP) ........7 STATUS Register .........................................................29, 30 Slave Mode Stop bit, P .....................................................................78, 83 SCL ............................................................................94 Synchronous Serial Port (SSP) SDA ............................................................................94 Block Diagram, SPI Mode ..........................................80 SLEEP .....................................................................129, 133 SPI Master/Slave Diagram .........................................81 SMP ...................................................................................83 SPI Mode ....................................................................80 Software Simulator (MPSIM) ...........................................165 Synchronous Serial Port Enable bit, SSPEN ................79, 84 SPBRG ..............................................................................29 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 277

PIC16C7X Synchronous Serial Port Mode Select bits, External Clock Timing ......................173, 189, 207, 226 SSPM3:SSPM0 ............................................................79, 84 I2C Bus Data ....................................180, 197, 215, 236 Synchronous Serial Port Module ........................................77 I2C Bus Start/Stop bits .....................179, 196, 214, 235 Synchronous Serial Port Status Register ...........................83 I2C Clock Synchronization .........................................92 I2C Data Transfer Wait State .....................................90 T I2C Multi-Master Arbitration .......................................92 T0CS bit .............................................................................31 I2C Reception (7-bit Address) ....................................95 T1CKPS0 bit ......................................................................65 Parallel Slave Port ...................................................194 T1CKPS1 bit ......................................................................65 Power-up Timer ...............................175, 191, 209, 228 T1CON ...............................................................................29 Reset ...............................................175, 191, 209, 228 T1CON Register ...........................................................29, 65 SPI Master Mode .......................................................87 T1OSCEN bit .....................................................................65 SPI Mode .................................................178, 195, 213 T1SYNC bit ........................................................................65 SPI Mode, Master/Slave Mode, No SS Control .........82 T2CKPS0 bit ......................................................................70 SPI Mode, Slave Mode With SS Control ...................82 T2CKPS1 bit ......................................................................70 SPI Slave Mode (CKE = 1) ........................................88 T2CON Register ...........................................................29, 70 SPI Slave Mode Timing (CKE = 0) ............................87 TAD ...................................................................................121 Start-up Timer ..................................175, 191, 209, 228 Timer Modules, Overview ..................................................57 Time-out Sequence .................................................139 Timer0 Timer0 .......................................59, 176, 192, 210, 229 RTCC .......................................................................136 Timer0 Interrupt Timing .............................................60 Timers Timer0 with External Clock ........................................61 Timer0 Timer1 .............................................176, 192, 210, 229 Block Diagram ....................................................59 USART Asynchronous Master Transmission ..........107 External Clock ....................................................61 USART Asynchronous Reception ...........................108 External Clock Timing ........................................61 USART RX Pin Sampling ................................104, 105 Increment Delay .................................................61 USART Synchronous Receive ................198, 216, 237 Interrupt ..............................................................59 USART Synchronous Reception .............................113 Interrupt Timing ..................................................60 USART Synchronous Transmission 111, 198, 216, 237 Overview ............................................................57 Wake-up from Sleep via Interrupt ............................146 Prescaler ............................................................62 Watchdog Timer ..............................175, 191, 209, 228 Prescaler Block Diagram ...................................62 TMR0 .................................................................................29 Section ...............................................................59 TMR0 Register .............................................................25, 27 Switching Prescaler Assignment ........................63 TMR1CS bit .......................................................................65 Synchronization .................................................61 TMR1H ..............................................................................29 T0CKI .................................................................61 TMR1H Register ....................................................23, 25, 27 T0IF ..................................................................143 TMR1IE bit .........................................................................33 Timing ................................................................59 TMR1IF bit ...................................................................35, 36 TMR0 Interrupt .................................................143 TMR1L ...............................................................................29 Timer1 TMR1L Register .....................................................23, 25, 27 Asynchronous Counter Mode ............................67 TMR1ON bit .......................................................................65 Block Diagram ....................................................66 TMR2 .................................................................................29 Capacitor Selection ............................................67 TMR2 Register .......................................................23, 25, 27 External Clock Input ...........................................66 TMR2IE bit .........................................................................33 External Clock Input Timing ...............................67 TMR2IF bit ...................................................................35, 36 Operation in Timer Mode ...................................66 TMR2ON bit .......................................................................70 Oscillator ............................................................67 TO bit .................................................................................30 Overview ............................................................57 TOUTPS0 bit .....................................................................70 Prescaler ......................................................66, 68 TOUTPS1 bit .....................................................................70 Resetting of Timer1 Registers ...........................68 TOUTPS2 bit .....................................................................70 Resetting Timer1 using a CCP Trigger Output ..68 TOUTPS3 bit .....................................................................70 Synchronized Counter Mode .............................66 TRISA ................................................................................29 T1CON ...............................................................65 TRISA Register ................................................24, 26, 28, 43 TMR1H ...............................................................67 TRISB ................................................................................29 TMR1L ...............................................................67 TRISB Register ................................................24, 26, 28, 45 Timer2 TRISC ................................................................................29 Block Diagram ....................................................69 TRISC Register ................................................24, 26, 28, 48 Module ...............................................................69 TRISD ................................................................................29 Overview ............................................................57 TRISD Register ......................................................26, 28, 50 Postscaler ..........................................................69 TRISE ................................................................................29 Prescaler ............................................................69 TRISE Register ......................................................26, 28, 51 T2CON ...............................................................70 Two’s Complement ..............................................................9 Timing Diagrams TXIE bit ..............................................................................34 A/D Conversion ................................182, 200, 218, 239 TXIF bit ..............................................................................36 Brown-out Reset ..............................134, 175, 209, 228 TXREG ..............................................................................29 Capture/Compare/PWM ...................177, 193, 211, 230 TXSTA ...............................................................................29 CLKOUT and I/O ..............................174, 190, 208, 227 TXSTA Register .................................................................99 DS30390E-page 278 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X U LIST OF EXAMPLES UA ................................................................................78, 83 Universal Synchronous Asynchronous Receiver Transmitter Example 3-1: Instruction Pipeline Flow............................17 (USART) ............................................................................99 Example 4-1: Call of a Subroutine in Page 1 Update Address bit, UA ...............................................78, 83 from Page 0..............................................41 USART Example 4-2: Indirect Addressing....................................41 Asynchronous Mode ................................................106 Example 5-1: Initializing PORTA......................................43 Asynchronous Receiver ...........................................108 Example 5-2: Initializing PORTB......................................45 Asynchronous Reception .........................................109 Example 5-3: Initializing PORTC.....................................48 Asynchronous Transmission ....................................107 Example 5-4: Read-Modify-Write Instructions Asynchronous Transmitter .......................................106 on an I/O Port............................................53 Baud Rate Generator (BRG) ....................................101 Example 7-1: Changing Prescaler (Timer0fi WDT).........63 Receive Block Diagram ............................................108 Example 7-2: Changing Prescaler (WDTfi Timer0).........63 Sampling ..................................................................104 Example 8-1: Reading a 16-bit Free-Running Timer.......67 Synchronous Master Mode ......................................110 Example 10-1: Changing Between Capture Synchronous Master Reception ...............................112 Prescalers.................................................73 Synchronous Master Transmission ..........................110 Example 10-2: PWM Period and Duty Cycle Synchronous Slave Mode ........................................114 Calculation.................................................75 Synchronous Slave Reception .................................114 Example 11-1: Loading the SSPBUF (SSPSR) Synchronous Slave Transmit ...................................114 Register....................................................80 Transmit Block Diagram ...........................................106 Example 11-2: Loading the SSPBUF (SSPSR) UV Erasable Devices ...........................................................7 Register (PIC16C76/77)...........................85 Example 12-1: Calculating Baud Rate Error....................101 W Equation 13-1: A/D Minimum Charging Time...................120 W Register Example 13-1: Calculating the Minimum Required ALU ..............................................................................9 Acquisition Time.....................................120 Wake-up from SLEEP ......................................................145 Example 13-2: A/D Conversion........................................122 Watchdog Timer (WDT) ...........................129, 133, 136, 144 Example 13-3: 4-bit vs. 8-bit Conversion Times..............123 WCOL ..........................................................................79, 84 Example 14-1: Saving STATUS, W, and PCLATH WDT .................................................................................136 Registers in RAM.....................................143 Block Diagram ..........................................................144 Period .......................................................................144 Programming Considerations ..................................144 Timeout ....................................................................136 Word ................................................................................129 WR pin ...............................................................................54 Write Collision Detect bit, WCOL .................................79, 84 X XMIT_MODE ......................................................................98 Z Z bit ....................................................................................30 Zero bit .................................................................................9 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 279

PIC16C7X LIST OF FIGURES Figure 8-1: T1CON: Timer1 Control Register (Address 10h)..........................................65 Figure 3-1: PIC16C72 Block Diagram.........................10 Figure 8-2: Timer1 Block Diagram..............................66 Figure 3-2: PIC16C73/73A/76 Block Diagram.............11 Figure 9-1: Timer2 Block Diagram..............................69 Figure 3-3: PIC16C74/74A/77 Block Diagram.............12 Figure 9-2: T2CON: Timer2 Control Register Figure 3-4: Clock/Instruction Cycle..............................17 (Address 12h)..........................................70 Figure 4-1: PIC16C72 Program Memory Map Figure 10-1: CCP1CON Register (Address 17h)/ and Stack..................................................19 CCP2CON Register (Address 1Dh)..........72 Figure 4-2: PIC16C73/73A/74/74A Program Figure 10-2: Capture Mode Operation Memory Map and Stack............................19 Block Diagram..........................................72 Figure 4-3: PIC16C76/77 Program Memory Figure 10-3: Compare Mode Operation Map and Stack..........................................20 Block Diagram..........................................73 Figure 4-4: PIC16C72 Register File Map....................21 Figure 10-4: Simplified PWM Block Diagram................74 Figure 4-5: PIC16C73/73A/74/74A Register Figure 10-5: PWM Output.............................................74 File Map....................................................21 Figure 11-1: SSPSTAT: Sync Serial Port Status Figure 4-6: PIC16C76/77 Register File Map...............22 Register (Address 94h).............................78 Figure 4-7: Status Register (Address 03h, Figure 11-2: SSPCON: Sync Serial Port Control 83h, 103h, 183h)......................................30 Register (Address 14h).............................79 Figure 4-8: OPTION Register (Address 81h, Figure 11-3: SSP Block Diagram (SPI Mode)...............80 181h).........................................................31 Figure 11-4: SPI Master/Slave Connection...................81 Figure 4-9: INTCON Register Figure 11-5: SPI Mode Timing, Master Mode (Address 0Bh, 8Bh, 10bh, 18bh)...............32 or Slave Mode w/o SS Control..................82 Figure 4-10: PIE1 Register PIC16C72 Figure 11-6: SPI Mode Timing, Slave Mode with (Address 8Ch)...........................................33 SS Control................................................82 Figure 4-11: PIE1 Register PIC16C73/73A/ Figure 11-7: SSPSTAT: Sync Serial Port Status 74/74A/76/77 (Address 8Ch).....................34 Register (Address 94h)(PIC16C76/77).....83 Figure 4-12: PIR1 Register PIC16C72 Figure 11-8: SSPCON: Sync Serial Port Control (Address 0Ch)...........................................35 Register (Address 14h)(PIC16C76/77).....84 Figure 4-13: PIR1 Register PIC16C73/73A/ Figure 11-9: SSP Block Diagram (SPI Mode) 74/74A/76/77 (Address 0Ch).....................36 (PIC16C76/77)..........................................85 Figure 4-14: PIE2 Register (Address 8Dh)....................37 Figure 11-10: SPI Master/Slave Connection Figure 4-15: PIR2 Register (Address 0Dh)....................38 PIC16C76/77)...........................................86 Figure 4-16: PCON Register (Address 8Eh).................39 Figure 11-11: SPI Mode Timing, Master Mode Figure 4-17: Loading of PC In Different (PIC16C76/77).........................................87 Situations..................................................40 Figure 11-12: SPI Mode Timing (Slave Mode Figure 4-18: Direct/Indirect Addressing.........................41 With CKE = 0) (PIC16C76/77).................87 Figure 5-1: Block Diagram of RA3:RA0 Figure 11-13: SPI Mode Timing (Slave Mode and RA5 Pins............................................43 With CKE = 1) (PIC16C76/77)..................88 Figure 5-2: Block Diagram of RA4/T0CKI Pin.............43 Figure 11-14: Start and Stop Conditions.........................89 Figure 5-3: Block Diagram of RB3:RB0 Pins...............45 Figure 11-15: 7-bit Address Format................................90 Figure 5-4: Block Diagram of RB7:RB4 Pins Figure 11-16: I2C 10-bit Address Format........................90 (PIC16C73/74)..........................................46 Figure 11-17: Slave-receiver Acknowledge....................90 Figure 5-5: Block Diagram of Figure 11-18: Data Transfer Wait State..........................90 RB7:RB4 Pins (PIC16C72/73A/ Figure 11-19: Master-transmitter Sequence...................91 74A/76/77).................................................46 Figure 11-20: Master-receiver Sequence........................91 Figure 5-6: PORTC Block Diagram Figure 11-21: Combined Format.....................................91 (Peripheral Output Override)....................48 Figure 11-22: Multi-master Arbitration Figure 5-7: PORTD Block Diagram (Two Masters)...........................................92 (in I/O Port Mode).....................................50 Figure 11-23: Clock Synchronization..............................92 Figure 5-8: PORTE Block Diagram Figure 11-24: SSP Block Diagram (in I/O Port Mode).....................................51 (I2C Mode)................................................93 Figure 5-9: TRISE Register (Address 89h)..................51 Figure 11-25: I2C Waveforms for Reception Figure 5-10: Successive I/O Operation.........................53 (7-bit Address)..........................................95 Figure 5-11: PORTD and PORTE Block Diagram Figure 11-26: I2C Waveforms for Transmission (Parallel Slave Port)..................................54 (7-bit Address)..........................................96 Figure 5-12: Parallel Slave Port Write Waveforms........55 Figure 11-27: Operation of the I2C Module in Figure 5-13: Parallel Slave Port Read Waveforms........55 IDLE_MODE, RCV_MODE or Figure 7-1: Timer0 Block Diagram...............................59 XMIT_MODE............................................98 Figure 7-2: Timer0 Timing: Internal Clock/No Figure 12-1: TXSTA: Transmit Status and Prescale....................................................59 Control Register (Address 98h)................99 Figure 7-3: Timer0 Timing: Internal Figure 12-2: RCSTA: Receive Status and Clock/Prescale 1:2....................................60 Control Register (Address 18h)..............100 Figure 7-4: Timer0 Interrupt Timing.............................60 Figure 12-3: RX Pin Sampling Scheme. BRGH = 0 Figure 7-5: Timer0 Timing with External Clock............61 (PIC16C73/73A/74/74A).........................104 Figure 7-6: Block Diagram of the Timer0/WDT Figure 12-4: RX Pin Sampling Scheme, BRGH = 1 Prescaler...................................................62 (PIC16C73/73A/74/74A).........................104 DS30390E-page 280 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X Figure 12-5: RX Pin Sampling Scheme, BRGH = 1 Figure 17-4: Reset, Watchdog Timer, Oscillator (PIC16C73/73A/74/74A).........................104 Start-up Timer and Power-up Timer Figure 12-6: RX Pin Sampling Scheme, Timing......................................................175 BRGH = 0 OR BRGH = 1 ( Figure 17-5: Brown-out Reset Timing..........................175 PIC16C76/77).........................................105 Figure 17-6: Timer0 and Timer1 External Figure 12-7: USART Transmit Block Diagram.............106 Clock Timings.........................................176 Figure 12-8: Asynchronous Master Transmission.......107 Figure 17-7: Capture/Compare/PWM Figure 12-9: Asynchronous Master Transmission Timings (CCP1).......................................177 (Back to Back).........................................107 Figure 17-8: SPI Mode Timing.....................................178 Figure 12-10: USART Receive Block Diagram..............108 Figure 17-9: I2C Bus Start/Stop Bits Timing.................179 Figure 12-11: Asynchronous Reception........................108 Figure 17-10: I2C Bus Data Timing................................180 Figure 12-12: Synchronous Transmission.....................111 Figure 17-11: A/D Conversion Timing............................182 Figure 12-13: Synchronous Transmission Figure 18-1: Load Conditions.......................................188 (Through TXEN)......................................111 Figure 18-2: External Clock Timing..............................189 Figure 12-14: Synchronous Reception Figure 18-3: CLKOUT and I/O Timing..........................190 (Master Mode, SREN).............................113 Figure 18-4: Reset, Watchdog Timer, Figure 13-1: ADCON0 Register (Address 1Fh)...........117 Oscillator Start-up Timer and Power-up Tim- Figure 13-2: ADCON1 Register (Address 9Fh)...........118 er Timing..................................................191 Figure 13-3: A/D Block Diagram..................................119 Figure 18-5: Timer0 and Timer1 External Figure 13-4: Analog Input Model.................................120 Clock Timings.........................................192 Figure 13-5: A/D Transfer Function.............................125 Figure 18-6: Capture/Compare/PWM Timings Figure 13-6: Flowchart of A/D Operation.....................126 (CCP1 and CCP2)...................................193 Figure 14-1: Configuration Word for Figure 18-7: Parallel Slave Port Timing PIC16C73/74...........................................129 (PIC16C74)..............................................194 Figure 14-2: Configuration Word for Figure 18-8: SPI Mode Timing.....................................195 PIC16C72/73A/74A/76/77.......................130 Figure 18-9: I2C Bus Start/Stop Bits Timing.................196 Figure 14-3: Crystal/Ceramic Resonator Figure 18-10: I2C Bus Data Timing................................197 Operation (HS, XT or LP Figure 18-11: USART Synchronous Transmission OSC Configuration).................................131 (Master/Slave) Timing..............................198 Figure 14-4: External Clock Input Operation Figure 18-12: USART Synchronous Receive (HS, XT or LP OSC Configuration).........131 (Master/Slave) Timing..............................198 Figure 14-5: External Parallel Resonant Crystal Figure 18-13: A/D Conversion Timing............................200 Oscillator Circuit......................................132 Figure 19-1: Load Conditions.......................................206 Figure 14-6: External Series Resonant Crystal Figure 19-2: External Clock Timing..............................207 Oscillator Circuit.....................................132 Figure 19-3: CLKOUT and I/O Timing..........................208 Figure 14-7: RC Oscillator Mode.................................132 Figure 19-4: Reset, Watchdog Timer, Figure 14-8: Simplified Block Diagram of On-chip Oscillator Start-up Timer and Reset Circuit............................................133 Power-up Timer Timing...........................209 Figure 14-9: Brown-out Situations...............................134 Figure 19-5: Brown-out Reset Timing..........................209 Figure 14-10: Time-out Sequence on Power-up Figure 19-6: Timer0 and Timer1 External (MCLR not Tied to VDD): Case 1.............139 Clock Timings.........................................210 Figure 14-11: Time-out Sequence on Power-up Figure 19-7: Capture/Compare/PWM Timings (MCLR Not Tied To VDD): Case 2..........139 (CCP1 and CCP2)...................................211 Figure 14-12: Time-out Sequence on Power-up Figure 19-8: Parallel Slave Port Timing (MCLR Tied to VDD)................................139 (PIC16C74A)...........................................212 Figure 14-13: External Power-on Reset Circuit Figure 19-9: SPI Mode Timing.....................................213 (for Slow VDD Power-up).........................140 Figure 19-10: I2C Bus Start/Stop Bits Timing.................214 Figure 14-14: External Brown-out Protection Figure 19-11: I2C Bus Data Timing................................215 Circuit 1...................................................140 Figure 19-12: USART Synchronous Transmission Figure 14-15: External Brown-out Protection (Master/Slave) Timing..............................216 Circuit 2...................................................140 Figure 19-13: USART Synchronous Receive Figure 14-16: Interrupt Logic.........................................142 (Master/Slave) Timing..............................216 Figure 14-17: INT Pin Interrupt Timing..........................142 Figure 19-14: A/D Conversion Timing............................218 Figure 14-18: Watchdog Timer Block Diagram.............144 Figure 20-1: Load Conditions.......................................225 Figure 14-19: Summary of Watchdog Figure 20-2: External Clock Timing..............................226 Timer Registers.......................................144 Figure 20-3: CLKOUT and I/O Timing..........................227 Figure 14-20: Wake-up from Sleep Through Figure 20-4: Reset, Watchdog Timer, Interrupt...................................................146 Oscillator Start-up Timer and Figure 14-21: Typical In-Circuit Serial Power-up Timer Timing...........................228 Programming Connection.......................146 Figure 20-5: Brown-out Reset Timing..........................228 Figure 15-1: General Format for Instructions..............147 Figure 20-6: Timer0 and Timer1 External Figure 17-1: Load Conditions......................................172 Clock Timings..........................................229 Figure 17-2: External Clock Timing.............................173 Figure 20-7: Capture/Compare/PWM Timings Figure 17-3: CLKOUT and I/O Timing.........................174 (CCP1 and CCP2)...................................230 Figure 20-8: Parallel Slave Port Timing (PIC16C77).............................................231 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 281

PIC16C7X Figure 20-9: SPI Master Mode Timing (CKE = 0)........232 Figure 21-27: Typical IDD vs. Frequency Figure 20-10: SPI Master Mode Timing (CKE = 1)........232 (XT Mode, 25(cid:176) C).....................................249 Figure 20-11: SPI Slave Mode Timing (CKE = 0)..........233 Figure 21-28: Maximum IDD vs. Frequency Figure 20-12: SPI Slave Mode Timing (CKE = 1)..........233 (XT Mode, -40(cid:176) C to 85(cid:176) C).......................249 Figure 20-13: I2C Bus Start/Stop Bits Timing................235 Figure 21-29: Typical IDD vs. Frequency Figure 20-14: I2C Bus Data Timing...............................236 (HS Mode, 25(cid:176) C)....................................250 Figure 20-15: USART Synchronous Transmission Figure 21-30: Maximum IDD vs. Frequency (Master/Slave) Timing.............................237 (HS Mode, -40(cid:176) C to 85(cid:176) C)......................250 Figure 20-16: USART Synchronous Receive (Master/Slave) Timing.............................237 Figure 20-17: A/D Conversion Timing...........................239 Figure 21-1: Typical IPD vs. VDD (WDT Disabled, RC Mode)................................................241 Figure 21-2: Maximum IPD vs. VDD (WDT Disabled, RC Mode)................................241 Figure 21-3: Typical IPD vs. VDD @ 25(cid:176) C (WDT Enabled, RC Mode).................................242 Figure 21-4: Maximum IPD vs. VDD (WDT Enabled, RC Mode).................................242 Figure 21-5: Typical RC Oscillator Frequency vs. VDD..................................242 Figure 21-6: Typical RC Oscillator Frequency vs. VDD..................................242 Figure 21-7: Typical RC Oscillator Frequency vs. VDD..................................242 Figure 21-8: Typical IPD vs. VDD Brown-out Detect Enabled (RC Mode).....................243 Figure 21-9: Maximum IPD vs. VDD Brown-out Detect Enabled (85(cid:176) C to -40(cid:176) C, RC Mode)......................243 Figure 21-10: Typical IPD vs. Timer1 Enabled (32 kHz, RC0/RC1= 33 pF/33 pF, RC Mode)................................................243 Figure 21-11: Maximum IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, 85(cid:176) C to -40(cid:176) C, RC Mode).......243 Figure 21-12: Typical IDD vs. Frequency (RC Mode @ 22 pF, 25(cid:176) C)......................244 Figure 21-13: Maximum IDD vs. Frequency (RC Mode @ 22 pF, -40(cid:176) C to 85(cid:176) C)........244 Figure 21-14: Typical IDD vs. Frequency (RC Mode @ 100 pF, 25(cid:176) C)....................245 Figure 21-15: Maximum IDD vs. Frequency ( RC Mode @ 100 pF, -40(cid:176) C to 85(cid:176) C).......245 Figure 21-16: Typical IDD vs. Frequency (RC Mode @ 300 pF, 25(cid:176) C)....................246 Figure 21-17: Maximum IDD vs. Frequency (RC Mode @ 300 pF, -40(cid:176) C to 85(cid:176) C)......246 Figure 21-18: Typical IDD vs. Capacitance @ 500 kHz (RC Mode)................................247 Figure 21-19: Transconductance(gm) of HS Oscillator vs. VDD..............................247 Figure 21-20: Transconductance(gm) of LP Oscillator vs. VDD....................................247 Figure 21-21: Transconductance(gm) of XT Oscillator vs. VDD....................................247 Figure 21-22: Typical XTAL Startup Time vs. VDD (LP Mode, 25(cid:176) C).....................................248 Figure 21-23: Typical XTAL Startup Time vs. VDD (HS Mode, 25(cid:176) C).....................................248 Figure 21-24: Typical XTAL Startup Time vs. VDD (XT Mode, 25(cid:176) C).....................................248 Figure 21-25: Typical Idd vs. Frequency (LP Mode, 25(cid:176) C).....................................249 Figure 21-26: Maximum IDD vs. Frequency (LP Mode, 85(cid:176) C to -40(cid:176) C).......................249 DS30390E-page 282 (cid:211) 1997 Microchip Technology Inc.

PIC16C7X LIST OF TABLES Table 12-8: Registers Associated with Synchronous Mas- ter Transmission......................................111 Table 1-1: PIC16C7XX Family of Devces....................6 Table 12-9: Registers Associated with Synchronous Mas- Table 3-1: PIC16C72 Pinout Description...................13 ter Reception...........................................112 Table 3-2: PIC16C73/73A/76 Pinout Description.......14 Table 12-10: Registers Associated with Table 3-3: PIC16C74/74A/77 Pinout Description.......15 Synchronous Slave Transmission...........115 Table 4-1: PIC16C72 Special Function Register Table 12-11: Registers Associated with Summary...................................................23 Synchronous Slave Reception.................115 Table 4-2: PIC16C73/73A/74/74A Special Table 13-1: TAD vs. Device Operating Function Register Summary......................25 Frequencies.............................................121 Table 4-3: PIC16C76/77 Special Function Table 13-2: Registers/Bits Associated with A/D, Register Summary....................................27 PIC16C72................................................126 Table 5-1: PORTA Functions.....................................44 Table 13-3: Summary of A/D Registers, Table 5-2: Summary of Registers Associated PIC16C73/73A/74/74A/76/77..................127 with PORTA..............................................44 Table 14-1: Ceramic Resonators................................131 Table 5-3: PORTB Functions.....................................46 Table 14-2: Capacitor Selection for Crystal Table 5-4: Summary of Registers Associated Oscillator..................................................131 with PORTB..............................................47 Table 14-3: Time-out in Various Situations, Table 5-5: PORTC Functions.....................................48 PIC16C73/74...........................................135 Table 5-6: Summary of Registers Associated Table 14-4: Time-out in Various Situations, with PORTC..............................................49 PIC16C72/73A/74A/76/77.......................135 Table 5-7: PORTD Functions.....................................50 Table 14-5: Status Bits and Their Significance, Table 5-8: Summary of Registers Associated PIC16C73/74...........................................135 with PORTD..............................................50 Table 14-6: Status Bits and Their Significance, Table 5-9: PORTE Functions.....................................52 PIC16C72/73A/74A/76/77.......................136 Table 5-10: Summary of Registers Associated Table 14-7: Reset Condition for Special with PORTE..............................................52 Registers..................................................136 Table 5-11: Registers Associated with Table 14-8: Initialization Conditions for all Parallel Slave Port.....................................55 Registers..................................................136 Table 7-1: Registers Associated with Timer0.............63 Table 15-1: Opcode Field Descriptions.......................147 Table 8-1: Capacitor Selection for the Table 15-2: PIC16CXX Instruction Set.......................148 Timer1 Oscillator.......................................67 Table 16-1: Development Tools from Microchip.........166 Table 8-2: Registers Associated with Timer1 Table 17-1: Cross Reference of Device Specs as a Timer/Counter...................................68 for Oscillator Configurations and Table 9-1: Registers Associated with Frequencies of Operation Timer2 as a Timer/Counter.......................70 (Commercial Devices).............................167 Table 10-1: CCP Mode - Timer Resource....................71 Table 17-2: External Clock Timing Table 10-2: Interaction of Two CCP Modules..............71 Requirements..........................................173 Table 10-3: Example PWM Frequencies and Table 17-3: CLKOUT and I/O Timing Resolutions at 20 MHz..............................75 Requirements..........................................174 Table 10-4: Registers Associated with Capture, Table 17-4: Reset, Watchdog Timer, Compare, and Timer1...............................75 Oscillator Start-up Timer, Power-up Table 10-5: Registers Associated with PWM Timer, and brown-out Reset and Timer2................................................76 Requirements..........................................175 Table 11-1: Registers Associated with SPI Table 17-5: Timer0 and Timer1 External Operation..................................................82 Clock Requirements................................176 Table 11-2: Registers Associated with SPI Table 17-6: Capture/Compare/PWM Operation (PIC16C76/77).........................88 Requirements (CCP1).............................177 Table 11-3: I2C Bus Terminology.................................89 Table 17-7: SPI Mode Requirements..........................178 Table 11-4: Data Transfer Received Byte Table 17-8: I2C Bus Start/Stop Bits Actions......................................................94 Requirements..........................................179 Table 11-5: Registers Associated with I2C Table 17-9: I2C Bus Data Requirements....................180 Operation..................................................97 Table 17-10: A/D Converter Characteristics: Table 12-1: Baud Rate Formula.................................101 PIC16C72-04 Table 12-2: Registers Associated with Baud (Commercial, Industrial, Extended) Rate Generator.......................................101 PIC16C72-10 Table 12-3: Baud Rates for Synchronous Mode........102 (Commercial, Industrial, Extended) Table 12-4: Baud Rates for Asynchronous Mode PIC16C72-20 (BRGH = 0).............................................102 (Commercial, Industrial, Extended) Table 12-5: Baud Rates for Asynchronous Mode PIC16LC72-04 (BRGH = 1).............................................103 (Commercial, Industrial)...........................181 Table 12-6: Registers Associated with Table 17-11: A/D Conversion Requirements................182 Asynchronous Transmission...................107 Table 18-1: Cross Reference of Device Table 12-7: Registers Associated with Specs for Oscillator Configurations Asynchronous Reception........................109 and Frequencies of Operation (Commercial Devices).............................183 (cid:211) 1997 Microchip Technology Inc. DS30390E-page 283

PIC16C7X Table 18-2: external Clock Timing Table 20-1: Cross Reference of Device Specs Requirements..........................................189 for Oscillator Configurations and Table 18-3: CLKOUT and I/O Timing Frequencies of Operation Requirements..........................................190 (Commercial Devices)............................220 Table 18-4: Reset, Watchdog Timer, Oscillator Table 20-2: External Clock Timing Start-up Timer and Power-up Timer Requirements.........................................226 Requirements.........................................191 Table 20-3: CLKOUT and I/O Timing Table 18-5: Timer0 and Timer1 External Clock Requirements.........................................227 Requirements..........................................192 Table 20-4: Reset, Watchdog Timer, Table 18-6: Capture/Compare/PWM Oscillator Start-up Timer, Power-up Requirements (CCP1 and CCP2)...........193 Timer, and brown-out reset Table 18-7: Parallel Slave Port Requirements Requirements.........................................228 (PIC16C74).............................................194 Table 20-5: Timer0 and Timer1 External Clock Table 18-8: SPI Mode Requirements.........................195 Requirements.........................................229 Table 18-9: I2C Bus Start/Stop Bits Table 20-6: Capture/Compare/PWM Requirements..........................................196 Requirements (CCP1 and CCP2)...........230 Table 18-10: I2C Bus Data Requirements....................197 Table 20-7: Parallel Slave Port Requirements Table 18-11: USART Synchronous Transmission (PIC16C77).............................................231 Requirements..........................................198 Table 20-8: SPI Mode requirements..........................234 Table 18-12: usart Synchronous Receive Table 20-9: I2C Bus Start/Stop Bits Requirements....235 Requirements..........................................198 Table 20-10: I2C Bus Data Requirements...................236 Table 18-13: A/D Converter Characteristics:................199 Table 20-11: USART Synchronous Transmission PIC16C73/74-04 Requirements.........................................237 (Commercial, Industrial) Table 20-12: USART Synchronous Receive PIC16C73/74-10 Requirements.........................................237 (Commercial, Industrial) Table 20-13: A/D Converter Characteristics:...............238 PIC16C73/74-20 PIC16C76/77-04 (Commercial, Industrial) (Commercial, Industrial, Extended) PIC16LC73/74-04 PIC16C76/77-10 (Commercial, Industrial)..........................199 (Commercial, Industrial, Extended) Table 18-14: A/D Conversion Requirements................200 PIC16C76/77-20 Table 19-1: Cross Reference of Device Specs (Commercial, Industrial, Extended) for Oscillator Configurations and PIC16LC76/77-04 Frequencies of Operation (Commercial, Industrial)..........................238 (Commercial Devices).............................201 Table 20-14: A/D Conversion Requirements...............239 Table 19-2: External Clock Timing Table 21-1: RC Oscillator Frequencies......................247 Requirements..........................................207 Table 21-2: Capacitor Selection for Crystal Table 19-3: CLKOUT and I/O Timing Oscillators...............................................248 Requirements..........................................208 Table E-1: Pin Compatible Devices..........................271 Table 19-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and brown-out reset Requirements.........209 Table 19-5: Timer0 and Timer1 External Clock Requirements..........................................210 Table 19-6: Capture/Compare/PWM Requirements (CCP1 and CCP2)...........211 Table 19-7: Parallel Slave Port Requirements (PIC16C74A)...........................................212 Table 19-8: SPI Mode Requirements.........................213 Table 19-9: I2C Bus Start/Stop Bits Requirements....214 Table 19-10: I2C Bus Data Requirements....................215 Table 19-11: USART Synchronous Transmission Requirements..........................................216 Table 19-12: USART Synchronous Receive Requirements..........................................216 Table 19-13: A/D Converter Characteristics:................217 PIC16C73A/74A-04 (Commercial, Industrial, Extended) PIC16C73A/74A-10 (Commercial, Industrial, Extended) PIC16C73A/74A-20 (Commercial, Industrial, Extended) PIC16LC73A/74A-04 (Commercial, Industrial)..........................217 Table 19-14: A/D Conversion Requirements................218 DS30390E-page 284 (cid:211) 1997 Microchip Technology Inc.

PIC16C6X ON-LINE SUPPORT The procedure to connect will vary slightly from country to country. Please check with your local CompuServe Microchip provides two methods of on-line support. agent for details if you have a problem. CompuServe These are the Microchip BBS and the Microchip World service allow multiple users various baud rates Wide Web (WWW) site. depending on the local point of access. Use Microchip's Bulletin Board Service (BBS) to get The following connect procedure applies in most loca- current information and help about Microchip products. tions. Microchip provides the BBS communication channel for you to use in extending your technical staff with 1. Set your modem to 8-bit, No parity, and One stop microcontroller and memory experts. (8N1). This is not the normal CompuServe setting which is 7E1. To provide you with the most responsive service possible, the Microchip systems team monitors the BBS, posts 2. Dial your local CompuServe access number. the latest component data and software tool updates, 3. Depress the <Enter> key and a garbage string will provides technical help and embedded systems appear because CompuServe is expecting a 7E1 insights, and discusses how Microchip products pro- setting. vide project solutions. 4. Type +, depress the <Enter> key and “Host Name:” The web site, like the BBS, is used by Microchip as a will appear. means to make files and information easily available to 5. Type MCHIPBBS, depress the <Enter> key and you customers. To view the site, the user must have access will be connected to the Microchip BBS. to the Internet and a web browser, such as Netscape or In the United States, to find the CompuServe phone Microsoft Explorer. Files are also available for FTP number closest to you, set your modem to 7E1 and dial download from our FTP site. (800) 848-4480 for 300-2400 baud or (800) 331-7166 Connecting to the Microchip Internet Web Site for 9600-14400 baud connection. After the system responds with “Host Name:”, type NETWORK, depress The Microchip web site is available by using your the <Enter> key and follow CompuServe's directions. favorite Internet browser to attach to: www.microchip.com For voice information (or calling from overseas), you may call (614) 723-1550 for your local CompuServe The file transfer site is available by using an FTP ser- number. vice to connect to: Microchip regularly uses the Microchip BBS to distribute ftp://ftp.futureone.com/pub/microchip technical information, application notes, source code, The web site and file transfer site provide a variety of errata sheets, bug reports, and interim patches for services. Users may download files for the latest Microchip systems software products. For each SIG, a Development Tools, Data Sheets, Application Notes, moderator monitors, scans, and approves or disap- User's Guides, Articles and Sample Programs. A vari- proves files submitted to the SIG. No executable files ety of Microchip specific business information is also are accepted from the user community in general to available, including listings of Microchip sales offices, limit the spread of computer viruses. distributors and factory representatives. Other data Systems Information and Upgrade Hot Line available for consideration is: The Systems Information and Upgrade Line provides • Latest Microchip Press Releases system users a listing of the latest versions of all of • Technical Support Section with Frequently Asked Microchip's development systems software products. Questions Plus, this line provides information on how customers • Design Tips can receive any currently available upgrade kits.The • Device Errata Hot Line Numbers are: • Job Postings 1-800-755-2345 for U.S. and most of Canada, and • Microchip Consultant Program Member Listing 1-602-786-7302 for the rest of the world. • Links to other useful web sites related to Microchip Products 970301 Connecting to the Microchip BBS Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks Connect worldwide to the Microchip BBS using either (cid:210) of Microchip Technology Incorporated in the U.S.A. and the Internet or the CompuServe communications net- other countries. FlexROM, MPLAB and fuzzyLAB, are work. trademarks and SQTP is a service mark of Microchip in Internet: the U.S.A. You can telnet or ftp to the Microchip BBS at the fuzzyTECH is a registered trademark of Inform Software Corporation. IBM, IBM PC-AT are registered trademarks address: mchipbbs.microchip.com of International Business Machines Corp. Pentium is a trademark of Intel Corporation. Windows is a trademark CompuServe Communications Network: and MS-DOS, Microsoft Windows are registered trade- When using the BBS via the Compuserve Network, marks of Microsoft Corporation. CompuServe is a regis- in most cases, a local call is your only expense. The tered trademark of CompuServe Incorporated. Microchip BBS connection does not use CompuServe All other trademarks mentioned herein are the property of membership services, therefore you do not need their respective companies. CompuServe membership to join Microchip's BBS. There is no charge for connecting to the Microchip BBS. (cid:211) 1996 Microchip Technology Inc. DS30390E-page 285

PIC16C6X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16C6X Literature Number: DS30390E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30390E-page 286 (cid:211) 1996 Microchip Technology Inc.

PIC16C7X PIC16C7X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. PART NO. -XX X /XX XXX Examples Pattern: QTP, SQTP, Code or Special Requirements a) PIC16C72 - 04/P 301 Package: JW = Windowed CERDIP Commercial Temp., PQ = MQFP (Metric PQFP) PDIP Package, 4 MHz, TQ = TQFP (Thin Quad Flatpack) normal VDD limits, QTP SO = SOIC pattern #301 SP = Skinny plastic dip P = PDIP b) PIC16LC76 - 041/SO L = PLCC Industrial Temp., SOIC SS = SSOP package, 4 MHz, Temperature - = 0(cid:176) C to +70(cid:176) C extended VDD limits Range: I = -40(cid:176) C to +85(cid:176) C c) PIC16C74A - 10E/P E = -40(cid:176) C to +125(cid:176) C Automotive Temp., Frequency 04 = 200 kHz (PIC16C7X-04) PDIP package, 10 MHz, Range: 04 = 4 MHz normal VDD limits 10 = 10 MHz 20 = 20 MHz Device PIC16C7X :VDD range 4.0V to 6.0V PIC16C7XT :VDD range 4.0V to 6.0V (Tape/Reel) PIC16LC7X :VDD range 2.5V to 6.0V PIC16LC7XT :VDD range 2.5V to 6.0V (Tape/Reel) * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices). Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. The Microchip Website at www.microchip.com 2. Your local Microchip sales office (see following page) 3. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 4. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302. DS30390E-page 287 (cid:211) 1997 Microchip Technology Inc.

Note the following details of the code protection feature on PICmicro® MCUs. (cid:127) The PICmicro family meets the specifications contained in the Microchip Data Sheet. (cid:127) Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl- edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable”. (cid:127) Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, FilterLab, ensure that your application meets with your specifications. KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, No representation or warranty is given and no liability is PICSTART, PRO MATE, SEEVAL and The Embedded Control assumed by Microchip Technology Incorporated with respect Solutions Company are registered trademarks of Microchip Tech- to the accuracy or use of such information, or infringement of nology Incorporated in the U.S.A. and other countries. patents or other intellectual property rights arising from such dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, use or otherwise. Use of Microchip’s products as critical com- In-Circuit Serial Programming, ICSP, ICEPIC, microPort, ponents in life support systems is not authorized except with Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, express written approval by Microchip. No licenses are con- MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode veyed, implicitly or otherwise, under any intellectual property and Total Endurance are trademarks of Microchip Technology rights. Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2002 Microchip Technology Inc.

M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia Microchip Technology Japan K.K. Benex S-1 6F 2355 West Chandler Blvd. Microchip Technology Australia Pty Ltd 3-18-20, Shinyokohama Chandler, AZ 85224-6199 Suite 22, 41 Rawson Street Kohoku-Ku, Yokohama-shi Tel: 480-792-7200 Fax: 480-792-7277 Epping 2121, NSW Kanagawa, 222-0033, Japan Technical Support: 480-792-7627 Australia Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Web Address: http://www.microchip.com Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Rocky Mountain China - Beijing Korea 2355 West Chandler Blvd. Microchip Technology Consulting (Shanghai) Microchip Technology Korea Chandler, AZ 85224-6199 Co., Ltd., Beijing Liaison Office 168-1, Youngbo Bldg. 3 Floor Tel: 480-792-7966 Fax: 480-792-7456 Unit 915 Samsung-Dong, Kangnam-Ku Bei Hai Wan Tai Bldg. Seoul, Korea 135-882 Atlanta No. 6 Chaoyangmen Beidajie Tel: 82-2-554-7200 Fax: 82-2-558-5934 500 Sugar Mill Road, Suite 200B Beijing, 100027, No. China Singapore Atlanta, GA 30350 Tel: 86-10-85282100 Fax: 86-10-85282104 Microchip Technology Singapore Pte Ltd. Tel: 770-640-0034 Fax: 770-640-0307 China - Chengdu 200 Middle Road Boston #07-02 Prime Centre Microchip Technology Consulting (Shanghai) 2 Lan Drive, Suite 120 Singapore, 188980 Co., Ltd., Chengdu Liaison Office Westford, MA 01886 Tel: 65-334-8870 Fax: 65-334-8850 Rm. 2401, 24th Floor, Tel: 978-692-3848 Fax: 978-692-3821 Taiwan Ming Xing Financial Tower Chicago No. 88 TIDU Street Microchip Technology Taiwan 333 Pierce Road, Suite 180 Chengdu 610016, China 11F-3, No. 207 Itasca, IL 60143 Tel: 86-28-6766200 Fax: 86-28-6766599 Tung Hua North Road Tel: 630-285-0071 Fax: 630-285-0075 China - Fuzhou Taipei, 105, Taiwan Dallas Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Microchip Technology Consulting (Shanghai) 4570 Westgrove Drive, Suite 160 Co., Ltd., Fuzhou Liaison Office Addison, TX 75001 Unit 28F, World Trade Plaza EUROPE Tel: 972-818-7423 Fax: 972-818-2924 No. 71 Wusi Road Detroit Fuzhou 350001, China Denmark Tri-Atria Office Building Tel: 86-591-7503506 Fax: 86-591-7503521 Microchip Technology Nordic ApS 32255 Northwestern Highway, Suite 190 China - Shanghai Regus Business Centre Farmington Hills, MI 48334 Microchip Technology Consulting (Shanghai) Lautrup hoj 1-3 Tel: 248-538-2250 Fax: 248-538-2260 Co., Ltd. Ballerup DK-2750 Denmark Kokomo Room 701, Bldg. B Tel: 45 4420 9895 Fax: 45 4420 9910 2767 S. Albright Road Far East International Plaza France Kokomo, Indiana 46902 No. 317 Xian Xia Road Microchip Technology SARL Tel: 765-864-8360 Fax: 765-864-8387 Shanghai, 200051 Parc d’Activite du Moulin de Massy Los Angeles Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 43 Rue du Saule Trapu 18201 Von Karman, Suite 1090 China - Shenzhen Batiment A - ler Etage Irvine, CA 92612 Microchip Technology Consulting (Shanghai) 91300 Massy, France Tel: 949-263-1888 Fax: 949-263-1338 Co., Ltd., Shenzhen Liaison Office Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 New York Rm. 1315, 13/F, Shenzhen Kerry Centre, Germany 150 Motor Parkway, Suite 202 Renminnan Lu Microchip Technology GmbH Hauppauge, NY 11788 Shenzhen 518001, China Gustav-Heinemann Ring 125 Tel: 631-273-5305 Fax: 631-273-5335 Tel: 86-755-2350361 Fax: 86-755-2366086 D-81739 Munich, Germany San Jose Hong Kong Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Microchip Technology Inc. Microchip Technology Hongkong Ltd. 2107 North First Street, Suite 590 Unit 901-6, Tower 2, Metroplaza Microchip Technology SRL San Jose, CA 95131 223 Hing Fong Road Centro Direzionale Colleoni Tel: 408-436-7950 Fax: 408-436-7955 Kwai Fong, N.T., Hong Kong Palazzo Taurus 1 V. Le Colleoni 1 Toronto Tel: 852-2401-1200 Fax: 852-2401-3431 20041 Agrate Brianza Milan, Italy 6285 Northam Drive, Suite 108 India Tel: 39-039-65791-1 Fax: 39-039-6899883 Mississauga, Ontario L4V 1X5, Canada Microchip Technology Inc. United Kingdom Tel: 905-673-0699 Fax: 905-673-6509 India Liaison Office Divyasree Chambers Arizona Microchip Technology Ltd. 505 Eskdale Road 1 Floor, Wing A (A3/A4) No. 11, O’Shaugnessey Road Winnersh Triangle Bangalore, 560 025, India Wokingham Tel: 91-80-2290061 Fax: 91-80-2290062 Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 01/18/02  2002 Microchip Technology Inc.