PIC16HV540 Enhanced PIC16C54 EPROM-Based 8-Bit CMOS Microcontroller With On-Chip Voltage Regulator High-Performance RISC CPU: Pin Configurations • Only 33 single word instructions to learn PDIP, SOIC, Windowed CERDIP (cid:127) All instructions are single cycle (200 ns) except for program branches which are two-cycle RA2 •1 18 RA1 (cid:127) Operating speed: DC - 20 MHz clock input RA3 2 17 RA0 T0CKI 3 P 16 OSC1/CLKIN DC - 200 ns instruction cycle MCLR/VPP 4 IC1 15 OSC2/CLKOUT (cid:127) 12-bit wide instructions VSS 5 6H 14 VDD RB0 6 V 13 RB7 (cid:127) 8-bit wide data path RB1 7 54 12 RB6 (cid:127) Seven special function hardware registers RB2 8 0 11 RB5 RB3 9 10 RB4 (cid:127) Four-level deep hardware stack (cid:127) Direct, indirect and relative addressing modes for data and instructions SSOP Peripheral Features: RA2 •1 20 RA1 (cid:127) 8-bit real time clock/counter (TMR0) with 8-bit pro- RA3 2 19 RA0 grammable prescaler T0CKI 3 P 18 OSC1/CLKIN (cid:127) Power-On Reset (POR) MCLR/VVPSPS 45 IC16H 1176 OVDSDC2/CLKOUT (cid:127) Brown-Out Protection VSS 6 V 15 VDD 5 RB0 7 4 14 RB7 (cid:127) Device Reset Timer (DRT) with short RC oscilla- RB1 8 0 13 RB6 tor start-up time RB2 9 12 RB5 (cid:127) Programmable Watchdog Timer (WDT) with its RB3 10 11 RB4 own on-chip RC oscillator for reliable operation (cid:127) Sleep Timer CMOS Technology: (cid:127) 8 High Voltage I/O (cid:127) 4 Regulated I/O (cid:127) Selectable on-chip 3V/5V Regulator (cid:127) Wake up from SLEEP on-pin change (cid:127) Low-power, high-speed CMOS EPROM technol- ogy (cid:127) Programmable code protection (cid:127) Fully static design (cid:127) Power saving SLEEP mode (cid:127) Wide-operating voltage range: (cid:127) Selectable oscillator options: - 3.5V to 15V - RC: Low-cost RC oscillator (cid:127) Temperature range: - XT: Standard crystal/resonator - Commercial: 0°C to 70°C - HS: High speed crystal/resonator - Industrial: -40°C to 85°C - LP: Power saving, low frequency crystal (cid:127) Low-power consumption (cid:127) Glitch filtering on MCLR and pin change inputs - < 2 mA typical @ 5V, 4 MHz - 15 µA typical @ 3V, 32 kHz - < 4.5 µA typical standby current @ 15V (with WDT disabled), 0°C to 70°C  2000 Microchip Technology Inc. Preliminary DS40197B-page 1

PIC16HV540 Table of Contents 1.0 General Description..................................................................................................................................... 3 2.0 PIC16HV540 Device Varieties..................................................................................................................... 5 3.0 Architectural Overview................................................................................................................................. 7 4.0 Memory Organization................................................................................................................................ 11 5.0 I/O Ports..................................................................................................................................................... 19 6.0 Timer0 Module and TMR0 Register........................................................................................................... 25 7.0 Special Features of the CPU..................................................................................................................... 31 8.0 Instruction Set Summary........................................................................................................................... 43 9.0 Development Support................................................................................................................................ 55 10.0 Electrical Characteristics - PIC16HV540................................................................................................... 61 11.0 DC and AC Characteristics - PIC16HV540................................................................................................ 69 12.0 Packaging Information............................................................................................................................... 73 Index........................................................................................................................................................................ 79 On-Line Support....................................................................................................................................................... 81 Reader Response.................................................................................................................................................... 82 PIC16HV540 Product Identification System............................................................................................................. 83 To Our Valued Customers Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi- sion of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: (cid:127) Microchip’s Worldwide Web site; http://www.microchip.com (cid:127) Your local Microchip sales office (see last page) (cid:127) The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: (cid:127) Fill out and mail in the reader response form in the back of this data sheet. (cid:127) E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. DS40197B-page 2 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 1.0 GENERAL DESCRIPTION use has been considered before (e.g., timer functions, replacement of “glue” logic in larger systems, copro- The PIC16HV540 from Microchip Technology is a low- cessor applications). cost, high-performance, 8-bit, fully-static, EPROM- based CMOS microcontroller. It is pin and software 1.2 Enhanced Features compatible with the PIC16C5X family of devices. It employs a RISC architecture with only 33 single word/ 1.2.1 REGULATED I/O PORTA INDEPENDENT single cycle instructions. All instructions are single OF CORE REGULATOR cycle except for program branches, which take two PORTA I/O pads and OSC2 output are powered by the cycles. The PIC16HV540 delivers performance an order of magnitude higher than its competitors in the regulated internal voltage VIO. A maximum of 10mA per output is allowed, or a total of 40mA. The core itself is same price category. The 12-bit wide instructions are powered from the independently regulated supply highly orthogonal resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy- VREG. to-use and easy-to-remember instruction set reduces 1.2.2 HIGH VOLTAGE I/O PORTB development time significantly. All eight PORTB I/Os are high voltage I/O. The inputs The PIC16HV540 is the first One-Time-Programmable (OTP) microcontroller with an on-chip 3 volt and 5 volt will tolerate input voltages as high as the VDD and out- regulator. This eliminates the need for an external reg- puts will swing from VSS to the VDD. The input threshold voltages vary with supply voltage. (See Electrical ulator in many applications powered from 9 Volt or 12 Characteristics.) Volt batteries or unregulated 6 volt, 9 volt or 12 volt mains adapters. The PIC16HV540 is ideally suited for 1.2.3 WAKE-UP ON PIN CHANGE ON PORTB applications that require very low standby current at [0:3] high voltages. These typically require expensive low current regulators. Four of the PORTB inputs latch the status of the pin at The PIC16HV540 is equipped with special features that the onset of sleep mode. A level change on the inputs reduce system cost and power requirements. The Power- resets the device, implementing wake up on pin change On Reset (POR) and Device Reset Timer (DRT) eliminate (via warm reset). The PCWUF bit in the status register the need for external reset circuitry. There are four oscilla- is reset to indicate that a pin change caused the reset tor configurations to choose from, including the power- condition. Any pin change (glitch insensitive) of the saving LP (Low Power) oscillator, cost saving RC oscilla- opposite level of the initial value wakes up the device. tor, and XT and HS for crystal oscillators. Power saving This option can be enabled/disabled in OPTION2 reg- SLEEP mode, Watchdog Timer and code protection fea- ister. (See OPTION2 Register, Register4-3.) tures improve system cost, power and reliability. 1.2.4 WAKE-UP ON PIN CHANGE WITH A The UV erasable CERDIP packaged versions are ideal SLOWLY-RISING VOLTAGE ON PORTB [7] for code development, while the cost-effective OTP ver- sions are suitable for production in any volume. The PORTB [7] also implements wake up from sleep, how- customer can take full advantage of Microchip’s price ever this input is specifically adapted so that a slowly leadership in OTP microcontrollers, while benefiting rising voltage does not cause excessive power con- from the OTP’s flexibility. sumption. This input can be used with external RC cir- cuits for long sleep periods without using the internal The PIC16HV540 is supported by a full-featured macro timer and prescaler. This option is also enabled/dis- assembler, a software simulator, an in-circuit emulator, abled in OPTION2 register. (The enable/disable bit is a low-cost development programmer, and a full fea-  shared with the other 4 wake-up inputs.) The PCWUF tured programmer. All the tools are supported on IBM bit in the status register is also shared with the other PC and compatible machines. four wake-up inputs. 1.1 Applications 1.2.5 LOW-VOLTAGE (BROWN-OUT) The PIC16HV540 fits in low-power battery applications DETECTION such as CO and smoke detection, toys, games, secu- A low voltage (Brown-out) detect circuit optionally rity systems and automobile modules. The EPROM resets the device at a voltage level higher than that at technology makes customizing of application programs which the PICmicro® device stops operating. The nom- (transmitter codes, receiver frequencies, etc.) inal trip voltages are 3.1 volts (for 5 volt operation) and extremely fast and convenient. The small footprint 2.2 volt (for 3 volt operation), respectively. The core package, for through hole or surface mounting, make remains in the reset state as long as this condition this microcontroller suitable for applications with space holds (as if a MCLR external reset was given). The limitations. Low-cost, low-power, high-performance, Brown-out trip level is user selectable, with built-in inter- ease of use and I/O flexibility make the PIC16HV540 locks. The Brown-out detector is disabled at power-up very versatile even in areas where no microcontroller and is activated by clearing the appropriate bit (BODEN) in OPTION2 register.  2000 Microchip Technology Inc. Preliminary DS40197B-page 3

PIC16HV540 1.2.6 INCREASED STACK DEPTH TABLE 1-1: PIC16HV540 DEVICE PIC16HV540 The stack depth is 4 levels to allow modular program implementation by using functions and subroutines. Clock Maximum Frequency (MHz) 20 Memory EPROM Program Memory 512 1.2.7 ENHANCED WATCHDOG TIMER (WDT) RAM Data Memory (bytes) 25 OPERATION Peripherals Timer Module(s) TMR0 The WDT is enabled by setting FUSE 2 in the configuration Packages I/O Pins 12 word. The WDT setting is latched and the fuse disabled Voltage Range (Volts) 3.5V-15V during SLEEP mode to reduce current consumption. Number of Instructions 33 If the WDT is disabled by FUSE 2, it can be enabled/dis- Packages 18-pin DIP abled under program control using bit 4 in OPTION2 Reg- SOIC ister (SWDTEN). The software WDT control is disabled at 20-pin SSOP power-up.  All PICmicro devices have Power-on Reset, selectable The current consumption of the on-chip oscillator (used WDT, selectable code protect and high I/O current capability. for the watchdog, oscillator startup timer and sleep timer) is less than 1µA (typical) at 3 Volt operation. 1.2.8 REDUCED EXTERNAL RC OSCILLATOR STARTUP TIME If the RC oscillator option is selected in the Configura- tion word (FOSC1=1 and FOSCO=1), the oscillator startup time is 1.0 ms nominal instead of 18 ms nomi- nal. This is applicable after power-up (POR), either WDT interrupt or wake-up, external reset on MCLR, PCWU (wake on pin change) and Brown-out. 1.2.9 LOW-VOLTAGE OPERATION OF THE ENTIRE CPU DURING SLEEP The voltage regulator can automatically lower the volt- age to the core from 5 Volt to 3 Volt during sleep, result- ing in reduced current consumption. This is an option bit (SL) in the OPTION2 register. 1.2.10 GLITCH FILTERS ON WAKE-UP PINS AND MCLR Glitch sensitive inputs for wake-up on pin change are filtered to reduce susceptibility to interference. A similar filter reduces false reset on MCLR. 1.2.11 PROGRAMMABLE CLOCK GENERATOR When used in RC mode, the CLKOUT pin can be used as a programmable clock output. The output is con- nected to TMR0, bit 0 and by setting the prescaler, clock out frequencies of CLKIN/8 to CLKIN/1024 can be generated. The CLKOUT pin can also be used as a general purpose output by modifying TMR0, bit 0. DS40197B-page 4 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 2.0 PIC16HV540 DEVICE 2.3 Quick-Turnaround-Production (QTP) VARIETIES Devices A variety of frequency ranges and packaging options Microchip offers a QTP Programming Service for fac- are available. Depending on application and tory production orders. This service is made available production requirements, the proper device option can for users who choose not to program a medium to high be selected using the information in this section. When quantity of units and whose code patterns have stabi- placing orders, please use the PIC16HV540 Product lized. The devices are identical to the OTP devices but Identification System at the back of this data sheet to with all EPROM locations and configuration bit options specify the correct part number. already programmed by the factory. Certain code and prototype verification procedures apply before produc- For the PIC16HV540 family of devices, there is one tion shipments are available. (Please contact your device type, as indicated in the device number: Microchip Technology sales office for more details.) 1. HV, as in PIC16HV540. These devices have EPROM program memory and operate over the 2.4 Serialized Quick-Turnaround- standard voltage range of 3.5 to 15 volts. Production (SQTP) Devices 2.1 UV Erasable Devices Microchip offers the unique programming service where a few user-defined locations in each device are The UV erasable versions, offered in CERDIP pack- programmed with different serial numbers. The serial ages, are optimal for prototype development and pilot numbers may be random, pseudo-random or sequen- programs. tial. UV erasable devices can be programmed for any of the Serial programming allows each device to have a  four oscillator configurations. Microchip’s PICSTART unique number which can serve as an entry code,  and PRO MATE programmers both support program- password or ID number. (Please contact your Microchip ming of the PIC16HV540. Third party programmers Technology sales office for more details.) also are available; refer to Literature Number DS00104 for a list of sources. 2.2 One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers expecting frequent code changes and updates. The OTP devices, packaged in plastic packages, per- mit the user to program them once. In addition to the program memory, the configuration bits must be pro- grammed.  2000 Microchip Technology Inc. Preliminary DS40197B-page 5

PIC16HV540 NOTES: DS40197B-page 6 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 3.0 ARCHITECTURAL OVERVIEW The PIC16HV540 device contains an 8-bit ALU and working register. The ALU is a general purpose arith- The high performance of the PIC16HV540 can be metic unit. It performs arithmetic and Boolean functions attributed to a number of architectural features com- between data in the working register and any register monly found in RISC microprocessors. To begin with, file. the PIC16HV540 uses a Harvard architecture in which program and data are accessed on separate buses. The ALU is 8-bits wide and capable of addition, sub- This improves bandwidth over traditional von Neumann traction, shift and logical operations. Unless otherwise architecture where program and data are fetched on mentioned, arithmetic operations are two's comple- the same bus. Separating program and data memory ment in nature. In two-operand instructions, typically further allows instructions to be sized differently than one operand is the W (working) register. The other the 8-bit wide data word. Instruction opcodes are 12- operand is either a file register or an immediate con- bits wide making it possible to have all single word stant. In single operand instructions, the operand is instructions. A 12-bit wide program memory access either the W register or a file register. bus fetches a 12-bit instruction in a single cycle. A two- The W register is an 8-bit working register used for ALU stage pipeline overlaps fetch and execution of instruc- operations. It is not an addressable register. tions. Consequently, all instructions (33) execute in a Depending on the instruction executed, the ALU may single cycle (200ns @ 20MHz) except for program affect the values of the Carry (C), Digit Carry (DC), branches. and Zero (Z) bits in the STATUS register. The C and The PIC16HV540 address 512x12 of program mem- DC bits operate as a borrow and digit borrow out bit, ory. All program memory is internal. respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. The PIC16HV540 can directly or indirectly address its register files and data memory. All special function reg- A simplified block diagram is shown in Figure3-1, with isters including the program counter are mapped in the the corresponding device pins described in Table3-1. data memory. The PIC16HV540 has a highly orthogo- nal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16HV540 simple yet efficient. In addition, the learn- ing curve is reduced significantly.  2000 Microchip Technology Inc. Preliminary DS40197B-page 7

PIC16HV540 FIGURE 3-1: PIC16HV540 BLOCK DIAGRAM VDD 3V/5V Regulator VREG RB7 4 RB<3:0> FILTER BOD RL/SL PC BODL/BODEN SWDTEN (OPTION2 REGISTER) PCWU (PIN CHANGE) 9-11 9-11 STACK 1 T0CKI CONFIGURATION WORD OSC1OSC2MCLR EPROM PIN 512 X 12 STACK 2 “DISABLE” “OSC PC STACK 3 SELECT” 12 STACK 4 WATCHDOG 2 TIMER “CODE PROTECT” OSCILLATOR/ INSTRUCTION TIMING & REGISTER CONTROL WDT CLKOUT 9 TIME WDT/TMR0 12 OUT PRESCALER 8 “SLEEP” INSTRUCTION 6 6 DECODER OPTION2 OPTION REG “OPTION” DIRECT ADDRESS “TRIS 7” FROM W FROM W GENERAL 5 PURPOSE DIRECT RAM REGISTER 8 ADDRESS 5-7 FILE (SRAM) 25 Bytes LS STATUS A ER TMR0 FSR T LI 8 DATA BUS W ALU 8 FROM W FROM W 4 8 4 8 “TRIS 6” “TRIS 5” TRISA PORTA TRISB PORTB RL/SL 4 8 VIO 3V/5V RA<3:0> HIGH VOLTAGE Regulator TRANSLATION 8 RB<7:0> DS40197B-page 8 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 TABLE 3-1: PINOUT DESCRIPTION - PIC16HV540 DIP, SOIC SSOP I/O/P Input Name Description No. No. Type Levels RA0 17 19 I/O TTL Independently regulated Bi-directional I/O port — VIO RA1 18 20 I/O TTL RA2 1 1 I/O TTL RA3 2 2 I/O TTL RB0 6 7 I/O TTL High-voltage Bi-directional I/O port. Wake-up on pin RB1 7 8 I/O TTL Sourced from VDD. change RB2 8 9 I/O TTL RB3 9 10 I/O TTL RB4 10 11 I/O TTL RB5 11 12 I/O TTL RB6 12 13 I/O TTL RB7 13 14 I/O TTL Wake-up on SLOW rising pin change. T0CKI 3 3 I ST Clock input to Timer 0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. MCLR/VPP 4 4 I ST Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. Voltage on the MCLR/ VPP pin must not exceed VDD(1) to avoid unintended entering of programming mode. OSC1/CLKIN 16 18 I ST Oscillator crystal input/external clock source input. OSC2/CLKOUT 15 17 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2/CLKOUT output is connected to TMR0, bit 0. Frequencies of CLKIN/8 to CLKIN/1024 can be generated on this pin. VDD 14 15,16 P — Positive supply. VSS 5 5,6 P — Ground reference. Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input. Note 1: VDD during programming mode can not exceed parameter PD1 called out in the PIC16C5X Programming Specification (Literature number DS30190).  2000 Microchip Technology Inc. Preliminary DS40197B-page 9

PIC16HV540 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining The clock input (OSC1/CLKIN pin) is internally divided An Instruction Cycle consists of four Q cycles (Q1, Q2, by four to generate four non-overlapping quadrature Q3 and Q4). The instruction fetch and execute are clocks namely Q1, Q2, Q3 and Q4. Internally, the pro- pipelined such that fetch takes one instruction cycle gram counter is incremented every Q1, and the instruc- while decode and execute takes another instruction tion is fetched from program memory and latched into cycle. However, due to the pipelining, each instruction instruction register in Q4. It is decoded and executed effectively executes in one cycle. If an instruction during the following Q1 through Q4. The clocks and causes the program counter to change (e.g., GOTO) instruction execution flow is shown in Figure3-2 and then two cycles are required to complete the instruction Example3-1. (Example3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Q3 phase clock Q4 PC PC PC+1 PC+2 OSC2/CLKOUT CLKIN/8(1) (RC mode) Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) Note 1: Frequencies of CLKIN8 to CLKIN/1024 are possible. EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 55H Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS40197B-page 10 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 4.0 MEMORY ORGANIZATION 4.2.1 GENERAL PURPOSE REGISTER FILE PIC16HV540 memory is organized into program mem- The register file is accessed either directly or indirectly ory and data memory. For devices with more than 512 through the file select register FSR (Section4.8). bytes of program memory, a paging scheme is used. Program memory pages are accessed using one or two FIGURE 4-2: PIC16HV540 REGISTER FILE STATUS register bits. For devices with a data memory MAP register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed File Address using the File Selection Register (FSR). 00h INDF(1) 4.1 Program Memory Organization 01h TMR0 The PIC16HV540 has a 9-bit Program Counter (PC) 02h PCL capable of addressing a 512 x 12 program memory 03h STATUS space (Figure4-1). Accessing a location above the 04h FSR physically implemented address will cause a wrap- 05h PORTA around. 06h PORTB The reset vector for the PIC16HV540 is at 1FFh. A 07h NOP at the reset vector location will cause a restart at location 000h. 08h FIGURE 4-1: PIC16HV540 PROGRAM MEMORY MAP AND STACK 0Fh General Purpose 10h Registers PC<8:0> 9 CALL, RETLW Stack Level 1 Stack Level 2 1Fh Stack Level 3 Stack Level 4 Note 1: Not a physical register. 000h y emorce POrno-gcrhaimp 0FFh 4.2.2 SPECIAL FUNCTION REGISTERS er MSpa Memory 100h The Special Function Registers are registers used by Us the CPU and peripheral functions to control the opera- tion of the device (Table4-1). Reset Vector 1FFh The special registers can be classified into two sets. The special function registers associated with the 4.2 Data Memory Organization “core” functions are described in this section. Those related to the operation of the peripheral features are Data memory is composed of registers, or bytes of described in the section for each peripheral feature. RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers. The special function registers include the TMR0 regis- ter, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options. The general purpose registers are used for data and control information under command of the instructions. For the PIC16HV540, the register file is composed of 10 special function registers and 25 general purpose registers (Figure4-2).  2000 Microchip Technology Inc. Preliminary DS40197B-page 11

PIC16HV540 TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY Value on Value on Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On MCLR and Wake-up on Brown-Out Reset WDT Reset Pin Change Reset N/A TRIS I/O control registers (TRISA, TRISB) 1111 1111 1111 1111 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler --11 1111 --11 1111 --11 1111 --11 1111 N/A OPTION2 Contains control bits to configure pin changes, software enabled --11 1111 --uu uuuu --uu uuuu --xx xxxx WDT, regulation and brown-out 00h INDF Uses contents of FSR to address data memory (not a physical regis- xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx ter) 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx 02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111 1111 1111 1111 1111 03h STATUS PCWUF PA1 PA0 TO PD Z DC C 1001 1xxx 100q quuu 000u uuuu x00x xxxx 04h FSR Indirect data memory address pointer 111x xxxx 111u uuuu 111u uuuu 111x xxxx 05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu ---- uuuu ---- xxxx 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx Legend: Shaded boxes = unimplemented or unused, – = unimplemented, read as ’0’ (if applicable) x = unknown, u = unchanged, q = value depends on condition. Note 1: The upper byte of the Program Counter is not directly accessible. See Section4.6 of the PIC16HV540 data sheet (DS40197B) for an expla- nation of how to access these bits. DS40197B-page 12 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 4.3 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register This register contains the arithmetic status of the ALU, as 000u u1uu (where u = unchanged). the RESET status, and the page preselect bits for pro- It is recommended, therefore, that only BCF, BSF and gram memories larger than 512 words. MOVWF instructions be used to alter the STATUS regis- The STATUS register can be the destination for any ter because these instructions do not affect the Z, DC instruction, as with any other register. If the STATUS or C bits from the STATUS register. For other instruc- register is the destination for an instruction that affects tions, which do affect STATUS bits, see Section8.0, the Z, DC or C bits, then the write to these three bits is Instruction Set Summary. disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable while the PCWUF bit is a read/write bit. There- fore, the result of an instruction with the STATUS regis- ter as destination may be different than intended. REGISTER 4-1: STATUS REGISTER (ADDRESS:03h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x PCWUF PA1 PA0 TO PD Z DC C R = Readable bit bit7 bit0 W = Writable bit - n = Value at POR reset bit 7: PCWUF: Pin Change Reset bit 1 = After Power-up Reset (POR) or SLEEP command 0 = After a wake-up on pin change event bit 6-5: Not Applicable bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF RRF or RLF 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred  2000 Microchip Technology Inc. Preliminary DS40197B-page 13

PIC16HV540 4.4 OPTION Register By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION regis- The OPTION register is a 6-bit wide, write-only register ter. A RESET sets the OPTION<5:0> bits. which contains various control bits to configure the Example4-1 illustrates how to initialize the OPTION Timer0/WDT prescaler and Timer0. register. EXAMPLE 4-1: INSTRUCTIONS FOR INITIALIZING OPTION REGISTER movlw ‘0000 0111’b ; load OPTION setup value into W OPTION ; initialize OPTION register REGISTER 4-2: OPTION REGISTER U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1 — — T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit bit7 0 U = Unimplemented bit - n = Value at POR reset bit 7-6: Unimplemented bit 5: T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0: PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 DS40197B-page 14 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 4.5 OPTION2 Register The OPTION2 register is a 6-bit wide, write-only regis- ter which contains various control bits to configure the added features on the PIC16HV540. A Power-on Reset sets the OPTION2<5:0> bits. Example4-2 illustrates how to initialize the OPTION2 register. Note: All Power-on Resets will disable the Brown-out Detect circuit. All subsequent resets will not disable the Brown-out Detect if enabled. EXAMPLE 4-2: INSTRUCTIONS FOR INITIALIZING OPTION2 REGISTER movlw ‘0001 0111’b ; load OPTION2 setup value into W tris 0x07 ; initialize OPTION2 register REGISTER 4-3: OPTION2 REGISTER (TRIS 07H) U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1 — — PCWU SWDTEN RL SL BODL BODEN W = Writable bit bit7 0 U = Unimplemented bit - n = Value at POR reset bit 7-6: Unimplemented bit 5: PCWU: Wake-up on Pin Change 1 = Disabled 0 = Enabled bit 4: SWDTEN: Software Controlled WDT Enable bit 1 = WDT is turned off it the WDTEN configuration bit = 0 0 = WDT is on if the WDTEN configuration bit = 0; if WDTEN bit = 1, then SWDTEN is ‘don’t care’ bit 3: RL: Regulated Voltage Level Select bit 1 = 5 volt 0 = 3 volt bit 2: SL: Sleep Voltage Level Select bit 1 = RL bit setting 0 = 3 volt bit 1: BODL: Brown-out Voltage Level Select bit 1 = RL bit setting, but SL during SLEEP 0 = 3 volt bit 0: BODEN: Brown-out Enabled 1 = Disabled 0 = Enabled  2000 Microchip Technology Inc. Preliminary DS40197B-page 15

PIC16HV540 4.6 Program Counter 4.6.1 EFFECTS OF RESET As a program instruction is executed, the Program The Program Counter is set upon a RESET, which Counter (PC) will contain the address of the next pro- means that the PC addresses the last location in the gram instruction to be executed. The PC value is last page i.e., the reset vector. increased by one every instruction cycle, unless an The STATUS register page preselect bits are cleared instruction changes the PC. upon a RESET, which means that page 0 is pre- For a GOTO instruction, bits 8:0 of the PC are provided selected. by the GOTO instruction word. (Figure4-3). Therefore, upon a RESET, a GOTO instruction at the For a CALL instruction, or any instruction where the reset vector location will automatically cause the pro- PCL is the destination, bits 7:0 of the PC again are pro- gram to jump to page0. vided by the instruction word. However, PC<8> does 4.7 Stack not come from the instruction word, but is always cleared (Figure4-3). PIC16HV540 device has a 12-bit wide L.I.F.O. (last in, Instructions where the PCL is the destination, or Modify first out) hardware 4 level stack. PCL instructions, include MOVWF PC, ADDWF PC, and A CALL instruction will push the current value of stack BSF PC, 5. . 1 into stack 2 and then push the current program Note: Because PC<8> is cleared in the CALL counter value, incremented by one, into stack level 1. If instruction, or any Modify PCL instruction, more than four sequential CALL’s are executed, only all subroutine calls or computed jumps are the most recent four return addresses are stored. limited to the first 256 locations of any pro- A RETLW instruction will pop the contents of stack level gram memory page (512 words long). 1 into the program counter and then copy stack level 2 contents into level 1. If more than four sequential FIGURE 4-3: LOADING OF PC RETLW’s are executed, the stack will be filled with the BRANCH INSTRUCTIONS - address previously stored in level 4. Note that the PIC16HV540 Wregister will be loaded with the literal value specified in the instruction. This is particularly useful for the GOTO Instruction implementation of data look-up tables within the 11 10 9 8 7 0 program memory. PC X X X PCL Upon any reset, the contents of the stack remain unchanged, however the program counter (PCL) will also be reset to 0. Instruction Word X - Not used Note 1: There are no STATUS bits to indicate stack overflows or stack underflow condi- tions. CALL or Modify PCL Instruction Note 2: There are no instructions mnemonics 11 10 9 8 7 0 called PUSH or POP. These are actions PC X X X PCL that occur from the execution of the CALL and RETLW instructions. Reset to ’0’ Instruction Word X - Not used DS40197B-page 16 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 4.8 Indirect Data Addressing; INDF and EXAMPLE 4-4: HOW TO CLEAR RAM FSR Registers USING INDIRECT ADDRESSING The INDF register is not a physical register. Addressing movlw 0x10 ;initialize pointer INDF actually addresses the register whose address is movwf FSR ; to RAM contained in the FSR register (FSR is a pointer). This is NEXT clrf INDF ;clear INDF register indirect addressing. incf FSR,F ;inc pointer btfsc FSR,4 ;all done? EXAMPLE 4-3: INDIRECT ADDRESSING goto NEXT ;NO, clear next CONTINUE (cid:127) Register file 05 contains the value 10h : ;YES, continue (cid:127) Register file 06 contains the value 0Ah The FSR is a 5-bit (PIC16HV540) wide register. It is (cid:127) Load the value 05 into the FSR register used in conjunction with the INDF register to indirectly (cid:127) A read of the INDF register will return the value address the data memory area. of10h The FSR<4:0> bits are used to select data memory (cid:127) Increment the value of the FSR register by one addresses 00h to 1Fh. (FSR = 06) PIC16HV540: Do not use banking. FSR<6:5> are (cid:127) A read of the INDR register now will return the unimplemented and read as'1's. value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example4-4. FIGURE 4-4: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing (FSR) 6 5 4 (opcode) 0 6 5 4 (FSR) 0 (Note 1) (Note 1) location select location select 00h Data 0Fh Memory(2) 10h 1Fh Bank 0 Note 1: Bits 5 and 6 are unimplemented and read as 1’s. 2: For register map detail, see Section4.2.  2000 Microchip Technology Inc. Preliminary DS40197B-page 17

PIC16HV540 NOTES: DS40197B-page 18 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 5.0 I/O PORTS 5.3 TRIS Registers As with any other register, the I/O registers can be writ- The output driver control registers are loaded with the ten and read under program control. However, read contents of the W register by executing the TRIS f instructions (e.g., MOVF PORTB,W) always read the I/O instruction. A '1' from a TRIS register bit puts the corre- pins independent of the pin’s input/output modes. On sponding output driver in a hi-impedance mode. A '0' RESET, all I/O ports are defined as input (inputs are at puts the contents of the output data latch on the hi-impedance) since the I/O control registers (TRISA, selected pins, enabling the output buffer. TRISB) are all set. Note: A read of the ports reads the pins, not the 5.1 PORTA output data latches. That is, if an output driver on a pin is enabled and driven high, PORTA is a 4-bit I/O register. Only the low order 4 bits but the external system is holding it low, a are used (RA3:RA0). Bits 7-4 are unimplemented and read of the port will indicate that the pin is read as '0's. The inputs will tolerate input voltages as low. high as VIO and outputs will swing from VSS to VIO. The The TRIS registers are “write-only” and are set (output internal voltage regulator VIO powers PORTA I/O pads. drivers disabled) upon RESET. The internal regulator output, VIO, is switchable between 3Vdc and 5Vdc, via the (RL) bit in the 5.4 I/O Interfacing OPTION2 register. The equivalent circuit for the PORTA and PORTB I/O 5.2 PORTB pins are shown in Figure5-1 through Figure5-4. All ports may be used for both input and output operation. PORTB is an 8-bit I/O register (PORTB<7:0>). All 8 For input operations, these ports are non-latching. Any PORTB I/Os are high voltage I/O. The inputs will toler- input must be present until read by an input instruction ate input voltages as high as VDD and outputs will swing (e.g., MOVF PORTB, W). The outputs are latched and from VSS to VDD. In addition, 5 of the PORTB pins can remain unchanged until the output latch is rewritten. To be configured for the wake-up on change feature. Pins use a port pin as output, the corresponding direction RB0, RB1, RB2 and RB3 latch the state of the pin at the control bit (in TRISA, TRISB) must be cleared (= 0). For onset of sleep mode. (No “dummy” read of the PORTB use as an input, the corresponding TRIS bit must be pins is required prior to executing the SLEEP instruc- set. Any I/O pin can be programmed individually as tion.) A level change on the input resets the device, input or output. implementing wake-up on pin change. The PCWUF bit in the status register is cleared to indicate that a pin change caused the reset. This feature can be enabled/ disabled in the OPTION2 register. PORTB pin RB7 also exhibits this wake-up on pin high feature but is specially adapted for a slow-rising input signal. This special feature prevents excessive power consumption when desiring long sleep periods without using the watchdog timer and prescaler. PCWUF bit in the status register is cleared to indicate that a pin change caused the reset. This feature can be enabled/ disabled in the OPTION2 register. Only pins configured as inputs can cause this wake-up on pin change to occur. To prevent false wake-up on pin change events on pins RB<0:3>, the pin state must be driven to a logic 1 or logic 0 and not left floating during the “SLEEP” state. For pin RB7, the pin state must be driven to logic 0 and allowed to ramp to a logic 1 for correct operation.  2000 Microchip Technology Inc. Preliminary DS40197B-page 19

PIC16HV540 FIGURE 5-1: BLOCK DIAGRAM OF PORTA<0:3> PINS DATA BUS D Q Data VIO WR Latch VIO PORTA CK Q P W N RA0-RA3 REG pins D Q TRIS TRIS Latch PORTA VSS VSS CK Q Reset RD PORTA FIGURE 5-2: BLOCK DIAGRAM OF PORTB<0:3> PINS DATA BUS D Q VDD Data WR Latch VDD PORTB CK Q Step-up VDD P Circuit W REG D Q TRIS RB0-RB3 TRIS Latch pins PORTB N CK Q VSS RD PORTB VSS Step-down Q D Circuit Q CK “SLEEP” RD PORTB M WAKE-UP ON U PIN CHANGE X DS40197B-page 20 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 FIGURE 5-3: BLOCK DIAGRAM OF PORTB<4:6> PINS DATA BUS D Q VDD Data WR Latch VDD PORTB CK Q Step-up VDD P Circuit W REG D Q TRIS RB4-RB6 TRIS Latch pins PORTB N CK Q VSS RD PORTB VSS Step-down Circuit FIGURE 5-4: BLOCK DIAGRAM OF PORTB<7> PIN DATA BUS D Q VDD Data WR Latch VDD PORTB CK Q Step-up VDD P Circuit W REG D Q TRIS RB7 pin TRIS Latch PORTB N CK Q VSS RD PORTB VSS Step-down Circuit VDD P WAKE-UP ON PIN CHANGE  2000 Microchip Technology Inc. Preliminary DS40197B-page 21

PIC16HV540 TABLE 5-1: SUMMARY OF PORT REGISTERS Value on Value on Value on Value on Power-On MCLR and Wake-up on Brown-Out Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset WDT Reset Pin Change Reset N/A TRIS I/O control registers (TRISA, TRISB) 1111 1111 1111 1111 1111 1111 1111 1111 05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu ---- uuuu ---- xxxx 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx 03h STATUS PCWUF PA1 PA0 TO PD Z DC C 100x xxxx 100q quuu 000u uuuu x00x xxxx N/A OPTION2 — — PCWU SWDTEN RL SL BODL BODEN --11 1111 --uu uuuu --uu uuuu --xx xxxx Legend: Shaded boxes = unimplemented, read as ‘0’, —= unimplemented, read as '0', x = unknown, u = unchanged. 5.5 I/O Programming Considerations EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN 5.5.1 BI-DIRECTIONAL I/O PORTS I/O PORT ;Initial PORT Settings Some instructions operate internally as read followed ; PORTB<7:4> Inputs by write operations. The BCF and BSF instructions, for ; PORTB<3:0> Outputs example, read the entire port into the CPU, execute the ;PORTB<7:6> have external pull-ups and are bit operation and re-write the result. Caution must be ;not connected to other circuitry used when these instructions are applied to a port ; where one or more pins are used as input/outputs. For ; PORT latch PORT pins example, a BSF operation on bit5 of PORTB will cause ; ---------- ---------- all eight bits of PORTB to be read into the CPU, bit5 to BCF PORTB, 7 ;01pp pppp 11pp pppp be set and the PORTB value to be written to the output BCF PORTB, 6 ;10pp pppp 11pp pppp latches. If another bit of PORTB is used as a bi-direc- MOVLW 03Fh ; TRIS PORTB ;10pp pppp 10pp pppp tional I/O pin (say bit0) and it is defined as an input at ; this time, the input signal present on the pin itself would ;Note that the user may have expected the pin be read into the CPU and rewritten to the data latch of ;values to be 00pp pppp. The 2nd BCF caused this particular pin, overwriting the previous content. As ;RB7 to be latched as the pin value (High). long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode 5.5.2 SUCCESSIVE OPERATIONS ON I/O later on, the content of the data latch may now be PORTS unknown. The actual write to an I/O port happens at the end of an Example5-1 shows the effect of two sequential read- instruction cycle, whereas for reading, the data must be modify-write instructions (e.g., BCF, BSF, etc.) on an I/ valid at the beginning of the instruction cycle O port. (Figure5-5). Therefore, care must be exercised if a A pin actively outputting a high or a low should not be write followed by a read operation is carried out on the driven from external devices at the same time in order same I/O port. The sequence of instructions should to change the level on this pin (“wired-or”, “wired-and”). allow the pin voltage to stabilize (load dependent) The resulting high output currents may damage the before the next instruction, which causes that file to be chip. read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. DS40197B-page 22 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 FIGURE 5-5: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 PC + 2 PC + 3 Instruction fetched MOVWF PORTB MOVF PORTB,W NOP NOP This example shows a write to PORTB followed by a read RB7:RB0 from PORTB. Port pin Port pin written here sampled here Instruction executed MOVWF PORTB MOVF PORTB,W NOP (Write to (Read PORTB) PORTB)  2000 Microchip Technology Inc. Preliminary DS40197B-page 23

PIC16HV540 NOTES: DS40197B-page 24 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 6.0 TIMER0 MODULE AND TMR0 Counter mode is selected by setting the T0CS bit REGISTER (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The The Timer0 module has the following features: incrementing edge is determined by the source edge (cid:127) 8-bit timer/counter register, TMR0 select bit T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external - Readable and writable clock input are discussed in detail in Section6.1. (cid:127) 8-bit software programmable prescaler The prescaler may be used by either the Timer0 mod- (cid:127) Internal or external clock select ule or the Watchdog Timer, but not both. The prescaler - Edge select for external clock assignment is controlled in software by the control bit Figure6-1 is a simplified block diagram of the Timer0 PSA (OPTION<3>). Clearing the PSA bit will assign the module, while Figure6-2 shows the electrical structure prescaler to Timer0. The prescaler is not readable or of the Timer0 input. writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are select- Timer mode is selected by clearing the T0CS bit able. Section6.2 details the operation of the prescaler. (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If A summary of registers associated with the Timer0 TMR0 register is written, the increment is inhibited for module is found in Table6-1. the following two cycles (Figure6-3 and Figure6-4). The user can work around this by writing an adjusted value to the TMR0 register. FIGURE 6-1: TIMER0 BLOCK DIAGRAM Data bus FOSC/4 0 PSout 8 1 Sync with 1 Internal 0 TMR0 reg 7 Clocks T0CKI Programmable 0 PSout pin Prescaler(2) T0SE(1) (2 cycle delay) Sync 3 PS2, PS1, PS0(1) PSA(1) T0CS(1) OSC2/ M CLKOUT U Internal Oscillator X Drive Circuit “SLEEP” Oscillator Mode Select(3) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure6-6). 3: Bit 0 of TMR0 will be output on OSC2/CLKOUT pin when RC oscillator mode is selected.  2000 Microchip Technology Inc. Preliminary DS40197B-page 25

PIC16HV540 FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN RIN T0CKI (1) Schmitt Trigger pin (1) N Input Buffer VSS VSS Note 1: ESD protection circuits. FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W Fetch Timer0 T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 FIGURE 6-4: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W Fetch Timer0 T0 T0+1 NT0 NT0+1 T0 Instruction Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Value on Value on Power-On MCLR and Wake-up on Brown-out Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset WDT Reset Pin Change Reset 01h TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx N/A OPTION — — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111 --11 1111 --11 1111 Legend: Shaded cells: Unimplemented bits, - = unimplemented, x = unknown, u = unchanged. DS40197B-page 26 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 6.1 Using Timer0 with an External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type pres- When an external clock input is used for Timer0, it must caler so that the prescaler output is symmetrical. For meet certain requirements. The external clock require- the external clock to meet the sampling requirement, ment is due to internal phase clock (TOSC) synchroniza- the ripple counter must be taken into account. There- tion. Also, there is a delay in the actual incrementing of fore, it is necessary for T0CKI to have a period of at Timer0 after synchronization. least 4TOSC (and a small RC delay of 40ns) divided by the prescaler value. The only requirement on T0CKI 6.1.1 EXTERNAL CLOCK SYNCHRONIZATION high and low time is that they do not violate the mini- mum pulse width requirement of 10 ns. Refer to param- When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization eters 40, 41 and 42 in the electrical specification of the desired device. of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and 6.1.2 TIMER0 INCREMENT DELAY Q4 cycles of the internal phase clocks (Figure6-5). Therefore, it is necessary for T0CKI to be high for at Since the prescaler output is synchronized with the least 2TOSC (and a small RC delay of 20ns) and low for internal clocks, there is a small delay from the time the at least 2TOSC (and a small RC delay of 20ns). Refer external clock edge occurs to the time the Timer0 mod- to the electrical specification of the desired device. ule is actually incremented. Figure6-5 shows the delay from the external clock edge to the timer incrementing. FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Small pulse Prescaler Output (2) misses sampling (1) External Clock/Prescaler (3) Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.  2000 Microchip Technology Inc. Preliminary DS40197B-page 27

PIC16HV540 6.2 Prescaler EXAMPLE 6-2: CHANGING PRESCALER (WDT→TIMER0) An 8-bit counter is available as a prescaler for the CLRWDT ;Clear WDT and Timer0 module, or as a postscaler for the Watchdog ;prescaler Timer (WDT) (WDT postscaler not implemented on MOVLW ’xxxx0xxx’ ;Select TMR0, new PIC16C52), respectively (Section6.1.2). For simplicity, ;prescale value and this counter is being referred to as “prescaler” through- ;clock source out this data sheet. Note that the prescaler may be OPTION used by either the Timer0 module or the WDT, but not 6.3 Programmable Clock Generator both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, When the PIC16HV540 is programmed to operate in and vice-versa. the RC oscillator mode, the CLKOUT pin is connected The PSA and PS2:PS0 bits (OPTION<3:0>) determine to the compliment state of TMR0<0>. Use of the pres- prescaler assignment and prescale ratio. caler rate select bits PSA:PS0 in the OPTION register will provide for frequencies of CLKIN/8 to CLKIN/1024 When assigned to the Timer0 module, all instructions on the CLKOUT pin. writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear EXAMPLE 6-3: the prescaler along with the WDT. The prescaler is nei- PRESCALER SETTING/CLKOUT FREQUENCY ther readable nor writable. On a RESET, the prescaler Fosc contains all '0's. CLKIN/1024 CLKIN/8 1Mhz 976 Hz 125 kHz 6.2.1 SWITCHING PRESCALER ASSIGNMENT 2Mhz 1953 Hz 250 kHz The prescaler assignment is fully under software con- 3Mhz 2930 Hz 375 kHz trol (i.e., it can be changed “on the fly” during program 4Mhz 3906 Hz 500 kHz execution). To avoid an unintended device RESET, the In addition to this mode of operation, TMR0<0> can be following instruction sequence (Example6-1) must be toggled via the bcf and bsf bit type instructions. For this executed when changing the prescaler assignment mode, the T0CS bit in the OPTION register must be set from Timer0 to the WDT. to 1. This setting configures TMR0 to increment on the T0CKI pin. To set the CLKOUT pin high, a bcf TMR0,0 EXAMPLE 6-1: CHANGING PRESCALER instruction is used and to set the CLKOUT pin low, the (TIMER0→WDT) bsf TMR0,0 instruction is used. The T0CKI pin should 1. CLRWDT ;Clear WDT be pulled high or low to prevent false state changes on 2. CLRF TMR0 ;Clear TMR0 & Prescaler 3. MOVLW '00xx1111’b ;These 3 lines (5, 6, 7) the CLKOUT pin. 4. OPTION ; are required only if ; desired 5. CLRWDT ;PS<2:0> are 000 or 001 6. MOVLW '00xx1xxx’b ;Set Postscaler to 7. OPTION ; desired WDT rate To change prescaler from the WDT to the Timer0 mod- ule, use the sequence shown in Example6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switch- ing the prescaler. DS40197B-page 28 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY ( = Fosc/4) Data Bus 0 8 M 1 U T0CKI 1 X M Sync pin U 2 0 TMR0 reg 7 0 X Cycles T0SE(1) T0CS(1) PSA(1) 0 8-bit Prescaler M U 1 X OSC2/ Watchdog 8 M CLKOUT Timer U PS<2:0>(1) Internal Oscillator X 8 - to - 1MUX Drive Circuit PSA(1) “SLEEP” 0 1 Oscillator Mode MUX PSA(1) Select WDTEN SWDTEN bit(2) Configuration WDT bit Time-Out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN is a bit in the OPTION2 register.  2000 Microchip Technology Inc. Preliminary DS40197B-page 29

PIC16HV540 NOTES: DS40197B-page 30 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 7.0 SPECIAL FEATURES OF THE The SLEEP mode is designed to offer a very low cur- CPU rent power-down mode. The user can wake up from SLEEP through external reset or through a Watchdog What sets a microcontroller apart from other proces- Timer time-out. Several oscillator options are also sors are special circuits that deal with the needs of real- made available to allow the part to fit the application. time applications. The PIC16HV540 family of micro- The RC oscillator option saves system cost while the controllers has a host of such features intended to max- LP crystal option saves power. A set of configuration imize system reliability, minimize cost through bits are used to select various options. elimination of external components, provide power sav- ing operating modes and offer code protection. These 7.1 Configuration Bits features are: Configuration bits can be programmed to select various (cid:127) Oscillator selection device configurations. Two bits are for the selection of (cid:127) Reset the oscillator type and one bit is the Watchdog Timer (cid:127) Power-On Reset (POR) enable bit. Nine bits are code protection bits (Figure7- (cid:127) Brown-out Detect 1) for the PIC16HV540 devices. (cid:127) Device Reset Timer (DRT) (cid:127) Wake-up from SLEEP on Pin Change (cid:127) Enhanced Watchdog Timer (WDT) (cid:127) SLEEP (cid:127) Code protection The PIC16HV540 Family has a Watchdog Timer which can be shut off only through configuration bit WDTEN. It runs off of its own RC oscillator for added reliability. There is an 18 ms delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. With this timer on-chip, most applications need no external reset circuitry. REGISTER 7-1: CONFIGURATION WORD FOR PIC16HV540 CP CP CP CP CP CP CP CP CP WDTEN FOSC1 FOSC0 Register:CONFIG bit11 bit0 Address(1):0FFFh bit 11-3: CP: Code Protection bits 1 = Code protection off 0 = Code protection on bit 2: WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) bit 1-0: FOSC<1:0>: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Refer to the PIC16C5X Programming Specification (Literature number DS30190) to determine how to access the configuration word.  2000 Microchip Technology Inc. Preliminary DS40197B-page 31

PIC16HV540 7.2 Oscillator Configurations FIGURE 7-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP 7.2.1 OSCILLATOR TYPES OSC CONFIGURATION) The PIC16HV540 can be operated in four different oscillator modes. The user can program two configura- Clock from OSC1 tion bits (FOSC1:FOSC0) to select one of these four ext. system PIC16HV540 modes: Open OSC2 (cid:127) LP: Low Power Crystal (cid:127) XT: Crystal/Resonator (cid:127) HS: High Speed Crystal/Resonator TABLE 7-1: CAPACITOR SELECTION (cid:127) RC: Resistor/Capacitor FOR CERAMIC RESONATORS - PIC16HV540 Note: Not all oscillator selections available for all parts. See Section7.1. Osc Resonator Cap. Range Cap. Range Type Freq C1 C2 7.2.2 CRYSTAL OSCILLATOR / CERAMIC XT 455 kHz 68-100 pF 68-100 pF RESONATORS 2.0 MHz 15-33 pF 15-33 pF In XT, LP or HS modes, a crystal or ceramic resonator 4.0 MHz 10-22 pF 10-22 pF is connected to the OSC1/CLKIN and OSC2/CLKOUT HS 8.0 MHz 10-22 pF 10-22 pF pins to establish oscillation (Figure7-1). The 16.0 MHz 10 pF 10 pF PIC16HV540 oscillator design requires the use of a Note: These values are for design guidance only. parallel cut crystal. Use of a series cut crystal may give Since each resonator has its own charac- a frequency out of the crystal manufacturers specifica- teristics, the user should consult the reso- tions. When in XT, LP or HS modes, the device can nator manufacturer for appropriate values have an external clock source drive the OSC1/CLKIN of external components. pin (Figure7-2). TABLE 7-2: CAPACITOR SELECTION FIGURE 7-1: CRYSTAL OPERATION FOR CRYSTAL OSCILLATOR (OR CERAMIC RESONATOR) - PIC16HV540 (HS, XT OR LP OSC Osc Resonator Cap.Range Cap. Range CONFIGURATION) Type Freq C1 C2 C1(1) OSC1 PIC16HV540 LP 32 kHz(1) 15 pF 15 pF XT 100 kHz 15-30 pF 200-300 pF SLEEP 200 kHz 15-30 pF 100-200 pF XTAL RF(3) To internal 455 kHz 15-30 pF 15-100 pF logic 1 MHz 15-30 pF 15-30 pF OSC2 RS(2) 2 MHz 15 pF 15 pF C2(1) 4 MHz 15 pF 15 pF HS 4 MHz 15 pF 15 pF Note 1: See Capacitor Selection tables for 8 MHz 15 pF 15 pF recommended values of C1 and C2. 20 MHz 15 pF 15 pF 2: A series resistor (RS) may be required for AT strip cut crystals. Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is 3: RF varies with the crystal chosen (approx. recommended. value = 10 MΩ). 2: These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Note: If you change from this device to another device, please verify oscillator characteris- tics in your application. DS40197B-page 32 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 7.2.3 EXTERNAL CRYSTAL OSCILLATOR FIGURE 7-4: EXTERNAL SERIES CIRCUIT RESONANT CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator or a simple oscillator (USING XT, HS OR LP circuit with TTL gates can be used as an external crys- OSCILLATOR MODE) tal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well- To Other designed crystal oscillator will provide good perfor- 330 330 Devices mance with TTL gates. Two types of crystal oscillator 74AS04 74AS04 74AS04 PIC16HV540 circuits can be used: one with parallel resonance, or CLKIN one with series resonance. 0.1 µF Figure7-3 shows implementation of a parallel resonant OSC2 XTAL oscillator circuit. The circuit is designed to use the fun- 100k damental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the negative feedback for stability. The 10kΩ potentiome- Note: If you change from this device to another ters bias the 74AS04 in the linear region. This circuit device, please verify oscillator characteris- could be used for external oscillator designs. tics in your application. FIGURE 7-3: EXTERNAL PARALLEL 7.2.4 RC OSCILLATOR RESONANT CRYSTAL For timing insensitive applications, the RC device OSCILLATOR CIRCUIT option offers additional cost savings. The RC oscillator (USING XT, HS OR LP frequency is a function of the supply voltage, the resis- OSCILLATOR MODE) tor (Rext) and capacitor (Cext) values, and the operat- ing temperature. In addition to this, the oscillator +5V To Other frequency will vary from unit to unit due to normal pro- Devices cess parameter variation. Furthermore, the difference 10k 4.7k 74AS04 PIC16HV540 in lead frame capacitance between package types will also affect the oscillation frequency, especially for low 74AS04 CLKIN Cext values. The user also needs to take into account variation due to tolerance of external R and C compo- OSC2 nents used. 10k 100k Figure7-5 shows how the R/C combination is con- XTAL nected to the PIC16HV540. For Rext values below 10k 2.2kΩ, the oscillator operation may become unstable, or stop completely. For very high Rext values 20 pF 20 pF (e.g.,1MΩ) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3kΩ and 100kΩ. Note: If you change from this device to another Although the oscillator will operate with no external device, please verify oscillator characteris- capacitor (Cext = 0 pF), we recommend using values tics in your application. above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency Figure7-4 shows a series resonant oscillator circuit. can vary dramatically due to changes in external This circuit is also designed to use the fundamental fre- capacitances, such as PCB trace capacitance or pack- quency of the crystal. The inverter performs a 180- age lead frame capacitance. degree phase shift in a series resonant oscillator cir- cuit. The 330Ω resistors provide the negative feedback to bias the inverters in their linear region.  2000 Microchip Technology Inc. Preliminary DS40197B-page 33

PIC16HV540 The Electrical Specifications sections show RC fre- 7.3 Reset quency variation from part to part due to normal pro- cess variation. The variation is larger for larger R (since PIC16HV540 devices may be reset in one of the follow- leakage current variation will affect RC frequency more ing ways: for large R) and for smaller C (since variation of input (cid:127) Power-On Reset (POR) capacitance will affect RC frequency more). (cid:127) MCLR reset (normal operation) Also, see the Electrical Specifications sections for vari- (cid:127) MCLR wake-up reset (from SLEEP) ation of oscillator frequency due to VDD for given Rext/ (cid:127) WDT reset (normal operation) Cext values as well as frequency variation due to oper- (cid:127) WDT wake-up reset (from SLEEP) ating temperature for given R, C, and VDD values. (cid:127) Wake-up from SLEEP on Pin Change When used in RC mode, the CLKOUT pin can be used (cid:127) Brown-out Detect as a programmable clock output. The output is connected to TMR0, bit 0, and by setting the prescaler Table7-3 shows these reset conditions for the PCL and rate select bits, clock out frequencies of CLKIN/8 to STATUS registers. CLKIN/1024 can be generated. Some registers are not affected in any reset condition. Their status is unknown on POR and unchanged in any FIGURE 7-5: RC OSCILLATOR MODE other reset. Most other registers are reset to a “reset state” on Power-On Reset (POR), MCLR or WDT VDD Reset. A MCLR, WDT Wake-up from SLEEP or Wake- up from SLEEP on Pin Change also results in a device REXT Internal RESET, and not a continuation of operation before OSC1 clock SLEEP. The TO and PD bits (STATUS <4:3>) and PCWUF N CEXT PIC16HV540 (STATUS<7>) are set or cleared depending on the dif- ferent reset conditions (Section7.9). These bits may be VSS used to determine the nature of the reset. TMR0, 0 OSC2/CLKOUT Table7-4 lists a full description of reset states of all reg- isters. Figure7-6 shows a simplified block diagram of the on-chip reset circuit. Note: If you change from this device to another device, please verify oscillator characteris- tics in your application. DS40197B-page 34 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 TABLE 7-3: RESET CONDITIONS FOR SPECIAL REGISTERS PCL STATUS Condition Addr: 02h Addr: 03h Power-on Reset 1111 1111 1001 1xxx MCLR Reset (normal operation) 1111 1111 u00u uuuu(1) MCLR Wake-up (from SLEEP) 1111 1111 1001 0uuu WDT Reset (normal operation) 1111 1111 u000 1uuu(2) WDT Wake-up (from SLEEP) 1111 1111 1000 0uuu Wake-up from SLEEP on Pin Change 1111 1111 000u uuuu Brown-out Reset 1111 1111 x00x xxxx Legend: u = unchanged, x = unknown, - = unimplemented read as ’0’. Note 1: TO and PD bits retain their last value until one of the other reset conditions occur. 2: The CLRWDT instruction will set the TO and PD bits. TABLE 7-4: RESET CONDITIONS FOR ALL REGISTERS MCLR or WDT Wake-up on Pin Brown-out Register Address Power-On Reset Reset Change Reset W N/A xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx TRIS N/A 1111 1111 1111 1111 1111 1111 1111 1111 OPTION N/A --11 1111 --11 1111 --11 1111 --11 1111 OPTION2 N/A --11 1111 --uu uuuu --uu uuuu --xx xxxx INDF 00h xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx PCL(1) 02h 1111 1111 1111 1111 1111 1111 1111 1111 STATUS(1) 03h 1001 1xxx 100? ?uuu 000u uuuu x00x xxxx FSR 04h 111x xxxx 111u uuuu 111u uuuu 111x xxxx PORTA 05h ---- xxxx ---- uuuu ---- uuuu ---- xxxx PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx General Purpose Register Files 07-1Fh xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx Legend: u = unchanged, x = unknown, - = unimplemented, read as ’0’, q = see tables in Section7.10 for possible values. ? = value depends on condition. Note 1: See Table7-3 for reset value for specific conditions. FIGURE 7-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Power-up Detect VDD POR (Power-on Reset) BOR (Brown-out Reset) MCLR/VPP pin WDT Time-out RESET S Q WDT 8-bit Asynch On-chip Ripple Counter RC OSC (Start-up Timer) R Q CHIP RESET  2000 Microchip Technology Inc. Preliminary DS40197B-page 35

PIC16HV540 7.4 Power-On Reset (POR) FIGURE 7-7: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW The PIC16HV540 incorporates on-chip Power-on VDD POWER-UP) Reset (POR) circuitry which provides an internal chip reset for most power-up situations. To use this feature, VDD VDD the user merely ties the MCLR/VPP pin to VDD. A sim- plified block diagram of the on-chip Power-on Reset cir- D R cuit is shown in Figure7-7. R1 The Power-on Reset circuit and the Device Reset MCLR Timer (Section7.5) circuit are closely related. On C PIC16HV540 power-up, the reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on- (cid:127) External Power-On Reset circuit is required only if chip reset signal. VDD power-up is too slow. The diode D helps dis- charge the capacitor quickly when VDD powers A power-up example where MCLR is not tied to VDD is down. shown in Figure7-8. VDD is allowed to rise and stabilize (cid:127) R < 40kΩ is recommended to make sure that volt- before bringing MCLR high. The chip will actually come age drop across R does not violate the device elec- out of reset TDRT msec after MCLR goes high. trical specification. In Figure7-9, the on-chip Power-on Reset feature is (cid:127) R1 = 100Ω to 1kΩ will limit any current flowing into being used (MCLR and VDD are tied together). The VDD MCLR from external capacitor C in the event of MCLR pin breakdown due to Electrostatic Dis- is stable before the start-up timer times out and there is charge (ESD) or Electrical Overstress (EOS). no problem in getting a proper reset. However, Figure7-10 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses a high on the MCLR/VPP pin, and when the MCLR/VPP pin (and VDD) actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not guaranteed to function cor- rectly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure7-7). Note: When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, tempera- ture, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For more information on PIC16HV540 POR, see Power-Up Considerations - AN522 in the Embedded Control Handbook. The POR circuit does not produce an internal reset when VDD declines. DS40197B-page 36 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 FIGURE 7-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD) VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.  2000 Microchip Technology Inc. Preliminary DS40197B-page 37

PIC16HV540 7.5 Device Reset Timer (DRT) 7.6 Brown-Out Detect (BOD) In the PIC16HV540, the Device Reset Timer (DRT) The PIC16HV540 has on-chip Brown-out Detect cir- runs any time the device is powered up. DRT runs from cuitry. If enabled and if the internal power, V falls REG, reset and varies based on oscillator selection (see below parameter B (See Section 10.1), for greater VDD Table7-5). time than parameter T (See Table10-3) the brown- BOD out condition will reset the chip. A reset is not guaran- The DRT provides a fixed 18 ms nominal time-out on teed if V falls below B for less time than param- reset. The DRT operates on an internal RC oscillator. REG VDD eter (T ). The processor is kept in RESET as long as the DRT is BOD active. The DRT delay allows Vdd to rise above Vdd On resets (Brown-out, Watchdog, MCLR and Wake-up min., and for the oscillator to stabilize. on Pin Change), the chip will remain in reset until V REG rises above B . Once the B threshold has been Oscillator circuits based on crystals or ceramic resona- VDD VDD met the DRT will now be invoked and will keep the chip tors require a certain time after power-up to establish a in reset an additional 18mS (LP, XT and HS oscillator stable oscillation. The on-chip DRT keeps the device in modes) or 1mS for EXTRC. a RESET condition for approximately 18 ms after the voltage on the MCLR/VPP pin has reach a logic high If VREG drops below BVDD while the DRT is running, the (VIH) level. Thus, external RC networks connected to chip will go back into a Brown-out Reset and the DRT the MCLR input are not required in most cases, allow- will be re-initialized. Once V rises above the B , REG VDD ing for savings in cost-sensitive and/or space restricted the DRT will execute the specified time period. applications. Figure7-11 shows typical Brown-out situations. The Device Reset time delay will vary from chip to chip The Brown-out Detect circuit can be disabled or due to VDD, temperature, and process variation. See enabled by setting the BODEN bit in the OPTION2 AC parameters for details. SFR. The Brown-out Detect is disabled upon all Power- on Resets (POR). The DRT will also be triggered upon a Watchdog Timer time-out, MCLR Reset, Wake-up from SLEEP on Pin 7.6.1 IMPLEMENTING THE ON-CHIP BOD Change and Brown-out Reset. When the external RC CIRCUIT oscillator mode is selected, all DRT periods, after the initial POR, are 1 ms (typical). The PIC16HV540 BOD circuitry differs from “conven- tional” brown-out detect circuitry in that the BOD cir- TABLE 7-5: DRT (DEVICE RESET TIMER cuitry on the PIC16HV540 does not directly detect PERIOD) “dips” in the external V supply voltage but rather the DD Oscillator Subsequent internal VREG. The functionality of the BOD circuitry POR Reset Configuration Resets ensures that program execution will halt and a reset state will be entered into prior to the internal logic EXTRC 18 ms (typical) 1 ms (typical) becoming corrupted. The BOD circuit has two select- LP, XT & HS 18 ms (typical) 18 ms (typical) able voltage settings, nominally 5V and 3V. Each regu- lation voltage setting with its associated minimum and maximum B parameters has an intended opera- VDD tional mode that must be carefully considered. For the 5V V setting, the minimum B parameter REG VDD is 2.7V This minimum B voltage is below the part . VDD V minimum requirements. This operational setting is DD primarily intended for use when the PIC16HV540 is operating at 4Mhz and V > 5.5V. DD For the 3V V setting, the minimum B parameter REG VDD is 1.8V. This minimum B voltage is below the part VDD V minimum requirements. This operational setting is DD primarily intended for use when the PIC16HV540 is in SLEEP. RAM retention is protected by the 1.8V trip level. For the regulation and Brown-out circuits to function as intended the applied V is nominally 0.5V greater than DD the regulation voltage setting. Finally, if the internal brown-out circuit is deemed not to meet system design requirements then an external brown-out protection circuit may be required. Microchip offers a complete family of voltage supervisor products which can meet most design requirements. DS40197B-page 38 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 FIGURE 7-11: BROWN-OUT SITUATIONS VREG BVDD(1) Internal Reset 18 ms(2) VREG BVDD(1) Internal 18 ms(2) Reset 18 ms(2) VREG BVDD(1) Internal Reset 18 ms(2) Note 1: BVDD depends on selection of bit ‘RL’ in OPTION2 SFR. 2: DRT time depends on which oscillator mode is selected and which reset state the part is in. 7.7 Watchdog Timer (WDT) 7.7.2 WDT PROGRAMMING CONSIDERATIONS The Watchdog Timer (WDT) is a free running on-chip The CLRWDT instruction clears the WDT and the RC oscillator which does not require any external com- postscaler, if assigned to the WDT, and prevents it from ponents. This RC oscillator is separate from the RC timing out and generating a device RESET. oscillator of the OSC1/CLKIN pin. That means that the The SLEEP instruction resets the WDT and the WDT will run even if the clock on the OSC1/CLKIN and postscaler, if assigned to the WDT. This gives the max- OSC2/CLKOUT pins have been stopped, for example, imum SLEEP time before a WDT Wake-up Reset. by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT Reset or Wake-up Reset 7.8 Internal Voltage Regulators generates a device RESET. The PIC16HV540 has 2 internal voltage regulators. The TO bit (STATUS<4>) will be cleared upon a Watch- The PORTA I/O pads and OSC2 are powered by one dog Timer Reset. internal voltage regulator V , while the second internal IO The Watchdog Timer is enabled/disabled by a device voltage regulator V , powers the PICmicro® device REG configuration bit (see Figure7-1). If the WDT is core. Both regulated voltage levels can be synchro- enabled, software execution may not disable this func- nously switched in the active modes between 3V and tion. When the WDTEN configuration bit is cleared, the 5V through bit “RL” in the OPTION2 register. In addi- SWDTEN bit, OPTION2<4>, enables/disables the tion, the “SL” bit in the OPTION2 register can be used operation of the WDT. to control the core’s regulated voltage level during SLEEP mode. V regulates the 15V power applied REG 7.7.1 WDT PERIOD to the V pin. DD The WDT has a nominal time-out period of 18 ms, (with The on-chip Brown-out Detect circuitry monitors the no prescaler). If a longer time-out period is desired, a CPU regulated voltage V , for determining if a REG prescaler with a division ratio of up to 1:128 can be brown-out reset is generated (see Section7.6 for more assigned to the WDT (under software control) by writ- details on the BOD). ing to the OPTION register. Thus, time-out a period of The regulator circuits are identical in functional nature a nominal 2.3 seconds can be realized. These periods but only the V regulator voltage can be measured, IO vary with temperature, VDD and part-to-part process externally (See Section10.1 for V parameters). The IO variations (see DC specs). operational voltage range and pin loading requirements Under worst case conditions (VDD = Min., Temperature must be considered to ensure proper system operation. = Max., max. WDT prescaler), it may take several sec- For example, if 3V regulation is implemented during the onds before a WDT time-out occurs. SLEEP mode and 40mA is being sourced from PORTA, the V regulation voltage may approach the specified IO minimum voltage. This may be an issue to consider for connections to external circuitry. Likewise, if zero cur- rent is sourced from the PORTA pins, the regulation  2000 Microchip Technology Inc. Preliminary DS40197B-page 39

PIC16HV540 voltage may approach the maximum value. Again this condition should be considered when interfacing to external circuitry. In addition, the voltage level applied to the external V DD pin and operational temperature affects the internal regulation voltage. FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source 0 M Postscaler Watchdog 1 U Postscaler Timer X 8 - to - 1 MUX PS<2:0> PSA To TMR0 WDTEN SWDTEN bit 0 1 Configuration bit MUX PSA Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. WDT Time-out TABLE 7-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Value on Value on Wake-up Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On MCLR and Brown-out on Pin Reset WDT Reset Reset Change N/A OPTION — — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111 --11 1111 --11 1111 N/A OPTION2 — — PCWU SWDTEN RL SL BODL BODEN --UU UUU --uu uuuu --uu uuuu --xx xxxx Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as '0', u = unchanged, x = unknown. DS40197B-page 40 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 7.9 Time-out Sequence and Power-down 7.10 Power-down Mode (SLEEP) Status Bits (TO/PD/PCWUF) A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). The TO, PD and PCWUF bits in the STATUS register can be tested to determine if a RESET condition has 7.10.1 SLEEP been caused by a power-up condition, a MCLR, Watch- dog Timer (WDT) Reset, WDT Wake-up Reset, or The Power-down mode is entered by executing a Wake-up from SLEEP on Pin Change. SLEEP instruction. If enabled, the Watchdog Timer will be cleared but TABLE 7-7: TO/PD/PCWUF STATUS keeps running, the TO bit (STATUS<4>) is set, the PD AFTER RESET bit (STATUS<3>) is cleared, the PCWUF bit (STATUS<7>) is set and the oscillator driver is turned PCWUF TO PD RESET was caused by off. The I/O ports maintain the status they had before 1 1 1 Power-up (POR) the SLEEP instruction was executed (driving high, driv- u u u MCLR Reset (normal operation)(1) ing low, or hi-impedance). u 1 0 MCLR Wake-up Reset (from SLEEP) u 0 1 WDT Reset (normal operation) It should be noted that a RESET generated by a WDT u 0 0 WDT Wake-up Reset (from SLEEP) time-out does not drive the MCLR/VPP pin low. 0 u u Wake-up from SLEEP on Pin Change For lowest current consumption while powered down, x x x Brown-out Reset the T0CKI input should be at VDD or VSS and the MCLR/ Legend: u = unchanged, x = unknown VPP pin must be at a logic high level (VIH MCLR). Note 1: The TO and PD and PCWUF bits maintain their status (u) until a reset occurs. A low-pulse on the MCLR input does 7.10.2 WAKE-UP FROM SLEEP not change the TO and PD and PCWUF status bits. These STATUS bits are only affected by events listed in The device can wake up from SLEEP through one of Table7-8. the following events: 1. An external reset input on MCLR/VPP pin. TABLE 7-8: EVENTS AFFECTING TO/PD 2. A Watchdog Timer Time-out Reset (if WDT was STATUS BITS enabled). Event PCWUF TO PD Remarks 3. A change on input pins PORTB:<0-3,7> when Wake-up on Pin Change is enabled. Power-up 1 1 1 WDT Time-out u 0 u No effect on 4. Brown-out Reset. PD These events cause a device RESET. The TO and PD SLEEP instruction 1 1 0 and PCWUF bits can be used to determine the cause CLRWDT instruction u 1 1 of device RESET. The TO bit is cleared if a WDT time- Wake-up from SLEEP 0 u u out occurred (and caused wake-up). The PD bit, which on Pin Change Legend: u = unchanged is set on power-up, is cleared when SLEEP is invoked. Note: A WDT time-out will occur regardless of the status of the TO The PCWUF bit indicates a change in state while in bit. A SLEEP instruction will be executed, regardless of the SLEEP at pins PORTB:<0-3,7> (since the SLEEP state status of the PD bit. Table7-7 reflects the status of TO and PD after the corresponding event. was entered). Table7-3 lists the reset conditions for the special func- The WDT is cleared when the device wakes from tion registers, while Table7-4 lists the reset conditions SLEEP, regardless of the wake-up source. for all the registers.  2000 Microchip Technology Inc. Preliminary DS40197B-page 41

PIC16HV540 7.11 Program Verification/Code Protection If the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code pro- tecting windowed devices. 7.12 ID Locations Four memory locations are designated as ID locations where the user can store checksum or other code-iden- tification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Use only the lower 4 bits of the ID locations and always program the upper 8 bits as ‘1’s. Note: Microchip will assign a unique pattern number for QTP and SQTP requests and for ROM devices. This pattern number will be unique and traceable to the submitted code. DS40197B-page 42 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 8.0 INSTRUCTION SET SUMMARY All instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- Each PIC16HV540 instruction is a 12-bit word divided gram counter is changed as a result of an instruction. into an OPCODE, which specifies the instruction type, In this case, the execution takes two instruction cycles. and one or more operands which further specify the One instruction cycle consists of four oscillator periods. operation of the instruction. The PIC16HV540 instruc- Thus, for an oscillator frequency of 4 MHz, the normal tion set summary in Table8-2 groups the instructions instruction execution time is 1 µs. If a conditional test is into byte-oriented, bit-oriented, and literal and control true or the program counter is changed as a result of an operations. Table8-1 shows the opcode field descrip- instruction, the instruction execution time is 2 µs. tions. Figure8-1 shows the three general formats that the For byte-oriented instructions, ’f’ represents a file reg- instructions can have. All examples in the figure use the ister designator and ’d’ represents a destination desig- following format to represent a hexadecimal number: nator. The file register designator is used to specify which one of the 32 file registers is to be used by the 0xhhh instruction. where ’h’ signifies a hexadecimal digit. The destination designator specifies where the result of the operation is to be placed. If ’d’ is ’0’, the result is FIGURE 8-1: GENERAL FORMAT FOR placed in the W register. If ’d’ is ’1’, the result is placed INSTRUCTIONS in the file register specified in the instruction. Byte-oriented file register operations For bit-oriented instructions, ’b’ represents a bit field 11 6 5 4 0 designator which selects the number of the bit affected OPCODE d f (FILE #) by the operation, while ’f’ represents the number of the file in which the bit is located. d = 0 for destination W d = 1 for destination f For literal and control operations, ’k’ represents an f = 5-bit file register address 8or 9-bit constant or literal value. Bit-oriented file register operations TABLE 8-1: OPCODE FIELD 11 8 7 5 4 0 DESCRIPTIONS OPCODE b (BIT #) f (FILE #) Field Description b = 3-bit bit address f Register file address (0x00 to 0x7F) f = 5-bit file register address W Working register (accumulator) Literal and control operations (except GOTO) b Bit address within an 8-bit file register 11 8 7 0 k Literal field, constant data or label OPCODE k (literal) x Don’t care location (= 0 or 1) The assembler will generate code with x = 0. k = 8-bit immediate value It is the recommended form of use for com- Literal and control operations - GOTO instruction patibility with all Microchip software tools. 11 9 8 0 d Destination select; d = 0 (store result in W) OPCODE k (literal) d = 1 (store result in file register ’f’) k = 9-bit immediate value Default is d = 1 label Label name TOS Top of Stack PC Program Counter WDT Watchdog Timer Counter TO Time-Out bit PD Power-Down bit dest Destination, either the W register or the specified register file location [ ] Options ( ) Contents → Assigned to < > Register bit field ∈ In the set of italics User defined term (font is courier)  2000 Microchip Technology Inc. Preliminary DS40197B-page 43

PIC16HV540 TABLE 8-2: INSTRUCTION SET SUMMARY 12-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb ADDWF f,d Add W and f 1 0001 11df ffff C,DC,Z 1,2,4 ANDWF f,d AND W with f 1 0001 01df ffff Z 2,4 CLRF f Clear f 1 0000 011f ffff Z 4 CLRW – Clear W 1 0000 0100 0000 Z COMF f, d Complement f 1 0010 01df ffff Z DECF f, d Decrement f 1 0000 11df ffff Z 2,4 DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2,4 INCF f, d Increment f 1 0010 10df ffff Z 2,4 INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2,4 IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2,4 MOVF f, d Move f 1 0010 00df ffff Z 2,4 MOVWF f Move W to f 1 0000 001f ffff None 1,4 NOP – No Operation 1 0000 0000 0000 None RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2,4 RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2,4 SUBWF f, d Subtract W from f 1 0000 10df ffff C,DC,Z 1,2,4 SWAPF f, d Swap f 1 0011 10df ffff None 2,4 XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2,4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 0100 bbbf ffff None 2,4 BSF f, b Bit Set f 1 0101 bbbf ffff None 2,4 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 0110 bbbf ffff None BTFSS f, b Bit Test f, Skip if Set 1 (2) 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Call subroutine 2 1001 kkkk kkkk None 1 CLRWDT k Clear Watchdog Timer 1 0000 0000 0100 TO, PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR Literal with W 1 1101 kkkk kkkk Z MOVLW k Move Literal to W 1 1100 kkkk kkkk None OPTION k Load OPTION register 1 0000 0000 0010 None RETLW k Return, place Literal in W 2 1000 kkkk kkkk None SLEEP – Go into standby mode 1 0000 0000 0011 TO, PD,PCWUF TRIS f Load TRIS register 1 0000 0000 0fff None 3 XORLW k Exclusive OR Literal to W 1 1111 kkkk kkkk Z Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO. (See individual device data sheets, Memory Section/Indirect Data Addressing, INDF and FSR Regis- ters) 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: The instruction TRIS f, where f = 5 or 6 causes the contents of the W register to be written to the tristate latches of PORTA or B respectively. A '1' forces the pin to a hi-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS40197B-page 44 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 ADDWF Add W and f ANDWF AND W with f Syntax: [ label ] ADDWF f,d Syntax: [ label ] ANDWF f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: (W) + (f) → (dest) Operation: (W) .AND. (f) → (dest) Status Affected: C, DC, Z Status Affected: Z Encoding: 0001 11df ffff Encoding: 0001 01df ffff Description: Add the contents of the W register and Description: The contents of the W register are register ’f’. If ’d’ is 0 the result is stored AND’ed with register 'f'. If 'd' is 0 the in the W register. If ’d’ is ’1’ the result is result is stored in the W register. If 'd' is stored back in register ’f’. '1' the result is stored back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: ADDWF FSR, 0 Example: ANDWF FSR, 1 Before Instruction Before Instruction W = 0x17 W = 0x17 FSR = 0xC2 FSR = 0xC2 After Instruction After Instruction W = 0xD9 W = 0x17 FSR = 0xC2 FSR = 0x02 ANDLW And literal with W BCF Bit Clear f Syntax: [ label ] ANDLW k Syntax: [ label ] BCF f,b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 31 Operation: (W).AND. (k) → (W) 0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: Z Status Affected: None Encoding: 1110 kkkk kkkk Encoding: 0100 bbbf ffff Description: The contents of the W register are AND’ed with the eight-bit literal 'k'. The Description: Bit 'b' in register 'f' is cleared. result is placed in the W register. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: BCF FLAG_REG, 7 Example: ANDLW 0x5F Before Instruction Before Instruction FLAG_REG = 0xC7 W = 0xA3 After Instruction After Instruction FLAG_REG = 0x47 W = 0x03  2000 Microchip Technology Inc. Preliminary DS40197B-page 45

PIC16HV540 BSF Bit Set f BTFSS Bit Test f, Skip if Set Syntax: [ label ] BSF f,b Syntax: [ label ] BTFSS f,b Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 0 ≤ b ≤ 7 0 ≤ b < 7 Operation: 1 → (f<b>) Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 0101 bbbf ffff Encoding: 0111 bbbf ffff Description: Bit ’b’ in register ’f’ is set. Description: If bit ’b’ in register ’f’ is ’1’ then the next instruction is skipped. Words: 1 If bit ’b’ is ’1’, then the next instruction Cycles: 1 fetched during the current instruction Example: BSF FLAG_REG, 7 execution, is discarded and an NOP is executed instead, making this a 2 cycle Before Instruction instruction. FLAG_REG = 0x0A Words: 1 After Instruction Cycles: 1(2) FLAG_REG = 0x8A Example: HERE BTFSS FLAG,1 BTFSC Bit Test f, Skip if Clear FALSE GOTO PROCESS_CODE TRUE • Syntax: [ label ] BTFSC f,b • Operands: 0 ≤ f ≤ 31 • 0 ≤ b ≤ 7 Before Instruction Operation: skip if (f<b>) = 0 PC = address (HERE) After Instruction Status Affected: None If FLAG<1> = 0, Encoding: 0110 bbbf ffff PC = address (FALSE); Description: If bit ’b’ in register ’f’ is 0 then the next if FLAG<1> = 1, instruction is skipped. PC = address (TRUE) If bit ’b’ is 0 then the next instruction fetched during the current instruction execution is discarded, and an NOP is executed instead, making this a 2 cycle instruction. Words: 1 Cycles: 1(2) Example: HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE (cid:127) (cid:127) (cid:127) Before Instruction PC = address (HERE) After Instruction if FLAG<1> = 0, PC = address (TRUE); if FLAG<1> = 1, PC = address(FALSE) DS40197B-page 46 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 CALL Subroutine Call CLRW Clear W Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0 ≤ k ≤ 255 Operands: None Operation: (PC) + 1→ Top of Stack; Operation: 00h → (W); k → PC<7:0>; 1 → Z (STATUS<6:5>) → PC<10:9>; Status Affected: Z 0 → PC<8> Encoding: 0000 0100 0000 Status Affected: None Description: The W register is cleared. Zero bit (Z) Encoding: 1001 kkkk kkkk is set. Description: Subroutine call. First, return address Words: 1 (PC+1) is pushed onto the stack. The Cycles: 1 eight bit immediate address is loaded into PC bits <7:0>. The upper bits Example: CLRW PC<10:9> are loaded from STA- TUS<6:5>, PC<8> is cleared. CALL is Before Instruction a two cycle instruction. W = 0x5A Words: 1 After Instruction W = 0x00 Cycles: 2 Z = 1 Example: HERE CALL THERE CLRWDT Clear Watchdog Timer Before Instruction PC = address (HERE) Syntax: [ label ] CLRWDT After Instruction Operands: None PC = address (THERE) Operation: 00h → WDT; TOS= address (HERE + 1) 0 → WDT prescaler (if assigned); 1 → TO; CLRF Clear f 1 → PD Syntax: [ label ] CLRF f Status Affected: TO, PD Operands: 0 ≤ f ≤ 31 Encoding: 0000 0000 0100 Operation: 00h → (f); 1 → Z Description: The CLRWDT instruction resets the WDT. It also resets the prescaler, if the Status Affected: Z prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are Encoding: 0000 011f ffff set. Description: The contents of register ’f’ are cleared Words: 1 and the Z bit is set. Cycles: 1 Words: 1 Example: CLRWDT Cycles: 1 Before Instruction Example: CLRF FLAG_REG WDT counter = ? Before Instruction After Instruction FLAG_REG = 0x5A WDT counter = 0x00 After Instruction WDT prescale = 0 FLAG_REG = 0x00 TO = 1 Z = 1 PD = 1  2000 Microchip Technology Inc. Preliminary DS40197B-page 47

PIC16HV540 COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF f,d Syntax: [ label ] DECFSZ f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: (f) → (dest) Operation: (f) – 1 → d; skip if result = 0 Status Affected: Z Status Affected: None Encoding: 0010 01df ffff Encoding: 0010 11df ffff Description: The contents of register ’f’ are comple- Description: The contents of register ’f’ are decre- mented. If ’d’ is 0 the result is stored in mented. If ’d’ is 0 the result is placed in the W register. If ’d’ is 1 the result is the W register. If ’d’ is 1 the result is stored back in register ’f’. placed back in register ’f’. Words: 1 If the result is 0, the next instruction, which is already fetched, is discarded Cycles: 1 and an NOP is executed instead mak- Example: COMF REG1,0 ing it a two cycle instruction. Before Instruction Words: 1 REG1 = 0x13 Cycles: 1(2) After Instruction Example: HERE DECFSZ CNT, 1 REG1 = 0x13 GOTO LOOP W = 0xEC CONTINUE (cid:127) (cid:127) DECF Decrement f (cid:127) Syntax: [ label ] DECF f,d Before Instruction PC = address (HERE) Operands: 0 ≤ f ≤ 31 d ∈ [0,1] After Instruction CNT = CNT - 1; Operation: (f) – 1 → (dest) if CNT = 0, Status Affected: Z PC = address (CONTINUE); if CNT ≠ 0, Encoding: 0000 11df ffff PC = address (HERE+1) Description: Decrement register ’f’. If ’d’ is 0 the result is stored in the W register. If ’d’ is GOTO Unconditional Branch 1 the result is stored back in register ’f’. Syntax: [ label ] GOTO k Words: 1 Operands: 0 ≤ k ≤ 511 Cycles: 1 Operation: k → PC<8:0>; Example: DECF CNT, 1 STATUS<6:5> → PC<10:9> Before Instruction Status Affected: None CNT = 0x01 Encoding: 101k kkkk kkkk Z = 0 After Instruction Description: GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC CNT = 0x00 bits <8:0>. The upper bits of PC are Z = 1 loaded from STATUS<6:5>. GOTO is a two cycle instruction. Words: 1 Cycles: 2 Example: GOTO THERE After Instruction PC = address (THERE) DS40197B-page 48 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 INCF Increment f IORLW Inclusive OR literal with W Syntax: [ label ] INCF f,d Syntax: [ label ] IORLW k Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .OR. (k) → (W) Operation: (f) + 1 → (dest) Status Affected: Z Status Affected: Z Encoding: 1101 kkkk kkkk Encoding: 0010 10df ffff Description: The contents of the W register are Description: The contents of register ’f’ are incre- OR’ed with the eight bit literal 'k'. The mented. If ’d’ is 0 the result is placed in result is placed in the W register. the W register. If ’d’ is 1 the result is Words: 1 placed back in register ’f’. Cycles: 1 Words: 1 Example: IORLW 0x35 Cycles: 1 Before Instruction Example: INCF CNT, 1 W = 0x9A Before Instruction After Instruction CNT = 0xFF W = 0xBF Z = 0 Z = 0 After Instruction CNT = 0x00 IORWF Inclusive OR W with f Z = 1 Syntax: [ label ] IORWF f,d INCFSZ Increment f, Skip if 0 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Syntax: [ label ] INCFSZ f,d Operation: (W).OR. (f) → (dest) Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Status Affected: Z Operation: (f) + 1 → (dest), skip if result = 0 Encoding: 0001 00df ffff Status Affected: None Description: Inclusive OR the W register with regis- ter 'f'. If 'd' is 0 the result is placed in Encoding: 0011 11df ffff the W register. If 'd' is 1 the result is Description: The contents of register ’f’ are incre- placed back in register 'f'. mented. If ’d’ is 0 the result is placed in Words: 1 the W register. If ’d’ is 1 the result is placed back in register ’f’. Cycles: 1 If the result is 0, then the next instruc- Example: IORWF RESULT, 0 tion, which is already fetched, is dis- Before Instruction carded and an NOP is executed instead making it a two cycle instruc- RESULT = 0x13 tion. W = 0x91 Words: 1 After Instruction RESULT = 0x13 Cycles: 1(2) W = 0x93 Example: HERE INCFSZ CNT, 1 Z = 0 GOTO LOOP CONTINUE (cid:127) (cid:127) (cid:127) Before Instruction PC = address (HERE) After Instruction CNT = CNT + 1; if CNT = 0, PC = address (CONTINUE); if CNT ≠ 0, PC = address (HERE +1)  2000 Microchip Technology Inc. Preliminary DS40197B-page 49

PIC16HV540 MOVF Move f MOVWF Move W to f Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (W) → (f) Operation: (f) → (dest) Status Affected: None Status Affected: Z Encoding: 0000 001f ffff Encoding: 0010 00df ffff Description: Move data from the W register to regis- Description: The contents of register ’f’ is moved to ter 'f'. destination ’d’. If ’d’ is 0, destination is Words: 1 the W register. If ’d’ is 1, the destination is file register ’f’. ’d’ is 1 is useful to test Cycles: 1 a file register since status flag Z is Example: MOVWF TEMP_REG affected. Before Instruction Words: 1 TEMP_REG = 0xFF Cycles: 1 W = 0x4F Example: MOVF FSR, 0 After Instruction TEMP_REG = 0x4F After Instruction W = 0x4F W = value in FSR register NOP No Operation MOVLW Move Literal to W Syntax: [ label ] NOP Syntax: [ label ] MOVLW k Operands: None Operands: 0 ≤ k ≤ 255 Operation: No operation Operation: k → (W) Status Affected: None Status Affected: None Encoding: 0000 0000 0000 Encoding: 1100 kkkk kkkk Description: No operation. Description: The eight bit literal ’k’ is loaded into the Words: 1 W register. The don’t cares will assem- Cycles: 1 ble as 0s. Example: NOP Words: 1 Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A DS40197B-page 50 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 OPTION Load OPTION Register RLF Rotate Left f through Carry Syntax: [ label ] OPTION Syntax: [ label ] RLF f,d Operands: None Operands: 0 ≤ f ≤ 31 Operation: (W) → OPTION d ∈ [0,1] Status Affected: None Operation: See description below Encoding: 0000 0000 0010 Status Affected: C Description: The content of the W register is loaded Encoding: 0011 01df ffff into the OPTION register. Description: The contents of register ’f’ are rotated Words: 1 one bit to the left through the Carry Cycles: 1 Flag. If ’d’ is 0 the result is placed in the W register. If ’d’ is 1 the result is stored Example OPTIO back in register ’f’. N C register ’f’ Before Instruction W = 0x07 Words: 1 After Instruction Cycles: 1 OPTION = 0x07 Example: RLF REG1,0 RETLW Return with Literal in W Before Instruction Syntax: [ label ] RETLW k REG1 = 1110 0110 Operands: 0 ≤ k ≤ 255 C = 0 Operation: k → (W); After Instruction TOS → PC REG1 = 1110 0110 W = 1100 1100 Status Affected: None C = 1 Encoding: 1000 kkkk kkkk RRF Rotate Right f through Carry Description: The W register is loaded with the eight bit literal ’k’. The program counter is Syntax: [ label ] RRF f,d loaded from the top of the stack (the Operands: 0 ≤ f ≤ 31 return address). This is a two cycle d ∈ [0,1] instruction. Operation: See description below Words: 1 Status Affected: C Cycles: 2 Encoding: 0011 00df ffff Example: CALL TABLE ;W contains ;table offset Description: The contents of register ’f’ are rotated ;value. one bit to the right through the Carry (cid:127) ;W now has table Flag. If ’d’ is 0 the result is placed in the (cid:127) ;value. W register. If ’d’ is 1 the result is placed (cid:127) back in register ’f’. TABLE ADDWF PC ;W = offset RETLW k1 ;Begin table C register ’f’ RETLW k2 ; (cid:127) Words: 1 (cid:127) Cycles: 1 (cid:127) RETLW kn ; End of table Example: RRF REG1,0 Before Instruction Before Instruction W = 0x07 REG1 = 1110 0110 C = 0 After Instruction W = value of k8 After Instruction REG1 = 1110 0110 W = 0111 0011 C = 0  2000 Microchip Technology Inc. Preliminary DS40197B-page 51

PIC16HV540 SLEEP Enter SLEEP Mode SUBWF Subtract W from f Syntax: [label] SLEEP Syntax: [label] SUBWF f,d Operands: None Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: 00h → WDT; 0 → WDT prescaler; Operation: (f) – (W) → (dest) 1 → TO; Status Affected: C, DC, Z 0 → PD 1→ PCWUF Encoding: 0000 10df ffff Description: Subtract (2’s complement method) the Status Affected: TO, PD, PCWUF W register from register 'f'. If 'd' is 0 the Encoding: 0000 0000 0011 result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Description: Time-out status bit (TO) is set. The power down status bit (PD) is cleared. Words: 1 The WDT and its prescaler are Cycles: 1 cleared. The processor is put into SLEEP mode Example 1: SUBWF REG1, 1 with the oscillator stopped. See sec- Before Instruction tion on SLEEP for more details. REG1 = 3 Words: 1 W = 2 C = ? Cycles: 1 After Instruction Example: SLEEP REG1 = 1 W = 2 C = 1 ; result is positive Example 2: Before Instruction REG1 = 2 W = 2 C = ? After Instruction REG1 = 0 W = 2 C = 1 ; result is zero Example 3: Before Instruction REG1 = 1 W = 2 C = ? After Instruction REG1 = FF W = 2 C = 0 ; result is negative DS40197B-page 52 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [label] XORLW k Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .XOR. k → (W) Operation: (f<3:0>) → (dest<7:4>); Status Affected: Z (f<7:4>) → (dest<3:0>) Encoding: 1111 kkkk kkkk Status Affected: None Description: The contents of the W register are Encoding: 0011 10df ffff XOR’ed with the eight bit literal 'k'. The Description: The upper and lower nibbles of register result is placed in the W register. ’f’ are exchanged. If ’d’ is 0 the result is Words: 1 placed in W register. If ’d’ is 1 the result is placed in register ’f’. Cycles: 1 Words: 1 Example: XORLW 0xAF Cycles: 1 Before Instruction W = 0xB5 Example SWAPF REG1, 0 After Instruction Before Instruction W = 0x1A REG1 = 0xA5 After Instruction XORWF Exclusive OR W with f REG1 = 0xA5 Syntax: [ label ] XORWF f,d W = 0X5A Operands: 0 ≤ f ≤ 31 TRIS Load TRIS Register d ∈ [0,1] Syntax: [ label ] TRIS f Operation: (W) .XOR. (f) → (dest) Operands: f = 5, 6 or 7 Status Affected: Z Operation: (W) → TRIS register f Encoding: 0001 10df ffff Status Affected: None Description: Exclusive OR the contents of the W Encoding: 0000 0000 0fff register with register 'f'. If 'd' is 0 the Description: TRIS register ’f’ (f = 5, 6, or 7*) is loaded result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. with the contents of the W register Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example TRIS PORTA Example XORWF REG,1 Before Instruction Before Instruction W = 0XA5 REG = 0xAF After Instruction W = 0xB5 TRISA = 0XA5 After Instruction REG = 0x1A *A TRIS 7 operation will update the OPTION2 SFR. W = 0xB5  2000 Microchip Technology Inc. Preliminary DS40197B-page 53

PIC16HV540 NOTES: DS40197B-page 54 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 9.0 DEVELOPMENT SUPPORT MPLAB allows you to: The PICmicro® microcontrollers are supported with a (cid:127) Edit your source files (either assembly or ‘C’) full range of hardware and software development tools: (cid:127) One touch assemble (or compile) and download to PICmicro tools (automatically updates all (cid:127) Integrated Development Environment project information) - MPLAB® IDE Software (cid:127) Debug using: (cid:127) Assemblers/Compilers/Linkers - source files - MPASM Assembler - absolute listing file - MPLAB-C17 and MPLAB-C18 C Compilers - object code - MPLINK/MPLIB Linker/Librarian The ability to use MPLAB with Microchip’s simulator, (cid:127) Simulators MPLAB-SIM, allows a consistent platform and the abil- - MPLAB-SIM Software Simulator ity to easily switch from the cost-effective simulator to (cid:127) Emulators the full featured emulator with minimal retraining. - MPLAB-ICE Real-Time In-Circuit Emulator - PICMASTER®/PICMASTER-CE In-Circuit 9.2 MPASM Assembler Emulator MPASM is a full featured universal macro assembler for - ICEPIC™ all PICmicro MCU’s. It can produce absolute code (cid:127) In-Circuit Debugger directly in the form of HEX files for device program- - MPLAB-ICD for PIC16F877 mers, or it can generate relocatable objects for MPLINK. (cid:127) Device Programmers - PRO MATE II Universal Programmer MPASM has a command line interface and a Windows  shell and can be used as a standalone application on a - PICSTART Plus Entry-Level Prototype Windows 3.x or greater system. MPASM generates Programmer relocatable object files, Intel standard HEX files, MAP (cid:127) Low-Cost Demonstration Boards files to detail memory usage and symbol reference, an - SIMICE absolute LST file which contains source lines and gen- - PICDEM-1 erated machine code, and a COD file for MPLAB - PICDEM-2 debugging. - PICDEM-3 MPASM features include: - PICDEM-17 (cid:127) MPASM and MPLINK are integrated into MPLAB  - SEEVAL projects.  - KEELOQ (cid:127) MPASM allows user defined macros to be created for streamlined assembly. 9.1 MPLAB Integrated Development (cid:127) MPASM allows conditional assembly for multi pur- Environment Software pose source files. The MPLAB IDE software brings an ease of software (cid:127) MPASM directives allow complete control over the development previously unseen in the 8-bit microcon- assembly process.  troller market. MPLAB is a Windows -based applica- 9.3 MPLAB-C17 and MPLAB-C18 tion which contains: C Compilers (cid:127) Multiple functionality - editor The MPLAB-C17 and MPLAB-C18 Code Development - simulator Systems are complete ANSI ‘C’ compilers and inte- grated development environments for Microchip’s - programmer (sold separately) PIC17CXXX and PIC18CXXX family of microcontrol- - emulator (sold separately) lers, respectively. These compilers provide powerful (cid:127) A full featured editor integration capabilities and ease of use not found with (cid:127) A project manager other compilers. (cid:127) Customizable tool bar and key mapping For easier source level debugging, the compilers pro- (cid:127) A status bar vide symbol information that is compatible with the (cid:127) On-line help MPLAB IDE memory display.  2000 Microchip Technology Inc. Preliminary DS40197B-page 55

PIC16HV540 9.4 MPLINK/MPLIB Linker/Librarian Interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- MPLINK is a relocatable linker for MPASM and cessors. The universal architecture of the MPLAB-ICE MPLAB-C17 and MPLAB-C18. It can link relocatable allows expansion to support new PICmicro microcon- objects from assembly or C source files along with pre- trollers. compiled libraries using directives from a linker script. The MPLAB-ICE Emulator System has been designed MPLIB is a librarian for pre-compiled code to be used as a real-time emulation system with advanced fea- with MPLINK. When a routine from a library is called tures that are generally found on more expensive from another source file, only the modules that contains development tools. The PC platform and Microsoft® that routine will be linked in with the application. This Windows 3.x/95/98 environment were chosen to best allows large libraries to be used efficiently in many dif- make these features available to you, the end user. ferent applications. MPLIB manages the creation and MPLAB-ICE 2000 is a full-featured emulator system modification of library files. with enhanced trace, trigger, and data monitoring fea- MPLINK features include: tures. Both systems use the same processor modules (cid:127) MPLINK works with MPASM and MPLAB-C17 and will operate across the full operating speed range and MPLAB-C18. of the PICmicro MCU. (cid:127) MPLINK allows all memory areas to be defined as 9.7 PICMASTER/PICMASTER CE sections to provide link-time flexibility. MPLIB features include: The PICMASTER system from Microchip Technology is a full-featured, professional quality emulator system. (cid:127) MPLIB makes linking easier because single librar- This flexible in-circuit emulator provides a high-quality, ies can be included instead of many smaller files. universal platform for emulating Microchip 8-bit (cid:127) MPLIB helps keep code maintainable by grouping PICmicro microcontrollers (MCUs). PICMASTER sys- related modules together. tems are sold worldwide, with a CE compliant model (cid:127) MPLIB commands allow libraries to be created available for European Union (EU) countries. and modules to be added, listed, replaced, deleted, or extracted. 9.8 ICEPIC 9.5 MPLAB-SIM Software Simulator ICEPIC is a low-cost in-circuit emulation solution for the Microchip Technology PIC16C5X, PIC16C6X, The MPLAB-SIM Software Simulator allows code PIC16C7X, and PIC16CXXX families of 8-bit one-time- development in a PC host environment by simulating programmable (OTP) microcontrollers. The modular the PICmicro series microcontrollers on an instruction system can support different subsets of PIC16C5X or level. On any given instruction, the data areas can be PIC16CXXX products through the use of examined or modified and stimuli can be applied from interchangeable personality modules or daughter a file or user-defined key press to any of the pins. The boards. The emulator is capable of emulating without execution can be performed in single step, execute until target application circuitry being present. break, or trace mode. 9.9 MPLAB-ICD In-Circuit Debugger MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPLAB-C18 and MPASM. The Soft- Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow- ware Simulator offers the flexibility to develop and erful, low-cost run-time development tool. This tool is debug code outside of the laboratory environment mak- based on the flash PIC16F877 and can be used to ing it an excellent multi-project software development develop for this and other PICmicro microcontrollers tool. from the PIC16CXXX family. MPLAB-ICD utilizes the In-Circuit Debugging capability built into the 9.6 MPLAB-ICE High Performance PIC16F87X. This feature, along with Microchip’s In-Cir- Universal In-Circuit Emulator with cuit Serial Programming protocol, offers cost-effective MPLAB IDE in-circuit flash programming and debugging from the graphical user interface of the MPLAB Integrated The MPLAB-ICE Universal In-Circuit Emulator is Development Environment. This enables a designer to intended to provide the product development engineer develop and debug source code by watching variables, with a complete microcontroller design tool set for single-stepping and setting break points. Running at PICmicro microcontrollers (MCUs). Software control of full speed enables testing hardware in real-time. The MPLAB-ICE is provided by the MPLAB Integrated MPLAB-ICD is also a programmer for the flash Development Environment (IDE), which allows editing, PIC16F87X family. “make” and download, and source debugging from a single environment. DS40197B-page 56 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 9.10 PRO MATE II Universal Programmer the PICDEM-1 board, on a PROMATE II or PICSTART-Plus programmer, and easily test firm- The PRO MATE II Universal Programmer is a full-fea- ware. The user can also connect the PICDEM-1 tured programmer capable of operating in stand-alone board to the MPLAB-ICE emulator and download the mode as well as PC-hosted mode. PRO MATE II is CE firmware to the emulator for testing. Additional proto- compliant. type area is available for the user to build some addi- The PRO MATE II has programmable VDD and VPP tional hardware and connect it to the microcontroller supplies which allows it to verify programmed memory socket(s). Some of the features include an RS-232 at VDD min and VDD max for maximum reliability. It has interface, a potentiometer for simulated analog input, an LCD display for instructions and error messages, push-button switches and eight LEDs connected to keys to enter commands and a modular detachable PORTB. socket assembly to support various package types. In 9.14 PICDEM-2 Low-Cost PIC16CXX stand-alone mode the PRO MATE II can read, verify or Demonstration Board program PICmicro devices. It can also set code-protect bits in this mode. The PICDEM-2 is a simple demonstration board that 9.11 PICSTART Plus Entry Level supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the Development System necessary hardware and software is included to The PICSTART programmer is an easy-to-use, low- run the basic demonstration programs. The user cost prototype programmer. It connects to the PC via can program the sample microcontrollers provided one of the COM (RS-232) ports. MPLAB Integrated with the PICDEM-2 board, on a PRO MATE II pro- Development Environment software makes using the grammer or PICSTART-Plus, and easily test firmware. programmer simple and efficient. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype PICSTART Plus supports all PICmicro devices with up area has been provided to the user for adding addi- to 40 pins. Larger pin count devices such as the tional hardware and connecting it to the microcontroller PIC16C92X, and PIC17C76X may be supported with socket(s). Some of the features include a RS-232 inter- an adapter socket. PICSTART Plus is CE compliant. face, push-button switches, a potentiometer for simu- 9.12 SIMICE Entry-Level lated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connec- Hardware Simulator tion to an LCD module and a keypad. SIMICE is an entry-level hardware development sys- 9.15 PICDEM-3 Low-Cost PIC16CXXX tem designed to operate in a PC-based environment Demonstration Board with Microchip’s simulator MPLAB-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology’s The PICDEM-3 is a simple demonstration board that MPLAB Integrated Development Environment (IDE) supports the PIC16C923 and PIC16C924 in the PLCC software. Specifically, SIMICE provides hardware sim- package. It will also support future 44-pin PLCC ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and microcontrollers with a LCD Module. All the neces- PIC16C5X families of PICmicro 8-bit microcontrollers. sary hardware and software is included to run the SIMICE works in conjunction with MPLAB-SIM to pro- basic demonstration programs. The user can pro- vide non-real-time I/O port emulation. SIMICE enables gram the sample microcontrollers provided with a developer to run simulator code for driving the target the PICDEM-3 board, on a PRO MATE II program- system. In addition, the target system can provide input mer or PICSTART Plus with an adapter socket, and to the simulator code. This capability allows for simple easily test firmware. The MPLAB-ICE emulator may and interactive debugging without having to manually also be used with the PICDEM-3 board to test firm- generate MPLAB-SIM stimulus files. SIMICE is a valu- ware. Additional prototype area has been provided to able debugging tool for entry-level system develop- the user for adding hardware and connecting it to the ment. microcontroller socket(s). Some of the features include 9.13 PICDEM-1 Low-Cost PICmicro an RS-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and Demonstration Board separate headers for connection to an external LCD The PICDEM-1 is a simple board which demonstrates module and a keypad. Also provided on the PICDEM-3 the capabilities of several of Microchip’s microcontrol- board is an LCD panel, with 4 commons and 12 seg- lers. The microcontrollers supported are: PIC16C5X ments, that is capable of displaying time, temperature (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, and day of the week. The PICDEM-3 provides an addi- PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and tional RS-232 interface and Windows 3.1 software for PIC17C44. All necessary hardware and software is showing the demultiplexed LCD signals on a PC. A sim- included to run basic demo programs. The users can ple serial interface allows the user to construct a hard- program the sample microcontrollers provided with ware demultiplexer for the LCD signals.  2000 Microchip Technology Inc. Preliminary DS40197B-page 57

PIC16HV540 9.16 PICDEM-17 The PICDEM-17 is an evaluation board that demon- strates the capabilities of several Microchip microcon- trollers, including PIC17C752, PIC17C756, PIC17C762, and PIC17C766. All necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. A programmed sample is included, and the user may erase it and program it with the other sample programs using the PRO MATE II or PICSTART Plus device programmers and easily debug and test the sample code. In addition, PICDEM-17 sup- ports down-loading of programs to and executing out of external FLASH memory on board. The PICDEM-17 is also usable with the MPLAB-ICE or PICMASTER emu- lator, and all of the sample programs can be run and modified using either emulator. Additionally, a gener- ous prototype area is available for user hardware. 9.17 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in trade- off analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system. 9.18 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS40197B-page 58 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 TABLE 9-1: DEVELOPMENT TOOLS FROM MICROCHIP 0152PCM Æ 7 7 6, XXXFRCM Æ Æ Æ Æ 4, 7 7 3, 7 XXXSCH Æ Æ Æ Æ 72, 5, 6 XXC39 4, //XXXXCC4522 Æ Æ 63, 6 2, 6 C 2XXC81CIP Æ Æ Æ Æ Æ Æ Æ 6 1 C PI h XX7C71CIP Æ Æ Æ Æ Æ Æ Æ Æ wit 1) 0 0 4 X4C71CIP Æ Æ Æ Æ Æ Æ Æ Æ 16 V D er ( g XX9C61CIP Æ Æ Æ Æ Æ Æ Æ Æ g u b e D XX8F61CIP Æ Æ Æ Æ Æ Æ cuit Cir n- D I X8C61CIP Æ Æ Æ Æ Æ Æ Æ Æ C ®-I B A L XX7C61CIP Æ Æ Æ Æ Æ Æ Æ MP e h e t X7C61CIP Æ Æ Æ Æ Æ *Æ Æ Æ †Æ†Æ us o w t o h X26F61CIP Æ Æ**Æ **Æ **Æ on n o ati m XXXC61CIP Æ Æ Æ Æ Æ Æ Æ Æ or nf or i X6C61CIP Æ Æ Æ Æ Æ *Æ Æ Æ †Æ m f o c p. hi c X5C61CIP Æ Æ Æ Æ Æ Æ Æ Æ Æ cro mi ww.e. X0X0X0C4211CCIPIP® MPLABIntegratedDevelopment EnvironmentÆÆ®MPLAB C17 Compiler ®MPLAB C18 Compiler MPASM/MPLINKÆÆ®MPLAB-ICEÆÆPICMASTER/PICMASTER-CEÆÆ ICEPICLow-CostIn-Circuit EmulatorÆ ®MPLAB-ICD In-Circuit Debugger PICSTARTPlus Low-Cost Universal Dev. KitÆÆ PRO MATE II Universal ProgrammerÆÆ SIMICEÆPICDEM-1 PICDEM-2 PICDEM-3 PICDEM-14AÆPICDEM-17 ® KLEvaluation KitEEOQ KL Transponder KitEEOQ microID™ Programmer’s Kit 125 kHz microID Developer’s Kit 125 kHz Anticollision microID Developer’s Kit 13.56 MHz Anticollision microID Developer’s Kit MCP2510 CAN Developer’s Kit Contact the Microchip Technology Inc. web site at wContact Microchip Technology Inc. for availability datDevelopment tool is available on select devices. slooT erawtfoS srotalumE reggubeD sremmargorP stiK lavE dna sdraoB omeD ***†  2000 Microchip Technology Inc. Preliminary DS40197B-page 59

PIC16HV540 NOTES: DS40197B-page 60 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 10.0 ELECTRICAL CHARACTERISTICS - PIC16HV540 Absolute Maximum Ratings† Ambient temperature under bias..............................................................................................................–20°C to +85°C Storage temperature............................................................................................................................. –65°C to +150°C Voltage on VDD with respect to VSS...................................................................................................................0 to +16V Voltage on MCLR with respect to VSS................................................................................................................0 to +14V Voltage on all other pins with respect to VSS.................................................................................–0.6V to (VDD + 0.6V) Total power dissipation(1).....................................................................................................................................800 mW Max. current out of VSS pin...................................................................................................................................150 mA Max. current into VDD pin......................................................................................................................................100 mA Max. current into an input pin (T0CKI only).....................................................................................................................±500 µA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20 mA Max. output current sunk by any I/O pin.................................................................................................................25 mA Max. output current sourced by any I/O pin............................................................................................................10 mA Max. output current sourced by a single I/O port A or B.........................................................................................40 mA Max. output current sourced by a single I/O port A or B ........................................................................................50 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL) 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2000 Microchip Technology Inc. Preliminary DS40197B-page 61

PIC16HV540 10.1 DC Characteristics: PIC16HV540-04, 20 (Commercial) PIC16HV540-04I, 20I (Industrial) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) Power Supply Pins –40°C ≤ TA ≤ +85°C (industrial) Characteristic Sym. Min. Typ.(1) Max. Units Conditions Supply Voltage VDD 3.5 15 V LP, XT and RC modes 4.5 — 15 V HS mode RAM Data Retention Voltage(2) VDR — 1.5* — V Device in SLEEP mode VDD start voltage to ensure VPOR — VSS — V See section on Power-on Reset for details. Power-on Reset VDD rise rate to ensure SVDD 0.05 V/ms See Section7.4 for details on Power-on Reset VDD Power-on Reset Supply Current(3) IDD HS option — 5 20 mA FOSC = 20 MHz, VDD = 15V, VREG = 5V XT and RC(4) options — 1.8 3.3 mA FOSC = 4 MHz, VDD = 15V, VREG = 5V LP option — 300 500 µA FOSC = 32 kHz, VDD = 15V, VREG = 5V, WDT disabled Power-down Current(5)(6) IPD — 4.5 20 µA VDD = 15V, VREG = 5V sleep timer enable, BOD disabled — 0.25 14 µA VDD = 15V, VREG = 3V sleep timer enable, BOD disabled — 1.8 10 µA VDD = 15V, VREG = 5V sleep timer disabled, BOD disabled — 1.4 5 µA VDD = 15V, VREG = 3V sleep timer disabled, BOD disabled Brown-out Current — 0.5 — µA VDD = 15V, VREG = 5V, BOD enabled Brown-out Detector Threshold BVDD 2.7 3.1 4.2 V VDD = 15V, VREG = 5V* (7) 1.8 2.2 2.8 V VDD = 15V, VREG = 3V* (7) Regulation Voltage VIO 2 3 4.5 V VDD = 15V, VREG = 3V, Unloaded outputs, SLEEP 4 5 6 V VDD = 15V, VREG = 5V, Unloaded outputs, SLEEP * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid- ance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in kΩ. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 6: The oscillator start-up time can be as much as 8 seconds for XT and LP oscillator selection, if the SLEEP mode is exited or during initial power-up. 7: See Section7.6.1 for additional information. DS40197B-page 62 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 10.2 DC Characteristics: PIC16HV540-04, 20 (Commercial) PIC16HV540-04I, 20I (Industrial) DC Characteristics Standard Operating Conditions (unless otherwise specified) All Pins Except Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) Power Supply Pins –40°C ≤ TA ≤ +85°C (industrial) Characteristic Sym. Min. Typ.(1) Max. Units Conditions Input Low Voltage VIL I/O Ports PORTA VSS — 0.10 VREG V Pin at Hi-impedance MCLR (Schmitt Trigger) VSS — 0.10 VREG V T0CKI (Schmitt Trigger) VSS — 0.10 VREG V OSC1 (Schmitt Trigger) VSS — 0.10 VREG V RC option only(4) OSC1 VSS — 0.3 VREG V HS, XT, and LP options I/O Ports PORTB VSS — 0.10 VREG V Input High Voltage VIH I/O Ports PORTA 0.25 VREG+0.8V — VREG V For all VREG MCLR (Schmitt Trigger) 0.85 VREG — VDD V T0CKI (Schmitt Trigger) 0.85 VREG — VDD V OSC1 (Schmitt Trigger) 4.5V — VDD V RC option only (VDD = 15V)(4) OSC1 4.5V — VDD V HS, XT, and LP options (VDD = 15V) I/O Ports PORTB 0.25 VREG+0.8V — VDD V Hysteresis of Schmitt VHYS 0.15 VREG* — — V Trigger inputs Input Leakage Current(3) IIL I/O Ports PORTA -1.0 0.5 +1.0 µA VSS ≤ VPIN ≤ VIO, Pin at Hi-impedance I/O Ports PORTB -1.0 0.5 +1.0 µA VSS ≤ VPIN ≤ VDD MCLR -5.0 +5.0 µA VPIN = VSS +0.25V(2) 0.5 +3.0 µA VPIN = VDD(2) T0CKI -3.0 0.5 +3.0 µA VSS ≤ VPIN ≤ VDD OSC1 -3.0 0.5 +3.0 µA VSS ≤ VPIN ≤ VDD, HS, XT, and LP options Output Low Voltage VOL I/O Ports PORTA — — 0.6 V VDD = 15V, VREG = 5V, IOL = 8.7 mA VDD = 15V, VREG = 3V, IOL = 5.0 mA OSC2/CLKOUT — — 0.6 V VDD = 15V, VREG = 5V, IOL = 1.2 mA, (RC option only) VDD = 15V, VREG = 3V, IOL = 1.0 mA, (RC option only) I/O Ports PORTB — — 0.6 V VDD = 15V, VREG = 5V, IOL = 3.0 mA VDD = 10V, VREG = 3V, IOL = 3.0 mA Output High Voltage VOH I/O ports(3) PORTA VREG-0.7 — — V VDD = 15V, VIO = 3V, IOH = -2.0 mA VDD = 15V, VIO = 5V, IOH = -3.0 mA OSC2/CLKOUT VREG-0.7 — — V VDD = 15V, VIO = 3V, IOH = -0.5 mA (RC option only) VDD = 15V, VIO = 5V, IOH = -1.0 mA (RC option only) I/O Ports PORTB VDD-0.7 — — V VDD = 15V, VIO = 5V, IOH = -5.4 mA Threshold Voltage I/O Ports PORTB [7] VLEV VDD-1.5 VDD-1.0 VDD-0.5 V VDD = 15V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels repre- sent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16HV540 be driven with external clock in RC mode.  2000 Microchip Technology Inc. Preliminary DS40197B-page 63

PIC16HV540 10.3 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 10-1: LOAD CONDITIONS - PIC16HV540 Pin CL = 50 pF for all pins except OSC2 CL 15 pF for OSC2 in XT, HS or LP options when external clock is used to drive OSC1 VSS DS40197B-page 64 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 10.4 Timing Diagrams and Specifications FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16HV540 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16HV540 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) Parameter Unit Sym. Characteristic Min. Typ.(1) Max. Conditions No. s FOSC External CLKIN Frequency(2) DC — 4.0 MHz RC osc mode DC — 2.0 MHz HS osc mode DC — 4.0 MHz XT osc mode DC — 200 kHz LP osc mode Oscillator Frequency(2) DC — 4.0 MHz RC osc mode 0.1 — 2.0 MHz HS osc mode 0.1 — 4.0 MHz XT osc mode 5 — 200 kHz LP osc mode 1 TOSC External CLKIN Period(2) 250 — — ns RC osc mode 250 — — ns HS osc mode 250 — — ns XT osc mode 5.0 — — µs LP osc mode Oscillator Period(2) 250 — — ns RC osc mode 250 — 10,000 ns HS osc mode 250 — 10,000 ns XT osc mode 50 — 200 µs LP osc mode 2 TCY Instruction Cycle Time(3) — 4/FOSC — — 3 TosL, Clock in (OSC1) Low or High Time 50* — — ns XT oscillator TosH 20* — — ns HS oscillator 2.0* — — µs LP oscillator 4 TosR, Clock in (OSC1) Rise or Fall Time — — 25* ns XT oscillator TosF — — 25* ns HS oscillator — — 50* ns LP oscillator * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at VREG = 5V, VDD = 9V, 25°C unless otherwise stated. These parame- ters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period.  2000 Microchip Technology Inc. Preliminary DS40197B-page 65

PIC16HV540 FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16HV540 Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 I/O Pin (input) 17 15 I/O Pin Old Value New Value (output) 20, 21 Note: All tests must be done with specified capacitive loads of 50 pF on I/O pins and CLKOUT. TABLE 10-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16HV540 Standard Operating Conditions (unless otherwise specified) AC Characteristics Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) Parameter Sym Characteristic Min Typ(1) Max Units No. 10 TosH2ckL OSC1↑ to CLKOUT↓(2) — 15 30** ns 11 TosH2ckH OSC1↑ to CLKOUT↑(2) — 15 30** ns 12 TckR CLKOUT rise time(2) — 5.0 15** ns 13 TckF CLKOUT fall time(2) — 5.0 15** ns 14 TckL2ioV CLKOUT↓ to Port out valid(2) — — 40** ns 17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid(3) — — 100* ns 18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid TBD — — ns (I/O in hold time) 19 TioV2osH Port input valid to OSC1↑ TBD — — ns (I/O in setup time) 20 TioR Port output rise time(3) — 10 25** ns 21 TioF Port output fall time(3) — 10 25** ns ** These parameters are design targets and are not tested. No characterization data available at this time. Note 1: Data in the Typical (“Typ”) column is at VREG = 5V, VDD = 9V, 25°C unless otherwise stated. These parame- ters are for design guidance only and are not tested. 2: Measurements are taken in RC Mode where CLKOUT output is 8 x TOSC. 3: See Figure10-1 for loading conditions. DS40197B-page 66 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 FIGURE 10-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16HV540 VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. FIGURE 10-5: BROWN-OUT DETECT TIMING VREG 35  2000 Microchip Technology Inc. Preliminary DS40197B-page 67

PIC16HV540 TABLE 10-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16HV540 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) Parameter No. Sym Characteristic Min. Typ.(1) Max. Units Conditions 30 TmcL MCLR Pulse Width (low) 2 — — µs VDD = 15V, VREG = 5V 31 Twdt Watchdog Timer Time-out Period 9.0* 18* 40* ms VDD = 15V, VREG = 5V 32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 15V, VREG = 5V, 0.55* 1.1* 2.5* RC mode 34 TioZ I/O Hi-impedance from MCLR Low — — 100* ns — Tpc Pin Change Pulse Width 2 — — µs 35 TBOD Brown-out Detect Pulse Width — 2 — µs VREG ≤ BVDD * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at VREG = 5V, VDD = 15V, 25°C unless otherwise stated. These param- eters are for design guidance only and are not tested. FIGURE 10-6: TIMER0 CLOCK TIMINGS - PIC16HV540 T0CKI 40 41 42 TABLE 10-4: TIMER0 CLOCK REQUIREMENTS - PIC16HV540 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) Parameter Sym Characteristic Min Typ(1) Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width- No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* — — ns Whichever is greater. N N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 3.8V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40197B-page 68 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 11.0 DC AND AC CHARACTERISTICS - PIC16HV540 The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for infor- mation only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ) respectively, where σ is standard deviation. FIGURE 11-1: TYPICAL RC OSCILLATOR FIGURE 11-2: TYPICAL RC OSCILLATOR FREQUENCY vs. FREQUENCY vs. VDD TEMPERATURE (CEXT = 20pF) 1.10 6000.0 1.08 REXT = 10k 1.06 5000.0 y VDD = 6V nc 1.04 e equ C) 1.02 VDD = 15V ) 4000.0 alized Fr (to 25° 100...099086 eq (kHz 3000.0 REXT = 24k m r F or 0.94 2000.0 N 0.92 0.90 1000.0 -40 0 25 55 85 Temp (C) REXT = 100k REXT = 390k 0.0 TABLE 11-1: RC OSCILLATOR 3.5 6 9 12 15 FREQUENCIES VDD (V) Average FOSC, VIO = 5V CEXT REXT FIGURE 11-3: TYPICAL RC OSCILLATOR 25°C, VDD = 6V 25°C, VDD = 15V FREQUENCY vs. VDD 20 pF 3.3k 4986.7 kHz (1) (CEXT = 100pF) 5k 4233.3 kHz (1) 2500.0 10k 2656.7 kHz 5150.0 kHz 24k 1223.3 kHz 3286.7 kHz 2000.0 REXT = 10k 100k 325.7 kHz 955.7 kHz 390k 79.0 kHz 250.7 kHz ) z 100 pF 3.3k 1916.7 kHz (1) H 1500.0 k 5k 1593.3 kHz (1) ( REXT = 24k q 10k 995.7 kHz 2086.7 kHz e 1000.0 r 24k 448.3 kHz 1210.0 kHz F 100k 116.0 kHz 355.7 kHz 500.0 390k 28.3 kHz 89.7 kHz REXT = 100k 300 pF 3.3k 744 kHz (1) REXT = 390k 0.0 5k 620.3 kHz (1) 10k 382.0 kHz 817.3 kHz 3.5 6 9 12 15 VDD (V) 24k 169.7 kHz 483.0 kHz 100k 44.1 kHz 135.7 kHz 390k 10.6 kHz 34.4 kHz Note 1: This combination of R, C and VDD draws too much current and prohibits oscillator operation.  2000 Microchip Technology Inc. Preliminary DS40197B-page 69

PIC16HV540 FIGURE 11-4: TYPICAL RC OSCILLATOR FIGURE 11-7: TYPICAL IPD vs. VDD, FREQUENCY vs. VDD WATCHDOG TIMER ENABLED (CEXT = 300pF) (VIO = 5V) 900.0 8.0 -40oC 800.0 REXT = 10k 7.0 700.0 6.0 Hz) 600.0 (uA)D 5.0 0oC k 500.0 IP ( REXT = 24k 4.0 eq 400.0 25oC Fr 300.0 3.0 85oC 200.0 2.0 REXT = 100k 6 9 12 15 100.0 REXT = 300k VDD (V) 0.0 3.5 6 9 12 15 FIGURE 11-8: MAXIMUM IPD vs. VDD, VDD (V) WATCHDOG TIMER ENABLED (VIO = 5V) 9 FIGURE 11-5: TYPICAL IPD vs. VDD, -40oC WATCHDOG TIMER 8 DISABLED (VIO = 5V) 85oC 7 4.0 3.5 -40oC 85oC (uA)D 6 IP 0oC 25oC 3.0 5 ) A u 25oC (2.5 4 PD 0oC I2.0 3 6 9 12 15 1.5 VDD (V) 1.0 FIGURE 11-9: TYPICAL IPD vs. VDD, 6 9 12 15 VDD (V) WATCHDOG TIMER DISABLED (VIO = 3V) FIGURE 11-6: MAXIMUM IPD vs. VDD, 4.50 WATCHDOG TIMER 4.00 DISABLED (VIO = 5V) -40oC 85oC 3.50 6 3.00 5.5 ) 25oC -40oC A 2.50 5 (u 0oC 85oC D 2.00 P 4.5 I 1.50 uA) 4 0oC 1.00 (D 3.5 IP 3 25oC 0.50 0.00 2.5 3.5 6 9 12 15 2 VDD (V) 1.5 1 6 9 12 15 VDD (V) DS40197B-page 70 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 FIGURE 11-10:MAXIMUM IPD vs. VDD, FIGURE 11-13:MAXIMUM IDD vs. WATCHDOG TIMER FREQUENCY, WATCHDOG DISABLED (VIO = 3V) TIMER DISABLED, RC MODE 5 (VDD = 15V, VIO = 5V, -40oC -40°C TO +85°C) 4.5 1000 4 900 3.5 A) 25oC 800 u (PD 3 0oC 700 I 600 2.5 A)500 µ 2 (D 400 85oC ID 1.5 300 200 1 3.5 6 9 12 15 100 VDD (V) 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (MHz) FIGURE 11-11:TYPICAL IPD vs. VDD, WATCHDOG TIMER ENABLED (VIO = 3V) FIGURE 11-14:MAXIMUM IDD vs. FREQUENCY, WATCHDOG 4.50 TIMER ENABLED, RC MODE 4.00 (VDD = 15V, VIO = 5V) -40oC 3.50 1000 A) 3.00 900 u (PD 2.50 800 I 0oC 700 2.00 600 25oC A)500 1.50 µ 1.00 85oC I (DD 400 300 3.5 6 9 12 15 200 VDD (V) 100 0 FIGURE 11-12:MAXIMUM IPD vs. VDD, 0.5 1 1.5 2 2.5 3 3.5 4 WATCHDOG TIMER ENABLED Frequency (MHz) (VIO = 3V) 66.0.0000 55.5.5000 55.0.0000 -40oC 44.5.5000 A) 44.0.0000 (uPD 3333..05..50000000 I 22.5.5000 0oC 25oC 22.0.0000 11.5.5000 11.0.0000 85oC 3.5 6 9 12 15 VDD (V)  2000 Microchip Technology Inc. Preliminary DS40197B-page 71

PIC16HV540 FIGURE 11-15:IOH vs. VOH ON PORTA, VDD = 15V (VIO = 5V) 0 -2 C 0° 4 -4 x - A) C C ma m 5° 5° I (OH -6 min 8 pical 2 y -8 t -10 -12 0 1 2 3 4 5 6 7 VOH (V) Note: Current being applied is being applied simultaneously to all 4 PORTA pins. FIGURE 11-16:IOH vs. VOH ON PORTA, VDD = 5V (VIO = 5V) 0 -2 -4 mA) 85°C I (OH -6 min 5°C 40°C -8 pical 2 max - y -10 t -12 0 1 2 3 4 5 6 VOH (V) Note: Current being applied is being applied simultaneously to all 4 PORTA pins. DS40197B-page 72 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 12.0 PACKAGING INFORMATION 12.1 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A c L A1 B1 β B p eB Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .890 .898 .905 22.61 22.80 22.99 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007  2000 Microchip Technology Inc. Preliminary DS40197B-page 73

PIC16HV540 12.2 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .291 .295 .299 7.39 7.49 7.59 Overall Length D .446 .454 .462 11.33 11.53 11.73 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .009 .011 .012 0.23 0.27 0.30 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051 DS40197B-page 74 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 12.3 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) E1 W2 D 2 n 1 W1 E A A2 c L A1 eB B1 B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .100 2.54 Top to Seating Plane A .170 .183 .195 4.32 4.64 4.95 Ceramic Package Height A2 .155 .160 .165 3.94 4.06 4.19 Standoff A1 .015 .023 .030 0.38 0.57 0.76 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Ceramic Pkg. Width E1 .285 .290 .295 7.24 7.37 7.49 Overall Length D .880 .900 .920 22.35 22.86 23.37 Tip to Seating Plane L .125 .138 .150 3.18 3.49 3.81 Lead Thickness c .008 .010 .012 0.20 0.25 0.30 Upper Lead Width B1 .050 .055 .060 1.27 1.40 1.52 Lower Lead Width B .016 .019 .021 0.41 0.47 0.53 Overall Row Spacing § eB .345 .385 .425 8.76 9.78 10.80 Window Width W1 .130 .140 .150 3.30 3.56 3.81 Window Length W2 .190 .200 .210 4.83 5.08 5.33 * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-036 Drawing No. C04-010  2000 Microchip Technology Inc. Preliminary DS40197B-page 75

PIC16HV540 12.4 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B 2 n 1 α c A A2 φ L A1 β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 20 20 Pitch p .026 0.65 Overall Height A .068 .073 .078 1.73 1.85 1.98 Molded Package Thickness A2 .064 .068 .072 1.63 1.73 1.83 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Overall Width E .299 .309 .322 7.59 7.85 8.18 Molded Package Width E1 .201 .207 .212 5.11 5.25 5.38 Overall Length D .278 .284 .289 7.06 7.20 7.34 Foot Length L .022 .030 .037 0.56 0.75 0.94 Lead Thickness c .004 .007 .010 0.10 0.18 0.25 Foot Angle φ 0 4 8 0.00 101.60 203.20 Lead Width B .010 .013 .015 0.25 0.32 0.38 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 DS40197B-page 76 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 12.5 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX PIC16HV540 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 9923NNN 18-Lead SOIC Example XXXXXXXXXXXX PIC16HV540 XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 9923NNN 18-Lead CERDIP Windowed Example XXXXXXXX PIC16HV5 XXXXXXXX XXXXXXXX YYWWNNN 9923NNN 20-Lead SSOP Example XXXXXXXXXXXX PIC16HV540 XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 9923NNN Legend: MM...M Microchip part number information XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2000 Microchip Technology Inc. Preliminary DS40197B-page 77

PIC16HV540 NOTES: DS40197B-page 78 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 INDEX O One-Time-Programmable (OTP) Devices ........................5 AAAALbpUspol icl.u.a.tt.ei.o .M.n..sa. .x..i..m......u..m...... ..R....a....t..i..n..g....s.... ...............................................................................................................................6..173 OOOsSPcCTilI lOasetNoler R cCteioognnisf itg.e.u.r. r.a....t..io....n....s.... .........................................................................................................................................313412 Architectural Overview ..................................................7 OscillHaSto r .T..y..p.e..s............................................................32 AssemMbPlAerSM Assembler .............................................55 LRPC .........................................................................................................................................3322 B XT .....................................................................32 Block Diagram BrowOPTTWn-iMInmoaC-RutCe1ct0r6h h0D/CdiW peo5. t.gDRXe.. Tce T.S.t si. Pme.e..rrt..eie ..eC..rs..s i..cr ...ac........ul....e....itr.... ................................................................................................................................................................................................................................................................32423.598015 PPPPPPPCIIIaaCCCcc DDDkk..aaEEE..gg.MMMei.n. ---.gM312.. .IaLLLn..rooof.ko.wwwi.rn.---m.gCCC. .aoooI.nt.sssi.fo.ttto .nPPP.r. mIII.CCC..a....1m1t..i66..oi..cCC..n..r X..Xo..... XXD......X ...De... m...De......meo......m o...B... ...ooB... ...aBo......rao...d...ra ...d...r.... d......... ....................................................1..........6..........,..... 355577577773 CCCalorcryk inbgit S..c..h..e.m...e.. ................................................................................................................1.07 PpiInC dSiTagArRaTms P..l.u..s. .E..n..t.r.y.. L..e..v..e.l. .D..e..v..e.l.o..p..m..e..n..t. .S..y.s..t.e..m.. ...............5.71 CCoodnefig Purroatteiocnti oBnit s. ....................................................................................................3..1..,. 4321 PORDev ice Reset Timer (DRT) .............................31,, 38 ConfiPguICra1t6ioCnR W54oCrd .........................................................................................................3311 PPDow e..r..-.O...n.. .R..e..s..e..t. .(.P...O..R...). ...........................................................3..1..,.. .3354,, 3461 TO .......................................................................34 41 DDDDDDCCeiegvv iCatie cnClheodaa pV rrAmarayCcer itb neeCittrt ih iSes.as.tu.ir c.pa..sp..c.. ot..e...r...rt... i...s....t....i....c........s.... ....-.... ....P........I....C........1........6........C........R........5........4........C........ .........................................................................................................656..92557 PPPPPPROOrroeowORRsgecr TTMaraBA-mlDAe roT..C ..wE...o...n...u... ...nM ...I...tI..e.o ...Urd... ...ne.......i v.........e..........r.....s.....a..........l..... .....P..........r.....o..........g..........r.....a.....m...............m...............e..........r..... ...........................................................................................................................11........99........,,.... 335412557168 E Q EElnehcatrPniccICael1d C6 WChaaRrt5ac4chtCdeo rgi.s. tT.i.ci.ms...e..r. .(.W...D..T..). ...............................................................3611 QQ ucicykc-leTsu r.n..a.r.o..u..n..d..-.P..r.o..d.u..c..t.io..n.. .(.Q..T..P..). .D...e.v..i.c.e..s.. ..................................1.50 EErxrtaetran a.l. .P..o.w...e..r.-.O..n.. .R..e..s..e.t. .C..i.r.c..u..it. ......................................................................3.62 RRReCa Od-sMciolldaitfoyr- W..r.i.t.e. ............................................................................................................3232 F Register File Map .......................................................11 Family of Devices FFeSaRtu Pr.eI.C.s.1 ..6....C....5....X.... ..................................................................................................................................................................................3..415 RReegseisStt ep..re.s.c.i.a..l .F..u..n..c..ti.o..n.. ........................................................................................3..1..,. 3141 FSR Register .............................................................17 SSEEVAL Evaluation and Programming System ...........58 IIIIIIIII///NNnnnOOOdssDD tt irIPrrPFFneuuro tcccoRer.tttgtr ii.esooDf.rag. nan.aci.. m st..CFiatn..em.l.y go..Arc.. wi ..ndl....e/...g.dP.... ....rCi.....ep.....s...o..e.....sn.....li.....isnn..........iigd...n....... eg...........r ......a..............t.......io..............n..............s....... ......................................................................................................................................................................................................................................................................................2111111320977095 SSSSSSSSTtoLeTppafEreeAActiwaccETTkiila aaiUPUz.lrl e S S.eFF..d ..ueSR.. ...Qnai...em...ctug..u.t...uiiir...csoe...lakt...nse...-t ... oTrR...o ...ruf....e ....(rtg....Mnh....i...a.seP....rt.... eo...L.C....ruA....Ps....nB.... U....d.....- -.....S....P.......I......Mr......o......)....d.. ......u.............c..............t.......io..............n.............. .......(.......S..............Q..............T..............P...................)......... D.....................e..............v.......i......3c.......e....71.....s.....,,..... 4153113.51361165 Instruction Set Summary .............................................43 T Timer0 KKeeLoq Evaluation and Programming Tools ...............58 STiwmitecrh0i n(gT MPRre0s)c Maloedr uAlses i.g..n..m..e..n..t. .......................................................2285 LLLooaadd inCgo nodf iPtioCn s.. ...................................................................................................................6146 TTiimmiinnTggM PDRaia0rga wrmaitmeht seE ra xSnteydrm nSabplo eClcoligofiycc kaa tni.od.n. .Ls.. o...a..d.... ..C....o....n....d....it..i..o....n....s.. ..........................662475 M TRIS Registers ..........................................................19 MCLR .................................................................................35 MemoPrIyC M16aCp5 4..s./.C...R..5..4..s./.C..5..5..s.. ...........................................................................1111 UUV Erasable Devices ....................................................5 MMePmLAoDPBrrayo t IagOn rtMraegmgearm naMitozeeardymt i Doo.nre.y .v. ..e...l...o......p......m......e......n......t... ...E......n......v...i...r...o......n......m......e......n......t... ...S......o...f...t...w.........a...r...e...... ...........51115111 WWWWW aaa.kktc.ee.h.--.duu..opp.g. ff. rr.Too..imm.m.. e.SS.r.LL .(.EEW..EE.D.PP.T. .o).... n..... P.........in...... ...C......h......a......n......g...e...... ...............................................................................................................34331195  2000 Microchip Technology Inc. Preliminary DS40197B-page 79

PIC16HV540 Period ................................................................39 Programming Considerations ...............................39 WWW, On-Line Support ................................................2 Z Zero bit .......................................................................7 DS40197B-page 80 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 ON-LINE SUPPORT Systems Information and Upgrade Hot Line Microchip provides on-line support on the Microchip The Systems Information and Upgrade Line provides World Wide Web (WWW) site. system users a listing of the latest versions of all of Microchip's development systems software products. The web site is used by Microchip as a means to make Plus, this line provides information on how customers files and information easily available to customers. To can receive any currently available upgrade kits.The view the site, the user must have access to the Internet Hot Line Numbers are: and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download 1-800-755-2345 for U.S. and most of Canada, and from our FTP site. 1-480-786-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 991103 The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User’s Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: (cid:127) Latest Microchip Press Releases Trademarks: The Microchip name, logo, PIC, PICmi- (cid:127) Technical Support Section with Frequently Asked cro, PICSTART, PICMASTER, PRO MATE and Questions MPLAB are registered trademarks of Microchip (cid:127) Design Tips Technology Incorporated in the U.S.A. and other countries. FlexROM and fuzzyLAB are trademarks (cid:127) Device Errata and SQTP is a service mark of Microchip in the (cid:127) Job Postings U.S.A. (cid:127) Microchip Consultant Program Member Listing All other trademarks mentioned herein are the prop- (cid:127) Links to other useful web sites related to erty of their respective companies. Microchip Products (cid:127) Conferences for products, Development Systems, technical information and more (cid:127) Listing of seminars and events  2000 Microchip Technology Inc. Preliminary DS40197B-page 81

PIC16HV540 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16HV540 Literature Number: DS40197B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS40197B-page 82 Preliminary  2000 Microchip Technology Inc.

PIC16HV540 PIC16HV540 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC16HV540 -XX X /XX XXX Pattern: QTP,SQTP, Code or Special Requirements JW = Windowed CERDIP SO = SOIC Package: P = PDIP SS = SSOP Temperature - = –0°C to +70°C Range: I = –40°C to +85°C Frequency 04 = 200 kHz (PICHV540-04) Range 04 = 4 MHz 20 = 20 MHz Device: PIC16HV540 :VDD range 3.5V to 15V PIC16HV540T :VDD range 3.5V to 15V (Tape/Reel) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277. 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2000 Microchip Technology Inc. Preliminary DS40197B-page 83

Note the following details of the code protection feature on PICmicro® MCUs. (cid:127) The PICmicro family meets the specifications contained in the Microchip Data Sheet. (cid:127) Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl- edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable”. (cid:127) Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, FilterLab, ensure that your application meets with your specifications. KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, No representation or warranty is given and no liability is PICSTART, PRO MATE, SEEVAL and The Embedded Control assumed by Microchip Technology Incorporated with respect Solutions Company are registered trademarks of Microchip Tech- to the accuracy or use of such information, or infringement of nology Incorporated in the U.S.A. and other countries. patents or other intellectual property rights arising from such dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, use or otherwise. Use of Microchip’s products as critical com- In-Circuit Serial Programming, ICSP, ICEPIC, microPort, ponents in life support systems is not authorized except with Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, express written approval by Microchip. No licenses are con- MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode veyed, implicitly or otherwise, under any intellectual property and Total Endurance are trademarks of Microchip Technology rights. Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2002 Microchip Technology Inc.

M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia Microchip Technology Japan K.K. Benex S-1 6F 2355 West Chandler Blvd. Microchip Technology Australia Pty Ltd 3-18-20, Shinyokohama Chandler, AZ 85224-6199 Suite 22, 41 Rawson Street Kohoku-Ku, Yokohama-shi Tel: 480-792-7200 Fax: 480-792-7277 Epping 2121, NSW Kanagawa, 222-0033, Japan Technical Support: 480-792-7627 Australia Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Web Address: http://www.microchip.com Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Rocky Mountain China - Beijing Korea 2355 West Chandler Blvd. Microchip Technology Consulting (Shanghai) Microchip Technology Korea Chandler, AZ 85224-6199 Co., Ltd., Beijing Liaison Office 168-1, Youngbo Bldg. 3 Floor Tel: 480-792-7966 Fax: 480-792-7456 Unit 915 Samsung-Dong, Kangnam-Ku Bei Hai Wan Tai Bldg. Seoul, Korea 135-882 Atlanta No. 6 Chaoyangmen Beidajie Tel: 82-2-554-7200 Fax: 82-2-558-5934 500 Sugar Mill Road, Suite 200B Beijing, 100027, No. China Singapore Atlanta, GA 30350 Tel: 86-10-85282100 Fax: 86-10-85282104 Microchip Technology Singapore Pte Ltd. Tel: 770-640-0034 Fax: 770-640-0307 China - Chengdu 200 Middle Road Boston #07-02 Prime Centre Microchip Technology Consulting (Shanghai) 2 Lan Drive, Suite 120 Singapore, 188980 Co., Ltd., Chengdu Liaison Office Westford, MA 01886 Tel: 65-6334-8870 Fax: 65-6334-8850 Rm. 2401, 24th Floor, Tel: 978-692-3848 Fax: 978-692-3821 Taiwan Ming Xing Financial Tower Chicago No. 88 TIDU Street Microchip Technology Taiwan 333 Pierce Road, Suite 180 Chengdu 610016, China 11F-3, No. 207 Itasca, IL 60143 Tel: 86-28-6766200 Fax: 86-28-6766599 Tung Hua North Road Tel: 630-285-0071 Fax: 630-285-0075 China - Fuzhou Taipei, 105, Taiwan Dallas Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Microchip Technology Consulting (Shanghai) 4570 Westgrove Drive, Suite 160 Co., Ltd., Fuzhou Liaison Office Addison, TX 75001 Unit 28F, World Trade Plaza EUROPE Tel: 972-818-7423 Fax: 972-818-2924 No. 71 Wusi Road Detroit Fuzhou 350001, China Denmark Tri-Atria Office Building Tel: 86-591-7503506 Fax: 86-591-7503521 Microchip Technology Nordic ApS 32255 Northwestern Highway, Suite 190 China - Shanghai Regus Business Centre Farmington Hills, MI 48334 Microchip Technology Consulting (Shanghai) Lautrup hoj 1-3 Tel: 248-538-2250 Fax: 248-538-2260 Co., Ltd. Ballerup DK-2750 Denmark Kokomo Room 701, Bldg. B Tel: 45 4420 9895 Fax: 45 4420 9910 2767 S. Albright Road Far East International Plaza France Kokomo, Indiana 46902 No. 317 Xian Xia Road Microchip Technology SARL Tel: 765-864-8360 Fax: 765-864-8387 Shanghai, 200051 Parc d’Activite du Moulin de Massy Los Angeles Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 43 Rue du Saule Trapu 18201 Von Karman, Suite 1090 China - Shenzhen Batiment A - ler Etage Irvine, CA 92612 Microchip Technology Consulting (Shanghai) 91300 Massy, France Tel: 949-263-1888 Fax: 949-263-1338 Co., Ltd., Shenzhen Liaison Office Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 New York Rm. 1315, 13/F, Shenzhen Kerry Centre, Germany 150 Motor Parkway, Suite 202 Renminnan Lu Microchip Technology GmbH Hauppauge, NY 11788 Shenzhen 518001, China Gustav-Heinemann Ring 125 Tel: 631-273-5305 Fax: 631-273-5335 Tel: 86-755-2350361 Fax: 86-755-2366086 D-81739 Munich, Germany San Jose Hong Kong Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Microchip Technology Inc. Microchip Technology Hongkong Ltd. 2107 North First Street, Suite 590 Unit 901-6, Tower 2, Metroplaza Microchip Technology SRL San Jose, CA 95131 223 Hing Fong Road Centro Direzionale Colleoni Tel: 408-436-7950 Fax: 408-436-7955 Kwai Fong, N.T., Hong Kong Palazzo Taurus 1 V. Le Colleoni 1 Toronto Tel: 852-2401-1200 Fax: 852-2401-3431 20041 Agrate Brianza Milan, Italy 6285 Northam Drive, Suite 108 India Tel: 39-039-65791-1 Fax: 39-039-6899883 Mississauga, Ontario L4V 1X5, Canada Microchip Technology Inc. United Kingdom Tel: 905-673-0699 Fax: 905-673-6509 India Liaison Office Divyasree Chambers Arizona Microchip Technology Ltd. 505 Eskdale Road 1 Floor, Wing A (A3/A4) No. 11, O’Shaugnessey Road Winnersh Triangle Bangalore, 560 025, India Wokingham Tel: 91-80-2290061 Fax: 91-80-2290062 Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 03/01/02  2002 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16HV540-20/SS PIC16HV540-20/SO PIC16HV540-20/P PIC16HV540T-04I/SO PIC16HV540T-04I/SS PIC16HV540-20I/SO PIC16HV540-20I/SS PIC16HV540T-04/SO PIC16HV540T-04/SS PIC16HV540T-20/SO PIC16HV540T-20/SS PIC16HV540/JW PIC16HV540-04I/P PIC16HV540-20I/P PIC16HV540T-20I/SS PIC16HV540T- 20I/SO PIC16HV540-04/SS PIC16HV540-04/SO PIC16HV540-04I/SO PIC16HV540-04I/SS PIC16HV540-04/P