PIC16F946 Data Sheet 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology Preliminary © 2005 Microchip Technology Inc. DS41265A

Note the following details of the code protection feature on Microchip devices: (cid:129) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:129) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:129) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:129) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:129) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PROMATE, PowerSmart, rfPIC, and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR WAR- registered trademarks of Microchip Technology Incorporated RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, in the U.S.A. and other countries. WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, PICMASTER, SEEVAL, SmartSensor and The Embedded MERCHANTABILITY OR FITNESS FOR PURPOSE. Control Solutions Company are registered trademarks of Microchip disclaims all liability arising from this information and Microchip Technology Incorporated in the U.S.A. its use. Use of Microchip’s products as critical components in Analog-for-the-Digital Age, Application Maestro, dsPICDEM, life support systems is not authorized except with express dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, written approval by Microchip. No licenses are conveyed, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial implicitly or otherwise, under any Microchip intellectual property Programming, ICSP, ICEPIC, Linear Active Thermistor, rights. MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary DS41265A-page ii © 2005 Microchip Technology Inc.

PIC16F946 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology High-Performance RISC CPU: Low-Power Features: (cid:129) Only 35 instructions to learn: (cid:129) Standby Current: - All single-cycle instructions except branches - <100nA @ 2.0V, typical (cid:129) Operating speed: (cid:129) Operating Current: - DC – 20MHz oscillator/clock input - 8.5μA @ 32kHz, 2.0V, typical - DC – 200ns instruction cycle - 100μA @ 1MHz, 2.0V, typical (cid:129) Program Memory Read (PMR) capability (cid:129) Watchdog Timer Current: - 1μA @ 2.0V, typical (cid:129) Interrupt capability (cid:129) 8-level deep hardware stack Peripheral Features: (cid:129) Direct, Indirect and Relative Addressing modes (cid:129) Liquid Crystal Display module: Special Microcontroller Features: - Up to 168 pixel drive capability (cid:129) Precision Internal Oscillator: - Selectable clock source - Factory calibrated to ±1% - Four commons - Software selectable frequency range of (cid:129) Up to 53 I/O pins and 1 input-only pin: 8MHz to 32kHz - High-current source/sink for direct LED drive - Software tunable - Interrupt-on-pin change - Two-Speed Start-up mode - Individually programmable weak pull-ups - Crystal fail detect for critical applications (cid:129) In-Circuit Serial Programming™ (ICSP™) via two - Clock mode switching during operation for pins power savings (cid:129) Analog comparator module with: (cid:129) Power-saving Sleep mode - Two analog comparators (cid:129) Wide operating voltage range (2.0V-5.5V) - Programmable on-chip voltage reference (cid:129) Industrial and Extended temperature range (CVREF) module (% of VDD) (cid:129) Power-on Reset (POR) - Comparator inputs and outputs externally accessible (cid:129) Power-up Timer (PWRT) and Oscillator Start-up (cid:129) A/D Converter: Timer (OST) - 10-bit resolution and 8 channels (cid:129) Brown-out Reset (BOR) with software control (cid:129) Timer0: 8-bit timer/counter with 8-bit option programmable prescaler (cid:129) Enhanced Low-Current Watchdog Timer (WDT) (cid:129) Enhanced Timer1: with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with - 16-bit timer/counter with prescaler software enable - External Gate Input mode - Option to use OSC1 and OSC2 as Timer1 (cid:129) Multiplexed Master Clear with pull-up/input pin oscillator if INTOSCIO or LP mode is (cid:129) Programmable code protection selected (cid:129) High-Endurance Flash/EEPROM cell: (cid:129) Timer2: 8-bit timer/counter with 8-bit period - 100,000 write Flash endurance register, prescaler and postscaler - 1,000,000 write EEPROM endurance (cid:129) Addressable Universal Synchronous - Flash/Data EEPROM retention: > 40 years Asynchronous Receiver Transmitter (AUSART) (cid:129) 2 Capture, Compare, PWM modules: - 16-bit Capture, max. resolution 12.5ns - 16-bit Compare, max. resolution 200ns - 10-bit PWM, max. frequency 20kHz (cid:129) Synchronous Serial Port (SSP) with I 2C™ Preliminary © 2005 Microchip Technology Inc. DS41265A-page 1

PIC16F946 Program Data Memory Memory LCD 10-bit A/D Timers Device I/O (segment CCP (ch) 8/16-bit Flash SRAM EEPROM drivers) (words) (bytes) (bytes) PIC16F946 8K 336 256 53 8 42 2 2/1 Pin Diagram – PIC16F946 TQFP DI/SDA/SEG8 CK/SCL/SEG9 CP1/SEG10 O/SEG11 EG18 EG17 X/DT/S X/CK/S 1CKI/C 1G/SD EG16 CP2 OM3 EG6 LCD3 LCD2 LCD1 S S R T T T S C C S V V V D5/ D4/ C7/ C6/ C5/ C4/ D3/ DD SS D2/ D1 D0/ C3/ C2/ C1/ C0/ R R R R R R R V V R R R R R R R 64 63 6261 60 59 58575655 54 53 52 51 5049 RD6/SEG19 1 48 RF7/SEG31 RD7/SEG20 2 47 RF6/SEG30 RG0/SEG36 3 46 RF5/SEG29 RG1/SEG37 4 45 RF4/SEG28 RG2/SEG38 5 44 RE7/SEG27 RG3/SEG39 6 43 RE6/SEG26 RG4/SEG40 7 42 RE5/SEG25 RG5/SEG41 8 PIC16F946 41 VSS VSS 9 40 RA6/OSC2/CLKO/T1OSO VDD 10 39 RA7/OSC1/CLKI/T1OSI RF0/SEG32 11 38 VDD RF1/SEG33 12 37 RE4/SEG24 RF2/SEG34 13 36 RE3/MCLR/VPP RF3/SEG35 14 35 RE2/AN7/SEG23 RB0/INT/SEG0 15 34 RE1/AN6/SEG22 RB1/SEG1 16 33 RE0/AN5/SEG21 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RB2/SEG2 RB3/SEG3VDD VSS RB4/COM0 RB5/COM1 B6/ICSPCLK/ICDCK/SEG14 7/ICSPDAT/ICDDAT/SEG13 AVSS AVDD RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/V-/COM2REFA3/AN3/C1+/V+/SEG15REF RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 R B R R Preliminary DS41265A-page 2 © 2005 Microchip Technology Inc.

PIC16F946 Table of Contents 1.0 Device Overview..........................................................................................................................................................................5 2.0 Memory Organization.................................................................................................................................................................11 3.0 I/O Ports.....................................................................................................................................................................................27 4.0 Clock Sources............................................................................................................................................................................71 5.0 Timer0 Module...........................................................................................................................................................................83 6.0 Timer1 Module With Gate Control..............................................................................................................................................87 7.0 Timer2 Module...........................................................................................................................................................................93 8.0 Comparator Module....................................................................................................................................................................95 9.0 Liquid Crystal Display (LCD) Driver Module.............................................................................................................................103 10.0 Programmable Low-Voltage Detect (PLVD) Module................................................................................................................131 11.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)..............................................................133 12.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................149 13.0 Data EEPROM and Flash Program Memory Control...............................................................................................................159 14.0 SSP Module Overview.............................................................................................................................................................165 15.0 Capture/Compare/PWM Modules............................................................................................................................................183 16.0 Special Features of the CPU....................................................................................................................................................191 17.0 Instruction Set Summary..........................................................................................................................................................213 18.0 Development Support...............................................................................................................................................................223 19.0 Electrical Specifications............................................................................................................................................................229 20.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................231 21.0 Packaging Information..............................................................................................................................................................255 Appendix A: Data Sheet Revision History..........................................................................................................................................259 Appendix B: Migrating From Other PICmicro® Devices....................................................................................................................259 Appendix C: Conversion Considerations...........................................................................................................................................260 Index..................................................................................................................................................................................................261 On-line Support..................................................................................................................................................................................269 Systems Information and Upgrade Hot Line......................................................................................................................................269 Reader Response..............................................................................................................................................................................270 Product Identification System............................................................................................................................................................271 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: (cid:129) Microchip’s Worldwide Web site; http://www.microchip.com (cid:129) Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 3

PIC16F946 NOTES: Preliminary DS41265A-page 4 © 2005 Microchip Technology Inc.

PIC16F946 1.0 DEVICE OVERVIEW This document contains device specific information for the PIC16F946. Additional information may be found in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023), downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16F946 devices are covered by this data sheet. It is available in a 64-pin package. Figure1-1 shows a block diagram of the device and Table1-1 shows the pinout description. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 5

PIC16F946 FIGURE 1-1: PIC16F946 BLOCK DIAGRAM PORTA Configuration RA0/AN0/C1-/SEG12 13 Data Bus 8 RA1/AN1/C2-/SEG7 Program Counter RA2/AN2/C2+/VREF-/COM2 Flash RA3/AN3/C1+/VREF+/SEG15 RA4/C1OUT/T0CKI/SEG4 8k x 14 RA5/AN4/C2OUT/SS/SEG5 Program 8-Level Stack (13-bit) RAM RA6/OSC2/CLKO/T1OSO Memory 336 x 8 bytes RA7/OSC1/CLKI/T1OSI File PORTB Registers RB0/INT/SEG0 Program 14 Bus Program Memory Read RAM Addr RB1/SEG1 (PRM) 9 RB2/SEG2 RB3/SEG3 Addr MUX RB4/COM0 Instruction Reg Direct Addr 7 Indirect RB5/COM1 8 Addr RB6/ICSPCLK/ICDCK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 FSR Reg PORTC RC0/VLCD1 8 Status Reg RC1/VLCD2 RC2/VLCD3 RC3/SEG6 Power-up RC4/T1G/SDO/SEG11 Timer 3 MUX RC5/T1CKI/CCP1/SEG10 RC6/TX/CK/SCK/SCL/SEG9 Oscillator RC7/RX/DT/SDI/SDA/SEG8 Instruction Start-up Timer PORTD Decode and Control Power-on ALU RD0/COM3 Reset RD1 OSC1/CLKI Watchdog 8 RD2/CCP2 Timing Timer RD3/SEG16 OSC2/CLKO Generation Brown-out W Reg RD4/SEG17 RD5/SEG18 Reset RD6/SEG19 RD7/SEG20 Internal PORTE Oscillator Block VDD VSS RE0/AN5/SEG21 RE1/AN6/SEG22 RE2/AN7/SEG23 RE3/MCLR/VPP RE4/SEG24 RE5/SEG25 RE6/SEG26 RE7/SEG27 PORTF RF0/SEG32 RF1/SEG33 RF2/SEG34 RF3/SEG35 RF4/SEG28 RF5/SEG29 RF6/SEG30 RF7/SEG31 PORTG RG0/SEG36 RG1/SEG37 RG2/SEG38 RG3/SEG39 RG4/SEG40 RG5/SEG41 Data EEPROM Timer0 Timer1 Timer2 10-bit A/D 256 bytes Addressable Comparators CCP1 CCP2 SSP BOR PLVD LCD USART Preliminary DS41265A-page 6 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 1-1: PIC16F946 PINOUT DESCRIPTIONS Input Output Name Function Description Type Type RA0/AN0/C1-/SEG12 RA0 TTL CMOS General purpose I/O. AN0 AN — Analog input Channel 0/Comparator 1 input – negative. C1- — AN Comparator 1 negative input. SEG12 — AN LCD analog output. RA1/AN1/C2-/SEG7 RA1 TTL CMOS General purpose I/O. AN1 AN — Analog input Channel 1/Comparator 2 input – negative. C2- — AN Comparator 2 negative input. SEG7 — AN LCD analog output. RA2/AN2/C2+/VREF-/COM2 RA2 TTL CMOS General purpose I/O. AN2 AN — Analog input Channel 2/Comparator 2 input – positive. C2+ — AN Comparator 2 positive input. VREF- AN — External Voltage Reference – negative. COM2 — AN LCD analog output. RA3/AN3/C1+/VREF+/SEG15 RA3 TTL CMOS General purpose I/O. AN3 AN — Analog input Channel 3/Comparator 1 input – positive. C1+ — AN Comparator 1 positive input. VREF+ AN — External Voltage Reference – positive. SEG15 — AN LCD analog output. RA4/C1OUT/T0CKI/SEG4 RA4 TTL CMOS General purpose I/O. C1OUT — CMOS Comparator 1 output. T0CKI ST — Timer0 clock input. SEG4 — AN LCD analog output. RA5/AN4/C2OUT/SS/SEG5 RA5 TTL CMOS General purpose I/O. AN4 AN — Analog input Channel 4. C2OUT — CMOS Comparator 2 output. SS TTL — Slave select input. SEG5 — AN LCD analog output. RA6/OSC2/CLKO/T1OSO RA6 TTL CMOS General purpose I/O. OSC2 — XTAL Crystal/Resonator. CLKO — CMOS TOSC/4 reference clock. T1OSO — XTAL Timer1 oscillator output. RA7/OSC1/CLKI/T1OSI RA7 TTL CMOS General purpose I/O. OSC1 XTAL — Crystal/Resonator. CLKI ST — Clock input. T1OSI XTAL — Timer1 oscillator input. RB0/INT/SEG0 RB0 TTL CMOS General purpose I/O. Individually enabled pull-up. INT ST — External interrupt pin. SEG0 — AN LCD analog output. RB1/SEG1 RB1 TTL CMOS General purpose I/O. Individually enabled pull-up. SEG1 — AN LCD analog output. RB2/SEG2 RB2 TTL CMOS General purpose I/O. Individually enabled pull-up. SEG2 — AN LCD analog output. Legend: AN = Analog input or output CMOS= CMOS compatible input or output D = Direct TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal Preliminary © 2005 Microchip Technology Inc. DS41265A-page 7

PIC16F946 TABLE 1-1: PIC16F946 PINOUT DESCRIPTIONS (CONTINUED) Input Output Name Function Description Type Type RB3/SEG3 RB3 TTL CMOS General purpose I/O. Individually enabled pull-up. SEG3 — AN LCD analog output. RB4/COM0 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. COM0 — AN LCD analog output. RB5/COM1 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. COM1 — AN LCD analog output. RB6/ICSPCLK/ICDCK/SEG14 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. ICSPCLK ST — ICSP™ clock. ICDCK ST — ICD clock I/O. SEG14 — AN LCD analog output. RB7/ICSPDAT/ICDDAT/SEG13 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. ICSPDAT ST CMOS ICSP Data I/O. ICDDAT ST CMOS ICD Data I/O. SEG13 — AN LCD analog output. RC0/VLCD1 RC0 ST CMOS General purpose I/O. VLCD1 AN — LCD analog input. RC1/VLCD2 RC1 ST CMOS General purpose I/O. VLCD2 AN — LCD analog input. RC2/VLCD3 RC2 ST CMOS General purpose I/O. VLCD3 AN — LCD analog input. RC3/SEG6 RC3 ST CMOS General purpose I/O. SEG6 — AN LCD analog output. RC4/T1G/SDO/SEG11 RC4 ST CMOS General purpose I/O. T1G ST — Timer1 gate input. SDO — CMOS Serial data output. SEG11 — AN LCD analog output. RC5/T1CKI/CCP1/SEG10 RC5 ST CMOS General purpose I/O. T1CKI ST — Timer1 clock input. CCP1 ST CMOS Capture 1 input/Compare 1 output/PWM 1 output. SEG10 — AN LCD analog output. RC6/TX/CK/SCK/SCL/SEG9 RC6 ST CMOS General purpose I/O. TX — CMOS USART asynchronous serial transmit. CK ST CMOS USART synchronous serial clock. SCK ST CMOS SPI™ clock. SCL ST CMOS I2C™ clock. SEG9 — AN LCD analog output. Legend: AN = Analog input or output CMOS= CMOS compatible input or output D = Direct TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal Preliminary DS41265A-page 8 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 1-1: PIC16F946 PINOUT DESCRIPTIONS (CONTINUED) Input Output Name Function Description Type Type RC7/RX/DT/SDI/SDA/SEG8 RC7 ST CMOS General purpose I/O. RX ST — USART asynchronous serial receive. DT ST CMOS USART synchronous serial data. SDI ST CMOS SPI™ data input. SDA ST CMOS I2C™ data. SEG8 — AN LCD analog output. RD0/COM3 RD0 ST CMOS General purpose I/O. COM3 — AN LCD analog output. RD1 RD1 ST CMOS General purpose I/O. RD2/CCP2 RD2 ST CMOS General purpose I/O. CCP2 ST CMOS Capture 2 input/Compare 2 output/PWM 2 output. RD3/SEG16 RD3 ST CMOS General purpose I/O. SEG16 — AN LCD analog output. RD4/SEG17 RD4 ST CMOS General purpose I/O. SEG17 — AN LCD analog output. RD5/SEG18 RD5 ST CMOS General purpose I/O. SEG18 — AN LCD analog output. RD6/SEG19 RD6 ST CMOS General purpose I/O. SEG19 — AN LCD analog output. RD7/SEG20 RD7 ST CMOS General purpose I/O. SEG20 — AN LCD analog output. RE0/AN5/SEG21 RE0 ST CMOS General purpose I/O. AN5 AN — Analog input Channel 5. SEG21 — AN LCD analog output. RE1/AN6/SEG22 RE1 ST CMOS General purpose I/O. AN6 AN — Analog input Channel 6. SEG22 — AN LCD analog output. RE2/AN7/SEG23 RE2 ST CMOS General purpose I/O. AN7 AN — Analog input Channel 7. SEG23 — AN LCD analog output. RE3/MCLR/VPP RE3 ST — Digital input only. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RE4/SEG24 RE4 ST CMOS General purpose I/O. SEG24 — AN LCD analog output. RE5/SEG25 RE5 ST CMOS General purpose I/O. SEG25 — AN LCD analog output. RE6/SEG26 RE6 ST CMOS General purpose I/O. SEG26 — AN LCD analog output. RE7/SEG27 RE7 ST CMOS General purpose I/O. SEG27 — AN LCD analog output. RF0/SEG32 RF0 ST CMOS General purpose I/O. SEG32 — AN LCD analog output. Legend: AN = Analog input or output CMOS= CMOS compatible input or output D = Direct TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal Preliminary © 2005 Microchip Technology Inc. DS41265A-page 9

PIC16F946 TABLE 1-1: PIC16F946 PINOUT DESCRIPTIONS (CONTINUED) Input Output Name Function Description Type Type RF1/SEG33 RF1 ST CMOS General purpose I/O. SEG33 — AN LCD analog output. RF2/SEG34 RF2 ST CMOS General purpose I/O. SEG34 — AN LCD analog output. RF3/SEG35 RF3 ST CMOS General purpose I/O. SEG35 — AN LCD analog output. RF4/SEG28 RF4 ST CMOS General purpose I/O. SEG28 — AN LCD analog output. RF5/SEG29 RF5 ST CMOS General purpose I/O. SEG29 — AN LCD analog output. RF6/SEG30 RF6 ST CMOS General purpose I/O. SEG30 — AN LCD analog output. RF7/SEG31 RF7 ST CMOS General purpose I/O. SEG31 — AN LCD analog output. RG0/SEG36 RG0 ST CMOS General purpose I/O. SEG36 — AN LCD analog output. RG1/SEG37 RG1 ST CMOS General purpose I/O. SEG37 — AN LCD analog output. RG2/SEG38 RG2 ST CMOS General purpose I/O. SEG38 — AN LCD analog output. RG3/SEG39 RG3 ST CMOS General purpose I/O. SEG39 — AN LCD analog output. RG4/SEG40 RG4 ST CMOS General purpose I/O. SEG10 — AN LCD analog output. RG5/SEG41 RG5 ST CMOS General purpose I/O. SEG41 — AN LCD analog output. VDD VDD D — Power supply for microcontroller. VSS VSS D — Ground reference for microcontroller. Legend: AN = Analog input or output CMOS= CMOS compatible input or output D = Direct TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal Preliminary DS41265A-page 10 © 2005 Microchip Technology Inc.

PIC16F946 2.0 MEMORY ORGANIZATION 2.2 Data Memory Organization The data memory is partitioned into multiple banks 2.1 Program Memory Organization which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). Bits RP0 The PIC16F946 has a 13-bit program counter capable and RP1 are bank select bits. of addressing an 8kx14 program memory space (0000h-1FFFh). The Reset vector is at 0000h and the RP0 RP1 (STATUS<6:5>) interrupt vector is at 0004h. = 00: → Bank 0 FIGURE 2-1: PROGRAM MEMORY MAP = 01: → Bank 1 AND STACK FOR THE = 10: → Bank 2 PIC16F946 = 11: → Bank 3 pc<12:0> Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special CALL, RETURN 13 Function Registers. Above the Special Function RETFIE, RETLW Registers are the General Purpose Registers, implemented as static RAM. All implemented banks Stack Level 1 contain Special Function Registers. Some frequently Stack Level 2 used Special Function Registers from one bank are mirrored in another bank for code reduction and Stack Level 8 quicker access. 2.2.1 GENERAL PURPOSE REGISTER Reset Vector 0000h FILE The register file is organized as 336x8 in the Interrupt Vector 0004h PIC16F946. Each register is accessed either directly or 0005h indirectly through the File Select Register (FSR) (see Page 0 Section2.5 “Indirect Addressing, INDF and FSR 07FFh Registers”). 0800h Page 1 2.2.2 SPECIAL FUNCTION REGISTERS On-chip 0FFFh Program The Special Function Registers are registers used by Memory 1000h the CPU and peripheral functions for controlling the Page 2 desired operation of the device (see Tables2-1, 17FFh 2-2,2-3 and 2-4). These registers are static RAM. 1800h The special registers can be classified into two sets: Page 3 core and peripheral. The Special Function Registers 1FFFh associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 11

PIC16F946 FIGURE 2-2: PIC16F946 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h WDTCON 105h TRISF 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h LCDCON 107h TRISG 187h PORTD 08h TRISD 88h LCDPS 108h PORTF 188h PORTE 09h TRISE 89h LVDCON 109h PORTG 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDATL 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADRL 10Dh EECON2(1) 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh 18Fh T1CON 10h OSCTUNE 90h LCDDATA0 110h LCDDATA12 190h TMR2 11h ANSEL 91h LCDDATA1 111h LCDDATA13 191h T2CON 12h PR2 92h LCDDATA2 112h LCDDATA14 192h SSPBUF 13h SSPADD 93h LCDDATA3 113h LCDDATA15 193h SSPCON 14h SSPSTAT 94h LCDDATA4 114h LCDDATA16 194h CCPR1L 15h WPUB 95h LCDDATA5 115h LCDDATA17 195h CCPR1H 16h IOCB 96h LCDDATA6 116h LCDDATA18 196h CCP1CON 17h CMCON1 97h LCDDATA7 117h LCDDATA19 197h RCSTA 18h TXSTA 98h LCDDATA8 118h LCDDATA20 198h TXREG 19h SPBRG 99h LCDDATA9 119h LCDDATA21 199h RCREG 1Ah 9Ah LCDDATA10 11Ah LCDDATA22 19Ah CCPR2L 1Bh 9Bh LCDDATA11 11Bh LCDDATA23 19Bh CCPR2H 1Ch CMCON0 9Ch LCDSE0 11Ch LCDSE3 19Ch CCP2CON 1Dh VRCON 9Dh LCDSE1 11Dh LCDSE4 19Dh ADRESH 1Eh ADRESL 9Eh LCDSE2 11Eh LCDSE5 19Eh ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh 20h A0h 120h General 1A0h Purpose General General Register General Purpose Purpose Purpose Register Register 80 Bytes Register 80 Bytes 80 Bytes 96 Bytes EFh 16Fh 1EFh accesses F0h accesses 170h accesses 1F0h 7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. Preliminary DS41265A-page 12 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 2-1: PIC16F946 SPECIAL REGISTERS SUMMARY BANK 0 Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR/BOR all other Reset Resets(1) Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 09h PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx uuuu uuuu 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF 0000 -0-0 0000 -0-0 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu 11h TMR2 Timer2 Module Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh(2) CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu 1Ch(2) CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu 1Dh(2) CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu 1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 13

PIC16F946 TABLE 2-2: PIC16F946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR/BOR all other Reset Resets(1) Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical xxxx xxxx xxxx xxxx register) 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 88h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111 89h TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3(3) TRISE2 TRISE1 TRISE0 1111 1111 1111 1111 8Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE 0000 -0-0 0000 -0-0 8Eh PCON — — — SBOREN — — POR BOR ---1 --qq ---u --uu 8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS(2) HTS LTS SCS -110 q000 -110 x000 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu 91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I 2 C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 0000 ---- 97h CMCON1 — — — — — — T1GSS C2SYNC ---- --10 ---- --10 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG SPBRG7 SPBRG6 SPBRG5 SPBRG4 SPBRG3 SPBRG2 SPBRG1 SPBRG0 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 9Dh VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu 9Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 --- Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section4.0 “Clock Sources”. 3: Bit is read-only; TRISE=1 always. Preliminary DS41265A-page 14 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 2-3: PIC16F946 SPECIAL REGISTERS SUMMARY BANK 2 Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR/BOR all other Reset Resets(1) Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 103h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 104h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 105h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 108h LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 0000 0000 109h LVDCON — — IRVST LVDEN — LVDL2 LVDL1 LVDL0 --00 -100 --00 -100 10Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Ch EEDATL EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 0000 0000 0000 0000 10Dh EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 0000 0000 0000 0000 10Eh EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000 10Fh EEADRH — — — EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---0 0000 ---0 0000 110h LCDDATA0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 111h LCDDATA1 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 112h LCDDATA2 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 113h LCDDATA3 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 114h LCDDATA4 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 115h LCDDATA5 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 116h LCDDATA6 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 117h LCDDATA7 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 118h LCDDATA8 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 119h LCDDATA9 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 11Ah LCDDATA10 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 11Bh LCDDATA11 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 11Ch LCDSE0(2) SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu 11Dh LCDSE1(2) SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu 11Eh LCDSE2(2) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu 11Fh — Unimplemented — — Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: This register is only initialized by a POR or BOR reset and is unchanged by other Resets. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 15

PIC16F946 TABLE 2-4: PIC16F946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR/BOR all other Reset Resets(1) Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical xxxx xxxx xxxx xxxx register) 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 182h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 183h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 184h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 185h TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 187h TRISG — — TRISG5 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 --11 1111 --11 1111 188h PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx xxxx uuuu uuuu 189h PORTG — — RG5 RG4 RG3 RG2 RG1 RG0 --xx xxxx --uu uuuu 18Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 18Ch EECON1 EEPGD — — — WRERR WREN WR RD 0--- x000 0--- q000 18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---- 190h LCDDATA12 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 191h LCDDATA13 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SE33 SEG32 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 192h LCDDATA14 — — — — — — SEG41 SEG40 ---- --xx ---- --uu COM0 COM0 193h LCDDATA15 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 194h LCDDATA16 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 195h LCDDATA17 — — — — — — SEG41 SEG40 ---- --xx ---- --uu COM1 COM1 196h LCDDATA18 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 197h LCDDATA19 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 198h LCDDATA20 — — — — — — SEG41 SEG40 ---- --xx ---- --uu COM2 COM2 199h LCDDATA21 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 19Ah LCDDATA22 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 19Bh LCDDATA23 — — — — — — SEG41 SEG40 ---- --xx ---- --uu COM3 COM3 19Ch LCDSE3(2) SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000 uuuu uuuu 19Dh LCDSE4(2) SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 0000 0000 uuuu uuuu 19Eh LCDSE5(2) — — — — — — SE41 SE40 ---- --00 ---- --uu 19Fh — Unimplemented — — Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: This register is only initialized by a POR or BOR reset and is unchanged by other Resets. Preliminary DS41265A-page 16 © 2005 Microchip Technology Inc.

PIC16F946 2.2.2.1 Status Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as The Status register, shown in Register2-1, contains: ‘000u u1uu’ (where u = unchanged). (cid:129) the arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, (cid:129) the Reset status SWAPF and MOVWF instructions are used to alter the (cid:129) the bank select bits for data memory (SRAM) Status register, because these instructions do not affect The Status register can be the destination for any any Status bits. For other instructions not affecting any instruction, like any other register. If the Status register Status bits (see Section17.0 “Instruction Set is the destination for an instruction that affects the Z, Summary”). DC or C bits, then the write to these three bits is Note1: The C and DC bits operate as a Borrow disabled. These bits are set or cleared according to the and Digit Borrow out bit, respectively, in device logic. Furthermore, the TO and PD bits are not subtraction. See the SUBLW and SUBWF writable. Therefore, the result of an instruction with the instructions for examples. Status register as destination may be different than intended. REGISTER 2-1: STATUS – STATUS REGISTER (ADDRESS: 03h, 83h, 103h OR 183h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 17

PIC16F946 2.2.2.2 Option Register Note: To achieve a 1:1 prescaler assignment for The Option register is a readable and writable register, TMR0, assign the prescaler to the WDT by which contains various control bits to configure: setting PSA bit to ‘1’ (OPTION_REG<3>). (cid:129) TMR0/WDT prescaler See Section5.4 “Prescaler”. (cid:129) External RB0/INT interrupt (cid:129) TMR0 (cid:129) Weak pull-ups on PORTB REGISTER 2-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h OR 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT/SEG0 pin 0 = Interrupt on falling edge of RB0/INT/SEG0 pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/C1OUT/T0CKI/SEG4 pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/C1OUT/T0CKI/SEG4 pin 0 = Increment on low-to-high transition on RA4/C1OUT/T0CKI/SEG4 pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 18 © 2005 Microchip Technology Inc.

PIC16F946 2.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt The INTCON register is a readable and writable condition occurs, regardless of the state of register, which contains the various enable and flag bits its corresponding enable bit or the global for TMR0 register overflow, PORTB change and enable bit, GIE (INTCON<7>). User external RB0/INT/SEG0 pin interrupts. software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh OR 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit 7 bit 0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 INTE: RB0/INT/SEG0 External Interrupt Enable bit 1 = Enables the RB0/INT/SEG0 external interrupt 0 = Disables the RB0/INT/SEF0 external interrupt bit 3 RBIE: PORTB Change Interrupt Enable bit(1) 1 = Enables the PORTB change interrupt 0 = Disables the PORTB change interrupt bit 2 T0IF: TMR0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: RB0/INT/SEG0 External Interrupt Flag bit 1 = The RB0/INT/SEG0 external interrupt occurred (must be cleared in software) 0 = The RB0/INT/SEG0 external interrupt did not occur bit 0 RBIF: PORTB Change Interrupt Flag bit 1 = When at least one of the PORTB <5:0> pins changed state (must be cleared in software) 0 = None of the PORTB <7:4> pins have changed state Note1: IOCB register must also be enabled. 2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 19

PIC16F946 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as Note: Bit PEIE (INTCON<6>) must be set to shown in Register2-1. enable any peripheral interrupt. REGISTER 2-4: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 20 © 2005 Microchip Technology Inc.

PIC16F946 2.2.2.5 PIE2 Register The PIE2 register contains the interrupt enable bits, as Note: Bit PEIE (INTCON<6>) must be set to shown in Register2-5. enable any peripheral interrupt. REGISTER 2-5: PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS: 8Dh) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE bit 7 bit 0 bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 C2IE: Comparator 2 Interrupt Enable bit 1 = Enables Comparator 2 interrupt 0 = Disables Comparator 2 interrupt bit 5 C1IE: Comparator 1 Interrupt Enable bit 1 = Enables Comparator 1 interrupt 0 = Disables Comparator 1 interrupt bit 4 LCDIE: LCD Module Interrupt Enable bit 1 = LCD interrupt is enabled 0 = LCD interrupt is disabled bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIE: Low Voltage Detect Interrupt Enable bit 1 = Enables LVD Interrupt 0 = Disables LVD Interrupt bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit (only available in PIC16F914/917) 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 21

PIC16F946 2.2.2.6 PIR1 Register The PIR1 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register2-6. condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-6: PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 EEIF: EE Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not started bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = The A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is not full bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The Transmission/Reception is complete (must be cleared in software) 0 = Waiting to Transmit/Receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture Mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Interrupt Flag bit 1 = A TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 22 © 2005 Microchip Technology Inc.

PIC16F946 2.2.2.7 PIR2 Register The PIR2 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register2-7. condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-7: PIR2 – PERIPHERAL INTERRUPT REQUEST REGISTER 2 (ADDRESS: 0Dh) R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 U-0 R/W-0 OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF bit 7 bit 0 bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 6 C2IF: Comparator 2 Interrupt Flag bit 1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed bit 5 C1IF: Comparator 1 Interrupt Flag bit 1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed bit 4 LCDIF: LCD Module Interrupt bit 1 = LCD has generated an interrupt 0 = LCD has not generated an interrupt bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit 1 = LVD has generated an interrupt 0 = LVD has not generated an interrupt bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit (only available in PIC16F914/917) Capture Mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 23

PIC16F946 2.2.2.8 PCON Register The Power Control (PCON) register (See Register2-8) contains flag bits to differentiate between a: (cid:129) Power-on Reset (POR ) (cid:129) Brown-out Reset (BOR ) (cid:129) Watchdog Timer Reset (WDT) (cid:129) External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register2-8. REGISTER 2-8: PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh) U-0 U-0 U-0 R/W-1 U-0 U-0 R/W-0 R/W-x — — — SBOREN — — POR BOR bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 SBOREN: Software BOR Enable bit(1) 1 = BOR enabled 0 = BOR disabled bit 3-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note1: BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 24 © 2005 Microchip Technology Inc.

PIC16F946 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low Note1: There are no Status bits to indicate stack byte comes from the PCL register, which is a readable overflow or stack underflow conditions. and writable register. The high byte (PC<12:8>) is not 2: There are no instructions/mnemonics directly readable or writable and comes from called PUSH or POP. These are actions PCLATH. On any Reset, the PC is cleared. Figure2-3 that occur from the execution of the CALL, shows the two situations for the loading of the PC. The RETURN, RETLW and RETFIE instruc- upper example in Figure2-3 shows how the PC is tions or the vectoring to an interrupt loaded on a write to PCL (PCLATH<4:0> → PCH). address. The lower example in Figure2-3 shows how the PC is loaded during a CALL or GOTO instruction 2.4 Program Memory Paging (PCLATH<4:3> → PCH). The PIC16F946 device is capable of addressing a FIGURE 2-3: LOADING OF PC IN continuous 8K word block of program memory. The DIFFERENT SITUATIONS CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program PCH PCL memory page. When doing a CALL or GOTO instruction, Instruction with 12 8 7 0 PCL as the upper 2 bits of the address are provided by PC Destination PCLATH<4:3>. When doing a CALL or GOTO instruction, PCLATH<4:0> 8 the user must ensure that the page select bits are 5 ALU Result programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or PCLATH interrupt) is executed, the entire 13-bit PC is POPed off the stack. Therefore, manipulation of the PCLATH<4:3> PCH PCL bits is not required for the RETURN instructions (which 12 11 10 8 7 0 POPs the address from the stack). PC GOTO, CALL Note: The contents of the PCLATH register are PCLATH<4:3> 11 unchanged after a RETURN or RETFIE 2 OPCODE<10:0> instruction is executed. The user must rewrite the contents of the PCLATH regis- PCLATH ter for any subsequent subroutine calls or GOTO instructions. 2.3.1 COMPUTED GOTO Example2-1 shows the calling of a subroutine in A computed GOTO is accomplished by adding an offset page1 of the program memory. This example assumes to the program counter (ADDWF PCL). When perform- that PCLATH is saved and restored by the Interrupt ing a table read using a computed GOTO method, care Service Routine (if interrupts are used). should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the EXAMPLE 2-1: CALL OF A SUBROUTINE Application Note AN556, “Implementing a Table Read” IN PAGE 1 FROM PAGE 0 (DS00556). ORG 0x500 BCF PCLATH,4 2.3.2 STACK BSF PCLATH,3 ;Select page 1 The PIC16F946 has an 8-levelx13-bit wide hardware ;(800h-FFFh) stack (see Figure2-1). The stack space is not part of CALL SUB1_P1 ;Call subroutine in either program or data space and the Stack Pointer is : ;page 1 (800h-FFFh) : not readable or writable. The PC is PUSHed onto the ORG 0x900 ;page 1 (800h-FFFh) stack when a CALL instruction is executed or an SUB1_P1 interrupt causes a branch. The stack is POPed in the : ;called subroutine event of a RETURN, RETLW or a RETFIE instruction ;page 1 (800h-FFFh) execution. PCLATH is not affected by a PUSH or POP : operation. RETURN ;return to ;Call subroutine The stack operates as a circular buffer. This means that ;in page 0 after the stack has been PUSHed eight times, the ninth ;(000h-7FFh) PUSH overwrites the value that was stored from the first PUSH. The tenth PUSH overwrites the second PUSH (and so on). Preliminary © 2005 Microchip Technology Inc. DS41265A-page 25

PIC16F946 2.5 Indirect Addressing, INDF and EXAMPLE 2-2: INDIRECT ADDRESSING FSR Registers MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM The INDF register is not a physical register. Addressing NEXTCLRF INDF ;clear INDF register the INDF register will cause indirect addressing. INCF FSR ;inc pointer BTFSS FSR,4 ;all done? Indirect addressing is possible by using the INDF GOTO NEXT ;no clear next register. Any instruction using the INDF register CONTINUE ;yes continue actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure2-4. A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example2-2. FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F946 Direct Addressing Indirect Addressing RP1 RP0 6 From Opcode 0 IRP 7 File Select Register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 180h Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note: For memory map detail, see Figure2-1. Preliminary DS41265A-page 26 © 2005 Microchip Technology Inc.

PIC16F946 3.0 I/O PORTS EXAMPLE 3-1: INITIALIZING PORTA BCF STATUS,RP0 ;Bank 0 This device includes four 8-bit port registers along with BCF STATUS,RP1 ; their corresponding TRIS registers and one four bit CLRF PORTA ;Init PORTA port: BSF STATUS,RP0 ;Bank 1 (cid:129) PORTA and TRISA BCF STATUS,RP1 ; MOVLW 07h ;Set RA<2:0> to (cid:129) PORTB and TRISB MOVWF CMCON0 ;digital I/O (cid:129) PORTC and TRISC CLF ANSEL ;Make all PORTA I/O (cid:129) PORTD and TRISD MOVLW F0h ;Set RA<7:4> as inputs MOVWF TRISA ;and set RA<3:0> (cid:129) PORTE and TRISE ; as outputs (cid:129) PORTF and TRISF BCF STATUS,RP0 ;Bank 0 (cid:129) PORTG and TRISG BCF STATUS,RP1 ; 3.1 PORTA and TRISA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register3-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Example3-1 shows how to initialize PORTA. Five of the pins of PORTA can be configured as analog inputs. These pins, RA5 and RA<3:0>, are configured as analog inputs on device power-up and must be reconfigured by the user to be used as I/O’s. This is done by writing the appropriate values to the CMCON0 and ANSEL registers (see Example3-1). Reading the PORTA register (Register3-1) reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. The TRISA register controls the direction of the PORTApins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. Note1: The CMCON0 (9Ch) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. 2: Analog lines that carry LCD signals (i.e., SEGx, COMy, where x and y are segment and common identifiers) are shown as direct connections to the device pins. The signals are outputs from the LCD module and may be tri-stated, depending on the configuration of the LCD module. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 27

PIC16F946 REGISTER 3-1: PORTA – PORTA REGISTER (ADDRESS: 05h) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 bit 7-0 RA<7:0>: PORTA I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is <VIL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 3-2: TRISA – PORTA TRI-STATE REGISTER (ADDRESS: 85h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 bit 7-0 TRISA<7:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note: TRISA<7:6> always reads ‘1’ in XT, HS and LP OSC modes. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 28 © 2005 Microchip Technology Inc.

PIC16F946 3.1.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet. 3.1.1.1 RA0/AN0/C1-/SEG12 Figure3-1 shows the diagram for this pin. The RA0/AN0/C1-/SEG12 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog input for the A/D (cid:129) an analog input for Comparator 1 (cid:129) an analog output for the LCD FIGURE 3-1: BLOCK DIAGRAM OF RA0/AN0/C1-/SEG12 Data Bus D Q WR PORTA VDD CK Q Data Latch D Q I/O Pin WR TRISA CK Q TRIS Latch Analog Input or SE12 and LCDEN TTL RD TRISA SE12 and LCDEN Input Buffer RD PORTA SE12 and LCDEN SEG12 To A/D Converter or Comparator Preliminary © 2005 Microchip Technology Inc. DS41265A-page 29

PIC16F946 3.1.1.2 RA1/AN1/C2-/SEG7 Figure3-2 shows the diagram for this pin. The RA1/AN1/C2-/SEG7 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog input for the A/D (cid:129) an analog input for Comparator 2 (cid:129) an analog output for the LCD FIGURE 3-2: BLOCK DIAGRAM OF RA1/AN1/C2-/SEG7 Data Bus D Q WR PORTA VDD CK Q Data Latch D Q I/O Pin WR TRISA CK Q TRIS Latch Analog Input or SE7 and LCDEN TTL RD TRISA SE7 and LCDEN Input Buffer RD PORTA SE7 and LCDEN SEG7 To A/D Converter or Comparator Preliminary DS41265A-page 30 © 2005 Microchip Technology Inc.

PIC16F946 3.1.1.3 RA2/AN2/C2+/VREF-/COM2 Figure3-3 shows the diagram for this pin. The RA2/AN2/C2+/VREF-/COM2 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog input for the A/D (cid:129) an analog input for Comparator 2 (cid:129) a voltage reference input for the A/D (cid:129) an analog output for the LCD FIGURE 3-3: BLOCK DIAGRAM OF RA2/AN2/C2+/VREF-/COM2 Data Bus D Q WR PORTA CK Q VDD Data Latch D Q I/O Pin WR TRISA CK Q TRIS Latch Analog Input or LCDEN and LMUX<1:0> = 1X RD TRISA LCDEN and TTL LMUX<1:0> = 1X Input Buffer RD PORTA LCDEN and LMUX<1:0> = 1X COM2 To A/D Converter or Comparator To A/D Module VREF- Input Preliminary © 2005 Microchip Technology Inc. DS41265A-page 31

PIC16F946 3.1.1.4 RA3/AN3/C1+/VREF+/SEG15 Figure3-4 shows the diagram for this pin. The RA3/AN3/C1+/VREF+/COM3/SEG15 pin is configurable to function as one of the following: (cid:129) a general purpose input (cid:129) an analog input for the A/D (cid:129) a voltage reference input for the A/D (cid:129) analog outputs for the LCD FIGURE 3-4: BLOCK DIAGRAM OF RA3/AN3/C1+/VREF+/SEG15 Data Bus D Q VDD WR PORTA CK Q Data Latch D QQ I/O Pin WR TRISA CK QQ VSS TRIS Latch Analog Input or SE15 and LCDEN TTL RD TRISA SE15 and LCDEN Input Buffer RD PORTA SE15 and LCDEN SEG15 To A/D Module VREF+ Input Preliminary DS41265A-page 32 © 2005 Microchip Technology Inc.

PIC16F946 3.1.1.5 RA4/C1OUT/T0CKI/SEG4 Figure3-5 shows the diagram for this pin. The RA4/C1OUT/T0CKI/SEG4 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) a digital output from Comparator 1 (cid:129) a clock input for TMR0 (cid:129) an analog output for the LCD FIGURE 3-5: BLOCK DIAGRAM OF RA4/C1OUT/T0CKI/SEG4 CM<2:0> = 110 or 101 C1OUT 1 Data Bus D Q 0 VDD WR PORTA CK Q Data Latch D Q I/O Pin WR TRISA CK Q VSS TRIS Latch Analog Input or SE4 and LCDEN TTL RD TRISA SE4 and LCDEN Input Buffer RD PORTA SE4 and LCDEN T0CKI Schmitt Trigger SE4 and LCDEN SEG4 Preliminary © 2005 Microchip Technology Inc. DS41265A-page 33

PIC16F946 3.1.1.6 RA5/AN4/C2OUT/SS/SEG5 Figure3-6 shows the diagram for this pin. The RA5/AN4/C2OUT/SS/SEG5 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) a digital output from Comparator 2 (cid:129) a slave select input (cid:129) an analog output for the LCD (cid:129) an analog input for the A/D FIGURE 3-6: BLOCK DIAGRAM OF RA5/AN4/C2OUT/SS/SEG5 CM<2:0> = 110 or 101 C2OUT 1 Data Bus D Q 0 VDD WR PORTA CK Q Data Latch D Q I/O Pin WR TRISA CK Q VSS TRIS Latch Analog Input or SE5 and LCDEN TTL RD TRISA SE5 and LCDEN RD PORTA To SS Input SE5 and LCDEN SEG5 AN4 Preliminary DS41265A-page 34 © 2005 Microchip Technology Inc.

PIC16F946 3.1.1.7 RA6/OSC2/CLKO/T1OSO Figure3-7 shows the diagram for this pin. The RA6/OSC2/CLKO/T1OSO pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) a crystal/resonator connection (cid:129) a clock output (cid:129) a TMR1 oscillator connection FIGURE 3-7: BLOCK DIAGRAM OF RA6/OSC2/CLKO/T1OSO From OSC1 Oscillator FOSC = 1x1 Circuit CLKO (FOSC/4) 1 Data Bus D Q 0 VDD WR PORTA CK Q Data Latch D Q RA6/OSC2/ CLKO/T1OSO Pin WR TRISA CK Q VSS FOSC = 00x, 010 TRIS Latch FOSC = 00x, 010 or T1OSCEN or T1OSCEN TTL Input Buffer RD TRISA RD PORTA Preliminary © 2005 Microchip Technology Inc. DS41265A-page 35

PIC16F946 3.1.1.8 RA7/OSC1/CLKI/T1OSI Figure3-8 shows the diagram for this pin. The RA7/OSC1/CLKI/T1OSI pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) a crystal/resonator connection (cid:129) a clock input (cid:129) a TMR1 oscillator connection FIGURE 3-8: BLOCK DIAGRAM OF RA7/OSC1/CLKI/T1OSI From OSC1 Oscillator Circuit FOSC = 011 Data Bus D Q WR PORTA CK Q VDD Data Latch D Q RA7/OSC1/ CLKI/T1OSI WR TRISA Pin CK Q FOSC = 10x TRIS Latch FOSC = 10x TTL Input Buffer RD TRISA RD PORTA TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on all Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets 05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu 10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 81h/181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 9Ch CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 11Ch LCDSE0(1) SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu 11Dh LCDSE1(1) SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: This register is only initialized by a POR or BOR and is unchanged by other Resets. Preliminary DS41265A-page 36 © 2005 Microchip Technology Inc.

PIC16F946 3.2 PORTB and TRISB Registers 3.3 Additional PORTB Pin Functions PORTB is a general purpose I/O port with similar RB<7:6> are used as data and clock signals, respectively, functionality as the PIC16F914. All PORTB pins can have for both serial programming and the in-circuit debugger a weak pull-up feature, and PORTB<7:4> implements an features on the device. Also, RB0 can be configured as an interrupt-on-input change function. external interrupt input. PORTB is also used for the Serial Flash programming 3.3.1 WEAK PULL-UPS interface. Each of the PORTB pins has an individually configurable Note: Analog lines that carry LCD signals internal weak pull-up. Control bits WPUB<7:0> enable or (i.e., SEGx, COMy, where x and y are seg- disable each pull-up. Refer to Register3-6. Each weak ment and common identifiers) are shown pull-up is automatically turned off when the port pin is as direct connections to the device pins. configured as an output. The pull-ups are disabled on a The signals are outputs from the LCD Power-on Reset by the RBPU bit (OPTION_REG<7>). module and may be tri-stated, depending on the configuration of the LCD module. 3.3.2 INTERRUPT-ON-CHANGE Four of the PORTB pins are individually configurable EXAMPLE 3-2: INITIALIZING PORTB as an interrupt-on-change pin. Control bits IOCB<7:4> BCF STATUS,RP0 ;Bank 0 enable or disable the interrupt function for each pin. BCF STATUS,RP1 ; Refer to Register3-5. The interrupt-on-change feature CLRF PORTB ;Init PORTB is disabled on a Power-on Reset. BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 ; For enabled interrupt-on-change pins, the values are MOVLW FFh ;Set RB<7:0> as inputs compared with the old value latched on the last read of MOVWF TRISB ; PORTB. The ‘mismatch’ outputs of the last read are BCF STATUS,RP0 ;Bank 0 OR’d together to set the PORTB Change Interrupt Flag BCF STATUS,RP1 ; bit (RBIF) in the INTCON register (Register2-3). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) Any read or write of PORTB. This will end the mismatch condition. b) Clear the flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading or writing PORTB will end the mismatch con- dition and allow flag bit RBIF to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After these Resets, the RBIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not getset. Furthermore, since a read or write on a port affects all bits of that port, care must be taken when using multiple pins in Interrupt-on-change mode. Changes on one pin may not be seen while servicing changes on another pin. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 37

PIC16F946 REGISTER 3-3: PORTB – PORTB REGISTER (ADDRESS: 06h OR 106h) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 bit 7-0 RB<7:0>: PORTB I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is <VIL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 3-4: TRISB – PORTB TRI-STATE REGISTER (ADDRESS: 86h, 186h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output Note: TRISB<7:6> always reads ‘1’ in XT, HS and LP OSC modes. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 3-5: IOCB – PORTB INTERRUPT-ON-CHANGE REGISTER (ADDRESS: 96h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IOCB7 IOCB6 IOCB5 IOCB4 — — — — bit 7 bit 0 bit 7-4 IOCB<7:4>: Interrupt-on-Change bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled bit 3-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 38 © 2005 Microchip Technology Inc.

PIC16F946 REGISTER 3-6: WPUB – WEAK PULL-UP REGISTER (ADDRESS: 95h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 bit 7-0 WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note1: Global RBPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISB<7:0> = 0). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 39

PIC16F946 3.3.3 PIN DESCRIPTIONS AND DIAGRAMS Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the LCD or interrupts, refer to the appropriate section in this data sheet. 3.3.3.1 RB0/INT/SEG0 Figure3-9 shows the diagram for this pin. The RB0/INT/SEG0 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an external edge triggered interrupt (cid:129) an analog output for the LCD 3.3.3.2 RB1/SEG1 Figure3-9 shows the diagram for this pin. The RB1/SEG1 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.3.3.3 RB2/SEG2 Figure3-9 shows the diagram for this pin. The RB2/SEG2 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.3.3.4 RB3/SEG3 Figure3-9 shows the diagram for this pin. The RB3/SEG3 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD Preliminary DS41265A-page 40 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 3-9: BLOCK DIAGRAM OF RB<3:0> SE<3:0> VDD RBPU(1) Weak VDD P Pull-up Data Bus D Q I/O Pin WR PORTB CK Data Latch D Q WR TRISB CK TRIS Latch SE<3:0> and LCDEN TTL Input Buffer RD TRISB RD PORTB SE<3:0> and LCDEN SEG<3:0> SE0 and LCDEN INT(2) Schmitt Trigger Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2: RB0 only. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 41

PIC16F946 3.3.3.5 RB4/COM0 Figure3-10 shows the diagram for this pin. The RB4/COM0 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD FIGURE 3-10: BLOCK DIAGRAM OF RB4/COM0 LCDEN VDD RBPU(1) Weak VDD P Pull-up Data Bus D Q I/O Pin WR PORTB CK Data Latch D Q WR TRISB CK TRIS Latch LCDEN TTL Input Buffer RD TRISB Q D RD PORTB LCDEN EN RD PORTB Set RBIF Q D From other RB<7:4> pins EN FOSC/4 LCDEN COM0 Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. Preliminary DS41265A-page 42 © 2005 Microchip Technology Inc.

PIC16F946 3.3.3.6 RB5/COM1 Figure3-11 shows the diagram for this pin. The RB5/COM1 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD FIGURE 3-11: BLOCK DIAGRAM OF RB5/COM1 ≠ LCDEN and LMUX<1:0> 00 VDD RBPU(1) Weak VDD P Pull-up Data Bus D Q I/O Pin WR PORTB CK Data Latch D Q WR TRISB CK TRIS Latch ≠ LCDEN and LMUX<1:0> 00 TTL Input Buffer RD TRISB Q D RD PORTB EN FOSC/4 Set RBIF Q D From other LCDEN and RB<7:4> pins ≠ LMUX<1:0> 00 EN RD PORTB ≠ LCDEN and LMUX<1:0> 00 COM1 Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 43

PIC16F946 3.3.3.7 RB6/ICSPCLK/ICDCK/SEG14 Figure3-12 shows the diagram for this pin. The RB6/ICSPCLK/ICDCK/SEG14 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an In-Circuit Serial Programming™ clock (cid:129) an ICD clock I/O (cid:129) an analog output for the LCD FIGURE 3-12: BLOCK DIAGRAM OF RB6/ICSPCLK/ICDCK/SEG14 Program Mode/ICD VDD RBPU(1) Weak P SE14 and LCDEN Pull-up VDD Data Bus D Q I/O Pin WR PORTB CK Data Latch D Q WR TRISB CK TRIS Latch TTL Input Buffer SE14 and LCDEN RD TRISB Q D RD PORTB EN RD PORTB Set RBIF Q D From other Program Mode/ICD RB<7:4> pins EN FOSC/4 SE14 and LCDEN PGC Schmitt Trigger Buffer SE14 and LCDEN SEG14 Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. Preliminary DS41265A-page 44 © 2005 Microchip Technology Inc.

PIC16F946 3.3.3.8 RB7/ICSPDAT/ICDDAT/SEG13 Figure3-13 shows the diagram for this pin. The RB7/ICSPDAT/ICDDAT/SEG13 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an In-Circuit Serial Programming™ I/O (cid:129) an ICD data I/O (cid:129) an analog output for the LCD FIGURE 3-13: BLOCK DIAGRAM OF RB7/ICSPDAT/ICDDAT/SEG13 PORT/Program Mode/ICD PGD VDD RBPU(1) SE13 and LCDEN Weak P Pull-up VDD Data Bus 1 D Q 0 I/O Pin WR PORTB CK Data Latch D Q WR TRISB CK TRIS Latch 0 PGD DRVEN 1 TTL Input Buffer RD TRISB SE13 and LCDEN Q D RD PORTB EN RD PORTB Set RBIF Q D From other Program Mode/ICD RB<7:4> pins EN FOSC/4 SE13 and LCDEN PGD Schmitt Trigger Buffer SE13 and LCDEN SEG13 Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 45

PIC16F946 TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on all Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets 06h/106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h/186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 0Bh/8Bh/ INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh/18Bh 95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 0000 ---- 107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 11Ch LCDSE0(1) SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu 11Dh LCDSE1(1) SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. Note 1: This register is only initialized by a POR or BOR and is unchanged by other Resets. Preliminary DS41265A-page 46 © 2005 Microchip Technology Inc.

PIC16F946 3.4 PORTC and TRISC Registers EXAMPLE 3-3: INITIALIZING PORTC BCF STATUS,RP0 ;Bank 0 PORTC is an 8-bit bidirectional port. PORTC is BCF STATUS,RP1 ; multiplexed with several peripheral functions. PORTC CLRF PORTC ;Init PORTC pins have Schmitt Trigger input buffers. BSF STATUS,RP0 ;Bank 1 All PORTC pins have latch bits (PORTC register). BCF STATUS,RP1 ; They, when written, will modify the contents of the MOVLW FFh ;Set RC<7:0> as inputs PORTC latch; thus, modifying the value driven out on MOVWF TRISC ; BCF STATUS,RP0 ;Bank 2 a pin if the corresponding TRISC bit is configured for BSF STATUS,RP1 ; output. CLRF LCDCON ;Disable VLCD<3:1> Note: Analog lines that carry LCD signals ;inputs on RC<2:0> (i.e., SEGx, VLCDy, where x and y are BCF STATUS,RP0 ;Bank 0 BCF STATUS,RP1 ; segment and LCD bias voltage identifiers) are shown as direct connections to the device pins. The signals are outputs from the LCD module and may be tri-stated, depending on the configuration of the LCD module. REGISTER 3-7: PORTC – PORTC REGISTER (ADDRESS: 07h) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 bit 7-0 RC<7:0>: PORTC I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is <VIL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 3-8: TRISC – PORTC TRI-STATE REGISTER (ADDRESS: 87h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output Note: TRISC<7:6> always reads ‘1’ in XT, HS and LP OSC modes. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 47

PIC16F946 3.4.1 PIN DESCRIPTIONS AND 3.4.1.3 RC2/VLCD3 DIAGRAMS Figure3-16 shows the diagram for this pin. The Each PORTC pin is multiplexed with other functions. The RC2/VLCD3 pin is configurable to function as one of pins and their combined functions are briefly described the following: here. For specific information about individual functions (cid:129) a general purpose I/O such as the LCD or SSP, refer to the appropriate section (cid:129) an analog input for the LCD bias voltage in this data sheet. 3.4.1.1 RC0/VLCD1 Figure3-14 shows the diagram for this pin. The RC0/VLCD1 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog input for the LCD bias voltage 3.4.1.2 RC1/VLCD2 Figure3-15 shows the diagram for this pin. The RC1/VLCD2 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog input for the LCD bias voltage FIGURE 3-14: BLOCK DIAGRAM OF RC0/VLCD1 Data Bus VDD D Q WR PORTC CK Q Data Latch RC0/VLCD1 Pin D Q WR TRISC CK Q TRIS Latch ≠ (VLCDEN and LMUX<1:0> 00) RD TRISC Schmitt Trigger RD PORTC ≠ (VLCDEN and LMUX<1:0> 00) VLCD1 Preliminary DS41265A-page 48 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 3-15: BLOCK DIAGRAM OF RC1/VLCD2 Data Bus VDD D Q WR PORTC CK Q Data Latch RC1/VLCD2 Pin D Q WR TRISC CK Q TRIS Latch ≠ (VLCDEN and LMUX<1:0> 00) RD TRISC Schmitt Trigger RD PORTC ≠ (VLCDEN and LMUX<1:0> 00) VLCD2 FIGURE 3-16: BLOCK DIAGRAM OF RC2/VLCD3 Data Bus VDD D Q WR PORTC CK Q Data Latch RC2/VLCD3 Pin D Q WR TRISC CK Q TRIS Latch VLCDEN RD TRISC Schmitt Trigger RD PORTC VLCDEN VLCD3 Preliminary © 2005 Microchip Technology Inc. DS41265A-page 49

PIC16F946 3.4.1.4 RC3/SEG6 Figure3-17 shows the diagram for this pin. The RC3/SEG6 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD FIGURE 3-17: BLOCK DIAGRAM OF RC3/SEG6 Data Bus VDD D Q WR PORTC CK Q Data Latch RC3/SEG6 Pin D Q WR TRISC CK Q TRIS Latch SE6 and LCDEN RD TRISC Schmitt Trigger RD PORTC SE6 and LCDEN SEG6 Preliminary DS41265A-page 50 © 2005 Microchip Technology Inc.

PIC16F946 3.4.1.5 RC4/T1G/SDO/SEG11 Figure3-18 shows the diagram for this pin. The RC4//T1G/SDO/SEG11pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) a TMR1 gate input (cid:129) a serial data output (cid:129) an analog output for the LCD FIGURE 3-18: BLOCK DIAGRAM OF RC4/T1G/SDO/SEG11 PORT/SDO Select SDO 0 Data Bus D Q 1 VDD WR PORTC CK Q Data Latch D Q RC4/T1G/ SDO/SEG11 Pin WR TRISC CK Q VSS TRIS Latch RD TRISC SE11 and LCDEN Schmitt Trigger Q D EN Q1 RD PORTC Timer1 Gate SE11 and LCDEN SEG11 Preliminary © 2005 Microchip Technology Inc. DS41265A-page 51

PIC16F946 3.4.1.6 RC5/T1CKI/CCP1/SEG10 Figure3-19 shows the diagram for this pin. The RC5/T1CKI/CCP1/SEG10 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) a TMR1 clock input (cid:129) a Capture input, Compare output or PWM output (cid:129) an analog output for the LCD FIGURE 3-19: BLOCK DIAGRAM OF RC5/T1CKI/CCP1/SEG10 (PORT/CCP1 Select) and CCPMX CCP1 Data Out 0 Data Bus D Q 1 VDD WR PORTC CK Q Data Latch D Q RC5/T1CKI/ CCP1/SEG10 Pin WR TRISC CK Q VSS TRIS Latch RD TRISC SE10 and LCDEN Schmitt Trigger RD PORTC Timer1 Gate SE10 and LCDEN SEG10 Preliminary DS41265A-page 52 © 2005 Microchip Technology Inc.

PIC16F946 3.4.1.7 RC6/TX/CK/SCK/SCL/SEG9 Figure3-20 shows the diagram for this pin. The RC6/TX/CK/SCK/SCL/SEG9 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an asynchronous serial output (cid:129) a synchronous clock I/O (cid:129) a SPI clock I/O (cid:129) an I 2C data I/O (cid:129) an analog output for the LCD FIGURE 3-20: BLOCK DIAGRAM OF RC6/TX/CK/SCK/SCL/SEG9 PORT/SCEN/SSP Mode Select(1) I2C™ Data Out 0 TX/CK Data Out 1 SCK Data Out 2 Data Bus D Q 3 VDD WR PORTC CK Q Data Latch D Q RC6/TX/ CK/SCK/ SCL/SEG9 WR TRISC CK Q VSS Pin TRIS Latch RD TRISC SCEN or I2C™ Drive SE9 and LCDEN Schmitt Trigger RD PORTC CK/SCL/SCK Input SE9 and LCDEN SEG9 Note 1: If all three data output sources are enabled, the following priority order will be used: (cid:129) USART data (cid:129) SSP data (cid:129) PORT data Preliminary © 2005 Microchip Technology Inc. DS41265A-page 53

PIC16F946 3.4.1.8 RC7/RX/DT/SDI/SDA/SEG8 Figure3-21 shows the diagram for this pin. The RC7/RX/DT/SDI/SDA/SEG8 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an asynchronous serial input (cid:129) a synchronous serial data I/O (cid:129) a SPI data I/O (cid:129) an I 2C data I/O (cid:129) an analog output for the LCD FIGURE 3-21: BLOCK DIAGRAM OF RC7/RX/DT/SDI/SDA/SEG8 SCEN/I2C™ Mode Select(1) DT Data Out 0 I2C™ Data Out 1 PORT/(SCEN or I2C™) Select VDD 0 1 RC7/RX/DT/ Data Bus SDI/SDA/ D Q SEG8 WR PORTC Pin CK Q Data Latch D Q WR TRISC CK Q TRIS Latch SE8 and LCDEN Schmitt I2C™ Drive RD TRISC Trigger or SCEN Drive RD PORTC RX/SDI Input SE8 and LCDEN SEG8 Note 1: If SSP and USART outputs are both enabled, the USART data output will have priority over the SSP data output. Both SSP and USART data outputs will have priority over the PORT data output. Preliminary DS41265A-page 54 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 3-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on all Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 11Ch LCDSE0(1) SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu 11Dh LCDSE1(1) SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Note 1: This register is only initialized by a POR or BOR and is unchanged by other Resets. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 55

PIC16F946 3.5 PORTD and TRISD Registers EXAMPLE 3-4: INITIALIZING PORTD BCF STATUS,RP0 ;Bank 0 PORTD is an 8-bit port with Schmitt Trigger input buffers. BCF STATUS,RP1 ; Each pin is individually configured as an input or output. CLRF PORTD ;Init PORTD PORTD is only available on the PIC16F946 and BSF STATUS,RP0 ;Bank 1 PIC16F946. BCF STATUS,RP1 ; MOVLW FFh ;Set RD<7:0> as inputs Note: Analog lines that carry LCD signals MOVWF TRISD ; (i.e., SEGx, COMy, where x and y are seg- BCF STATUS,RP0 ;Bank 0 ment and common identifiers) are shown BCF STATUS,RP1 ; as direct connections to the device pins. The signals are outputs from the LCD module and may be tri-stated, depending on the configuration of the LCD module. REGISTER 3-9: PORTD – PORTD REGISTER (ADDRESS: 08h) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 bit 7 bit 0 bit 7-0 RD<7:0>: PORTD I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is <VIL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 3-10: TRISD – PORTD TRI-STATE REGISTER (ADDRESS: 88h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 bit 7 bit 0 bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output Note: TRISD<7:6> always reads ‘1’ in XT, HS and LP OSC modes. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 56 © 2005 Microchip Technology Inc.

PIC16F946 3.5.1 PIN DESCRIPTIONS AND 3.5.1.7 RD6/SEG19 DIAGRAMS Figure3-25 shows the diagram for this pin. The Each PORTD pin is multiplexed with other functions. The RD6/SEG19 pin is configurable to function as one of pins and their combined functions are briefly described the following: here. For specific information about individual functions (cid:129) a general purpose I/O such as the comparator or the A/D, refer to the (cid:129) an analog output for the LCD appropriate section in this data sheet. 3.5.1.8 RD7/SEG20 3.5.1.1 RD0/COM3 Figure3-25 shows the diagram for this pin. The Figure3-22 shows the diagram for this pin. The RD7/SEG20 pin is configurable to function as one of RD0/COM3 pin is configurable to function as one of the the following: following: (cid:129) a general purpose I/O (cid:129) a general purpose I/O (cid:129) an analog output for the LCD (cid:129) an analog input from Comparator 1 3.5.1.2 RD1 Figure3-23 shows the diagram for this pin. The RD1 pin is configurable to function as one of the following: (cid:129) a general purpose I/O 3.5.1.3 RD2/CCP2 Figure3-24 shows the diagram for this pin. The RD2/CCP2 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) a Capture input, Compare output or PWM output 3.5.1.4 RD3/SEG16 Figure3-25 shows the diagram for this pin. The RD3/SEG16 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.5.1.5 RD4/SEG17 Figure3-25 shows the diagram for this pin. The RD4/SEG17 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.5.1.6 RD5/SEG18 Figure3-25 shows the diagram for this pin. The RD5/SEG18 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD Preliminary © 2005 Microchip Technology Inc. DS41265A-page 57

PIC16F946 FIGURE 3-22: BLOCK DIAGRAM OF RD0/COM3 VDD Data Bus D Q WR PORTD CK Q RD0/COM3 Pin Data Latch D Q WR TRISD CK Q TRIS Latch Schmitt Trigger RD TRISD LCDEN and LMUX<1:0> = 11 RD PORTD LCDEN and LMUX<1:0> = 11 COM3 FIGURE 3-23: BLOCK DIAGRAM OF RD1 VDD Data Bus D Q WR PORTD CK Q RD1 Pin Data Latch D Q WR TRISD CK Q TRIS Latch Schmitt Trigger RD TRISD RD PORTD Preliminary DS41265A-page 58 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 3-24: BLOCK DIAGRAM OF RD2/CCP2 (PORT/CCP2 Select) and CCPMX VDD CCP2 Data Out 0 Data Bus D Q 1 RD2/CCP2 WR PORTD Pin CK Q Data Latch D Q WR TRISD CK Q TRIS Latch Schmitt Trigger RD TRISD RD PORTD CCP2 Input FIGURE 3-25: BLOCK DIAGRAM OF RD<7:3> VDD Data Bus D Q WR PORTD CK Q RD<7:3> Pin Data Latch D Q WR TRISD CK Q TRIS Latch SE<20:16> and LCDEN Schmitt RD TRISD Trigger RD PORTD SE<20:16> and LCDEN SEG<20:16> Preliminary © 2005 Microchip Technology Inc. DS41265A-page 59

PIC16F946 TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on all Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 1Dh(2) CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 88h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111 107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 11Eh LCDSE2(1) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD. Note 1: This register is only initialized by a POR or BOR and is unchanged by other Resets. Preliminary DS41265A-page 60 © 2005 Microchip Technology Inc.

PIC16F946 3.6 PORTE and TRISE Registers EXAMPLE 3-5: INITIALIZING PORTE BCF STATUS,RP0 ;Bank 0 PORTE is a 4-bit port with Schmitt Trigger input buffers. BCF STATUS,RP1 ; RE<7:0> are individually configured as inputs or out- CLRF PORTE ;Init PORTE puts. RE3 is only available as an input if MCLRE is ‘0’ BSF STATUS,RP0 ;Bank 1 in Configuration Word (Register16-1).. BCF STATUS,RP1 ; MOVLW 0Fh ;Set RE<3:0> as inputs Note: Analog lines that carry LCD signals MOVWF TRISE ; (i.e., SEGx, where x are segment identifi- CLRF ANSEL ;Make RE<2:0> as I/O’s ers) are shown as direct connections to BCF STATUS,RP0 ;Bank 0 the device pins. The signals are outputs BCF STATUS,RP1 ; from the LCD module and may be tri-stated, depending on the configuration of the LCD module. REGISTER 3-11: PORTE – PORTE REGISTER (ADDRESS: 09h) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 bit 7 bit 0 bit 7-0 RE<7:0>: PORTE I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is <VIL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 3-12: TRISE – PORTE TRI-STATE REGISTER (ADDRESS: 89h) R/W-1 R/W-1 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7-4 TRISE<7:4>: Data Direction bits bit 3 TRISE3: Data Direction bit. RE3 is always an input, so this bit always reads as a ‘1’ bit 2-0 TRISE<2:0>: Data Direction bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 61

PIC16F946 3.6.1 PIN DESCRIPTIONS AND 3.6.1.7 RE6/SEG26 DIAGRAMS Figure3-26 shows the diagram for this pin. The Each PORTE pin is multiplexed with other functions. The RE6/SEG26 pin is configurable to function as one of pins and their combined functions are briefly described the following: here. For specific information about individual functions (cid:129) a general purpose I/O such as the comparator or the A/D, refer to the (cid:129) an analog output for the LCD appropriate section in this data sheet. 3.6.1.8 RE7/SEG27 3.6.1.1 RE0/AN5/SEG21 Figure3-26 shows the diagram for this pin. The Figure3-26 shows the diagram for this pin. The RE7/SEG27 pin is configurable to function as one of RE0/AN5/SEG21 pin is configurable to function as one the following: of the following: (cid:129) a general purpose I/O (cid:129) a general purpose I/O (cid:129) an analog output for the LCD (cid:129) an analog input for the A/D (cid:129) an analog output for the LCD 3.6.1.2 RE1/AN6/SEG22 Figure3-26 shows the diagram for this pin. The RE1/AN6/SEG22 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog input for the A/D (cid:129) an analog output for the LCD 3.6.1.3 RE2/AN7/SEG23 Figure3-26 shows the diagram for this pin. The RE2/AN7/SEG23 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog input for the A/D (cid:129) an analog output for the LCD 3.6.1.4 RE3/MCLR/VPP Figure3-27 shows the diagram for this pin. The RE3/MCLR/VPP pin is configurable to function as one of the following: (cid:129) a digital input only (cid:129) as Master Clear Reset with weak pull-up (cid:129) a programming voltage reference input 3.6.1.5 RE4/SEG24 Figure3-26 shows the diagram for this pin. The RE4/SEG24 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.6.1.6 RE5/SEG25 Figure3-26 shows the diagram for this pin. The RE5/SEG25 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD Preliminary DS41265A-page 62 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 3-26: BLOCK DIAGRAM OF RE<7:4, 2:0> VDD Data Bus D Q WR PORTE CK Q RE<7:4,2:0> Pins Data Latch D Q WR TRISE CK Q TRIS Latch RD TRISE Analog Mode or Schmitt SE<27:21> and LCDEN Trigger RD PORTE SE<27:21> and LCDEN SEG<27:21> AN<7:5>(1) Note 1: Analog input for A/D apply to RE<2:0> pins only. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 63

PIC16F946 FIGURE 3-27: BLOCK DIAGRAM OF RE3/MCLR/VPP HV Schmitt Trigger MCLR circuit Buffer MCLR Filter Programming mode HV Detect MCLRE RE3/MCLR/VPP(1) Data Bus HV Schmitt Trigger Buffer RE TRISE RE PORTE Note 1: RE3 will read ‘0’ when pin is MCLR. TABLE 3-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on all Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets 09h PORTE RE7 R6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx uuuu uuuu 1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 89h TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3(2) TRISE2 TRISE1 TRISE0 1111 1111 1111 1111 91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 11Eh LCDSE2(1) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu 19Ch LCDSE3(1) SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Note 1: This register is only initialized by a POR or BOR and is unchanged by other Resets. 2: Bit is read-only; TRISE = 1 always. Preliminary DS41265A-page 64 © 2005 Microchip Technology Inc.

PIC16F946 3.7 PORTF and TRISF Registers EXAMPLE 3-6: INITIALIZING PORTF BCF STATUS,RP0 ;Bank 3 PORTF is an 8-bit port with Schmitt Trigger input BCF STATUS,RP1 ; buffers. RF<7:0> are individually configured as inputs CLRF PORTF ;Init PORTF or outputs, depending on the state of the port direction. BSF STATUS,RP0 ;Bank 1 The port bits are also multiplexed with LCD segment BCF STATUS,RP1 ; functions. MOVLW 0Fh ;Set RF<3:0> as inputs MOVWF TRISF ; Note: Analog lines that carry LCD signals CLRF ANSEL ;Make RF<2:0> as I/O’s (i.e., SEGx, where x are segment identifiers) BCF STATUS,RP0 ;Bank 0 are shown as direct connections to the BCF STATUS,RP1 ; device pins. The signals are outputs from the LCD module and may be tri-stated, depending on the configuration of the LCD module. REGISTER 3-13: PORTF – PORTF REGISTER (ADDRESS: 188h) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 bit 7 bit 0 bit 7-0 RF<7:0>: PORTF I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is <VIL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 3-14: TRISF – PORTF TRI-STATE REGISTER (ADDRESS: 185h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 bit 7 bit 0 bit 7-0 TRISF<7:0>: Data Direction bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 65

PIC16F946 3.7.1 PIN DESCRIPTIONS AND 3.7.1.7 RF6/SEG30 DIAGRAMS Figure3-28 shows the diagram for this pin. The Each PORTF pin is multiplexed with other functions. The RF6/SEG30 pin is configurable to function as one of pins and their combined functions are briefly described the following: here. For specific information about individual functions, (cid:129) a general purpose I/O refer to the appropriate section in this data sheet. (cid:129) an analog output for the LCD 3.7.1.1 RF0/SEG32 3.7.1.8 RF7/SEG31 Figure3-28 shows the diagram for this pin. The Figure3-28 shows the diagram for this pin. The RF0/SEG32 pin is configurable to function as one of RF7/SEG31 pin is configurable to function as one of the following: the following: (cid:129) a general purpose I/O (cid:129) a general purpose I/O (cid:129) an analog output for the LCD (cid:129) an analog output for the LCD 3.7.1.2 RF1/SEG33 Figure3-28 shows the diagram for this pin. The RF1/SEG33 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.7.1.3 RF2/SEG34 Figure3-28 shows the diagram for this pin. The RF2/SEG34 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.7.1.4 RF3/SEG35 Figure3-28 shows the diagram for this pin. The RF3/SEG35 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.7.1.5 RF4/SEG28 Figure3-28 shows the diagram for this pin. The RF4/SEG28 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.7.1.6 RF5/SEG29 Figure3-28 shows the diagram for this pin. The RF5/SEG29 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD Preliminary DS41265A-page 66 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 3-28: BLOCK DIAGRAM OF RF<7:0> VDD Data Bus D Q WR PORTF CK Q RF<7:0> Pin Data Latch D Q WR TRISF CK Q TRIS Latch Analog Mode or RD TRISF SE<31:28, 35:32> and LCDEN Schmitt Trigger RD PORTF SE<31:28, 35:32> and LCDEN SEG<31:28, 35:32> TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Value on all Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets 1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 185h TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111 188h PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx xxxx uuuu uuuu 19Ch LCDSE3(1) SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000 uuuu uuuu 19Dh LCDSE4(1) SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTF. Note 1: This register is only initialized by a POR or BOR and is unchanged by other Resets. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 67

PIC16F946 3.8 PORTG and TRISG Registers EXAMPLE 3-7: INITIALIZING PORTG BCF STATUS,RP0 ;Bank 3 PORTG is an 8-bit port with Schmitt Trigger input BCF STATUS,RP1 ; buffers. RG<5:0> are individually configured as inputs CLRF PORTG ;Init PORTG or outputs, depending on the state of the port direction. BSF STATUS,RP0 ;Bank 1 The port bits are also multiplexed with LCD segment BCF STATUS,RP1 ; functions. MOVLW 0Fh ;Set RG<3:0> as inputs MOVWF TRISF ; Note: Analog lines that carry LCD signals CLRF ANSEL ;Make RG<2:0> as I/O’s (i.e., SEGx, where x are segment identifiers) BCF STATUS,RP0 ;Bank 0 are shown as direct connections to the BCF STATUS,RP1 ; device pins. The signals are outputs from the LCD module and may be tri-stated, depending on the configuration of the LCD module. REGISTER 3-15: PORTG – PORTG REGISTER (ADDRESS: 189h) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — RG5 RG4 RG3 RG2 RG1 RG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RG<5:0>: PORTG I/O Pin bits 1 = Port pin is >VIH 0 = Port pin is <VIL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 3-16: TRISG – PORTG TRI-STATE REGISTER (ADDRESS: 187h) U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — TRISG5 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISG<5:0>: Data Direction bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 68 © 2005 Microchip Technology Inc.

PIC16F946 3.8.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTG pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet. 3.8.1.1 RG0/SEG36 Figure3-29 shows the diagram for this pin. The RG0/SEG36 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.8.1.2 RG1/SEG37 Figure3-29 shows the diagram for this pin. The RG1/SEG37 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.8.1.3 RG2/SEG38 Figure3-29 shows the diagram for this pin. The RG2/SEG38 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.8.1.4 RG3/SEG39 Figure3-29 shows the diagram for this pin. The RG3/SEG39 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.8.1.5 RG4/SEG40 Figure3-29 shows the diagram for this pin. The RG4/SEG40 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD 3.8.1.6 RG5/SEG41 Figure3-29 shows the diagram for this pin. The RG5/SEG41 pin is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) an analog output for the LCD Preliminary © 2005 Microchip Technology Inc. DS41265A-page 69

PIC16F946 FIGURE 3-29: BLOCK DIAGRAM OF RG<5:0> VDD Data Bus D Q WR PORTG CK Q RG<5:0> Pin Data Latch D Q WR TRISG CK Q TRIS Latch Analog Mode or RD TRISG SE<41:36> and LCDEN Schmitt Trigger RD PORTG SE<41:36> and LCDEN SEG<41:36> TABLE 3-7: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Value on all Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets 1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 187h TRISG — — TRISG5 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 --11 1111 --11 1111 189h PORTG — — RG5 RG4 RG3 RG2 RG1 RG0 --xx xxxx --uu uuuu 19Dh LCDSE4(1) SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 0000 0000 uuuu uuuu 19Eh LCDSE5(1) — — — — — — SE41 SE40 ---- --00 ---- --uu Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTG. Note 1: This register is only initialized by a POR or BOR and is unchanged by other Resets. Preliminary DS41265A-page 70 © 2005 Microchip Technology Inc.

PIC16F946 4.0 CLOCK SOURCES The PIC16F946 can be configured in one of eight clock modes. 4.1 Overview 1. EC – External clock with I/O on RA6. 2. LP – Low-gain Crystal or Ceramic Resonator The PIC16F946 has a wide variety of clock sources Oscillator mode. and selection features to allow it to be used in a wide 3. XT – Medium-gain Crystal or Ceramic Resonator range of applications while maximizing performance Oscillator mode. and minimizing power consumption. Figure4-1 illustrates a block diagram of the PIC16F946 clock 4. HS – High-gain Crystal or Ceramic Resonator sources. mode. 5. RC – External Resistor-Capacitor (RC) with Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators, and FOSC/4 output on RA6. Resistor-Capacitor (RC) circuits. In addition, the system 6. RCIO – External Resistor-Capacitor with I/O on clock source can be configured from one of two internal RA6. oscillators, with a choice of speeds selectable via 7. INTOSC – Internal oscillator with FOSC/4 output software. Additional clock features include: on RA6 and I/O on RA7. (cid:129) Selectable system clock source between external 8. INTOSCIO – Internal oscillator with I/O on RA6 or internal via software. and RA7. (cid:129) Two-Speed Clock Start-up mode, which Clock source modes are configured by the FOSC<2:0> minimizes latency between external oscillator bits in the Configuration Word register (see start-up and code execution. Section16.0 “Special Features of the CPU”). The (cid:129) Fail-Safe Clock Monitor (FSCM) designed to internal clock can be generated by two oscillators. The detect a failure of the external clock source (LP, HFINTOSC is a high-frequency calibrated oscillator. XT, HS, EC or RC modes) and switch to the The LFINTOSC is a low-frequency uncalibrated Internal Oscillator. oscillator. FIGURE 4-1: PIC16F946 SYSTEM CLOCK BLOCK DIAGRAM FOSC<2:0> (Configuration Word) External Oscillator SCS OSC2 (OSCCON<0>) Sleep LP, XT, HS, RC, RCIO, EC OSC1 IRCF<2:0> X (OSCCON<6:4>) U M System Clock (CPU and Peripherals) 8 MHz 111 4 MHz Internal Oscillator 110 2 MHz r 101 e 1 MHz al 100 X HFINTOSC sc 500 kHz U 8 MHz st 011 M o 250 kHz P 010 125 kHz 001 LFINTOSC 31 kHz 000 31 kHz LCD Module Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) Preliminary © 2005 Microchip Technology Inc. DS41265A-page 71

PIC16F946 REGISTER 4-1: OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh) U-0 R/W-1 R/W-1 R/W-0 R-q R-0 R-0 R/W-0 — IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 000 = 31kHz 001 = 125kHz 010 = 250kHz 011 = 500kHz 100 = 1MHz 101 = 2MHz 110 = 4MHz 111 = 8MHz bit 3 OSTS: Oscillator Start-up Time-out Status bit 1 = Device is running from the external system clock defined by FOSC<2:0> 0 = Device is running from the internal system clock (HFINTOSC or LFINTOSC) bit 2 HTS: HFINTOSC (High Frequency – 8MHz to 125kHz) Status bit 1 = HFINTOSC is stable 0 = HFINTOSC is not stable bit 1 LTS: LFINTOSC (Low Frequency – 31kHz) Stable bit 1 = LFINTOSC is stable 0 = LFINTOSC is not stable bit 0 SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> Note1: The value of the OSTS bit on device power-up is dependent on the value of the Configuration Word (CONFIG) of the device. The value of the OSTS bit will be ‘0’ on a device Power-on Reset (POR) or any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, if the following conditions are true: OSTS = 0 if: FOSC<2:0> = 000 (LP) or 001 (XT) or 010 (HS) and IESO = 1 or FSCM = 1 (IESO will be enabled automatically if FSCM is enabled) If any of the above conditions are not met, the value of the OSTS bit will be ‘1’ on a device POR. See Section4.6 “Two-Speed Clock Start-up Mode” and Section4.7 “Fail-Safe Clock Monitor” for more details. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown q = value depends on condition Preliminary DS41265A-page 72 © 2005 Microchip Technology Inc.

PIC16F946 4.2 Clock Source Modes 4.3.1.1 Special Case Clock source modes can be classified as external or An exception to this is when the device is put to Sleep internal. while the following conditions are true: (cid:129) External clock modes rely on external circuitry for (cid:129) LP is the selected primary oscillator mode. the clock source. Examples are oscillator modules (cid:129) T1OSCEN = 1 (Timer1 oscillator is enabled). (EC mode), quartz crystal resonators or ceramic (cid:129) SCS = 0 (oscillator mode is defined by resonators (LP, XT and HS modes), and FOSC<2:0>). Resistor-Capacitor (RC mode) circuits. (cid:129) OSTS = 1 (device is running from primary system (cid:129) Internal clock sources are contained internally clock). within the PIC16F946. The PIC16F946 has two For this case, the OST is not necessary after a wake-up internal oscillators: the 8MHz High-Frequency from Sleep, since Timer1 continues to run during Sleep Internal Oscillator (HFINTOSC) and 31kHz and uses the same LP oscillator circuit as its clock Low-Frequency Internal Oscillator (LFINTOSC). source. For these devices, this case is typically seen The system clock can be selected between external or when the LCD module is running during Sleep. internal clock sources via the System Clock Selection In applications where the OSCTUNE register is used to (SCS) bit (see Section4.5 “Clock Switching”). shift the FINTOSC frequency, the application should not expect the FINTOSC frequency to stabilize immediately. 4.3 External Clock Modes In this case, the frequency may shift gradually toward the new value. The time for this frequency shift is less 4.3.1 OSCILLATOR START-UP TIMER than eight cycles of the base frequency. (OST) Note: When the OST is invoked, the WDOG is If the PIC16F946 is configured for LP, XT or HS modes, held in Reset, because the WDOG ripple the Oscillator Start-up Timer (OST) counts 1024 oscil- counter is used by the OST to perform the lations from the OSC1 pin, following a Power-on Reset oscillator delay count. When the OST (POR), and the Power-up Timer (PWRT) has expired (if count has expired, the WDOG will begin configured), or a wake-up from Sleep. During this time, counting (if enabled). the program counter does not increment and program execution is suspended. The OST ensures that the Table4-1 shows examples where the oscillator delay is oscillator circuit, using a quartz crystal resonator or invoked. ceramic resonator, has started and is providing a stable In order to minimize latency between external oscillator system clock to the PIC16F946. When switching start-up and code execution, the Two-Speed Clock between clock sources a delay is required to allow the Start-up mode can be selected (see Section4.6 new clock to stabilize. These oscillator delays are “Two-Speed Clock Start-up Mode”). shown in Table4-1. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 73

PIC16F946 TABLE 4-1: OSCILLATOR DELAY EXAMPLES System Clock Oscillator Delay Frequency Switching From Comments Source (TOST) LFIOSC 31kHz Sleep 10μs internal delay Following a wake-up from Sleep mode or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. HFIOSC 125kHz-8MHz Sleep 10μs internal delay Following a wake-up from Sleep mode or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. XT or HS 4-20MHz INTOSC or Sleep 1024 clock cycles Following a change from INTOSC, an OST of 1024 cycles must occur. LP 32 kHz INTOSC or Sleep 1024 clock cycles Following a change from INTOSC, an OST of 1024 cycles must occur. See Section4.3.1.1 “Special Case” for special case conditions. LP with T1OSC 32 kHz Sleep 10μs internal delay Following a wake-up from Sleep mode, enabled an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. See Section4.3.1.1 “Special Case” for details about this special case. EC, RC 0-20MHz Sleep 10μs internal delay Following a wake-up from Sleep mode or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. EC, RC 0-20MHz LFIOSC 10μs internal delay Following a switch from a LFIOSC or POR, an internal delay is invoked to allow the memory bias to stabilize before program execution can begin. Preliminary DS41265A-page 74 © 2005 Microchip Technology Inc.

PIC16F946 4.3.2 EC MODE 4.3.3 LP, XT, HS MODES The External Clock (EC) mode allows an externally The LP, XT and HS modes support the use of quartz generated logic level as the system clock source. crystal resonators or ceramic resonators connected to When operating in this mode, an external clock source the OSC1 and OSC2 pins (Figures4-3 and4-4). The is connected to the OSC1 pin and the RA6 pin is mode selects a low, medium or high gain setting of the available for general purpose I/O. Figure4-2 shows the internal inverter-amplifier to support various resonator pin connections for EC mode. types and speed. The Oscillator Start-up Timer (OST) is disabled when LP Oscillator mode selects the lowest gain setting of the EC mode is selected. Therefore, there is no delay in internal inverter-amplifier. LP mode current consumption operation after a Power-on Reset (POR) or wake-up is the least of the three modes. This mode is best suited from Sleep. Because the PIC16F946 design is fully to drive resonators with a low drive level specification, for static, stopping the external clock input will have the example, tuning fork type crystals. effect of halting the device while leaving all data intact. Note: In the past, the sources for the LP oscilla- Upon restarting the external clock, the device will tor and Timer1 oscillator have been sepa- resume operation as if no time had elapsed. rate circuits. In this family of devices, the LP oscillator and Timer1 oscillator use the FIGURE 4-2: EXTERNAL CLOCK (EC) same oscillator circuitry. When using a MODE OPERATION device configured for the LP oscillator and with T1OSCEN = 1, the source of the clock for each function comes from the PIC16F946 same oscillator block. Clock OSC1/ XT Oscillator mode selects the intermediate gain FOSC Internal (External CLKIN Clock setting of the internal inverter-amplifier. XT mode System) current consumption is the medium of the three modes. FOSC<2:0> = 011 This mode is best suited to drive resonators with a medium drive level specification, for example, low-frequency/AT-cut quartz crystal resonators. RA6 RA6/OSC2/CLKO/T1OSO HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting, for example, high-frequency/AT-cut quartz crystal resonators or ceramic resonators. Figures4-3 and4-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 75

PIC16F946 FIGURE 4-3: QUARTZ CRYSTAL FIGURE 4-4: CERAMIC RESONATOR OPERATION (LP, XT OR OPERATION HS MODE) (XT OR HS MODE) PIC16F946 PIC16F946 OSC1 OSC1 C1 To Int. C1 To Int. Logic Logic Quartz RF(2) RF(3) RF(2) Crystal Sleep(3) Sleep OSC2 OSC2 RS(1) RS(1) C2 C2 Ceramic Resonator Note1: A series resistor (RS) may be required for Note1: A series resistor (RS) may be required for quartz crystals with low drive level. ceramic resonators with low drive level. 2: The value of RF varies with the oscillator 2: The value of RF varies with the oscillator mode selected (typically between 2MΩ to mode selected (typically between 2MΩ to 10MΩ). 10MΩ). 3: If using LP mode and T1OSC in enable, 3: An additional parallel feedback resistor the LP oscillator will continue to run during (RP) may be required for proper ceramic Sleep. resonator operation (typical value 1MΩ). Note1: Quartz crystal characteristics vary according to type, package and manufac- turer. The user should consult the manufacturer data sheets for specifica- tions and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. Preliminary DS41265A-page 76 © 2005 Microchip Technology Inc.

PIC16F946 4.3.4 EXTERNAL RC MODES 4.4 Internal Clock Modes The External Resistor-Capacitor (RC) modes support The PIC16F946 has two independent, internal the use of an external RC circuit. This allows the oscillators that can be configured or selected as the designer maximum flexibility in frequency choice while system clock source. keeping costs to a minimum when clock accuracy is not 1. The HFINTOSC (High-Frequency Internal required. There are two modes, RC and RCIO. Oscillator) is factory calibrated and operates at In RC mode, the RC circuit connects to the OSC1 pin. 8MHz. The frequency of the HFINTOSC can be The OSC2/CLKO pin outputs the RC oscillator user adjusted ±12% via software using the frequency divided by 4. This signal may be used to OSCTUNE register (Register4-2). provide a clock for external circuitry, synchronization, 2. The LFINTOSC (Low-Frequency Internal calibration, test or other application requirements. Oscillator) is uncalibrated and operates at Figure4-5 shows the RC mode connections. approximately 31kHz. FIGURE 4-5: RC MODE The system clock speed can be selected via software using the Internal Oscillator Frequency Select (IRCF) VDD bits. PIC16F946 The system clock can be selected between external or REXT internal clock sources via the System Clock Selection OSC1 Internal (SCS) bit (see Section4.5 “Clock Switching”). Clock CEXT 4.4.1 INTOSC AND INTOSCIO MODES The INTOSC and INTOSCIO modes configure the VSS OSC2/CLKO internal oscillators as the system clock source when the FOSC/4 device is programmed using the Oscillator Selection (FOSC) bits in the Configuration Word register Recommended values:3 kΩ ≤ REXT ≤ 100 kΩ (Register16-1). CEXT > 20 pF In INTOSC mode, the OSC1 pin is available for general purpose I/O. The OSC2/CLKO pin outputs the selected In RCIO mode, the RC circuit is connected to the OSC1 internal oscillator frequency divided by 4. The CLKO pin. The OSC2 pin becomes an additional general signal may be used to provide a clock for external purpose I/O pin. The I/O pin becomes bit 4 of PORTA circuitry, synchronization, calibration, test or other (RA4). Figure4-6 shows the RCIO mode connections. application requirements. FIGURE 4-6: RCIO MODE In INTOSCIO mode, the OSC1 and OSC2 pins are available for general purpose I/O. VDD PIC16F946 4.4.2 HFINTOSC REXT The High-Frequency Internal Oscillator (HFINTOSC) is OSC1 Internal a factory calibrated 8MHz internal clock source. The Clock frequency of the HFINTOSC can be altered CEXT approximately ±12% via software using the OSCTUNE register (Register4-2). VSS I/O (OSC2) The output of the HFINTOSC connects to a postscaler RA6 and multiplexer (see Figure4-1). One of seven frequencies can be selected via software using the Recommended values:3 kΩ ≤ REXT ≤ 100 kΩ IRCF bits (see Section4.4.4 “Frequency Select Bits CEXT > 20 pF (IRCF)”). The HFINTOSC is enabled by selecting any frequency The RC oscillator frequency is a function of the supply between 8MHz and 125kHz (IRCF ≠ 000) as the voltage, the resistor (REXT) and capacitor (CEXT) System Clock Source (SCS = 1), or when Two-Speed values and the operating temperature. In addition to Start-up is enabled (IESO = 1 and IRCF ≠ 000). this, the oscillator frequency will vary from unit to unit due to normal threshold voltage. Furthermore, the The HF Internal Oscillator (HTS) bit (OSCCON<2>) difference in lead frame capacitance between package indicates whether the HFINTOSC is stable or not. types will also affect the oscillation frequency or for low CEXT values. The user also needs to take into account variation due to tolerance of external RC components used. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 77

PIC16F946 4.4.2.1 OSCTUNE Register When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. The The HFINTOSC is factory calibrated but can be HFINTOSC clock will stabilize within 1ms. Code adjusted in software by writing to the OSCTUNE execution continues during this shift. There is no register (Register4-2). indication that the shift has occurred. The OSCTUNE register has a tuning range of ±12%. OSCTUNE does not affect the LFINTOSC frequency. The default value of the OSCTUNE register is ‘0’. The Operation of features that depend on the LFINTOSC value is a 5-bit two’s complement number. Due to clock source frequency, such as the Power-up Timer process variation, the monotonicity and frequency step (PWRT), Watchdog Timer (WDT), Fail-Safe Clock cannot be specified. Monitor (FSCM) and peripherals, are not affected by the change in frequency. REGISTER 4-2: OSCTUNE – OSCILLATOR TUNING RESISTOR (ADDRESS: 90h) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = (cid:129) (cid:129) (cid:129) 00001 = 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 = (cid:129) (cid:129) (cid:129) 10000 = Minimum frequency Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 78 © 2005 Microchip Technology Inc.

PIC16F946 4.4.3 LFINTOSC 4.4.5 HF AND LF INTOSC CLOCK SWITCH TIMING The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated (approximate) 31kHz internal clock When switching between the LFINTOSC and the source. HFINTOSC, the new oscillator may already be shut down to save power. If this is the case, there is a 10μs The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure4-1). 31kHz can be delay after the IRCF bits are modified before the frequency selection takes place. The LTS/HTS bits will selected via software using the IRCF bits (see Section4.4.4 “Frequency Select Bits (IRCF)”). The reflect the current active status of the LFINTOSC and the HFINTOSC oscillators. The timing of a frequency LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe selection is as follows: Clock Monitor (FSCM). 1. IRCF bits are modified. The LFINTOSC is enabled by selecting 31kHz 2. If the new clock is shut down, a 10μs clock (IRCF=000) as the System Clock Source (SCS = 1), start-up delay is started. or when any of the following are enabled: 3. Clock switch circuitry waits for a falling edge of (cid:129) Two-Speed Start-up (IESO = 1 and IRCF = 000) the current clock. (cid:129) Power-up Timer (PWRT) 4. CLKO is held low and the clock switch circuitry waits for a rising edge in the new clock. (cid:129) Watchdog Timer (WDT) 5. CLKO is now connected with the new clock. (cid:129) Fail-Safe Clock Monitor (FSCM) HTS/LTS bits are updated as required. (cid:129) Selected as LCD module clock source 6. Clock switch is complete. The LF Internal Oscillator (LTS) bit (OSCCON<1>) If the internal oscillator speed selected is between indicates whether the LFINTOSC is stable or not. 8MHz and 125kHz, there is no start-up delay before 4.4.4 FREQUENCY SELECT BITS (IRCF) the new frequency is selected. This is because the old and the new frequencies are derived from the The output of the 8MHz HFINTOSC and 31kHz HFINTOSC via the postscaler and multiplexer. LFINTOSC connect to a postscaler and multiplexer (see Figure4-1). The Internal Oscillator Frequency 4.5 Clock Switching select bits, IRCF<2:0> (OSCCON<6:4>), select the frequency output of the internal oscillators. One of eight The system clock source can be switched between frequencies can be selected via software: external and internal clock sources via software using (cid:129) 8 MHz the System Clock Select (SCS) bit. (cid:129) 4 MHz (Default after Reset) 4.5.1 SYSTEM CLOCK SELECT (SCS) BIT (cid:129) 2 MHz The System Clock Select (SCS) bit (OSCCON<0>) (cid:129) 1 MHz selects the system clock source that is used for the (cid:129) 500 kHz CPU and peripherals. (cid:129) 250 kHz (cid:129) When SCS = 0, the system clock source is (cid:129) 125 kHz determined by configuration of the FOSC<2:0> (cid:129) 31 kHz bits in the Configuration Word register (CONFIG). Note: Following any Reset, the IRCF bits are set (cid:129) When SCS = 1, the system clock source is to ‘110’ and the frequency selection is set chosen by the internal oscillator frequency to 4MHz. The user can modify the IRCF selected by the IRCF bits. After a Reset, SCS is bits to select a different frequency. always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bit. The user can monitor the OSTS (OSCCON<3>) to determine the current system clock source. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 79

PIC16F946 4.5.2 OSCILLATOR START-UP TIME-OUT 4.6.2 TWO-SPEED START-UP STATUS BIT SEQUENCE The Oscillator Start-up Time-out Status (OSTS) bit 1. Wake-up from Power-on Reset or Sleep. (OSCCON<3>) indicates whether the system clock is 2. Instructions begin execution by the internal running from the external clock source, as defined by oscillator at the frequency set in the IRCF bits the FOSC bits, or from the internal clock source. In (OSCCON<6:4>). particular, OSTS indicates that the Oscillator Start-up 3. OST enabled to count 1024 clock cycles. Timer (OST) has timed out for LP, XT or HS modes. 4. OST timed out, wait for falling edge of the internal oscillator. 4.6 Two-Speed Clock Start-up Mode 5. OSTS is set. Two-Speed Start-up mode provides additional power 6. System clock held low until the next falling edge savings by minimizing the latency between external of new clock (LP, XT or HS mode). oscillator start-up and code execution. In applications 7. System clock is switched to external clock that make heavy use of the Sleep mode, Two-Speed source. Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the 4.6.3 CHECKING EXTERNAL/INTERNAL overall power consumption of the device. CLOCK STATUS This mode allows the application to wake-up from Checking the state of the OSTS bit (OSCCON<3>) will Sleep, perform a few instructions using the INTOSC confirm if the PIC16F946 is running from the external as the clock source and go back to Sleep without clock source as defined by the FOSC bits in the waiting for the primary oscillator to become stable. Configuration Word (CONFIG) or the internal oscillator. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit (OSCCON<3>) to remain clear. When the PIC16F946 is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section4.3.1 “Oscillator Start-up Timer (OST)”). The OST timer will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit (OSCCON<3>) is set, program execution switches to the external oscillator. 4.6.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: (cid:129) IESO = 1 (CONFIG<10>) Internal/External Switchover bit. (cid:129) SCS = 0. (cid:129) FOSC configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: (cid:129) Power-on Reset (POR) and, if enabled, after PWRT has expired, or (cid:129) Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. Preliminary DS41265A-page 80 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 4-7: TWO-SPEED START-UP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 INTOSC TTOST OSC1 0 1 1022 1023 OSC2 Program Counter PC PC + 1 PC + 2 System Clock 4.7 Fail-Safe Clock Monitor The frequency of the internal oscillator will depend upon the value contained in the IRCF bits (OSCCON<6:4>). The Fail-Safe Clock Monitor (FSCM) is designed to Upon entering the Fail-Safe condition, the OSTS bit allow the device to continue to operate in the event of (OSCCON<3>) is automatically cleared to reflect that an oscillator failure. The FSCM can detect oscillator the internal oscillator is active and the WDT is cleared. failure at any point after the device has exited a Reset The SCS bit (OSCCON<0>) is not updated. Enabling or Sleep condition and the Oscillator Start-up Timer FSCM does not affect the LTS bit. (OST) has expired. The FSCM sample clock is generated by dividing the INTOSC clock by 64. This will allow enough time FIGURE 4-8: FSCM BLOCK DIAGRAM between FSCM sample clocks for a system clock edge to occur. Figure4-8 shows the FSCM block diagram. On the rising edge of the sample clock, a monitoring latch (CM=0) will be cleared. On a falling edge of the Primary primary system clock, the monitoring latch will be set Clock Clock Clock (CM=1). In the event that a falling edge of the sample Fail Failure clock occurs, and the monitoring latch is not set, a clock Detector Detected failure has been detected. The assigned internal LFINTOSC ÷ 64 oscillator is enabled when FSCM is enabled as Oscillator reflected by the IRCF. Note 1: Two-Speed Start-up is automatically enabled when the Fail-Safe Clock Monitor mode is enabled. The FSCM function is enabled by setting the FCMEN 2: Primary clocks with a frequency ≤ ~488 bit in the Configuration Word (CONFIG). It is applicable Hz will be considered failed by the FSCM. to all external clock options (LP, XT, HS, EC or RC A slow starting oscillator can cause an modes). FSCM interrupt. In the event of an external clock failure, the FSCM will set the OSFIF bit (PIR2<7>) and generate an oscillator fail interrupt if the OSFIE bit (PIE2<7>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscillator unless the external clock recovers and the Fail-Safe condition is exited. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 81

PIC16F946 4.7.1 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction, or a modification of the SCS bit. While in Fail-Safe condition, the PIC16F946 uses the internal oscillator as the system without exiting the Fail-Safe condition. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. FIGURE 4-9: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 4.7.2 RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect oscillator failure at Note: Due to the wide range of oscillator start-up any point after the device has exited a Reset or Sleep times, the Fail-Safe circuit is not active condition and the Oscillator Start-up Timer (OST) has during oscillator start-up (i.e., after exiting expired. If the external clock is EC or RC mode, Reset or Sleep). After an appropriate monitoring will begin immediately following these amount of time, the user should check the events. OSTS bit (OSCCON<3>) to verify the For LP, XT or HS mode the external oscillator may oscillator start-up and system clock require a start-up time considerably longer than the switchover has successfully completed. FSCM sample clock time, a false clock failure may be detected (see Figure4-9). To prevent this, the internal oscillator is automatically configured as the system clock and functions until the external clock is stable (the OST has timed out). This is identical to Two-Speed Start-up mode. Once the external oscillator is stable, the LFINTOSC returns to its role as the FSCM source. TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Value on Value on: Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS(2) HTS LTS SCS -110 q000 -110 x000 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu 2007h(1) CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: See Register16-1 for operation of all Configuration Word bits. 2: See Register4-1 for details. Preliminary DS41265A-page 82 © 2005 Microchip Technology Inc.

PIC16F946 5.0 TIMER0 MODULE Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module The Timer0 module timer/counter has the following will increment either on every rising or falling edge of pin features: RA4/C1OUT/T0CKI/SEG4. The incrementing edge is (cid:129) 8-bit timer/counter determined by the source edge (T0SE) control bit (OPTION_REG<4>). Clearing the T0SE bit selects the (cid:129) Readable and writable rising edge. (cid:129) 8-bit software programmable prescaler (cid:129) Internal or external clock select 5.2 Timer0 Interrupt (cid:129) Interrupt on overflow from FFh to 00h A Timer0 interrupt is generated when the TMR0 (cid:129) Edge select for external clock register timer/counter overflows from FFh to 00h. This Figure5-1 is a block diagram of the Timer0 module and overflow sets the T0IF bit (INTCON<2>). The interrupt the prescaler shared with the WDT. can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit must be cleared in software by the Timer0 5.1 Timer0 Operation module Interrupt Service Routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the Timer mode is selected by clearing the T0CS bit processor from Sleep, since the timer is shut off during (OPTION_REG<5>). In Timer mode, the Timer0 Sleep. module will increment every instruction cycle (without prescaler). If TMR0 is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKO (= FOSC/4) Data Bus 0 8 1 SYNC 2 1 TMR0 Cycles T0CKI 0 pin 0 T0SE T0CS 8-bit Set Flag bit T0IF on Overflow Prescaler PSA 1 8 WDTE PSA SWDTEN PS<2:0> 1 WDT 16-bit Time-out 0 Prescaler 16 31kHz Watchdog INTOSC Timer PSA WDTPS<3:0> Note: T0SE, T0CS, PSA and PS<2:0> are bits in the Option register; WDTPS<3:0> are bits in the WDTCON register. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 83

PIC16F946 5.3 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20ns) and low for at least 2 TOSC (and a small RC delay of 20ns). Refer to the electrical specification of the desired device. REGISTER 5-1: OPTION_REG – OPTION REGISTER (ADDRESS: 81h OR 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values in WPUA register bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT/SEG0 pin 0 = Interrupt on falling edge of RB0/INT/SEG0 pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/C1OUT/T0CKI/SEG4 pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/C1OUT/T0CKI/SEG4 pin 0 = Increment on low-to-high transition on RA4/C1OUT/T0CKI/SEG4 pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate(1) 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Note1: A dedicated 16-bit WDT postscaler is available for the PIC16F946. See Section16.6 “Watchdog Timer (WDT)” for more information. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 84 © 2005 Microchip Technology Inc.

PIC16F946 5.4 Prescaler EXAMPLE 5-1: CHANGING PRESCALER (TIMER0→WDT) An 8-bit counter is available as a prescaler for the BCF STATUS,RP0 ;Bank 0 Timer0 module, or as a postscaler for the Watchdog CLRWDT ;Clear WDT Timer. For simplicity, this counter will be referred to as CLRF TMR0 ;Clear TMR0 and “prescaler” throughout this data sheet. The prescaler ; prescaler assignment is controlled in software by the control bit BSF STATUS,RP0 ;Bank 1 PSA (OPTION_REG<3>). Clearing the PSA bit will assign the prescaler to Timer0. Prescale values are MOVLW b’00101111’ ;Required if desired selectable via the PS<2:0> bits (OPTION_REG<2:0>). MOVWF OPTION_REG ; PS2:PS0 is CLRWDT ; 000 or 001 The prescaler is not readable or writable. When ; assigned to the Timer0 module, all instructions writing MOVLW b’00101xxx’ ;Set postscaler to to the TMR0 register (e.g., CLRF 1, MOVWF 1, MOVWF OPTION_REG ; desired WDT rate BSF 1, x....etc.) will clear the prescaler. When BCF STATUS,RP0 ;Bank 0 assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. To change prescaler from the WDT to the TMR0 module, use the sequence shown in Example5-2. This 5.4.1 SWITCHING PRESCALER precaution must be taken even if the WDT is disabled. ASSIGNMENT The prescaler assignment is fully under software control EXAMPLE 5-2: CHANGING PRESCALER (i.e., it can be changed “on-the-fly” during program (WDT→TIMER0) execution). To avoid an unintended device Reset, the CLRWDT ;Clear WDT and following instruction sequence (Example5-1 and ; prescaler Example5-2) must be executed when changing the BSF STATUS,RP0 ;Bank 1 prescaler assignment from Timer0 to WDT. MOVLW b’xxxx0xxx’ ;Select TMR0, ; prescale, and ; clock source MOVWF OPTION_REG ; BCF STATUS,RP0 ;Bank 0 TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 01h TMR0 Timer0 Module register xxxx xxxx uuuu uuuu 0Bh/10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 85

PIC16F946 NOTES: Preliminary DS41265A-page 86 © 2005 Microchip Technology Inc.

PIC16F946 6.0 TIMER1 MODULE WITH GATE The Timer1 Control register (T1CON), shown in CONTROL Register6-1, is used to enable/disable Timer1 and select the various features of the Timer1 module. The PIC16F946 has a 16-bit timer. Figure6-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: (cid:129) 16-bit timer/counter (TMR1H:TMR1L) (cid:129) Readable and writable (cid:129) Internal or external clock selection (cid:129) Synchronous or asynchronous operation (cid:129) Interrupt-on-overflow from FFFFh to 0000h (cid:129) Wake-up upon overflow (Asynchronous mode) (cid:129) Optional external enable input: - Selectable gate source: T1G or C2 output (T1GSS) - Selectable gate polarity (T1GINV) (cid:129) Optional LP oscillator FIGURE 6-1: TIMER1 ON THE PIC16F946 BLOCK DIAGRAM TMR1ON T1GE T1GINV Clear on special TMR1ON event trigger T1GE Set Flag bit TMR1IF on To C2 Comparator Module Overflow TMR1 Clock TMR1(1) Synchronized 0 Clock Input TMR1H TMR1L 1 LP OSC (2) T1SYNC OSC1/T1OSI 1 1 Synchronize Prescaler 1, 2, 4, 8 FOSC/4 det 0 Internal 0 OSC2/T1OSO Clock 2 Sleep Input T1CKPS<1:0> FOSC = 000 FOSC = x00 T1CS RC4/T1G/ 1 T1OSCEN SDO/SEG11 RC5/T1CKI/ C2OUT 0 CCP1/SEG10 T1GSS Note 1: Timer1 increments on the rising edge. 2: ST Buffer is low-power type when using LP oscillator or high-speed type when using T1CKI. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 87

PIC16F946 6.1 Timer1 Modes of Operation 6.3 Timer1 Prescaler Timer1 can operate in one of three modes: Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits (cid:129) 16-bit timer with prescaler (T1CON<5:4>) control the prescale counter. The (cid:129) 16-bit synchronous counter prescale counter is not directly readable or writable; (cid:129) 16-bit asynchronous counter however, the prescaler counter is cleared upon a write In Timer mode, Timer1 is incremented on every to TMR1H or TMR1L. instruction cycle. In Counter mode, Timer1 is incremented 6.4 Timer1 Gate on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to Timer1 gate source is software configurable to be the the microcontroller system clock or run asynchronously. T1G pin or the output of Comparator 2. This allows the In the Timer1 module, the module clock can be gated device to directly time external events using T1G or by the Timer1 gate, which can be selected as either the analog events using Comparator 2. See CMCON1 T1G pin or Comparator 2 output. (Register8-2) for selecting the Timer1 gate source. If an external clock oscillator is needed (and the This feature can simplify the software for a Delta-Sigma microcontroller is using the INTOSC without CLKO), A/D converter and many other applications. For more Timer1 can use the LP oscillator as a clock source. information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Note: In Counter mode, a falling edge must be registered by the counter prior to the first Note: T1GE bit (T1CON<6>) must be set to use incrementing rising edge. either T1G or C2OUT as the Timer1 gate source. See Register8-2 for more 6.2 Timer1 Interrupt information on selecting the Timer1 gate source. The Timer1 register pair (TMR1H:TMR1L) increments Timer1 gate can be inverted using the T1GINV bit to FFFFh and rolls over to 0000h. When Timer1 rolls (T1CON<7>), whether it originates from the T1G pin or over, the Timer1 Interrupt Flag bit (PIR1<0>) is set. To Comparator 2 output. This configures Timer1 to enable the interrupt on rollover, you must set these bits: measure either the active-high or active-low time (cid:129) Timer1 Interrupt Enable bit (PIE1<0>) between events. (cid:129) PEIE bit (INTCON<6>) (cid:129) GIE bit (INTCON<7>) The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. Preliminary DS41265A-page 88 © 2005 Microchip Technology Inc.

PIC16F946 REGISTER 6-1: T1CON – TIMER1 CONTROL REGISTER (ADDRESS: 10h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is inverted 0 = Timer1 gate is not inverted bit 6 T1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored. If TMR1ON = 1: 1 = Timer1 gate is enabled 0 = Timer1 gate is disabled bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value bit 3 T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKO oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from RC5/T1CKI/CCP1/SEG10 pin or T1OSC (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: T1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit (CMCON1<1>), as a Timer1 gate source. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 89

PIC16F946 6.5 Timer1 Operation in 6.6 TIMER1 OSCILLATOR Asynchronous Counter Mode To minimize the multiplexing of peripherals on the I/O If control bit T1SYNC (T1CON<2>) is set, the external ports, the dedicated TMR1 oscillator, which is normally clock input is not synchronized. The timer continues to used for TMR1 real-time clock applications, is eliminated. increment asynchronous to the internal phase clocks. Instead, the TMR1 module can enable the LP oscillator. The timer will continue to run during Sleep and can If the microcontroller is programmed to run from generate an interrupt-on-overflow, which will wake-up INTOSC with no CLKO or LP oscillator: the processor. However, special precautions in 1. Setting the T1OSCEN and TMR1CS bits to ‘1’ software are needed to read/write the timer (see will enable the LP oscillator to clock TMR1 while Section6.5.1 “Reading and Writing Timer1 in the microcontroller is clocked from either the Asynchronous Counter Mode”). INTOSC or LP oscillator. Note that the T1OSC Note: The ANSEL (91h) and CMCON0 (9Ch) and LP oscillators share the same circuitry. registers must be initialized to configure an Therefore, when LP oscillator is selected and analog channel as a digital input. Pins T1OSC is enabled, both the microcontroller and configured as analog inputs will read ‘0’. the Timer1 module share the same clock source. 6.5.1 READING AND WRITING TIMER1 IN 2. Sleep mode does not shut off the LP oscillator ASYNCHRONOUS COUNTER operation (i.e., if the INTOSC oscillator runs MODE the microcontroller, T1OSCEN=1 and Reading TMR1H or TMR1L, while the timer is running TMR1CS=1, TMR1 is running from the LP from an external asynchronous clock, will ensure a oscillator), then the LP oscillator will continue to valid read (taken care of in hardware). However, the run during Sleep mode. user should keep in mind that reading the 16-bit timer In all oscillator modes except for INTOSC with no in two 8-bit values itself, poses certain problems, since CLKOUT and LP, the T1OSC enable option is unavail- the timer may overflow between the reads. able and is ignored. For writes, it is recommended that the user simply stop Note: When INTOSC without CLKO oscillator is the timer and write the desired values. A write selected and T1OSCEN = 1, the LP contention may occur by writing to the timer registers, oscillator will run continuously independent while the register is incrementing. This may produce an of the TMR1ON bit. unpredictable value in the timer register. Reading the 16-bit value requires some care. 6.7 Resetting Timer1 Using a CCP Examples in the “PICmicro® Mid-Range MCU Family Trigger Output Reference Manual” (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode. If the CCP1 or CCP2 module is configured in Compare mode to generate a “special event trigger” (CCP1M<3:0> = 1011), this signal will reset Timer1. Note: The special event triggers from the CCP1 and CCP2 modules will not set interrupt flag bit, TMR1IF (PIR1<0>). Timer1 must be configured for either Timer or Synchro- nized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for Timer1. Preliminary DS41265A-page 90 © 2005 Microchip Technology Inc.

PIC16F946 6.8 Resetting of Timer1 Register Pair (TMR1H, TMR1L) TMR1H and TMR1L registers are not reset to 00h on a POR, or any other Reset, except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other Resets, the register is unaffected. 6.9 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: (cid:129) Timer1 must be on (T1CON<0>) (cid:129) TMR1IE bit (PIE1<0>) must be set (cid:129) PEIE bit (INTCON<6>) must be set The device will wake-up on an overflow. If the GIE bit (INTCON<7>) is set, the device will wake-up and jump to the Interrupt Service Routine (0004h) on an overflow. If the GIE bit is clear, execution will continue with the next instruction. TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER1 Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh/ INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 8Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu 97h CMCON1 — — — — — — T1GSS C2SYNC ---- --10 ---- --10 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 91

PIC16F946 NOTES: Preliminary DS41265A-page 92 © 2005 Microchip Technology Inc.

PIC16F946 7.0 TIMER2 MODULE 7.1 Timer2 Operation The Timer2 module timer has the following features: Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is (cid:129) 8-bit timer (TMR2 register) readable and writable, and is cleared on any device (cid:129) 8-bit period register (PR2) Reset. The input clock (FOSC/4) has a prescale option (cid:129) Readable and writable (both registers) of 1:1, 1:4 or 1:16, selected by control bits T2CKPSx (cid:129) Software programmable prescaler (1:1, 1:4, 1:16) (T2CON<1:0>). The match output of TMR2 goes (cid:129) Software programmable postscaler (1:1 to 1:16) through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched (cid:129) Interrupt on TMR2 match with PR2 in flag bit TMR2IF, (PIR1<1>)). Timer2 has a control register shown in Register7-1. The prescaler and postscaler counters are cleared TMR2 can be shut-off by clearing control bit TMR2ON when any of the following occurs: (T2CON<2>) to minimize power consumption. Figure7-1 is a simplified block diagram of the Timer2 (cid:129) A write to the TMR2 register module. The prescaler and postscaler selection of (cid:129) A write to the T2CON register Timer2 are controlled by this register. (cid:129) Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 7-1: T2CON – TIMER2 CONTROL REGISTER (ADDRESS: 12h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits 0000 =1:1 Postscale 0001 =1:2 Postscale (cid:129) (cid:129) (cid:129) 1111 =1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 =Prescaler is 1 01 =Prescaler is 4 1x =Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 93

PIC16F946 7.2 Timer2 Interrupt 7.3 Timer2 Output The Timer2 module has an 8-bit period register, PR2. The output of TMR2 (before the postscaler) is fed to the Timer2 increments from 00h until it matches PR2 and SSP module, which optionally uses it to generate the then resets to 00h on the next increment cycle. PR2 is shift clock. a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 7-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 Output(1) bit TMR2IF Prescaler Reset FOSC/4 TMR2 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T2CKPS<1:0> PR2 4 TOUTPS<3:0> Note1: TMR2 register output can be software selected by the SSP module as a baud clock. TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh/ INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 8Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 11h TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 92h PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Preliminary DS41265A-page 94 © 2005 Microchip Technology Inc.

PIC16F946 8.0 COMPARATOR MODULE The CMCON0 register (Register8-1) controls the comparator input and output multiplexers. A block The Comparator module contains two analog diagram of the various comparator configurations is comparators. The inputs to the comparators are shown in Figure8-3. multiplexed with I/O port pins RA<3:0>, while the outputs are multiplexed to pins RA<5:4>. An on-chip Comparator Voltage Reference (CVREF) can also be applied to the inputs of the comparators. REGISTER 8-1: CMCON0 – COMPARATOR CONFIGURATION REGISTER (ADDRESS: 9Ch) R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 0 = C2 VIN+ > C2 VIN- 1 = C2 VIN+ < C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 0 = C1 VIN+ > C1 VIN- 1 = C1 VIN+ < C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 Output inverted 0 = C2 Output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 Output inverted 0 = C1 Output not inverted bit 3 CIS: Comparator Input Switch bit When CM<2:0> = 010: 1 = C1 VIN- connects to RA3/AN3/C1+/VREF+/SEG15 C2 VIN- connects to RA2/AN2/C2+/VREF-/COM2 0 = C1 VIN- connects to RA0/AN0/C1-/SEG12 C2 VIN- connects to RA1/AN1/C2-/SEG7 When CM<2:0> = 001: 1 = C1 VIN- connects to RA3/AN3/C1+/VREF+/SEG15 0 = C1 VIN- connects to RA0/AN0/C1-/SEG12 When CM<2:0> = 101: 1 = C2 VIN+ connects to internal 0.6V reference 0 = C2 VIN+ connects to RA2/AN2/C2+/VREF-/COM2 bit 2-0 CM<2:0>: Comparator Mode bits(1) See Figure8-3 for comparator modes and CM<2:0> bit settings. Note1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 95

PIC16F946 8.1 Comparator Operation FIGURE 8-1: SINGLE COMPARATOR A single comparator is shown in Figure8-1 along with the relationship between the analog input levels and VIN+ + Output the digital output. When the analog input at VIN+ is less VIN- – than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure8-1 represent VIVNI-N– the uncertainty due to input offsets and response time. VVININ++ Note: To use CIN+ and CIN- pins as analog inputs, the appropriate bits must be programmed in the CMCON0 (9Ch) Output register. Output The polarity of the comparator output can be inverted by setting the CxINV bits (CMCON0<5:4>). Clearing 8.2 Analog Input Connection CxINV results in a non-inverted output. A complete Considerations table showing the output state versus input conditions and the polarity bit is shown in Table8-1. A simplified circuit for an analog input is shown in Figure8-2. Since the analog pins are connected to a TABLE 8-1: OUTPUT STATE VS. INPUT digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between CONDITIONS VSS and VDD. If the input voltage deviates from this Input Conditions CINV CxOUT range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A VIN- > VIN+ 0 0 maximum source impedance of 10 kΩ is recommended VIN- < VIN+ 0 1 for the analog sources. Any external component VIN- > VIN+ 1 1 connected to an analog input pin, such as a capacitor VIN- < VIN+ 1 0 or a Zener diode, should have very little leakage. FIGURE 8-2: ANALOG INPUT MODEL VDD Rs < 10K VT = 0.6V RIC AIN VA C5 PpIFN VT = 0.6V L±5ea00ka ngAe Vss Legend: CPIN= Input Capacitance VT = Threshold Voltage ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage Preliminary DS41265A-page 96 © 2005 Microchip Technology Inc.

PIC16F946 8.3 Comparator Configuration If the Comparator mode is changed, the comparator output level may not be valid for the specified mode There are eight modes of operation for the comparators. change delay shown in Section19.0 “Electrical The CMCON0 register is used to select these modes. Specifications”. Figure8-3 shows the eight possible modes. Note: Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur. FIGURE 8-3: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) Comparators Off CM<2:0> = 000 CM<2:0> = 111 RA0/AN0/ A VIN- RA0/AN0/ D VIN- C1-/SEG12 C1-/SEG12 RA3/AN3/ A VIN+ C1 Off (Read as ‘0’) RA3/AN3/ D VIN+ C1 Off (Read as ‘0’) C1+/VREF+/SEG15 C1+/VREF+/SEG15 RA1/AN1/ A VIN- RA1/AN1/ D VIN- C2-/SEG7 C2-/SEG7 RA2/AN2/ A VIN+ C2 Off (Read as ‘0’) RA2/AN2/ D VIN+ C2 Off (Read as ‘0’) C2+/VREF-/COM2 C2+/VREF-/COM2 Four Inputs Multiplexed to Two Comparators Two Independent Comparators CM<2:0> = 010 CM<2:0> = 100 RA0/AN0/ A RA0/AN0/ A VIN- C1-/SEG12 CIS = 0 VIN- C1-/SEG12 RA3/AN3/ A CIS = 1 RA3/AN3/ A VIN+ C1 C1OUT C1+/VREF+/SEG15 VIN+ C1 C1OUT C1+/VREF+/SEG15 RA1/AN1/ A C2-/SEG7 CIS = 0 VIN- RC2A-1/S/AENG17/ A VIN- RA2/AN2/ A CIS = 1 VIN+ C2 C2OUT RA2/AN2/ A VIN+ C2 C2OUT C2+/VREF-/COM2 C2+/VREF-/COM2 From CVREF Module Two Common Reference Comparators Two Common Reference Comparators with Outputs CM<2:0> = 011 CM<2:0> = 110 RA0/AN0/ A VIN- RA0/AN0/ A VIN- CR1A-3/S/AENG31/2 D VIN+ C1 C1OUT C1-/SEG12 VIN+ C1 C1OUT C1+/VREF+/SEG15 RA4 RA1/AN1/ RA1/AN1/ A VIN- C2-/SEG7 A VIN- CR2A-2/S/AENG27/ A VIN+ C2 C2OUT RA2/AN2/ A VIN+ C2 C2OUT C2+/VREF-/COM2 C2+/VREF-/COM2 RA5 One Independent Comparator with Reference Option Three Inputs Multiplexed to Two Comparators CM<2:0> = 101 CM<2:0> = 001 RA0/AN0/ D VIN- RA0/AN0/ A C1-/SEG12 C1-/SEG12 CIS = 0 VIN- RA3/AN3/ D VIN+ C1 Off (Read as ‘0’) RA3/AN3/ A CIS = 1 C1+/VREF+/ C1+/VREF+/SEG15 VIN+ C1 C1OUT SEG15 RA1/AN1/ A VIN- RA1/AN1/ A VIN- C2-/SEG7 C2-/SEG7 RA2/AN2/ A CIS = 0 VIN+ C2 C2OUT RA2/AN2/ A VIN+ C2 C2OUT C2+/VREF-/ A CIS = 1 C2+/VREF-/COM2 COM2 RA5 Internal 0.6V reference Legend: A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON0<3>) is the computer Input Switch. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 97

PIC16F946 FIGURE 8-4: COMPARATOR C1 OUTPUT BLOCK DIAGRAM M P U ort P LTIP C1INV in L s E X To C1OUT pin To Data Bus Q D EN RD CMCON Set C1IF bit Q D EN RD CMCON CL NReset FIGURE 8-5: COMPARATOR C2 OUTPUT BLOCK DIAGRAM M P U ort P LTIP C2INV in L s E X C2SYNC To TMR1 0 To C2OUT pin 1 Q D EN TMR1 Clock Source(1) To Data Bus Q D EN RD CMCON Set C2IF bit Q D EN RD CMCON CL Reset Note 1: Comparator 2 output is latched on falling edge of T1 clock source. Preliminary DS41265A-page 98 © 2005 Microchip Technology Inc.

PIC16F946 REGISTER 8-2: CMCON1 – COMPARATOR CONFIGURATION REGISTER (ADDRESS: 97h) U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 — — — — — — T1GSS C2SYNC bit 7 bit 0 bit 7-2: Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit 1 = Timer1 gate source is T1G pin (RC4 must be configured as digital input) 0 = Timer1 gate source is Comparator 2 Output bit 0 C2SYNC: Comparator 2 Synchronize bit 1 = C2 output synchronized with falling edge of Timer1 clock 0 = C2 output not synchronized with Timer1 clock Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 8.4 Comparator Outputs 8.5 Comparator Interrupts The comparator outputs are read through the The comparator interrupt flags are set whenever there is CMCON0 register. These bits are read-only. The a change in the output value of its respective comparator. comparator outputs may also be directly output to the Software will need to maintain information about the RA4 and RA5 I/O pins. When enabled, multiplexers in status of the output bits, as read from CMCON0<7:6>, to the output path of the RA4 and RA5 pins will switch determine the actual change that has occurred. The CxIF and the output of each pin will be the unsynchronized bits, PIR2<6:5>, are the Comparator Interrupt flags. This output of the comparator. The uncertainty of each of bit must be reset in software by clearing it to ‘0’. Since it the comparators is related to the input offset voltage is also possible to write a ‘1’ to this register, a simulated and the response time given in the specifications. interrupt may be initiated. Figure8-4 and Figure8-5 show the output block The CxIE bits (PIE2<6:5>) and the PEIE bit diagram for Comparator 1 and 2. (INTCON<6>) must be set to enable the interrupts. In The TRIS bits will still function as an output addition, the GIE bit must also be set. If any of these enable/disable for the RA4 and RA5 pins while in this bits are cleared, the interrupt is not enabled, though the mode. CxIF bits will still be set if an interrupt condition occurs. The polarity of the comparator outputs can be changed The user, in the Interrupt Service Routine, can clear the using the C1INV and C2INV bits (CMCON0<5:4>). interrupt in the following manner: Timer1 gate source can be configured to use the T1G a) Any read or write of CMCON0. This will end the pin or Comparator 2 output as selected by the T1GSS mismatch condition. bit (CMCON1<1>). This feature can be used to time b) Clear flag bit CxIF the duration or interval of analog events. The output of A mismatch condition will continue to set flag bit CxIF. Comparator 2 can also be synchronized with Timer1 Reading CMCON0 will end the mismatch condition and by setting the C2SYNC bit (CMCON1<0>). When allow flag bits CxIF to be cleared. enabled, the output of Comparator 2 is latched on the falling edge of Timer1 clock source. If a prescaler is Note: If a change in the CMCON0 register used with Timer1, Comparator 2 is latched after the (CxOUT) should occur when a read prescaler. To prevent a race condition, the Comparator operation is being executed (start of the Q2 2 output is latched on the falling edge of the Timer1 cycle), then the CxIF (PIR2<6:5>) interrupt clock source and Timer1 increments on the rising edge flag may not get set. of its clock source. See (Figure8-5), Comparator 2 Block Diagram and (Figure5-1), Timer1 Block Diagram for more information. It is recommended to synchronize Comparator 2 with Timer1 by setting the C2SYNC bit when Comparator 2 is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if Comparator 2 changes during an increment. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 99

PIC16F946 8.6 Comparator Reference 8.6.2 VOLTAGE REFERENCE ACCURACY/ERROR The Comparator module also allows the selection of an internally generated voltage reference for one of the The full range of VSS to VDD cannot be realized due to comparator inputs. The VRCON register, Register8-3, the construction of the module. The transistors on the controls the voltage reference module shown in top and bottom of the resistor ladder network Figure8-6. (Figure8-6) keep CVREF from approaching VSS or VDD. The exception is when the module is disabled by 8.6.1 CONFIGURING THE VOLTAGE clearing the VREN bit (VRCON<7>). When disabled, REFERENCE the reference voltage is VSS when VR<3:0> = 0000. This allows the comparators to detect a zero-crossing The voltage reference can output 32 distinct voltage and not consume CVREF module current. levels; 16 in a high range and 16 in a low range. The voltage reference is VDD derived and therefore, the The following equation determines the output voltages: CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the comparator voltage EQUATION 8-1: reference can be found in Section19.0 “Electrical VRR = 1 (low range): CVREF = (VR3:VR0/24) x VDD Specifications”. VRR = 0 (high range): CVREF = (VDD/4) + (VR3:VR0 x VDD/32) FIGURE 8-6: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR 16-1 Analog MUX VREN CVREF to Comparator Input VR<3:0> VREN VR <3:0> = ‘0000’ Preliminary DS41265A-page 100 © 2005 Microchip Technology Inc.

PIC16F946 8.7 Comparator Response Time 8.9 Effects of a Reset Response time is the minimum time, after selecting a A device Reset forces the CMCON0, CMCON1 and new reference voltage or input source, before the VRCON registers to their Reset states. This forces the comparator output is ensured to have a valid level. If Comparator module to be in the Comparator Reset the internal reference is changed, the maximum delay mode, CM<2:0>=000 and the voltage reference to its of the internal voltage reference must be considered OFF state. Thus, all potential inputs are analog inputs when using the comparator outputs. Otherwise, the with the comparator and voltage reference disabled to maximum delay of the comparators should be used consume the smallest current possible. (Table19-9). 8.8 Operation During Sleep The comparators and voltage reference, if enabled before entering Sleep mode, remain active during Sleep. This results in higher Sleep currents than shown in the power-down specifications. The additional current consumed by the comparator and the voltage reference is shown separately in the specifications. To minimize power consumption while in Sleep mode, turn off the comparator, CM<2:0> = 111, and voltage reference, VRCON<7> = 0. While the comparator is enabled during Sleep, an interrupt will wake-up the device. If the GIE bit (INTCON<7>) is set, the device will jump to the inter- rupt vector (0004h), and if clear, continues execution with the next instruction. If the device wakes up from Sleep, the contents of the CMCON0, CMCON1 and VRCON registers are not affected. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 101

PIC16F946 REGISTER 8-3: VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 9Dh) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN — VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 bit 7 VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS. bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ bit 3-0 VR<3:0>: CVREF Value Selection bits 0 ≤ VR<3:0> ≤ 15 When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown TABLE 8-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 0Dh PIR2 OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF 0000 -0-0 0000 -0-0 9Ch CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 97h CMCON1 — — — — — — T1GSS C2SYNC ---- --10 ---- --10 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 8Dh PIE2 OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE 0000 -0-0 0000 -0-0 9Dh VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the comparator or Comparator Voltage Reference module. Preliminary DS41265A-page 102 © 2005 Microchip Technology Inc.

PIC16F946 9.0 LIQUID CRYSTAL DISPLAY Once the module is initialized for the LCD panel, the (LCD) DRIVER MODULE individual bits of the LCDDATA<11:0> registers are cleared/set to represent a clear/dark pixel, The Liquid Crystal Display (LCD) driver module respectively: generates the timing control to drive a static or (cid:129) LCDDATA0 SEG7COM0:SEG0COM0 multiplexed LCD panel. In the PIC16F946 device, the (cid:129) LCDDATA1 SEG15COM0:SEG8COM0 module drives the panels of up to four commons and up (cid:129) LCDDATA2 SEG23COM0:SEG16COM0 to 42 segments. It also provides control of the LCD pixel data. (cid:129) LCDDATA3 SEG7COM1:SEG0COM1 (cid:129) LCDDATA4 SEG15COM1:SEG8COM1 The LCD driver module supports: (cid:129) LCDDATA5 SEG23COM1:SEG16COM1 (cid:129) Direct driving of LCD panel (cid:129) LCDDATA6 SEG7COM2:SEG0COM2 (cid:129) Three LCD clock sources with selectable prescaler (cid:129) LCDDATA7 SEG15COM2:SEG8COM2 (cid:129) Up to four commons: (cid:129) LCDDATA8 SEG23COM2:SEG16COM2 - Static (cid:129) LCDDATA9 SEG7COM3:SEG0COM3 - 1/2 multiplex (cid:129) LCDDATA10 SEG15COM3:SEG8COM3 - 1/3 multiplex (cid:129) LCDDATA11 SEG23COM3:SEG16COM3 - 1/4 multiplex (cid:129) LCDDATA12 SEG31COM0:SEG24COM0 (cid:129) 42 segments (cid:129) LCDDATA13 SEG39COM0:SEG32COM0 (cid:129) Static, 1/2 or 1/3 LCD Bias (cid:129) LCDDATA14 SEG41COM0:SEG40COM0 The module has 32 registers: (cid:129) LCDDATA15 SEG31COM1:SEG24COM1 (cid:129) LCD Control Register (LCDCON) (cid:129) LCDDATA16 SEG39COM1:SEG32COM1 (cid:129) LCD Phase Register (LCDPS) (cid:129) LCDDATA17 SEG41COM1:SEG40COM1 (cid:129) Six LCD Segment Enable Registers (cid:129) LCDDATA18 SEG31COM2:SEG24COM2 (LCDSE<5:0>) (cid:129) LCDDATA19 SEG39COM2:SEG32COM2 (cid:129) 24 LCD Data Registers (LCDDATA<11:0>) (cid:129) LCDDATA20 SEG41COM2:SEG40COM2 The LCDCON register, shown in Register9-1, controls (cid:129) LCDDATA21 SEG31COM3:SEG24COM3 the operation of the LCD driver module. The LCDPS (cid:129) LCDDATA22 SEG39COM3:SEG32COM3 register, shown in Register9-2, configures the LCD (cid:129) LCDDATA23 SEG41COM3:SEG40COM3 clock source prescaler and the type of waveform; Type-A or Type-B. The LCDSE<2:0> registers configure As an example, LCDDATAx is detailed in Register9-4. the functions of the port pins: Once the module is configured, the LCDEN (cid:129) LCDSE0 SE<7:0> (LCDCON<7>) bit is used to enable or disable the LCD (cid:129) LCDSE1 SE<15:8> module. The LCD panel can also operate during Sleep by clearing the SLPEN (LCDCON<6>) bit. (cid:129) LCDSE2 SE<23:16> (cid:129) LCDSE3 SE<31:24> (cid:129) LCDSE4 SE<39:32> (cid:129) LCDSE5 SE<41:40> As an example, LCDSEn is detailed in Register9-3. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 103

PIC16F946 FIGURE 9-1: LCD DRIVER MODULE BLOCK DIAGRAM 168 LCDDATAx Data Bus Registers to SEG<42:0> 24 x 8 42 To I/O Pads(1) (= 4 x 24) MUX Timing Control LCDCON COM<3:0> LCDPS To I/O Pads(1) LCDSEn FOSC/8192 Clock Source T10SC/32 Select and Prescaler LFINTOSC/32 Note 1: These signals are connected directly to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module. Preliminary DS41265A-page 104 © 2005 Microchip Technology Inc.

PIC16F946 REGISTER 9-1: LCDCON – LIQUID CRYSTAL DISPLAY CONTROL REGISTER (ADDRESS: 107h) R/W-0 R/W-0 R/C-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 bit 7 bit 0 bit 7 LCDEN: LCD Driver Enable bit 1 = LCD driver module is enabled 0 = LCD driver module is disabled bit 6 SLPEN: LCD Driver Enable in Sleep mode bit 1 = LCD driver module is disabled in Sleep mode 0 = LCD driver module is enabled in Sleep mode bit 5 WERR: LCD Write Failed Error bit 1 = LCDDATAx register written while LCDPS<WA> = 0 (must be cleared in software) 0 = No LCD write error bit 4 VLCDEN: LCD Bias Voltage Pins Enable bit 1 = VLCD pins are enabled 0 = VLCD pins are disabled bit 3-2 CS<1:0>: Clock Source Select bits 00 = FOSC/8192 01 = T1OSC (Timer1)/32 1x = LFINTOSC (31 kHz)/32 bit 1-0 LMUX<1:0>: Commons Select bits LMUX<1:0> Multiplex Maximum Number of Pixels Bias 00 Static (COM0) 42 Static 01 1/2 (COM<1:0>) 84 1/2 or 1/3 10 1/3 (COM<2:0>) 126 1/2 or 1/3 11 1/4 (COM<3:0>) 168 1/3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Only clearable bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown - n = Value at POR Preliminary © 2005 Microchip Technology Inc. DS41265A-page 105

PIC16F946 REGISTER 9-2: LCDPS – LCD PRESCALER SELECT REGISTER (ADDRESS: 108h) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 bit 7 bit 0 bit 7 WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary) 0 = Type-A waveform (phase changes within each common type) bit 6 BIASMD: Bias Mode Select bit When LMUX<1:0> = 00: 0 = Static Bias mode (do not set this bit to ‘1’) When LMUX<1:0> = 01: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 10: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 11: 0 = 1/3 Bias mode (do not set this bit to ‘1’) bit 5 LCDA: LCD Active Status bit 1 = LCD driver module is active 0 = LCD driver module is inactive bit 4 WA: LCD Write Allow Status bit 1 = Write into the LCDDATAx registers is allowed 0 = Write into the LCDDATAx registers is not allowed bit 3-0 LP<3:0>: LCD Prescaler Select bits 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 106 © 2005 Microchip Technology Inc.

PIC16F946 REGISTER 9-3: LCDSEn – LCD SEGMENT REGISTERS (ADDRESS: 11Ch, 11Dh, 11Eh, 19Ch, 19Dh, OR 19Eh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEn SEn SEn SEn SEn SEn SEn SEn bit 7 bit 0 bit 7-0 SEn: Segment Enable bits 1 = Segment function of the pin is enabled 0 = I/O function of the pin is enabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 9-4: LCDDATAx – LCD DATA REGISTERS (ADDRESS: 110h-119h, 11Ah, 11Bh, 190h-199h, 19Ah, OR 19Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEGx- SEGx- SEGx- SEGx- SEGx- SEGx- SEGx- SEGx- COMy COMy COMy COMy COMy COMy COMy COMy bit 7 bit 0 bit 7-0 SEGx-COMy: Pixel On bits 1 = Pixel on (dark) 0 = Pixel off (clear) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 107

PIC16F946 9.1 LCD Clock Source Selection 9.1.1 LCD PRESCALER The LCD driver module has 3 possible clock sources: A 16-bit counter is available as a prescaler for the LCD clock. The prescaler is not directly readable or writable; (cid:129) F OSC/8192 its value is set by the LP<3:0> bits (LCDPS<3:0>), which (cid:129) T1OSC/32 determine the prescaler assignment and prescale ratio. (cid:129) LFINTOSC/32 The prescale values from 1:1 through 1:16. The first clock source is the system clock divided by 8192 (FOSC/8192). This divider ratio is chosen to 9.2 LCD Bias Types provide about 1 kHz output when the system clock is 8MHz. The divider is not programmable. Instead, the The LCD driver module can be configured into three LCD prescaler bits, LCDPS<3:0>, are used to set the bias types: LCD frame clock rate. (cid:129) Static Bias (2 voltage levels: V SS and VDD) The second clock source is the T1OSC/32. This also (cid:129) 1/2 Bias (3 voltage levels: V SS, 1/2 VDD and VDD) gives about 1 kHz when a 32.768 kHz crystal is used (cid:129) 1/3 Bias (4 voltage levels: V SS, 1/3 VDD, 2/3 VDD with the Timer1 oscillator. To use the Timer1 oscillator and VDD) as a clock source, the T1OSCEN (T1CON<3>) bit This module uses an external resistor ladder to should be set. generate the LCD bias voltages. The third clock source is the 31 kHz LFINTOSC/32, which The external resistor ladder should be connected to the provides approximately 1 kHz output. Bias 1 pin, Bias 2 pin, Bias 3 pin and VSS. The Bias 3 The second and third clock sources may be used to pin should also be connected to VDD. continue running the LCD while the processor is in Figure9-2 shows the proper way to connect the Sleep. resistor ladder to the Bias pins. Using the bits, CS<1:0> (LCDCON<3:2>), any of these Note: VLCD pins used to supply LCD bias clock sources can be selected. voltage are enabled on power-up (POR) and must be disabled by the user by clearing LCDCON<4>, the VLCDEN bit, (see Register9-1). FIGURE 9-2: LCD BIAS RESISTOR LADDER CONNECTION DIAGRAM Static 1/2 Bias 1/3 Bias Bias VLCD 0 VSS VSS VSS VLCD 3 To VLCD 1 — 1/2 VDD 1/3 VDD VLCD 2 LCD VLCD 2 — 1/2 VDD 2/3 VDD VVLLCCDD 10(1) Driver VLCD 3 VDD VDD VDD LCD Bias 3 LCD Bias 2 LCD Bias 1 Connections for External R-ladder VDD* Static Bias 1/2 Bias VDD* 10kΩ* 10kΩ* VSS VDD* 10kΩ* 10kΩ* 10kΩ* 1/3 Bias VSS * These values are provided for design guidance only and should be optimized for the application by the designer. Note 1: Internal connection. Preliminary DS41265A-page 108 © 2005 Microchip Technology Inc.

PIC16F946 9.3 LCD Multiplex Types TABLE 9-2: FRAME FREQUENCY FORMULAS The LCD driver module can be configured into four multiplex types: Multiplex Frame Frequency = (cid:129) Static (only COM0 used) Static Clock source/(4 x 1 x (LP<3:0> + 1)) (cid:129) 1/2 multiplex (COM0 and COM1 are used) 1/2 Clock source/(2 x 2 x (LP<3:0> + 1)) (cid:129) 1/3 multiplex (COM0, COM1 and COM2 are used) 1/3 Clock source/(1 x 3 x (LP<3:0> + 1)) (cid:129) 1/4 multiplex (all COM0, COM1, COM2 and COM3 1/4 Clock source/(1 x 4 x (LP<3:0> + 1)) are used) Note: Clock source is FOSC/8192, T1OSC/32 or The LMUX<1:0> setting decides the function of RB5, LFINTOSC/32. RA2 and RD0 pins (see Table9-1 for details). If the pin is a digital I/O, the corresponding TRIS bit TABLE 9-3: APPROXIMATE FRAME controls the data direction. If the pin is a COM drive, FREQUENCY (IN Hz) USING then the TRIS setting of that pin is overridden. FOSC @ 8 MHz, TIMER1 @ 32.768 kHz OR INTOSC Note: On a Power-on Reset, the LMUX<1:0> bits are ‘11’. LP<3:0> Static 1/2 1/3 1/4 TABLE 9-1: RD0, RA2, RB5 FUNCTION 2 85 85 114 85 3 64 64 85 64 LMUX RD0 RA2 RB5 <1:0> 4 51 51 68 51 5 43 43 57 43 00 Digital I/O Digital I/O Digital I/O 6 37 37 49 37 01 Digital I/O Digital I/O COM1 Driver 7 32 32 43 32 10 Digital I/O COM2 Driver COM1 Driver 11 COM3 Driver COM2 Driver COM1 Driver 9.4 Segment Enables The LCDSEn registers are used to select the pin function for each segment pin. The selection allows each pin to operate as either an LCD segment driver or as one of the pin’s alternate functions. To configure the pin as a segment pin, the corresponding bits in the LCDSEn registers must be set to ‘1’. See Figures9-4 and9-5 for more details. If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. Any bit set in the LCDSEn registers overrides any bit settings in the corresponding TRIS register. Note: On a Power-on Reset, these pins are configured as digital I/O. 9.5 Pixel Control The LCDDATAx registers contain bits which define the state of each pixel. Each bit defines one unique pixel. Register9-4 shows the correlation of each bit in the LCDDATAx registers to the respective common and segment signals. Any LCD pixel location not being used for display can be used as general purpose RAM. 9.6 LCD Frame Frequency The rate at which the COM and SEG outputs change is called the LCD frame frequency. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 109

PIC16F946 FIGURE 9-3: LCD CLOCK GENERATION 0 12 3 FOSC ÷8192 M MM M O OO O C CC C ÷4 STAT T1OSC 32 kHz ÷32 Crystal Osc. ÷1, 2, 3, 4 ÷2 DUP 4-bit Prog Presc Ring Counter TRIP QUAD LFINTOSC ÷32 Nom FRC=31kHz LP<3:0> LMUX<1:0> (LCDPS<3:0>) (LCDCON<1:0>) CS<1:0> LMUX<1:0> (LCDCON<3:2>) (LCDCON<1:0>) Preliminary DS41265A-page 110 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 9-4: LCD SEGMENT MAPPING WORKSHEET (PART 1 OF 2) AlternateFunctions INT C1OUT/T0CKI C2OUT/AN4/SS AN1 RX/DT/SDI/SDA TX/CK/SCK/SCL T1CKI/CCP1 /SDOT1G AN0 CSPDAT/ICDDAT ICSPCK/ICDCK AN3/V+REF AN5 AN6 AN7 I ORT RB0 RB1 RB2 RB3 RA4 RA5 RC3 RA1 RC7 RC6 RC5 RC4 RA0 RB7 RB6 RA3 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 P n Pin No. 8/40-pi 21/33 22/34 23/35 24/36 6/6 7/7 14/18 3/3 18/26 17/25 16/24 15/23 2/2 28/40 27/39 5/5 -/26 -/27 -/28 -/29 -/30 -/8 -/9 -/10 2 nt CDme Lg e S 3 M CO CDDATAxAddress DDATA9, 0 DDATA9, 1 DDATA9, 2 DDATA9, 3 DDATA9, 4 DDATA9, 5 DDATA9, 6 DDATA9, 7 DDATA10, 0 DDATA10, 1 DDATA10, 2 DDATA10, 3 DDATA10, 4 DDATA10, 5 DDATA10, 6 DDATA10, 7 DDATA11, 0 DDATA11, 1 DDATA11, 2 DDATA11, 3 DDATA11, 4 DDATA11, 5 DDATA11, 6 DDATA11, 7 L C C C C C C C C C C C C C C C C C C C C C C C C L L L L L L L L L L L L L L L L L L L L L L L L nt CDme Lg e S 2 M O C Axs 6, 0 6, 1 6, 2 6, 3 6, 4 6, 5 6, 6 6, 7 7, 0 7, 1 7, 2 7, 3 7, 4 7, 5 7, 6 7, 7 8, 0 8, 1 8, 2 8, 3 8, 4 8, 5 8, 6 8, 7 Ts A A A A A A A A A A A A A A A A A A A A A A A A Ae T T T T T T T T T T T T T T T T T T T T T T T T CDDAddr DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA L C C C C C C C C C C C C C C C C C C C C C C C C L L L L L L L L L L L L L L L L L L L L L L L L nt CDme Lg e S 1 M O C Axs 3, 0 3, 1 3, 2 3, 3 3, 4 3, 5 3, 6 3, 7 4, 0 4, 1 4, 2 4, 3 4, 4 4, 5 4, 6 4, 7 5, 0 5, 1 5, 2 5, 3 5, 4 5, 5 5, 6 5, 7 Ts A A A A A A A A A A A A A A A A A A A A A A A A Ae T T T T T T T T T T T T T T T T T T T T T T T T CDDAddr DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA L C C C C C C C C C C C C C C C C C C C C C C C C L L L L L L L L L L L L L L L L L L L L L L L L nt CDme Lg e S 0 M O C Axs 0, 0 0, 1 0, 2 0, 3 0, 4 0, 5 0, 6 0, 7 1, 0 1, 1 1, 2 1, 3 1, 4 1, 5 1, 6 1, 7 2, 0 2, 1 2, 2 2, 3 2, 4 2, 5 2, 6 2, 7 Ts A A A A A A A A A A A A A A A A A A A A A A A A Ae T T T T T T T T T T T T T T T T T T T T T T T T CDDAddr DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA DDA L C C C C C C C C C C C C C C C C C C C C C C C C L L L L L L L L L L L L L L L L L L L L L L L L n o CDcti 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Ln G G G G G G G G G G G G G G G G G G G G G G G G u E E E E E E E E E E E E E E E E E E E E E E E E F S S S S S S S S S S S S S S S S S S S S S S S S Preliminary © 2005 Microchip Technology Inc. DS41265A-page 111

PIC16F946 FIGURE 9-5: LCD SEGMENT MAPPING WORKSHEET (PART 2 OF 2) ateons AlternFuncti PORT RE4 RE5 RE6 RE7 RF4 RF5 RF6 RF7 RF0 RF1 RF2 RF3 RG0 RG1 RG2 RG3 RG4 RG5 n o. pi n N 40- 37 42 43 44 45 46 47 48 11 12 13 14 3 4 5 6 7 8 Pi 8/ 2 nt CDme Lg e S 3 M CO DATAxdress ATA21, 0 ATA21, 1 ATA21, 2 ATA21, 3 ATA21, 4 ATA21, 5 ATA21, 6 ATA21, 7 ATA22, 0 ATA22, 1 ATA22, 2 ATA22, 3 ATA22, 4 ATA22, 5 ATA22, 6 ATA22, 7 ATA23, 0 ATA23, 1 Dd D D D D D D D D D D D D D D D D D D CA D D D D D D D D D D D D D D D D D D L C C C C C C C C C C C C C C C C C C L L L L L L L L L L L L L L L L L L nt CDme Lg e S 2 M CO DATAxdress ATA18, 0 ATA18, 1 ATA18, 2 ATA18, 3 ATA18, 4 ATA18, 5 ATA18, 6 ATA18, 7 ATA19, 0 ATA19, 1 ATA19, 2 ATA19, 3 ATA19, 4 ATA19, 5 ATA19, 6 ATA19, 7 ATA20, 0 ATA20, 1 Dd D D D D D D D D D D D D D D D D D D CA D D D D D D D D D D D D D D D D D D L C C C C C C C C C C C C C C C C C C L L L L L L L L L L L L L L L L L L nt CDme Lg e S 1 M CO DATAxdress ATA15, 0 ATA15, 1 ATA15, 2 ATA15, 3 ATA15, 4 ATA15, 5 ATA15, 6 ATA15, 7 ATA16, 0 ATA16, 1 ATA16, 2 ATA16, 3 ATA16, 4 ATA16, 5 ATA16, 6 ATA16, 7 ATA17, 0 ATA17, 1 Dd D D D D D D D D D D D D D D D D D D CA D D D D D D D D D D D D D D D D D D L C C C C C C C C C C C C C C C C C C L L L L L L L L L L L L L L L L L L nt CDme Lg e S 0 M CO DATAxdress ATA12, 0 ATA12, 1 ATA12, 2 ATA12, 3 ATA12, 4 ATA12, 5 ATA12, 6 ATA12, 7 ATA13, 0 ATA13, 1 ATA13, 2 ATA13, 3 ATA13, 4 ATA13, 5 ATA13, 6 ATA13, 7 ATA14, 0 ATA14, 1 Dd D D D D D D D D D D D D D D D D D D CA D D D D D D D D D D D D D D D D D D L C C C C C C C C C C C C C C C C C C L L L L L L L L L L L L L L L L L L n o CDcti 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Ln G G G G G G G G G G G G G G G G G G u E E E E E E E E E E E E E E E E E E F S S S S S S S S S S S S S S S S S S Preliminary DS41265A-page 112 © 2005 Microchip Technology Inc.

PIC16F946 9.7 LCD Waveform Generation The LCDs can be driven by two types of waveform: Type-A and Type-B. In Type-A waveform, the phase LCD waveforms are generated so that the net AC changes within each common type, whereas in Type-B voltage across the dark pixel should be maximized and waveform, the phase changes on each frame the net AC voltage across the clear pixel should be boundary. Thus, Type-A waveform maintains ‘0’VDC minimized. The net DC voltage across any pixel should over a single frame, whereas Type-B waveform takes be zero. two frames. The COM signal represents the time slice for each Note1: If Sleep has to be executed with LCD common, while the SEG contains the pixel data. Sleep enabled (LCDCON<SLPEN> is The pixel signal (COM-SEG) will have no DC compo- ‘1’), then care must be taken to execute nent and it can take only one of the two rms values. The Sleep only when VDC on all the pixels is higher rms value will create a dark pixel and a lower ‘0’. rms value will create a clear pixel. 2: When the LCD clock source is FOSC/8192, As the number of commons increases, the delta if Sleep is executed, irrespective of the between the two rms values decreases. The delta LCDCON<SLPEN> setting, the LCD goes represents the maximum contrast that the display can into Sleep. Thus, take care to see that VDC have. on all pixels is ‘0’ when Sleep is executed. Figure9-6 through Figure9-16 provide waveforms for static, half-multiplex, one-third-multiplex and quarter-multiplex drives for Type-A and Type-B waveforms. FIGURE 9-6: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE V 1 COM0 V COM0 0 V 1 SEG0 V 0 V 1 SEG1 V 0 V 1 COM0-SEG0 V0 -V 1 COM0-SEG1 V 0 1 Frame 76543 2 10 GGGGG G GG EEEEE E EE SSSSS S SS Preliminary © 2005 Microchip Technology Inc. DS41265A-page 113

PIC16F946 FIGURE 9-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V 2 COM0 V 1 V 0 COM1 V 2 COM1 V COM0 1 V 0 V 2 SEG0 V1 V 0 V 2 SEG1 V1 V 0 3 2 1 0 V2 G G G G E E E E V S S S S 1 COM0-SEG0 V0 -V 1 -V 2 V 2 V 1 COM0-SEG1 V0 -V 1 -V 2 1 Frame Preliminary DS41265A-page 114 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 9-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V 2 COM0 V 1 COM1 V 0 COM0 V 2 COM1 V 1 V 0 V 2 SEG0 V 1 V 0 V 2 3 2 1 0 SEG1 G G G G V E E E E 1 S S S S V 0 V 2 V 1 COM0-SEG0 V0 -V 1 -V 2 V 2 V 1 COM0-SEG1 V0 -V 1 -V 2 2 Frames Preliminary © 2005 Microchip Technology Inc. DS41265A-page 115

PIC16F946 FIGURE 9-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V 3 V 2 COM0 V 1 COM1 V 0 V 3 COM0 V 2 COM1 V 1 V 0 V 3 V 2 SEG0 V 1 V 0 V 3 V 2 3 2 1 0 SEG1 G G G G V E E E E 1 S S S S V 0 V 3 V 2 V 1 COM0-SEG0 V0 -V 1 -V 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V0 -V 1 -V 2 1 Frame -V 3 Preliminary DS41265A-page 116 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 9-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V 3 V 2 COM0 V 1 COM1 V 0 V 3 COM0 V 2 COM1 V 1 V 0 V 3 V 2 SEG0 V 1 V 0 V 3 V 2 3 2 1 0 SEG1 G G G G V E E E E 1 S S S S V 0 V 3 V 2 V 1 COM0-SEG0 V0 -V 1 -V 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V0 -V 1 -V 2 2 Frames -V 3 Preliminary © 2005 Microchip Technology Inc. DS41265A-page 117

PIC16F946 FIGURE 9-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V 2 COM0 V 1 V 0 V 2 COM2 COM1 V 1 V 0 COM1 V 2 COM0 COM2 V 1 V 0 V 2 SEG0 V SEG2 1 V 0 V 2 SEG1 V 1 2 1 0 V G G G 0 E E E S S S V 2 V 1 COM0-SEG0 V 0 -V 1 -V 2 V 2 V 1 COM0-SEG1 V 0 -V 1 -V 2 1 Frame Preliminary DS41265A-page 118 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 9-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V 2 COM0 V 1 V 0 COM2 V 2 COM1 V 1 COM1 V COM0 0 V 2 COM2 V 1 V 0 V 2 SEG0 V 1 V 2 1 0 0 G G G E E E S S S V 2 SEG1 V 1 V 0 V 2 V 1 COM0-SEG0 V 0 -V 1 -V 2 V 2 V 1 COM0-SEG1 V 0 -V 1 -V 2 2 Frames Preliminary © 2005 Microchip Technology Inc. DS41265A-page 119

PIC16F946 FIGURE 9-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V 3 V 2 COM0 V 1 V 0 COM2 V3 V 2 COM1 V 1 COM1 V COM0 0 V 3 V 2 COM2 V 1 V 0 V 3 V 2 SEG0 V SEG2 1 V 2 1 0 0 G G G E E E V S S S 3 V 2 SEG1 V 1 V 0 V 3 V 2 V 1 COM0-SEG0 V 0 -V 1 -V 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V 0 -V 1 -V 2 -V 3 1 Frame Preliminary DS41265A-page 120 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 9-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V 3 V 2 COM0 V 1 V 0 COM2 V3 V 2 COM1 V 1 COM1 V COM0 0 V 3 V 2 COM2 V 1 V 0 V 3 V 2 SEG0 V 1 V 2 1 0 0 G G G E E E V S S S 3 V 2 SEG1 V 1 V 0 V 3 V 2 V 1 COM0-SEG0 V 0 -V 1 -V 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V 0 -V 1 -V 2 -V 3 2 Frames Preliminary © 2005 Microchip Technology Inc. DS41265A-page 121

PIC16F946 FIGURE 9-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 V 3 COM2 COM0 V2 V 1 V 0 V 3 COM1 V COM1 2 V 1 COM0 V 0 V 3 V COM2 2 V 1 V 0 V 3 V COM3 2 V 1 V 0 V 3 V SEG0 2 V 1 V 0 1 0 G G V3 E E V S S SEG1 V2 1 V 0 V 3 V 2 V 1 COM0-SEG0 V0 -V 1 -V 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V0 -V 1 -V 2 -V 3 1 Frame Preliminary DS41265A-page 122 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 9-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 V 3 COM2 COM0 V2 V 1 V 0 V 3 COM1 V COM1 2 V 1 COM0 V 0 V 3 V COM2 2 V 1 V 0 V 3 V COM3 2 V 1 V 0 V 3 V SEG0 2 V 1 V 0 1 0 G G V3 E E V S S SEG1 V2 1 V 0 V 3 V 2 V 1 COM0-SEG0 V0 -V 1 -V 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V0 -V 1 -V 2 -V 3 2 Frames Preliminary © 2005 Microchip Technology Inc. DS41265A-page 123

PIC16F946 9.8 LCD Interrupts When the LCD driver is running with Type-B waveforms and the LMUX<1:0> bits are not equal to ‘00’, there are The LCD timing generation provides an interrupt that some additional issues that must be addressed. Since defines the LCD frame timing. This interrupt can be the DC voltage on the pixel takes two frames to maintain used to coordinate the writing of the pixel data with the zero volts, the pixel data must not change between start of a new frame. Writing pixel data at the frame subsequent frames. If the pixel data were allowed to boundary allows a visually crisp transition of the image. change, the waveform for the odd frames would not This interrupt can also be used to synchronize external necessarily be the complement of the waveform events to the LCD. generated in the even frames and a DC component A new frame is defined to begin at the leading edge of would be introduced into the panel. Therefore, when the COM0 common signal. The interrupt will be set using Type-B waveforms, the user must synchronize the immediately after the LCD controller completes LCD pixel updates to occur within a subframe after the accessing all pixel data required for a frame. This will frame interrupt. occur at a fixed interval before the frame boundary To correctly sequence writing while in Type-B, the (TFINT), as shown in Figure9-17. The LCD controller interrupt will only occur on complete phase intervals. If the will begin to access data for the next frame within the user attempts to write when the write is disabled, the interval from the interrupt to when the controller begins WERR (LCDCON<5>) bit is set. to access data after the interrupt (TFWR). New data must be written within TFWR, as this is when the LCD Note: The interrupt is not generated when the controller will begin to access the data for the next Type-A waveform is selected and when the frame. Type-B with no multiplex (static) is selected. FIGURE 9-17: WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE (EXAMPLE – TYPE-B, NON-STATIC) LCD Controller Accesses Interrupt Next Frame Data Occurs V 3 V 2 COM0 V 1 V 0 V 3 V 2 COM1 V 1 V 0 V 3 V 2 COM2 V 1 V 0 COM3 V3 V 2 V 1 V 0 2 Frames TFINT Frame Frame TFWR Frame Boundary Boundary Boundary TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2 TFINT = (TFWR/2 – (2 TCY + 40 ns)) →minimum =1.5(TFRAME/4) – (2 TCY + 40 ns) (TFWR/2 – (1 TCY + 40 ns)) →maximum=1.5(TFRAME/4) – (1 TCY + 40 ns) Preliminary DS41265A-page 124 © 2005 Microchip Technology Inc.

PIC16F946 9.9 Operation During Sleep The LCD module can operate during Sleep. The selec- tion is controlled by bit SLPEN (LCDCON<6>). Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will cease all functions and go into a very low-current Consumption mode. The module will stop operation immediately and drive the minimum LCD voltage on both segment and common lines. Figure9-18 shows this operation. To ensure that no DC component is introduced on the panel, the SLEEP instruction should be executed imme- diately after a LCD frame boundary. The LCD interrupt can be used to determine the frame boundary. See Section9.8 “LCD Interrupts” for the formulas to calculate the delay. If a SLEEP instruction is executed and SLPEN = 0, the module will continue to display the current contents of the LCDDATA registers. To allow the module to continue operation while in Sleep, the clock source must be either the LFINTOSC or T1OSC external oscillator. While in Sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shut down of the core and other peripheral functions. Table9-4 shows the status of the LCD module during a Sleep while using each of the three available clock sources: TABLE 9-4: LCD MODULE STATUS DURING SLEEP Operation Clock Source SLPEN During Sleep? 0 Yes T1OSC 1 No 0 Yes LFINTOSC 1 No 0 No FOSC/4 1 No Note: The LFINTOSC or external T1OSC oscillator must be used to operate the LCD module during Sleep. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 125

PIC16F946 FIGURE 9-18: SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS<1:0> = 00 V 3 V 2 V 1 COM0 V 0 V 3 V 2 V 1 COM1 V0 V 3 V 2 V 1 COM2 V0 V 3 V 2 V 1 SEG0 V 0 2 Frames SLEEP Instruction Execution Wake-up Preliminary DS41265A-page 126 © 2005 Microchip Technology Inc.

PIC16F946 9.10 Configuring the LCD Module The following is the sequence of steps to configure the LCD module. 1. Select the frame clock prescale using bits LP<3:0> (LCDPS<3:0>). 2. Configure the appropriate pins to function as segment drivers using the LCDSEn registers. 3. Configure the LCD module for the following using the LCDCON register: -Multiplex and Bias mode, bits LMUX<1:0> -Timing source, bits CS<1:0> -Sleep mode, bit SLPEN 4. Write initial values to pixel data registers, LCDDATA0 through LCDDATA11. 5. Clear LCD Interrupt Flag, LCDIF (PIR2<4>) and if desired, enable the interrupt by setting bit LCDIE (PIE2<4>). 6. Enable bias voltage pins (VLCD<3:1>) by setting VLCDEN (LCDCON<4>). 7. Enable the LCD module by setting bit LCDEN (LCDCON<7>). Preliminary © 2005 Microchip Technology Inc. DS41265A-page 127

PIC16F946 TABLE 9-5: REGISTERS ASSOCIATED WITH LCD OPERATION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu 0Bh/8Bh/ INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh/18Bh 0Dh PIR2 OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF 0000 -0-0 0000 -0-0 8Dh PIE2 OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE 0000 -0-0 0000 -0-0 107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 108h LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 0000 0000 110h LCDDATA0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 111h LCDDATA1 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 112h LCDDATA2 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 113h LCDDATA3 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 114h LCDDATA4 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 115h LCDDATA5 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 116h LCDDATA6 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 117h LCDDATA7 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 118h LCDDATA8 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 119h LCDDATA9 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 11Ah LCDDATA10 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 11Bh LCDDATA11 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 11Ch LCDSE0(2) SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu 11Dh LCDSE1(2) SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu 11Eh LCDSE2(2) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu 190h LCDDATA12 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 191h LCDDATA13 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SE33 SEG32 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 192h LCDDATA14 — — — — — — SEG41 SEG40 ---- --xx ---- --uu COM0 COM0 193h LCDDATA15 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 194h LCDDATA16 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 195h LCDDATA17 — — — — — — SEG41 SEG40 ---- --xx ---- --uu COM1 COM1 196h LCDDATA18 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 197h LCDDATA19 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 198h LCDDATA20 — — — — — — SEG41 SEG40 ---- --xx ---- --uu COM2 COM2 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the LCD module. Note 1: These pins may be configured as port pins, depending on the oscillator mode selected. 2: This register is only initialized by a POR or BOR and is unchanged by other Resets. Preliminary DS41265A-page 128 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 9-5: REGISTERS ASSOCIATED WITH LCD OPERATION (CONTINUED) Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 199h LCDDATA21 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 19Ah LCDDATA22 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 19Bh LCDDATA23 — — — — — — SEG41 SEG40 ---- --xx ---- --uu COM3 COM3 19Ch LCDSE3(2) SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000 uuuu uuuu 19Dh LCDSE4(2) SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 0000 0000 uuuu uuuu 19Eh LCDSE5(2) — — — — — — SE41 SE40 ---- --00 ---- --uu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the LCD module. Note 1: These pins may be configured as port pins, depending on the oscillator mode selected. 2: This register is only initialized by a POR or BOR and is unchanged by other Resets. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 129

PIC16F946 NOTES: Preliminary DS41265A-page 130 © 2005 Microchip Technology Inc.

PIC16F946 10.0 PROGRAMMABLE 10.1.1 PLVD CALIBRATION LOW-VOLTAGE DETECT The PIC16F91X stores the PLVD calibration values in (PLVD) MODULE fuses located in the Calibration Word 2 (2009h). The Calibration Word 2 is not erased when using the spec- The Programmable Low-Voltage Detect module is an ified bulk erase sequence in the “PIC16F91X Memory interrupt driven supply level detection. The voltage Programming Specification” (DS41244) and thus, does detection monitors the internal power supply. not require reprogramming. 10.1 Voltage Trip Points The PIC16F946 device supports eight internal PLVD trip points. See Register10-1 for available PLVD trip point voltages. REGISTER 10-1: LVDCON – LOW-VOLTAGE DETECT CONTROL REGISTER (ADDRESS: 109h) U-0 U-0 R-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — — IRVST LVDEN — LVDL2 LVDL1 LVDL0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Status Flag bit(1) 1 = Indicates that the PLVD is stable and PLVD interrupt is reliable 0 = Indicates that the PLVD is not stable and PLVD interrupt should not be enabled bit 4 LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables PLVD, powers up PLVD circuit and supporting reference circuitry 0 = Disables PLVD, powers down PLVD and supporting circuitry bit 3 Unimplemented: Read as ‘0’ bit 2-0 LVDL<2:0>: Low-Voltage Detection Limit bits (nominal values) 111 = 4.5V 110 = 4.2V 101 = 4.0V 100 = 2.3V (default) 011 = 2.2V 010 = 2.1V 001 = 2.0V 000 = 1.9V(2) Note1: The IRVST bit is usable only when the HFINTOSC is running. When using an external crystal to run the microcontroller, the PLVD settling time is expected to be <50 μs when VDD = 5V and <25 μs when VDD = 3V. Appropriate software delays should be used after enabling the PLVD module to ensure proper status readings of the module. 2: Not tested and below minimum VDD. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 131

PIC16F946 TABLE 10-1: REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh/8Bh/ INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh/18Bh 0Dh PIR2 OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF 0000 -0-0 0000 -0-0 8Dh PIE2 OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE 0000 -0-0 0000 -0-0 109h LVDCON — — IRVST LVDEN — LVDL2 LVDL1 LVDL0 --00 -100 --00 -100 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the PLVD module. Preliminary DS41265A-page 132 © 2005 Microchip Technology Inc.

PIC16F946 11.0 ADDRESSABLE UNIVERSAL The USART can be configured in the following modes: SYNCHRONOUS (cid:129) Asynchronous (full-duplex) ASYNCHRONOUS RECEIVER (cid:129) Synchronous – Master (half-duplex) TRANSMITTER (USART) (cid:129) Synchronous – Slave (half-duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be The Universal Synchronous Asynchronous Receiver set in order to configure pins RC6/TX/CK/SCK/SCL/SEG9 Transmitter (USART) module is one of the two serial and RC7/RX/DT/SDI/SDA/SEG8 as the Universal I/O modules. (USART is also known as a Serial Synchronous Asynchronous Receiver Transmitter. Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that The USART module also has a multi-processor can communicate with peripheral devices, such as communication capability using 9-bit address detection. CRT terminals and personal computers, or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. REGISTER 11-1: TXSTA – TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as ‘0’ bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data, can be Parity bit Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 133

PIC16F946 REGISTER 11-2: RCSTA – RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT/SDI/SDA/SEG8 and RC6/TX/CK/SCK/SCL/SEG9 pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 134 © 2005 Microchip Technology Inc.

PIC16F946 11.1 USART Baud Rate Generator It may be advantageous to use the high baud rate (BRG) (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16 (X + 1)) equation can reduce the The BRG supports both the Asynchronous and baud rate error in some cases. Synchronous modes of the USART. It is a dedicated Writing a new value to the SPBRG register causes the 8-bit baud rate generator. The SPBRG register controls BRG timer to be reset (or cleared). This ensures the the period of a free running 8-bit timer. In BRG does not wait for a timer overflow before Asynchronous mode, bit BRGH (TXSTA<2>) also outputting the new baud rate. controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table11-1 shows the formula for 11.1.1 SAMPLING computation of the baud rate for different USART modes which only apply in Master mode (internal The data on the RC7/RX/DT/SDI/SDA/SEG8 pin is sampled three times by a majority detect circuit to clock). determine if a high or a low level is present at the RX Given the desired baud rate and FOSC, the nearest pin. integer value for the SPBRG register can be calculated using the formula in Table11-1. From this, the error in baud rate can be determined. TABLE 11-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64 (X + 1)) Baud Rate = FOSC/(16 (X + 1)) 1 (Synchronous) Baud Rate = FOSC/(4 (X + 1)) N/A Legend: X = value in SPBRG (0 to 255) TABLE 11-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 135

PIC16F946 TABLE 11-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz BAUD RATE % SPBRG % SPBRG % SPBRG (K) KBAUD ERROR value KBAUD ERROR value KBAUD ERROR value (decimal) (decimal) (decimal) 0.3 — — — — — — — — — 1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129 2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64 9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15 19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7 28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4 33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4 57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2 HIGH 1.221 — 255 0.977 — 255 0.610 — 255 LOW 312.500 — 0 250.000 — 0 156.250 — 0 FOSC = 4 MHz FOSC = 3.6864 MHz BAUD RATE % SPBRG % SPBRG (K) ERROR value ERROR value KBAUD (decimal) KBAUD (decimal) 0.3 0.300 0 207 0.3 0 191 1.2 1.202 0.17 51 1.2 0 47 2.4 2.404 0.17 25 2.4 0 23 9.6 8.929 6.99 6 9.6 0 5 19.2 20.833 8.51 2 19.2 0 2 28.8 31.250 8.51 1 28.8 0 1 33.6 — — — — — — 57.6 62.500 8.51 0 57.6 0 0 HIGH 0.244 — 255 0.225 — 255 LOW 62.500 — 0 57.6 — 0 TABLE 11-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz BAUD RATE % SPBRG % SPBRG % SPBRG (K) KBAUD ERROR value KBAUD ERROR value KBAUD ERROR value (decimal) (decimal) (decimal) 0.3 — — — — — — — — — 1.2 — — — — — — — — — 2.4 — — — — — — 2.441 1.71 255 9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64 19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31 28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21 33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18 57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10 HIGH 4.883 — 255 3.906 — 255 2.441 - 255 LOW 1250.000 — 0 1000.000 — 0 625.000 - 0 FOSC = 4 MHz FOSC = 3.6864 MHz BAUD RATE % SPBRG % SPBRG (K) ERROR value ERROR value KBAUD (decimal) KBAUD (decimal) 0.3 — — — — — — 1.2 1.202 0.17 207 1.2 0 191 2.4 2.404 0.17 103 2.4 0 95 9.6 9.615 0.16 25 9.6 0 23 19.2 19.231 0.16 12 19.2 0 11 28.8 27.798 3.55 8 28.8 0 7 33.6 35.714 6.29 6 32.9 2.04 6 57.6 62.500 8.51 3 57.6 0 3 HIGH 0.977 — 255 0.9 — 255 LOW 250.000 — 0 230.4 — 0 Preliminary DS41265A-page 136 © 2005 Microchip Technology Inc.

PIC16F946 11.2 USART Asynchronous Mode Transmission is enabled by setting enable bit, TXEN (TXSTA<5>). The actual transmission will not occur until In this mode, the USART uses standard the TXREG register has been loaded with data and the Non-Return-to-Zero (NRZ) format (one Start bit, eight Baud Rate Generator (BRG) has produced a shift clock or nine data bits and one Stop bit). The most common (Figure11-2). The transmission can also be started by data format is 8 bits. An on-chip, dedicated, 8-bit Baud first loading the TXREG register and then setting enable Rate Generator (BRG) can be used to derive standard bit TXEN. Normally, when transmission is first started, the baud rate frequencies from the oscillator. The USART TSR register is empty. At that point, transfer to the transmits and receives the LSb first. The transmitter TXREG register will result in an immediate transfer to and receiver are functionally independent but use the TSR, resulting in an empty TXREG. A back-to-back same data format and baud rate. The baud rate transfer is thus possible (Figure11-3). Clearing enable bit generator produces a clock, either x16 or x64 of the bit TXEN during a transmission will cause the transmission shift rate, depending on bit BRGH (TXSTA<2>). Parity to be aborted and will reset the transmitter. As a result, the is not supported by the hardware, but can be RC6/TX/CK/SCK/SCL/SEG9 pin will revert to implemented in software (and stored as the ninth data high-impedance. bit). Asynchronous mode is stopped during Sleep. In order to select 9-bit transmission, transmit bit TX9 Asynchronous mode is selected by clearing bit SYNC (TXSTA<6>) should be set and the ninth bit should be (TXSTA<4>). written to TX9D (TXSTA<0>). The ninth bit must be The USART Asynchronous module consists of the written before writing the 8-bit data to the TXREG reg- following important elements: ister. This is because a data write to the TXREG regis- ter can result in an immediate transfer of the data to the (cid:129) Baud Rate Generator TSR register (if the TSR is empty). In such a case, an (cid:129) Sampling Circuit incorrect ninth data bit may be loaded in the TSR (cid:129) Asynchronous Transmitter register. (cid:129) Asynchronous Receiver When setting up an Asynchronous Transmission, follow these steps: 11.2.1 USART ASYNCHRONOUS TRANSMITTER 1. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, The USART transmitter block diagram is shown in set bit BRGH (Section11.1 “USART Baud Figure11-1. The heart of the transmitter is the Transmit Rate Generator (BRG)”). (Serial) Shift Register (TSR). The shift register obtains 2. Enable the asynchronous serial port by clearing its data from the Read/Write Transmit Buffer, TXREG. bit SYNC and setting bit SPEN. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has 3. If interrupts are desired, then set enable bit TXIE. been transmitted from the previous load. As soon as 4. If 9-bit transmission is desired, then set transmit the Stop bit is transmitted, the TSR is loaded with new bit TX9. data from the TXREG register (if available). Once the 5. Enable the transmission by setting bit TXEN, TXREG register transfers the data to the TSR register which will also set bit TXIF. (occurs in one TCY), the TXREG register is empty and 6. If 9-bit transmission is selected, the ninth bit flag bit, TXIF (PIR1<4>), is set. This interrupt can be should be loaded in bit TX9D. enabled/disabled by setting/clearing enable bit, TXIE 7. Load data to the TXREG register (starts (PIE1<4>). Flag bit TXIF will be set regardless of the transmission). state of enable bit TXIE and cannot be cleared in soft- 8. If using interrupts, ensure that GIE and PEIE ware. It will reset only when new data is loaded into the (bits 7 and 6) of the INTCON register are set. TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read-only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. Note1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. TXIF is cleared by loading TXREG. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 137

PIC16F946 FIGURE 11-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR Register RC6/TX/CK/SCK/ Interrupt SCL/SEG9 pin TXEN Baud Rate CLK TRMT SPEN SPBRG Baud Rate Generator TX9 TX9D FIGURE 11-2: ASYNCHRONOUS MASTER TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK/ SCK/SCL/SEG9 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 11-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) RC6/TX/CK/ SCK/SCL/SEG9 Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit Word 1 Word 2 (Interrupt Reg. Flag) T(RTReragMn. TsE mmbiitpt tSyh Fifltag) TWraonrds m1it Shift Reg. WTraonrds m2it Shift Reg. Note: This timing diagram shows two consecutive transmissions. Preliminary DS41265A-page 138 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 11-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh,18Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 139

PIC16F946 11.2.2 USART ASYNCHRONOUS When setting up an Asynchronous Reception, follow RECEIVER these steps: The receiver block diagram is shown in Figure11-4. 1. Initialize the SPBRG register for the appropriate The data is received on the baud rate. If a high-speed baud rate is desired, RC7/RX/DT/SDI/SDA/SEG8 pin and drives the data set bit BRGH (Section11.1 “USART Baud recovery block. The data recovery block is actually a Rate Generator (BRG)”). high-speed shifter, operating at x16 times the baud 2. Enable the asynchronous serial port by clearing rate; whereas the main receive serial shifter operates bit SYNC and setting bit SPEN. at the bit rate or at FOSC. 3. If interrupts are desired, then set enable bit Once Asynchronous mode is selected, reception is RCIE. enabled by setting bit CREN (RCSTA<4>). 4. If 9-bit reception is desired, then set bit RX9. The heart of the receiver is the Receive (Serial) Shift 5. Enable the reception by setting bit CREN. Register (RSR). After sampling the Stop bit, the 6. Flag bit RCIF will be set when reception is com- received data in the RSR is transferred to the RCREG plete and an interrupt will be generated if enable register (if it is empty). If the transfer is complete, flag bit RCIE is set. bit, RCIF (PIR1<5>), is set. The actual interrupt can be 7. Read the RCSTA register to get the ninth bit (if enabled/disabled by setting/clearing enable bit, RCIE enabled) and determine if any error occurred (PIE1<5>). Flag bit RCIF is a read-only bit which is during reception. cleared by the hardware. It is cleared when the RCREG 8. Read the 8-bit received data by reading the register has been read and is empty. The RCREG is a RCREG register. double-buffered register (i.e., it is a two-deep FIFO). It 9. If any error occurred, clear the error by clearing is possible for two bytes of data to be received and enable bit CREN. transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of 10. If using interrupts, ensure that GIE and PEIE the Stop bit of the third byte, if the RCREG register is (bits 7 and 6) of the INTCON register are set. still full, the Overrun Error bit, OERR (RCSTA<1>), will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in soft- ware. This is done by resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to the RCREG register are inhib- ited and no further data will be received. It is, therefore, essential to clear error bit OERR if it is set. Framing error bit, FERR (RCSTA<2>), is set if a Stop bit is detected as clear. Bit FERR and the 9th receive bit are buffered the same way as the receive data. Reading the RCREG will load bits RX9D and FERR with new values, therefore, it is essential for the user to read the RCSTA register before reading the RCREG register in order not to lose the old FERR and RX9D information. Preliminary DS41265A-page 140 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 11-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN FOSC SPBRG ÷64 MSb RSR Register LSb or Baud Rate Generator ÷16 Stop (8) 7 • • • 1 0 Start RC7/RX/DT/ SDI/SDA/SEG8 Pin Buffer Data RX9 and Control Recovery SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF Data Bus RCIE FIGURE 11-5: ASYNCHRONOUS RECEPTION RX (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word, causing the OERR (Overrun Error) bit to be set. TABLE 11-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh,18Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 141

PIC16F946 11.2.3 SETTING UP 9-BIT MODE WITH (cid:129) Flag bit RCIF will be set when reception is ADDRESS DETECT complete, and an interrupt will be generated if enable bit RCIE was set. When setting up an Asynchronous Reception with (cid:129) Read the RCSTA register to get the ninth bit and address detect enabled: determine if any error occurred during reception. (cid:129) Initialize the SPBRG register for the appropriate (cid:129) Read the 8-bit received data by reading the baud rate. If a high-speed baud rate is desired, RCREG register to determine if the device is set bit BRGH. being addressed. (cid:129) Enable the asynchronous serial port by clearing (cid:129) If any error occurred, clear the error by clearing bit SYNC and setting bit SPEN. enable bit CREN. (cid:129) If interrupts are desired, then set enable bit RCIE. (cid:129) If the device has been addressed, clear the (cid:129) Set bit RX9 to enable 9-bit reception. ADDEN bit to allow data bytes and address bytes (cid:129) Set ADDEN to enable address detect. to be read into the receive buffer and interrupt the (cid:129) Enable the reception by setting enable bit CREN. CPU. FIGURE 11-6: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN FOSC SPBRG ÷ 64 MSb RSR Register LSb or Baud Rate Generator ÷ 16 Stop (8) 7 • • • 1 0 Start RC7/RX/DT SDI/SDA/SEG8 Pin Buffer Data RX9 and Control Recovery 8 SPEN RX9 Enable ADDEN Load of Receive RX9 Buffer ADDEN RSR<8> 8 RX9D RCREG Register FIFO 8 Interrupt RCIF Data Bus RCIE Preliminary DS41265A-page 142 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 11-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT RC7/RX/DT/ Start Start SDI/SDA/SEG8 bit bit 0 bit 1 bit 8 Stop bit bit 0 bit 8 Stop bit bit Load RSR bit 8 = 0, Data Byte bit 8 = 1, Address Byte Word 1 RCREG Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADDEN = 1. FIGURE 11-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST RC7/RX/DT/ Start Start SDI/SDA/SEG8 bit bit 0 bit 1 bit 8 Stop bit bit 0 bit 8 Stop bit bit Load RSR bit 8 = 1, Address Byte bit 8 = 0, Data Byte Word 1 RCREG Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADDEN was not updated and still = 0. TABLE 11-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh,18Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 143

PIC16F946 11.3 USART Synchronous Clearing enable bit TXEN during a transmission will Master Mode cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to In Synchronous Master mode, the data is transmitted in high-impedance. If either bit CREN or bit SREN is set a half-duplex manner (i.e., transmission and reception during a transmission, the transmission is aborted and do not occur at the same time). When transmitting data, the DT pin reverts to a high-impedance state (for a the reception is inhibited and vice versa. Synchronous reception). The CK pin will remain an output if bit CSRC mode is entered by setting bit, SYNC (TXSTA<4>). In is set (internal clock). The transmitter logic, however, is addition, enable bit, SPEN (RCSTA<7>), is set in order not reset, although it is disconnected from the pins. In to configure the RC6/TX/CK/SCK/SCL/SEG9 and order to reset the transmitter, the user has to clear bit RC7/RX/DT/SDI/SDA/SEG8 I/O pins to CK (clock) and TXEN. If bit SREN is set (to interrupt an on-going trans- DT (data) lines, respectively. The Master mode indi- mission and receive a single word), then after the sin- cates that the processor transmits the master clock on gle word is received, bit SREN will be cleared and the the CK line. The Master mode is entered by setting bit, serial port will revert back to transmitting, since bit CSRC (TXSTA<7>). TXEN is still set. The DT line will immediately switch from High-Impedance Receive mode to transmit and 11.3.1 USART SYNCHRONOUS MASTER start driving. To avoid this, bit TXEN should be cleared. TRANSMISSION In order to select 9-bit transmission, the TX9 The USART transmitter block diagram is shown in (TXSTA<6>) bit should be set and the ninth bit should Figure11-6. The heart of the transmitter is the Transmit be written to bit TX9D (TXSTA<0>). The ninth bit must (Serial) Shift Register (TSR). The shift register obtains be written before writing the 8-bit data to the TXREG its data from the Read/Write Transmit Buffer register, register. This is because a data write to the TXREG can TXREG. The TXREG register is loaded with data in result in an immediate transfer of the data to the TSR software. The TSR register is not loaded until the last register (if the TSR is empty). If the TSR was empty and bit has been transmitted from the previous load. As the TXREG was written before writing the “new” TX9D, soon as the last bit is transmitted, the TSR is loaded the “present” value of bit TX9D is loaded. with new data from the TXREG (if available). Once the Steps to follow when setting up a Synchronous Master TXREG register transfers the data to the TSR register Transmission: (occurs in one TCYCLE), the TXREG is empty and inter- rupt bit, TXIF (PIR1<4>), is set. The interrupt can be 1. Initialize the SPBRG register for the appropriate enabled/disabled by setting/clearing enable bit TXIE baud rate (Section11.1 “USART Baud Rate (PIE1<4>). Flag bit TXIF will be set regardless of the Generator (BRG)”). state of enable bit TXIE and cannot be cleared in soft- 2. Enable the synchronous master serial port by ware. It will reset only when new data is loaded into the setting bits SYNC, SPEN and CSRC. TXREG register. While flag bit TXIF indicates the status 3. If interrupts are desired, set enable bit TXIE. of the TXREG register, another bit, TRMT (TXSTA<1>), 4. If 9-bit transmission is desired, set bit TX9. shows the status of the TSR register. TRMT is a 5. Enable the transmission by setting bit TXEN. read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit so the user has to poll 6. If 9-bit transmission is selected, the ninth bit this bit in order to determine if the TSR register is should be loaded in bit TX9D. empty. The TSR is not mapped in data memory so it is 7. Start transmission by loading data to the TXREG not available to the user. register. Transmission is enabled by setting enable bit, TXEN 8. If using interrupts, ensure that GIE and PEIE (TXSTA<5>). The actual transmission will not occur (bits 7 and 6) of the INTCON register are set. until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock (Figure11-9). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure11-10). This is advantageous when slow baud rates are selected, since the BRG is kept in Reset when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally, when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible. Preliminary DS41265A-page 144 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 11-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh,18Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. FIGURE 11-9: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT/ SDI/SDA/SEG8 bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX/CK/ SCK/SCL/SEG9 Write to TXREG reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words. FIGURE 11-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT/SDI/SDA/SEG8 bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK/SCK/SCL/SEG9 Write to TXREG Reg TXIF bit TRMT bit TXEN bit Preliminary © 2005 Microchip Technology Inc. DS41265A-page 145

PIC16F946 11.3.2 USART SYNCHRONOUS MASTER When setting up a Synchronous Master Reception: RECEPTION 1. Initialize the SPBRG register for the appropriate Once Synchronous mode is selected, reception is baud rate (Section11.1 “USART Baud Rate enabled by setting either enable bit, SREN Generator (BRG)”). (RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data 2. Enable the synchronous master serial port by is sampled on the RC7/RX/DT/SDI/SDA/SEG8 pin on setting bits SYNC, SPEN and CSRC. the falling edge of the clock. If enable bit SREN is set, 3. Ensure bits CREN and SREN are clear. then only a single word is received. If enable bit CREN 4. If interrupts are desired, then set enable bit is set, the reception is continuous until CREN is RCIE. cleared. If both bits are set, CREN takes precedence. 5. If 9-bit reception is desired, then set bit RX9. After clocking the last bit, the received data in the Receive Shift Register (RSR) is transferred to the 6. If a single reception is required, set bit SREN. RCREG register (if it is empty). When the transfer is For continuous reception, set bit CREN. complete, interrupt flag bit, RCIF (PIR1<5>), is set. The 7. Interrupt flag bit RCIF will be set when reception actual interrupt can be enabled/disabled by set- is complete and an interrupt will be generated if ting/clearing enable bit, RCIE (PIE1<5>). Flag bit RCIF enable bit RCIE was set. is a read-only bit which is reset by the hardware. In this 8. Read the RCSTA register to get the ninth bit (if case, it is reset when the RCREG register has been enabled) and determine if any error occurred read and is empty. The RCREG is a double-buffered during reception. register (i.e., it is a two-deep FIFO). It is possible for two 9. Read the 8-bit received data by reading the bytes of data to be received and transferred to the RCREG register. RCREG FIFO and a third byte to begin shifting into the 10. If any error occurred, clear the error by clearing RSR register. On the clocking of the last bit of the third bit CREN. byte, if the RCREG register is still full, then Overrun 11. If using interrupts, ensure that GIE and PEIE Error bit, OERR (RCSTA<1>), is set. The word in the (bits 7 and 6) of the INTCON register are set. RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited so it is essential to clear bit OERR if it is set. The ninth receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. TABLE 11-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh,18Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Preliminary DS41265A-page 146 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 11-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT/ SDI/SDA/SEG8 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX/CK/ SCK/SCL/SEG9 Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0. 11.4 USART Synchronous Slave Mode When setting up a Synchronous Slave Transmission, follow these steps: Synchronous Slave mode differs from the Master mode 1. Enable the synchronous slave serial port by set- in the fact that the shift clock is supplied externally at ting bits SYNC and SPEN and clearing bit the RC6/TX/CK/SCK/SCL/SEG9 pin (instead of being CSRC. supplied internally in Master mode). This allows the device to transfer or receive data while in Sleep mode. 2. Clear bits CREN and SREN. Slave mode is entered by clearing bit, CSRC 3. If interrupts are desired, then set enable bit (TXSTA<7>). TXIE. 4. If 9-bit transmission is desired, then set bit TX9. 11.4.1 USART SYNCHRONOUS SLAVE 5. Enable the transmission by setting enable bit TRANSMIT TXEN. The operation of the Synchronous Master and Slave 6. If 9-bit transmission is selected, the ninth bit modes is identical, except in the case of the Sleep mode. should be loaded in bit TX9D. If two words are written to the TXREG and then the 7. Start transmission by loading data to the TXREG SLEEP instruction is executed, the following will occur: register. a) The first word will immediately transfer to the 8. If using interrupts, ensure that GIE and PEIE TSR register and transmit. (bits 7 and 6) of the INTCON register are set. b) The second word will remain in TXREG register. c) Flag bit TXIF will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. e) If enable bit TXIE is set, the interrupt will wake the chip from Sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). Preliminary © 2005 Microchip Technology Inc. DS41265A-page 147

PIC16F946 TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh,18Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. 11.4.2 USART SYNCHRONOUS SLAVE When setting up a Synchronous Slave Reception, RECEPTION follow these steps: The operation of the Synchronous Master and Slave 1. Enable the synchronous master serial port by modes is identical, except in the case of the Sleep setting bits SYNC and SPEN and clearing bit mode. Bit SREN is a “don't care” in Slave mode. CSRC. 2. If interrupts are desired, set enable bit RCIE. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during 3. If 9-bit reception is desired, set bit RX9. Sleep. On completely receiving the word, the RSR 4. To enable reception, set enable bit CREN. register will transfer the data to the RCREG register 5. Flag bit RCIF will be set when reception is and if enable bit RCIE bit is set, the interrupt generated complete and an interrupt will be generated if will wake the chip from Sleep. If the global interrupt is enable bit RCIE was set. enabled, the program will branch to the interrupt vector 6. Read the RCSTA register to get the ninth bit (if (0004h). enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register. 8. If any error occurred, clear the error by clearing bit CREN. 9. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. TABLE 11-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh,18Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Preliminary DS41265A-page 148 © 2005 Microchip Technology Inc.

PIC16F946 12.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representation of that signal. The PIC16F946 has up to eight analog inputs, multiplexed into one sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either VDD or a voltage applied by the VREF pin. Figure12-1 shows the block diagram of the A/D on the PIC16F946. FIGURE 12-1: A/D BLOCK DIAGRAM VDD VCFG0 = 0 VREF+ VCFG0 = 1 RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 A/D RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/SEG15 GO/DONE 10 RA5/AN4/C2OUT/SS/SEG5 ADFM RE0/AN5/SEG21 10 RE1/AN6/SEG22 ADON RE2/AN7/SEG23 ADRESH ADRESL VSS CHS<2:0> VCFG1 = 0 VREF- VCFG1 = 1 Preliminary © 2005 Microchip Technology Inc. DS41265A-page 149

PIC16F946 12.1 A/D Configuration and Operation 12.1.4 CONVERSION CLOCK There are three registers available to control the The A/D conversion cycle requires 11 TAD. The source functionality of the A/D module: of the conversion clock is software selectable via the ADCS bits (ADCON1<6:4>). There are seven possible 1. ANSEL (Register12-1) clock options: 2. ADCON0 (Register12-2) (cid:129) F OSC/2 3. ADCON1 (Register12-3) (cid:129) F OSC/4 12.1.1 ANALOG PORT PINS (cid:129) F OSC/8 The ANS<7:0> bits (ANSEL<7:0>) and the TRIS bits (cid:129) F OSC/16 control the operation of the A/D port pins. Set the (cid:129) F OSC/32 corresponding TRIS bits to set the pin output driver to (cid:129) F OSC/64 its high-impedance state. Likewise, set the correspond- (cid:129) F RC (dedicated internal oscillator) ing ANSEL bit to disable the digital input buffer. For correct conversion, the A/D conversion clock Note: Analog voltages on any pin that is defined (1/TAD) must be selected to ensure a minimum TAD of as a digital input may cause the input 1.6μs. Table12-1 shows a few TAD calculations for buffer to conduct excess current. selected frequencies. 12.1.2 CHANNEL SELECTION There are up to eight analog channels on the PIC16F946, AN<7:0>. The CHS<2:0> bits (ADCON0<4:2>) control which channel is connected to the sample and hold circuit. 12.1.3 VOLTAGE REFERENCE There are two options for each reference to the A/D converter, VREF+ and VREF-. VREF+ can be connected to either VDD or an externally applied voltage. Alternatively, VREF- can be connected to either VSS or an externally applied voltage. VCFG<1:0> bits are used to select the reference source. TABLE 12-1: TAD vs. DEVICE OPERATING FREQUENCIES A/D Clock Source (TAD) Device Frequency Operation ADCS<2:0> 20 MHz 5 MHz 4 MHz 1.25 MHz 2 TOSC 000 100 ns(2) 400 ns(2) 500 ns(2) 1.6 μs 4 TOSC 100 200 ns(2) 800 ns(2) 1.0 μs(2) 3.2 μs 8 TOSC 001 400 ns(2) 1.6 μs 2.0 μs 6.4 μs 16 TOSC 101 800 ns(2) 3.2 μs 4.0 μs 12.8 μs(3) 32 TOSC 010 1.6 μs 6.4 μs 8.0 μs(3) 25.6 μs(3) 64 TOSC 110 3.2 μs 12.8 μs(3) 16.0 μs(3) 51.2 μs(3) A/D RC x11 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical TAD time of 4 μs for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be performed during Sleep. Preliminary DS41265A-page 150 © 2005 Microchip Technology Inc.

PIC16F946 12.1.5 STARTING A CONVERSION The A/D conversion is initiated by setting the GO/DONE bit (ADCON0<1>). When the conversion is complete, the A/D module: (cid:129) Clears the GO/DONE bit (cid:129) Sets the ADIF flag (PIR1<6>) (cid:129) Generates an interrupt (if enabled) If the conversion must be aborted, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete A/D conversion sample. Instead, the ADRESH:ADRESL registers will retain the value of the previous conversion. After an aborted conversion, a 2TAD delay is required before another acquisition can be initiated. Following the delay, an input acquisition is automatically started on the selected channel. Note: The GO/DONE bit should not be set in the same instruction that turns on the A/D. FIGURE 12-2: A/D CONVERSION TAD CYCLES TCY TO TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit ADRESH and ADRESL registers are loaded, GO/DONE bit is cleared, ADIF bit is set, Holding Capacitor is Connected to Analog Input 12.1.6 CONVERSION OUTPUT The A/D conversion can be supplied in two formats: left or right shifted. The ADFM bit (ADCON0<7>) controls the output format. Figure12-3 shows the output formats. FIGURE 12-3: 10-BIT A/D RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result Preliminary © 2005 Microchip Technology Inc. DS41265A-page 151

PIC16F946 REGISTER 12-1: ANSEL – ANALOG SELECT REGISTER (ADDRESS: 91h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 bit 7-0: ANS<7:0>: Analog Select bits Select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input.(1) 0 = Digital I/O. Pin is assigned to port or special function. Note1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 12-2: ADCON0 – A/D CONTROL REGISTER (ADDRESS: 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 bit 7 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified bit 6 VCFG1: Voltage Reference bit 1 = VREF- pin 0 = VSS bit 5 VCFG0: Voltage Reference bit 1 = VREF+ pin 0 = VDD bit 4-2 CHS<2:0>: Analog Channel Select bits 000 =Channel 00 (AN0) 001 =Channel 01 (AN1) 010 =Channel 02 (AN2) 011 =Channel 03 (AN3) 100 =Channel 04 (AN4) 101 =Channel 05 (AN5) 110 =Channel 06 (AN6) 111 =Channel 07 (AN7) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: A/D Conversion Status bit 1 = A/D converter module is operating 0 = A/D converter is shut off and consumes no operating current Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 152 © 2005 Microchip Technology Inc.

PIC16F946 REGISTER 12-3: ADCON1 – A/D CONTROL REGISTER 1 (ADDRESS: 9Fh) U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCS2 ADCS1 ADCS0 — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max.) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 bit 3-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 153

PIC16F946 12.1.7 CONFIGURING THE A/D EXAMPLE 12-1: A/D CONVERSION After the A/D module has been configured as desired, ;This code block configures the A/D ;for polling, Vdd reference, R/C clock the selected channel must be acquired before the ;and RA0 input. conversion is started. The analog input channels must ; have their corresponding TRIS bits selected as inputs. ;Conversion start and wait for complete To determine sample time, see Section19.0 “Electrical ;polling code included. Specifications”. After this sample time has elapsed, the ; A/D conversion can be started. BSF STATUS,RP0 ;Bank 1 MOVLW B’01110000’ ;A/D RC clock These steps should be followed for an A/D conversion: MOVWF ADCON1 1. Configure the A/D module: BSF TRISA,0 ;Set RA0 to input BSF ANSEL,0 ;Set RA0 to analog (cid:129) Configure analog/digital I/O (ANSEL) BCF STATUS,RP0 ;Bank 0 (cid:129) Configure voltage reference (ADCON0) MOVLW B’10000001’ ;Right, Vdd Vref, AN0 (cid:129) Select A/D input channel (ADCON0) MOVWF ADCON0 CALL SampleTime ;Wait min sample time (cid:129) Select A/D conversion clock (ADCON1) BSF ADCON0,GO ;Start conversion (cid:129) Turn on A/D module (ADCON0) BTFSC ADCON0,GO ;Is conversion done? 2. Configure A/D interrupt (if desired): GOTO $-1 ;No, test again MOVF ADRESH,W ;Read upper 2 bits (cid:129) Clear ADIF bit (PIR1<6>) MOVWF RESULTHI (cid:129) Set ADIE bit (PIE1<6>) BSF STATUS,RP0 ;Bank 1 (cid:129) Set PEIE and GIE bits (INTCON<7:6>) MOVF ADRESL,W ;Read lower 8 bits 3. Wait the required acquisition time. MOVWF RESULTLO 4. Start conversion: (cid:129) Set GO/DONE bit (ADCON0<1>) 5. Wait for A/D conversion to complete, by either: (cid:129) Polling for the GO/DONE bit to be cleared (with interrupts disabled); OR (cid:129) Waiting for the A/D interrupt 6. Read A/D Result register pair (ADRESH:ADRESL); clear bit ADIF if required. 7. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before the next acquisition starts. Preliminary DS41265A-page 154 © 2005 Microchip Technology Inc.

PIC16F946 12.2 A/D Acquisition Requirements As the impedance is decreased, the acquisition time may be decreased. After the analog input channel is For the A/D converter to meet its specified accuracy, selected (changed), this acquisition must be done the charge holding capacitor (CHOLD) must be allowed before the conversion can be started. to fully charge to the input channel voltage level. The To calculate the minimum acquisition time, analog input model is shown in Figure12-4. The Equation12-1 may be used. This equation assumes source impedance (RS) and the internal sampling that 1/2 LSb error is used (1024 steps for the A/D). The switch (RSS) impedance directly affect the time 1/2 LSb error is the maximum error allowed for the A/D required to charge the capacitor CHOLD. The sampling to meet its specified resolution. switch (RSS) impedance varies over the device voltage (VDD), see Figure12-4. The maximum recom- To calculate the minimum acquisition time, TACQ, see mended impedance for analog sources is 10 kΩ. the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023). EQUATION 12-1: ACQUISITION TIME TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+[(Temperature - 25°C)(0.05µs/°C)] Where CHOLD is charged to within 1/2 lsb: ⎛ 1 ⎞ VAPPLIED⎝1– 2---0---4----7--⎠ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb ⎛ –----T---C---⎞ VAPPLIED⎜1–eRC⎟ = VCHOLD ;[2] VCHOLD charge response to VAPPLIED ⎝ ⎠ –Tc ⎛ -R----C----⎞ ⎛ 1 ⎞ VAPPLIED⎜1–e ⎟ = VAPPLIED⎝1– 2---0---4---7---⎠ ;combining [1] and [2] ⎝ ⎠ Solving for TC: TC = –CHOLD(RIC+RSS+RS) ln(1/2047) = –10pF(1kΩ+7kΩ+10kΩ) ln(0.0004885) = 1.37µs Therefore: TACQ = 2µS+1.37µS+[(50°C- 25°C)(0.05µS/°C)] = 4.67µS Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 155

PIC16F946 FIGURE 12-4: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC ≤ 1k SS RSS CHOLD VA C5 PpIFN VT = 0.6V I± L5E0A0K AnGAE == 1D0A pCF capacitance VSS 6V 5V RSS Legend: CPIN = Input Capacitance VDD4V VT = Threshold Voltage 3V 2V I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance 5 6 7 891011 SS = Sampling Switch Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) (kΩ) 12.3 A/D Operation During Sleep interrupt is enabled, the device awakens from Sleep. If the GIE bit (INTCON<7>) is set, the program counter is The A/D converter module can operate during Sleep. set to the interrupt vector (0004h). If GIE is clear, the This requires the A/D clock source to be set to the next instruction is executed. If the A/D interrupt is not internal oscillator. When the RC clock source is enabled, the A/D module is turned off, although the selected, the A/D waits one instruction before starting ADON bit remains set. the conversion. This allows the SLEEP instruction to be When the A/D clock source is something other than executed, thus eliminating much of the switching noise RC, a SLEEP instruction causes the present conversion from the conversion. When the conversion is complete, to be aborted, and the A/D module is turned off. The the GO/DONE bit is cleared and the result is loaded ADON bit remains set. into the ADRESH:ADRESL registers. If the A/D FIGURE 12-5: A/D TRANSFER FUNCTION Full-Scale Range 1 LSB Ideal 3FFh 3FEh 3FDh 3FCh 1/2 LSB Ideal ut 3FBh p ut O D A/ 004h Full-Scale Center of 003h Transition Full-Scale Code 002h 001h 000h Analog Input 1/2 LSB Ideal F E R V Zero-Scale Zero-Scale Transition Preliminary DS41265A-page 156 © 2005 Microchip Technology Inc.

PIC16F946 12.4 Effects of Reset A device Reset forces all registers to their Reset state. Thus, the A/D module is turned off and any pending conversion is aborted. The ADRESH:ADRESL registers are unchanged. TABLE 12-2: SUMMARY OF A/D REGISTERS Value on Value on: Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu 09h PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx uuuu uuuu 0Bh/ INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 8Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 1Eh ADRESH Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result xxxx xxxx uuuu uuuu 1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 89h TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 1111 1111 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 9Eh ADRESL Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result xxxx xxxx uuuu uuuu 9Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ---- Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for A/D module. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 157

PIC16F946 NOTES: Preliminary DS41265A-page 158 © 2005 Microchip Technology Inc.

PIC16F946 13.0 DATA EEPROM AND FLASH 13.1 EEADRL and EEADRH Registers PROGRAM MEMORY The EEADRL and EEADRH registers can address up CONTROL to a maximum of 256bytes of data EEPROM or up to a maximum of 8k words of program EEPROM. Data EEPROM memory is readable and writable and the Flash program memory is readable during normal When selecting a program address value, the MSB of operation (full VDD range). These memories are not the address is written to the EEADRH register and the directly mapped in the register file space. Instead, they LSB is written to the EEADRL register. When selecting are indirectly addressed through the Special Function a data address value, only the LSB of the address is Registers. There are six SFRs used to access these written to the EEADRL register. memories: 13.1.1 EECON1 AND EECON2 REGISTERS (cid:129) EECON1 EECON1 is the control register for EE memory (cid:129) EECON2 accesses. (cid:129) EEDATL Control bit EEPGD determines if the access will be a (cid:129) EEDATH program or data memory access. When clear, as it is (cid:129) EEADRL when reset, any subsequent operations will operate on (cid:129) EEADRH the data memory. When set, any subsequent operations When interfacing the data memory block, EEDATL will operate on the program memory. Program memory holds the 8-bit data for read/write, and EEADRL holds can only be read. the address of the EE data location being accessed. Control bits RD and WR initiate read and write, This device has 256 bytes of data EEPROM with an respectively. These bits cannot be cleared, only set, in address range from 0h to 0FFh. software. They are cleared in hardware at completion When interfacing the program memory block, the of the read or write operation. The inability to clear the EEDATL and EEDATH registers form a 2-byte word WR bit in software prevents the accidental, premature that holds the 14-bit data for read, and the EEADRL termination of a write operation. and EEADRH registers form a 2-byte word that holds The WREN bit, when set, will allow a write operation to the 13-bit address of the EEPROM location being data EEPROM. On power-up, the WREN bit is clear. accessed. This device has 4k and 8k words of program The WRERR bit is set when a write operation is EEPROM with an address range from 0h-0FFFh and interrupted by a MCLR or a WDT Time-out Reset 0h-1FFFh. The program memory allows one-word during normal operation. In these situations, following reads. Reset, the user can check the WRERR bit and rewrite the location. The data and address will be unchanged The EEPROM data memory allows byte read and write. in the EEDATL and EEADRL registers. A byte write automatically erases the location and writes the new data (erase before write). Interrupt flag bit EEIF (PIR1<7>), is set when write is complete. It must be cleared in the software. The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip EECON2 is not a physical register. Reading EECON2 charge pump rated to operate over the voltage range of will read all ‘0’s. The EECON2 register is used the device for byte or word operations. exclusively in the data EEPROM write sequence. When the device is code-protected, the CPU may continue to read and write the data EEPROM memory and read the program memory. When code-protected, the device programmer can no longer access data or program memory. Additional information on the data EEPROM is available in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023). Preliminary © 2005 Microchip Technology Inc. DS41265A-page 159

PIC16F946 REGISTER 13-1: EEDATL – EEPROM DATA LOW BYTE REGISTER (ADDRESS: 10Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 bit 7 bit 0 bit 7-0 EEDATL<7:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 13-2: EEADRL – EEPROM ADDRESS LOW BYTE REGISTER (ADDRESS: 10Dh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 bit 7 bit 0 bit 7-0 EEADRL<7:0>: Specifies one of 256 locations for EEPROM Read/Write operation bits or low byte for program memory reads Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 13-3: EEDATH – EEPROM DATA HIGH BYTE REGISTER (ADDRESS: 10Eh) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 bit 7 bit 0 bit 5-0 EEDATH<5:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 13-4: EEADRH – EEPROM ADDRESS HIGH BYTE REGISTER (ADDRESS: 10Fh) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 bit 7 bit 0 bit 4-0 EEADRH<4:0>: Specifies one of 256 locations for EEPROM Read/Write operation bits or high bits for program memory reads Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 160 © 2005 Microchip Technology Inc.

PIC16F946 REGISTER 13-5: EECON1 – EEPROM CONTROL REGISTER 1 (ADDRESS: 18Ch) R/W-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — — WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory bit 6-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or Brown-out Reset) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM bit 1 WR: Write Control bit EEPGD = 1: This bit is ignored EEPGD = 0: 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates a memory read (RD is cleared in hardware. The RD bit can only be set, not cleared, in software.) 0 = Does not initiate an memory read Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 161

PIC16F946 13.1.2 READING THE DATA EEPROM The steps to write to EEPROM data memory are: MEMORY 1. If step 10 is not implemented, check the WR bit To read a data memory location, the user must write the to see if a write is in progress. address to the EEADRL register, clear the EEPGD 2. Write the address to EEADR. Make sure that the control bit (EECON1<7>), and then set control bit RD address is not larger than the memory size of (EECON1<0>). The data is available in the very next the device. cycle, in the EEDATL register; therefore, it can be read 3. Write the 8-bit data value to be programmed in in the next instruction. EEDATL will hold this value until the EEDATA register. another read or until it is written to by the user (during 4. Clear the EEPGD bit to point to EEPROM data a write operation). memory. 5. Set the WREN bit to enable program operations. EXAMPLE 13-1: DATA EEPROM READ 6. Disable interrupts (if enabled). BSF STATUS,RP1 ; 7. Execute the special five instruction sequence: BCF STATUS,RP0 ; Bank 2 MOVF DATA_EE_ADDR,W ; Data Memory (cid:129) Write 55h to EECON2 in two steps (first to W, MOVWF EEADR ; Address to read then to EECON2) BSF STATUS,RP0 ; Bank 3 (cid:129) Write AAh to EECON2 in two steps (first to BCF EECON1,EEPGD ; Point to Data W, then to EECON2) ; memory (cid:129) Set the WR bit BSF EECON1,RD ; EE Read BCF STATUS,RP0 ; Bank 2 8. Enable interrupts (if using interrupts). MOVF EEDATA,W ; W = EEDATA 9. Clear the WREN bit to disable program operations. 13.1.3 WRITING TO THE DATA EEPROM 10. At the completion of the write cycle, the WR bit MEMORY is cleared and the EEIF interrupt flag bit is set. (EEIF must be cleared by firmware.) If step 1 is To write an EEPROM data location, the user must first not implemented, then firmware should check write the address to the EEADRL register and the data for EEIF to be set, or WR to clear, to indicate the to the EEDATL register. Then the user must follow a end of the program cycle. specific sequence to initiate the write for each byte. The write will not initiate if the sequence described below EXAMPLE 13-2: DATA EEPROM WRITE is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. Interrupts BSF STATUS,RP1 ; should be disabled during this codesegment. BSF STATUS,RP0 BTFSC EECON1,WR ;Wait for write Additionally, the WREN bit in EECON1 must be set to GOTO $-1 ;to complete enable write. This mechanism prevents accidental BCF STATUS,RP0 ;Bank 2 writes to data EEPROM due to errant (unexpected) MOVF DATA_EE_ADDR,W;Data Memory code execution (i.e., lost programs). The user should MOVWF EEADR ;Address to write keep the WREN bit clear at all times, except when MOVF DATA_EE_DATA,W;Data Memory Value updating EEPROM. The WREN bit is not cleared MOVWF EEDATA ;to write byhardware. BSF STATUS,RP0 ;Bank 3 BCF EECON1,EEPGD;Point to DATA After a write sequence has been initiated, clearing the ;memory WREN bit will not affect this write cycle. The WR bit will BSF EECON1,WREN ;Enable writes be inhibited from being set unless the WREN bit is set. BCF INTCON,GIE ;Disable INTs. At the completion of the write cycle, the WR bit is MOVLW 55h ; cleared in hardware and the EE Write Complete Iecnlnetaeabrrreluedp ttb hyFis lsa oginf ttwbeiartr rue(pE.tE IoFr) piso lls etht.i sT hbeit . uEseErI Fc amnu estit hbeer RequiredSequence MMMBOOOSVVVFWLWFWF EEAEEEAEChCCOOONNN221,WR ;;;;W WSrreiittt eeW R5A 5Abhhit to ;begin write BSF INTCON,GIE ;Enable INTs. BCF EECON1,WREN ;Disable writes Preliminary DS41265A-page 162 © 2005 Microchip Technology Inc.

PIC16F946 13.1.4 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must write two bytes of the address to the EEADRL and EEADRH registers, set the EEPGD control bit (EECON1<7>), and then set control bit RD (EECON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF EECON1,RD” instruction to be ignored. The data is available in the very next cycle, in the EEDATL and EEDATH registers; therefore, it can be read as two bytes in the following instructions. EEDATL and EEDATH registers will hold this value until another read or until it is written to by the user (during a write operation). Note1: The two instructions following a program memory read are required to be NOP’s. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. 2: If the WR bit is set when EEPGD = 1, it will be immediately reset to ‘0’ and no operation will take place. EXAMPLE 13-3: FLASH PROGRAM READ BSF STATUS, RP1 ; BCF STATUS, RP0 ; Bank 2 MOVLW MS_PROG_EE_ADDR; MOVWF EEADRH ; MS Byte of Program Address to read MOVLW LS_PROG_EE_ADDR; MOVWF EEADR ; LS Byte of Program Address to read BSF STATUS, RP0 ; Bank 3 BSF EECON1, EEPGD ; Point to PROGRAM memory BSF EECON1, RD ; EE Read RequiredSequence ; NNOOPP ;; mAenmyo riyn sitsr urcetaido nisn hseerceo nadr ec yicglneo raefdt ears BpSrFo gErEaCmON1,RD ; BCF STATUS, RP0 ; Bank 2 MOVF EEDATA, W ; W = LS Byte of Program EEDATA MOVWF DATAL ; MOVF EEDATH, W ; W = MS Byte of Program EEDATA MOVWF DATAH ; Preliminary © 2005 Microchip Technology Inc. DS41265A-page 163

PIC16F946 FIGURE 13-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR PC PC + 1 EEADRH,EEADRL PPCC ++ 33 PC + 4 PC + 5 Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4) INSTR(PC - 1) BSF EECON1,RD INSTR(PC + 1) Forced NOP INSTR(PC + 3) INSTR(PC + 4) executed here executed here executed here executed here executed here executed here RD bit EEDATH EEDATL register EERHLT TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh/8Bh/ INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 10Ch EEDATL EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 0000 0000 0000 0000 10Dh EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 0000 0000 0000 0000 10Eh EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000 10Fh EEADRH — — — EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---0 0000 ---0 0000 18Ch EECON1 EEPGD — — — WRERR WREN WR RD 0--- x000 ---- q000 18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---- Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by data EEPROM module. Preliminary DS41265A-page 164 © 2005 Microchip Technology Inc.

PIC16F946 14.0 SSP MODULE OVERVIEW The Synchronous Serial Port (SSP) module is a serial interface used to communicate with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: (cid:129) Serial Peripheral Interface (SPI™) (cid:129) Inter-Integrated Circuit (I 2 C™) An overview of I2C operations and additional information on the SSP module can be found in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023). Refer to Application Note AN578, “Use of the SSP Module in the Multi-Master Environment” (DS00578). 14.1 SPI Mode This section contains register definitions and operational characteristics of the SPI module. Additional information on the SPI module can be found in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023). The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: (cid:129) Serial Data Out (SDO) – RC4/T1G/SDO/SEG11 (cid:129) Serial Data In (SDI) – RC7/RX/DT/SDI/SDA/SEG8 (cid:129) Serial Clock (SCK) – RC6/TX/CK/SCK/SCL/SEG9 Additionally, a fourth pin may be used when in a Slave mode of operation: (cid:129) Slave Select (SS ) – RA5/AN4/C2OUT/SS/SEG5 When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: (cid:129) Master mode (SCK is the clock output) (cid:129) Slave mode (SCK is the clock input) (cid:129) Clock Polarity (Idle state of SCK) (cid:129) Clock edge (output data on rising/falling edge of SCK) (cid:129) Clock Rate (Master mode only) (cid:129) Slave Select mode (Slave mode only) Preliminary © 2005 Microchip Technology Inc. DS41265A-page 165

PIC16F946 REGISTER 14-1: SSPSTAT – SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: SPI™ Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I 2 C™ mode: This bit must be maintained clear bit 6 CKE: SPI Clock Edge Select bit SPI mode, CKP = 0: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK (Microwire alternate) SPI mode, CKP = 1: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK (Microwire default) I 2 C mode: This bit must be maintained clear bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the Start bit is detected last. SSPEN is cleared. 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last. SSPEN is cleared. 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit Information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or ACK bit. 1 = Read 0 = Write bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I 2 C mode only): 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 166 © 2005 Microchip Technology Inc.

PIC16F946 REGISTER 14-2: SSPCON – SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI™ mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the over- flow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I 2 C™ mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In SPI mode: 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level (Microwire default) 0 = Idle state for clock is a low level (Microwire alternate) In I 2 C mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1011 = I2C Firmware Controlled Master mode (slave idle) 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary © 2005 Microchip Technology Inc. DS41265A-page 167

PIC16F946 FIGURE 14-1: SSP BLOCK DIAGRAM . (SPIMODE) Note1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = Internal Data Bus 0100), the SPI module will reset if the SS pin is set to VDD. Read Write 2: If the SPI is used in Slave mode with CKE=1, then the SS pin control must be SSPBUF reg enabled. RC7/RX/ DT/SDI/ 3: When the SPI is in Slave mode with SS pin SDA/SEG8 control enabled (SSPCON<3:0> = 0100), SSPSR reg the state of the SS pin can affect the state bit 0 Shift read back from the TRISC<4> bit. The Clock peripheral OE signal from the SSP module into PORTC controls the state that is read RC4/T1G/ Peripheral OE back from the TRISC<4> bit (see SDO/SEG11 Section19.4 “DC Characteristics: PIC16F946-I (Industrial), PIC16F946-E SS Control Enable (Extended)” for information on PORTC). RA5/AN2/ If read-modify-write instructions, such as C2OUT/SS/ Edge BSF, are performed on the TRISC register SEG5 Select while the SS pin is high, this will cause the TRISC<4> bit to be set, thus disabling the 2 SDO output. Clock Select SSPM<3:0> TMR2 Output 4 2 Edge Select Prescaler TCY RC6/TX/CK/ 4, 16, 64 SCK/SCL/ TRISC<6> SEG9 To enable the serial port, SSPEN bit (SSPCON<5>) must be set. To reset or reconfigure SPI mode: (cid:129) Clear bit SSPEN (cid:129) Re-initialize the SSPCON register (cid:129) Set SSPEN bit This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave in a serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. This is: (cid:129) SDI must have TRISC<7> set (cid:129) SDO must have TRISC<4> cleared (cid:129) SCK (Master mode) must have TRISC<6> cleared (cid:129) SCK (Slave mode) must have TRISC<6> set (cid:129) SS must have TRISA<5> set. Preliminary DS41265A-page 168 © 2005 Microchip Technology Inc.

PIC16F946 14.2 Operation When the application software is expecting to receive valid data, the SSPBUF should be read before the next When initializing the SPI, several options need to be byte of data to transfer is written to the SSPBUF. Buffer specified. This is done by programming the appropriate Full bit, BF (SSPSTAT<0>), indicates when SSPBUF control bits (SSPCON<5:0> and SSPSTAT<7:6>). has been loaded with the received data (transmission These control bits allow the following to be specified: is complete). When the SSPBUF is read, the BF bit is (cid:129) Master mode (SCK is the clock output) cleared. This data may be irrelevant if the SPI is only a (cid:129) Slave mode (SCK is the clock input) transmitter. Generally, the SSP interrupt is used to determine when the transmission/reception has com- (cid:129) Clock Polarity (Idle state of SCK) pleted. The SSPBUF must be read and/or written. If the (cid:129) Data Input Sample Phase (middle or end of data interrupt method is not going to be used, then software output time) polling can be done to ensure that a write collision does (cid:129) Clock Edge (output data on rising/falling edge of not occur. Example14-1 shows the loading of the SCK) SSPBUF (SSPSR) for data transmission. (cid:129) Clock Rate (Master mode only) The SSPSR is not directly readable or writable and can (cid:129) Slave Select mode (Slave mode only) only be accessed by addressing the SSPBUF register. The SSP consists of a transmit/receive shift register Additionally, the SSP Status register (SSPSTAT) (SSPSR) and a buffer register (SSPBUF). The SSPSR indicates the various status conditions. shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full detect bit, BF (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the Write Collision detect bit, WCOL (SSPCON<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. EXAMPLE 14-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit Preliminary © 2005 Microchip Technology Inc. DS41265A-page 169

PIC16F946 14.3 Enabling SPI I/O 14.4 Typical Connection To enable the serial port, SSP Enable bit, SSPEN Figure14-2 shows a typical connection between two (SSPCON<5>), must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1) SPI mode, clear the SSPEN bit, re-initialize the initiates the data transfer by sending the SCK signal. SSPCON registers and then set the SSPEN bit. This Data is shifted out of both shift registers on their configures the SDI, SDO, SCK and SS pins as serial programmed clock edge and latched on the opposite port pins. For the pins to behave as the serial port func- edge of the clock. Both processors should be tion, some must have their data direction bits (in the programmed to the same Clock Polarity (CKP), then TRIS register) appropriately programmed. That is: both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy (cid:129) SDI is automatically controlled by the SPI module data) depends on the application software. This leads (cid:129) SDO must have TRISC<4> bit cleared to three scenarios for data transmission: (cid:129) SCK (Master mode) must have TRISC<6> bit (cid:129) Master sends data – Slave sends dummy data cleared (cid:129) Master sends data – Slave sends data (cid:129) SCK (Slave mode) must have TRISC<6> bit set (cid:129) Master sends dummy data – Slave sends data (cid:129) SS must have TRISA<5> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 14-2: SPI™ MASTER/SLAVE CONNECTION SPI™ Master SSPM<3:0> = 00xxb SPI™ Slave SSPM<3:0> = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK Processor 1 Processor 2 Preliminary DS41265A-page 170 © 2005 Microchip Technology Inc.

PIC16F946 14.5 Master Mode Figure14-3, Figure14-5 and Figure14-6, where the MSB is transmitted first. In Master mode, the SPI clock The master can initiate the data transfer at any time rate (bit rate) is user programmable to be one of the because it controls the SCK. The master determines following: when the slave (Processor 2, Figure14-2) is to broadcast data by the software protocol. (cid:129) F OSC/4 (or TCY) (cid:129) F OSC/16 (or 4 (cid:129) TCY) In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is (cid:129) F OSC/64 (or 16 (cid:129) TCY) only going to receive, the SDO output could be (cid:129) Timer2 output/2 disabled (programmed as an input). The SSPSR This allows a maximum data rate (at 40 MHz) of register will continue to shift in the signal present on the 10Mbps. SDI pin at the programmed clock rate. As each byte is Figure14-3 shows the waveforms for Master mode. received, it will be loaded into the SSPBUF register as When the CKE bit is set, the SDO data is valid before if a normal received byte (interrupts and Status bits there is a clock edge on SCK. The change of the input appropriately set). This could be useful in receiver sample is shown based on the state of the SMP bit. The applications as a “Line Activity Monitor” mode. time when the SSPBUF is loaded with the received The clock polarity is selected by appropriately program- data is shown. ming the CKP bit (SSPCON<4>). This then, would give waveforms for SPI communication as shown in FIGURE 14-3: SPI™ MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2↓ SSPBUF Preliminary © 2005 Microchip Technology Inc. DS41265A-page 171

PIC16F946 14.6 Slave Mode becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the applica- In Slave mode, the data is transmitted and received as tion. the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), While in Slave mode, the external clock is supplied by the SPI module will reset if the SS pin is set the external clock source on the SCK pin. This external to VDD. clock must meet the minimum high and low times as specified in the electrical specifications. 2: If the SPI is used in Slave Mode with CKE set, then the SS pin control must be While in Sleep mode, the slave can transmit/receive enabled. data. When a byte is received, the device will wake-up from Sleep. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to 14.7 Slave Select Synchronization a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can The SS pin allows a Synchronous Slave mode. The be connected to the SDI pin. When the SPI needs to SPI must be in Slave mode with SS pin control enabled operate as a receiver, the SDO pin can be configured (SSPCON<3:0> = 04h). The pin must not be driven low as an input. This disables transmissions from the SDO. for the SS pin to function as an input. The data latch The SDI can always be left as an input (SDI function) must be high. When the SS pin is low, transmission and since it cannot create a bus conflict. reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and FIGURE 14-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2↓ SSPBUF Preliminary DS41265A-page 172 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 14-5: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2↓ SSPBUF FIGURE 14-6: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF Preliminary © 2005 Microchip Technology Inc. DS41265A-page 173

PIC16F946 14.8 Sleep Operation 14.10 Bus Mode Compatibility In Master mode, all module clocks are halted and the Table14-1 shows the compatibility between the transmission/reception will remain in that state until the standard SPI modes and the states of the CKP and device wakes from Sleep. After the device returns to CKE control bits. normal mode, the module will continue to trans- mit/receive data. TABLE 14-1: SPI™ BUS MODES In Slave mode, the SPI Transmit/Receive Shift register Control Bits State Standard SPI™ operates asynchronously to the device. This allows the Mode Terminology device to be placed in Sleep mode and data to be CKP CKE shifted into the SPI Transmit/Receive Shift register. 0, 0 0 1 When all 8 bits have been received, the SSP interrupt 0, 1 0 0 flag bit will be set and if enabled, will wake the device from Sleep. 1, 0 1 1 1, 1 1 0 14.9 Effects of a Reset There is also a SMP bit which controls when the data is A Reset disables the SSP module and terminates the sampled. current transfer. TABLE 14-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh,8Bh. INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh,18Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode. Preliminary DS41265A-page 174 © 2005 Microchip Technology Inc.

PIC16F946 14.11 SSP I 2 C Operation The SSPCON register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) The SSP module in I2C mode, fully implements all allow one of the following I2C modes to be selected: slave functions, except general call support, and pro- (cid:129) I 2C Slave mode (7-bit address) vides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master func- (cid:129) I 2C Slave mode (10-bit address) tions. The SSP module implements the Standard mode (cid:129) I 2C Slave mode (7-bit address), with Start and specifications, as well as 7-bit and 10-bit addressing. Stop bit interrupts enabled to support Firmware Master mode Two pins are used for data transfer. These are the RC6/TX/CK/SCK/SCL/SEG9 pin, which is the clock (cid:129) I 2C Slave mode (10-bit address), with Start and (SCL), and the RC7/RX/DT/SDI/SDA/SEG8 pin, which Stop bit interrupts enabled to support Firmware is the data (SDA). Master mode (cid:129) I 2C Start and Stop bit interrupts enabled to The SSP module functions are enabled by setting SSP support Firmware Master mode; Slave is idle enable bit SSPEN (SSPCON<5>). Selection of any I2C mode with the SSPEN bit set FIGURE 14-7: SSP BLOCK DIAGRAM forces the SCL and SDA pins to be open drain, pro- (I 2 C™ MODE) vided these pins are programmed to inputs by setting the appropriate TRISC bits. Pull-up resistors must be provided externally to the SCL and SDA pins for proper Internal Data Bus operation of the I2C module. Read Write Additional information on SSP I2C operation can be RC6/TX/ found in the “PICmicro® Mid-Range MCU Family CK/SCK/ SCL/SEG9 SSPBUF reg Reference Manual” (DS33023). Shift 14.12 Slave Mode Clock In Slave mode, the SCL and SDA pins must be config- SSPSR reg ured as inputs (TRISC<7:6> set). The SSP module will RC7/ MSb LSb override the input state with the output data when RX/DT/ SDI/ required (slave-transmitter). SDA/ Match Detect Addr Match When an address is matched, or the data transfer after SEG8 an address match is received, the hardware automati- cally will generate the Acknowledge (ACK) pulse, and SSPADD reg then load the SSPBUF register with the received value currently in the SSPSR register. Start and Set, Reset Stop bit Detect S, P bits There are certain conditions that will cause the SSP (SSPSTAT reg) module not to give this ACK pulse. They include (either or both): The SSP module has five registers for the I2C operation, a) The Buffer Full bit BF (SSPSTAT<0>) was set which are listed below. before the transfer was received. (cid:129) SSP Control Register (SSPCON) b) The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received. (cid:129) SSP Status Register (SSPSTAT) (cid:129) Serial Receive/Transmit Buffer (SSPBUF) In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table14-3 (cid:129) SSP Shift Register (SSPSR) – Not directly shows the results of when a data transfer byte is received, accessible given the status of bits BF and SSPOV. The shaded cells (cid:129) SSP Address Register (SSPADD) show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. For high and low times of the I2C specification, as well as the requirements of the SSP module, see Section19.0 “Electrical Specifications”. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 175

PIC16F946 14.12.1 ADDRESSING The sequence of events for 10-bit address is as follows, with steps 7-9 for slave-transmitter: Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, 1. Receive first (high) byte of address (bits SSPIF, the 8-bits are shifted into the SSPSR register. All BF and bit UA (SSPSTAT<1>) are set). incoming bits are sampled with the rising edge of the 2. Update the SSPADD register with second (low) clock (SCL) line. The value of register SSPSR<7:1> is byte of address (clears bit UA and releases the compared to the value of the SSPADD register. The SCL line). address is compared on the falling edge of the eighth 3. Read the SSPBUF register (clears bit BF) and clock (SCL) pulse. If the addresses match, and the BF clear flag bit SSPIF. and SSPOV bits are clear, the following events occur: 4. Receive second (low) byte of address (bits a) The SSPSR register value is loaded into the SSPIF, BF and UA are set). SSPBUF register. 5. Update the SSPADD register with the first (high) b) The Buffer Full bit, BF is set. byte of address; if match releases SCL line, this c) An ACK pulse is generated. will clear bit UA. d) SSP Interrupt Flag bit, SSPIF (PIR1<3>) is set 6. Read the SSPBUF register (clears bit BF) and (interrupt is generated if enabled) on the falling clear flag bit SSPIF. edge of the ninth SCL pulse. 7. Receive repeated Start condition. In 10-bit Address mode, two address bytes need to be 8. Receive first (high) byte of address (bits SSPIF received by the slave (Figure14-8). The five Most and BF are set). Significant bits (MSbs) of the first address byte specify 9. Read the SSPBUF register (clears bit BF) and if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must clear flag bit SSPIF. specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. TABLE 14-3: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Set bit SSPIF Transfer is Received SSPSR → SSPBUF Generate ACK (SSP Interrupt occurs Pulse if enabled) BF SSPOV 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition. Preliminary DS41265A-page 176 © 2005 Microchip Technology Inc.

PIC16F946 14.12.2 RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON<6>) is set. This is an error condition due to the user’s firmware. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. FIGURE 14-8: I 2 C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF (PIR1<3>) Cleared in software Bus Master terminates transfer BF (SSPSTAT<0>) SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 177

PIC16F946 FIGURE 14-9: I2C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS) ers nt. ACK 9P Bus mastterminatetransfer SSPOV is setbecause SSPBUF isstill full. ACK is not se 0 D 8 1 e D 7 ar eceive Data Byte D5D4D3D2 3456 Cleared in softw R D6 2 7 D 1 K AC 9 0 D 8 gh d low untilSPADD has Receive Data Byte D7D6D5D4D3D1D2 1234576 Cleared in software Cleared by hardware whenSSPADD is updated with hibyte of address Clock is helClock is held low untilupdate of Supdate of SSPADD has taken placetaken place First Byte of AddressReceive Second Byte of Address0R/W = ACKACK110A9A8A7A6A5A4A3A2A1A0 3456789123456789 Cleared in softwareed in software SSPBUF is writtenDummy read of SSPBUFto clear BF flagwith contents of SSPSR >) UA is set indicatingCleared by hardwarethat the SSPADD needs towhen SSPADD is updatedbe updatedwith low byte of address UA is set indicatingthat SSPADD needs tobe updated 00es not reset to ‘’ when SEN = ) Receive 11 12 Clear AT<0>) PCON<6 AT<1>) (CKP do SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST CKP Preliminary DS41265A-page 178 © 2005 Microchip Technology Inc.

PIC16F946 14.12.3 TRANSMISSION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and When the R/W bit of the incoming address byte is set the SSPSTAT register is used to determine the status and an address match occurs, the R/W bit of the of the byte. Flag bit SSPIF is set on the falling edge of SSPSTAT register is set. The received address is the ninth clock pulse. loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin As a slave-transmitter, the ACK pulse from the master RC6/TX/CK/SCK/SCL/SEG9 is held low. The transmit receiver is latched on the rising edge of the ninth SCL data must be loaded into the SSPBUF register, which input pulse. If the SDA line was high (not ACK), then also loads the SSPSR register. Then, pin the data transfer is complete. When the ACK is latched RC6/TX/CK/SCK/SCL/SEG9 should be enabled by by the slave, the slave logic is reset (resets SSPSTAT setting bit CKP (SSPCON<4>). The master must mon- register) and the slave then monitors for another occur- itor the SCL pin prior to asserting another clock pulse. rence of the Start bit. If the SDA line was low (ACK), the The slave devices may be holding off the master by transmit data must be loaded into the SSPBUF register, stretching the clock. The eight data bits are shifted out which also loads the SSPSR register. Then pin on the falling edge of the SCL input. This ensures that RC6/TX/CK/SCK/SCL/SEG9 should be enabled by the SDA signal is valid during the SCL high time setting bit CKP. (Figure14-10). FIGURE 14-10: I 2 C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address R/W = 1 Transmitting Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Data in SCL held low sampled while CPU responds to SSPIF SSPIF (PIR1<3>) Cleared in software BF (SSPSTAT<0>) From SSP Interrupt SSPBUF is written in software Service Routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) Preliminary © 2005 Microchip Technology Inc. DS41265A-page 179

PIC16F946 FIGURE 14-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag ardware h Clock is held low untilupdate of SSPADD has Clock is held low untiltaken place1CKP is set to ‘’ Receive First Byte of Addressss1R/W = Transmitting Data Byte ACK11110A8A9ACKD7D6D5D4D3D1D2 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPBUFWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address CKP is set in software CKP is automatically cleared in holding SCL low e Clock is held low untilupdate of SSPADD has taken place0= Receive Second Byte of Addr A7A6A5A4A3A2A1A0CK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated withlow byte of address UA is set indicatingthat SSPADD needsto be updated W A R/Receive First Byte of Address 11110A9A8 12345678 AT<0>) SSPBUF is writtenwith contents ofSSPSRAT<1>) UA is set indicatingthat the SSPADDneeds to be updated ON<4>) SDA SCLS SSPIF (PIR1<3>) BF (SSPST UA (SSPST CKP (SSPC Preliminary DS41265A-page 180 © 2005 Microchip Technology Inc.

PIC16F946 14.13 Master Mode 14.14 Multi-Master Mode Master mode of operation is supported in firmware In Multi-Master mode, the interrupt generation on the using interrupt generation on the detection of the Start detection of the Start and Stop conditions, allows the and Stop conditions. The Stop (P) and Start (S) bits are determination of when the bus is free. The Stop (P) cleared from a Reset or when the SSP module is dis- and Start (S) bits are cleared from a Reset or when the abled. The Stop (P) and Start (S) bits will toggle based SSP module is disabled. The Stop (P) and Start (S) on the Start and Stop conditions. Control of the I2C bus bits will toggle based on the Start and Stop conditions. may be taken when the P bit is set or the bus is idle and Control of the I2C bus may be taken when bit P both the S and P bits are clear. (SSPSTAT<4>) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the In Master mode, the SCL and SDA lines are manipu- SSP Interrupt will generate the interrupt when the Stop lated by clearing the corresponding TRISC<6:7> bit(s). condition occurs. The output level is always low, irrespective of the value(s) in PORTC<6:7>. So when transmitting data, a In Multi-Master operation, the SDA line must be moni- ‘1’ data bit must have the TRISC<7> bit set (input) and tored to see if the signal level is the expected output a ‘0’ data bit must have the TRISC<7> bit cleared (out- level. This check only needs to be done when a high put). The same scenario is true for the SCL line with the level is output. If a high level is expected and a low TRISC<6> bit. Pull-up resistors must be provided level is present, the device needs to release the SDA externally to the SCL and SDA pins for proper opera- and SCL lines (set TRISC<6:7>). There are two tion of the I2C module. stages where this arbitration can be lost, these are: The following events will cause the SSP Interrupt Flag (cid:129) Address Transfer bit, SSPIF, to be set (SSP Interrupt will occur if (cid:129) Data Transfer enabled): When the slave logic is enabled, the slave continues (cid:129) Start condition to receive. If arbitration was lost during the address (cid:129) Stop condition transfer stage, communication to the device may be in (cid:129) Data transfer byte transmitted/received progress. If addressed, an ACK pulse will be gener- ated. If arbitration was lost during the data transfer Master mode of operation can be done with either the stage, the device will need to re-transfer the data at a Slave mode idle (SSPM<3:0> = 1011), or with the later time. Slave active. When both Master and Slave modes are enabled, the software needs to differentiate the 14.14.1 CLOCK SYNCHRONIZATION AND source(s) of the interrupt. THE CKP BIT When the CKP bit is cleared, the SCL output is forced to ‘0’; however, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure14-12). Preliminary © 2005 Microchip Technology Inc. DS41265A-page 181

PIC16F946 FIGURE 14-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX-1 SCL Master device asserts clock CKP Master device deasserts clock WR SSPCON TABLE 14-4: REGISTERS ASSOCIATED WITH I 2 C ™ OPERATION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh,18Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C™ mode) Address Register 0000 0000 0000 0000 94h SSPSTAT SMP(1) CKE(1) D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in I2C mode. Note 1: Maintain these bits clear in I2C mode. Preliminary DS41265A-page 182 © 2005 Microchip Technology Inc.

PIC16F946 15.0 CAPTURE/COMPARE/PWM CCP2 Module: MODULES Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and Each Capture/Compare/PWM (CCP) module contains CCPR2H (high byte). The CCP2CON register controls a 16-bit register which can operate as a: the operation of CCP2. The special event trigger is (cid:129) 16-bit Capture register generated by a compare match and will reset Timer1 (cid:129) 16-bit Compare register and start an A/D conversion (if the A/D module is enabled). (cid:129) PWM Master/Slave Duty Cycle register Additional information on CCP modules is available in Both the CCP1 and CCP2 modules are identical in the “PICmicro® Mid-Range MCU Family Reference operation, with the exception being the operation of the Manual” (DS33023) and in Application Note AN594, special event trigger. Table15-1 and Table15-2 show “Using the CCP Modules” (DS00594). the resources and interactions of the CCP module(s). In the following sections, the operation of a CCP TABLE 15-1: CCP MODE – TIMER module is described with respect to CCP1. CCP2 RESOURCES REQUIRED operates the same as CCP1, except where noted. CCP1 Module: CCP Mode Timer Resource Capture/Compare/PWM Register1 (CCPR1) is com- Capture Timer1 prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls Compare Timer1 the operation of CCP1. The special event trigger is PWM Timer2 generated by a compare match and will reset Timer1. TABLE 15-2: INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture Same TMR1 time base Capture Compare The compare should be configured for the special event trigger, which clears TMR1 Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1 PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt) PWM Capture None PWM Compare None Preliminary © 2005 Microchip Technology Inc. DS41265A-page 183

PIC16F946 REGISTER 15-1: CCP1CON – CCP2CON(1) REGISTER (ADDRESS: 17h/1Dh) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 184 © 2005 Microchip Technology Inc.

PIC16F946 15.1 Capture Mode 15.1.4 CCP PRESCALER In Capture mode, CCPR1H:CCPR1L captures the There are four prescaler settings, specified by bits 16-bit value of the TMR1 register when an event occurs CCP1M<3:0>. Whenever the CCP module is turned on pin RC5/T1CKI/CCP1/SEG10. An event is defined off, or the CCP module is not in Capture mode, the as one of the following: prescaler counter is cleared. Any Reset will clear the prescaler counter. (cid:129) Every falling edge Switching from one capture prescaler to another may (cid:129) Every rising edge generate an interrupt. Also, the prescaler counter will (cid:129) Every 4th rising edge not be cleared, therefore, the first capture may be from (cid:129) Every 16th rising edge a non-zero prescaler. Example15-1 shows the recom- The type of event is configured by control bits mended method for switching between capture pre- CCP1M<3:0> (CCPxCON<3:0>). When a capture is scalers. This example also clears the prescaler counter made, the interrupt request flag bit CCP1IF (PIR1<2>) and will not generate the “false” interrupt. is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register EXAMPLE 15-1: CHANGING BETWEEN CCPR1 is read, the old captured value is overwritten by CAPTURE PRESCALERS the new value. CLRF CCP1CON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load the W reg with 15.1.1 CCP PIN CONFIGURATION ; the new prescaler In Capture mode, the RC5/T1CKI/CCP1/SEG10 pin ; move value and CCP ON MOVWF CCP1CON ; Load CCP1CON with this should be configured as an input by setting the ; value TRISC<5> bit. Note: If the RC5/T1CKI/CCP1/SEG10 pin is configured as an output, a write to the port can cause a capture condition. FIGURE 15-3: CAPTURE MODE OPERATION BLOCK DIAGRAM RC5/T1CKI/ CCP1/SEG10 Set Flag bit CCP1IF pin (PIR1<2>) Prescaler ÷ 1, 4, 16 CCPR1H CCPR1L and Capture edge detect Enable TMR1H TMR1L CCP1CON<3:0> Qs 15.1.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode, or Synchro- nized Counter mode, for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. 15.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF, following any such change in Operating mode. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 185

PIC16F946 15.2 Compare Mode 15.2.3 SOFTWARE INTERRUPT MODE In Compare mode, the 16-bit CCPR1 register value is When Generate Software Interrupt mode is chosen, the constantly compared against the TMR1 register pair RC5/T1CKI/CCP1/SEG10 pin is not affected. The value. When a match occurs, the CCPIF bit is set, causing a CCP interrupt (if enabled). RC5/T1CKI/CCP1/SEG10 pin is: 15.2.4 SPECIAL EVENT TRIGGER (cid:129) Driven high In this mode, an internal hardware trigger is generated, (cid:129) Driven low which may be used to initiate an action. (cid:129) Remains unchanged The special event trigger output of CCP1 resets the The action on the pin is based on the value of control TMR1 register pair. This allows the CCPR1 register to bits CCP1M<3:0> (CCP1CON<3:0>). At the same effectively be a 16-bit programmable period register for time, interrupt flag bit CCP1IF is set. Timer1. The special event trigger output of CCP2 resets the FIGURE 15-4: COMPARE MODE TMR1 register pair and starts an A/D conversion (if the OPERATION BLOCK A/D module is enabled). DIAGRAM Note: The special event trigger from the Special event trigger will: CCP1and CCP2 modules will not set inter- reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>). rupt flag bit TMR1IF (PIR1<0>). Special Event Trigger 15.3 PWM Mode (PWM) Set Flag bit CCP1IF In Pulse-Width Modulation mode, the CCPx pin pro- RC5/T1CKI/ (PIR1<2>) CCP1/SEG10 CCPR1H CCPR1L duces up to a 10-bit resolution PWM output. Since the pin RC5/T1CKI/CCP1/SEG10 pin is multiplexed with the Q S Output PORTC data latch, the TRISC<5> bit must be cleared R Logic Match Comparator to make the RC5/T1CKI/CCP1/SEG10 pin an output. TRISC<5> TMR1H TMR1L Note: Clearing the CCP1CON register will force Output Enable CCP1CON<3:0> Mode Select the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data 15.2.1 CCP PIN CONFIGURATION latch. Figure15-5 shows a simplified block diagram of the The user must configure the RC5/T1CKI/CCP1/SEG10 CCP module in PWM mode. pin as an output by clearing the TRISC<5> bit. For a step-by-step procedure on how to set up the CCP Note: Clearing the CCP1CON register will force module for PWM operation, see Section15.3.3 the RC5/T1CKI/CCP1/SEG10 compare “Setup for PWM Operation”. output latch to the default low level. This is not the PORTC I/O data latch. 15.2.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode, or Synchro- nized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. Preliminary DS41265A-page 186 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 15-5: SIMPLIFIED PWM BLOCK When TMR2 is equal to PR2, the following three events DIAGRAM occur on the next increment cycle: (cid:129) TMR2 is cleared CCP1CON<5:4> Duty Cycle Registers (cid:129) The RC5/T1CKI/CCP1/SEG10 pin is set CCPR1L (exception: if PWM duty cycle=0%, the RC5/T1CKI/CCP1/SEG10 pin will not be set) (cid:129) The PWM duty cycle is latched from CCPR1L into CCPR1H CCPR1H (Slave) RC5/T1CKI/ Note: The Timer2 postscaler (see Section7.0 CCP1/SEG10 “Timer2 Module”) is not used in the Comparator R Q determination of the PWM frequency. The postscaler could be used to have a servo TMR2 (1) update rate at a different frequency than S the PWM output. Comparator TRISC<5> 15.3.2 PWM DUTY CYCLE Clear Timer, CCP1 pin and The PWM duty cycle is specified by writing to the latch D.C. PR2 CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains Note 1: The 8-bit timer is concatenated with 2-bit internal Q the eight MSbs and the CCP1CON<5:4> contains the clock, or 2 bits of the prescaler, to create 10-bit time two LSbs. This 10-bit value is represented by base. CCPR1L:CCP1CON<5:4>. The following equation is A PWM output (Figure15-6) has a time base (period) used to calculate the PWM duty cycle in time: and a time that the output stays high (duty cycle). The PWM duty cycle =(CCPR1L:CCP1CON<5:4>) (cid:129) frequency of the PWM is the inverse of the period TOSC (cid:129)(TMR2 prescale value) (1/period). CCPR1L and CCP1CON<5:4> can be written to at any FIGURE 15-6: PWM OUTPUT time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 Period occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are Duty Cycle used to double buffer the PWM duty cycle. This double buffering is essential for glitch-free PWM operation. TMR2 = PR2 When the CCPR1H and 2-bit latch match TMR2, con- TMR2 = Duty Cycle catenated with an internal 2-bit Q clock, or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. TMR2 = PR2 The maximum PWM resolution (bits) for a given PWM frequency is given by the formula: 15.3.1 PWM PERIOD log⎛-------------------------F----O---S---C--------------------------⎞ The PWM period is specified by writing to the PR2 ⎝FPWM×TMR2 Prescaler⎠ PWM Resolution = ---------------------------------------------------------------------------bits register. The PWM period can be calculated using the log(2) following formula: PWM period = (PR2) + 1] (cid:129) 4 (cid:129) T OSC (cid:129) Note: If the PWM duty cycle value is longer than (TMR2 prescale value) the PWM period, the RC5/T1CKI/CCP1/SEG10 pin will not be cleared. PWM frequency is defined as 1/[PWM period]. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 187

PIC16F946 15.3.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 register. 2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. 3. Make the RC5/T1CKI/CCP1/SEG10 pin an output by clearing the TRISC<5> bit. 4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. 5. Configure the CCP1 module for PWM operation. TABLE 15-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFFh 0xFFh 0xFFh 0x3Fh 0x1Fh 0x17h Maximum Resolution (bits) 10 10 10 8 7 5.5 TABLE 15-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh, 18Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF 0000 -0-0 0000 -0-0 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE 0000 -0-0 0000 -0-0 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. Preliminary DS41265A-page 188 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 15-3: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 10Bh, 18Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF 0000 -0-0 0000 -0-0 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE 0000 -0-0 0000 -0-0 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 11h TMR2 Timer2 Module Register 0000 0000 0000 0000 92h PR2 Timer2 Module Period Register 1111 1111 1111 1111 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 189

PIC16F946 NOTES: Preliminary DS41265A-page 190 © 2005 Microchip Technology Inc.

PIC16F946 16.0 SPECIAL FEATURES OF THE The PIC16F946 has two timers that offer necessary CPU delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until The PIC16F946 has a host of features intended to the crystal oscillator is stable. The other is the maximize system reliability, minimize cost through Power-up Timer (PWRT), which provides a fixed delay elimination of external components, provide power of 64ms (nominal) on power-up only, designed to saving features and offer code protection. keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if These features are: a brown-out occurs, which can use the Power-up (cid:129) Reset Timer to provide at least a 64ms Reset. With these - Power-on Reset (POR) three functions-on-chip, most applications need no - Power-up Timer (PWRT) external Reset circuitry. - Oscillator Start-up Timer (OST) The Sleep mode is designed to offer a very low-current - Brown-out Reset (BOR) Power-down mode. The user can wake-up from Sleep through: (cid:129) Interrupts (cid:129) Watchdog Timer (WDT) (cid:129) External Reset (cid:129) Oscillator Selection (cid:129) Watchdog Timer Wake-up (cid:129) Sleep (cid:129) An interrupt (cid:129) Code Protection Several oscillator options are also made available to (cid:129) ID Locations allow the part to fit the application. The INTOSC option saves system cost, while the LP crystal option saves (cid:129) In-Circuit Serial Programming™ power. A set of configuration bits are used to select various options (see Register16-1). Preliminary © 2005 Microchip Technology Inc. DS41265A-page 191

PIC16F946 16.1 Configuration Bits Note: Address 2007h is beyond the user The configuration bits can be programmed (read as program memory space. It belongs to the ‘0’), or left unprogrammed (read as ‘1’) to select various special configuration memory space device configurations as shown in Register16-1. (2000h-3FFFh), which can be accessed These bits are mapped in program memory location only during programming. See 2007h. “PIC16F91X/946 Memory Programming Specification” (DS41244) for more information. REGISTER 16-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h) — DEBUG FCMEN IESO BOREN1 BOREN0 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 13 bit 0 bit 13 Unimplemented: Read as ‘1’ bit 12 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are dedicated to the debugger bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 10 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled 0 = Internal External Switchover mode is disabled bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit (PCON<4>) 00 = BOR disabled bit 7 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 6 CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 5 MCLRE: RB3/MCLR/VPP pin function select bit(4) 1 = RB3/MCLR/VPP pin function is MCLR 0 = RB3/MCLR/VPP pin function is digital input, MCLR internally tied to VDD bit 4 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>) bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI 110 = RCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI 101 = INTOSC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI 100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI 011 = EC: I/O function on RA6/OSC2/CLKO/T1OSO pin, CLKI on RA7/OSC1/CLKI/T1OSI 010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI 001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI 000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off. 3: The entire program memory will be erased when the code protection is turned off. 4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS41265A-page 192 © 2005 Microchip Technology Inc.

PIC16F946 16.2 Reset They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and The PIC16F946 differentiates between various kinds of PD bits are set or cleared differently in different Reset Reset: situations, as indicated in Table16-2. These bits are a) Power-on Reset (POR) used in software to determine the nature of the Reset. b) WDT Reset during normal operation See Table16-5 for a full description of Reset states of all registers. c) WDT Reset during Sleep d) MCLR Reset during normal operation A simplified block diagram of the On-Chip Reset Circuit is shown in Figure16-1. e) MCLR Reset during Sleep f) Brown-out Reset (BOR) The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section19.0 “Electrical Some registers are not affected in any Reset condition; Specifications” for pulse width specifications. their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on: (cid:129) Power-on Reset (cid:129) MCLR Reset (cid:129) MCLR Reset during Sleep (cid:129) WDT Reset (cid:129) Brown-out Reset (BOR) FIGURE 16-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/VPP pin SLEEP WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out(1) Reset BOREN SBOREN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1/ CLKI pin PWRT LFINTOSC 11-bit Ripple Counter Enable PWRT Enable OST Note 1: Refer to the Configuration Word register (Register16-1). Preliminary © 2005 Microchip Technology Inc. DS41265A-page 193

PIC16F946 16.3 Power-on Reset FIGURE 16-2: RECOMMENDED MCLR CIRCUIT The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper VDD operation. To take advantage of the POR, simply PIC16F946 connect the MCLR pin through a resistor to VDD. This R1 will eliminate external RC components usually needed 1kΩ (or greater) to create Power-on Reset. A maximum rise time for VDD is required. See Section19.0 “Electrical Specifi- MCLR cations” for details. If the BOR is enabled, the maxi- mum rise time specification does not apply. The BOR C1 circuitry will keep the device in Reset until VDD reaches 0.1 μF (optional, not critical) VBOR (see Section16.3.3 “Brown-Out Reset (BOR)”). Note: The POR circuit does not produce an internal Reset when VDD declines. To 16.3.2 POWER-UP TIMER (PWRT) re-enable the POR, VDD must reach Vss The Power-up Timer provides a fixed 64ms (nominal) for a minimum of 100μs. time-out on power-up only, from POR or Brown-out When the device starts normal operation (exits the Reset. The Power-up Timer operates from the 31kHz Reset condition), device operating parameters (i.e., LFINTOSC oscillator. For more information, see voltage, frequency, temperature, etc.) must be met to Section4.4 “Internal Clock Modes”. The chip is kept ensure operation. If these conditions are not met, the in Reset as long as PWRT is active. The PWRT delay device must be held in Reset until the operating allows the VDD to rise to an acceptable level. A config- conditions are met. uration bit, PWRTE, can disable (if set) or enable (if For additional information, refer to Application Note cleared or programmed) the Power-up Timer. The AN607, “Power-up Trouble Shooting” (DS00607). Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. 16.3.1 MCLR The Power-up Timer delay will vary from chip-to-chip PIC16F946 has a noise filter in the MCLR Reset path. and vary due to: The filter will detect and ignore small pulses. (cid:129) V DD variation It should be noted that a WDT Reset does not drive (cid:129) Temperature variation MCLR pin low. (cid:129) Process variation The behavior of the ESD protection on the MCLR pin See DC parameters for details (Section19.0 has been altered from early devices of this family. “Electrical Specifications”). Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure16-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When cleared, MCLR is internally tied to VDD and an internal weak pull-up is enabled for the MCLR pin. In-Circuit Serial Programming is not affected by selecting the internal MCLR option. Preliminary DS41265A-page 194 © 2005 Microchip Technology Inc.

PIC16F946 16.3.3 BROWN-OUT RESET (BOR) This will occur regardless of VDD slew rate. A Reset is not insured to occur if VDD falls below VBOR for less The BOREN0 and BOREN1 bits in the Configuration than parameter (TBOR). Word register selects one of four BOR modes. Two modes have been added to allow software or hardware On any Reset (Power-on, Brown-out, Watchdog Timer, control of the BOR enable. When BOREN<1:0>=01, etc.), the chip will remain in Reset until VDD rises above the SBOREN bit (PCON<4>) enables/disables the VBOR (see Figure16-3). The Power-up Timer will now BOR allowing it to be controlled in software. By select- be invoked, if enabled and will keep the chip in Reset ing BOREN<1:0>, the BOR is automatically disabled in an additional 64ms. Sleep to conserve power and enabled on wake-up. In Note: The Power-up Timer is enabled by the this mode, the SBOREN bit is disabled. See PWRTE bit in the Configuration Word. Register16-1 for the Configuration Word definition. If VDD drops below VBOR while the Power-up Timer is If VDD falls below VBOR for greater than parameter running, the chip will go back into a Brown-out Reset (TBOR) (see Section19.0 “Electrical Specifica- and the Power-up Timer will be re-initialized. Once VDD tions”), the Brown-out situation will reset the device. rises above VBOR, the Power-up Timer will execute a 64ms Reset. FIGURE 16-3: BROWN-OUT SITUATIONS VDD VBOR Internal Reset 64 ms(1) VDD VBOR Internal < 64 ms Reset 64 ms(1) VDD VBOR Internal Reset 64 ms(1) Note 1: 64ms delay only if PWRTE bit is programmed to ‘0’. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 195

PIC16F946 16.3.4 TIME-OUT SEQUENCE 16.3.5 POWER CONTROL (PCON) REGISTER On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then The Power Control (PCON) register (address 8Eh) has OST is activated after the PWRT time-out has expired. two Status bits to indicate what type of Reset that last The total time-out will vary based on oscillator configu- occurred. ration and PWRTE bit status. For example, in EC mode Bit0 is BOR (Brown-out Reset). BOR is unknown on with PWRTE bit erased (PWRT disabled), there will be Power-on Reset. It must then be set by the user and no time-out at all. Figure16-4, Figure16-5 and Figure checked on subsequent Resets to see if BOR = 0, 16-6 depict time-out sequences. The device can exe- indicating that a Brown-out has occurred. The BOR cute code from the INTOSC while OST is active, by Status bit is a “don’t care” and is not necessarily enabling Two-Speed Start-up or Fail-Safe Monitor (see predictable if the brown-out circuit is disabled Section4.6.2 “Two-Speed Start-up Sequence” and (BOREN<1:0> = 00 in the Configuration Word register). Section4.7 “Fail-Safe Clock Monitor”). Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on Since the time-outs occur from the POR pulse, if MCLR Reset and unaffected otherwise. The user must write a is kept low long enough, the time-outs will expire. Then, ‘1’ to this bit following a Power-on Reset. On a bringing MCLR high will begin execution immediately subsequent Reset, if POR is ‘0’, it will indicate that a (see Figure16-5). This is useful for testing purposes or Power-on Reset has occurred (i.e., VDD may have to synchronize more than one PIC16F946 device gone too low). operating in parallel. For more information, see Section16.3.3 “Brown-Out Table16-5 shows the Reset conditions for some Reset (BOR)”. special registers, while Table16-5 shows the Reset conditions for all the registers. TABLE 16-1: TIME-OUT IN VARIOUS SITUATIONS Power-up Brown-out Reset Wake-up from Oscillator Configuration PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 Sleep XT, HS, LP(1) TPWRT + 1024 (cid:129) 1024 (cid:129)TOSC TPWRT + 1024 (cid:129) 1024 (cid:129)TOSC 1024 (cid:129)TOSC TOSC TOSC RC, EC, INTOSC TPWRT — TPWRT — — Note 1: LP mode with T1OSC disabled. TABLE 16-2: PCON BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 u 1 1 Power-on Reset 1 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets(1) 03h STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu 8Eh PCON — — — SBOREN — — POR BOR --01 --qq --0u --uu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Preliminary DS41265A-page 196 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 16-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 16-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 16-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset Preliminary © 2005 Microchip Technology Inc. DS41265A-page 197

PIC16F946 TABLE 16-4: INITIALIZATION CONDITION FOR REGISTERS (cid:129) MCLR Reset (cid:129) Wake-up from Sleep Register Address Power-on (cid:129) WDT Reset through interrupt Reset (cid:129) Brown-out Reset (1) (cid:129) Wake-up from Sleep through WDT time-out W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/ xxxx xxxx xxxx xxxx uuuu uuuu 100h/180h TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/ 0000 0000 0000 0000 PC + 1(3) 102h/182h STATUS 03h/83h/ 0001 1xxx 000q quuu(4) uuuq quuu(4) 103h/183h FSR 04h/84h/ xxxx xxxx uuuu uuuu uuuu uuuu 104h/184h PORTA 05h xxxx xxxx 0000 0000 uuuu uuuu PORTB 06h/106h xxxx xxxx 0000 0000 uuuu uuuu PORTC 07h xxxx xxxx 0000 0000 uuuu uuuu PORTD 08h xxxx xxxx 0000 0000 uuuu uuuu PORTE 09h xxxx xxxx 0000 0000 uuuu uuuu PCLATH 0Ah/8Ah/ ---0 0000 ---0 0000 ---u uuuu 10Ah/18Ah INTCON 0Bh/8Bh/ 0000 000x 0000 000x uuuu uuuu(2) 10Bh/18Bh PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2) PIR2 0Dh 0000 -0-0 0000 -0-0 uuuu -u-u TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu uuuu uuuu TMR2 11h 01-0 0-00 01-0 0-00 uu-u u-uu T2CON 12h -000 0000 -000 0000 -uuu uuuu SSPBUF 13h xxxx xxxx xxxx xxxx uuuu uuuu SSPCON 14h 0000 0000 0000 0000 uuuu uuuu CCPR1L 15h 0000 0000 0000 0000 uuuu uuuu CCPR1H 16h 0000 0010 0000 0010 uuuu uuuu CCP1CON 17h 000x 000x 000x 000x uuuu uuuu RCSTA 18h ---0 1000 ---0 1000 ---u uuuu TXREG 19h 0000 0000 0000 0000 uuuu uuuu RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu CCP2CON 1Dh --00 0000 --00 0000 --uu uuuu ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table16-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. Preliminary DS41265A-page 198 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 16-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) (cid:129) MCLR Reset (cid:129) Wake-up from Sleep Register Address Power-on (cid:129) WDT Reset through interrupt Reset (cid:129) Brown-out Reset (1) (cid:129) Wake-up from Sleep through WDT time-out ADCON0 1Fh 0000 0000 0000 0000 uuuu uuuu OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu TRISA 85h 1111 1111 1111 1111 uuuu uuuu TRISB 86h/186h 1111 1111 1111 1111 uuuu uuuu TRISC 87h 1111 1111 1111 1111 uuuu uuuu TRISD 88h 1111 1111 1111 1111 uuuu uuuu TRISE 89h 1111 1111 1111 1111 uuuu uuuu PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu PIE2 8Dh 0000 0000 0000 0000 uuuu uuuu PCON 8Eh --01 --0x --0u --uu(1,5) --uu --uu OSCCON 8Fh -110 q000 -110 x000 -uuu uuuu OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu ANSEL 91h 1111 1111 1111 1111 uuuu uuuu PR2 92h 1111 1111 1111 1111 1111 1111 SSPADD 93h 0000 0000 0000 0000 uuuu uuuu SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu WPUB 95h 1111 1111 1111 1111 uuuu uuuu IOCB 96h 0000 ---- 0000 ---- uuuu ---- CMCON1 97h ---- --10 ---- --10 ---- --uu TXSTA 98h 0000 -010 0000 -010 uuuu -uuu SPBRG 99h 0000 0000 0000 0000 uuuu uuuu CMCON0 9Ch 0000 0000 0000 0000 uuuu uuuu VRCON 9Dh 0-0- 0000 0-0- 0000 u-u- uuuu ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 9Fh -000 ---- -000 ---- -uuu ---- WDTCON 105h ---0 1000 ---0 1000 ---u uuuu LCDCON 107h 0001 0011 0001 0011 uuuu uuuu LCDPS 108h 0000 0000 0000 0000 uuuu uuuu LVDCON 109h --00 -100 --00 -100 --uu -uuu EEDATL 10Ch 0000 0000 0000 0000 uuuu uuuu EEADRL 10Dh 0000 0000 0000 0000 uuuu uuuu EEDATH 10Eh --00 0000 0000 0000 uuuu uuuu EEADRH 10Fh ---0 0000 0000 0000 uuuu uuuu LCDDATA0 110h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA1 111h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA2 112h xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table16-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 199

PIC16F946 TABLE 16-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) (cid:129) MCLR Reset (cid:129) Wake-up from Sleep Register Address Power-on (cid:129) WDT Reset through interrupt Reset (cid:129) Brown-out Reset (1) (cid:129) Wake-up from Sleep through WDT time-out LCDDATA3 113h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA4 114h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA5 115h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA6 116h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA7 117h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA8 118h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA9 119h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA10 11Ah xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA11 11Bh xxxx xxxx uuuu uuuu uuuu uuuu LCDSE0 11Ch 0000 0000 uuuu uuuu uuuu uuuu LCDSE1 11Dh 0000 0000 uuuu uuuu uuuu uuuu LCDSE2 11Eh 0000 0000 uuuu uuuu uuuu uuuu TRISF 185h 1111 1111 1111 1111 uuuu uuuu TRISG 187h --11 1111 --11 1111 --uu uuuu PORTF 188h xxxx xxxx 0000 0000 uuuu uuuu PORTG 189h --xx xxxx --00 0000 --uu uuuu LCDDATA12 190h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA13 191h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA14 192h ---- --xx ---- --uu ---- --uu LCDDATA15 193h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA16 194h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA17 195h ---- --xx ---- --uu ---- --uu LCDDATA18 196h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA19 197h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA20 198h ---- --xx ---- --uu ---- --uu LCDDATA21 199h xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA22 19Ah xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA23 19Bh ---- --xx ---- --uu ---- --uu LCDSE3 19Ch 0000 0000 uuuu uuuu uuuu uuuu LCDSE4 19Dh 0000 0000 uuuu uuuu uuuu uuuu LCDSE5 19Eh ---- --00 ---- --uu ---- --uu EECON1 18Ch x--- x000 u--- q000 u--- uuuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table16-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. Preliminary DS41265A-page 200 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 16-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Status PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx --01 --0x MCLR Reset during normal operation 000h 000u uuuu --0u --uu MCLR Reset during Sleep 000h 0001 0uuu --0u --uu WDT Reset 000h 0000 uuuu --0u --uu WDT Wake-up PC + 1 uuu0 0uuu --uu --uu Brown-out Reset 000h 0001 1uuu --01 --10 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu --uu --uu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 201

PIC16F946 16.4 Interrupts The following interrupt flags are contained in the PIR2 register: The PIC16F946 has multiple sources of interrupt: (cid:129) Fail-Safe Clock Monitor Interrupt (cid:129) External Interrupt RB0/INT/SEG0 (cid:129) Comparator 1 and 2 Interrupts (cid:129) TMR0 Overflow Interrupt (cid:129) LCD Interrupt (cid:129) PORTB Change Interrupts (cid:129) PLVD Interrupt (cid:129) 2 Comparator Interrupts (cid:129) CCP2 Interrupt (cid:129) A/D Interrupt When an interrupt is serviced: (cid:129) Timer1 Overflow Interrupt (cid:129) The GIE is cleared to disable any further interrupt. (cid:129) EEPROM Data Write Interrupt (cid:129) The return address is pushed onto the stack. (cid:129) Fail-Safe Clock Monitor Interrupt (cid:129) The PC is loaded with 0004h. (cid:129) LCD Interrupt (cid:129) PLVD Interrupt For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be (cid:129) USART Receive and Transmit Interrupts three or four instruction cycles. The exact latency (cid:129) CCP1 and CCP2 Interrupts depends upon when the interrupt event occurs (see (cid:129) TMR2 Interrupt Figure16-8). The latency is the same for one or The Interrupt Control (INTCON) register and Peripheral two-cycle instructions. Once in the Interrupt Service Interrupt Request 1 (PIR1) register record individual Routine, the source(s) of the interrupt can be interrupt requests in flag bits. The INTCON register determined by polling the interrupt flag bits. The also has individual and global interrupt enable bits. interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt A Global Interrupt Enable bit, GIE (INTCON<7>), requests. enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be Note1: Individual interrupt flag bits are set, disabled through their corresponding enable bits in the regardless of the status of their INTCON register and PIE1 register. GIE is cleared on corresponding mask bit or the GIE bit. Reset. 2: When an instruction that clears the GIE The Return from Interrupt instruction, RETFIE, exits bit is executed, any interrupts that were the interrupt routine, as well as sets the GIE bit, which pending for execution in the next cycle re-enables unmasked interrupts. are ignored. The interrupts, which were ignored, are still pending to be serviced The following interrupt flags are contained in the when the GIE bit is set again. INTCON register: (cid:129) INT Pin Interrupt For additional information on Timer1, A/D or data EEPROM modules, refer to the respective peripheral (cid:129) PORTB Change Interrupt section. (cid:129) TMR0 Overflow Interrupt Note: The ANSEL (91h) and CMCON0 (9Ch) The peripheral interrupt flags are contained in the special registers must be initialized to configure registers, PIR1 and PIR2. The corresponding interrupt an analog channel as a digital input. Pins enable bit are contained in the special registers, PIE1 configured as analog inputs will read ‘0’. and PIE2. Also, if a LCD output function is active on The following interrupt flags are contained in the PIR1 an external interrupt pin, that interrupt register: function will be disabled. (cid:129) EEPROM Data Write Interrupt (cid:129) A/D Interrupt (cid:129) USART Receive and Transmit Interrupts (cid:129) Timer1 Overflow Interrupt (cid:129) CCP1 Interrupt (cid:129) SSP Interrupt Preliminary DS41265A-page 202 © 2005 Microchip Technology Inc.

PIC16F946 16.4.1 RB0/INT/SEG0 INTERRUPT 16.4.2 TMR0 INTERRUPT External interrupt on RB0/INT/SEG0 pin is edge-trig- An overflow (FFh → 00h) in the TMR0 register will set gered; either rising if the INTEDG bit (OPTION<6>) is the T0IF (INTCON<2>) bit. The interrupt can be set, or falling, if the INTEDG bit is clear. When a valid enabled/disabled by setting/clearing T0IE edge appears on the RB0/INT/SEG0 pin, the INTF bit (INTCON<5>) bit. See Section5.0 “Timer0 Module” (INTCON<1>) is set. This interrupt can be disabled by for operation of the Timer0 module. clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the Interrupt Service 16.4.3 PORTB INTERRUPT Routine before re-enabling this interrupt. The An input change on PORTB sets the RBIF RB0/INT/SEG0 interrupt can wake-up the processor (INTCON<0>) bit. The interrupt can be from Sleep if the INTE bit was set prior to going into enabled/disabled by setting/clearing the RBIE Sleep. The status of the GIE bit decides whether or not (INTCON<3>) bit. Plus, individual pins can be the processor branches to the interrupt vector following configured through the IOCB register. wake-up (0004h). See Section16.7 “Power-Down Note: If a change on the I/O pin should occur Mode (Sleep)” for details on Sleep and Figure16-10 when the read operation is being executed for timing of wake-up from Sleep through (start of the Q2 cycle), then the RBIF RB0/INT/SEG0 interrupt. interrupt flag may not get set. FIGURE 16-7: INTERRUPT LOGIC IOC-RB4 IOCB4 IOC-RB5 IOCB5 IOC-RB6 IOCB6 IOC-RB7 IOCB7 TMR0IF Wake-up (If in Sleep mode) TMR2IF TMR0IE TMR2IE INTF TMR1IF INTE Interrupt to CPU TMR1IE RBIF C1IF RBIE C1IE C2IF PEIF C2IE PEIE ADIF ADIE GIE OSFIF OSFIE EEIF EEIE CCP1IF CCP1IE CCP2IF CCP2IE RCIF RCIE TXIF TXIE SSPIF SSPIE LCDIF LCDIE LVDIF LVDIE Preliminary © 2005 Microchip Technology Inc. DS41265A-page 203

PIC16F946 FIGURE 16-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKO(3) (4) INT pin (1) INTF Flag (1) (5) Interrupt Latency(2) (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC - 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction. 3: CLKO is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section19.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. TABLE 16-6: SUMMARY OF INTERRUPT REGISTERS Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 8Bh 0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF 0000 -0-0 0000 -0-0 8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE 0000 -0-0 0000 -0-0 Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the interrupt module. Preliminary DS41265A-page 204 © 2005 Microchip Technology Inc.

PIC16F946 16.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and Status registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC16F946 (see Figure2-2), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, make it easier to context save and restore. The same code shown in Example16-1 can be used to: (cid:129) Store the W register (cid:129) Store the Status register (cid:129) Execute the ISR code (cid:129) Restore the Status (and Bank Select Bit register) (cid:129) Restore the W register Note: The PIC16F946 normally does not require saving the PCLATH. However, if computed GOTO’s are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR. EXAMPLE 16-1: SAVING STATUS AND W REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into Status register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W Preliminary © 2005 Microchip Technology Inc. DS41265A-page 205

PIC16F946 16.6 Watchdog Timer (WDT) A new prescaler has been added to the path between the INTOSC and the multiplexers used to select the For PIC16F946, the WDT has been modified from path for the WDT. This prescaler is 16 bits and can be previous PIC16F devices. The new WDT is code and programmed to divide the INTOSC by 32 to 65536, functionally compatible with previous PIC16F WDT giving the WDT a nominal range of 1ms to 268s. modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaled value for the WDT and 16.6.2 WDT CONTROL TMR0 at the same time. In addition, the WDT time-out The WDTE bit is located in the Configuration Word value can be extended to 268 seconds. WDT is cleared register. When set, the WDT runs continuously. under certain conditions described in Table16-7. When the WDTE bit in the Configuration Word register 16.6.1 WDT OSCILLATOR is set, the SWDTEN bit (WDTCON<0>) has no effect. If WDTE is clear, then the SWDTEN bit can be used to The WDT derives its time base from the 31kHz enable and disable the WDT. Setting the bit will enable LFINTOSC. The LTS bit does not reflect that the it and clearing the bit will disable it. LFINTOSC is enabled. The PSA and PS<2:0> bits (OPTION_REG) have the The value of WDTCON is ‘---0 1000’ on all Resets. same function as in previous versions of the PIC16F This gives a nominal time base of 16ms, which is family of microcontrollers. See Section5.0 “Timer0 compatible with the time base generated with previous Module” for more information. PIC16F microcontroller versions. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled). FIGURE 16-9: WATCHDOG TIMER BLOCK DIAGRAM 0 From TMR0 Clock Source Prescaler(1) 1 16-bit WDT Prescaler 8 PSA PS<2:0> 31kHz WDTPS<3:0> To TMR0 LFINTOSC Clock 0 1 PSA WDTE from Configuration Word register SWDTEN from WDTCON WDT Time-out Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information. TABLE 16-7: WDT STATUS Conditions WDT WDTE = 0 CLRWDT Command Cleared Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Preliminary DS41265A-page 206 © 2005 Microchip Technology Inc.

PIC16F946 REGISTER 16-2: WDTCON – WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 105h) U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note1: If WDTE configuration bit=1, then WDT is always enabled, irrespective of this control bit. If WDTE configuration bit=0, then it is possible to turn WDT on/off with this control bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown TABLE 16-8: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 105h WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 2007h(1) CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register16-1 for operation of all Configuration Word register bits. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 207

PIC16F946 16.7 Power-Down Mode (Sleep) The following peripheral interrupts can wake the device from Sleep: The Power-down mode is entered by executing a 1. TMR1 Interrupt. Timer1 must be operating as an SLEEP instruction. asynchronous counter. If the Watchdog Timer is enabled: 2. EUSART Receive Interrupt (cid:129) WDT will be cleared but keeps running. 3. A/D conversion (when A/D clock source is RC) (cid:129) PD bit in the Status register is cleared. 4. EEPROM write operation completion (cid:129) TO bit is set. 5. Comparator output changes state (cid:129) Oscillator driver is turned off. 6. Interrupt-on-change (cid:129) I/O ports maintain the status they had before 7. External Interrupt from INT pin SLEEP was executed (driving high, low or 8. PLVD Interrupt high-impedance). 9. LCD Interrupt (if running during Sleep) For lowest current consumption in this mode, all I/O Other peripherals cannot generate interrupts since pins should be either at VDD or VSS, with no external during Sleep, no on-chip clocks are present. circuitry drawing current from the I/O pin, and the comparators and CVREF should be disabled. I/O pins When the SLEEP instruction is being executed, the next that are high-impedance inputs should be pulled high instruction (PC + 1) is pre-fetched. For the device to or low externally to avoid switching currents caused by wake-up through an interrupt event, the corresponding floating inputs. The T0CKI input should also be at VDD interrupt enable bit must be set (enabled). Wake-up is or VSS for lowest current consumption. The regardless of the state of the GIE bit. If the GIE bit is contribution from on-chip pull-ups on PORTB should be clear (disabled), the device continues execution at the considered. instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after The MCLR pin must be at a logic high level. the SLEEP instruction, then branches to the interrupt Note: It should be noted that a Reset generated address (0004h). In cases where the execution of the by a WDT time-out does not drive MCLR instruction following SLEEP is not desirable, the user pin low. should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is 16.7.1 WAKE-UP FROM SLEEP cleared), but any interrupt source has both The device can wake-up from Sleep through one of the its interrupt enable bit and the correspond- following events: ing interrupt flag bits set, the device will 1. External Reset input on MCLR pin. immediately wake-up from Sleep. The SLEEP instruction is completely executed. 2. Watchdog Timer wake-up (if WDT was enabled). The WDT is cleared when the device wakes up from 3. Interrupt from RB0/INT/SEG0 pin, PORTB Sleep, regardless of the source of wake-up. change or a peripheral interrupt. 16.7.2 WAKE-UP USING INTERRUPTS The first event will cause a device Reset. The two latter events are considered a continuation of program When global interrupts are disabled (GIE cleared) and execution. The TO and PD bits in the Status register any interrupt source has both its interrupt enable bit can be used to determine the cause of a device Reset. and interrupt flag bit set, one of the following will occur: The PD bit, which is set on power-up, is cleared when (cid:129) If the interrupt occurs before the execution of a Sleep is invoked. TO bit is cleared if WDT wake-up SLEEP instruction, the SLEEP instruction will occurred. complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. (cid:129) If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Preliminary DS41265A-page 208 © 2005 Microchip Technology Inc.

PIC16F946 Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. FIGURE 16-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) CLKO(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency(3) GIE bit Processor in (INTCON<7>) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC - 1) Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. 3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. 4: CLKO is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 209

PIC16F946 16.8 Code Protection A typical In-Circuit Serial Programming connection is shown in Figure16-11. If the code protection bit(s) have not been programmed, the on-chip program memory can be FIGURE 16-11: TYPICAL IN-CIRCUIT read out using ICSP for verification purposes. SERIAL PROGRAMMING Note: The entire data EEPROM and Flash CONNECTION program memory will be erased when the code protection is turned off. See the To Normal “PIC16F91X/946 Memory Programming Connections Specification” (DS41244) for more infor- External mation. Connector * Signals PIC16F946 +5V VDD 16.9 ID Locations 0V VSS Four memory locations (2000h-2003h) are designated VPP RE3/MCLR/VPP as ID locations where the user can store checksum or RB6/ICSPCLK/ other code identification numbers. These locations are CLK ICDCK/SEG14 not accessible during normal execution, but are Data I/O RB7/ICSPDATA/ readable and writable during Program/Verify mode. ICDDAT/SEG13 Only the Least Significant 7 bits of the ID locations are used. 16.10 In-Circuit Serial Programming * * * The PIC16F946 microcontrollers can be serially programmed while in the end application circuit. This is To Normal Connections simply done with two lines for clock and data and three other lines for: * Isolation devices (as required) (cid:129) power (cid:129) ground (cid:129) programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the micro- controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RB7/ICSPDAT/ICDDAT/SEG13 and RB6/ICSPCLK/ICDCK/SEG14 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See “PIC16F91X/946 Memory Programming Specification” (DS41244) for more information. RB7/ICSPDAT/ICD- DAT/SEG13 becomes the programming data and RB6/ICSPCLK/ICDCK/SEG14 becomes the program- ming clock. Both RB7/ICSPDAT/ICDDAT/SEG13 and RB6/ICSPCLK/ICDCK/SEG14 are Schmitt Trigger inputs in this mode. After Reset, to place the device into Program/Verify mode, the Program Counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. For complete details of serial programming, please refer to the “PIC16F91X/946 Memory Programming Specification” (DS41244). Preliminary DS41265A-page 210 © 2005 Microchip Technology Inc.

PIC16F946 16.11 In-Circuit Debugger For more information, see “Using MPLAB® ICD 2” (DS51265), available on Microchip’s web site The PIC16F946-ICD can be used in any of the package (www.microchip.com). types. The device will be mounted on the target appli- cation board, which in turn has a 3 or 4 wire connection 16.11.1 ICD PINOUT to the ICD tool. The devices in the PIC16F946 device carries the When the debug bit in the Configuration Word circuitry for the In-Circuit Debugger on-chip and on (CONFIG<12>) is programmed to a ‘0’, the In-Circuit existing device pins. This eliminates the need for a Debugger functionality is enabled. This function allows separate die or package for the ICD device. The pinout simple debugging functions when used with MPLAB® for the ICD device is the same as the devices (see ICD 2. When the microcontroller has this feature Section1.0 “Device Overview” for complete pinout enabled, some of the resources are not available for and pin descriptions). Table16-9 shows the location general use. See Table16-9 for more detail. and function of the ICD related pins on the 28 and 40 pin devices. Note: The user’s application must have the circuitry required to support ICD functionality. Once the ICD circuitry is enabled, normal device pin functions on RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 will not be usable. The ICD circuitry uses these pins for communication with the ICD2 external debugger. TABLE 16-9: PIC16F946-ICD PIN DESCRIPTIONS Pin Name Type Pull-up Description 24 ICDDATA TTL — In Circuit Debugger Bidirectional data 23 ICDCLK ST — In Circuit Debugger Bidirectional clock 36 MCLR/VPP HV — Programming voltage 10, 19, 38, 57 VDD P — 9, 20, 41, 56 VSS P — 26 AVDD P — 25 AVDD P — Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, P = Power, HV = High Voltage Preliminary © 2005 Microchip Technology Inc. DS41265A-page 211

PIC16F946 NOTES: Preliminary DS41265A-page 212 © 2005 Microchip Technology Inc.

PIC16F946 17.0 INSTRUCTION SET SUMMARY 17.1 READ-MODIFY-WRITE OPERATIONS The PIC16F946 instruction set is highly orthogonal and is comprised of three basic categories: Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (RMW) (cid:129) Byte-oriented operations operation. The register is read, the data is modified, (cid:129) Bit-oriented operations and the result is stored according to either the instruc- (cid:129) Literal and control operations tion, or the destination designator ‘d’. A read operation Each PIC16 instruction is a 14-bit word divided into an is performed on a register even if the instruction writes opcode, which specifies the instruction type and one or to that register. more operands, which further specify the operation of For example, a CLRF GPIO instruction will read GPIO, the instruction. The formats for each of the categories clear all the data bits, then write the result back to is presented in Figure17-1, while the various opcode GPIO. This example would have the unintended result fields are summarized in Table17-1. of clearing the condition that set the GPIF flag. Table17-2 lists the instructions recognized by the MPASMTM assembler. A complete description of each TABLE 17-1: OPCODE FIELD instruction is also available in the “PICmicro® DESCRIPTIONS Mid-Range MCU Family Reference Manual” (DS33023). Field Description For byte-oriented instructions, ‘f’ represents a file f Register file address (0x00 to 0x7F) register designator and ‘d’ represents a destination W Working register (accumulator) designator. The file register designator specifies which b Bit address within an 8-bit file register file register is to be used by the instruction. k Literal field, constant data or label The destination designator specifies where the result of x Don’t care location (= 0 or 1). the operation is to be placed. If ‘d’ is zero, the result is The assembler will generate code with x = 0. placed in the W register. If ‘d’ is one, the result is placed It is the recommended form of use for in the file register specified in the instruction. compatibility with all Microchip software tools. For bit-oriented instructions, ‘b’ represents a bit field d Destination select; d = 0: store result in W, designator, which selects the bit affected by the d = 1: store result in file register f. operation, while ‘f’ represents the address of the file in Default is d = 1. which the bit is located. PC Program Counter For literal and control operations, ‘k’ represents an TO Time-out bit 8-bit or 11-bit constant, or literal value. PD Power-down bit One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1μs. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. Note: To maintain upward compatibility with future products, do not use the OPTION and TRIS instructions. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 213

PIC16F946 FIGURE 17-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value Preliminary DS41265A-page 214 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 17-2: PIC16F946 INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1, 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1, 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into Standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 215

PIC16F946 17.2 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 Operation: (W) + k → (W) Operation: 0 → (f<b>) Status Affected: C, DC, Z Status Affected: None Description: The contents of the W register are added to the eight-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared. and the result is placed in the W register. ADDWF Add W and f BSF Bit Set f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + (f) → (destination) Operation: 1 → (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set. with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND Literal with W BTFSC Bit Test, Skip if Clear Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSC f,b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 Operation: (W) .AND. (k) → (W) 0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: The contents of W register are AND’ed with the eight-bit literal Description: If bit ‘b’ in register ‘f’ is ‘1’, the next ‘k’. The result is placed in the W instruction is executed. register. If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction. ANDWF AND W with f Syntax: [ label ] ANDWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .AND. (f) → (destination) Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Preliminary DS41265A-page 216 © 2005 Microchip Technology Inc.

PIC16F946 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 127 Operands: None 0 ≤ b < 7 Operation: 00h → WDT Operation: skip if (f<b>) = 1 0 → WDT prescaler, 1 → TO Status Affected: None 1 → PD Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Status Affected: TO, PD instruction is executed. If bit ‘b’ is ‘1’, then the next Description: CLRWDT instruction resets the instruction is discarded and a NOP Watchdog Timer. It also resets the is executed instead, making this a prescaler of the WDT. two-cycle instruction. Status bits TO and PD are set. CALL Call Subroutine COMF Complement f Syntax: [ label ] CALL k Syntax: [ label ] COMF f,d Operands: 0 ≤ k ≤ 2047 Operands: 0 ≤ f ≤ 127 Operation: (PC)+ 1→ TOS, d ∈ [0,1] k → PC<10:0>, Operation: (f) → (destination) (PCLATH<4:3>) → PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are Description: Call Subroutine. First, return complemented. If ‘d’ is ‘0’, the address (PC + 1) is PUSHed onto result is stored in W. If ‘d’ is ‘1’, the stack. The eleven-bit the result is stored back in immediate address is loaded into register ‘f’. PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: 00h → (f) 1 → Z Operation: (f) - 1 → (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Decrement register ‘f’. If ‘d’ is ‘0’, cleared and the Z bit is set. the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h → (W) 1 → Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 217

PIC16F946 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f) - 1 → (destination); Operation: (f) + 1 → (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. If the result is ‘1’, the next If the result is ‘1’, the next instruction is executed. If the instruction is executed. If the result is ‘0’, then a NOP is result is ‘0’, a NOP is executed executed instead, making it a instead, making it a two-cycle two-cycle instruction. instruction. GOTO Go to Address IORLW Inclusive OR Literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0 ≤ k ≤ 2047 Operands: 0 ≤ k ≤ 255 Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Operation: (W) .OR. k → (W) Status Affected: None Status Affected: Z Description: GOTO is an unconditional branch. Description: The contents of the W register are The eleven-bit immediate value is OR’ed with the eight-bit literal ‘k’. loaded into PC bits <10:0>. The The result is placed in the W upper bits of PC are loaded from register. PCLATH<4:3>. GOTO is a two-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f) + 1 → (destination) Operation: (W) .OR. (f) → (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Inclusive OR the W register with incremented. If ‘d’ is ‘0’, the result register ‘f’. If ‘d’ is ‘0’, the result is is placed in the W register. If ‘d’ is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. Preliminary DS41265A-page 218 © 2005 Microchip Technology Inc.

PIC16F946 MOVF Move f MOVWF Move W to f Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) → (f) Operation: (f) → (dest) Status Affected: None Status Affected: Z Encoding: 00 0000 1fff ffff Encoding: 00 1000 dfff ffff Description: Move data from W register to Description: The contents of register ‘f’ is register ‘f’. moved to a destination dependent upon the status of ‘d’. If ‘d’ = 0, Words: 1 destination is W register. If ‘d’ = 1, Cycles: 1 the destination is file register ‘f’ Example: MOVWF OPTION itself. ‘d’ = 1 is useful to test a file register since status flag Z is Before Instruction affected. OPTION= 0xFF W = 0x4F Words: 1 After Instruction Cycles: 1 OPTION= 0x4F Example: MOVF FSR, 0 W = 0x4F After Instruction W = value in FSR register Z = 1 MOVLW Move Literal to W NOP No Operation Syntax: [ label ] MOVLW k Syntax: [ label ] NOP Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W) Operation: No operation Status Affected: None Status Affected: None Encoding: 11 00xx kkkk kkkk Encoding: 00 0000 0xx0 0000 Description: The eight bit literal ‘k’ is loaded Description: No operation. into W register. The “don’t cares” Words: 1 will assemble as ‘0’s. Cycles: 1 Words: 1 Example: NOP Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A Preliminary © 2005 Microchip Technology Inc. DS41265A-page 219

PIC16F946 RETFIE Return from Interrupt RETLW Return with Literal in W Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, Operation: k → (W); 1 → GIE TOS → PC Status Affected: None Status Affected: None Encoding: 00 0000 0000 1001 Encoding: 11 01xx kkkk kkkk Description: Return from Interrupt. Stack is Description: The W register is loaded with the POPed and Top-of-Stack (TOS) is eight-bit literal ‘k’. The program loaded in the PC. Interrupts are counter is loaded from the top of enabled by setting Global Interrupt the stack (the return address). Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. This is a two-cycle instruction. Words: 1 Words: 1 Cycles: 2 Cycles: 2 Example: CALL TABLE ;W contains table Example: RETFIE ;offset value (cid:129) ;W now has table After Interrupt TABLE value PC = TOS (cid:129) GIE= 1 (cid:129) ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; (cid:129) (cid:129) (cid:129) RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS → PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Preliminary DS41265A-page 220 © 2005 Microchip Technology Inc.

PIC16F946 RLF Rotate Left f through Carry SLEEP Go into Standby mode Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 Operands: None d ∈ [0,1] Operation: 00h → WDT, Operation: See description below 0 → WDT prescaler, 1 → TO, Status Affected: C 0 → PD Encoding: 00 1101 dfff ffff Status Affected: TO, PD Description: The contents of register ‘f’ are Description: The power-down Status bit, PD is rotated one bit to the left through cleared. Time-out Status bit, TO the Carry Flag. If ‘d’ is ‘0’, the is set. Watchdog Timer and its result is placed in the W register. If prescaler are cleared. ‘d’ is ‘1’, the result is stored back in The processor is put into Sleep register ‘f’. mode with the oscillator stopped. C Register f Words: 1 SUBLW Subtract W from Literal Cycles: 1 Syntax: [ label ] SUBLW k Example: RLF REG1,0 Operands: 0 ≤ k ≤ 255 Before Instruction REG1 = 1110 0110 Operation: k - (W) → (W) C = 0 Status Affected: C, DC, Z After Instruction REG1 = 1110 0110 Description: The W register is subtracted (2’s W = 1100 1100 complement method) from the C = 1 eight-bit literal ‘k’. The result is placed in the W register. RRF Rotate Right f through Carry SUBWF Subtract W from f Syntax: [ label ] RRF f,d Syntax: [ label ] SUBWF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: See description below Operation: (f) - (W) → (destination) Status Affected: C Status Affected: C, DC, Z Description: The contents of register ‘f’ are Description: Subtract (2’s complement method) rotated one bit to the right through W register from register ‘f’. If ‘d’ is the Carry Flag. If ‘d’ is ‘0’, the ‘0’, the result is stored in the W result is placed in the W register. register. If ‘d’ is ‘1’, the result is If ‘d’ is ‘1’, the result is placed stored back in register ‘f’. back in register ‘f’. C Register f Preliminary © 2005 Microchip Technology Inc. DS41265A-page 221

PIC16F946 SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. XORLW Exclusive OR Literal with W Syntax: [ label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. XORWF Exclusive OR W with f Syntax: [ label ] XORWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .XOR. (f) → (destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Preliminary DS41265A-page 222 © 2005 Microchip Technology Inc.

PIC16F946 18.0 DEVELOPMENT SUPPORT 18.1 MPLAB Integrated Development Environment Software The PICmicro® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- (cid:129) Integrated Development Environment controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software based application that contains: (cid:129) Assemblers/Compilers/Linkers (cid:129) An interface to debugging tools - MPASMTM Assembler - simulator - MPLAB C17 and MPLAB C18 C Compilers - programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - emulator (sold separately) - MPLAB C30 C Compiler - in-circuit debugger (sold separately) - MPLAB ASM30 Assembler/Linker/Library (cid:129) A full-featured editor with color coded context (cid:129) Simulators (cid:129) A multiple project manager - MPLAB SIM Software Simulator (cid:129) Customizable data windows with direct edit of contents - MPLAB dsPIC30 Software Simulator (cid:129) High-level source code debugging (cid:129) Emulators (cid:129) Mouse over variable inspection - MPLAB ICE 2000 In-Circuit Emulator (cid:129) Extensive on-line help - MPLAB ICE 4000 In-Circuit Emulator (cid:129) In-Circuit Debugger The MPLAB IDE allows you to: - MPLAB ICD 2 (cid:129) Edit your source files (either assembly or C) (cid:129) Device Programmers (cid:129) One touch assemble (or compile) and download - PRO MATE® II Universal Device Programmer to PICmicro emulator and simulator tools (automatically updates all project information) - PICSTART® Plus Development Programmer (cid:129) Debug using: - MPLAB PM3 Device Programmer - source files (assembly or C) (cid:129) Low-Cost Demonstration Boards - mixed assembly and C - PICDEMTM 1 Demonstration Board - machine code - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective - PICDEM 3 Demonstration Board simulators, through low-cost in-circuit debuggers, to - PICDEM 4 Demonstration Board full-featured emulators. This eliminates the learning - PICDEM 17 Demonstration Board curve when upgrading to tools with increasing flexibility - PICDEM 18R Demonstration Board and power. - PICDEM LIN Demonstration Board 18.2 MPASM Assembler - PICDEM USB Demonstration Board (cid:129) Evaluation Kits The MPASM assembler is a full-featured, universal - KEELOQ® Security ICs macro assembler for all PICmicro MCUs. - PICDEM MSC The MPASM assembler generates relocatable object - microID® RFID files for the MPLINK object linker, Intel® standard hex files, MAP files to detail memory usage and symbol ref- - CAN erence, absolute LST files that contain source lines and - PowerSmart® Battery Management generated machine code and COFF files for - Analog debugging. The MPASM assembler features include: (cid:129) Integration into MPLAB IDE projects (cid:129) User defined macros to streamline assembly code (cid:129) Conditional assembly for multi-purpose source files (cid:129) Directives that allow complete control over the assembly process Preliminary © 2005 Microchip Technology Inc. DS41265A-page 223

PIC16F946 18.3 MPLAB C17 and MPLAB C18 18.6 MPLAB ASM30 Assembler, Linker C Compilers and Librarian The MPLAB C17 and MPLAB C18 Code Development MPLAB ASM30 assembler produces relocatable Systems are complete ANSI C compilers for machine code from symbolic assembly language for Microchip’s PIC17CXXX and PIC18CXXX family of dsPIC30F devices. MPLAB C30 compiler uses the microcontrollers. These compilers provide powerful assembler to produce it’s object file. The assembler integration capabilities, superior code optimization and generates relocatable object files that can then be ease of use not found with other compilers. archived or linked with other relocatable object files and archives to create an executable file. Notable features For easy source level debugging, the compilers provide of the assembler include: symbol information that is optimized to the MPLAB IDE debugger. (cid:129) Support for the entire dsPIC30F instruction set (cid:129) Support for fixed-point and floating-point data 18.4 MPLINK Object Linker/ (cid:129) Command line interface MPLIB Object Librarian (cid:129) Rich directive set The MPLINK object linker combines relocatable (cid:129) Flexible macro language objects created by the MPASM assembler and the (cid:129) MPLAB IDE compatibility MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from precompiled libraries, using 18.7 MPLAB SIM Software Simulator directives from a linker script. The MPLAB SIM software simulator allows code devel- The MPLIB object librarian manages the creation and opment in a PC hosted environment by simulating the modification of library files of precompiled code. When PICmicro series microcontrollers on an instruction a routine from a library is called from a source file, only level. On any given instruction, the data areas can be the modules that contain that routine will be linked in examined or modified and stimuli can be applied from with the application. This allows large libraries to be a file, or user defined key press, to any pin. The execu- used efficiently in many different applications. tion can be performed in Single-Step, Execute Until The object linker/library features include: Break or Trace mode. (cid:129) Efficient linking of single libraries instead of many The MPLAB SIM simulator fully supports symbolic smaller files debugging using the MPLAB C17 and MPLAB C18 (cid:129) Enhanced code maintainability by grouping CCompilers, as well as the MPASM assembler. The related modules together software simulator offers the flexibility to develop and debug code outside of the laboratory environment, (cid:129) Flexible creation of libraries with easy module making it an excellent, economical software listing, replacement, deletion and extraction development tool. 18.5 MPLAB C30 C Compiler 18.8 MPLAB SIM30 Software Simulator The MPLAB C30 C compiler is a full-featured, ANSI The MPLAB SIM30 software simulator allows code compliant, optimizing compiler that translates standard development in a PC hosted environment by simulating ANSI C programs into dsPIC30F assembly language the dsPIC30F series microcontrollers on an instruction source. The compiler also supports many command level. On any given instruction, the data areas can be line options and language extensions to take full examined or modified and stimuli can be applied from advantage of the dsPIC30F device hardware capabili- a file, or user defined key press, to any of the pins. ties and afford fine control of the compiler code generator. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB C30 is distributed with a complete ANSI C MPLAB ASM30 assembler. The simulator runs in either standard library. All library functions have been vali- a Command Line mode for automated tasks, or from dated and conform to the ANSI C library standard. The MPLAB IDE. This high-speed simulator is designed to library includes functions for string manipulation, debug, analyze and optimize time intensive DSP dynamic memory allocation, data conversion, time- routines. keeping and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high-level source debugging with the MPLAB IDE. Preliminary DS41265A-page 224 © 2005 Microchip Technology Inc.

PIC16F946 18.9 MPLAB ICE 2000 18.11 MPLAB ICD 2 In-Circuit Debugger High-Performance Universal Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 universal in-circuit emulator is USB interface. This tool is based on the Flash intended to provide the product development engineer PICmicro MCUs and can be used to develop for these with a complete microcontroller design tool set for and other PICmicro microcontrollers. The MPLAB PICmicro microcontrollers. Software control of the ICD2 utilizes the in-circuit debugging capability built MPLAB ICE 2000 in-circuit emulator is advanced by into the Flash devices. This feature, along with the MPLAB Integrated Development Environment, Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) which allows editing, building, downloading and source protocol, offers cost effective in-circuit Flash debugging debugging from a single environment. from the graphical user interface of the MPLAB The MPLAB ICE 2000 is a full-featured emulator Integrated Development Environment. This enables a system with enhanced trace, trigger and data monitor- designer to develop and debug source code by setting ing features. Interchangeable processor modules allow breakpoints, single-stepping and watching variables, the system to be easily reconfigured for emulation of CPU status and peripheral registers. Running at full different processors. The universal architecture of the speed enables testing hardware and applications in MPLAB ICE in-circuit emulator allows expansion to real-time. MPLAB ICD2 also serves as a development support new PICmicro microcontrollers. programmer for selected PICmicro devices. The MPLAB ICE 2000 in-circuit emulator system has 18.12 PRO MATE II Universal Device been designed as a real-time emulation system with advanced features that are typically found on more Programmer expensive development tools. The PC platform and Microsoft® Windows 32-bit operating system were The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at chosen to best make these features available in a simple, unified application. VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages 18.10 MPLAB ICE 4000 and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the High-Performance Universal PROMATE II device programmer can read, verify and In-Circuit Emulator program PICmicro devices without a PC connection. It The MPLAB ICE 4000 universal in-circuit emulator is can also set code protection in this mode. intended to provide the product development engineer with a complete microcontroller design tool set for 18.13 MPLAB PM3 Device Programmer high-end PICmicro microcontrollers. Software control The MPLAB PM3 is a universal, CE compliant device of the MPLAB ICE in-circuit emulator is provided by the programmer with programmable voltage verification at MPLAB Integrated Development Environment, which VDDMIN and VDDMAX for maximum reliability. It features allows editing, building, downloading and source a large LCD display (128 x 64) for menus and error debugging from a single environment. messages and a modular detachable socket assembly The MPLAB ICD 4000 is a premium emulator system, to support various package types. The ICSP™ cable providing the features of MPLAB ICE 2000, but with assembly is included as a standard item. In increased emulation memory and high-speed perfor- Stand-Alone mode, the MPLAB PM3 device program- mance for dsPIC30F and PIC18XXXX devices. Its mer can read, verify and program PICmicro devices advanced emulator features include complex triggering without a PC connection. It can also set code protection and timing, up to 2 Mb of emulation memory and the in this mode. MPLAB PM3 connects to the host PC via ability to view variables in real-time. an RS-232 or USB cable. MPLAB PM3 has high-speed The MPLAB ICE 4000 in-circuit emulator system has communications and optimized algorithms for quick been designed as a real-time emulation system with programming of large memory devices and incorpo- advanced features that are typically found on more rates an SD/MMC card for file storage and secure data expensive development tools. The PC platform and applications. Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 225

PIC16F946 18.14 PICSTART Plus Development 18.17 PICDEM 2 Plus Programmer Demonstration Board The PICSTART Plus development programmer is an The PICDEM 2 Plus demonstration board supports easy-to-use, low-cost, prototype programmer. It con- many 18, 28 and 40-pin microcontrollers, including nects to the PC via a COM (RS-232) port. MPLAB PIC16F87X and PIC18FXX2 devices. All the neces- Integrated Development Environment software makes sary hardware and software is included to run the dem- using the programmer simple and efficient. The onstration programs. The sample microcontrollers PICSTART Plus development programmer supports provided with the PICDEM 2 demonstration board can most PICmicro devices up to 40 pins. Larger pin count be programmed with a PRO MATE II device program- devices, such as the PIC16C92X and PIC17C76X, mer, PICSTART Plus development programmer, or may be supported with an adapter socket. The MPLAB ICD 2 with a Universal Programmer Adapter. PICSTART Plus development programmer is CE The MPLAB ICD 2 and MPLAB ICE in-circuit emulators compliant. may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the 18.15 PICDEM 1 PICmicro circuitry for additional application components. Some Demonstration Board of the features include an RS-232 interface, a 2x16 LCD display, a piezo speaker, an on-board temperature The PICDEM 1 demonstration board demonstrates the sensor, four LEDs and sample PIC18F452 and capabilities of the PIC16C5X (PIC16C54 to PIC16F877 Flash microcontrollers. PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All 18.18 PICDEM 3 PIC16C92X necessary hardware and software is included to run Demonstration Board basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can The PICDEM 3 demonstration board supports the be programmed with a PRO MATE II device program- PIC16C923 and PIC16C924 in the PLCC package. All mer or a PICSTART Plus development programmer. the necessary hardware and software is included to run The PICDEM 1 demonstration board can be connected the demonstration programs. to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional appli- 18.19 PICDEM 4 8/14/18-Pin cation components. Features include an RS-232 Demonstration Board interface, a potentiometer for simulated analog input, The PICDEM 4 can be used to demonstrate the capa- push button switches and eight LEDs. bilities of the 8, 14 and 18-pin PIC16XXXX and 18.16 PICDEM.net Internet/Ethernet PIC18XXXX MCUs, including the PIC16F818/819, Demonstration Board PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to The PICDEM.net demonstration board is an Inter- showcase the many features of these low pin count net/Ethernet demonstration board using the parts, including LIN and Motor Control using ECCP. PIC18F452 microcontroller and TCP/IP firmware. The Special provisions are made for low-power operation board supports any 40-pin DIP device that conforms to with the supercapacitor circuit and jumpers allow the standard pinout used by the PIC16F877 or on-board hardware to be disabled to eliminate current PIC18C452. This kit features a user friendly TCP/IP draw in this mode. Included on the demo board are pro- stack, web server with HTML, a 24L256 Serial visions for Crystal, RC or Canned Oscillator modes, a EEPROM for Xmodem download to web pages into five volt regulator for use with a nine volt wall adapter Serial EEPROM, ICSP/MPLAB ICD 2 interface con- or battery, DB-9 RS-232 interface, ICD connector for nector, an Ethernet interface, RS-232 interface and a programming via ICSP and development with MPLAB 16 x 2 LCD display. Also included is the book and ICD 2, 2 x 16 liquid crystal display, PCB footprints for CD-ROM “TCP/IP Lean, Web Servers for Embedded H-Bridge motor driver, LIN transceiver and EEPROM. Systems,” by Jeremy Bentham Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a proto- typing area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User’s Guide. Preliminary DS41265A-page 226 © 2005 Microchip Technology Inc.

PIC16F946 18.20 PICDEM 17 Demonstration Board 18.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several The PICDEM USB Demonstration Board shows off the Microchip microcontrollers, including PIC17C752, capabilities of the PIC16C745 and PIC16C765 USB PIC17C756A, PIC17C762 and PIC17C766. A pro- microcontrollers. This board provides the basis for grammed sample is included. The PRO MATE II device future USB products. programmer, or the PICSTART Plus development pro- grammer, can be used to reprogram the device for user 18.25 Evaluation and tailored application development. The PICDEM 17 Programming Tools demonstration board supports program download and execution from external on-board Flash memory. A In addition to the PICDEM series of circuits, Microchip generous prototype area is available for user hardware has a line of evaluation kits and demonstration software expansion. for these products. (cid:129) K EELOQ evaluation and programming tools for 18.21 PICDEM 18R PIC18C601/801 Microchip’s HCS Secure Data Products Demonstration Board (cid:129) CAN developers kit for automotive network The PICDEM 18R demonstration board serves to assist applications development of the PIC18C601/801 family of Microchip (cid:129) Analog design boards and filter design software microcontrollers. It provides hardware implementation (cid:129) PowerSmart battery charging evaluation/ of both 8-bit Multiplexed/Demultiplexed and 16-bit calibration kits Memory modes. The board includes 2 Mb external (cid:129) IrDA ® development kit Flash memory and 128 Kb SRAM memory, as well as (cid:129) microID development and rfLab TM development serial EEPROM, allowing access to the wide range of software memory types supported by the PIC18C601/801. (cid:129) SEEVAL ® designer kit for memory evaluation and 18.22 PICDEM LIN PIC16C43X endurance calculations Demonstration Board (cid:129) PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma The powerful LIN hardware and software kit includes a ADC and flow rate sensor series of boards and three PICmicro microcontrollers. Check the Microchip web page and the latest Product The small footprint PIC16C432 and PIC16C433 are Selector Guide for the complete list of demonstration used as slaves in the LIN communication and feature and evaluation kits. on-board LIN transceivers. A PIC16F874 Flash microcontroller serves as the master. All three micro- controllers are programmed with firmware to provide LIN bus communication. 18.23 PICkitTM 1 Flash Starter Kit A complete “development system in a box”, the PICkit Flash Starter Kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin Flash PIC® microcontrollers. Powered via USB, the board operates under a simple Windows GUI. The PICkit 1 Starter Kit includes the User’s Guide (on CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB® IDE (Integrated Development Environment) software, software and hardware “Tips ‘n Tricks for 8-pin Flash PIC® Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 227

PIC16F946 NOTES: Preliminary DS41265A-page 228 © 2005 Microchip Technology Inc.

PIC16F946 19.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss(2) ...........................................................................................-0.3V to +13.5V Voltage on all other pins with respect to VSS ...........................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)...................................................................................................................................1.0 W Maximum current out of VSS pin.....................................................................................................................300 mA Maximum current into VDD pin........................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)................................................................................................................±20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)..........................................................................................................±20 mA Maximum output current sunk by any I/O pin....................................................................................................25 mA Maximum output current sourced by any I/O pin..............................................................................................25 mA Maximum current sunk by all ports (combined)..............................................................................................200 mA Maximum current sourced by all ports (combined).........................................................................................200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL). 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 Ω should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 229

PIC16F946 FIGURE 19-1: PIC16F946 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 4.5 4.0 VDD (VOLTS) 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20 FREQUENCY (MHZ) Note1: The shaded region indicates the permissible combinations of voltage and frequency. Preliminary DS41265A-page 230 © 2005 Microchip Technology Inc.

PIC16F946 19.1 DC Characteristics: PIC16F946-I (Industrial), PIC16F946-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. VDD Supply Voltage FOSC < = 4 MHz: D001 2.0 — 5.5 V D001C 3.0 — 5.5 V FOSC < = 10 MHz D001D 4.5 — 5.5 V FOSC < = 20 MHz D002 VDR RAM Data Retention 1.5* — — V Device in Sleep mode Voltage(1) D003 VPOR VDD Start Voltage to — VSS — V See Section16.3 “Power-on Reset” for ensure internal Power-on details. Reset signal D004 SVDD VDD Rise Rate to ensure 0.05 — — V/ms See Section16.3 “Power-on Reset” for internal Power-on Reset * details. signal D005 VBOR Brown-out Reset — 2.1 — V * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 231

PIC16F946 19.2 DC Characteristics: PIC16F946-I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D010 Supply Current (IDD)(1, 2) — 8 TBD μA 2.0 FOSC = 32kHz — 11 TBD μA 3.0 LP Oscillator mode — 33 TBD μA 5.0 D011 — 110 TBD μA 2.0 FOSC = 1MHz — 190 TBD μA 3.0 XT Oscillator mode — 330 TBD μA 5.0 D012 — 220 TBD μA 2.0 FOSC = 4MHz — 370 TBD μA 3.0 XT Oscillator mode — 0.6 TBD mA 5.0 D013 — 70 TBD μA 2.0 FOSC = 1MHz — 140 TBD μA 3.0 EC Oscillator mode — 260 TBD μA 5.0 D014 — 180 TBD μA 2.0 FOSC = 4MHz — 320 TBD μA 3.0 EC Oscillator mode — 500 TBD μA 5.0 D015 — 5 TBD μA 2.0 FOSC = 31kHz — 14 TBD μA 3.0 INTOSC mode — 30 TBD mA 5.0 D016 — 340 TBD μA 2.0 FOSC = 4MHz — 500 TBD μA 3.0 INTOSC mode — 0.8 TBD mA 5.0 D017 — 180 TBD μA 2.0 FOSC = 4MHz — 320 TBD μA 3.0 EXTRC mode — 580 TBD μA 5.0 D018 — 2.1 TBD mA 4.5 FOSC = 20MHz — 3.0 TBD mA 5.0 HS Oscillator mode Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. Preliminary DS41265A-page 232 © 2005 Microchip Technology Inc.

PIC16F946 19.2 DC Characteristics: PIC16F946-I (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D020 Power-down Base — 0.1 TBD μA 2.0 WDT, BOR, Comparators, VREF and Current (IPD)(4) — 0.5 TBD μA 3.0 T1OSC disabled — 0.75 TBD μA 5.0 D021 — 0.6 TBD μA 2.0 WDT Current — 1.8 TBD μA 3.0 — 8.4 TBD μA 5.0 D022 — 58 TBD μA 3.0 BOR Current — 75 TBD μA 5.0 D023 — 35 TBD μA 2.0 Comparator Current(3) — 65 TBD μA 3.0 — 130 TBD μA 5.0 D024 — 40 TBD μA 2.0 CVREF Current — 50.5 TBD μA 3.0 — 80 TBD μA 5.0 D025 — 2.1 TBD μA 2.0 T1OSC Current — 2.5 TBD μA 3.0 — 3.4 TBD μA 5.0 D026 — 1.2 TBD nA 3.0 A/D Current — 0.0022 TBD μA 5.0 Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 233

PIC16F946 19.3 DC Characteristics: PIC16F946-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D010E Supply Current (IDD)(1, 2) — 8 TBD μA 2.0 FOSC = 32kHz — 11 TBD μA 3.0 LP Oscillator mode — 33 TBD μA 5.0 D011E — 110 TBD μA 2.0 FOSC = 1MHz — 190 TBD μA 3.0 XT Oscillator mode — 330 TBD μA 5.0 D012E — 220 TBD μA 2.0 FOSC = 4MHz — 370 TBD μA 3.0 XT Oscillator mode — 0.6 TBD mA 5.0 D013E — 70 TBD μA 2.0 FOSC = 1MHz — 140 TBD μA 3.0 EC Oscillator mode — 260 TBD μA 5.0 D014E — 180 TBD μA 2.0 FOSC = 4MHz — 320 TBD μA 3.0 EC Oscillator mode — 500 TBD μA 5.0 D015E — 5 TBD μA 2.0 FOSC = 31kHz — 14 TBD μA 3.0 INTOSC mode — 30 TBD mA 5.0 D016E — 340 TBD μA 2.0 FOSC = 4MHz — 500 TBD μA 3.0 INTOSC mode — 0.8 TBD mA 5.0 D017E — 180 TBD μA 2.0 FOSC = 4MHz — 320 TBD μA 3.0 EXTRC mode — 580 TBD μA 5.0 D018E — 2.1 TBD mA 4.5 FOSC = 20MHz — 3.0 TBD mA 5.0 HS Oscillator mode Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. Preliminary DS41265A-page 234 © 2005 Microchip Technology Inc.

PIC16F946 19.3 DC Characteristics: PIC16F946-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D020E Power-down Base — 0.1 TBD μA 2.0 WDT, BOR, Comparators, VREF Current (IPD)(4) — 0.5 TBD μA 3.0 and T1OSC disabled — 0.75 TBD μA 5.0 D021E — 0.6 TBD μA 2.0 WDT Current — 1.8 TBD μA 3.0 — 8.4 TBD μA 5.0 D022E — 58 TBD μA 3.0 BOR Current — 75 TBD μA 5.0 D023E — 35 TBD μA 2.0 Comparator Current(3) — 65 TBD μA 3.0 — 130 TBD μA 5.0 D024E — 40 TBD μA 2.0 CVREF Current — 50.5 TBD μA 3.0 — 80 TBD μA 5.0 D025E — 2.1 TBD μA 2.0 T1OSC Current — 2.5 TBD μA 3.0 — 3.4 TBD μA 5.0 D026E — 1.2 TBD μA 3.0 A/D Current(3) — 0.0022 TBD μA 5.0 Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 235

PIC16F946 19.4 DC Characteristics: PIC16F946-I (Industrial), PIC16F946-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O port: D030 with TTL buffer VSS — 0.8 V 4.5V ≤ VDD ≤ 5.5V D030A VSS — 0.15 VDD V Otherwise D031 with Schmitt Trigger buffer VSS — 0.2 VDD V Entire range D032 MCLR, OSC1 (RC mode) VSS — 0.2 VDD V D033 OSC1 (XT and LP modes)(1) VSS — 0.3 V D033A OSC1 (HS mode)(1) VSS — 0.3 VDD V D034 I2C™ mode VSS — 0.3VDD V Entire VDD Range VIH Input High Voltage I/O port: — D040 with TTL buffer 2.0 — VDD V 4.5V ≤ VDD ≤ 5.5V D040A (0.25 VDD + — VDD V Otherwise 0.8) D041 with Schmitt Trigger buffer 0.8 VDD — VDD V Entire range D042 MCLR 0.8 VDD — VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V (Note 1) D043A OSC1 (HS mode) 0.7 VDD — VDD V (Note 1) D043B OSC1 (RC mode) 0.9 VDD — VDD V D044 I2C mode 0.7VDD — VDD V Entire VDD Range D070 IPUR PORTB Weak Pull-up Current 50* 250 400* μA VDD = 5.0V, VPIN = VSS IIL Input Leakage Current(2) D060 I/O port — ± 0.1 ± 1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR(3) — ± 0.1 ± 5 μA VSS ≤ VPIN ≤ VDD D063 OSC1 — ± 0.1 ± 5 μA VSS ≤ VPIN ≤ VDD, XT, HS and LP OSC configuration VOL Output Low Voltage D080 I/O port — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.) D083 OSC2/CLKO (RC mode) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V (Ind.) IOL = 1.2 mA, VDD = 4.5V (Ext.) VOH Output High Voltage D090 I/O port VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.) D092 OSC2/CLKO (RC mode) VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V (Ind.) IOH = -1.0 mA, VDD = 4.5V (Ext.) * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Preliminary DS41265A-page 236 © 2005 Microchip Technology Inc.

PIC16F946 19.4 DC Characteristics: PIC16F946-I (Industrial), PIC16F946-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Capacitive Loading Specs on Output Pins D100 COS OSC2 pin — — 15* pF In XT, HS and LP modes C2 when external clock is used to drive OSC1 D101 CIO All I/O pins — — 50* pF Data EEPROM Memory D120 ED Byte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C D120A ED Byte Endurance 10K 100K — E/W +85°C ≤ TA ≤ +125°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON1 to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 5 6 ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifica- tions are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C ≤ TA ≤ +85°C Cycles before Refresh(2) Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C D130A ED Cell Endurance 1K 10K — E/W +85°C ≤ TA ≤ +125°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VPEW VDD for Erase/Write 4.5 — 5.5 V D133 TPEW Erase/Write cycle time — 2 2.5 ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifica- tions are violated * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 237

PIC16F946 19.5 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 19-2: LOAD CONDITIONS Load Condition 1 Load Condition 2 VDD/2 RL PIN CL PIN CL VSS VSS Legend: RL = 464Ω CL = 50 pF for all pins 15 pF for OSC2 output Preliminary DS41265A-page 238 © 2005 Microchip Technology Inc.

PIC16F946 19.6 AC Characteristics: PIC16F946 (Industrial, Extended) FIGURE 19-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 19-1: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. FOSC External CLKI Frequency(1) DC — 37 kHz LP Oscillator mode DC — 4 MHz XT Oscillator mode DC — 20 MHz HS Oscillator mode DC — 20 MHz EC Oscillator mode Oscillator Frequency(1) 5 — 37 kHz LP Oscillator mode — 4 — MHz INTOSC mode DC — 4 MHz RC Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 20 MHz HS Oscillator mode 1 TOSC External CLKI Period(1) 27 — ∞ μs LP Oscillator mode 50 — ∞ Ns HS Oscillator mode 50 — ∞ ns EC Oscillator mode 250 — ∞ ns XT Oscillator mode Oscillator Period(1) 27 200 μs LP Oscillator mode — 250 — ns INTOSC mode 250 — — ns RC Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 2 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC 3 TosL, External CLKI (OSC1) High 2* — — μs LP oscillator, TOSC L/H duty cycle TosH External CLKI Low 20* — — ns HS oscillator, TOSC L/H duty cycle 100 * — — ns XT oscillator, TOSC L/H duty cycle 4 TosR, External CLKI Rise — — 50* ns LP oscillator TosF External CLKI Fall — — 25* ns XT oscillator — — 15* ns HS oscillator * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 239

PIC16F946 TABLE 19-2: PRECISION INTERNAL OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Freq. Sym Characteristic Min Typ† Max Units Conditions No. Tolerance F10 FOSC Internal Calibrated ±1% — 8.00 TBD MHz VDD and Temperature TBD INTOSC Frequency(1) ±2% — 8.00 TBD MHz 2.5V ≤ VDD ≤ 5.5V 0°C ≤ TA ≤ +85°C ±5% — 8.00 TBD MHz 2.0V ≤ VDD ≤ 5.5V -40°C ≤ TA ≤ +85°C (Ind.) -40°C ≤ TA ≤ +125°C (Ext.) F14 TIOSC Oscillator Wake-up from — — TBD TBD μs VDD = 2.0V, -40°C to +85°C ST Sleep Start-up Time* — — TBD TBD μs VDD = 3.0V, -40°C to +85°C — — TBD TBD μs VDD = 5.0V, -40°C to +85°C Legend: TBD = To Be Determined * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended. Preliminary DS41265A-page 240 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 19-4: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 11 10 22 CLKO 23 13 12 19 18 14 16 I/O PIN (Input) 17 15 I/O PIN Old Value New Value (Output) 20, 21 TABLE 19-3: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. 10* TOSH2CKL OSC1↑ to CLOUT↓ — 75 200 ns (Note 1) 11* TOSH2CKH OSC1↑ to CLOUT↑ — 75 200 ns (Note 1) 12* TCKR CLKO Rise Time — 35 100 ns (Note 1) 13* TCKF CLKO Fall Time — 35 100 ns (Note 1) 14* TCKL2IOV CLKO↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15* TIOV2CKH Port In Valid before CLKO↑ TOSC + 200 ns — — ns (Note 1) 16* TCKH2IOI Port In Hold after CLKO↑ 0 — — ns (Note 1) 17* TOSH2IOV OSC1↑ (Q1 cycle) to Port Out Valid — 50 150* ns — — 300 ns 18* TOSH2IOI OSC1↑ (Q2 cycle) to Port 3.0-5.5V 100 — — ns Input Invalid (I/O in hold time) 2.0-5.5V 200 — — ns 19* TIOV2OSH Port Input Valid to OSC1↑ 0 — — ns (I/O in setup time) 20* TIOR Port Output Rise Time 3.0-5.5V — 10 40 ns 2.0-5.5V — — 145 21* TIOF Port Output Fall Time 3.0-5.5V — 10 40 ns 2.0-5.5V — — 145 22* TINP INT Pin High or Low Time 25 — — ns 23* TRBP PORTA change INT High or Low Time TCY — — ns * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKO output is 4 x TOSC. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 241

PIC16F946 FIGURE 19-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins FIGURE 19-6: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD BVDD (Device not in Brown-out Reset) (Device in Brown-out Reset) 35 Reset (due to BOR) 64 MS Time-out(1) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word is programmed to ‘0’. Preliminary DS41265A-page 242 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — μs VDD = 5V, -40°C to +85°C 11 18 24 ms Extended temperature 31 TWDT Watchdog Timer Time-out 10 17 25 ms VDD = 5V, -40°C to +85°C Period (No Prescaler) 10 17 30 ms Extended temperature 32 TOST Oscillation Start-up Timer — 1024 TOSC — — TOSC = OSC1 period Period 33* TPWRT Power-up Timer Period 28* 64 132* ms VDD = 5V, -40°C to +85°C TBD TBD TBD ms Extended Temperature 34 TIOZ I/O High-impedance from — — 2.0 μs MCLR Low or Watchdog Timer Reset BVDD Brown-out Reset Voltage 2.025 — 2.175 V 35 TBOR Brown-out Reset Pulse Width 100* — — μs VDD ≤ BVDD (D005) Legend: TBD = To Be Determined * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 19-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 48 TMR0 or TMR1 Preliminary © 2005 Microchip Technology Inc. DS41265A-page 243

PIC16F946 TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = prescale 20 or TCY + 40 value (2, 4, ..., N 256) 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 3.0-5.5V 15 — — ns with Prescaler 2.0-5.5V 25 — — ns Asynchronous 3.0-5.5V 30 — — ns 2.0-5.5V 50 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 3.0-5.5V 15 — — ns with Prescaler 2.0-5.5V 25 — — ns Asynchronous 3.0-5.5V 30 — — ns 2.0-5.5V 50 — — ns 47* TT1P T1CKI Input Synchronous 3.0-5.5V GREATER OF: — — ns N = prescale Period 30 OR TCY + 40 value (1, 2, 4, 8) N 2.0-5.5V 50 OR TCY + 40 — — ns N Asynchronous 3.0-5.5V 60 — — ns 2.0-5.5V 100 — — ns FT1 Timer1 oscillator input frequency range DC — 37* kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZTMR1 Delay from external clock edge to timer 2 TOSC* — 7 TOSC* — increment * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 19-8: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK SCK/SCL/SEG9 121 121 RC7/RX/DT/ SDI/SDA/SEG8 120 122 Note: Refer to Figure19-2 for load conditions. Preliminary DS41265A-page 244 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 19-6: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param. Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DT SYNC XMIT (Master and Slave) 3.0-5.5V — 80 ns V Clock high to data-out valid 2.0-5.5V — 100 ns 121 TCKRF Clock out rise time and fall time 3.0-5.5V — 45 ns (Master mode) 2.0-5.5V — 50 ns 122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns 2.0-5.5V — 50 ns FIGURE 19-9: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK SCK/SCL/SEG9 125 RC7/RX/DT/ SDI/SDA/SEG8 126 Note: Refer to Figure19-2 for load conditions. TABLE 19-7: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK ↓ (DT hold time) 10 — ns 126 TCKL2DTL Data-hold after CK ↓ (DT hold time) 15 — ns FIGURE 19-10: CAPTURE/COMPARE/PWM TIMINGS CCP1/CCP2 (Capture mode) 50 51 52 CCP1/CCP2 (Compare mode) 53 54 Note:Refer to Figure19-2 for load conditions. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 245

PIC16F946 TABLE 19-8: CAPTURE/COMPARE/PWM REQUIREMENTS Param. Sym Characteristic Min Typ† Max Units Conditions No. 50* TCCL CCP1 No Prescaler 0.5TCY + 5 — — ns input low time With Prescaler 3.0-5.5V 10 — — ns 2.0-5.5V 20 — — ns 51* TCCH CCP1 No Prescaler 0.5TCY + 5 — — ns input high time With Prescaler 3.0-5.5V 10 — — ns 2.0-5.5V 20 — — ns 52* TCCP CCP1 input period 3TCY + 40 — — ns N = prescale N value (1,4 or 16) 53* TCCR CCP1 output fall time 3.0-5.5V — 10 25 ns 2.0-5.5V — 25 50 ns 54* TCCF CCP1 output fall time 3.0-5.5V — 10 25 ns 2.0-5.5V — 25 45 ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 19-9: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Comparator Specifications Operating temperature -40°C ≤ TA ≤ +125°C Sym Characteristics Min Typ Max Units Comments VOS Input Offset Voltage — ±5.0 ±10 mV VCM Input Common Mode Voltage 0 — VDD – 1.5 V CMRR Common Mode Rejection Ratio +55* — — db TRT Response Time(1) — 150 400* ns TMC2COV Comparator Mode Change to — — 10* μs Output Valid * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from VSS to VDD – 1.5V. TABLE 19-10: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Voltage Reference Specifications Operating temperature -40°C ≤ TA ≤ +125°C Sym. Characteristics Min Typ Max Units Comments Resolution — VDD/24* — LSb Low Range (VRR = 1) — VDD/32 — LSb High Range (VRR = 0) Absolute Accuracy — — ±1/4* LSb Low Range (VRR = 1) — — ±1/2* LSb High Range (VRR = 0) Unit Resistor Value (R) — 2K* — Ω Settling Time(1) — — 10* μs * These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. Preliminary DS41265A-page 246 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 19-11: PIC16F946 PLVD CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +125°C Operating Voltage VDD Range 2.0V-5.5V Sym. Characteristic Min Typ† Max Units Conditions VPLVD PLVD LVDL<2:0> = 000 TBD 1.9 TBD V Voltage TBD TBD 2.0 TBD V TBD TBD 2.1 TBD V TBD TBD 2.2 TBD V TBD TBD 2.3 TBD V TBD TBD 4.0 TBD V TBD TBD 4.2 TBD V TBD TBD 4.5 TBD V Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 247

PIC16F946 FIGURE 19-11: SPI™ MASTER MODE TIMING (CKE=0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure19-2 for load conditions. FIGURE 19-12: SPI™ MASTER MODE TIMING (CKE=1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure19-2 for load conditions. Preliminary DS41265A-page 248 © 2005 Microchip Technology Inc.

PIC16F946 FIGURE 19-13: SPI™ SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure19-2 for load conditions. FIGURE 19-14: SPI™ SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure19-2 for load conditions. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 249

PIC16F946 TABLE 19-12: SPI™ MODE REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 70* TSSL2SCH, SS↓ to SCK↓ or SCK↑ input TCY — — ns TSSL2SCL 71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns 72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns 73* TDIV2SCH, Setup time of SDI data input to SCK edge 100 — — ns TDIV2SCL 74* TSCH2DIL, Hold time of SDI data input to SCK edge 100 — — ns TSCL2DIL 75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns 2.0-5.5V — 25 50 ns 76* TDOF SDO data output fall time — 10 25 ns 77* TSSH2DOZ SS↑ to SDO output high-impedance 10 — 50 ns 78* TSCR SCK output rise time 3.0-5.5V — 10 25 ns (Master mode) 2.0-5.5V — 25 50 ns 79* TSCF SCK output fall time (Master mode) — 10 25 ns 80* TSCH2DOV, SDO data output valid after 3.0-5.5V — — 50 ns TSCL2DOV SCK edge 2.0-5.5V — — 145 ns 81* TDOV2SCH, SDO data output setup to SCK edge TCY — — ns TDOV2SCL 82* TSSL2DOV SDO data output valid after SS↓ edge — — 50 ns 83* TSCH2SSH, SS ↑ after SCK edge 1.5TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 19-15: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure19-2 for load conditions. Preliminary DS41265A-page 250 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 19-13: I2C™ BUS START/STOP BITS REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — Start condition 91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first Hold time 400 kHz mode 600 — — clock pulse is generated 92* TSU:STO Stop condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO Stop condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. FIGURE 19-16: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure19-2 for load conditions. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 251

PIC16F946 TABLE 19-14: I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100* THIGH Clock high time 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz SSP Module 1.5TCY — 101* TLOW Clock low time 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz SSP Module 1.5TCY — 102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF 103* TF SDA and SCL fall 100 kHz mode — 300 ns time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF 90* TSU:STA Start condition 100 kHz mode 4.7 — μs Only relevant for setup time 400 kHz mode 0.6 — μs Repeated Start condition 91* THD:STA Start condition hold 100 kHz mode 4.0 — μs After this period the first time 400 kHz mode 0.6 — μs clock pulse is generated 106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs 107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2) time 400 kHz mode 100 — ns 92* TSU:STO Stop condition 100 kHz mode 4.7 — μs setup time 400 kHz mode 0.6 — μs 109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns 110* TBUF Bus free time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission can start CB Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT=1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. Preliminary DS41265A-page 252 © 2005 Microchip Technology Inc.

PIC16F946 TABLE 19-15: PIC16F946 A/D CONVERTER CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 10 bits bits A03 EIL Integral Error — — <±1 LSb VREF = 5.0V A04 EDL Differential Error — — <±1 LSb No missing codes to 10 bits VREF = 5.0V A06 EOFF Offset Error — — <±1 LSb VREF = 5.0V A07 EGN Gain Error — — <±1 LSb VREF = 5.0V A10 — Monotonicity — assured(1) — — VSS ≤ VAIN ≤ VREF+ A20 VREF Reference Voltage 2.5 — VDD V Full 10-bit accuracy (VREF+ – VREF-) A21 VREF+ Reference Voltage High VDD – 2.5V — VDD + 0.3V V A22 VREF- Reference Voltage Low VSS – 0.3V — VREF+ -2V V A25 VAIN Analog Input Voltage VSS – 0.3V — VREF+ +0.3V V A30 ZAIN Recommended Imped- — — 10 kΩ ance of Analog Voltage Source A50 IREF VREF Input Current (2) — — ±5 μA During VAIN acquisition. ±150 μA During A/D conversion cycle. * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREF+ current is from RA3/AN3/C1+/VREF+/SEG15 pin or VDD, whichever is selected as the VREF+ source. VREF- current is from RA2/AN2/C2+/VREF-/COM2 pin or VSS, whichever is selected as the VREF- source. FIGURE 19-17: PIC16F946 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 134 (TOSC/2)(1) 1 TCY 131 Q4 130 A/D CLK A/D DATA 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE SAMPLING STOPPED SAMPLE 132 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 253

PIC16F946 TABLE 19-16: PIC16F946 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D Clock Period(2) 1.6 — — μs TOSC-based, VREF ≥ 3.0V 3.0* — — μs TOSC-based, VREF full range 130 TAD A/D Internal RC ADCS<1:0> = 11 (RC mode) Oscillator Period 3.0* 6.0 9.0* μs At VDD = 2.5V 2.0* 4.0 6.0* μs At VDD = 5.0V 131 TCNV Conversion Time — 11 — TAD Set GO/DONE bit to new data in A/D (not including Result register Acquisition Time)(1) 132 TACQ Acquisition Time 11.5 — μs 5* — — μs The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 4.1mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). 134 TGO Q4 to A/D Clock — TOSC/2 — — If the A/D clock source is selected as Start RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Table12-1 for minimum conditions. Preliminary DS41265A-page 254 © 2005 Microchip Technology Inc.

PIC16F946 20.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs are not available at this time. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 255

PIC16F946 NOTES: Preliminary DS41265A-page 256 © 2005 Microchip Technology Inc.

PIC16F946 21.0 PACKAGING INFORMATION 21.1 Package Marking Information 64-Lead TQFP (10x10x1mm) Example XXXXXXXXXX PICXXFXXXX XXXXXXXXXX -I/PT XXXXXXXXXX 0410017 YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PICmicro® device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 257

PIC16F946 21.2 Package Details The following sections give the technical details of the packages. 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45° α A c L φ A2 β A1 (F) Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 64 64 Pitch p .020 0.50 Pins per Side n1 16 16 Overall Height A .039 .043 .047 1.00 1.10 1.20 Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05 Standoff A1 .002 .006 .010 0.05 0.15 0.25 Foot Length L .018 .024 .030 0.45 0.60 0.75 Footprint (Reference) (F) .039 1.00 Foot Angle φ 0 3.5 7 0 3.5 7 Overall Width E .463 .472 .482 11.75 12.00 12.25 Overall Length D .463 .472 .482 11.75 12.00 12.25 Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10 Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10 Lead Thickness c .005 .007 .009 0.13 0.18 0.23 Lead Width B .007 .009 .011 0.17 0.22 0.27 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 *Controlling Parameter Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-085 Preliminary DS41265A-page 258 © 2005 Microchip Technology Inc.

PIC16F946 APPENDIX A: DATA SHEET APPENDIX B: MIGRATING FROM REVISION HISTORY OTHER PICmicro® DEVICES Revision A This discusses some of the issues in migrating from This is a new data sheet. other PICmicro devices to the PIC16F946 family of devices. This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its con- formance with these parameters. Due to process differ- ences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. B.1 PIC16F917 to PIC16F946 TABLE B-1: FEATURE COMPARISON Feature PIC16F917 PIC16F946 Max Operating Speed 20MHz 20MHz Max Program Memory 8K 8K (Words) I/O 35 53 LCD Segment Drivers 24 42 Max SRAM (Bytes) 352 336 A/D Resolution 10-bit 10-bit Data EEPROM (bytes) 256 256 Timers (8/16-bit) 2/1 2/1 Oscillator Modes 8 8 Brown-out Reset Y Y Internal Pull-ups RB<7:0> RB<7:0> Interrupt-on-change RB<7:4> RB<7:4> Comparator 2 2 USART Y Y Extended WDT Y Y Software Control Y Y Option of WDT/BOR INTOSC Frequencies 32kHz - 32kHz - 8MHz 8MHz Clock Switching Y Y Preliminary © 2005 Microchip Technology Inc. DS41265A-page 259

PIC16F946 APPENDIX C: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in TableC-1. TABLE C-1: CONVERSION CONSIDERATIONS Characteristic PIC16F946 PIC16F926 PIC18F6490 Pins 64 64 64 Timers 3 3 4 Interrupts 20 9 22 Communication USART, SSP SSP USART, SSP (SPI™, I2C™ Slave) (SPI, I2C Master/Slave) (SPI, I2C Master/Slave) Frequency 20 MHz 20 MHz 20 MHz Voltage 2.0V-5.5V 2.5V-5.5V 2.0V-5.5V A/D 10-bit, 10-bit, 10-bit, 7 conversion clock selects 4 conversion clock selects 8 conversion clock selects CCP 2 1 2 Comparator 2 — 2 Comparator Voltage Yes — Yes Reference Program Memory 8K Flash 8K OTP 8K Flash RAM 332 bytes 336 bytes 768 bytes EEPROM Data 256 bytes — — Code Protection On/Off Segmented, starting at end On/Off of program memory Program Memory — — — Write Protection LCD Module 42 segment drivers, 32 segment drivers, 32 segment drivers, 4 commons 4 commons 4 commons Other In-Circuit Debugger — In-Circuit Debugger Preliminary DS41265A-page 260 © 2005 Microchip Technology Inc.

PIC16F946 INDEX A PWM Mode...............................................................187 RA0 Pin......................................................................29 A/D RA1 Pin......................................................................30 Acquisition Requirements.........................................155 RA2 Pin......................................................................31 Analog Port Pins.......................................................150 RA3 Pin......................................................................32 Associated Registers................................................157 RA4 Pin......................................................................33 Block Diagram...........................................................149 RA5 Pin......................................................................34 Calculating Acquisition Time.....................................155 RA6 Pin......................................................................35 Channel Selection.....................................................150 RA7 Pin......................................................................36 Configuration and Operation.....................................150 RB Pins.......................................................................41 Configuring................................................................154 RB4 Pin......................................................................42 Configuring Interrupt.................................................154 RB5 Pin......................................................................43 Conversion (TAD) Cycles..........................................151 RB6 Pin......................................................................44 Conversion Clock......................................................150 RB7 Pin......................................................................45 Effects of Reset.........................................................157 RC0 Pin......................................................................48 Internal Sampling Switch (RSS) Impedance..............155 RC1 Pin......................................................................49 Operation During Sleep............................................156 RC2 Pin......................................................................49 Output Format...........................................................151 RC3 Pin......................................................................50 Reference Voltage (VREF).........................................150 RC4 Pin......................................................................51 Source Impedance....................................................155 RC5 Pin......................................................................52 Specifications............................................................254 RC6 Pin......................................................................53 Starting a Conversion...............................................151 RC7 Pin......................................................................54 TAD vs. Operating Frequencies.................................150 RD Pins......................................................................59 Absolute Maximum Ratings..............................................229 RD0 Pin......................................................................58 AC Characteristics RD1 Pin......................................................................58 Industrial and Extended............................................239 RD2 Pin......................................................................59 Load Conditions........................................................238 RE Pins.......................................................................63 ACK pulse.........................................................................175 Resonator Operation..................................................76 ADCON0 Register.............................................................152 RF Pins.......................................................................67 ADCON1 Register.............................................................153 RG Pins......................................................................70 Addressable Universal Synchronous Asynchronous Receiver SSP (I2C Mode)........................................................175 Transmitter. See USART SSP (SPI Mode).......................................................168 Analog Input Connections...................................................96 System Clock..............................................................71 Analog-to-Digital Converter Module. See A/D Timer1........................................................................87 ANSEL Register................................................................152 Timer2........................................................................94 Assembler TMR0/WDT Prescaler................................................83 MPASM Assembler...................................................223 USART Receive...............................................141, 142 Asynchronous Reception USART Transmit......................................................138 Associated Registers........................................141, 143 Watchdog Timer (WDT)............................................206 Asynchronous Transmission BRGH bit..........................................................................135 Associated Registers................................................139 Brown-out Reset (BOR)....................................................195 B Associated Registers................................................196 Baud Rate Generator Specifications...........................................................243 Associated Registers................................................135 Timing and Characteristics.......................................242 BF bit.................................................................................166 C Block Diagram of RF...........................................................67 C Compilers Block Diagrams MPLAB C17..............................................................224 A/D............................................................................149 MPLAB C18..............................................................224 Analog Input Model.............................................96, 156 MPLAB C30..............................................................224 Capture Mode...........................................................185 Capture/Compare/PWM (CCP)........................................183 Comparator 1..............................................................98 Associated Registers Comparator 2..............................................................98 Capture, Compare and Timer1.........................188 Comparator Modes.....................................................97 PWM and Timer2..............................................189 Comparator Voltage Reference (CVREF)..................100 Capture Mode...........................................................185 Compare Mode.........................................................186 Block Diagram..................................................185 Fail-Safe Clock Monitor (FSCM).................................81 CCP1CON Register..........................................184 In-Circuit Serial Programming Connections..............210 CCP1IF.............................................................185 Interrupt Logic...........................................................203 Prescaler..........................................................185 LCD Clock Generation..............................................110 CCP Timer Resources..............................................183 LCD Driver Module...................................................104 Compare LCD Resistor Ladder Connection.............................108 Special Trigger Output of CCP1.......................186 MCLR Circuit.............................................................194 Special Trigger Output of CCP2.......................186 On-Chip Reset Circuit...............................................193 Compare Mode.........................................................186 PIC16F946....................................................................6 Preliminary © 2005 Microchip Technology Inc. DS41265A-page 261

PIC16F946 Block Diagram...................................................186 Customer Change Notification Service.............................269 Software Interrupt Mode...................................186 Customer Notification Service..........................................269 Special Event Trigger........................................186 Customer Support.............................................................269 Interaction of Two CCP Modules (table)...................183 D PWM Mode...............................................................186 Block Diagram...................................................187 D/A bit...............................................................................166 Duty Cycle.........................................................187 Data EEPROM Memory....................................................159 Example Frequencies/Resolutions (Table).......188 Associated Registers................................................164 PWM Period......................................................187 Reading....................................................................162 Special Event Trigger and A/D Conversions.............186 Writing......................................................................162 CCP. See Capture/Compare/PWM Data Memory......................................................................11 CCP1CON Register....................................................60, 184 Data/Address bit (D/A)......................................................166 CCPR1H Register.............................................................183 DC Characteristics CCPR1L Register..............................................................183 Extended and Industrial............................................236 CCPxM0 bit.......................................................................184 Industrial and Extended............................................231 CCPxM1 bit.......................................................................184 Demonstration Boards CCPxM2 bit.......................................................................184 PICDEM 1.................................................................226 CCPxM3 bit.......................................................................184 PICDEM 17...............................................................227 CCPxX bit..........................................................................184 PICDEM 18R............................................................227 CCPxY bit..........................................................................184 PICDEM 2 Plus.........................................................226 CKE bit..............................................................................166 PICDEM 3.................................................................226 CKP bit..............................................................................167 PICDEM 4.................................................................226 CMCON0 Register..............................................................95 PICDEM LIN.............................................................227 CMCON1 Register..............................................................99 PICDEM USB...........................................................227 Code Examples PICDEM.net Internet/Ethernet..................................226 A/D Conversion.........................................................154 Development Support.......................................................223 Assigning Prescaler to Timer0....................................85 Device Overview...................................................................5 Assigning Prescaler to WDT.......................................85 E Call of a Subroutine in Page 1 from Page 0................25 Indirect Addressing.....................................................26 EEADRH Registers...................................................159, 160 Initializing PORTA.......................................................27 EEADRL Registers...................................................159, 160 Initializing PORTB.......................................................37 EECON1 Register.....................................................159, 161 Initializing PORTC.......................................................47 EECON2 Register.............................................................159 Initializing PORTD.......................................................56 EEDATH Register.............................................................160 Initializing PORTE.......................................................61 EEDATL Register.............................................................160 Initializing PORTF.......................................................65 Electrical Specifications....................................................229 Initializing PORTG......................................................68 Enhanced Capture/Compare/PWM (ECCP) Loading the SSPBUF (SSPSR) Register..................169 Enhanced PWM Mode Saving Status and W Registers in RAM...................205 TMR2 to PR2 Match...........................................93 Code Protection................................................................210 Errata....................................................................................3 Comparator Module............................................................95 Evaluation and Programming Tools..................................227 Comparator Voltage Reference (CVREF) F Associated Registers................................................102 Effects of a Reset......................................................101 Fail-Safe Clock Monitor......................................................81 Response Time.........................................................101 Fail-Safe Condition Clearing.......................................82 Comparator Voltage Reference (CVREF)..........................100 Reset and Wake-up from Sleep..................................82 Accuracy/Error..........................................................100 Firmware Instructions.......................................................213 Configuring................................................................100 Flash Program Memory....................................................159 Specifications............................................................246 Fuses. See Configuration Bits Comparators G Associated Registers................................................102 General Purpose Register File...........................................11 C2OUT as T1 Gate...............................................88, 99 Configurations.............................................................97 I Effects of a Reset......................................................101 I/O Ports..............................................................................27 Interrupts.....................................................................99 I2C Mode Operation....................................................................96 Addressing................................................................176 Operation During Sleep............................................101 Associated Registers................................................182 Outputs.......................................................................99 Master Mode.............................................................181 Response Time.........................................................101 Mode Selection.........................................................175 Specifications............................................................246 Multi-Master Mode....................................................181 Synchronizing C2OUT w/ Timer1...............................99 Operation..................................................................175 CONFIG Register..............................................................192 Reception.................................................................177 Configuration Bits..............................................................192 Slave Mode Conversion Considerations...............................................260 SCL and SDA pins............................................175 CPU Features...................................................................191 Transmission............................................................179 Preliminary DS41265A-page 262 © 2005 Microchip Technology Inc.

PIC16F946 ID Locations......................................................................210 L In-Circuit Debugger...........................................................211 LCD In-Circuit Serial Programming (ICSP)...............................210 Associated Registers................................................128 Indirect Addressing, INDF and FSR Registers...................26 Bias Types................................................................108 Instruction Format.............................................................214 Clock Source Selection............................................108 Instruction Set...................................................................213 Configuring the Module............................................127 ADDLW.....................................................................216 Frame Frequency.....................................................109 ADDWF.....................................................................216 Interrupts..................................................................124 ANDLW.....................................................................216 LCDCON Register....................................................103 ANDWF.....................................................................216 LCDDATA Register..................................................103 BCF...........................................................................216 LCDPS Register.......................................................103 BSF...........................................................................216 LCDSE Register.......................................................103 BTFSC......................................................................217 Multiplex Types.........................................................109 BTFSS......................................................................216 Operation During Sleep............................................125 CALL.........................................................................217 Pixel Control.............................................................109 CLRF.........................................................................217 Prescaler..................................................................108 CLRW.......................................................................217 Segment Enables.....................................................109 CLRWDT...................................................................217 Waveform Generation..............................................113 COMF.......................................................................217 LCDCON Register............................................................103 DECF........................................................................217 LCDDATA Register...........................................................103 DECFSZ....................................................................218 LCDPS Register...............................................................103 GOTO.......................................................................218 LP Bits......................................................................108 INCF..........................................................................218 LCDSE Register...............................................................103 INCFSZ.....................................................................218 Liquid Crystal Display (LCD) Driver..................................103 IORLW......................................................................218 Load Conditions................................................................238 IORWF......................................................................218 MOVF........................................................................219 M MOVLW....................................................................219 MCLR...............................................................................194 MOVWF....................................................................219 Internal......................................................................194 NOP..........................................................................219 Memory Organization.........................................................11 RETFIE.....................................................................220 Data............................................................................11 RETLW.....................................................................220 Program......................................................................11 RETURN...................................................................220 Microchip Internet Web Site..............................................269 RLF...........................................................................221 Migrating from other PICmicro Devices............................259 RRF...........................................................................221 MPLAB ASM30 Assembler, Linker, Librarian...................224 SLEEP......................................................................221 MPLAB ICD 2 In-Circuit Debugger...................................225 SUBLW.....................................................................221 MPLAB ICE 2000 High-Performance Universal SUBWF.....................................................................221 In-Circuit Emulator....................................................225 SWAPF.....................................................................222 MPLAB ICE 4000 High-Performance Universal XORLW.....................................................................222 In-Circuit Emulator....................................................225 XORWF.....................................................................222 MPLAB Integrated Development Environment Software..223 Summary Table.........................................................215 MPLAB PM3 Device Programmer....................................225 INTCON Register................................................................19 MPLINK Object Linker/MPLIB Object Librarian................224 Inter-Integrated Circuit (I2C). See I2C Mode Internal Oscillator Block O INTOSC OPCODE Field Descriptions.............................................213 Specifications....................................................240 OPTION_REG Register................................................18, 84 Internal Sampling Switch (Rss) Impedance......................155 OSCCON Register..............................................................72 Internet Address................................................................269 Oscillator Interrupt Sources Associated Registers..................................................82 USART Receive/Transmit Complete........................133 Oscillator Configurations.....................................................71 Interrupts...........................................................................202 Oscillator Delay Examples..........................................74 A/D............................................................................154 Special Cases.............................................................73 Associated Registers................................................204 Oscillator Specifications....................................................239 Comparators...............................................................99 Oscillator Start-up Timer (OST) Context Saving..........................................................205 Specifications...........................................................243 Interrupt-on-change....................................................37 Oscillator Switching PORTB Interrupt-on-Change....................................203 Fail-Safe Clock Monitor..............................................81 RB0/INT/SEG0..........................................................203 Two-Speed Clock Start-up.........................................80 TMR0........................................................................203 OSCTUNE Register............................................................78 TMR1..........................................................................88 P TMR2 to PR2 Match...................................................94 TMR2 to PR2 Match (PWM).......................................93 P (Stop) bit........................................................................166 INTOSC Specifications.....................................................240 Packaging.........................................................................257 IOCB Register.....................................................................38 Marking.....................................................................257 PDIP Details.............................................................258 Preliminary © 2005 Microchip Technology Inc. DS41265A-page 263

PIC16F946 Paging, Program Memory...................................................25 RD0............................................................................57 PCL and PCLATH...............................................................25 RD1............................................................................57 Computed GOTO........................................................25 RD2............................................................................57 Stack...........................................................................25 RD3............................................................................57 PCON Register.................................................................196 RD4............................................................................57 PICkit 1 Flash Starter Kit...................................................227 RD5............................................................................57 PICSTART Plus Development Programmer.....................226 RD6............................................................................57 PIE1 Register......................................................................20 RD7............................................................................57 PIE2 Register......................................................................21 Registers....................................................................56 Pin Diagram PORTD Register.................................................................56 PIC16F946, 64-Pin.......................................................2 PORTE Pinout Description.................................................................7 Associated Registers..................................................64 PIR1 Register......................................................................22 Pin Descriptions and Diagrams..................................62 PIR2 Register......................................................................23 RE0.............................................................................62 PORTA RE1.............................................................................62 Associated Registers..................................................36 RE2.............................................................................62 Pin Descriptions and Diagrams...................................29 RE3.............................................................................62 RA0.............................................................................29 RE4.............................................................................62 RA1.............................................................................30 RE5.............................................................................62 RA2.............................................................................31 RE6.............................................................................62 RA3.............................................................................32 RE7.............................................................................62 RA4.............................................................................33 Registers....................................................................61 RA5.............................................................................34 PORTE Register.................................................................61 RA6.............................................................................35 PORTF RA7.............................................................................36 Associated Registers..................................................67 Registers.....................................................................27 Pin Descriptions and Diagrams..................................66 Specifications............................................................241 Registers....................................................................65 PORTA Register.................................................................28 RF0.............................................................................66 PORTB RF1.............................................................................66 Additional Pin Functions.............................................37 RF2.............................................................................66 Weak Pull-up.......................................................37 RF3.............................................................................66 Associated Registers..................................................46 RF4.............................................................................66 Interrupt-on-change....................................................37 RF5.............................................................................66 Pin Descriptions and Diagrams...................................40 RF6.............................................................................66 RB0.............................................................................40 RF7.............................................................................66 RB1.............................................................................40 PORTF Register.................................................................65 RB2.............................................................................40 PORTG RB3.............................................................................40 Associated Registers..................................................70 RB4.............................................................................42 Pin Descriptions and Diagrams..................................69 RB5.............................................................................43 Registers....................................................................68 RB6.............................................................................44 RG0............................................................................69 RB7.............................................................................45 RG1............................................................................69 Registers.....................................................................37 RG2............................................................................69 PORTB Register.................................................................38 RG3............................................................................69 PORTC RG4............................................................................69 Associated Registers..................................................55 RG5............................................................................69 Pin Descriptions and Diagrams...................................48 PORTG Register.................................................................68 RC0.............................................................................48 Power-Down Mode (Sleep)...............................................208 RC1.............................................................................48 Power-on Reset................................................................194 RC2.............................................................................48 Power-up Timer (PWRT)..................................................194 RC3.............................................................................50 Specifications...........................................................243 RC4.............................................................................51 Precision Internal Oscillator Parameters..........................240 RC5.............................................................................52 Prescaler RC6.............................................................................53 Shared WDT/Timer0...................................................85 RC6/TX/CK/SCK/SCL/SEG9 Pin..............................134 Switching Prescaler Assignment................................85 RC7.............................................................................54 PRO MATE II Universal Device Programmer...................225 RC7/RX/DT Pin.........................................................135 Product Identification System...........................................271 RC7/RX/DT/SDI/SDA/SEG8 Pin...............................134 Program Memory................................................................11 Registers.....................................................................47 Map and Stack (PIC16F946)......................................11 Specifications............................................................241 Paging........................................................................25 TRISC Register.........................................................133 Programmable Low-Voltage Detect (PLVD) Module........131 PORTC Register.................................................................47 Programming, Device Instructions....................................213 PORTD Pulse-Width Modulation.See Capture/Compare/PWM, PWM Associated Registers..................................................60 Mode. Pin Descriptions and Diagrams...................................57 Preliminary DS41265A-page 264 © 2005 Microchip Technology Inc.

PIC16F946 R TRISB (PORTB Tri-state)...........................................38 TRISC (PORTC Tri-state)...........................................47 R/W bit..............................................................................166 TRISD (PORTD Tri-state)...........................................56 RCSTA Register TRISE (PORTE Tri-state)...........................................61 ADDEN Bit................................................................134 TRISF (PORTF Tri-state)...........................................65 CREN Bit...................................................................134 TRISG (PORTG Tri-state)..........................................68 FERR Bit...................................................................134 TXSTA (Transmit Status and Control)......................133 OERR Bit..................................................................134 VRCON (Voltage Reference Control).......................102 RX9 Bit......................................................................134 WDTCON (Watchdog Timer Control).......................207 RX9D Bit...................................................................134 WPUB (Weak Pull-up PORTB)...................................39 SPEN Bit...........................................................133, 134 Reset................................................................................193 SREN Bit...................................................................134 Revision History................................................................259 Reader Response.............................................................270 Read-Modify-Write Operations.........................................213 S Receive Overflow Indicator bit (SSPOV)..........................167 S (Start) bit.......................................................................166 Registers SCI. See USART ADCON0 (A/D Control 0)..........................................152 Serial Communication Interface. See USART. ADCON1 (A/D Control 1)..........................................153 Slave Select Synchronization...........................................172 ANSEL (Analog Select).............................................152 SMP bit.............................................................................166 CCP1CON (CCP Control 2)......................................184 Software Simulator (MPLAB SIM)....................................224 CCP2CON (CCP Control 1)......................................184 Software Simulator (MPLAB SIM30)................................224 CMCON0 (Comparator Control 0)..............................95 Special Function Registers.................................................11 CMCON1 (Comparator Control 1)..............................99 SPI Mode..................................................................165, 172 CONFIG (Configuration Word)..................................192 Associated Registers................................................174 EEADRH (EEPROM Address)..................................160 Bus Mode Compatibility............................................174 EEADRL (EEPROM Address)..................................160 Effects of a Reset.....................................................174 EECON1 (EEPROM Control 1).................................161 Enabling SPI I/O.......................................................170 EEDATH (EEPROM Data)........................................160 Master Mode.............................................................171 EEDATL (EEPROM Data)........................................160 Master/Slave Connection.........................................170 INTCON (Interrupt Control).........................................19 Serial Clock (SCK pin)..............................................165 IOCB (PORTB Interrupt-on-change)...........................38 Serial Data In (SDI pin).............................................165 LCDCON (LCD Control)............................................105 Serial Data Out (SDO pin)........................................165 LCDDATAx (LCD Datax)..........................................107 Slave Select..............................................................165 LCDPS (LCD Prescaler Select)................................106 Slave Select Synchronization...................................172 LCDSEn (LCD Segment)..........................................107 Sleep Operation........................................................174 LVDCON (Low-Voltage Detect Control)....................131 SPI Clock..................................................................171 OPTION_REG......................................................18, 84 Typical Connection...................................................170 OSCCON (Oscillator Control).....................................72 SSP OSCTUNE..................................................................78 Overview PCON (Power Control).............................................196 SPI Master/Slave Connection...................................170 PIE1 (Peripheral Interrupt Enable 1)...........................20 SSP I2C Operation...........................................................175 PIE2 (Peripheral Interrupt Enable 2)...........................21 Slave Mode...............................................................175 PIR1 (Peripheral Interrupt Register 1)........................22 SSP Module PIR2 (Peripheral Interrupt Register 2)........................23 Clock Synchronization and the CKP Bit...................181 PORTA........................................................................28 SPI Master Mode......................................................171 PORTB........................................................................38 SPI Slave Mode........................................................172 PORTC.......................................................................47 SSPBUF...................................................................171 PORTD.......................................................................56 SSPSR.....................................................................171 PORTE........................................................................61 SSPEN bit.........................................................................167 PORTF........................................................................65 SSPM bits.........................................................................167 PORTG.......................................................................68 SSPOV bit........................................................................167 RCSTA (Receive Status and Control).......................134 Status Register...................................................................17 Reset Values.............................................................198 Synchronous Master Reception Reset Values (Special Registers).............................201 Associated Registers................................................146 Special Function Register Map Synchronous Master Transmission PIC16F946..........................................................12 Associated Registers................................................145 Special Register Summary Synchronous Serial Port Enable bit (SSPEN)..................167 Bank 0.................................................................13 Synchronous Serial Port Mode Select bits (SSPM)..........167 Bank 1.................................................................14 Synchronous Serial Port. See SSP Bank 2.................................................................15 Synchronous Slave Reception Bank 3.................................................................16 Associated Registers................................................148 SSPCON (Sync Serial Port Control) Register...........167 Synchronous Slave Transmission SSPSTAT (Sync Serial Port Status) Register...........166 Associated Registers................................................148 Status..........................................................................17 T1CON (Timer1 Control).............................................89 T2CON (Timer2 Control).............................................93 TRISA (PORTA Tri-state)...........................................28 Preliminary © 2005 Microchip Technology Inc. DS41265A-page 265

PIC16F946 T SPI Master Mode (CKE = 1, SMP = 1).....................248 SPI Mode (Master Mode)..........................................171 T1CON Register..................................................................89 SPI Mode (Slave Mode with CKE = 0)......................173 Time-out Sequence...........................................................196 SPI Mode (Slave Mode with CKE = 1)......................173 Timer0 SPI Slave Mode (CKE = 0).......................................249 Associated Registers..................................................85 SPI Slave Mode (CKE = 1).......................................249 External Clock.............................................................84 Synchronous Reception (Master Mode, SREN).......147 External Clock Requirements...................................244 Synchronous Transmission......................................145 Interrupt.......................................................................83 Synchronous Transmission (Through TXEN)...........145 Operation....................................................................83 Time-out Sequence T0CKI..........................................................................84 Case 1..............................................................197 Timer0 Module....................................................................83 Case 2..............................................................197 Timer1 Case 3..............................................................197 Associated Registers..................................................91 Timer0 and Timer1 External Clock...........................243 Asynchronous Counter Mode.....................................90 Timer1 Incrementing Edge.........................................88 Reading and Writing...........................................90 Two Speed Start-up....................................................81 External Clock Requirements...................................244 Type-A in 1/2 MUX, 1/2 Bias Drive...........................114 Interrupt.......................................................................88 Type-A in 1/2 MUX, 1/3 Bias Drive...........................116 Modes of Operations...................................................88 Type-A in 1/3 MUX, 1/2 Bias Drive...........................118 Operation During Sleep..............................................91 Type-A in 1/3 MUX, 1/3 Bias Drive...........................120 Prescaler.....................................................................88 Type-A in 1/4 MUX, 1/3 Bias Drive...........................122 Resetting of Timer1 Registers....................................91 Type-A/Type-B in Static Drive..................................113 Resetting Timer1 Using a CCP Trigger Output...........90 Type-B in 1/2 MUX, 1/2 Bias Drive...........................115 Timer1 Gate Type-B in 1/2 MUX, 1/3 Bias Drive...........................117 Inverting Gate.....................................................88 Type-B in 1/3 MUX, 1/2 Bias Drive...........................119 Selecting Source...........................................88, 99 Type-B in 1/3 MUX, 1/3 Bias Drive...........................121 Synchronizing C2OUT w/ Timer1.......................99 Type-B in 1/4 MUX, 1/3 Bias Drive...........................123 TMR1H Register.........................................................87 USART Synchronous Receive (Master/Slave).........245 TMR1L Register..........................................................87 USART Synchronous Transmission (Master/Slave).244 Timer1 Module with Gate Control.......................................87 Wake-up from Interrupt.............................................209 Timer2.................................................................................93 Timing Parameter Symbology..........................................238 Associated registers....................................................94 Timing Requirements Operation....................................................................93 I2C Bus Data.............................................................252 Postscaler...................................................................93 I2C Bus Start/Stop Bits.............................................251 PR2 Register...............................................................93 SPI Mode..................................................................250 Prescaler.....................................................................93 TMR1H Register.................................................................87 TMR2 Output..............................................................94 TMR1L Register..................................................................87 TMR2 Register............................................................93 TRISA TMR2 to PR2 Match Interrupt...............................93, 94 Registers....................................................................27 Timing Diagrams TRISA Register...................................................................28 A/D Conversion.........................................................253 TRISB Asynchronous Master Transmission.........................138 Registers....................................................................37 Asynchronous Master Transmission (Back-to-Back)138 TRISB Register...................................................................38 Asynchronous Reception..........................................141 TRISC Asynchronous Reception with Address Byte First....143 Registers....................................................................47 Asynchronous Reception with Address Detect.........143 TRISC Register...................................................................47 Brown-out Reset (BOR)............................................242 TRISD Brown-out Reset Situations......................................195 Registers....................................................................56 Capture/Compare/PWM............................................245 TRISD Register...................................................................56 CLKO and I/O...........................................................241 TRISE Clock Synchronization..............................................182 Registers....................................................................61 Comparator Output.....................................................96 TRISE Register...................................................................61 External Clock...........................................................239 TRISF Fail-Safe Clock Monitor (FSCM).................................82 I2C Bus Data.............................................................251 Registers....................................................................65 I2C Bus Start/Stop Bits..............................................250 TRISF Register...................................................................65 I2C Reception (7-bit Address)...................................177 TRISG I2C Slave Mode (Transmission, 10-bit Address).......180 Registers....................................................................68 I2C Slave Mode with SEN = 0 (Reception, TRISG Register..................................................................68 Two-Speed Clock Start-up Mode........................................80 10-bit Address)..................................................178 I2C Transmission (7-bit Address)..............................179 TXSTA Register BRGH Bit..................................................................133 INT Pin Interrupt........................................................204 CSRC Bit..................................................................133 LCD Interrupt Timing in Quarter-Duty Cycle Drive....124 SYNC Bit..................................................................133 LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00.126 TRMT Bit...................................................................133 Reset, WDT, OST and Power-up Timer...................242 TX9 Bit......................................................................133 Slave Synchronization..............................................172 Preliminary DS41265A-page 266 © 2005 Microchip Technology Inc.

PIC16F946 TX9D Bit....................................................................133 W TXEN Bit...................................................................133 Wake-up Using Interrupts.................................................208 U Watchdog Timer (WDT)....................................................206 Associated Registers................................................207 UA.....................................................................................166 Clock Source............................................................206 Update Address bit, UA....................................................166 Modes.......................................................................206 USART..............................................................................133 Period.......................................................................206 Address Detect Enable (ADDEN Bit)........................134 Specifications...........................................................243 Asynchronous Mode.................................................137 WCOL bit..........................................................................167 Asynchronous Receive (9-bit Mode).........................142 WDTCON Register...........................................................207 Asynchronous Receive with Address Detect. WPUB Register...................................................................39 See Asynchronous Receive (9-bit Mode). Write Collision Detect bit (WCOL)....................................167 Asynchronous Receiver............................................140 WWW Address.................................................................269 Asynchronous Reception..........................................140 WWW, On-Line Support.......................................................3 Asynchronous Transmitter........................................137 Baud Rate Generator (BRG).....................................135 Baud Rate Formula...........................................135 Baud Rates, Asynchronous Mode (BRGH = 0) 136 Baud Rates, Asynchronous Mode (BRGH = 1) 136 High Baud Rate Select (BRGH Bit)..................133 Sampling...........................................................135 Clock Source Select (CSRC Bit)...............................133 Continuous Receive Enable (CREN Bit)...................134 Framing Error (FERR Bit).........................................134 Mode Select (SYNC Bit)...........................................133 Overrun Error (OERR Bit).........................................134 Receive Data, 9th Bit (RX9D Bit)..............................134 Receive Enable, 9-bit (RX9 Bit)................................134 Serial Port Enable (SPEN Bit)...........................133, 134 Single Receive Enable (SREN Bit)...........................134 Synchronous Master Mode.......................................144 Requirements, Synchronous Receive..............245 Requirements, Synchronous Transmission......245 Timing Diagram, Synchronous Receive...........245 Timing Diagram, Synchronous Transmission...244 Synchronous Master Reception................................146 Synchronous Master Transmission...........................144 Synchronous Slave Mode.........................................147 Synchronous Slave Reception..................................148 Synchronous Slave Transmit....................................147 Transmit Data, 9th Bit (TX9D)...................................133 Transmit Enable (TXEN Bit)......................................133 Transmit Enable, Nine-bit (TX9 Bit)..........................133 Transmit Shift Register Status (TRMT Bit)................133 V Voltage Reference. See Comparator Voltage Reference (CVREF) VRCON Register...............................................................102 Preliminary © 2005 Microchip Technology Inc. DS41265A-page 267

PIC16F946 NOTES: Preliminary DS41265A-page 268 © 2005 Microchip Technology Inc.

PIC16F946 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to (cid:129) Distributor or Representative customers. Accessible by using your favorite Internet (cid:129) Local Sales Office browser, the web site contains the following informa- (cid:129) Field Application Engineer (FAE) tion: (cid:129) Technical Support (cid:129) Product Support – Data sheets and errata, appli- (cid:129) Development Systems Information Line cation notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, representa- documents, latest software releases and archived tive or field application engineer (FAE) for support. software Local sales offices are also available to help custom- (cid:129) General Technical Support – Frequently Asked ers. A listing of sales offices and locations is included in Questions (FAQ), technical support requests, the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com (cid:129) Business of Microchip – Product selector and In addition, there is a Development Systems Informa- ordering guides, latest Microchip press releases, tion Line which lists the latest versions of Microchip’s listing of seminars and events, listings of Micro- development systems software products. This line also chip sales offices, distributors and factory repre- provides information on how customers can receive sentatives currently available upgrade kits. The Development Systems Information Line num- CUSTOMER CHANGE NOTIFICATION bers are: SERVICE 1-800-755-2345 – United States and most of Canada Microchip’s customer notification service helps keep 1-480-792-7302 – Other International Locations customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notifi- cation and follow the registration instructions. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 269

PIC16F946 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16F946 Literature Number: DS41265A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? Preliminary DS41265A-page 270 © 2005 Microchip Technology Inc.

PIC16F946 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F946-E/SP 301 = Extended Temp., Range skinny PDIP package, 20 MHz, QTP pattern #301 b) PIC16F946-I/SO = Industrial Temp., SOIC package, 20 MHz Device: PIC16F946(1), PIC16F946T(2) Temperature I = -40°C to +85°C Range: E = -40°C to +125°C Package: PT = TQFP (Thin Quad Flatpack) Pattern: 3-Digit Pattern Code for QTP (blank otherwise) Note1: F = Standard Voltage Range LF = Wide Voltage Range 2: T=In tape and reel. * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. Preliminary © 2005 Microchip Technology Inc. DS41265A-page 271

WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Australia - Sydney India - Bangalore Austria - Weis 2355 West Chandler Blvd. Tel: 61-2-9868-6733 Tel: 91-80-2229-0061 Tel: 43-7242-2244-399 Chandler, AZ 85224-6199 Fax: 61-2-9868-6755 Fax: 91-80-2229-0062 Fax: 43-7242-2244-393 Tel: 480-792-7200 China - Beijing India - New Delhi Denmark - Ballerup Fax: 480-792-7277 Tel: 86-10-8528-2100 Tel: 91-11-5160-8631 Tel: 45-4450-2828 Technical Support: Fax: 86-10-8528-2104 Fax: 91-11-5160-8632 Fax: 45-4485-2829 http://support.microchip.com Web Address: China - Chengdu Japan - Kanagawa France - Massy www.microchip.com Tel: 86-28-8676-6200 Tel: 81-45-471- 6166 Tel: 33-1-69-53-63-20 Fax: 86-28-8676-6599 Fax: 81-45-471-6122 Fax: 33-1-69-30-90-79 Atlanta Alpharetta, GA China - Fuzhou Korea - Seoul Germany - Ismaning Tel: 770-640-0034 Tel: 86-591-8750-3506 Tel: 82-2-554-7200 Tel: 49-89-627-144-0 Fax: 770-640-0307 Fax: 86-591-8750-3521 Fax: 82-2-558-5932 or Fax: 49-89-627-144-44 China - Hong Kong SAR 82-2-558-5934 Italy - Milan Boston Westborough, MA Tel: 852-2401-1200 Malaysia - Penang Tel: 39-0331-742611 Tel: 774-760-0087 Fax: 852-2401-3431 Tel:011-604-646-8870 Fax: 39-0331-466781 Fax: 774-760-0088 China - Shanghai Fax:011-604-646-5086 Netherlands - Drunen Chicago Tel: 86-21-5407-5533 Philippines - Manila Tel: 31-416-690399 Itasca, IL Fax: 86-21-5407-5066 Tel: 011-632-634-9065 Fax: 31-416-690340 Tel: 630-285-0071 China - Shenyang Fax: 011-632-634-9069 England - Berkshire Fax: 630-285-0075 Tel: 86-24-2334-2829 Singapore Tel: 44-118-921-5869 Fax: 86-24-2334-2393 Fax: 44-118-921-5820 Dallas Tel: 65-6334-8870 Addison, TX China - Shenzhen Fax: 65-6334-8850 Tel: 972-818-7423 Tel: 86-755-8203-2660 Taiwan - Kaohsiung Fax: 972-818-2924 Fax: 86-755-8203-1760 Tel: 886-7-536-4818 Detroit China - Shunde Fax: 886-7-536-4803 Farmington Hills, MI Tel: 86-757-2839-5507 Taiwan - Taipei Tel: 248-538-2250 Fax: 86-757-2839-5571 Tel: 886-2-2500-6610 Fax: 248-538-2260 China - Qingdao Fax: 886-2-2508-0102 Kokomo Tel: 86-532-502-7355 Taiwan - Hsinchu Kokomo, IN Fax: 86-532-502-7205 Tel: 886-3-572-9526 Tel: 765-864-8360 Fax: 886-3-572-6459 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 04/20/05 Preliminary DS41265A-page 272 © 2005 Microchip Technology Inc.