PIC16F882/883/884/886/887 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers High-Performance RISC CPU Peripheral Features • Only 35 Instructions to Learn: • 24/35 I/O Pins with Individual Direction Control: - All single-cycle instructions except branches - High current source/sink for direct LED drive • Operating Speed: - Interrupt-on-Change pin - DC – 20MHz oscillator/clock input - Individually programmable weak pull-ups - DC – 200ns instruction cycle - Ultra Low-Power Wake-up (ULPWU) • Interrupt Capability • Analog Comparator Module with: • 8-Level Deep Hardware Stack - Two analog comparators • Direct, Indirect and Relative Addressing modes - Programmable on-chip voltage reference (CVREF) module (% of VDD) Special Microcontroller Features - Fixed Voltage Reference (0.6V) • Precision Internal Oscillator: - Comparator inputs and outputs externally - Factory calibrated to ±1% accessible - Software selectable frequency range of - SR Latch mode 8MHz to 31kHz - External Timer1 Gate (count enable) - Software tunable • A/D Converter: - Two-Speed Start-up mode - 10-bit resolution and 11/14 channels - Crystal fail detect for critical applications • Timer0: 8-bit Timer/Counter with 8-bit - Clock mode switching during operation for Programmable Prescaler power savings • Enhanced Timer1: • Power-Saving Sleep mode - 16-bit timer/counter with prescaler • Wide Operating Voltage Range (2.0V-5.5V) - External Gate Input mode • Industrial and Extended Temperature Range - Dedicated low-power 32kHz oscillator • Power-on Reset (POR) • Timer2: 8-bit Timer/Counter with 8-bit Period • Power-up Timer (PWRT) and Oscillator Start-up Register, Prescaler and Postscaler Timer (OST) • Enhanced Capture, Compare, PWM+ Module: • Brown-out Reset (BOR) with Software Control - 16-bit Capture, max. resolution 12.5ns Option - Compare, max. resolution 200ns • Enhanced Low-Current Watchdog Timer (WDT) - 10-bit PWM with 1, 2 or 4 output channels, with On-Chip Oscillator (software selectable programmable “dead time”, max. frequency nominal 268 seconds with full prescaler) with 20kHz software enable - PWM output steering control • Multiplexed Master Clear with Pull-up/Input Pin • Capture, Compare, PWM Module: • Programmable Code Protection - 16-bit Capture, max. resolution 12.5ns • High Endurance Flash/EEPROM Cell: - 16-bit Compare, max. resolution 200ns - 100,000 write Flash endurance - 10-bit PWM, max. frequency 20kHz - 1,000,000 write EEPROM endurance • Enhanced USART Module: - Flash/Data EEPROM retention: > 40 years - Supports RS-485, RS-232, and LIN 2.0 • Program Memory Read/Write during run time - Auto-Baud Detect • In-Circuit Debugger (on board) - Auto-Wake-Up on Start bit • In-Circuit Serial ProgrammingTM (ICSPTM) via Two Low-Power Features Pins • Master Synchronous Serial Port (MSSP) Module • Standby Current: supporting 3-wire SPI (all 4 modes) and I2C™ - 50nA @ 2.0V, typical Master and Slave Modes with I2C Address Mask • Operating Current: - 11A @ 32kHz, 2.0V, typical - 220A @ 4MHz, 2.0V, typical • Watchdog Timer Current: - 1A @ 2.0V, typical  2006-2015 Microchip Technology Inc. DS40001291H-page 1

PIC16F882/883/884/886/887 PIC16F882/883/884/886/887 Family Types Program Data Memory Memory 10-bit A/D ECCP/ Timers Device I/O EUSART MSSP Comparators Flash SRAM EEPROM (ch) CCP 8/16-bit (words) (bytes) (bytes) PIC16F882 2048 128 128 24 11 1/1 1 1 2 2/1 PIC16F883 4096 256 256 24 11 1/1 1 1 2 2/1 PIC16F884 4096 256 256 35 14 1/1 1 1 2 2/1 PIC16F886 8192 368 256 24 11 1/1 1 1 2 2/1 PIC16F887 8192 368 256 35 14 1/1 1 1 2 2/1 DS40001291H-page 2  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 Pin Diagrams – PIC16F882/883/886, 28-Pin PDIP, SOIC, SSOP RE3/MCLR/VPP 1 28 RB7/ICSPDAT RA0/AN0/ULPWU/C12IN0- 2 27 RB6/ICSPCLK RA1/AN1/C12IN1- 3 26 RB5/AN13/T1G RA2/AN2/VREF-/CVREF/C2IN+ 4 25 RB4/AN11/P1D RA3/AN3/VREF+/C1IN+ 5 86 24 RB3/AN9/PGM/C12IN2- 8 RA4/T0CKI/C1OUT 6 3/ 23 RB2/AN8/P1B 8 RA5/AN4/SS/C2OUT 7 8 22 RB1/AN10/P1C/C12IN3- 2/ VSS 8 8 21 RB0/AN12/INT 8 RA7/OSC1/CLKIN 9 6F 20 VDD RA6/OSC2/CLKOUT 10 C1 19 VSS RC0/T1OSO/T1CKI 11 PI 18 RC7/RX/DT RC1/T1OSI/CCP2 12 17 RC6/TX/CK RC2/P1A/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA  2006-2015 Microchip Technology Inc. DS40001291H-page 3

PIC16F882/883/884/886/887 TABLE 1: 28-PIN PDIP, SOIC, SSOP ALLOCATION TABLE (PIC16F882/883/886) P O S S C/ rs I/O PDIP/SOI Analog omparato Timers ECCP EUSART MSSP Interrupt Pull-up Basic n C Pi 8- 2 RA0 2 AN0/ULPWU C12IN0- — — — — — — — RA1 3 AN1 C12IN1- — — — — — — — RA2 4 AN2 C2IN+ — — — — — — VREF-/CVREF RA3 5 AN3 C1IN+ — — — — — — VREF+ RA4 6 — C1OUT T0CKI — — — — — — RA5 7 AN4 C2OUT — — — SS — — — RA6 10 — — — — — — — — OSC2/CLKOUT RA7 9 — — — — — — — — OSC1/CLKIN RB0 21 AN12 — — — — — IOC/INT Y — RB1 22 AN10 C12IN3- — P1C — — IOC Y — RB2 23 AN8 — — P1B — — IOC Y — RB3 24 AN9 C12IN2- — — — — IOC Y PGM RB4 25 AN11 — — P1D — — IOC Y — RB5 26 AN13 — T1G — — — IOC Y — RB6 27 — — — — — — IOC Y ICSPCLK RB7 28 — — — — — — IOC Y ICSPDAT RC0 11 — — T1OSO/T1CKI — — — — — — RC1 12 — — T1OSI CCP2 — — — — — RC2 13 — — — CCP1/P1A — — — — — RC3 14 — — — — — SCK/SCL — — — RC4 15 — — — — — SDI/SDA — — — RC5 16 — — — — — SDO — — — RC6 17 — — — — TX/CK — — — — RC7 18 — — — — RX/DT — — — — RE3 1 — — — — — — — Y(1) MCLR/VPP — 20 — — — — — — — — VDD — 8 — — — — — — — — VSS — 19 — — — — — — — — VSS Note 1: Pull-up activated only with external MCLR configuration. DS40001291H-page 4  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 Pin Diagrams – PIC16F882/883/886, 28-Pin QFN - 0 N 2I 1 C 1-U/ N1/C12INN0/ULPW CLR/VPP SPDAT SPCLK N13/T1G N11/P1D AA M C C A A 1/0/ 3/ 7/I 6/I 5/ 4/ AA E B B B B RR R R R R R 8 7 6 5 4 3 2 2 2 2 2 2 2 2 RA2/AN2/VREF-/CVREF/C2IN+ 1 21 RB3/AN9/PGM/C12IN2- RA3/AN3/VREF+/C1IN+ 2 20 RB2/AN8/P1B RA4/T0CKI/C1OUT 3 19 RB1/AN10/P1C/C12IN3- RA5/AN4/SS/C2OUT 4 PIC16F882/883/886 18 RB0/AN12/INT VSS 5 17 VDD RA7/OSC1/CLKIN 6 16 VSS RA6/OSC2/CLKOUT 7 15 RC7/RX/DT 0 1 2 3 4 8 9 1 1 1 1 1 0/T1OSO/T1CKI C1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK C R R  2006-2015 Microchip Technology Inc. DS40001291H-page 5

PIC16F882/883/884/886/887 TABLE 2: 28-PIN QFN ALLOCATION TABLE (PIC16F882/883/886) N rs I/O 28-Pin QF Analog Comparato Timers ECCP EUSART MSSP Interrupt Pull-up Basic RA0 27 AN0/ULPWU C12IN0- — — — — — — — RA1 28 AN1 C12IN1- — — — — — — — RA2 1 AN2 C2IN+ — — — — — — VREF-/CVREF RA3 2 AN3 C1IN+ — — — — — — VREF+ RA4 3 — C1OUT T0CKI — — — — — — RA5 4 AN4 C2OUT — — — SS — — — RA6 7 — — — — — — — — OSC2/CLKOUT RA7 6 — — — — — — — — OSC1/CLKIN RB0 18 AN12 — — — — — IOC/INT Y — RB1 19 AN10 C12IN3- — P1C — — IOC Y — RB2 20 AN8 — — P1B — — IOC Y — RB3 21 AN9 C12IN2- — — — — IOC Y PGM RB4 22 AN11 — — P1D — — IOC Y — RB5 23 AN13 — T1G — — — IOC Y — RB6 24 — — — — — — IOC Y ICSPCLK RB7 25 — — — — — — IOC Y ICSPDAT RC0 8 — — T1OSO/T1CKI — — — — — — RC1 9 — — T1OSI CCP2 — — — — — RC2 10 — — — CCP1/P1A — — — — — RC3 11 — — — — — SCK/SCL — — — RC4 12 — — — — — SDI/SDA — — — RC5 13 — — — — — SDO — — — RC6 14 — — — — TX/CK — — — — RC7 15 — — — — RX/DT — — — — RE3 26 — — — — — — — Y(1) MCLR/VPP — 17 — — — — — — — — VDD — 5 — — — — — — — — VSS — 16 — — — — — — — — VSS Note 1: Pull-up activated only with external MCLR configuration. DS40001291H-page 6  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 Pin Diagrams – PIC16F884/887, 40-Pin PDIP RE3/MCLR/VPP 1 40 RB7/ICSPDAT RA0/AN0/ULPWU/C12IN0- 2 39 RB6/ICSPCLK RA1/AN1/C12IN1- 3 38 RB5/AN13/T1G RA2/AN2/VREF-/CVREF/C2IN+ 4 37 RB4/AN11 RA3/AN3/VREF+/C1IN+ 5 36 RB3/AN9/PGM/C12IN2- RA4/T0CKI/C1OUT 6 35 RB2/AN8 RA5/AN4/SS/C2OUT 7 34 RB1/AN10/C12IN3- RE0/AN5 8 33 RB0/AN12/INT 7 RE1/AN6 9 88 32 VDD RE2/AN7 10 4/ 31 VSS 8 VDD 11 F8 30 RD7/P1D 6 VSS 12 1 29 RD6/P1C C RA7/OSC1/CLKIN 13 PI 28 RD5/P1B RA6/OSC2/CLKOUT 14 27 RD4 RC0/T1OSO/T1CKI 15 26 RC7/RX/DT RC1/T1OSI/CCP2 16 25 RC6/TX/CK RC2/P1A/CCP1 17 24 RC5/SDO RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0 19 22 RD3 RD1 20 21 RD2  2006-2015 Microchip Technology Inc. DS40001291H-page 7

PIC16F882/883/884/886/887 TABLE 3: 40-PIN PDIP ALLOCATION TABLE (PIC16F884/887) I/O 0-Pin PDIP Analog omparators Timers ECCP EUSART MSSP Interrupt Pull-up Basic 4 C RA0 2 AN0/ULPWU C12IN0- — — — — — — — RA1 3 AN1 C12IN1- — — — — — — — RA2 4 AN2 C2IN+ — — — — — — VREF-/CVREF RA3 5 AN3 C1IN+ — — — — — — VREF+ RA4 6 — C1OUT T0CKI — — — — — — RA5 7 AN4 C2OUT — — — SS — — — RA6 14 — — — — — — — — OSC2/CLKOUT RA7 13 — — — — — — — — OSC1/CLKIN RB0 33 AN12 — — — — — IOC/INT Y — RB1 34 AN10 C12IN3- — — — — IOC Y — RB2 35 AN8 — — — — — IOC Y — RB3 36 AN9 C12IN2- — — — — IOC Y PGM RB4 37 AN11 — — — — — IOC Y — RB5 38 AN13 — T1G — — — IOC Y — RB6 39 — — — — — — IOC Y ICSPCLK RB7 40 — — — — — — IOC Y ICSPDAT RC0 15 — — T1OSO/T1CKI — — — — — — RC1 16 — — T1OSI CCP2 — — — — — RC2 17 — — — CCP1/P1A — — — — — RC3 18 — — — — — SCK/SCL — — — RC4 23 — — — — — SDI/SDA — — — RC5 24 — — — — — SDO — — — RC6 25 — — — — TX/CK — — — — RC7 26 — — — — RX/DT — — — — RD0 19 — — — — — — — — — RD1 20 — — — — — — — — — RD2 21 — — — — — — — — — RD3 22 — — — — — — — — — RD4 27 — — — — — — — — — RD5 28 — — — P1B — — — — — RD6 29 — — — P1C — — — — — RD7 30 — — — P1D — — — — — RE0 8 AN5 — — — — — — — — RE1 9 AN6 — — — — — — — — RE2 10 AN7 — — — — — — — — RE3 1 — — — — — — — Y(1) MCLR/VPP — 11 — — — — — — — — VDD — 32 — — — — — — — — VDD — 12 — — — — — — — — VSS — 31 — — — — — — — — VSS Note 1: Pull-up activated only with external MCLR configuration. DS40001291H-page 8  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 Pin Diagrams – PIC16F884/887, 44-Pin QFN P2KI CC X/CKDODI/SDA CK/SCL1A/CCP11OSCI/C1OSO/T1 TSS SPTT 6/5/4/32103/2/1/0/ CCCDDDDCCCC RRRRRRRRRRR 43210987654 44444333333 RC7/RX/DT 1 33 RA6/OSC2/CLKOUT RD4 2 32 RA7/OSC1/CLKIN RD5/P1B 3 31 VSS RD6/P1C 4 30 VSS RD7/P1D 5 29 NC VSS 6 PIC16F884/887 28 VDD VDD 7 27 RE2/AN7 VDD 8 26 RE1/AN6 RB0/AN12/INT 9 25 RE0/AN5 RB1/AN10/C12IN3- 10 24 RA5/AN4/SS/C2OUT RB2/AN8 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 AN9/PGM/C12IN2-NCRB4/AN11RB5/AN13/T1GRB6/ICSPCLKRB7/ICSPDATRE3/MCLR/VPP0/ULPWU/C12IN0-RA1/AN1/C12IN1--/CV/C2IN+REFREFAN3//V+/C1IN+REF B3/ AN 2/VA3/ R 0/ NR A A R 2/ A R  2006-2015 Microchip Technology Inc. DS40001291H-page 9

PIC16F882/883/884/886/887 TABLE 4: 44-PIN QFN ALLOCATION TABLE (PIC16F884/887) N rs I/O 44-Pin QF Analog Comparato Timers ECCP EUSART MSSP Interrupt Pull-up Basic RA0 19 AN0/ULPWU C12IN0- — — — — — — — RA1 20 AN1 C12IN1- — — — — — — — RA2 21 AN2 C2IN+ — — — — — — VREF-/CVREF RA3 22 AN3 C1IN+ — — — — — — VREF+ RA4 23 — C1OUT T0CKI — — — — — — RA5 24 AN4 C2OUT — — — SS — — — RA6 33 — — — — — — — — OSC2/CLKOUT RA7 32 — — — — — — — — OSC1/CLKIN RB0 9 AN12 — — — — — IOC/INT Y — RB1 10 AN10 C12IN3- — — — — IOC Y — RB2 11 AN8 — — — — — IOC Y — RB3 12 AN9 C12IN2- — — — — IOC Y PGM RB4 14 AN11 — — — — — IOC Y — RB5 15 AN13 — T1G — — — IOC Y — RB6 16 — — — — — — IOC Y ICSPCLK RB7 17 — — — — — — IOC Y ICSPDAT RC0 34 — — T1OSO/T1CKI — — — — — — RC1 35 — — T1OSI CCP2 — — — — — RC2 36 — — — CCP1/P1A — — — — — RC3 37 — — — — — SCK/SCL — — — RC4 42 — — — — — SDI/SDA — — — RC5 43 — — — — — SDO — — — RC6 44 — — — — TX/CK — — — — RC7 1 — — — — RX/DT — — — — RD0 38 — — — — — — — — — RD1 39 — — — — — — — — — RD2 40 — — — — — — — — — RD3 41 — — — — — — — — — RD4 2 — — — — — — — — — RD5 3 — — — P1B — — — — — RD6 4 — — — P1C — — — — — RD7 5 — — — P1D — — — — — RE0 25 AN5 — — — — — — — — RE1 26 AN6 — — — — — — — — RE2 27 AN7 — — — — — — — — RE3 18 — — — — — — — Y(1) MCLR/VPP — 7 — — — — — — — — VDD — 8 — — — — — — — — VDD — 28 — — — — — — — — VDD — 6 — — — — — — — — VSS — 30 — — — — — — — — VSS — 31 — — — — — — — — VSS — 13 — — — — — — — — NC (no connect) — 29 — — — — — — — — NC (no connect) Note 1: Pull-up activated only with external MCLR configuration. DS40001291H-page 10  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 Pin Diagrams – PIC16F884/887, 44-Pin TQFP 2 P C DA CLCP1CI/C X/CKDODI/S CK/S1A/C1OS TSS SPT 6/5/4/32103/2/1/ CCCDDDDCCCC RRRRRRRRRRN 43210987654 RC7/RX/DT 1 4444433333333 NC RD4 2 32 RC0/T1OSO/T1CKI RD5/P1B 3 31 RA6/OSC2/CLKOUT RD6/P1C 4 30 RA7/OSC1/CLKIN RD7/P1D 5 29 VSS VSS 6 PIC16F884/887 28 VDD VDD 7 27 RE2/AN7 RB0/AN12/INT 8 26 RE1/AN6 RB1/AN10/C12IN3- 9 25 RE0/AN5 RB2/AN8 10 24 RA5/AN4/SS/C2OUT RB3/AN9/PGM/C12IN2- 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 NCNCRB4/AN11RB5/AN13/T1GRB6/ICSPCLKRB7/ICSPDATRE3/MCLR/VPP0/ULPWU/C12IN0-RA1/AN1/C12IN1--/CV/C2IN+REFREFAN3//V+/C1IN+REF AN 2/VA3/ 0/ NR A A R 2/ A R  2006-2015 Microchip Technology Inc. DS40001291H-page 11

PIC16F882/883/884/886/887 TABLE 5: 44-PIN TQFP ALLOCATION TABLE (PIC16F884/887) P s I/O 4-Pin TQF Analog omparator Timers ECCP EUSART MSSP Interrupt Pull-up Basic 4 C RA0 19 AN0/ULPWU C12IN0- — — — — — — — RA1 20 AN1 C12IN1- — — — — — — — RA2 21 AN2 C2IN+ — — — — — — VREF-/CVREF RA3 22 AN3 C1IN+ — — — — — — VREF+ RA4 23 — C1OUT T0CKI — — — — — — RA5 24 AN4 C2OUT — — — SS — — — RA6 31 — — — — — — — — OSC2/CLKOUT RA7 30 — — — — — — — — OSC1/CLKIN RB0 8 AN12 — — — — — IOC/INT Y — RB1 9 AN10 C12IN3- — — — — IOC Y — RB2 10 AN8 — — — — — IOC Y — RB3 11 AN9 C12IN2- — — — — IOC Y PGM RB4 14 AN11 — — — — — IOC Y — RB5 15 AN13 — T1G — — — IOC Y — RB6 16 — — — — — — IOC Y ICSPCLK RB7 17 — — — — — — IOC Y ICSPDAT RC0 32 — — T1OSO/T1CKI — — — — — — RC1 35 — — T1OSI CCP2 — — — — — RC2 36 — — — CCP1/P1A — — — — — RC3 37 — — — — — SCK/SCL — — — RC4 42 — — — — — SDI/SDA — — — RC5 43 — — — — — SDO — — — RC6 44 — — — — TX/CK — — — — RC7 1 — — — — RX/DT — — — — RD0 38 — — — — — — — — — RD1 39 — — — — — — — — — RD2 40 — — — — — — — — — RD3 41 — — — — — — — — — RD4 2 — — — — — — — — — RD5 3 — — — P1B — — — — — RD6 4 — — — P1C — — — — — RD7 5 — — — P1D — — — — — RE0 25 AN5 — — — — — — — — RE1 26 AN6 — — — — — — — — RE2 27 AN7 — — — — — — — — RE3 18 — — — — — — — Y(1) MCLR/VPP — 7 — — — — — — — — VDD — 28 — — — — — — — — VDD — 6 — — — — — — — — VSS — 13 — — — — — — — — NC (no connect) — 29 — — — — — — — — VSS — 34 — — — — — — — — NC (no connect) — 33 — — — — — — — — NC (no connect) — 12 — — — — — — — — NC (no connect) Note 1: Pull-up activated only with external MCLR configuration. DS40001291H-page 12  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 Table of Contents 1.0 Device Overview........................................................................................................................................................................14 2.0 Memory Organization.................................................................................................................................................................22 3.0 I/O Ports.....................................................................................................................................................................................40 4.0 Oscillator Module (With Fail-Safe Clock Monitor).......................................................................................................................63 5.0 Timer0 Module...........................................................................................................................................................................75 6.0 Timer1 Module with Gate Control...............................................................................................................................................78 7.0 Timer2 Module...........................................................................................................................................................................83 8.0 Comparator Module....................................................................................................................................................................85 9.0 Analog-to-Digital Converter (ADC) Module................................................................................................................................99 10.0 Data EEPROM and Flash Program Memory Control...............................................................................................................110 11.0 Capture/Compare/PWM Modules (CCP1 and CCP2)..............................................................................................................121 12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................148 13.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................175 14.0 Special Features of the CPU....................................................................................................................................................205 15.0 Instruction Set Summary..........................................................................................................................................................226 16.0 Development Support...............................................................................................................................................................235 17.0 Electrical Specifications............................................................................................................................................................239 18.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................270 19.0 Packaging Information..............................................................................................................................................................298 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2006-2015 Microchip Technology Inc. DS40001291H-page 13

PIC16F882/883/884/886/887 1.0 DEVICE OVERVIEW The PIC16F882/883/884/886/887 devices are covered by this data sheet. The PIC16F882/883/886 devices are available in 28-pin PDIP, SOIC, SSOP and QFN packages. The PIC16F884/887 are available in a 40-pin PDIP and 44-pin QFN and TQFP packages. Figure1-1 shows the block diagram of the PIC16F882/883/886 devices and Figure1-2 shows a block diagram of the PIC16F884/887 devices. Table1-1 and Table1-2 show the corresponding pinout descriptions. DS40001291H-page 14  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 1-1: PIC16F882/883/886 BLOCK DIAGRAM Configuration PORTA 13 8 RA0 Data Bus Program Counter RA1 Flash RA2 2K(2)/4K(1)/ RA3 8K X 14 RA4 RAM Program RA5 Memory 8-Level Stack 128(2)/256(1)/ RA6 (13-Bit) 368 Bytes RA7 File Registers Program PORTB 14 Bus RAM Addr RB0 9 RB1 Instruction Reg Addr MUX RB2 RB3 Direct Addr 7 Indirect RB4 8 Addr RB5 RB6 FSR Reg RB7 STATUS Reg PORTC 8 RC0 RC1 RC2 3 RC3 MUX Power-up RC4 Timer RC5 RC6 Instruction Oscillator Decode and Start-up Timer ALU RC7 Control Power-on PORTE OSC1/CLKIN Reset 8 Timing Watchdog Generation Timer W Reg OSC2/CLKOUT Brown-out CCP2 RE3 Reset Internal Oscillator Block CCP2 MCLR VDD VSS In-Circuit Debugger (ICD) T1OSI Timer1 32 kHz A T1OSO Oscillator X/CK X/DT CP1/P1 1B 1C 1D DO DI/SDA CK/SCL S T0CKI T1G T1CKI T R C P P P S S S S Master Synchronous Timer0 Timer1 Timer2 EUSART ECCP Serial Port (MSSP) VREF+ VREF+ Analog-To-Digital Converter 2 Analog Comparators VREF- 8 EEDATA VREF- (ADC) and Reference CVREF 128(2)/ 256 Bytes Data EEPROM AN0AN1AN2AN3AN4AN8AN9AN10AN11AN12AN13 C1IN+C12IN0-C12IN1-C12IN2-C12IN3-C1OUTC2IN+C2OUT EEADDR Note 1: PIC16F883 only. 2: MemHigh only.  2006-2015 Microchip Technology Inc. DS40001291H-page 15

PIC16F882/883/884/886/887 FIGURE 1-2: PIC16F884/PIC16F887 BLOCK DIAGRAM Configuration PORTA 13 8 RA0 Data Bus Program Counter RA1 Flash RA2 4K(1)/8K X 14 RA3 RA4 Program RAM RA5 Memory 8-Level Stack 256(1)/368 Bytes RA6 (13-Bit) File RA7 Registers Program PORTB 14 Bus RAM Addr RB0 9 RB1 Instruction Reg Addr MUX RB2 RB3 Direct Addr 7 Indirect RB4 8 Addr RB5 RB6 FSR Reg RB7 STATUS Reg PORTC 8 RC0 RC1 RC2 3 RC3 MUX Power-up RC4 Timer RC5 RC6 Instruction Oscillator Decode and Start-up Timer ALU RC7 Control Power-on PORTD OSC1/CLKIN Reset 8 RD0 Timing Watchdog RD1 Generation Timer W Reg RD2 RD3 OSC2/CLKOUT Brown-out CCP2 RD4 Reset RD5 Internal RD6 Oscillator RD7 Block CCP2 PORTE MCLR VDD VSS RE0 In-Circuit RE1 Debugger RE2 (ICD) RE3 T1OSI Timer1 32 kHz A T1OSTO0CKI T1GOscillatTo1rCKI TX/CK RX/DT CCP1/P1 P1B P1C P1D SDO SDI/SDA SCK/SCL SS Master Synchronous Timer0 Timer1 Timer2 EUSART ECCP Serial Port (MSSP) VREF+ VREF+ Analog-To-Digital Converter 2 Analog Comparators VREF- 8 EEDATA VREF- (ADC) and Reference CVREF 256 Bytes Data EEPROM AN0AN1AN2AN3AN4AN5AN6AN7AN8AN9AN10AN11AN12AN13 C1IN+C12IN0-C12IN1-C12IN2-C12IN3-C1OUTC2IN+C2OUT EEADDR Note 1: PIC16F884 only. DS40001291H-page 16  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/ULPWU/C12IN0- RA0 TTL CMOS General purpose I/O. AN0 AN — A/D Channel 0 input. ULPWU AN — Ultra Low-Power Wake-up input. C12IN0- AN — Comparator C1 or C2 negative input. RA1/AN1/C12IN1- RA1 TTL CMOS General purpose I/O. AN1 AN — A/D Channel 1 input. C12IN1- AN — Comparator C1 or C2 negative input. RA2/AN2/VREF-/CVREF/C2IN+ RA2 TTL CMOS General purpose I/O. AN2 AN — A/D Channel 2. VREF- AN — A/D Negative Voltage Reference input. CVREF — AN Comparator Voltage Reference output. C2IN+ AN — Comparator C2 positive input. RA3/AN3/VREF+/C1IN+ RA3 TTL — General purpose I/O. AN3 AN — A/D Channel 3. VREF+ AN — Programming voltage. C1IN+ AN — Comparator C1 positive input. RA4/T0CKI/C1OUT RA4 TTL CMOS General purpose I/O. T0CKI ST — Timer0 clock input. C1OUT — CMOS Comparator C1 output. RA5/AN4/SS/C2OUT RA5 TTL CMOS General purpose I/O. AN4 AN — A/D Channel 4. SS ST — Slave Select input. C2OUT — CMOS Comparator C2 output. RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O. OSC2 — XTAL Master Clear with internal pull-up. CLKOUT — CMOS FOSC/4 output. RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O. OSC1 XTAL — Crystal/Resonator. CLKIN ST — External clock input/RC oscillator connection. RB0/AN12/INT RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN12 AN — A/D Channel 12. INT ST — External interrupt. RB1/AN10/P1C/C12IN3- RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN10 AN — A/D Channel 10. P1C — CMOS PWM output. C12IN3- AN — Comparator C1 or C2 negative input. RB2/AN8/P1B RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN8 AN — A/D Channel 8. P1B — CMOS PWM output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal  2006-2015 Microchip Technology Inc. DS40001291H-page 17

PIC16F882/883/884/886/887 TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RB3/AN9/PGM/C12IN2- RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN9 AN — A/D Channel 9. PGM ST — Low-voltage ICSP™ Programming enable pin. C12IN2- AN — Comparator C1 or C2 negative input. RB4/AN11/P1D RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN11 AN — A/D Channel 11. P1D — CMOS PWM output. RB5/AN13/T1G RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN13 AN — A/D Channel 13. T1G ST — Timer1 Gate input. RB6/ICSPCLK RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ICSPCLK ST — Serial Programming Clock. RB7/ICSPDAT RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ICSPDAT ST CMOS ICSP™ Data I/O. RC0/T1OSO/T1CKI RC0 ST CMOS General purpose I/O. T1OSO — CMOS Timer1 oscillator output. T1CKI ST — Timer1 clock input. RC1/T1OSI/CCP2 RC1 ST CMOS General purpose I/O. T1OSI ST — Timer1 oscillator input. CCP2 ST CMOS Capture/Compare/PWM2. RC2/P1A/CCP1 RC2 ST CMOS General purpose I/O. P1A — CMOS PWM output. CCP1 ST CMOS Capture/Compare/PWM1. RC3/SCK/SCL RC3 ST CMOS General purpose I/O. SCK ST CMOS SPI clock. SCL ST OD I2C™ clock. RC4/SDI/SDA RC4 ST CMOS General purpose I/O. SDI ST — SPI data input. SDA ST OD I2C data input/output. RC5/SDO RC5 ST CMOS General purpose I/O. SDO — CMOS SPI data output. RC6/TX/CK RC6 ST CMOS General purpose I/O. TX — CMOS EUSART asynchronous transmit. CK ST CMOS EUSART synchronous clock. RC7/RX/DT RC7 ST CMOS General purpose I/O. RX ST — EUSART asynchronous input. DT ST CMOS EUSART synchronous data. RE3/MCLR/VPP RE3 TTL — General purpose input. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. VSS VSS Power — Ground reference. VDD VDD Power — Positive supply. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal DS40001291H-page 18  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/ULPWU/C12IN0- RA0 TTL CMOS General purpose I/O. AN0 AN — A/D Channel 0 input. ULPWU AN — Ultra Low-Power Wake-up input. C12IN0- AN — Comparator C1 or C2 negative input. RA1/AN1/C12IN1- RA1 TTL CMOS General purpose I/O. AN1 AN — A/D Channel 1 input. C12IN1- AN — Comparator C1 or C2 negative input. RA2/AN2/VREF-/CVREF/C2IN+ RA2 TTL CMOS General purpose I/O. AN2 AN — A/D Channel 2. VREF- AN — A/D Negative Voltage Reference input. CVREF — AN Comparator Voltage Reference output. C2IN+ AN — Comparator C2 positive input. RA3/AN3/VREF+/C1IN+ RA3 TTL CMOS General purpose I/O. AN3 AN — A/D Channel 3. VREF+ AN — A/D Positive Voltage Reference input. C1IN+ AN — Comparator C1 positive input. RA4/T0CKI/C1OUT RA4 TTL CMOS General purpose I/O. T0CKI ST — Timer0 clock input. C1OUT — CMOS Comparator C1 output. RA5/AN4/SS/C2OUT RA5 TTL CMOS General purpose I/O. AN4 AN — A/D Channel 4. SS ST — Slave Select input. C2OUT — CMOS Comparator C2 output. RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O. OSC2 — XTAL Crystal/Resonator. CLKOUT — CMOS FOSC/4 output. RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O. OSC1 XTAL — Crystal/Resonator. CLKIN ST — External clock input/RC oscillator connection. RB0/AN12/INT RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN12 AN — A/D Channel 12. INT ST — External interrupt. RB1/AN10/C12IN3- RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN10 AN — A/D Channel 10. C12IN3- AN — Comparator C1 or C2 negative input. RB2/AN8 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN8 AN — A/D Channel 8. RB3/AN9/PGM/C12IN2- RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN9 AN — A/D Channel 9. PGM ST — Low-voltage ICSP™ Programming enable pin. C12IN2- AN — Comparator C1 or C2 negative input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal  2006-2015 Microchip Technology Inc. DS40001291H-page 19

PIC16F882/883/884/886/887 TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RB4/AN11 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN11 AN — A/D Channel 11. RB5/AN13/T1G RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN13 AN — A/D Channel 13. T1G ST — Timer1 Gate input. RB6/ICSPCLK RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ICSPCLK ST — Serial Programming Clock. RB7/ICSPDAT RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ICSPDAT ST TTL ICSP™ Data I/O. RC0/T1OSO/T1CKI RC0 ST CMOS General purpose I/O. T1OSO — XTAL Timer1 oscillator output. T1CKI ST — Timer1 clock input. RC1/T1OSI/CCP2 RC1 ST CMOS General purpose I/O. T1OSI XTAL — Timer1 oscillator input. CCP2 ST CMOS Capture/Compare/PWM2. RC2/P1A/CCP1 RC2 ST CMOS General purpose I/O. P1A ST CMOS PWM output. CCP1 — CMOS Capture/Compare/PWM1. RC3/SCK/SCL RC3 ST CMOS General purpose I/O. SCK ST CMOS SPI clock. SCL ST OD I2C™ clock. RC4/SDI/SDA RC4 ST CMOS General purpose I/O. SDI ST — SPI data input. SDA ST OD I2C data input/output. RC5/SDO RC5 ST CMOS General purpose I/O. SDO — CMOS SPI data output. RC6/TX/CK RC6 ST CMOS General purpose I/O. TX — CMOS EUSART asynchronous transmit. CK ST CMOS EUSART synchronous clock. RC7/RX/DT RC7 ST CMOS General purpose I/O. RX ST — EUSART asynchronous input. DT ST CMOS EUSART synchronous data. RD0 RD0 TTL CMOS General purpose I/O. RD1 RD1 TTL CMOS General purpose I/O. RD2 RD2 TTL CMOS General purpose I/O. RD3 RD3 TTL CMOS General purpose I/O. RD4 RD4 TTL CMOS General purpose I/O. RD5/P1B RD5 TTL CMOS General purpose I/O. P1B — CMOS PWM output. RD6/P1C RD6 TTL CMOS General purpose I/O. P1C — CMOS PWM output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal DS40001291H-page 20  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RD7/P1D RD7 TTL CMOS General purpose I/O. P1D AN — PWM output. RE0/AN5 RE0 TTL CMOS General purpose I/O. AN5 AN — A/D Channel 5. RE1/AN6 RE1 TTL CMOS General purpose I/O. AN6 AN — A/D Channel 6. RE2/AN7 RE2 TTL CMOS General purpose I/O. AN7 AN — A/D Channel 7. RE3/MCLR/VPP RE3 TTL — General purpose input. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. VSS VSS Power — Ground reference. VDD VDD Power — Positive supply. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal  2006-2015 Microchip Technology Inc. DS40001291H-page 21

PIC16F882/883/884/886/887 2.0 MEMORY ORGANIZATION FIGURE 2-2: PROGRAM MEMORY MAP AND STACK FOR THE 2.1 Program Memory Organization PIC16F883/PIC16F884 The PIC16F882/883/884/886/887 devices have a 13-bit PC<12:0> program counter capable of addressing a 2Kx14 (0000h-07FFh) for the PIC16F882, 4Kx14 (0000h- CALL, RETURN 13 RETFIE, RETLW 0FFFh) for the PIC16F883/PIC16F884, and 8Kx14 (0000h-1FFFh) for the PIC16F886/PIC16F887 program memory space. Accessing a location above these Stack Level 1 boundaries will cause a wrap-around within the first 8K x Stack Level 2 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures2-2 and2-3). Stack Level 8 FIGURE 2-1: PROGRAM MEMORY MAP Reset Vector 0000h AND STACK FOR THE PIC16F882 PC<12:0> Interrupt Vector 0004h 0005h CALL, RETURN 13 Page 0 RETFIE, RETLW On-Chip 07FFh Program Memory 0800h Page 1 Stack Level 1 0FFFh Stack Level 2 FIGURE 2-3: PROGRAM MEMORY MAP Stack Level 8 AND STACK FOR THE Reset Vector 0000h PIC16F886/PIC16F887 PC<12:0> CALL, RETURN 13 Interrupt Vector 0004h RETFIE, RETLW On-Chip 0005h Program Page 0 Memory 07FFh Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 On-Chip 0FFFh Program Memory 1000h Page 2 17FFh 1800h Page 3 1FFFh DS40001291H-page 22  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 2.2 Data Memory Organization The data memory (see Figures2-2 and 2-3) is partitioned into four banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. The General Purpose Registers, implemented as static RAM, are located in the last 96 locations of each Bank. Register locations F0h-FFh in Bank 1, 170h-17Fh in Bank 2 and 1F0h-1FFh in Bank 3, point to addresses 70h-7Fh in Bank0. The actual number of General Purpose Resisters (GPR) implemented in each Bank depends on the device. Details are shown in Figures2-5 and 2-6. All other RAM is unimplemented and returns ‘0’ when read. RP<1:0> of the STATUS register are the bank select bits: RP1 RP0 0 0 Bank 0 is selected 0 1 Bank 1 is selected 1 0 Bank 2 is selected 1 1 Bank 3 is selected 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 x 8 in the PIC16F882, 256 x 8 in the PIC16F883/PIC16F884, and 368 x 8 in the PIC16F886/PIC16F887. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.  2006-2015 Microchip Technology Inc. DS40001291H-page 23

PIC16F882/883/884/886/887 FIGURE 2-4: PIC16F882 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h WDTCON 105h SRCON 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h 08h 88h CM2CON0 108h ANSEL 188h PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh T1CON 10h OSCTUNE 90h 110h 190h TMR2 11h SSPCON2 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPR1L 15h WPUB 95h 115h 195h CCPR1H 16h IOCB 96h 116h 196h CCP1CON 17h VRCON 97h 117h 197h RCSTA 18h TXSTA 98h 118h 198h TXREG 19h SPBRG 99h 119h 199h RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh 20h General A0h 120h 1A0h Purpose Registers General 32 Bytes BFh Purpose Registers C0h 96 Bytes EFh 16Fh 1EFh accesses F0h accesses 170h accesses 1F0h 7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. DS40001291H-page 24  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 2-5: PIC16F883/PIC16F884 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h WDTCON 105h SRCON 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h PORTD(2) 08h TRISD(2) 88h CM2CON0 108h ANSEL 188h PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh T1CON 10h OSCTUNE 90h 110h 190h TMR2 11h SSPCON2 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPR1L 15h WPUB 95h 115h 195h CCPR1H 16h IOCB 96h 116h 196h CCP1CON 17h VRCON 97h 117h 197h RCSTA 18h TXSTA 98h 118h 198h TXREG 19h SPBRG 99h 119h 199h RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh 20h A0h 120h 1A0h General General Purpose Purpose General Registers Registers Purpose Registers 80 Bytes 80 Bytes 96 Bytes EFh 16Fh 1EFh accesses F0h accesses 170h accesses 1F0h 7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. 2: PIC16F884 only.  2006-2015 Microchip Technology Inc. DS40001291H-page 25

PIC16F882/883/884/886/887 FIGURE 2-6: PIC16F886/PIC16F887 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h WDTCON 105h SRCON 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h PORTD(2) 08h TRISD(2) 88h CM2CON0 108h ANSEL 188h PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh T1CON 10h OSCTUNE 90h 110h 190h TMR2 11h SSPCON2 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPR1L 15h WPUB 95h 115h 195h CCPR1H 16h IOCB 96h General 116h General 196h Purpose Purpose CCP1CON 17h VRCON 97h 117h 197h Registers Registers RCSTA 18h TXSTA 98h 118h 198h TXREG 19h SPBRG 99h 16 Bytes 119h 16 Bytes 199h RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh 20h A0h 120h 1A0h General General General Purpose 3Fh Purpose Purpose General Registers Purpose 40h Registers Registers Registers 80 Bytes 80 Bytes 80 Bytes 96 Bytes 6Fh EFh 16Fh 1EFh 70h accesses F0h accesses 170h accesses 1F0h 7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. 2: PIC16F887 only. DS40001291H-page 26  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 2-1: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu(5) 04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 05h PORTA(3) RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx 0000 0000 06h PORTB(3) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 0000 0000 07h PORTC(3) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 0000 0000 08h PORTD(3,4) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 0000 0000 09h PORTE(3) — — — — RE3 RE2(4) RE1(4) RE0(4) ---- xxxx ---- 0000 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u 0Ch PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 0000 0000 0Dh PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 0000 00-0 0000 0000 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu 11h TMR2 Timer2 Module Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON(2) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 0000 19h TXREG EUSART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG EUSART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 000 1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/ ADON 0000 0000 00-0 0000 DONE Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK register. See Registers13-2 and13-4 for more details. 3: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets). 4: PIC16F884/PIC16F887 only. 5: See Table14-5 for Reset value for specific condition.  2006-2015 Microchip Technology Inc. DS40001291H-page 27

PIC16F882/883/884/886/887 TABLE 2-2: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu(5) 84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 88h TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111 89h TRISE — — — — TRISE3 TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 ---- 1111 8Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u 8Ch PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 0000 0000 8Dh PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 0000 00-0 0000 0000 8Eh PCON — — ULPWUE SBOREN — — POR BOR --01 --qq --0u --uu(4,6) 8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 -110 q000 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu 91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD(2) Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 93h SSPMSK(2) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000 97h VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 -010 99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 9Ah SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 9Bh PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 0000 0000 9Ch ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000 9Dh PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu 9Fh ADCON1 ADFM — VCFG1 VCFG0 — — — — 0-00 ---- 0-00 ---- Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: Accessible only when SSPCON register bits SSPM<3:0> = 1001. 3: PIC16F884/PIC16F887 only. 4: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 5: See Table14-5 for Reset value for specific condition. 6: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. DS40001291H-page 28  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 2-3: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 103h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu(3) 104h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 105h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 0000 0000 107h CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 0-00 108h CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 0-00 109h CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC 0000 --10 0000 0--0 10Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u 10Ch EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 10Dh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 10Eh EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000 10Fh EEADRH — — — EEADRH4(2) EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 ---0 0000 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F886/PIC16F887 only. 3: See Table14-5 for Reset value for specific condition. TABLE 2-4: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 183h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu(3) 184h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 185h SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — FVREN 0000 00-0 0000 00-0 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 187h BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 188h ANSEL ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 189h ANSELH — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 --11 1111 1111 1111 18Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF(1) 0000 000x 0000 000u 18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 ---- q000 18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---- Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F884/PIC16F887 only. 3: See Table14-5 for Reset value for specific condition.  2006-2015 Microchip Technology Inc. DS40001291H-page 29

PIC16F882/883/884/886/887 2.2.2.1 STATUS Register For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register2-1, contains: as ‘000u u1uu’ (where u = unchanged). • the arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, • the Reset status SWAPF and MOVWF instructions are used to alter the • the bank select bits for data memory (GPR and STATUS register, because these instructions do not SFR) affect any Status bits. For other instructions not affect- The STATUS register can be the destination for any ing any Status bits, see Section15.0 “Instruction Set instruction, like any other register. If the STATUS Summary” register is the destination for an instruction that affects Note1: The C and DC bits operate as a Borrow the Z, DC or C bits, then the write to these three bits is and Digit Borrow out bit, respectively, in disabled. These bits are set or cleared according to the subtraction. device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER DEFINITIONS: STATUS REGISTER 2-1: STATUS: STATUS REGISTER R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS40001291H-page 30  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 2.2.2.2 OPTION Register The OPTION register, shown in Register2-2, is a readable and writable register, which contains various control bits to configure: • Timer0/WDT prescaler • External INT interrupt • Timer0 • Weak pull-ups on PORTB Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’. See Section6.3 “Timer1 Pres- caler”. REGISTER DEFINITIONS: OPTION REGISTER REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128  2006-2015 Microchip Technology Inc. DS40001291H-page 31

PIC16F882/883/884/886/887 2.2.2.3 INTCON Register The INTCON register, shown in Register2-3, is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external INT pin interrupts. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER DEFINITIONS: INTERRUPT CONTROL REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE(1) T0IF(2) INTF RBIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 RBIE: PORTB Change Interrupt Enable bit(1) 1 = Enables the PORTB change interrupt 0 = Disables the PORTB change interrupt bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred (must be cleared in software) 0 = The INT external interrupt did not occur bit 0 RBIF: PORTB Change Interrupt Flag bit 1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in software) 0 = None of the PORTB general purpose I/O pins have changed state Note 1: IOCB register must also be enabled. 2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. DS40001291H-page 32  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register2-4. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. REGISTER DEFINITIONS: PIE1 REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt  2006-2015 Microchip Technology Inc. DS40001291H-page 33

PIC16F882/883/884/886/887 2.2.2.5 PIE2 Register The PIE2 register contains the interrupt enable bits, as shown in Register2-5. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. REGISTER DEFINITIONS: PIE2 REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables oscillator fail interrupt 0 = Disables oscillator fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables Comparator C2 interrupt 0 = Disables Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables Comparator C1 interrupt 0 = Disables Comparator C1 interrupt bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit 1 = Enables EEPROM write operation interrupt 0 = Disables EEPROM write operation interrupt bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enables Bus Collision interrupt 0 = Disables Bus Collision interrupt bit 2 ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable bit 1 = Enables Ultra Low-Power Wake-up interrupt 0 = Disables Ultra Low-Power Wake-up interrupt bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables CCP2 interrupt 0 = Disables CCP2 interrupt DS40001291H-page 34  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 2.2.2.6 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register2-6. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER DEFINITIONS: PIR1 REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = A/D conversion complete (must be cleared in software) 0 = A/D conversion has not completed or has not been started bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer is full (cleared by reading RCREG) 0 = The EUSART receive buffer is not full bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer is empty (cleared by writing to TXREG) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = The MSSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Rou- tine. The conditions that will set this bit are: SPI A transmission/reception has taken place I 2 C Slave/Master A transmission/reception has taken place I 2 C Master The initiated Start condition was completed by the MSSP module The initiated Stop condition was completed by the MSSP module The initiated restart condition was completed by the MSSP module The initiated Acknowledge condition was completed by the MSSP module A Start condition occurred while the MSSP module was idle (Multi-master system) A Stop condition occurred while the MSSP module was idle (Multi-master system) 0 = No MSSP interrupt condition has occurred bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = A Timer2 to PR2 match occurred (must be cleared in software) 0 = No Timer2 to PR2 match occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow  2006-2015 Microchip Technology Inc. DS40001291H-page 35

PIC16F882/883/884/886/887 2.2.2.7 PIR2 Register The PIR2 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register2-7. condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER DEFINITIONS: PIR2 REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 6 C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed bit 4 EEIF: EE Write Operation Interrupt Flag bit 1 = Write operation completed (must be cleared in software) 0 = Write operation has not completed or has not started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision has occurred in the MSSP when configured for I2C Master mode 0 = No bus collision has occurred bit 2 ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag bit 1 = Wake-up condition has occurred (must be cleared in software) 0 = No Wake-up condition has occurred bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode DS40001291H-page 36  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 2.2.2.8 PCON Register The Power Control (PCON) register (see Register2-8) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR. REGISTER DEFINITIONS: PCON REGISTER 2-8: PCON: POWER CONTROL REGISTER U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x — — ULPWUE SBOREN(1) — — POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit 1 = Ultra Low-Power Wake-up enabled 0 = Ultra Low-Power Wake-up disabled bit 4 SBOREN: Software BOR Enable bit(1) 1 = BOR enabled 0 = BOR disabled bit 3-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: BOREN<1:0> = 01 in the Configuration Word Register 1 for this bit to control the BOR.  2006-2015 Microchip Technology Inc. DS40001291H-page 37

PIC16F882/883/884/886/887 2.3 PCL and PCLATH 2.3.2 STACK The Program Counter (PC) is 13 bits wide. The low byte The PIC16F882/883/884/886/887 devices have an comes from the PCL register, which is a readable and 8-levelx13-bit wide hardware stack (see Figures2-2 writable register. The high byte (PC<12:8>) is not directly and 2-3). The stack space is not part of either program readable or writable and comes from PCLATH. On any or data space and the Stack Pointer is not readable or Reset, the PC is cleared. Figure2-7 shows the two writable. The PC is PUSHed onto the stack when a situations for the loading of the PC. The upper example CALL instruction is executed or an interrupt causes a in Figure2-7 shows how the PC is loaded on a write to branch. The stack is POPed in the event of a RETURN, PCL (PCLATH<4:0>  PCH). The lower example in RETLW or a RETFIE instruction execution. PCLATH is Figure2-7 shows how the PC is loaded during a CALL or not affected by a PUSH or POP operation. GOTO instruction (PCLATH<4:3>  PCH). The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth FIGURE 2-7: LOADING OF PC IN push overwrites the value that was stored from the first DIFFERENT SITUATIONS push. The tenth push overwrites the second push (and so on). PCH PCL Instruction with Note1: There are no Status bits to indicate stack 12 8 7 0 PCL as PC Destination overflow or stack underflow conditions. 2: There are no instructions/mnemonics PCLATH<4:0> 8 5 ALU Result called PUSH or POP. These are actions that occur from the execution of the PCLATH CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an PCH PCL interrupt address. 12 11 10 8 7 0 PC GOTO, CALL 2.4 Indirect Addressing, INDF and PCLATH<4:3> 11 FSR Registers 2 OPCODE<10:0> The INDF register is not a physical register. Addressing PCLATH the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF 2.3.1 MODIFYING PCL register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register Executing any instruction with the PCL register as the (FSR). Reading INDF itself indirectly will produce 00h. destination simultaneously causes the Program Writing to the INDF register indirectly results in a no Counter PC<12:8> bits (PCH) to be replaced by the operation (although Status bits may be affected). An contents of the PCLATH register. This allows the entire effective 9-bit address is obtained by concatenating the contents of the program counter to be changed by 8-bit FSR and the IRP bit of the STATUS register, as writing the desired upper five bits to the PCLATH shown in Figure2-8. register. When the lower eight bits are written to the PCL register, all 13 bits of the program counter will A simple program to clear RAM location 20h-2Fh using change to the values contained in the PCLATH register indirect addressing is shown in Example2-1. and those being written to the PCL register. A computed GOTO is accomplished by adding an offset EXAMPLE 2-1: INDIRECT ADDRESSING to the program counter (ADDWF PCL). Care should be MOVLW 0x20 ;initialize pointer exercised when jumping into a look-up table or MOVWF FSR ;to RAM program branch table (computed GOTO) by modifying NEXT CLRF INDF ;clear INDF register the PCL register. Assuming that PCLATH is set to the INCF FSR ;inc pointer table start address, if the table length is greater than BTFSS FSR,4 ;all done? 255 instructions or if the lower eight bits of the memory GOTO NEXT ;no clear next CONTINUE ;yes continue address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table. For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556). DS40001291H-page 38  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 2-8: DIRECT/INDIRECT ADDRESSING PIC16F882/883/884/886/887 Direct Addressing Indirect Addressing RP1 RP0 6 From Opcode 0 IRP 7 File Select Register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 180h Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note: For memory map detail, see Figures2-2 and2-3.  2006-2015 Microchip Technology Inc. DS40001291H-page 39

PIC16F882/883/884/886/887 3.0 I/O PORTS The TRISA register (Register3-2) controls the PORTA pin output drivers, even when they are being used as There are as many as 35 general purpose I/O pins analog inputs. The user should ensure the bits in the available. Depending on which peripherals are TRISA register are maintained set when using them as enabled, some or all of the pins may not be available as analog inputs. I/O pins configured as analog input always general purpose I/O. In general, when a peripheral is read ‘0’. enabled, the associated pin may not be used as a Note: The ANSEL register must be initialized to general purpose I/O pin. configure an analog channel as a digital input. Pins configured as analog inputs 3.1 PORTA and the TRISA Registers will read ‘0’. PORTA is a 8-bit wide, bidirectional port. The EXAMPLE 3-1: INITIALIZING PORTA corresponding data direction register is TRISA (Register3-2). Setting a TRISA bit (= 1) will make the BANKSELPORTA ; corresponding PORTA pin an input (i.e., disable the CLRF PORTA ;Init PORTA output driver). Clearing a TRISA bit (= 0) will make the BANKSELANSEL ; corresponding PORTA pin an output (i.e., enables CLRF ANSEL ;digital I/O BANKSELTRISA ; output driver and puts the contents of the output latch MOVLW 0Ch ;Set RA<3:2> as inputs on the selected pin). Example3-1 shows how to MOVWF TRISA ;and set RA<5:4,1:0> initialize PORTA. ;as outputs Reading the PORTA register (Register3-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. REGISTER 3-1: PORTA: PORTA REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RA<7:0>: PORTA I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 3-2: TRISA: PORTA TRI-STATE REGISTER R/W-1(1) R/W-1(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: TRISA<7:6> always reads ‘1’ in XT, HS and LP Oscillator modes. DS40001291H-page 40  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 3.2 Additional Pin Functions RA0 also has an Ultra Low-Power Wake-up option. The next three sections describe these functions. 3.2.1 ANSEL REGISTER The ANSEL register (Register3-3) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSEL bits has no affect on digital out- put functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. REGISTER 3-3: ANSEL: ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2: Not implemented on MemHigh.  2006-2015 Microchip Technology Inc. DS40001291H-page 41

PIC16F882/883/884/886/887 3.2.2 ULTRA LOW-POWER WAKE-UP A series resistor between RA0 and the external capacitor provides overcurrent protection for the The Ultra Low-Power Wake-up (ULPWU) on RA0 allows RA0/AN0/ULPWU/C12IN0- pin and can allow for a slow falling voltage to generate an interrupt-on-change software calibration of the time-out (see Figure3-1). A on RA0 without excess current consumption. The mode timer can be used to measure the charge time and is selected by setting the ULPWUE bit of the PCON discharge time of the capacitor. The charge time can register. This enables a small current sink, which can be then be adjusted to provide the desired interrupt delay. used to discharge a capacitor on RA0. This technique will compensate for the affects of Follow these steps to use this feature: temperature, voltage and component accuracy. The a) Charge the capacitor on RA0 by configuring the Ultra Low-Power Wake-up peripheral can also be RA0 pin to output (= 1). configured as a simple Programmable Low Voltage Detect or temperature sensor. b) Configure RA0 as an input. c) Set the ULPWUIE bit of the PIE2 register to Note: For more information, refer to AN879, enable interrupt. “Using the Microchip Ultra Low-Power d) Set the ULPWUE bit of the PCON register to Wake-up Module” Application Note begin the capacitor discharge. (DS00879). e) Execute a SLEEP instruction. EXAMPLE 3-2: ULTRA LOW-POWER When the voltage on RA0 drops below VIL, an interrupt WAKE-UP INITIALIZATION will be generated which will cause the device to wake-up and execute the next instruction. If the GIE bit BANKSELPORTA ; of the INTCON register is set, the device will then call BSF PORTA,0 ;Set RA0 data latch the interrupt vector (0004h). BANKSELANSEL ; BCF ANSEL,0 ;RA0 to digital I/O This feature provides a low-power technique for BANKSELTRISA ; periodically waking up the device from Sleep. The BCF TRISA,0 ;Output high to time-out is dependent on the discharge time of the RC CALL CapDelay ;charge capacitor circuit on RA0. See Example3-2 for initializing the BANKSELPIR2 ; Ultra Low-Power Wake-up module. BCF PIR2,ULPWUIF ;Clear flag BANKSELPCON BSF PCON,ULPWUE ;Enable ULP Wake-up BSF TRISA,0 ;RA0 to input BSF PIE2, ULPWUIE ;Enable interrupt MOVLW B’11000000’ ;Enable peripheral MOVWF INTCON ;interrupt SLEEP ;Wait for IOC NOP ; DS40001291H-page 42  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 3.2.3 PIN DESCRIPTIONS AND 3.2.3.1 RA0/AN0/ULPWU/C12IN0- DIAGRAMS Figure3-1 shows the diagram for this pin. This pin is Each PORTA pin is multiplexed with other functions. The configurable to function as one of the following: pins and their combined functions are briefly described • a general purpose I/O here. For specific information about individual functions • an analog input for the ADC such as the comparator or the A/D Converter (ADC), • a negative analog input to Comparator C1 or C2 refer to the appropriate section in this data sheet. • an analog input for the Ultra Low-Power Wake-up FIGURE 3-1: BLOCK DIAGRAM OF RA0 Data Bus VDD D Q WR CK I/O Pin Q PORTA VSS - + VTRG D Q TRWISRA CK Q IULP 0 1 RD TRISA Analog(1) VSS Input Mode ULPWUE RD PORTA To Comparator To A/D Converter Note 1: ANSEL determines Analog Input mode.  2006-2015 Microchip Technology Inc. DS40001291H-page 43

PIC16F882/883/884/886/887 3.2.3.2 RA1/AN1/C12IN1- 3.2.3.3 RA2/AN2/VREF-/CVREF/C2IN+ Figure3-2 shows the diagram for this pin. This pin is Figure3-3 shows the diagram for this pin. This pin is configurable to function as one of the following: configurable to function as one of the following: • a general purpose I/O • a general purpose I/O • an analog input for the ADC • an analog input for the ADC • a negative analog input to Comparator C1 or C2 • a negative voltage reference input for the ADC and CVREF FIGURE 3-2: BLOCK DIAGRAM OF RA1 • a comparator voltage reference output • a positive analog input to Comparator C2 Data Bus FIGURE 3-3: BLOCK DIAGRAM OF RA2 VDD D Q WR CK Data Bus PORTA Q VROE CVREF VDD D Q I/O Pin D Q WR CK Q PORTA WR CK TRISA Q VSS Analog(1) I/O Pin D Q RD Input Mode TRISA WR CK TRISA Q VSS RD Analog(1) PORTA RD Input Mode TRISA To Comparator RD PORTA To A/D Converter Note 1: ANSEL determines Analog Input mode. To Comparator (positive input) To Comparator (VREF-) To A/D Converter (VREF-) To A/D Converter (analog channel) Note 1: ANSEL determines Analog Input mode. DS40001291H-page 44  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 3.2.3.4 RA3/AN3/VREF+/C1IN+ 3.2.3.5 RA4/T0CKI/C1OUT Figure3-4 shows the diagram for this pin. This pin is Figure3-5 shows the diagram for this pin. This pin is configurable to function as one of the following: configurable to function as one of the following: • a general purpose input • a general purpose I/O • an analog input for the ADC • a clock input for Timer0 • a positive voltage reference input for the ADC and • a digital output from Comparator C1 CVREF • a positive analog input to Comparator C1 FIGURE 3-5: BLOCK DIAGRAM OF RA4 FIGURE 3-4: BLOCK DIAGRAM OF RA3 Data Bus C1OUT Enable VDD D Q Data Bus WR CK D Q VDD PORTA Q C1OUT 1 WR CK Q 0 I/O Pin PORTA D Q I/O Pin WR CK D Q TRISA Q VSS TRWIRSA CK Q VSS RD TRISA Analog(1) RD Input Mode TRISA RD PORTA RD PORTA To Timer0 To Comparator (positive input) To Comparator (VREF+) To A/D Converter (VREF+) To A/D Converter (analog channel) Note 1: ANSEL determines Analog Input mode.  2006-2015 Microchip Technology Inc. DS40001291H-page 45

PIC16F882/883/884/886/887 3.2.3.6 RA5/AN4/SS/C2OUT 3.2.3.7 RA6/OSC2/CLKOUT Figure3-6 shows the diagram for this pin. This pin is Figure3-7 shows the diagram for this pin. This pin is configurable to function as one of the following: configurable to function as one of the following: • a general purpose I/O • a general purpose I/O • an analog input for the ADC • a crystal/resonator connection • a slave select input • a clock output • a digital output from Comparator C2 FIGURE 3-7: BLOCK DIAGRAM OF RA6 FIGURE 3-6: BLOCK DIAGRAM OF RA5 Oscillator Data Bus Circuit Data Bus C2OUT OSC2 Enable CLKOUT VDD VDD Enable D Q POWRRTA CK Q C2OUT 1 D Q FOSC/4 1 WR CK 0 I/O Pin 0 I/O Pin PORTA Q CLKOUT D Q Enable TRWIRSA CK Q VSS D Q INTOSCIO/ VSS Analog(1) WR CK EXTRCIO/EC(1) RD Input Mode TRISA Q TRISA CLKOUT RD Enable TRISA RD PORTA RD PORTA To SS Input To A/D Converter Note 1: ANSEL determines Analog Input mode. Note1: With I/O option. DS40001291H-page 46  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 3.2.3.8 RA7/OSC1/CLKIN Figure3-8 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a crystal/resonator connection • a clock input FIGURE 3-8: BLOCK DIAGRAM OF RA7 Data Bus Oscillator Circuit OSC1 VDD D Q WR CK Q PORTA I/O Pin D Q WR CK TRISA Q VSS INTOSC RD Mode TRISA RD PORTA CLKIN TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 104 ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 41 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 89 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 90 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC 92 PCON — — ULPWUE SBOREN — — POR BOR 37 OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 31 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 40 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 177 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 40 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.  2006-2015 Microchip Technology Inc. DS40001291H-page 47

PIC16F882/883/884/886/887 3.3 PORTB and TRISB Registers 3.4.1 ANSELH REGISTER PORTB is an 8-bit wide, bidirectional port. The The ANSELH register (Register3-4) is used to corresponding data direction register is TRISB configure the Input mode of an I/O pin to analog. (Register3-6). Setting a TRISB bit (= 1) will make the Setting the appropriate ANSELH bit high will cause all corresponding PORTB pin an input (i.e., put the digital reads on the pin to be read as ‘0’ and allow corresponding output driver in a High-Impedance mode). analog functions on the pin to operate correctly. Clearing a TRISB bit (= 0) will make the corresponding The state of the ANSELH bits has no affect on digital PORTB pin an output (i.e., enable the output driver and output functions. A pin with TRIS clear and ANSELH put the contents of the output latch on the selected pin). set will still operate as a digital output, but the Input Example3-3 shows how to initialize PORTB. mode will be analog. This can cause unexpected Reading the PORTB register (Register3-5) reads the behavior when executing read-modify-write status of the pins, whereas writing to it will write to the instructions on the affected port. PORT latch. All write operations are read-modify-write 3.4.2 WEAK PULL-UPS operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written Each of the PORTB pins has an individually configurable to the PORT data latch. internal weak pull-up. Control bits WPUB<7:0> enable or The TRISB register (Register3-6) controls the PORTB disable each pull-up (see Register3-7). Each weak pin output drivers, even when they are being used as pull-up is automatically turned off when the port pin is analog inputs. The user should ensure the bits in the configured as an output. All pull-ups are disabled on a TRISB register are maintained set when using them as Power-on Reset by the RBPU bit of the OPTION register. analog inputs. I/O pins configured as analog input always 3.4.3 INTERRUPT-ON-CHANGE read ‘0’. Example3-3 shows how to initialize PORTB. All of the PORTB pins are individually configurable as an EXAMPLE 3-3: INITIALIZING PORTB interrupt-on-change pin. Control bits IOCB<7:0> enable BANKSELPORTB ; or disable the interrupt function for each pin. Refer to CLRF PORTB ;Init PORTB Register3-8. The interrupt-on-change feature is BANKSELTRISB ; disabled on a Power-on Reset. MOVLW B‘11110000’;Set RB<7:4> as inputs For enabled interrupt-on-change pins, the present value ;and RB<3:0> as outputs is compared with the old value latched on the last read MOVWF TRISB ; of PORTB to determine which bits have changed or mismatched the old value. The ‘mismatch’ outputs of the last read are OR’d together to set the PORTB Note: The ANSELH register must be initialized Change Interrupt flag bit (RBIF) in the INTCON register. to configure an analog channel as a digital This interrupt can wake the device from Sleep. The user, input. Pins configured as analog inputs in the Interrupt Service Routine, clears the interrupt by: will read ‘0’. a) Any read or write of PORTB. This will end the mismatch condition. 3.4 Additional PORTB Pin Functions b) Clear the flag bit RBIF. PORTB pins RB<7:0> on the device family device have A mismatch condition will continue to set flag bit RBIF. an interrupt-on-change option and a weak pull-up Reading or writing PORTB will end the mismatch option. The following three sections describe these condition and allow flag bit RBIF to be cleared. The latch PORTB pin functions. holding the last read value is not affected by a MCLR nor Every PORTB pin on this device family has an Brown-out Reset. After these Resets, the RBIF flag will interrupt-on-change option and a weak pull-up option. continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not getset. Furthermore, since a read or write on a port affects all bits of that port, care must be taken when using multiple pins in Interrupt-on-Change mode. Changes on one pin may not be seen while servicing changes on another pin. DS40001291H-page 48  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 REGISTER 3-4: ANSELH: ANALOG SELECT HIGH REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANS<13:8>: Analog Select bits Analog select between analog or digital function on pins AN<13:8>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 3-5: PORTB: PORTB REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RB<7:0>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 3-6: TRISB: PORTB TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output  2006-2015 Microchip Technology Inc. DS40001291H-page 49

PIC16F882/883/884/886/887 REGISTER 3-7: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 WPUB<7:0>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled Note1: Global RBPU bit of the OPTION register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. REGISTER 3-8: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled DS40001291H-page 50  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 3.4.4 PIN DESCRIPTIONS AND FIGURE 3-9: BLOCK DIAGRAM OF DIAGRAMS RB<3:0> Each PORTB pin is multiplexed with other functions. The Analog(1) pins and their combined functions are briefly described Data Bus Input Mode here. For specific information about individual functions D Q VDD such as the SSP, I2C or interrupts, refer to the appropriate WR CK Q Weak section in this data sheet. WPUB 3.4.4.1 RB0/AN12/INT RD RBPU WPUB Figure3-9 shows the diagram for this pin. This pin is configurable to function as one of the following: CCP1OUT Enable VDD • a general purpose I/O D Q CCP1OUT 1 • an analog input for the ADC WR CK Q PORTB • an external edge triggered interrupt 0 3.4.4.2 RB1/AN10/P1C(1)/C12IN3- I/O Pin D Q Figure3-9 shows the diagram for this pin. This pin is WR CK configurable to function as one of the following: TRISB Q VSS • a general purpose I/O RD Analog(1) • an analog input for the ADC TRISB Input Mode (1) • a PWM output • an analog input to Comparator C1 or C2 RD PORTB Note1: P1C is available on PIC16F882/883/886 D Q only. Q D WR CK Q IOCB 3.4.4.3 RB2/AN8/P1B(1) EN Q3 RD Figure3-9 shows the diagram for this pin. This pin is IOCB Q D configurable to function as one of the following: EN • a general purpose I/O Interrupt-on- Change • an analog input for the ADC (1) • a PWM output RD PORTB Note1: P1B is available on PIC16F882/883/886 only. RB0/INT RB3/PGM 3.4.4.4 RB3/AN9/PGM/C12IN2- To A/D Converter Figure3-9 shows the diagram for this pin. This pin is configurable to function as one of the following: To Comparator (RB1, RB3) • a general purpose I/O Note 1: ANSELH determines Analog Input mode. • an analog input for the ADC • Low-voltage In-Circuit Serial Programming enable pin • an analog input to Comparator C1 or C2  2006-2015 Microchip Technology Inc. DS40001291H-page 51

PIC16F882/883/884/886/887 3.4.4.5 RB4/AN11/P1D(1) Figure3-10 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC (1) • a PWM output Note1: P1D is available on PIC16F882/883/886 only. 3.4.4.6 RB5/AN13/T1G Figure3-10 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • a Timer1 gate input 3.4.4.7 RB6/ICSPCLK Figure3-10 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • In-Circuit Serial Programming clock 3.4.4.8 RB7/ICSPDAT Figure3-10 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • In-Circuit Serial Programming data DS40001291H-page 52  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 3-10: BLOCK DIAGRAM OF RB<7:4> Analog(1) Input Mode VDD Data Bus D Q Weak WR CK Q WPUB RBPU RD CCP1OUT Enable WPUB VDD D Q CCP1OUT 101 WR CK Q PORTB 010 I/O Pin D Q WR CK VSS TRISB Q RD TRISB Analog(1) Input Mode RD PORTB D Q Q D ICSP™(2) WR CK Q IOCB EN Q3 RD IOCB Q D EN Interrupt-on- Change RD PORTB To Timer1 T1G(3) To A/D Converter To ICSPCLK (RB6) and ICSPDAT (RB7) Available on PIC16F882/PIC16F883/PIC16F886 only. Note 1: ANSELH determines Analog Input mode. 2: Applies to RB<7:6> pins only). 3: Applies to RB5 pin only. TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELH — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 49 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 122 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC 92 IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 50 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 31 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 49 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 49 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 50 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by PORTB.  2006-2015 Microchip Technology Inc. DS40001291H-page 53

PIC16F882/883/884/886/887 3.5 PORTC and TRISC Registers The TRISC register (Register3-10) controls the PORTC pin output drivers, even when they are being used as PORTC is a 8-bit wide, bidirectional port. The analog inputs. The user should ensure the bits in the corresponding data direction register is TRISC TRISC register are maintained set when using them as (Register3-10). Setting a TRISC bit (= 1) will make the analog inputs. I/O pins configured as analog input always corresponding PORTC pin an input (i.e., put the read ‘0’. corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding EXAMPLE 3-4: INITIALIZING PORTC PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). BANKSELPORTC ; Example3-4 shows how to initialize PORTC. CLRF PORTC ;Init PORTC BANKSELTRISC ; Reading the PORTC register (Register3-9) reads the MOVLW B‘00001100’ ;Set RC<3:2> as inputs status of the pins, whereas writing to it will write to the MOVWF TRISC ;and set RC<7:4,1:0> PORT latch. All write operations are read-modify-write ;as outputs operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. REGISTER 3-9: PORTC: PORTC REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 3-10: TRISC: PORTC TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1(1) R/W-1(1) TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TRISC<7:0>: PORTC Tri-State Control bit 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output Note 1: TRISC<1:0> always reads ‘1’ in LP Oscillator mode. DS40001291H-page 54  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 3.5.1 RC0/T1OSO/T1CKI 3.5.3 RC2/P1A/CCP1 Figure3-11 shows the diagram for this pin. This pin is Figure3-13 shows the diagram for this pin. This pin is configurable to function as one of the following: configurable to function as one of the following: • a general purpose I/O • a general purpose I/O • a Timer1 oscillator output • a PWM output • a Timer1 clock input • a Capture input and Compare output for Comparator C1 FIGURE 3-11: BLOCK DIAGRAM OF RC0 FIGURE 3-13: BLOCK DIAGRAM OF RC2 Data Bus Timer1 Oscillator T1OSCEN Circuit Data bus VDD CCP1CON D Q VDD D Q WR CK Q PORTC WR CK PORTC Q CCP1/P1A 01 I/O Pin D Q 10 I/O Pin D Q WR CK TRISC Q VSS WR CK TRISC Q VSS RD TRISC RD TRISC RD PORTC RD PORTC To Enhanced CCP1 To Timer1 clock input 3.5.2 RC1/T1OSI/CCP2 Figure3-12 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 oscillator input • a Capture input and Compare/PWM output for Comparator C2 FIGURE 3-12: BLOCK DIAGRAM OF RC1 T1OSCEN Timer1 Oscillator Data Bus T1OSI Circuit CCP2CON VDD D Q POWRRTC CK Q CCP2 01 10 I/O Pin D Q WR CK TRISC Q VSS T1OSCEN RD TRISC RD PORTC To CCP2  2006-2015 Microchip Technology Inc. DS40001291H-page 55

PIC16F882/883/884/886/887 3.5.4 RC3/SCK/SCL 3.5.6 RC5/SDO Figure3-14 shows the diagram for this pin. This pin is Figure3-16 shows the diagram for this pin. This pin is configurable to function as one of the following: configurable to function as one of the following: • a general purpose I/O • a general purpose I/O • a SPI clock • a serial data output • an I2C™ clock FIGURE 3-16: BLOCK DIAGRAM OF RC5 FIGURE 3-14: BLOCK DIAGRAM OF RC3 Port/SDO Select Data Bus Data Bus SDO 01 SSPEN D Q VDD D Q 10 VDD SCK 01 POWRRTC CK Q POWRRTC CK Q I/O Pin 10 I/O Pin D Q D Q TRWIRSC CK Q VSS TRWIRSC CK Q VSS RD RD TRISC TRISC RD RD PORTC PORTC To SSPSR 3.5.5 RC4/SDI/SDA Figure3-15 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a SPI data I/O • an I2C data I/O FIGURE 3-15: BLOCK DIAGRAM OF RC4 Data Bus SSPEN VDD D Q SDI/SDA 01 WR CK Q PORTC 10 I/O Pin D Q WR CK TRISC Q VSS RD TRISC RD PORTC To SSPSR DS40001291H-page 56  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 3.5.7 RC6/TX/CK 3.5.8 RC7/RX/DT Figure3-17 shows the diagram for this pin. This pin is Figure3-18 shows the diagram for this pin. This pin is configurable to function as one of the following: configurable to function as one of the following: • a general purpose I/O • a general purpose I/O • an asynchronous serial output • an asynchronous serial input • a synchronous clock I/O • a synchronous serial data I/O FIGURE 3-17: BLOCK DIAGRAM OF RC6 FIGURE 3-18: BLOCK DIAGRAM OF RC7 SPEN SPEN TXEN SYNC Data Bus SYNC Data Bus EUSACRKT D Q EUSART VDD 01 DT EUSART WR CK 01 TX Q 10 VDD PORTC D Q 10 01 I/O Pin WR CK Q D Q PORTC 10 WR CK I/O Pin TRISC Q VSS D Q RD TRWIRSC CK Q VSS TRISC RD RD TRISC PORTC EUSART RX/DT RD PORTC TABLE 3-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 122 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 123 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 54 PSTRCON — — — STRSYNC STRD STRC STRB STRA 144 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 158 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 177 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 81 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 54 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.  2006-2015 Microchip Technology Inc. DS40001291H-page 57

PIC16F882/883/884/886/887 3.6 PORTD and TRISD Registers The TRISD register (Register3-12) controls the PORTD pin output drivers, even when they are being used as PORTD(1) is a 8-bit wide, bidirectional port. The analog inputs. The user should ensure the bits in the corresponding data direction register is TRISD TRISD register are maintained set when using them as (Register3-12). Setting a TRISD bit (= 1) will make the analog inputs. I/O pins configured as analog input always corresponding PORTD pin an input (i.e., put the read ‘0’. corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding EXAMPLE 3-5: INITIALIZING PORTD PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example3-5 shows how to initialize PORTD. BANKSELPORTD ; Reading the PORTD register (Register3-11) reads the CLRF PORTD ;Init PORTD status of the pins, whereas writing to it will write to the BANKSELTRISD ; PORT latch. All write operations are read-modify-write MOVLW B‘00001100’ ;Set RD<3:2> as inputs operations. Therefore, a write to a port implies that the MOVWF TRISD ;and set RD<7:4,1:0> port pins are read, this value is modified and then written ;as outputs to the PORT data latch. Note1: PORTD is available on PIC16F884/887 only. REGISTER 3-11: PORTD: PORTD REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 3-12: TRISD: PORTD TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TRISD<7:0>: PORTD Tri-State Control bit 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output DS40001291H-page 58  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 3.6.1 RD<4:0> 3.6.3 RD6/P1C(1) Figure3-19 shows the diagram for these pins. These Figure3-20 shows the diagram for this pin. This pin is pins are configured to function as general purpose configurable to function as one of the following: I/O’s. • a general purpose I/O Note: RD<4:0> is available on PIC16F884/887 • a PWM output only. Note1: RD6/P1C is available on PIC16F884/887 only. See RB1/AN10/P1C/C12IN3- for FIGURE 3-19: BLOCK DIAGRAM OF this function on PIC16F882/883/886. RD<4:0> 3.6.4 RD7/P1D(1) Data Bus Figure3-20 shows the diagram for this pin. This pin is VDD configurable to function as one of the following: D Q • a general purpose I/O WR CK Q PORTD • a PWM output I/O Pin Note1: RD7/P1D is available on PIC16F884/887 D Q only. See RB4/AN11/P1D for this function WR CK on PIC16F882/883/886. TRISD Q VSS FIGURE 3-20: BLOCK DIAGRAM OF RD TRISD RD<7:5> RD PORTD Data Bus PSTRCON VDD D Q 3.6.2 RD5/P1B(1) POWRRTD CK Q CCP1 01 Figure3-20 shows the diagram for this pin. This pin is configurable to function as one of the following: 10 I/O Pin D Q • a general purpose I/O WR CK • a PWM output TRISD Q VSS Note1: RD5/P1B is available on PIC16F884/887 RD only. See RB2/AN8/P1B for this function TRISD on PIC16F882/883/886. RD PORTD TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 58 PSTRCON — — — STRSYNC STRD STRC STRB STRA 144 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 58 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.  2006-2015 Microchip Technology Inc. DS40001291H-page 59

PIC16F882/883/884/886/887 3.7 PORTE and TRISE Registers The TRISE register (Register3-14) controls the PORTE pin output drivers, even when they are being used as PORTE(1) is a 4-bit wide, bidirectional port. The analog inputs. The user should ensure the bits in the corresponding data direction register is TRISE. Setting a TRISE register are maintained set when using them as TRISE bit (= 1) will make the corresponding PORTE pin analog inputs. I/O pins configured as analog input always an input (i.e., put the corresponding output driver in a read ‘0’. High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., Note: The ANSEL register must be initialized to enable the output driver and put the contents of the configure an analog channel as a digital output latch on the selected pin). The exception is RE3, input. Pins configured as analog inputs which is input only and its TRIS bit will always read as will read ‘0’. ‘1’. Example3-6 shows how to initialize PORTE. EXAMPLE 3-6: INITIALIZING PORTE Reading the PORTE register (Register3-13) reads the status of the pins, whereas writing to it will write to the BANKSELPORTE ; PORT latch. All write operations are read-modify-write CLRF PORTE ;Init PORTE operations. Therefore, a write to a port implies that the BANKSELANSEL ; port pins are read, this value is modified and then CLRF ANSEL ;digital I/O written to the PORT data latch. RE3 reads ‘0’ when BCF STATUS,RP1 ;Bank 1 MCLRE = 1. BANKSELTRISE ; MOVLW B‘00001100’ ;Set RE<3:2> as inputs Note1: RE<2:0> pins are available on MOVWF TRISE ;and set RE<1:0> PIC16F884/887 only. ;as outputs REGISTER 3-13: PORTE: PORTE REGISTER U-0 U-0 U-0 U-0 R-x R/W-x R/W-x R/W-x — — — — RE3 RE2 RE1 RE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 RD<3:0>: PORTE General Purpose I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 3-14: TRISE: PORTE TRI-STATE REGISTER U-0 U-0 U-0 U-0 R-1(1) R/W-1 R/W-1 R/W-1 — — — — TRISE3 TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 TRISE<3:0>: PORTE Tri-State Control bit 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output Note 1: TRISE<3> always reads ‘1’. DS40001291H-page 60  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 3.7.1 RE0/AN5(1) 3.7.4 RE3/MCLR/VPP This pin is configurable to function as one of the Figure3-22 shows the diagram for this pin. This pin is following: configurable to function as one of the following: • a general purpose I/O • a general purpose input • an analog input for the ADC • as Master Clear Reset with weak pull-up Note1: RE0/AN5 is available on PIC16F884/887 FIGURE 3-22: BLOCK DIAGRAM OF RE3 only. VDD 3.7.2 RE1/AN6(1) MCLRE Weak This pin is configurable to function as one of the following: Data Bus MCLRE • a general purpose I/O Reset Input Pin • an analog input for the ADC RD VSS TRISE Note1: RE1/AN6 is available on PIC16F884/887 MCLRE VSS only. RD PORTE 3.7.3 RE2/AN7(1) This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC Note1: RE2/AN7 is available on PIC16F884/887 only. FIGURE 3-21: BLOCK DIAGRAM OF RE<2:0> Data Bus VDD D Q WR CK Q PORTE I/O Pin D Q WR CK TRISE Q VSS Analog(1) RD Input Mode TRISE RD PORTE To A/D Converter Note 1: ANSEL determines Analog Input mode.  2006-2015 Microchip Technology Inc. DS40001291H-page 61

PIC16F882/883/884/886/887 TABLE 3-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 41 PORTE — — — — RE3 RE2 RE1 RE0 60 TRISE — — — — TRISE3 TRISE2 TRISE1 TRISE0 60 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE DS40001291H-page 62  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 4.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of eight FAIL-SAFE CLOCK MONITOR) clock modes. 1. EC – External clock with I/O on OSC2/CLKOUT. 4.1 Overview 2. LP – 32kHz Low-Power Crystal mode. 3. XT – Medium Gain Crystal or Ceramic Resonator The oscillator module has a wide variety of clock Oscillator mode. sources and selection features that allow it to be used 4. HS – High Gain Crystal or Ceramic Resonator in a wide range of applications while maximizing perfor- mode. mance and minimizing power consumption. Figure4-1 illustrates a block diagram of the oscillator module. 5. RC – External Resistor-Capacitor (RC) with FOSC/4 output on OSC2/CLKOUT. Clock sources can be configured from external 6. RCIO – External Resistor-Capacitor (RC) with oscillators, quartz crystal resonators, ceramic resonators I/O on OSC2/CLKOUT. and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two 7. INTOSC – Internal oscillator with FOSC/4 output on OSC2 and I/O on OSC1/CLKIN. internal oscillators, with a choice of speeds selectable via software. Additional clock features include: 8. INTOSCIO – Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT. • Selectable system clock source between external or internal via software. Clock Source modes are configured by the FOSC<2:0> • Two-Speed Start-up mode, which minimizes bits in the Configuration Word Register 1 (CONFIG1). latency between external oscillator start-up and The internal clock can be generated from two internal code execution. oscillators. The HFINTOSC is a calibrated high- frequency oscillator. The LFINTOSC is an uncalibrated • Fail-Safe Clock Monitor (FSCM) designed to low-frequency oscillator. detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. FIGURE 4-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FOSC<2:0> (Configuration Word Register 1) External Oscillator SCS<0> (OSCCON Register) OSC2 Sleep LP, XT, HS, RC, RCIO, EC OSC1 IRCF<2:0> UX (OSCCON Register) M System Clock (CPU and Peripherals) 8 MHz 111 INTOSC Internal Oscillator 4 MHz 110 2 MHz 101 er 1 MHz HFINTOSC cal 100 UX 8 MHz sts 500 kHz 011 M o P 250 kHz 010 125 kHz 001 LFINTOSC 31 kHz 000 31 kHz Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)  2006-2015 Microchip Technology Inc. DS40001291H-page 63

PIC16F882/883/884/886/887 4.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure4-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • Frequency Status bits (HTS, LTS) • System clock control bits (OSTS, SCS) REGISTER DEFINITIONS: OSCILLATOR CONTROL REGISTER 4-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0 — IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8MHz 110 = 4MHz (default) 101 = 2MHz 100 = 1MHz 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31kHz (LFINTOSC) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC) bit 2 HTS: HFINTOSC Status bit (High Frequency – 8MHz to 125kHz) 1 = HFINTOSC is stable 0 = HFINTOSC is not stable bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31kHz) 1 = LFINTOSC is stable 0 = LFINTOSC is not stable bit 0 SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> of the CONFIG1 register Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled. DS40001291H-page 64  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 4.3 Clock Source Modes 4.4 External Clock Modes Clock Source modes can be classified as external or 4.4.1 OSCILLATOR START-UP TIMER internal. (OST) • External Clock modes rely on external circuitry for If the oscillator module is configured for LP, XT or HS the clock source. Examples are: oscillator mod- modes, the Oscillator Start-up Timer (OST) counts ules (EC mode), quartz crystal resonators or 1024 oscillations from OSC1. This occurs following a ceramic resonators (LP, XT and HS modes) and Power-on Reset (POR) and when the Power-up Timer Resistor-Capacitor (RC) mode circuits. (PWRT) has expired (if configured), or a wake-up from • Internal clock sources are contained internally Sleep. During this time, the program counter does not within the oscillator module. The oscillator module increment and program execution is suspended. The has two internal oscillators: the 8MHz High- OST ensures that the oscillator circuit, using a quartz Frequency Internal Oscillator (HFINTOSC) and crystal resonator or ceramic resonator, has started and the 31kHz Low-Frequency Internal Oscillator is providing a stable system clock to the oscillator (LFINTOSC). module. When switching between clock sources, a The system clock can be selected between external or delay is required to allow the new clock to stabilize. internal clock sources via the System Clock Select These oscillator delays are shown in Table4-1. (SCS) bit of the OSCCON register. See Section4.6 In order to minimize latency between external oscillator “Clock Switching” for additional information. start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section4.7 “Two- Speed Clock Start-up Mode”). TABLE 4-1: OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Oscillator Delay LFINTOSC 31kHz Sleep/POR Oscillator Warm-up Delay (TWARM) HFINTOSC 125kHz to 8MHz Sleep/POR EC, RC DC – 20MHz 2 cycles LFINTOSC (31kHz) EC, RC DC – 20MHz 1 cycle of each Sleep/POR LP, XT, HS 32kHz to 20MHz 1024 Clock Cycles (OST) LFINTOSC (31kHz) HFINTOSC 125kHz to 8MHz 1s (approx.) 4.4.2 EC MODE FIGURE 4-2: EXTERNAL CLOCK (EC) MODE OPERATION The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is Clock from OSC1/CLKIN connected to the OSC1 input and the OSC2 is available Ext. System for general purpose I/O. Figure4-2 shows the pin PIC® MCU connections for EC mode. I/O OSC2/CLKOUT(1) The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up Note 1: Alternate pin functions are listed in the from Sleep. Because the PIC® MCU design is fully Section1.0 “Device Overview”. static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.  2006-2015 Microchip Technology Inc. DS40001291H-page 65

PIC16F882/883/884/886/887 4.4.3 LP, XT, HS MODES Note 1: Quartz crystal characteristics vary The LP, XT and HS modes support the use of quartz according to type, package and crystal resonators or ceramic resonators connected to manufacturer. The user should consult the OSC1 and OSC2 (Figure4-3). The mode selects a low, manufacturer data sheets for specifications medium or high gain setting of the internal inverter- and recommended application. amplifier to support various resonator types and speed. 2: Always verify oscillator performance over LP Oscillator mode selects the lowest gain setting of the the VDD and temperature range that is internal inverter-amplifier. LP mode current consumption expected for the application. is the least of the three modes. This mode is designed to 3: For oscillator design assistance, reference drive only 32.768 kHz tuning-fork type crystals (watch the following Microchip Applications Notes: crystals). • AN826, “Crystal Oscillator Basics and XT Oscillator mode selects the intermediate gain Crystal Selection for rfPIC® and PIC® setting of the internal inverter-amplifier. XT mode Devices” (DS00826) current consumption is the medium of the three modes. • AN849, “Basic PIC® Oscillator Design” This mode is best suited to drive resonators with a (DS00849) medium drive level specification. • AN943, “Practical PIC® Oscillator HS Oscillator mode selects the highest gain setting of the Analysis and Design” (DS00943) internal inverter-amplifier. HS mode current consumption • AN949, “Making Your Oscillator Work” is the highest of the three modes. This mode is best (DS00949) suited for resonators that require a high drive setting. Figure4-3 and Figure4-4 show typical circuits for FIGURE 4-4: CERAMIC RESONATOR quartz crystal and ceramic resonators, respectively. OPERATION (XT OR HS MODE) FIGURE 4-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) PIC® MCU OSC1/CLKIN PIC® MCU C1 To Internal OSC1/CLKIN Logic C1 To Internal RP(3) RF(2) Sleep Logic Quartz RF(2) Sleep Crystal C2 Ceramic RS(1) OSC2/CLKOUT Resonator C2 RS(1) OSC2/CLKOUT Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. Note 1: A series resistor (RS) may be required for 2: The value of RF varies with the Oscillator mode quartz crystals with low drive level. selected (typically between 2M to 10M. 2: The value of RF varies with the Oscillator mode 3: An additional parallel feedback resistor (RP) selected (typically between 2M to 10M. may be required for proper ceramic resonator operation. DS40001291H-page 66  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 4.4.4 EXTERNAL RC MODES 4.5 Internal Clock Modes The external Resistor-Capacitor (RC) modes support The oscillator module has two independent, internal the use of an external RC circuit. This allows the oscillators that can be configured or selected as the designer maximum flexibility in frequency choice while system clock source. keeping costs to a minimum when clock accuracy is not 1. The HFINTOSC (High-Frequency Internal required. There are two modes: RC and RCIO. Oscillator) is factory calibrated and operates at In RC mode, the RC circuit connects to OSC1. OSC2/ 8MHz. The frequency of the HFINTOSC can be CLKOUT outputs the RC oscillator frequency divided user-adjusted via software using the OSCTUNE by 4. This signal may be used to provide a clock for register (Register4-2). external circuitry, synchronization, calibration, test or 2. The LFINTOSC (Low-Frequency Internal other application requirements. Figure4-5 shows the Oscillator) is uncalibrated and operates at external RC mode connections. 31kHz. FIGURE 4-5: EXTERNAL RC MODES The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register. VDD PIC® MCU The system clock can be selected between external or REXT internal clock sources via the System Clock Selection (SCS) bit of the OSCCON register. See Section4.6 OSC1/CLKIN Internal Clock “Clock Switching” for more information. CEXT 4.5.1 INTOSC AND INTOSCIO MODES VSS The INTOSC and INTOSCIO modes configure the FOSC/4 or OSC2/CLKOUT(1) internal oscillators as the system clock source when I/O(2) the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1). Recommended values: 10 k  REXT  100 k, <3V 3 k  REXT  100 k, 3-5V In INTOSC mode, OSC1/CLKIN is available for general CEXT > 20 pF, 2-5V purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT Note 1: Alternate pin functions are listed in the signal may be used to provide a clock for external Section1.0 “Device Overview”. circuitry, synchronization, calibration, test or other 2: Output depends upon RC or RCIO Clock application requirements. mode. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT In RCIO mode, the RC circuit is connected to OSC1. are available for general purpose I/O. OSC2 becomes an additional general purpose I/O pin. The RC oscillator frequency is a function of the supply 4.5.2 HFINTOSC voltage, the resistor (REXT) and capacitor (CEXT) values The High-Frequency Internal Oscillator (HFINTOSC) is and the operating temperature. Other factors affecting a factory calibrated 8MHz internal clock source. The the oscillator frequency are: frequency of the HFINTOSC can be altered via • threshold voltage variation software using the OSCTUNE register (Register4-2). • component tolerances The output of the HFINTOSC connects to a postscaler • packaging variations in capacitance and multiplexer (see Figure4-1). One of seven The user also needs to take into account variation due frequencies can be selected via software using the to tolerance of external RC components used. IRCF<2:0> bits of the OSCCON register. See Section4.5.4 “Frequency Select Bits (IRCF)” for more information. The HFINTOSC is enabled by selecting any frequency between 8MHz and 125kHz by setting the IRCF<2:0> bits of the OSCCON register000. Then, set the System Clock Source (SCS) bit of the OSCCON register to ‘1’ or enable Two-Speed Start-up by setting the IESO bit in the Configuration Word Register 1 (CONFIG1) to ‘1’. The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not.  2006-2015 Microchip Technology Inc. DS40001291H-page 67

PIC16F882/883/884/886/887 4.5.2.1 OSCTUNE Register When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new The HFINTOSC is factory calibrated but can be frequency. Code execution continues during this shift. adjusted in software by writing to the OSCTUNE There is no indication that the shift has occurred. register (Register4-2). OSCTUNE does not affect the LFINTOSC frequency. The default value of the OSCTUNE register is ‘0’. The Operation of features that depend on the LFINTOSC value is a 5-bit two’s complement number. clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. REGISTER 4-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = • • • 00001 = 00000 = Oscillator module is running at the factory-calibrated frequency. 11111 = • • • 10000 = Minimum frequency DS40001291H-page 68  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 4.5.3 LFINTOSC 4.5.5 HFINTOSC AND LFINTOSC CLOCK SWITCH TIMING The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31kHz internal clock source. When switching between the LFINTOSC and the The output of the LFINTOSC connects to a postscaler HFINTOSC, the new oscillator may already be shut down to save power (see Figure4-6). If this is the case, and multiplexer (see Figure4-1). Select 31kHz, via software, using the IRCF<2:0> bits of the OSCCON there is a delay after the IRCF<2:0> bits of the OSCCON register are modified before the frequency register. See Section4.5.4 “Frequency Select Bits (IRCF)” for more information. The LFINTOSC is also the selection takes place. The LTS and HTS bits of the OSCCON register will reflect the current active status frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). of the LFINTOSC and HFINTOSC oscillators. The timing of a frequency selection is as follows: The LFINTOSC is enabled by selecting 31kHz 1. IRCF<2:0> bits of the OSCCON register are (IRCF<2:0> bits of the OSCCON register=000) as the system clock source (SCS bit of the OSCCON modified. register= 1), or when any of the following are enabled: 2. If the new clock is shut down, a clock start-up delay is started. • Two-Speed Start-up IESO bit of the Configuration 3. Clock switch circuitry waits for a falling edge of Word Register 1 = 1 and IRCF<2:0> bits of the the current clock. OSCCON register = 000 4. CLKOUT is held low and the clock switch • Power-up Timer (PWRT) circuitry waits for a rising edge in the new clock. • Watchdog Timer (WDT) 5. CLKOUT is now connected with the new clock. • Fail-Safe Clock Monitor (FSCM) LTS and HTS bits of the OSCCON register are The LF Internal Oscillator (LTS) bit of the OSCCON updated as required. register indicates whether the LFINTOSC is stable or 6. Clock switch is complete. not. See Figure4-1 for more details. 4.5.4 FREQUENCY SELECT BITS (IRCF) If the internal oscillator speed selected is between The output of the 8MHz HFINTOSC and 31kHz 8MHz and 125kHz, there is no start-up delay before LFINTOSC connects to a postscaler and multiplexer the new frequency is selected. This is because the old (see Figure4-1). The Internal Oscillator Frequency and new frequencies are derived from the HFINTOSC Select bits IRCF<2:0> of the OSCCON register select via the postscaler and multiplexer. the frequency output of the internal oscillators. One of Start-up delay specifications are located in the eight frequencies can be selected via software: oscillator tables of Section17.0 “Electrical • 8 MHz Specifications”. • 4 MHz (Default after Reset) • 2 MHz • 1 MHz • 500 kHz • 250 kHz • 125 kHz • 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 4MHz. The user can modify the IRCF bits to select a different frequency.  2006-2015 Microchip Technology Inc. DS40001291H-page 69

PIC16F882/883/884/886/887 FIGURE 4-6: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <2:0> 0 0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC   IRCF <2:0> 0 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <2:0> = 0 ¼ 0 System Clock DS40001291H-page 70  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 4.6 Clock Switching 4.7 Two-Speed Clock Start-up Mode The system clock source can be switched between Two-Speed Start-up mode provides additional power external and internal clock sources via software using savings by minimizing the latency between external the System Clock Select (SCS) bit of the OSCCON oscillator start-up and code execution. In applications register. that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up 4.6.1 SYSTEM CLOCK SELECT (SCS) BIT time from the time spent awake and can reduce the The System Clock Select (SCS) bit of the OSCCON overall power consumption of the device. register selects the system clock source that is used for This mode allows the application to wake-up from the CPU and peripherals. Sleep, perform a few instructions using the INTOSC • When the SCS bit of the OSCCON register = 0, as the clock source and go back to Sleep without the system clock source is determined by waiting for the primary oscillator to become stable. configuration of the FOSC<2:0> bits in the Note: Executing a SLEEP instruction will abort Configuration Word Register 1 (CONFIG1). the oscillator start-up time and will cause • When the SCS bit of the OSCCON register = 1, the OSTS bit of the OSCCON register to the system clock source is chosen by the internal remain clear. oscillator frequency selected by the IRCF<2:0> bits of the OSCCON register. After a Reset, the When the oscillator module is configured for LP, XT or SCS bit of the OSCCON register is always HS modes, the Oscillator Start-up Timer (OST) is cleared. enabled (see Section4.4.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until Note: Any automatic clock switch, which may 1024 oscillations are counted. Two-Speed Start-up occur from Two-Speed Start-up or Fail- mode minimizes the delay in code execution by Safe Clock Monitor, does not update the operating from the internal oscillator as the OST is SCS bit of the OSCCON register. The user counting. When the OST count reaches 1024 and the can monitor the OSTS bit of the OSCCON OSTS bit of the OSCCON register is set, program register to determine the current system execution switches to the external oscillator. clock source. 4.7.1 TWO-SPEED START-UP MODE 4.6.2 OSCILLATOR START-UP TIME-OUT CONFIGURATION STATUS (OSTS) BIT Two-Speed Start-up mode is configured by the The Oscillator Start-up Time-out Status (OSTS) bit of following settings: the OSCCON register indicates whether the system • IESO (of the Configuration Word Register 1) = 1; clock is running from the external clock source, as Internal/External Switchover bit (Two-Speed defined by the FOSC<2:0> bits in the Configuration Start-up mode enabled). Word Register 1 (CONFIG1), or from the internal clock source. In particular, OSTS indicates that the Oscillator • SCS (of the OSCCON register) = 0. Start-up Timer (OST) has timed out for LP, XT or HS • FOSC<2:0> bits in the Configuration Word modes. Register 1 (CONFIG1) configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two- speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.  2006-2015 Microchip Technology Inc. DS40001291H-page 71

PIC16F882/883/884/886/887 4.7.2 TWO-SPEED START-UP 4.7.3 CHECKING TWO-SPEED CLOCK SEQUENCE STATUS 1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCCON 2. Instructions begin execution by the internal register will confirm if the microcontroller is running oscillator at the frequency set in the IRCF<2:0> from the external clock source, as defined by the bits of the OSCCON register. FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1), or the internal oscillator. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. 5. OSTS is set. 6. System clock held low until the next falling edge of new clock (LP, XT or HS mode). 7. System clock is switched to external clock source. FIGURE 4-7: TWO-SPEED START-UP HFINTOSC TTOST OSC1 0 1 1022 1023 OSC2 Program Counter P C - N PC PC + 1 System Clock DS40001291H-page 72  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 4.8 Fail-Safe Clock Monitor 4.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset, to continue operating should the external oscillator fail. executing a SLEEP instruction or toggling the SCS bit The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bit is toggled, the Oscillator Start-up Timer (OST) has expired. The the OST is restarted. While the OST is running, the FSCM is enabled by setting the FCMEN bit in the device continues to operate from the INTOSC selected Configuration Word Register 1 (CONFIG1). The FSCM in OSCCON. When the OST times out, the Fail-Safe is applicable to all external Oscillator modes (LP, XT, condition is cleared and the device will be operating HS, EC, RC and RCIO). from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. FIGURE 4-8: FSCM BLOCK DIAGRAM 4.8.4 RESET OR WAKE-UP FROM SLEEP Clock Monitor The FSCM is designed to detect an oscillator failure Latch after the Oscillator Start-up Timer (OST) has expired. External S Q The OST is used after waking up from Sleep and after Clock any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as LFINTOSC soon as the Reset or wake-up has completed. When Oscillator ÷ 64 R Q the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing 31 kHz 488 Hz code while the OST is operating. (~32 s) (~2 ms) Note: Due to the wide range of oscillator start-up Sample Clock Clock times, the Fail-Safe circuit is not active Failure during oscillator start-up (i.e., after exiting Detected Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify 4.8.1 FAIL-SAFE DETECTION the oscillator start-up and that the system The FSCM module detects a failed oscillator by clock switchover has successfully comparing the external oscillator to the FSCM sample completed. clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure4-8. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half- cycle of the sample clock elapses before the primary clock goes low. 4.8.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2006-2015 Microchip Technology Inc. DS40001291H-page 73

PIC16F882/883/884/886/887 FIGURE 4-9: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS 64 OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 68 PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 34 PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 36 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. TABLE 4-3: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page CONFIG1(1) 13:8 — — DEBUG LVP FCMEN IESO BOREN 1 BOREN0 206 7:0 CPD CP MCLRE PWRTE WDTE FOSC 2 FOSC 1 FOSC 0 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: See Configuration Word Register 1 (Register14-1) for operation of all register bits. DS40001291H-page 74  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 5.0 TIMER0 MODULE 5.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the When used as a timer, the Timer0 module can be used following features: as either an 8-bit timer or an 8-bit counter. • 8-bit timer/counter register (TMR0) 5.1.1 8-BIT TIMER MODE • 8-bit prescaler (shared with Watchdog Timer) When used as a timer, the Timer0 module will • Programmable internal or external clock source increment every instruction cycle (without prescaler). • Programmable external clock edge selection Timer mode is selected by clearing the T0CS bit of the • Interrupt on overflow OPTION register to ‘0’. Figure5-1 is a block diagram of the Timer0 module. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. 5.1.2 8-BIT COUNTER MODE When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’. FIGURE 5-1: TIMER0/WDT PRESCALER BLOCK DIAGRAM FOSC/4 Data Bus 0 8 1 Sync 1 2 Tcy TMR0 T0CKI 0 pin 0 T0SE T0CS 8-bit Set Flag bit T0IF on Overflow Prescaler PSA 1 8 WDTE PSA SWDTEN PS<2:0> 1 WDT 16-bit Time-out Prescaler 0 16 31kHz Watchdog INTOSC Timer PSA WDTPS<3:0> Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word Register1.  2006-2015 Microchip Technology Inc. DS40001291H-page 75

PIC16F882/883/884/886/887 5.1.3 SOFTWARE PROGRAMMABLE When changing the prescaler assignment from the PRESCALER WDT to the Timer0 module, the following instruction sequence must be executed (see Example5-2). A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer EXAMPLE 5-2: CHANGING PRESCALER (WDT), but not both simultaneously. The prescaler (WDTTIMER0) assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit CLRWDT ;Clear WDT and must be cleared to a ‘0’. ;prescaler There are eight prescaler options for the Timer0 mod- BANKSEL OPTION_REG ; MOVLW b’11110000’ ;Mask TMR0 select and ule ranging from 1:2 to 1:256. The prescale values are ANDWF OPTION_REG,W ;prescaler bits selectable via the PS<2:0> bits of the OPTION register. IORLW b’00000011’ ;Set prescale to 1:16 In order to have a 1:1 prescaler value for the Timer0 MOVWF OPTION_REG ; module, the prescaler must be assigned to the WDT module. 5.1.4 TIMER0 INTERRUPT The prescaler is not readable or writable. When Timer0 will generate an interrupt when the TMR0 assigned to the Timer0 module, all instructions writing to register overflows from FFh to 00h. The T0IF interrupt the TMR0 register will clear the prescaler. flag bit of the INTCON register is set every time the When the prescaler is assigned to WDT, a CLRWDT TMR0 register overflows, regardless of whether or not instruction will clear the prescaler along with the WDT. the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the 5.1.3.1 Switching Prescaler Between T0IE bit of the INTCON register. Timer0 and WDT Modules Note: The Timer0 interrupt cannot wake the As a result of having the prescaler assigned to either processor from Sleep since the timer is Timer0 or the WDT, it is possible to generate an frozen during Sleep. unintended device Reset when switching prescaler values. When changing the prescaler assignment from 5.1.5 USING TIMER0 WITH AN Timer0 to the WDT module, the instruction sequence EXTERNAL CLOCK shown in Example5-1, must be executed. When Timer0 is in Counter mode, the synchronization EXAMPLE 5-1: CHANGING PRESCALER of the T0CKI input and the Timer0 register is accom- (TIMER0WDT) plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the BANKSEL TMR0 ; high and low periods of the external clock source must CLRWDT ;Clear WDT meet the timing requirements as shown in the CLRF TMR0 ;Clear TMR0 and Section17.0 “Electrical Specifications”. ;prescaler BANKSEL OPTION_REG ; BSF OPTION_REG,PSA ;Select WDT CLRWDT ; ; MOVLW b’11111000’ ;Mask prescaler ANDWF OPTION_REG,W ;bits IORLW b’00000101’ ;Set WDT prescaler MOVWF OPTION_REG ;to 1:32 DS40001291H-page 76  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 REGISTER DEFINITIONS: OPTION REGISTER REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits BIT VALUE TMR0 RATE WDT RATE 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Note 1: A dedicated 16-bit WDT postscaler is available. See Section14.5 “Watchdog Timer (WDT)” for more information. TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page TMR0 Timer0 Module Register 75 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 77 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 40 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.  2006-2015 Microchip Technology Inc. DS40001291H-page 77

PIC16F882/883/884/886/887 6.0 TIMER1 MODULE WITH GATE 6.1 Timer1 Operation CONTROL The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register The Timer1 module is a 16-bit timer/counter with the pair. Writes to TMR1H or TMR1L directly update the following features: counter. • 16-bit timer/counter register pair (TMR1H:TMR1L) When used with an internal clock source, the module is • Programmable internal or external clock source a timer. When used with an external clock source, the • 3-bit prescaler module can be used as either a timer or counter. • Optional LP oscillator • Synchronous or asynchronous operation 6.2 Clock Source Selection • Timer1 gate (count enable) via comparator or The TMR1CS bit of the T1CON register is used to select T1G pin the clock source. When TMR1CS = 0, the clock source • Interrupt on overflow is FOSC/4. When TMR1CS = 1, the clock source is • Wake-up on overflow (external clock, supplied externally. Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with ECCP) Clock Source TMR1CS • Comparator output synchronization to Timer1 FOSC/4 0 clock T1CKI pin 1 Figure6-1 is a block diagram of the Timer1 module. FIGURE 6-1: TIMER1 BLOCK DIAGRAM TMR1GE T1GINV TMR1ON Set flag bit TMR1IF on To C2 Comparator Module Overflow TMR1(2) Timer1 Clock Synchronized EN 0 clock input TMR1H TMR1L 1 Oscillator (1) T1SYNC T1OSO/T1CKI 1 Prescaler Synchronize(3) 1, 2, 4, 8 det 0 T1OSI 2 T1CKPS<1:0> TMR1CS T1G 1 INTOSC SYNCC2OUT(4) 0 Without CLKOUT T1OSCEN FOSC/4 Internal T1GSS Clock Note 1: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 4: SYNCC2OUT is synchronized when the C2SYNC bit of the CM2CON1 register is set. DS40001291H-page 78  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 6.2.1 INTERNAL CLOCK SOURCE 6.5 Timer1 Operation in Asynchronous Counter Mode When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples If control bit T1SYNC of the T1CON register is set, the of FOSC as determined by the Timer1 prescaler. external clock input is not synchronized. The timer continues to increment asynchronous to the internal 6.2.2 EXTERNAL CLOCK SOURCE phase clocks. The timer will continue to run during When the external clock source is selected, the Timer1 Sleep and can generate an interrupt on overflow, module may work as a timer or a counter. which will wake-up the processor. However, special When counting, Timer1 is incremented on the rising precautions in software are needed to read/write the edge of the external clock input T1CKI. In addition, the timer (see Section6.5.1 “Reading and Writing Counter mode clock can be synchronized to the Timer1 in Asynchronous Counter Mode”). microcontroller system clock or run asynchronously. Note: When switching from synchronous to If an external clock oscillator is needed (and the asynchronous operation, it is possible to microcontroller is using the INTOSC without CLKOUT), skip an increment. When switching from Timer1 can use the LP oscillator as a clock source. asynchronous to synchronous operation, it is possible to produce a single spurious In Counter mode, a falling edge must be registered by increment. the counter prior to the first incrementing rising edge after one or more of the following conditions (see 6.5.1 READING AND WRITING TIMER1 IN Figure6-2): ASYNCHRONOUS COUNTER • Timer1 is enabled after POR or BOR Reset MODE • A write to TMR1H or TMR1L Reading TMR1H or TMR1L while the timer is running • T1CKI is high when Timer1 is disabled and when from an external asynchronous clock will ensure a valid Timer1 is re-enabled T1CKI is low. read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 6.3 Timer1 Prescaler 8-bit values itself, poses certain problems, since the Timer1 has four prescaler options allowing 1, 2, 4 or 8 timer may overflow between the reads. divisions of the clock input. The T1CKPS bits of the For writes, it is recommended that the user simply stop T1CON register control the prescale counter. The the timer and write the desired values. A write prescale counter is not directly readable or writable; contention may occur by writing to the timer registers, however, the prescaler counter is cleared upon a write to while the register is incrementing. This may produce an TMR1H or TMR1L. unpredictable value in the TMR1H:TTMR1L register pair. 6.4 Timer1 Oscillator 6.6 Timer1 Gate A low-power 32.768kHz oscillator is built-in between pins T1OSI (input) and T1OSO (amplifier output). The Timer1 gate source is software configurable to be the oscillator is enabled by setting the T1OSCEN control T1G pin or the output of Comparator C2. This allows the bit of the T1CON register. The oscillator will continue to device to directly time external events using T1G or run during Sleep. analog events using Comparator C2. See the CM2CON1 register (Register8-3) for selecting the The Timer1 oscillator is identical to the LP oscillator. Timer1 gate source. This feature can simplify the The user must provide a software time delay to ensure software for a Delta-Sigma A/D converter and many proper oscillator start-up. other applications. For more information on Delta-Sigma TRISC0 and TRISC1 bits are set when the Timer1 A/D converters, see the Microchip web site oscillator is enabled. RC0 and RC1 bits read as ‘0’ and (www.microchip.com). TRISC0 and TRISC1 bits read as ‘1’. Note: TMR1GE bit of the T1CON register must Note: The oscillator requires a start-up and be set to use the Timer1 gate. stabilization time before use. Thus, T1OSCEN should be set and a suitable Timer1 gate can be inverted using the T1GINV bit of delay observed prior to enabling Timer1. the T1CON register, whether it originates from the T1G pin or Comparator C2 output. This configures Timer1 to measure either the active-high or active-low time between events.  2006-2015 Microchip Technology Inc. DS40001291H-page 79

PIC16F882/883/884/886/887 6.7 Timer1 Interrupt In Compare mode, an event is triggered when the value CCPRxH:CCPRxL register pair matches the value in The Timer1 register pair (TMR1H:TMR1L) increments the TMR1H:TMR1L register pair. This event can be a to FFFFh and rolls over to 0000h. When Timer1 rolls Special Event Trigger. over, the Timer1 interrupt flag bit of the PIR1 register is See Section11.0 “Capture/Compare/PWM Modules set. To enable the interrupt on rollover, you must set (CCP1 and CCP2)” for more information. these bits: • Timer1 interrupt enable bit of the PIE1 register 6.10 ECCP Special Event Trigger • PEIE bit of the INTCON register • GIE bit of the INTCON register If an ECCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This The interrupt is cleared by clearing the TMR1IF bit in special event does not cause a Timer1 interrupt. The the Interrupt Service Routine. ECCP module may still be configured to generate a Note: The TMR1H:TTMR1L register pair and ECCP interrupt. the TMR1IF bit should be cleared before In this mode of operation, the CCPRxH:CCPRxL enabling interrupts. register pair effectively becomes the period register for Timer1. 6.8 Timer1 Operation During Sleep Timer1 should be synchronized to the FOSC to utilize the Special Event Trigger. Asynchronous operation of Timer1 can only operate during Sleep when setup in Timer1 can cause a Special Event Trigger to be Asynchronous Counter mode. In this mode, an external missed. crystal or clock source can be used to increment the counter. To set up the timer to wake the device: In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the ECCP, the write • TMR1ON bit of the T1CON register must be set will take precedence. • TMR1IE bit of the PIE1 register must be set For more information, see Section11.0 “Capture/ • PEIE bit of the INTCON register must be set Compare/PWM Modules (CCP1 and CCP2)”. The device will wake-up on an overflow and execute the next instruction. If the GIE bit of the INTCON 6.11 Comparator Synchronization register is set, the device will call the Interrupt Service Routine (0004h). The same clock used to increment Timer1 can also be used to synchronize the comparator output. This 6.9 ECCP Capture/Compare Time feature is enabled in the Comparator module. Base When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. The ECCP module uses the TMR1H:TMR1L register This ensures Timer1 does not miss an increment if the pair as the time base when operating in Capture or comparator changes. Compare mode. For more information, see Section8.0 “Comparator In Capture mode, the value in the TMR1H:TMR1L Module”. register pair is copied into the CCPRxH:CCPRxL register pair on a configured event. FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. DS40001291H-page 80  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 6.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register6-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER DEFINITIONS: TIMER1 CONTROL REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 6 TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 Gate function 0 = Timer1 is always counting bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register, as a Timer1 gate source.  2006-2015 Microchip Technology Inc. DS40001291H-page 81

PIC16F882/883/884/886/887 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC 92 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 78 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 78 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 81 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. DS40001291H-page 82  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 7.0 TIMER2 MODULE The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to The Timer2 module is an 8-bit timer with the following 00h and the PR2 register is set to FFh. features: Timer2 is turned on by setting the TMR2ON bit in the • 8-bit timer register (TMR2) T2CON register to a ‘1’. Timer2 is turned off by clearing • 8-bit period register (PR2) the TMR2ON bit to a ‘0’. • Interrupt on TMR2 match with PR2 The Timer2 prescaler is controlled by the T2CKPS bits • Software programmable prescaler (1:1, 1:4, 1:16) in the T2CON register. The Timer2 postscaler is • Software programmable postscaler (1:1 to 1:16) controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared See Figure7-1 for a block diagram of Timer2. when: 7.1 Timer2 Operation • A write to TMR2 occurs. • A write to T2CON occurs. The clock input to the Timer2 module is the system • Any device Reset occurs (Power-on Reset, MCLR instruction clock (FOSC/4). The clock is fed into the Reset, Watchdog Timer Reset, or Brown-out Timer2 prescaler, which has prescale options of 1:1, Reset). 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. Note: TMR2 is not cleared when T2CON is written. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: • TMR2 is reset to 00h on the next increment cycle • The Timer2 postscaler is incremented The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. FIGURE 7-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 bit TMR2IF Output Prescaler Reset FOSC/4 TMR2 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T2CKPS<1:0> PR2 4 TOUTPS<3:0>  2006-2015 Microchip Technology Inc. DS40001291H-page 83

PIC16F882/883/884/886/887 REGISTER DEFINITIONS: TIMER2 CONTROL REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 =Prescaler is 1 01 =Prescaler is 4 1x =Prescaler is 16 TABLE 7-1: SUMMARY OF ASSOCIATED TIMER2 REGISTERS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 PR2 Timer2 Module Period Register 83 TMR2 Holding Register for the 8-bit TMR2 Register 83 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 84 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. DS40001291H-page 84  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 8.0 COMPARATOR MODULE 8.1 Comparator Overview Comparators are used to interface analog circuits to a A single comparator is shown in Figure8-1 along with digital circuit by comparing two analog voltages and the relationship between the analog input levels and providing a digital indication of their relative magnitudes. the digital output. When the analog voltage at VIN+ is The comparators are very useful mixed signal building less than the analog voltage at VIN-, the output of the blocks because they provide analog functionality comparator is a digital low level. When the analog independent of the program execution. The analog voltage at VIN+ is greater than the analog voltage at comparator module includes the following features: VIN-, the output of the comparator is a digital high level. • Independent comparator control FIGURE 8-1: SINGLE COMPARATOR • Programmable input selection • Comparator output is available internally/externally • Programmable output polarity VIN+ + Output • Interrupt-on-change VIN- – • Wake-up from Sleep • PWM shutdown • Timer1 gate (count enable) • Output synchronization to Timer1 clock input VIN- • SR Latch VIN+ • Programmable and Fixed Voltage Reference Note: Only Comparator C2 can be linked to Timer1. Output Note: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time.  2006-2015 Microchip Technology Inc. DS40001291H-page 85

PIC16F882/883/884/886/887 FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> 2 C1POL To D Q Data Bus Q1 C12IN0- 0 EN RD_CM1CON0 C12IN1- 1 MUX Set C1IF D Q C12IN2- 2 Q3*RD_CM1CON0 EN C12IN3- 3 CL To PWM Logic Reset C1ON(1) C1R C1VIN- - C1IN+ 0 C1 C1OUT MUX C1VIN+ + FixedRef 1 C1OUT (to SR Latch) 0 MUX C1POL CVREF 1 C1VREF C1RSEL Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM C2POL To D Q Data Bus Q1 EN RD_CM2CON0 C2CH<1:0> Set C2IF 2 D Q Q3*RD_CM2CON0 C12IN0- 0 C2ON(1) ENCL Reset C12IN1- 1 MUX C2VIN- C12IN2- 2 C2VIN+ C2 C2OUT C12IN3- 3 C2SYNC C2POL C2R 0 SYNCC2OUT MUX D Q 1 To Timer1 Gate, SR Latch, C2IN+ 0 PWM Logic, and other MUX From Timer1 peripherals Clock FixedRef 1 0 MUX CVREF 1 C2VREF C2RSEL Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. DS40001291H-page 86  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 8.2 Comparator Control 8.2.4 COMPARATOR OUTPUT SELECTION Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 The output of the comparator can be monitored by and CM2CON0 for Comparator C2. In addition, reading either the CxOUT bit of the CMxCON0 register Comparator C2 has a second control register, or the MCxOUT bit of the CM2CON1 register. In order CM2CON1, for controlling the interaction with Timer1 and to make the output available for an external connection, simultaneous reading of both comparator outputs. the following conditions must be true: The CM1CON0 and CM2CON0 registers (see Registers • CxOE bit of the CMxCON0 register must be set 8-1 and 8-2, respectively) contain the control and Status • Corresponding TRIS bit must be cleared bits for the following: • CxON bit of the CMxCON0 register must be set • Enable • Input selection Note1: The CxOE bit overrides the PORT data • Reference selection latch. Setting the CxON has no impact on • Output selection the port override. • Output polarity 2: The internal output of the comparator is latched with each instruction cycle. 8.2.1 COMPARATOR ENABLE Unless otherwise specified, external Setting the CxON bit of the CMxCON0 register enables outputs are not latched. the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current 8.2.5 COMPARATOR OUTPUT POLARITY consumption. Inverting the output of the comparator is functionally 8.2.2 COMPARATOR INPUT SELECTION equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by The CxCH<1:0> bits of the CMxCON0 register direct setting the CxPOL bit of the CMxCON0 register. one of four analog input pins to the comparator Clearing the CxPOL bit results in a non-inverted output. inverting input. Table8-1 shows the output state versus input Note: To use CxIN+ and CxIN- pins as analog conditions, including polarity control. inputs, the appropriate bits must be set in TABLE 8-1: COMPARATOR OUTPUT the ANSEL and ANSELH registers and STATE VS. INPUT the corresponding TRIS bits must also be CONDITIONS set to disable the output drivers. Input Condition CxPOL CxOUT 8.2.3 COMPARATOR REFERENCE CxVIN- > CxVIN+ 0 0 SELECTION CxVIN- < CxVIN+ 0 1 Setting the CxR bit of the CMxCON0 register directs an CxVIN- > CxVIN+ 1 1 internal voltage reference or an analog input pin to the non-inverting input of the comparator. See CxVIN- < CxVIN+ 1 0 Section8.10 “Comparator Voltage Reference” for more information on the internal voltage reference 8.3 Comparator Response Time module. The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference specifications in Section17.0 “Electrical Specifications” for more details.  2006-2015 Microchip Technology Inc. DS40001291H-page 87

PIC16F882/883/884/886/887 8.4 Comparator Interrupt Operation FIGURE 8-4: COMPARATOR INTERRUPT TIMING W/O The comparator interrupt flag can be set whenever CMxCON0 READ there is a change in the output value of the comparator. Changes are recognized by means of a mismatch Q1 circuit which consists of two latches and an exclusive- Q3 or gate (see Figures8-2 and 8-3). One latch is updated CIN+ TRT with the comparator output level when the CMxCON0 CxOUT register is read. This latch retains the value until the Set CxIF (level) next read of the CMxCON0 register or the occurrence CxIF of a Reset. The other latch of the mismatch circuit is updated on every Q1 system clock. A mismatch reset by software condition will occur when a comparator output change is clocked through the second latch on the Q1 clock FIGURE 8-5: COMPARATOR cycle. At this point the two mismatch latches have INTERRUPT TIMING WITH opposite output levels which is detected by the CMxCON0 READ exclusive-or gate and fed to the interrupt circuitry. The mismatch condition persists until either the CMxCON0 Q1 register is read or the comparator output returns to the Q3 previous state. CxIN+ TRT Note 1: A write operation to the CMxCON0 CxOUT register will also clear the mismatch Set CxIF (level) condition because all writes include a read CxIF operation at the beginning of the write cleared by CMxCON0 read reset by software cycle. 2: Comparator interrupts will operate correctly regardless of the state of CxOE. Note1: If a change in the CMxCON0 register The comparator interrupt is set by the mismatch edge (CxOUT) should occur when a read oper- and not the mismatch level. This means that the inter- ation is being executed (start of the Q2 rupt flag can be reset without the additional step of cycle), then the CxIF of the PIR2 register reading or writing the CMxCON0 register to clear the interrupt flag may not get set. mismatch registers. When the mismatch registers are 2: When either comparator is first enabled, cleared, an interrupt will occur upon the comparator’s bias circuitry in the comparator module return to the previous state, otherwise no interrupt will may cause an invalid output from the be generated. comparator until the bias circuitry is Software will need to maintain information about the stable. Allow about 1 s for bias settling status of the comparator output, as read from the then clear the mismatch condition and CMxCON0 register, or CM2CON1 register, to determine interrupt flags before enabling comparator the actual change that has occurred. interrupts. The CxIF bit of the PIR2 register is the comparator interrupt flag. This bit must be reset in software by clearing it to ‘0’. Since it is also possible to write a ‘1’ to this register, an interrupt can be generated. The CxIE bit of the PIE2 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CxIF bit of the PIR2 register will still be set if an interrupt condition occurs. DS40001291H-page 88  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 8.5 Operation During Sleep and the PEIE bit of the INTCON register must be set. The instruction following the Sleep instruction always The comparator, if enabled before entering Sleep mode, executes following a wake from Sleep. If the GIE bit of remains active during Sleep. The additional current the INTCON register is also set, the device will then consumed by the comparator is shown separately in the execute the Interrupt Service Routine. Section17.0 “Electrical Specifications”. If the comparator is not used to wake the device, power 8.6 Effects of a Reset consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off A device Reset forces the CMxCON0 and CM2CON1 by clearing the CxON bit of the CMxCON0 register. registers to their Reset states. This forces both comparators and the voltage references to their Off A change to the comparator output can wake-up the states. device from Sleep. To enable the comparator to wake the device from Sleep, the CxIE bit of the PIE2 register REGISTER DEFINITIONS: COMPARATOR C1 REGISTER 8-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT = 0 when C1VIN+ > C1VIN- C1OUT = 1 when C1VIN+ < C1VIN- If C1POL = 0 (non-inverted polarity): C1OUT = 1 when C1VIN+ > C1VIN- C1OUT = 0 when C1VIN+ < C1VIN- bit 5 C1OE: Comparator C1 Output Enable bit 1 = C1OUT is present on the C1OUT pin(1) 0 = C1OUT is internal only bit 4 C1POL: Comparator C1 Output Polarity Select bit 1 = C1OUT logic is inverted 0 = C1OUT logic is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 C1R: Comparator C1 Reference Select bit (non-inverting input) 1 = C1VIN+ connects to C1VREF output 0 = C1VIN+ connects to C1IN+ pin bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit 00 = C12IN0- pin of C1 connects to C1VIN- 01 = C12IN1- pin of C1 connects to C1VIN- 10 = C12IN2- pin of C1 connects to C1VIN- 11 = C12IN3- pin of C1 connects to C1VIN- Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port TRIS bit = 0.  2006-2015 Microchip Technology Inc. DS40001291H-page 89

PIC16F882/883/884/886/887 REGISTER DEFINITIONS: COMPARATOR C2 REGISTER 8-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT = 0 when C2VIN+ > C2VIN- C2OUT = 1 when C2VIN+ < C2VIN- If C2POL = 0 (non-inverted polarity): C2OUT = 1 when C2VIN+ > C2VIN- C2OUT = 0 when C2VIN+ < C2VIN- bit 5 C2OE: Comparator C2 Output Enable bit 1 = C2OUT is present on C2OUT pin(1) 0 = C2OUT is internal only bit 4 C2POL: Comparator C2 Output Polarity Select bit 1 = C2OUT logic is inverted 0 = C2OUT logic is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input) 1 = C2VIN+ connects to C2VREF 0 = C2VIN+ connects to C2IN+ pin bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits 00 = C12IN0- pin of C2 connects to C2VIN- 01 = C12IN1- pin of C2 connects to C2VIN- 10 = C12IN2- pin of C2 connects to C2VIN- 11 = C12IN3- pin of C2 connects to C2VIN- Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port TRIS bit = 0. DS40001291H-page 90  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 8.7 Analog Input Connection Considerations Note1: When reading a PORT register, all pins configured as analog inputs will read as a A simplified circuit for an analog input is shown in ‘0’. Pins configured as digital inputs will Figure8-6. Since the analog input pins share their convert as an analog input, according to connection with a digital input, they have reverse the input specification. biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. 2: Analog levels on any pin defined as a If the input voltage deviates from this range by more digital input, may cause the input buffer to than 0.6V in either direction, one of the diodes is consume more current than is specified. forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. FIGURE 8-6: ANALOG INPUT MODEL VDD Rs < 10K VT  0.6V RIC To ADC Input AIN VA C5 PpIFN VT  0.6V I±L5E0A0K AnGAE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage Note1: See Section17.0 “Electrical Specifications”.  2006-2015 Microchip Technology Inc. DS40001291H-page 91

PIC16F882/883/884/886/887 8.8 Additional Comparator Features 8.8.2 SYNCHRONIZING COMPARATOR C2 OUTPUT TO TIMER1 There are three additional comparator features: The Comparator C2 output can be synchronized with • Timer1 count enable (gate) Timer1 by setting the C2SYNC bit of the CM2CON1 • Synchronizing output with Timer1 register. When enabled, the C2 output is latched on the • Simultaneous read of comparator outputs falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after 8.8.1 COMPARATOR C2 GATING TIMER1 the prescaling function. To prevent a race condition, the This feature can be used to time the duration or interval comparator output is latched on the falling edge of the of analog events. Clearing the T1GSS bit of the Timer1 clock source and Timer1 increments on the CM2CON1 register will enable Timer1 to increment rising edge of its clock source. See the Comparator based on the output of Comparator C2. This requires Block Diagram (Figures8-2 and 8-3) and the Timer1 that Timer1 is on and gating is enabled. See Block Diagram (Figure6-1) for more information. Section6.0 “Timer1 Module with Gate Control” for 8.8.3 SIMULTANEOUS COMPARATOR details. OUTPUT READ It is recommended to synchronize the comparator with Timer1 by setting the C2SYNC bit when the comparator The MC1OUT and MC2OUT bits of the CM2CON1 is used as the Timer1 gate source. This ensures Timer1 register are mirror copies of both comparator outputs. does not miss an increment if the comparator changes The ability to read both outputs simultaneously from a during an increment. single register eliminates the timing skew of reading separate registers. Note1: Obtaining the status of C1OUT or C2OUT by reading CM2CON1 does not affect the comparator interrupt mismatch registers. REGISTER 8-3: CM2CON1: COMPARATOR C2 CONTROL REGISTER 1 R-0 R-0 R/W-0 R/W-0 U-0 U-0 R/W-1 R/W-0 MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 C1RSEL: Comparator C1 Reference Select bit 1 = CVREF routed to C1VREF input of Comparator C1 0 = Absolute voltage reference (0.6) routed to C1VREF input of Comparator C1 (or 1.2V precision reference on parts so equipped) bit 4 C2RSEL: Comparator C2 Reference Select bit 1 = CVREF routed to C2VREF input of Comparator C2 0 = Absolute voltage reference (0.6) routed to C2VREF input of Comparator C2 (or 1.2V precision reference on parts so equipped) bit 3-2 Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit 1 = Timer1 gate source is T1G 0 = Timer1 gate source is SYNCC2OUT. bit 0 C2SYNC: Comparator C2 Output Synchronization bit 1 = Output is synchronous to falling edge of Timer1 clock 0 = Output is asynchronous DS40001291H-page 92  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 8.9 Comparator SR Latch 8.9.2 LATCH OUTPUT The SR latch module provides additional control of the The SR<1:0> bits of the SRCON register control the comparator outputs. The module consists of a single latch output multiplexers and determine four possible SR latch and output multiplexers. The SR latch can be output configurations. In these four configurations, the set, reset or toggled by the comparator outputs. The SR CxOUT I/O port logic is connected to: latch may also be set or reset, independent of • C1OUT and C2OUT comparator output, by control bits in the SRCON control • C1OUT and SR latch Q register. The SR latch output multiplexers select • C2OUT and SR latch Q whether the latch outputs or the comparator outputs are • SR latch Q and Q directed to the I/O port logic for eventual output to a pin. After any Reset, the default output configuration is the 8.9.1 LATCH OPERATION unlatched C1OUT and C2OUT mode. This maintains The latch is a Set-Reset latch that does not depend on a compatibility with devices that do not have the SR latch clock source. Each of the Set and Reset inputs are feature. active-high. Each latch input is connected to a The applicable TRIS bits of the corresponding ports comparator output and a software controlled pulse must be cleared to enable the port pin output drivers. generator. The latch can be set by C1OUT or the PULSS Additionally, the CxOE comparator output enable bits of bit of the SRCON register. The latch can be reset by the CMxCON0 registers must be set in order to make the C2OUT or the PULSR bit of the SRCON register. The comparator or latch outputs available on the output pins. latch is reset-dominant, therefore, if both Set and Reset The latch configuration enable states are completely inputs are high the latch will go to the Reset state. Both independent of the enable states for the comparators. the PULSS and PULSR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch set or Reset operation. FIGURE 8-7: SR LATCH SIMPLIFIED BLOCK DIAGRAM SR0 C1OE PULSS Pulse Gen(2) 0 C1OUT (from comparator) MUX S Q 1 C1OUT pin(3) C1SEN SR Latch(1) C2OE SYNCC2OUT (from comparator) R Q 1 C2REN MUX 0 C2OUT pin(3) PULSR Pulse SR1 Gen(2) Note 1: If R=1 and S=1 simultaneously, Q=0, Q=1 2: Pulse generator causes a 1/2 Q-state (1 Tosc) pulse width. 3: Output shown for reference only. See I/O port pin block diagram for more detail.  2006-2015 Microchip Technology Inc. DS40001291H-page 93

PIC16F882/883/884/886/887 REGISTER DEFINITIONS: SR LATCH REGISTER 8-4: SRCON: SR LATCH CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 R/W-0 SR1(2) SR0(2) C1SEN C2REN PULSS PULSR — FVREN bit 7 bit 0 Legend: S = Bit is set only - R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SR1: SR Latch Configuration bit(2) 1 = C2OUT pin is the latch Q output 0 = C2OUT pin is the C2 comparator output bit 6 SR0: SR Latch Configuration bits(2) 1 = C1OUT pin is the latch Q output 0 = C1OUT pin is the C1 Comparator output bit 5 C1SEN: C1 Set Enable bit 1 = C1 comparator output sets SR latch 0 = C1 comparator output has no effect on SR latch bit 4 C2REN: C2 Reset Enable bit 1 = C2 comparator output resets SR latch 0 = C2 comparator output has no effect on SR latch bit 3 PULSS: Pulse the SET Input of the SR Latch bit 1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware. 0 = Does not trigger pulse generator bit 2 PULSR: Pulse the Reset Input of the SR Latch bit 1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware. 0 = Does not trigger pulse generator bit 1 Unimplemented: Read as ‘0’ bit 0 FVREN: Fixed Voltage Reference Enable bit 1 = 0.6V Reference FROM INTOSC LDO is enabled 0 = 0.6V Reference FROM INTOSC LDO is disabled Note 1: The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on the pin), regardless of the SR latch operation. 2: To enable an SR Latch output to the pin, the appropriate CxOE and TRIS bits must be properly configured. DS40001291H-page 94  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 8.10 Comparator Voltage Reference 8.10.3 OUTPUT CLAMPED TO VSS The comparator voltage reference module provides an The CVREF output voltage can be set to Vss with no internally generated voltage reference for the power consumption by clearing the FVREN bit of the comparators. The following features are available: VRCON register. • Independent from Comparator operation This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current. • Two 16-level voltage ranges • Output clamped to VSS Note: Depending on the application, additional • Ratiometric with VDD components may be required for a zero cross circuit. Reference TB3013, “Using • Fixed Reference (0.6V) the ESD Parasitic Diodes on Mixed Signal The VRCON register (Register8-5) controls the Microcontrollers” (DS93013), for more voltage reference module shown in Figure8-8. information. The voltage source is selectable through both ends of the 16 connection resistor ladder network. Bit VRSS of 8.10.4 OUTPUT RATIOMETRIC TO VDD the VRCON register selects either the internal or The comparator voltage reference is VDD derived and external voltage source. therefore, the CVREF output changes with fluctuations in The PIC16F882/883/884/886/887 allows the CVREF VDD. The tested absolute accuracy of the Comparator signal to be output to the RA2 pin of PORTA under Voltage Reference can be found in Section17.0 certain configurations only. For more details, see “Electrical Specifications”. Figure8-9. 8.10.5 FIXED VOLTAGE REFERENCE 8.10.1 INDEPENDENT OPERATION The Fixed Voltage Reference is independent of VDD, The comparator voltage reference is independent of with a nominal output voltage of 0.6V. This reference the comparator configuration. Setting the VREN bit of can be enabled by setting the FVREN bit of the the VRCON register will enable the voltage reference. SRCON register to ‘1’. This reference is always enabled when the HFINTOSC oscillator is active. 8.10.2 OUTPUT VOLTAGE SELECTION 8.10.6 FIXED VOLTAGE REFERENCE The CVREF voltage reference has two ranges with 16 STABILIZATION PERIOD voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The When the Fixed Voltage Reference module is enabled, 16 levels are set with the VR<3:0> bits of the VRCON it will require some time for the reference and its register. amplifier circuits to stabilize. The user program must include a small delay routine to allow the module to The CVREF output voltage is determined by the following settle. See Section17.0 “Electrical Specifications” equations: for the minimum delay requirement. EQUATION 8-1: CVREF OUTPUT VOLTAGE 8.10.7 VOLTAGE REFERENCE VRR = 1 (low range): SELECTION CVREF = (VR<3:0>/24)VLADDER Multiplexers on the output of the voltage reference module enable selection of either the CVREF or Fixed VRR = 0 (high range): Voltage Reference for use by the comparators. CVREF = (VLADDER/4) + (VR<3:0>VLADDER/32) Setting the C1RSEL bit of the CM2CON1 register VLADDER = VDD or ([VREF+] - [VREF-]) or VREF+ enables current to flow in the CVREF voltage divider and selects the CVREF voltage for use by C1. Clearing the C1RSEL bit selects the fixed voltage for use by C1. The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure8-8. Setting the C2RSEL bit of the CM2CON1 register enables current to flow in the CVREF voltage divider and selects the CVREF voltage for use by C2. Clearing the C2RSEL bit selects the fixed voltage for use by C2. When both the C1RSEL and C2RSEL bits are cleared, current flow in the CVREF voltage divider is disabled minimizing the power drain of the voltage reference peripheral.  2006-2015 Microchip Technology Inc. DS40001291H-page 95

PIC16F882/883/884/886/887 FIGURE 8-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages VREF+ VRSS = 1 8R R R R R VRSS = 0 VDD 8R VRR Analog MUX VREF- VRSS = 1 15 CVREF VRSS = 0 To Comparators and ADC Module 0 VR<3:0> VROE 4 VREN CVREF C1RSEL C2RSEL FVREN Sleep HFINTOSC enable EN FixedRef 0.6V Fixed Voltage To Comparators Reference and ADC Module FIGURE 8-9: COMPARATOR AND ADC VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD 1 AVDD 1 0 0 VRSS VCFG0 CVREF Comparator ADC Voltage Voltage VROE Reference Reference VCFG1 VRSS 0 0 AVSS 1 AVSS 1 VCFG1 VREF- DS40001291H-page 96  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 8-2: COMPARATOR AND ADC VOLTAGE REFERENCE PRIORITY Comp. Comp. ADC ADC RA3 RA2 CFG1 CFG0 VRSS VROE Reference (+) Reference (-) Reference (+) Reference (-) I/O I/O AVDD AVSS AVDD AVSS 0 0 0 0 I/O CVREF AVDD AVSS AVDD AVSS 0 0 0 1 VREF+ VREF- VREF+ VREF- AVDD AVSS 0 0 1 0 VREF+ CVREF VREF+ AVSS AVDD AVSS 0 0 1 1 VREF+ I/O AVDD AVSS VREF+ AVSS 0 1 0 0 VREF+ CVREF AVDD AVSS VREF+ AVSS 0 1 0 1 VREF+ VREF- VREF+ VREF- VREF+ AVSS 0 1 1 0 VREF+ CVREF VREF+ AVSS VREF+ AVSS 0 1 1 1 I/O VREF- AVDD AVSS AVDD VREF- 1 0 0 0 I/O VREF- AVDD AVSS AVDD VREF- 1 0 0 1 VREF+ VREF- VREF+ VREF- AVDD VREF- 1 0 1 0 VREF+ VREF- VREF+ VREF- AVDD VREF- 1 0 1 1 VREF+ VREF- AVDD AVSS VREF+ VREF- 1 1 0 0 VREF+ VREF- AVDD AVSS VREF+ VREF- 1 1 0 1 VREF+ VREF- VREF+ VREF- VREF+ VREF- 1 1 1 0 VREF+ VREF- VREF+ VREF- VREF+ VREF- 1 1 1 1  2006-2015 Microchip Technology Inc. DS40001291H-page 97

PIC16F882/883/884/886/887 REGISTER DEFINITIONS: VOLTAGE REFERENCE CONTROL REGISTER 8-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN VROE VRR VRSS VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VREN: Comparator C1 Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 VROE: Comparator C2 Voltage Reference Enable bit 1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF/C2IN+ pin 0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF/C2IN+ pin bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 VRSS: Comparator VREF Range Selection bit 1 = Comparator Reference Source, CVRSRC = (VREF+) - (VREF-) 0 = Comparator Reference Source, CVRSRC = VDD - VSS bit 3-0 VR<3:0>: CVREF Value Selection 0  VR<3:0>  15 When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD TABLE 8-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 41 ANSELH — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 49 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 89 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 90 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC 92 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 34 PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 36 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 40 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 49 SRCON SR1 SR0 C1SEN C2SEN PULSS PULSR — FVREN 94 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 40 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 49 VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 98 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator. DS40001291H-page 98  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. Figure9-1 shows the block diagram of the ADC. FIGURE 9-1: ADC BLOCK DIAGRAM VCFG1 = 0 AVSS VREF- VCFG1 = 1 AVDD VCFG0 = 0 VREF+ VCFG0 = 1 AN0 0000 AN1 0001 AN2 0010 AN3 0011 AN4 0100 AN5 0101 AN6 0110 AN7 0111 ADC AN8 1000 GO/DONE 10 AN9 1001 AN10 1010 0 = Left Justify ADFM AN11 1011 1 = Right Justify AN12 1100 ADON 10 AN13 1101 VSS ADRESH ADRESL CVREF 1110 FixedRef 1111 CHS<3:0>  2006-2015 Microchip Technology Inc. DS40001291H-page 99

PIC16F882/883/884/886/887 9.1 ADC Configuration 9.1.3 ADC VOLTAGE REFERENCE When configuring and using the ADC the following The VCFG bits of the ADCON1 register provide functions must be considered: independent control of the positive and negative voltage references. The positive voltage reference can • Port configuration be either VDD or an external voltage source. Likewise, • Channel selection the negative voltage reference can be either VSS or an • ADC voltage reference selection external voltage source. • ADC conversion clock source 9.1.4 CONVERSION CLOCK • Interrupt control • Results formatting The source of the conversion clock is software select- able via the ADCS bits of the ADCON0 register. There 9.1.1 PORT CONFIGURATION are four possible clock options: The ADC can be used to convert both analog and digital • FOSC/2 signals. When converting analog signals, the I/O pin • FOSC/8 should be configured for analog by setting the associated • FOSC/32 TRIS and ANSEL bits. See the corresponding Port • FRC (dedicated internal oscillator) section for more information. The time to complete one bit conversion is defined as Note: Analog voltages on any pin that is defined TAD. One full 10-bit conversion requires 11 TAD periods as a digital input may cause the input buf- as shown in Figure9-2. fer to conduct excess current. For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in 9.1.2 CHANNEL SELECTION Section17.0 “Electrical Specifications” for more The CHS bits of the ADCON0 register determine which information. Table9-1 gives examples of appropriate channel is connected to the sample and hold circuit. ADC clock selections. When changing channels, a delay is required before Note: Unless using the FRC, any changes in the starting the next conversion. Refer to Section9.2 system clock frequency will change the “ADC Operation” for more information. ADC clock frequency, which may adversely affect the ADC result. DS40001291H-page 100  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<1:0> 20 MHz 8 MHz 4 MHz 1 MHz FOSC/2 00 100 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/8 01 400 ns(2) 1.0 s(2) 2.0 s 8.0 s(3) FOSC/32 10 1.6 s 4.0 s 8.0 s(3) 32.0 s(3) FRC 11 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 4 s for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY to TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input 9.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section14.3 “Interrupts” for more information.  2006-2015 Microchip Technology Inc. DS40001291H-page 101

PIC16F882/883/884/886/887 9.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure9-3 shows the two output formats. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result 9.2 ADC Operation 9.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This 9.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC To enable the ADC module, the ADON bit of the option. When the FRC clock source is selected, the ADCON0 register must be set to a ‘1’. Setting the GO/ ADC waits one additional instruction before starting the DONE bit of the ADCON0 register to a ‘1’ will start the conversion. This allows the SLEEP instruction to be Analog-to-Digital conversion. executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device Note: The GO/DONE bit should not be set in the will wake-up from Sleep when the conversion same instruction that turns on the ADC. completes. If the ADC interrupt is disabled, the ADC Refer to Section9.2.6 “A/D Conversion module is turned off after the conversion completes, Procedure”. although the ADON bit remains set. 9.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conver- When the conversion is complete, the ADC module will: sion to be aborted and the ADC module is turned off, • Clear the GO/DONE bit although the ADON bit remains set. • Set the ADIF flag bit 9.2.5 SPECIAL EVENT TRIGGER • Update the ADRESH:ADRESL registers with new conversion result The ECCP Special Event Trigger allows periodic ADC measurements without software intervention. When 9.2.3 TERMINATING A CONVERSION this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The Using the Special Event Trigger does not assure ADRESH:ADRESL registers will not be updated with proper ADC timing. It is the user’s responsibility to the partially complete Analog-to-Digital conversion ensure that the ADC timing requirements are met. sample. Instead, the ADRESH:ADRESL register pair See Section11.0 “Capture/Compare/PWM Modules will retain the value of the previous conversion. Addi- (CCP1 and CCP2)” for more information. tionally, a 2TAD delay is required before another acqui- sition can be initiated. Following this delay, an input acquisition is automatically started on the selected channel. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. DS40001291H-page 102  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 9.2.6 A/D CONVERSION PROCEDURE EXAMPLE 9-1: A/D CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss as reference, Frc clock and AN0 input. 1. Configure Port: ; • Disable pin output driver (See TRIS register) ;Conversion start & polling for completion • Configure pin as analog ; are included. ; 2. Configure the ADC module: BANKSEL ADCON1 ; • Select ADC conversion clock MOVLW B’10000000’ ;right justify • Configure voltage reference MOVWF ADCON1 ;Vdd and Vss as Vref BANKSEL TRISA ; • Select ADC input channel BSF TRISA,0 ;Set RA0 to input • Select result format BANKSEL ANSEL ; • Turn on ADC module BSF ANSEL,0 ;Set RA0 to analog 3. Configure ADC interrupt (optional): BANKSEL ADCON0 ; MOVLW B’11000001’ ;ADC Frc clock, • Clear ADC interrupt flag MOVWF ADCON0 ;AN0, On • Enable ADC interrupt CALL SampleTime ;Acquisiton delay • Enable peripheral interrupt BSF ADCON0,GO ;Start conversion • Enable global interrupt(1) BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again 4. Wait the required acquisition time(2). BANKSEL ADRESH ; 5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space 6. Wait for ADC conversion to complete by one of BANKSEL ADRESL ; the following: MOVF ADRESL,W ;Read lower 8 bits • Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section9.3 “A/D Acquisition Requirements”.  2006-2015 Microchip Technology Inc. DS40001291H-page 103

PIC16F882/883/884/886/887 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the opera- tion of the ADC. Note: For ANSEL and ANSELH registers, see Register3-3 and Register3-4, respectively. REGISTER DEFINITIONS: ADC CONTROL REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = AN0 0001 = AN1 0010 = AN2 0011 = AN3 0100 = AN4 0101 = AN5 0110 = AN6 0111 = AN7 1000 = AN8 1001 = AN9 1010 = AN10 1011 = AN11 1100 = AN12 1101 = AN13 1110 = CVREF 1111 = Fixed Ref (0.6V Fixed Voltage Reference) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current DS40001291H-page 104  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 ADFM — VCFG1 VCFG0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference bit 1 = VREF- pin 0 = VSS bit 4 VCFG0: Voltage Reference bit 1 = VREF+ pin 0 = VDD bit 3-0 Unimplemented: Read as ‘0’  2006-2015 Microchip Technology Inc. DS40001291H-page 105

PIC16F882/883/884/886/887 REGISTER 9-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 9-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES1 ADRES0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 9-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — — — — ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 9-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result DS40001291H-page 106  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 9.3 A/D Acquisition Requirements an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition For the ADC to meet its specified accuracy, the charge time, Equation9-1 may be used. This equation holding capacitor (CHOLD) must be allowed to fully assumes that 1/2 LSb error is used (1024 steps for the charge to the input channel voltage level. The Analog ADC). The 1/2 LSb error is the maximum error allowed Input model is shown in Figure9-4. The source for the ADC to meet its specified resolution. impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure9-4. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), EQUATION 9-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– ------n---+-----1------------ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb 2 –1 –TC  ---------- VAPPLIED1–eRC = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– ------n----+----1------------ ;combining [1] and [2]   2  –1 Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/2047) = –10pF1k+7k+10k ln(0.0004885) = 1.37µs Therefore: TACQ = 2ΜS+1.37ΜS+50°C- 25°C0.05ΜS/°C = 4.67ΜS Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification.  2006-2015 Microchip Technology Inc. DS40001291H-page 107

PIC16F882/883/884/886/887 FIGURE 9-4: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC  1k SS Rss VA C5 PpIFN VT = 0.6V I± L5E0A0K AnGAE(1) CHOLD = 10 pF VSS/VREF- 6V 5V RSS Legend: CPIN = Input Capacitance VDD4V VT = Threshold Voltage 3V 2V I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance 5 6 7 891011 SS = Sampling Switch Sampling Switch CHOLD = Sample/Hold Capacitance (k) Note 1: See Section17.0 “Electrical Specifications”. FIGURE 9-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh de 3FCh 1 LSB ideal o C 3FBh ut p ut Full-Scale O C 004h Transition D A 003h 002h 001h 000h Analog Input Voltage 1 LSB ideal VSS/VREF- Zero-Scale VDD/VREF+ Transition DS40001291H-page 108  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 104 ADCON1 ADFM — VCFG1 VCFG0 — — — — 105 ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 41 ANSELH — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 49 ADRESH A/D Result Register High Byte 106 ADRESL A/D Result Register Low Byte 106 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 40 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 49 PORTE — — — — RE3 RE2 RE1 RE0 60 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 40 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 49 TRISE — — — — TRISE3 TRISE2 TRISE1 TRISE0 60 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.  2006-2015 Microchip Technology Inc. DS40001291H-page 109

PIC16F882/883/884/886/887 10.0 DATA EEPROM AND FLASH 10.1 EEADR and EEADRH Registers PROGRAM MEMORY The EEADR and EEADRH registers can address up to CONTROL a maximum of 256bytes of data EEPROM or up to a maximum of 8K words of program EEPROM. The Data EEPROM and Flash program memory are readable and writable during normal operation (full VDD When selecting a program address value, the MSB of range). These memories are not directly mapped in the the address is written to the EEADRH register and the register file space. Instead, they are indirectly LSB is written to the EEADR register. When selecting a addressed through the Special Function Registers data address value, only the LSB of the address is (SFRs). There are six SFRs used to access these written to the EEADR register. memories: 10.1.1 EECON1 AND EECON2 REGISTERS • EECON1 EECON1 is the control register for EE memory • EECON2 accesses. • EEDAT Control bit EEPGD determines if the access will be a pro- • EEDATH gram or data memory access. When clear, as it is when • EEADR reset, any subsequent operations will operate on the data • EEADRH (bit 4 on PIC16F886/PIC16F887 only) memory. When set, any subsequent operations will oper- When interfacing the data memory block, EEDAT holds ate on the program memory. Program memory can only the 8-bit data for read/write, and EEADR holds the be read. address of the EEDAT location being accessed. These Control bits RD and WR initiate read and write, devices have 256 bytes of data EEPROM with an respectively. These bits cannot be cleared, only set, in address range from 0h to 0FFh. software. They are cleared in hardware at completion When accessing the program memory block of the of the read or write operation. The inability to clear the PIC16F886/PIC16F887 devices, the EEDAT and EED- WR bit in software prevents the accidental, premature ATH registers form a 2-byte word that holds the 14-bit termination of a write operation. data for read/write, and the EEADR and EEADRH reg- The WREN bit, when set, will allow a write operation to isters form a 2-byte word that holds the 12-bit address data EEPROM. On power-up, the WREN bit is clear. of the EEPROM location being read. The PIC16F882 The WRERR bit is set when a write operation is devices have 2K words of program EEPROM with an interrupted by a MCLR or a WDT Time-out Reset address range from 0h to 07FFh. The PIC16F883/ during normal operation. In these situations, following PIC16F884 devices have 4K words of program Reset, the user can check the WRERR bit and rewrite EEPROM with an address range from 0h to 0FFFh. the location. The program memory allows one-word reads. Interrupt flag bit EEIF of the PIR2 register is set when The EEPROM data memory allows byte read and write. write is complete. It must be cleared in the software. A byte write automatically erases the location and EECON2 is not a physical register. Reading EECON2 writes the new data (erase before write). will read all ‘0’s. The EECON2 register is used The write time is controlled by an on-chip timer. The exclusively in the data EEPROM write sequence. write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. Depending on the setting of the Flash Program Memory Self Write Enable bits WRT<1:0> of the Configuration Word Register 2, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are allowed. When the device is code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. When code-protected, the device programmer can no longer access data or program memory. DS40001291H-page 110  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 REGISTER DEFINITIONS: DATA EEPROM CONTROL REGISTER 10-1: EEDAT: EEPROM DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EEDAT<7:0>: Eight Least Significant Address bits to Write to or Read from data EEPROM or Read from program memory REGISTER 10-2: EEADR: EEPROM ADDRESS REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EEADR<7:0>: Eight Least Significant Address bits for EEPROM Read/Write Operation(1) or Read from program memory REGISTER 10-3: EEDATH: EEPROM DATA HIGH BYTE REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 EEDATH<5:0>: Six Most Significant Data bits from program memory REGISTER 10-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — EEADRH4(1) EEADRH3 EEADRH2 EEADRH1 EEADRH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 EEADRH<4:0>: Specifies the four Most Significant Address bits or high bits for program memory reads Note 1: PIC16F886/PIC16F887 only.  2006-2015 Microchip Technology Inc. DS40001291H-page 111

PIC16F882/883/884/886/887 REGISTER 10-5: EECON1: EEPROM CONTROL REGISTER R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — — WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory bit 6-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOR Reset) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in software.) 0 = Does not initiate a memory read DS40001291H-page 112  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 10.1.2 READING THE DATA EEPROM 10.1.3 WRITING TO THE DATA EEPROM MEMORY MEMORY To read a data memory location, the user must write the To write an EEPROM data location, the user must first address to the EEADR register, clear the EEPGD write the address to the EEADR register and the data control bit of the EECON1 register, and then set control to the EEDAT register. Then the user must follow a bit RD. The data is available at the very next cycle, in specific sequence to initiate the write for each byte. the EEDAT register; therefore, it can be read in the next The write will not initiate if the above sequence is not instruction. EEDAT will hold this value until another followed exactly (write 55h to EECON2, write AAh to read or until it is written to by the user (during a write EECON2, then set WR bit) for each byte. Interrupts operation). should be disabled during this codesegment. Additionally, the WREN bit in EECON1 must be set to EXAMPLE 10-1: DATA EEPROM READ enable write. This mechanism prevents accidental BANKSEL EEADR ; writes to data EEPROM due to errant (unexpected) MOVLW DATA_EE_ADDR ; code execution (i.e., lost programs). The user should MOVWF EEADR ;Data Memory keep the WREN bit clear at all times, except when ;Address to read updating EEPROM. The WREN bit is not cleared BANKSEL EECON1 ; byhardware. BCF EECON1, EEPGD ;Point to DATA memory BSF EECON1, RD ;EE Read After a write sequence has been initiated, clearing the BANKSEL EEDAT ; WREN bit will not affect this write cycle. The WR bit will MOVF EEDAT, W ;W = EEDAT be inhibited from being set unless the WREN bit is set. BCF STATUS, RP1 ;Bank 0 At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. EXAMPLE 10-2: DATA EEPROM WRITE BANKSEL EEADR ; MOVLW DATA_EE_ADDR ; MOVWF EEADR ;Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDAT ;Data Memory Value to write BANKSEL EECON1 ; BCF EECON1, EEPGD ;Point to DATA memory BSF EECON1, WREN ;Enable writes BCF INTCON, GIE ;Disable INTs. BTFSC INTCON, GIE ;SEE AN576 GOTO $-2 MOVLW 55h ; RequiredSequence MMMOOOVVVWLWFWF EAEEAEChCOONN22 ;;;WWrriittee 5A5Ahh BSF EECON1, WR ;Set WR bit to begin write BSF INTCON, GIE ;Enable INTs. SLEEP ;Wait for interrupt to signal write complete BCF EECON1, WREN ;Disable writes BCF STATUS, RP0 ;Bank 0 BCF STATUS, RP1  2006-2015 Microchip Technology Inc. DS40001291H-page 113

PIC16F882/883/884/886/887 10.1.4 READING THE FLASH PROGRAM EEDAT and EEDATH registers will hold this value until MEMORY another read or until it is written to by the user. To read a program memory location, the user must Note1: The two instructions following a program write the Least and Most Significant address bits to the memory read are required to be NOPs. EEADR and EEADRH registers, set the EEPGD con- This prevents the user from executing a trol bit of the EECON1 register, and then set control bit 2-cycle instruction on the next instruction RD. Once the read control bit is set, the program mem- after the RD bit is set. ory Flash controller will use the second instruction 2: If the WR bit is set when EEPGD = 1, it cycle to read the data. This causes the second instruc- will be immediately reset to ‘0’ and no tion immediately following the “BSF EECON1,RD” operation will take place. instruction to be ignored. The data is available in the very next cycle, in the EEDAT and EEDATH registers; therefore, it can be read as two bytes in the following instructions. EXAMPLE 10-3: FLASH PROGRAM READ BANKSELEEADR ; MOVLW MS_PROG_EE_ADDR ; MOVWF EEADRH ;MS Byte of Program Address to read MOVLW LS_PROG_EE_ADDR ; MOVWF EEADR ;LS Byte of Program Address to read BANKSELEECON1 ; BSF EECON1, EEPGD ;Point to PROGRAM memory BSF EECON1, RD ;EE Read Required; Sequence NOP ;First instruction after BSF EECON1,RD executes normally NOP ;Any instructions here are ignored as program ;memory is read in second cycle after BSF EECON1,RD ; BANKSELEEDAT ; MOVF EEDAT, W ;W = LS Byte of Program Memory MOVWF LOWPMBYTE ; MOVF EEDATH, W ;W = MS Byte of Program EEDAT MOVWF HIGHPMBYTE ; BCF STATUS, RP1 ;Bank 0 DS40001291H-page 114  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 10-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR PC PC + 1 EEADRH,EEADR PPCC ++ 33 PC + 4 PC + 5 Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDAT INSTR (PC + 3) INSTR (PC + 4) INSTR(PC - 1) BSF EECON1,RD INSTR(PC + 1) Forced NOP INSTR(PC + 3) INSTR(PC + 4) executed here executed here executed here executed here executed here executed here RD bit EEDATH EEDAT Register EERHLT  2006-2015 Microchip Technology Inc. DS40001291H-page 115

PIC16F882/883/884/886/887 10.2 Writing to Flash Program Memory After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the erase/write operation. Flash program memory may only be written to if the The user must place two NOP instructions after the WR destination address is in a segment of memory that is bit is set. Since data is being written to buffer registers, not write-protected, as defined in bits WRT<1:0> of the the writing of the first seven words of the block appears Configuration Word Register 2. Flash program memory to occur immediately. The processor will halt internal must be written in 8-word blocks (4-word blocks for 4K operations for the typical 4ms, only during the cycle in memory devices). See Figures10-2 and10-3 for more which the erase takes place (i.e., the last word of the details. A block consists of eight words with sequential sixteen-word block erase). This is not Sleep mode as addresses, with a lower boundary defined by an the clocks and peripherals will continue to run. After the address, where EEADR<2:0>=000. All block writes to 8-word write cycle, the processor will resume operation program memory are done as 16-word erase by 8-word with the third instruction after the EECON1 write write operations. The write operation is edge-aligned instruction. The above sequence must be repeated for and cannot occur across boundaries. the higher eight words. To write program data, it must first be loaded into the buffer registers (see Figure10-2). This is accomplished by first writing the destination address to EEADR and EEADRH and then writing the data to EEDATA and EEDATH. After the address and data have been set up, then the following sequence of events must be executed: 1. Set the EEPGD control bit of the EECON1 register. 2. Write 55h, then AAh, to EECON2 (Flash programming sequence). 3. Set the WR control bit of the EECON1 register. All eight buffer register locations should be written to with correct data. If less than eight words are being written to in the block of eight words, then a read from the program memory location(s) not being written to must be performed. This takes the data from the pro- gram location(s) not being written and loads it into the EEDATA and EEDATH registers. Then the sequence of events to transfer data to the buffer registers must be executed. To transfer data from the buffer registers to the program memory, the EEADR and EEADRH must point to the last location in the 8-word block (EEADR<2:0> = 111). Then the following sequence of events must be executed: 1. Set the EEPGD control bit of the EECON1 register. 2. Write 55h, then AAh, to EECON2 (Flash programming sequence). 3. Set control bit WR of the EECON1 register to begin the write operation. The user must follow the same specific sequence to initiate the write for each word in the program block, writing each program word in sequence (000, 001, 010, 011, 100, 101, 110, 111). When the write is performed on the last word (EEADR<2:0> = 111), a block of sixteen words is automatically erased and the content of the 8-word buffer registers are written into the program memory. DS40001291H-page 116  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 10-2: BLOCK WRITES TO 2K AND 4K FLASH PROGRAM MEMORY 7 5 0 7 0 Sixteen words of EEDATH EEDATA Flash are erased, then four buffers 6 8 are transferred to Flash automatically First word of block after this word to be written is written 14 14 14 14 EEADR<1:0> = 00 EEADR<1:0> = 01 EEADR<1:0> = 10 EEADR<1:0> = 11 Buffer Register Buffer Register Buffer Register Buffer Register Program Memory FIGURE 10-3: BLOCK WRITES TO 8K FLASH PROGRAM MEMORY 7 5 0 7 0 Sixteen words of EEDATH EEDATA Flash are erased, then eight buffers 6 8 are transferred to Flash automatically First word of block after this word to be written is written 14 14 14 14 EEADR<2:0> = 000 EEADR<2:0> = 001 EEADR<2:0> = 010 EEADR<2:0> = 111 Buffer Register Buffer Register Buffer Register Buffer Register Program Memory  2006-2015 Microchip Technology Inc. DS40001291H-page 117

PIC16F882/883/884/886/887 An example of the complete 8-word write sequence is shown in Example10-4. The initial address is loaded into the EEADRH and EEADR register pair; the eight words of data are loaded using indirect addressing. EXAMPLE 10-4: WRITING TO FLASH PROGRAM MEMORY ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; This write routine assumes the following: ; A valid starting address (the least significant bits = '000') ; is loaded in ADDRH:ADDRL ; ADDRH, ADDRL and DATADDR are all located in data memory ; BANKSEL EEADRH MOVF ADDRH,W ; Load initial address MOVWF EEADRH ; MOVF ADDRL,W ; MOVWF EEADR ; MOVF DATAADDR,W ; Load initial data address MOVWF FSR ; LOOP MOVF INDF,W ; Load first data byte into lower MOVWF EEDATA ; INCF FSR,F ; Next byte MOVF INDF,W ; Load second data byte into upper MOVWF EEDATH ; INCF FSR,F ; BANKSEL EECON1 BSF EECON1,EEPGD ; Point to program memory BSF EECON1,WREN ; Enable writes BCF INTCON,GIE ; Disable interrupts (if using) BTFSC INTCON,GIE ; See AN576 GOTO $-2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Required Sequence MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1,WR ; Set WR bit to begin write NOP ; Required to transfer data to the buffer NOP ; registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts (comment out if not using interrupts) BANKSEL EEADR MOVF EEADR, W INCF EEADR,F ; Increment address ANDLW 0x0F ; Indicates when sixteen words have been programmed SUBLW 0x0F ; 0x0F = 16 words ; 0x0B = 12 words (PIC16F884/883/882 only) ; 0x07 = 8 words ; 0x03 = 4 words(PIC16F884/883/882 only) BTFSS STATUS,Z ; Exit on a match, GOTO LOOP ; Continue if more data needs to be written DS40001291H-page 118  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 10.3 Write Verify 10.5 Data EEPROM Operation During Code-Protect Depending on the application, good programming practice may dictate that the value written to the data Data memory can be code-protected by programming EEPROM should be verified (see Example10-5) to the the CPD bit in the Configuration Word Register 1 desired value to be written. (Register14-1) to ‘0’. When the data memory is code-protected, only the EXAMPLE 10-5: WRITE VERIFY CPU is able to read and write data to the data BANKSEL EEDAT ; EEPROM. It is recommended to code-protect the pro- MOVF EEDAT, W ;EEDAT not changed gram memory when code-protecting data memory. ;from previous write This prevents anyone from programming zeros over BANKSEL EECON1 ; the existing code (which will execute as NOPs) to reach BSF EECON1, RD ;YES, Read the an added routine, programmed in unused program ;value written memory, which outputs the contents of data memory. BANKSEL EEDAT ; Programming unused locations in program memory to XORWF EEDAT, W ; ‘0’ will also help prevent data memory code protection BTFSS STATUS, Z ;Is data the same from becoming breached. GOTO WRITE_ERR ;No, handle error : ;Yes, continue BCF STATUS, RP1 ;Bank 0 10.3.1 USING THE DATA EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM (specification D124) without exceeding the total number of write cycles to a single byte (specifications D120 and D120A). If this is the case, then a refresh of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. 10.4 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64ms duration) prevents EEPROMwrite. The write initiate sequence and the WREN bit together help prevent an accidental write during: • Brown-out • Power Glitch • Software Malfunction  2006-2015 Microchip Technology Inc. DS40001291H-page 119

PIC16F882/883/884/886/887 TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page EECON1 EEPGD — — — WRERR WREN WR RD 112 EECON2 EEPROM Control Register 2 (not a physical register) — EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 111 EEADRH — — — EEADRH4(1) EEADRH3 EEADRH2 EEADRH1 EEADRH0 111 EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 111 EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 111 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 34 PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 36 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by data EEPROM module. Note 1: PIC16F886/PIC16F887 only. DS40001291H-page 120  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 11.0 CAPTURE/COMPARE/PWM MODULES (CCP1 AND CCP2) This device contains one Enhanced Capture/Compare/ PWM (CCP1) and Capture/Compare/PWM module (CCP2). The CCP1 and CCP2 modules are identical in operation, with the exception of the Enhanced PWM features available on CCP1 only. See Section11.6 “PWM (Enhanced Mode)” for more information. Note: CCPRx and CCPx throughout this document refer to CCPR1 or CCPR2 and CCP1 or CCP2, respectively. 11.1 Enhanced Capture/Compare/PWM (CCP1) The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. Table11-1 shows the timer resources required by the ECCP module. TABLE 11-1: ECCP MODE – TIMER RESOURCES REQUIRED ECCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2  2006-2015 Microchip Technology Inc. DS40001291H-page 121

PIC16F882/883/884/886/887 REGISTER DEFINITIONS: CCP CONTROL REGISTER 11-1: CCP1CON: ENHANCED CCP1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 P1M<1:0>: PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: ECCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low DS40001291H-page 122  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 11.2 Capture/Compare/PWM (CCP2) TABLE 11-2: CCP MODE – TIMER RESOURCES REQUIRED The Capture/Compare/PWM module is a peripheral which allows the user to time and control different CCP Mode Timer Resource events. In Capture mode, the peripheral allows the Capture Timer1 timing of the duration of an event. The Compare mode Compare Timer1 allows the user to trigger an external event when a predetermined amount of time has expired. The PWM PWM Timer2 mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. The timer resources used by the module are shown in Table11-2. Additional information on CCP modules is available in the Application Note AN594, “Using the CCP Modules” (DS00594). REGISTER 11-2: CCP2CON: CCP2 CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DC2B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR2L. bit 3-0 CCP2M<3:0>: CCP2 Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP2 module) 0001 = Unused (reserved) 0010 = Unused (reserved) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP2IF bit is set) 1001 = Compare mode, clear output on match (CCP2IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP2IF bit is set, CCP2 pin is unaffected) 1011 = Compare mode, trigger special event (CCP2IF bit is set, TMR1 is reset and A/D conversion is started if the ADC module is enabled. CCP2 pin is unaffected.) 11xx = PWM mode.  2006-2015 Microchip Technology Inc. DS40001291H-page 123

PIC16F882/883/884/886/887 11.3 Capture Mode 11.3.2 TIMER1 MODE SELECTION In Capture mode, the CCPRxH, CCPRxL register pair Timer1 must be running in Timer mode or Synchronized captures the 16-bit value of the TMR1 register when an Counter mode for the CCP module to use the capture event occurs on pin CCPx. An event is defined as one feature. In Asynchronous Counter mode, the capture of the following and is configured by the CCP1M<3:0> operation may not work. bits of the CCP1CON register: 11.3.3 SOFTWARE INTERRUPT • Every falling edge When the Capture mode is changed, a false capture • Every rising edge interrupt may be generated. The user should keep the • Every 4th rising edge CCPxIE interrupt enable bit of the PIEx register clear to • Every 16th rising edge avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag following any change in Operating mode. must be cleared in software. If another capture occurs 11.3.4 CCP PRESCALER before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new There are four prescaler settings specified by the captured value (see Figure11-1). CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not 11.3.1 CCP PIN CONFIGURATION in Capture mode, the prescaler counter is cleared. Any In Capture mode, the CCPx pin should be configured Reset will clear the prescaler counter. as an input by setting the associated TRIS control bit. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To Note: If the CCPx pin is configured as an output, avoid this unexpected operation, turn the module off by a write to the port can cause a capture clearing the CCPxCON register before changing the condition. prescaler (see Example11-1). FIGURE 11-1: CAPTURE MODE EXAMPLE 11-1: CHANGING BETWEEN OPERATION BLOCK CAPTURE PRESCALERS DIAGRAM BANKSELCCP1CON ;Set Bank bits to point Set Flag bit CCPxIF ;to CCP1CON (PIRx register) Prescaler CLRF CCP1CON ;Turn CCP module off  1, 4, 16 MOVLW NEW_CAPT_PS;Load the W reg with CCPx CCPRxH CCPRxL ; the new prescaler pin ; move value and CCP ON and Capture MOVWF CCP1CON ;Load CCP1CON with this Edge Detect Enable ; value TMR1H TMR1L CCPxCON<3:0> System Clock (FOSC) DS40001291H-page 124  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 11.4 Compare Mode 11.4.2 TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is In Compare mode, Timer1 must be running in either constantly compared against the TMR1 register pair Timer mode or Synchronized Counter mode. The value. When a match occurs, the CCPx module may: compare operation may not work in Asynchronous Counter mode. • Toggle the CCPx output • Set the CCPx output 11.4.3 SOFTWARE INTERRUPT MODE • Clear the CCPx output When Generate Software Interrupt mode is chosen • Generate a Special Event Trigger (CCPxM<3:0>=1010), the CCPx module does not • Generate a Software Interrupt assert control of the CCPx pin (see the CCP1CON register). The action on the pin is based on the value of the CCPxM<3:0> control bits of the CCPx1CON register. 11.4.4 SPECIAL EVENT TRIGGER All Compare modes can generate an interrupt. When Special Event Trigger mode is chosen (CCPxM<3:0>=1011), the CCPx module does the FIGURE 11-2: COMPARE MODE following: OPERATION BLOCK • Resets Timer1 DIAGRAM • Starts an ADC conversion if ADC is enabled CCPxCON<3:0> Mode Select The CCPx module does not assert control of the CCPx pin in this mode (see the CCPxCON register). Set CCPxIF Interrupt Flag The Special Event Trigger output of the CCP occurs (PIRx) CCPx 4 immediately upon a match between the TMR1H, Pin CCPRxH CCPRxL TMR1L register pair and the CCPRxH, CCPRxL Q S register pair. The TMR1H, TMR1L register pair is not Output Comparator R Logic Match reset until the next rising edge of the Timer1 clock. This allows the CCPRxH, CCPRxL register pair to TMR1H TMR1L TRIS effectively provide a 16-bit programmable period Output Enable register for Timer1. Special Event Trigger Note1: The Special Event Trigger from the CCP Special Event Trigger will: module does not set interrupt flag bit • Clear TMR1H and TMR1L registers. TMRxIF of the PIR1 register. • NOT set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by • Set the GO/DONE bit to start the ADC conversion. changing the contents of the CCPRxH and CCPRxL register pair, between the 11.4.1 CCP PIN CONFIGURATION clock edge that generates the Special Event Trigger and the clock edge that The user must configure the CCPx pin as an output by generates the Timer1 Reset, will clearing the associated TRIS bit. preclude the Reset from occurring. Note: Clearing the CCP1CON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch.  2006-2015 Microchip Technology Inc. DS40001291H-page 125

PIC16F882/883/884/886/887 11.5 PWM Mode The PWM output (Figure11-4) has a time base (period) and a time that the output stays high (duty The PWM mode generates a Pulse-Width Modulated cycle). signal on the CCPx pin. The duty cycle, period and resolution are determined by the following registers: FIGURE 11-4: CCP PWM OUTPUT • PR2 • T2CON Period • CCPRxL Pulse Width • CCPxCON TMR2 = PR2 In Pulse-Width Modulation (PWM) mode, the CCP TMR2 = CCPRxL:CCPxCON<5:4> module produces up to a 10-bit resolution PWM output TMR2 = 0 on the CCPx pin. Since the CCPx pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCPx pin output driver. 11.5.1 PWM PERIOD Note: Clearing the CCPxCON register will The PWM period is specified by the PR2 register of relinquish CCPx control of the CCPx pin. Timer2. The PWM period can be calculated using the formula of Equation11-1. Figure11-3 shows a simplified block diagram of PWM operation. EQUATION 11-1: PWM PERIOD Figure11-4 shows a typical waveform of the PWM signal. PWM Period = PR2+14TOSC For a step-by-step procedure on how to set up the CCP (TMR2 Prescale Value) module for PWM operation, see Section11.5.7 “Setup for PWM Operation”. Note: TOSC = 1/FOSC FIGURE 11-3: SIMPLIFIED PWM BLOCK When TMR2 is equal to PR2, the following three events DIAGRAM occur on the next increment cycle: • TMR2 is cleared CCPxCON<5:4> Duty Cycle Registers • The CCPx pin is set. (Exception: If the PWM duty cycle=0%, the pin will not be set.) CCPRxL • The PWM duty cycle is latched from CCPRxL into CCPRxH. CCPRxH(2) (Slave) Note: The Timer2 postscaler (see Section7.1 CCPx “Timer2 Operation”) is not used in the Comparator R Q determination of the PWM frequency. S TMR2 (1) TRIS Comparator Clear Timer2, toggle CCPx pin and latch duty cycle PR2 Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. 2: In PWM mode, CCPRxH is a read-only register. DS40001291H-page 126  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 11.5.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB<1:0> bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPRxH register is read-only. Equation11-2 is used to calculate the PWM pulse width. Equation11-3 is used to calculate the PWM duty cycle ratio. EQUATION 11-2: PULSE WIDTH Pulse Width = CCPRxL:CCPxCON<5:4>  TOSC  (TMR2 Prescale Value) EQUATION 11-3: DUTY CYCLE RATIO CCPRxL:CCPxCON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------- 4PR2+1 The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure11-3).  2006-2015 Microchip Technology Inc. DS40001291H-page 127

PIC16F882/883/884/886/887 11.5.3 PWM RESOLUTION EQUATION 11-4: PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution log4PR2+1 Resolution = ------------------------------------------ bits will result in 1024 discrete duty cycles, whereas an 8-bit log2 resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is Note: If the pulse width value is greater than the 255. The resolution is a function of the PR2 register period the assigned PWM pin(s) will value as shown by Equation11-4. remain unchanged. TABLE 11-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 11-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 DS40001291H-page 128  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 11.5.4 OPERATION IN SLEEP MODE 11.5.7 SETUP FOR PWM OPERATION In Sleep mode, the TMR2register will not increment The following steps should be taken when configuring and the state of the module will not change. If the CCPx the CCP module for PWM operation: pin is driving a value, it will continue to drive that value. 1. Disable the PWM pin (CCPx) output drivers as When the device wakes up, TMR2 will continue from its an input by setting the associated TRIS bit. previous state. 2. Set the PWM period by loading the PR2 register. 11.5.5 CHANGES IN SYSTEM CLOCK 3. Configure the CCP module for the PWM mode FREQUENCY by loading the CCPxCON register with the appropriate values. The PWM frequency is derived from the system clock 4. Set the PWM duty cycle by loading the CCPRxL frequency. Any changes in the system clock frequency register and DCxB<1:0> bits of the CCPxCON will result in changes to the PWM frequency. See register. Section4.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. 5. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the 11.5.6 EFFECTS OF RESET PIR1 register. Any Reset will force all ports to Input mode and the • Set the Timer2 prescale value by loading the CCP registers to their Reset states. T2CKPS bits of the T2CON register. • Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCPx pin output driver by clearing the associated TRIS bit.  2006-2015 Microchip Technology Inc. DS40001291H-page 129

PIC16F882/883/884/886/887 11.6 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the The Enhanced PWM Mode can generate a PWM signal PWM pins is configurable and is selected by setting the on up to four different output pins with up to ten bits of CCP1M bits in the CCP1CON register appropriately. resolution. It can do this through four different PWM Table11-5 shows the pin assignments for each output modes: Enhanced PWM mode. • Single PWM Figure11-5 shows an example of a simplified block • Half-Bridge PWM diagram of the Enhanced PWM module. • Full-Bridge PWM, Forward mode Note: To prevent the generation of an • Full-Bridge PWM, Reverse mode incomplete waveform when the PWM is To select an Enhanced PWM mode, the P1M bits of the first enabled, the ECCP module waits until CCP1CON register must be set appropriately. the start of a new PWM period before Note: The PWM Enhanced mode is available on generating a PWM signal. the Enhanced Capture/Compare/PWM module (CCP1) only. FIGURE 11-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DC1B<1:0> P1M<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L CCP1/P1A CCP1/P1A TRISn CCPR1H (Slave) P1B P1B Output TRISn Comparator R Q Controller P1C P1C TMR2 (1) S TRISn P1D P1D Comparator Clear Timer2, TRISn toggle PWM pin and latch duty cycle PR2 PWM1CON Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. Note1: The TRIS register value for each PWM output must be configured appropriately. 2: Clearing the CCPxCON register will relinquish ECCP control of all PWM output pins. 3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions. TABLE 11-5: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode P1M<1:0> CCP1/P1A P1B P1C P1D Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Pulse Steering enables outputs in Single mode. DS40001291H-page 130  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 11-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse PR2+1 P1M<1:0> Signal 0 Width Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section11.6.6 “Programmable Dead-Band Delay Mode”).  2006-2015 Microchip Technology Inc. DS40001291H-page 131

PIC16F882/883/884/886/887 FIGURE 11-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) P1M<1:0> Signal 0 Pulse PR2+1 Width Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section11.6.6 “Programmable Dead-Band Delay Mode”). DS40001291H-page 132  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 11.6.1 HALF-BRIDGE MODE Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must In Half-Bridge mode, two pins are used as outputs to be cleared to configure P1A and P1B as outputs. drive push-pull loads. The PWM output signal is output on the CCPx/P1A pin, while the complementary PWM FIGURE 11-8: EXAMPLE OF HALF- output signal is output on the P1B pin (see Figure11-9). BRIDGE PWM OUTPUT This mode can be used for Half-Bridge applications, as shown in Figure11-9, or for Full-Bridge applications, Period Period where four power switches are being modulated with two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay P1A(2) can be used to prevent shoot-through current in Half- td Bridge power devices. The value of the PDC<6:0> bits of td the PWM1CON register sets the number of instruction P1B(2) cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output (1) (1) (1) remains inactive during the entire cycle. See Section11.6.6 “Programmable Dead-Band Delay td = Dead-Band Delay Mode” for more details of the dead-band delay Note 1: At this time, the TMR2 register is equal to the operations. PR2 register. 2: Output signals are shown as active-high. FIGURE 11-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A - Load FET Driver + P1B - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver P1A Load FET FET Driver Driver P1B  2006-2015 Microchip Technology Inc. DS40001291H-page 133

PIC16F882/883/884/886/887 11.6.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure11-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure11-11. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure11-11. P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 11-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D DS40001291H-page 134  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 11-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high.  2006-2015 Microchip Technology Inc. DS40001291H-page 135

PIC16F882/883/884/886/887 11.6.2.1 Direction Change in Full-Bridge The Full-Bridge mode does not provide dead-band Mode delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation In the Full-Bridge mode, the P1M1 bit in the CCP1CON where dead-band delay is required. This situation register allows users to control the forward/reverse occurs when both of the following conditions are true: direction. When the application firmware changes this direction control bit, the module will change to the new 1. The direction of the PWM output changes when direction on the next PWM cycle. the duty cycle of the output is at or near 100%. 2. The turn off time of the power switch, including A direction change is initiated in software by changing the power device and driver circuit, is greater the P1M1 bit of the CCP1CON register. The following than the turn on time. sequence occurs prior to the end of the current PWM period: Figure11-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty • The modulated outputs (P1B and P1D) are placed cycle. In this example, at time t1, the output P1A and in their inactive state. P1D become inactive, while output P1C becomes • The associated unmodulated outputs (P1A and active. Since the turn off time of the power devices is P1C) are switched to drive in the opposite longer than the turn on time, a shoot-through current direction. will flow through power devices QC and QD (see • PWM modulation resumes at the beginning of the Figure11-10) for the duration of ‘t’. The same next period. phenomenon will occur to power devices QA and QB See Figure11-12 for an illustration of this sequence. for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 11-12: EXAMPLE OF PWM DIRECTION CHANGE Signal Period(1) Period P1A (Active-High) P1B (Active-High) Pulse Width P1C (Active-High) (2) P1D (Active-High) Pulse Width Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is (1/Fosc)  TMR2 prescale value. DS40001291H-page 136  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 11-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential T = TOFF – TON Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver.  2006-2015 Microchip Technology Inc. DS40001291H-page 137

PIC16F882/883/884/886/887 11.6.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high- impedance state. The external circuits must keep the power switch devices in the Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). The CCP1M<1:0> bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. DS40001291H-page 138  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 11.6.4 ENHANCED PWM AUTO- A shutdown condition is indicated by the ECCPASE SHUTDOWN MODE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating The PWM mode supports an Auto-Shutdown mode that normally. If the bit is a ‘1’, the PWM outputs are in the will disable the PWM outputs when an external shutdown state. shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This When a shutdown event occurs, two things happen: mode is used to help prevent the PWM from damaging The ECCPASE bit is set to ‘1’. The ECCPASE will the application. remain set until cleared in firmware or an auto-restart The auto-shutdown sources are selected using the occurs (see Section11.6.5 “Auto-Restart Mode”). ECCPAS<2:0> bits of the ECCPAS register. A shutdown The enabled PWM pins are asynchronously placed in event may be generated by: their shutdown states. The PWM output pins are • A logic ‘0’ on the INT pin grouped into pairs [P1A/P1C] and [P1B/P1D]. The state of each pin pair is determined by the PSSAC and • Comparator C1 PSSBD bits of the ECCPAS register. Each pin pair may • Comparator C2 be placed into one of three states: • Setting the ECCPASE bit in firmware • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) FIGURE 11-14: AUTO-SHUTDOWN BLOCK DIAGRAM ECCPAS<2:0> PSSAC<0> 1 P1A_DRV 0 111 110 101 PSSAC<1> P1A 100 TRISx INT 011 From Comparator C2 010 PSSBD<0> 1 From Comparator C1 001 P1B_DRV 0 000 PRSEN PSSBD<1> R S P1B TRISx From Data Bus ECCPASE D Q Write to ECCPASE PSSAC<0> 1 P1C_DRV 0 PSSAC<1> P1C TRISx PSSBD<0> 1 P1D_DRV 0 PSSBD<1> P1D TRISx  2006-2015 Microchip Technology Inc. DS40001291H-page 139

PIC16F882/883/884/886/887 REGISTER 11-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits 000 =Auto-Shutdown is disabled 001 =Comparator C1 output high 010 =Comparator C2 output high(1) 011 =Either Comparators output is high 100 =VIL on INT pin 101 =VIL on INT pin or Comparator C1 output high 110 =VIL on INT pin or Comparator C2 output high 111 =VIL on INT pin or either Comparators output is high bit 3-2 PSSACn: Pins P1A and P1C Shutdown State Control bits 00 = Drive pins P1A and P1C to ‘0’ 01 = Drive pins P1A and P1C to ‘1’ 1x = Pins P1A and P1C tri-state bit 1-0 PSSBDn: Pins P1B and P1D Shutdown State Control bits 00 = Drive pins P1B and P1D to ‘0’ 01 = Drive pins P1B and P1D to ‘1’ 1x = Pins P1B and P1D tri-state Note 1: If C2SYNC is enabled, the shutdown will be delayed by Timer1. Note1: The auto-shutdown condition is a level- based signal, not an edge-based signal. As long as the level is present, the auto- shutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period. DS40001291H-page 140  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 11-15: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0) ShutdownEvent ECCPASE bit PWM Activity PWM Period ECCPASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes 11.6.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automati- cally restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register. If auto-restart is enabled, the ECCPASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPASE bit will be cleared via hardware and normal operation will resume. FIGURE 11-16: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) ShutdownEvent ECCPASE bit PWM Activity PWM Period Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes  2006-2015 Microchip Technology Inc. DS40001291H-page 141

PIC16F882/883/884/886/887 11.6.6 PROGRAMMABLE DEAD-BAND FIGURE 11-17: EXAMPLE OF HALF- DELAY MODE BRIDGE PWM OUTPUT In Half-Bridge applications where all power switches Period Period are modulated at the PWM frequency, the power Pulse Width switches normally require more time to turn off than to turn on. If both the upper and lower power switches are P1A(2) switched at the same time (one turned on, and the td other turned off), both switches may be on for a short td period of time until one switch completely turns off. P1B(2) During this brief interval, a very high current (shoot- through current) will flow through both power switches, (1) (1) (1) shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during td = Dead-Band Delay switching, turning on either of the power switches is normally delayed to allow the other switch to Note 1: At this time, the TMR2 register is equal to the completely turn off. PR2 register. In Half-Bridge mode, a digitally programmable dead- 2: Output signals are shown as active-high. band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure11-17 for illustration. The lower seven bits of the associated PWM1CON register (Register11-4) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 11-18: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A V - Load FET Driver + P1B V - V- DS40001291H-page 142  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 REGISTER DEFINITIONS: PWM CONTROL REGISTER 11-4: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits PDCn = Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active.  2006-2015 Microchip Technology Inc. DS40001291H-page 143

PIC16F882/883/884/886/887 11.6.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the Note: The associated TRIS bits must be set to PWM pins to be the modulated signal. Additionally, the output (‘0’) to enable the pin output driver same PWM signal can be simultaneously available on in order to see the PWM signal on the pin. multiple pins. While the PWM Steering mode is active, CCP1M<1:0> Once the Single Output mode is selected bits of the CCP1CON register select the PWM output (CCP1M<3:2>=11 and P1M<1:0>=00 of the polarity for the P1<D:A> pins. CCP1CON register), the user firmware can bring out The PWM auto-shutdown operation also applies to the same PWM signal to one, two, three or four output PWM Steering mode as described in Section11.6.4 pins by setting the appropriate STR<D:A> bits of the “Enhanced PWM Auto-Shutdown Mode”. An auto- PSTRCON register, as shown in Table11-5. shutdown event will only affect pins that have PWM outputs enabled. REGISTER DEFINITIONS: PULSE STEERING CONTROL REGISTER 11-5: PSTRCON: PULSE STEERING CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRD: Steering Enable bit D 1 = P1D pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1D pin is assigned to port pin bit 2 STRC: Steering Enable bit C 1 = P1C pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1C pin is assigned to port pin bit 1 STRB: Steering Enable bit B 1 = P1B pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1B pin is assigned to port pin bit 0 STRA: Steering Enable bit A 1 = P1A pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2>=11 and P1M<1:0>=00. DS40001291H-page 144  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 11-19: SIMPLIFIED STEERING BLOCK DIAGRAM STRA P1A Signal P1A pin CCP1M1 1 PORT Data 0 TRIS STRB P1B pin CCP1M0 1 PORT Data 0 TRIS STRC P1C pin CCP1M1 1 PORT Data 0 TRIS STRD P1D pin CCP1M0 1 PORT Data 0 TRIS Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0>=00 and CCP1M<3:2>=11. 2: Single PWM output requires setting at least one of the STRx bits.  2006-2015 Microchip Technology Inc. DS40001291H-page 145

PIC16F882/883/884/886/887 11.6.7.1 Steering Synchronization Figures 11-20 and 11-21 illustrate the timing diagrams of the PWM steering depending on the STRSYNC The STRSYNC bit of the PSTRCON register gives the setting. user two selections of when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRCON register. In this case, the output signal at the P1<D:A> pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. When the STRSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. FIGURE 11-20: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0) PWM Period PWM STRn P1<D:A> PORT Data PORT Data P1n = PWM FIGURE 11-21: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) PWM STRn P1<D:A> PORT Data PORT Data P1n = PWM DS40001291H-page 146  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 11-6: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 122 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 123 CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) 124 CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) 124 CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) 124 CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) 124 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC 92 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 34 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 36 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 81 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 78 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 78 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 54 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture and Compare. TABLE 11-7: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 122 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 123 ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 140 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PR2 Timer2 Period Register 83 PSTRCON — — — STRSYNC STRD STRC STRB STRA 144 PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 143 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 84 TMR2 Timer2 Module Register 83 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 49 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 54 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 58 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.  2006-2015 Microchip Technology Inc. DS40001291H-page 147

PIC16F882/883/884/886/887 12.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer • Half-duplex synchronous master independent of device program execution. The • Half-duplex synchronous slave EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous Interface (SCI), can be configured as a full-duplex modes asynchronous system or half-duplex synchronous • Sleep operation system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT The EUSART module implements the following terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems: with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate circuits, serial EEPROMs or other microcontrollers. • Wake-up on Break reception These devices typically do not have internal clocks for • 13-bit Break character transmit baud rate generation and require the external clock signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and receiver are shown in Figure12-1 and Figure12-2. FIGURE 12-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREG Register TXIF 8 MSb LSb TX/CK pin (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT SPEN Baud Rate Generator FOSC ÷ n TX9 BRG16 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 X 0 0 0 SPBRGH SPBRG BRGH X 1 1 0 0 BRG16 X 1 0 1 0 DS40001291H-page 148  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 12-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN OERR RCIDL RX/DT pin MSb RSR Register LSb Panind BCuoffnetrrol DReactaovery Stop (8) 7 • • • 1 0 START Baud Rate Generator FOSC RX9 ÷ n BRG16 n + 1 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 FIFO SPBRGH SPBRG BRGH X 1 1 0 0 FERR RX9D RCREG Register BRG16 X 1 0 1 0 8 Data Bus RCIF Interrupt RCIE The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCTL) These registers are detailed in Register12-1, Register12-2 and Register12-3, respectively.  2006-2015 Microchip Technology Inc. DS40001291H-page 149

PIC16F882/883/884/886/887 12.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the Note 1: When the SPEN bit is set the RX/DT I/O standard non-return-to-zero (NRZ) format. NRZ is pin is automatically configured as an input, implemented with two levels: a VOH mark state which regardless of the state of the correspond- represents a ‘1’ data bit, and a VOL space state which ing TRIS bit and whether or not the represents a ‘0’ data bit. NRZ refers to the fact that EUSART receiver is enabled. The RX/DT consecutively transmitted data bits of the same value pin data can be read via a normal PORT stay at the output level of that bit without returning to a read but PORT latch data output is pre- neutral level between each bit transmission. An NRZ cluded. transmission port idles in the mark state. Each character 2: The TXIF transmitter interrupt flag is set transmission consists of one Start bit followed by eight when the TXEN enable bit is set. or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the 12.1.1.2 Transmitting Data Stop bits are always marks. The most common data A transmission is initiated by writing a character to the format is eight bits. Each transmitted bit persists for a TXREG register. If this is the first character, or the period of 1/(Baud Rate). An on-chip dedicated 8-bit/16- previous character has been completely flushed from bit Baud Rate Generator is used to derive standard the TSR, the data in the TXREG is immediately baud rate frequencies from the system oscillator. See transferred to the TSR register. If the TSR still contains Table12-5 for examples of baud rate configurations. all or part of a previous character, the new character The EUSART transmits and receives the LSb first. The data is held in the TXREG until the Stop bit of the EUSART’s transmitter and receiver are functionally previous character has been transmitted. The pending independent, but share the same data format and baud character in the TXREG is then transferred to the TSR rate. Parity is not supported by the hardware, but can in one TCY immediately following the Stop bit be implemented in software and stored as the ninth transmission. The transmission of the Start bit, data bits data bit. and Stop bit sequence commences immediately following the transfer of the data to the TSR from the 12.1.1 EUSART ASYNCHRONOUS TXREG. TRANSMITTER 12.1.1.3 Transmit Interrupt Flag The EUSART transmitter block diagram is shown in Figure12-1. The heart of the transmitter is the serial The TXIF interrupt flag bit of the PIR1 register is set Transmit Shift Register (TSR), which is not directly whenever the EUSART transmitter is enabled and no accessible by software. The TSR obtains its data from character is being held for transmission in the TXREG. the transmit buffer, which is the TXREG register. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been 12.1.1.1 Enabling the Transmitter queued for transmission in the TXREG. The TXIF flag bit The EUSART transmitter is enabled for asynchronous is not cleared immediately upon writing TXREG. TXIF operations by configuring the following three control becomes valid in the second instruction cycle following bits: the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit • TXEN = 1 is read-only, it cannot be set or cleared by software. • SYNC = 0 The TXIF interrupt can be enabled by setting the TXIE • SPEN = 1 interrupt enable bit of the PIE1 register. However, the All other EUSART control bits are assumed to be in TXIF flag bit will be set whenever the TXREG is empty, their default state. regardless of the state of TXIE enable bit. Setting the TXEN bit of the TXSTA register enables the To use interrupts when transmitting data, set the TXIE transmitter circuitry of the EUSART. Clearing the SYNC bit only when there is more data to send. Clear the bit of the TXSTA register configures the EUSART for TXIE interrupt enable bit upon writing the last character asynchronous operation. Setting the SPEN bit of the of the transmission to the TXREG. RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. DS40001291H-page 150  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 12.1.1.4 TSR Status 12.1.1.6 Asynchronous Transmission Setup: The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRG register pair and status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired TRMT bit is set when the TSR register is empty and is baud rate (see Section12.3 “EUSART Baud cleared when a character is transferred to the TSR Rate Generator (BRG)”). register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit. No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 poll this bit to determine the TSR status. control bit. A set ninth data bit will indicate that Note: The TSR register is not mapped in data the eight Least Significant data bits are an memory, so it is not available to the user. address when the receiver is set for address detection. 12.1.1.5 Transmitting 9-Bit Characters 4. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit The EUSART supports 9-bit character transmissions. to be set. When the TX9 bit of the TXSTA register is set the EUSART will shift nine bits out for each character trans- 5. If interrupts are desired, set the TXIE interrupt mitted. The TX9D bit of the TXSTA register is the ninth, enable bit of the PIE1 register. An interrupt will and Most Significant, data bit. When transmitting 9-bit occur immediately provided that the GIE and data, the TX9D data bit must be written before writing PEIE bits of the INTCON register are also set. the eight Least Significant bits into the TXREG. All nine 6. If 9-bit transmission is selected, the ninth bit bits of data will be transferred to the TSR shift register should be loaded into the TX9D data bit. immediately after the TXREG is written. 7. Load 8-bit data into the TXREG register. This A special 9-bit Address mode is available for use with will start the transmission. multiple receivers. See Section12.1.2.7 “Address Detection” for more information on the Address mode. FIGURE 12-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag)  2006-2015 Microchip Technology Inc. DS40001291H-page 151

PIC16F882/883/884/886/887 FIGURE 12-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Transmit Buffer Reg. Empty Flag) 1 TCY TRMT bit Word 1 Word 2 (Transmit Shift Transmit Shift Reg. Transmit Shift Reg. Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 12-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 159 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 RCREG EUSART Receive Data Register 155 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 158 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 160 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 160 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 54 TXREG EUSART Transmit Data Register 150 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 157 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission. DS40001291H-page 152  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 12.1.2 EUSART ASYNCHRONOUS 12.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit, systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data Figure12-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts the baud rate, whereas the serial Receive Shift character reception, without generating an error, and Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data are immediately transferred to a two character First-In- recovery circuit counts a full bit time to the center of the First-Out (FIFO) memory. The FIFO buffering allows next bit. The bit is then sampled by a majority detect reception of two complete characters and the start of a circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. third character before software must start servicing the This repeats until all data bits have been sampled and EUSART receiver. The FIFO and RSR registers are not shifted into the RSR. One final bit time is measured and directly accessible by software. Access to the received the level sampled. This is the Stop bit, which is always data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this 12.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this character. See Section12.1.2.4 “Receive Framing The EUSART receiver is enabled for asynchronous Error” for more information on framing errors. operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have • CREN = 1 been received, the character in the RSR is transferred • SYNC = 0 to the EUSART receive FIFO and the RCIF interrupt • SPEN = 1 flag bit of the PIR1 register is set. The top character in All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the their default state. RCREG register. Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun of the TXSTA register configures the EUSART for asyn- condition is cleared. See Section12.1.2.5 chronous operation. Setting the SPEN bit of the RCSTA “Receive Overrun Error” for more register enables the EUSART and automatically config- information on overrun errors. ures the RX/DT I/O pin as an input. If the RX/DT pin is shared with an analog peripheral the analog I/O function 12.1.2.3 Receive Interrupts must be disabled by clearing the corresponding ANSEL The RCIF interrupt flag bit of the PIR1 register is set bit. whenever the EUSART receiver is enabled and there is Note: When the SPEN bit is set the TX/CK I/O an unread character in the receive FIFO. The RCIF pin is automatically configured as an interrupt flag bit is read-only, it cannot be set or cleared output, regardless of the state of the by software. corresponding TRIS bit and whether or RCIF interrupts are enabled by setting all of the not the EUSART transmitter is enabled. following bits: The PORT latch is disconnected from the • RCIE interrupt enable bit of the PIE1 register output driver so it is not possible to use the TX/CK pin as a general purpose output. • PEIE peripheral interrupt enable bit of the INTCON register • GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.  2006-2015 Microchip Technology Inc. DS40001291H-page 153

PIC16F882/883/884/886/887 12.1.2.4 Receive Framing Error 12.1.2.7 Address Detection Each character in the receive FIFO buffer has a A special Address Detection mode is available for use corresponding framing error Status bit. A framing error when multiple receivers share the same transmission indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA FERR bit of the RCSTA register. The FERR bit register. represents the status of the top unread character in the Address detection requires 9-bit character reception. receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters before reading the RCREG. with the ninth data bit set will be transferred to the The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt unread character in the receive FIFO. A framing error bit. All other characters will be ignored. (FERR = 1) does not preclude reception of additional Upon receiving an address character, user software characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon Reading the next character from the FIFO buffer will address match, user software must disable address advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next corresponding framing error. Stop bit occurs. When user software detects the end of The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit. affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. 12.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated If a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 12.1.2.6 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG. DS40001291H-page 154  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 12.1.2.8 Asynchronous Reception Setup: 12.1.2.9 9-bit Address Detection Mode Setup 1. Initialize the SPBRGH, SPBRG register pair and This mode would typically be used in RS-485 systems. the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section12.3 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRG register pair and 2. Enable the serial port by setting the SPEN bit. the BRGH and BRG16 bits to achieve the The SYNC bit must be clear for asynchronous desired baud rate (see Section12.3 “EUSART operation. Baud Rate Generator (BRG)”). 3. If interrupts are desired, set the RCIE bit of the 2. Enable the serial port by setting the SPEN bit. PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous INTCON register. operation. 4. If 9-bit reception is desired, set the RX9 bit. 3. If interrupts are desired, set the RCIE bit of the 5. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the 6. The RCIF interrupt flag bit will be set when a INTCON register. character is transferred from the RSR to the 4. Enable 9-bit reception by setting the RX9 bit. receive buffer. An interrupt will be generated if 5. Enable address detection by setting the ADDEN the RCIE interrupt enable bit was also set. bit. 7. Read the RCSTA register to get the error flags 6. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 7. The RCIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 8. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit register. was also set. 9. If an overrun occurred, clear the OERR flag by 8. Read the RCSTA register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. FIGURE 12-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 RCREG RCREG RCIDL Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.  2006-2015 Microchip Technology Inc. DS40001291H-page 155

PIC16F882/883/884/886/887 TABLE 12-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 159 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 RCREG EUSART Receive Data Register 155 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 158 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 160 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 160 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 54 TXREG EUSART Transmit Data Register 150 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 157 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception. DS40001291H-page 156  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 12.2 Clock Accuracy with The first (preferred) method uses the OSCTUNE Asynchronous Operation register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution The factory calibrates the Internal Oscillator block out- changes to the system clock source. See Section4.5 put (INTOSC). However, the INTOSC frequency may “Internal Clock Modes” for more information. drift as VDD or temperature changes, and this directly The other method adjusts the value in the Baud Rate affects the asynchronous baud rate. Two methods may Generator. This can be done automatically with the be used to adjust the baud rate clock, but both require Auto-Baud Detect feature (see Section12.3.1 “Auto- a reference clock source of some kind. Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. REGISTER DEFINITIONS: EUSART CONTROL REGISTER 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2006-2015 Microchip Technology Inc. DS40001291H-page 157

PIC16F882/883/884/886/887 REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001291H-page 158  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 REGISTER 12-3: BAUDCTL: BAUD RATE CONTROL REGISTER R-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the RB7/TX/CK pin 0 = Transmit non-inverted data to the RB7/TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2006-2015 Microchip Technology Inc. DS40001291H-page 159

PIC16F882/883/884/886/887 12.3 EUSART Baud Rate Generator If the system clock is changed during an active receive (BRG) operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to The Baud Rate Generator (BRG) is an 8-bit or 16-bit make sure that the receive operation is Idle before timer that is dedicated to the support of both the changing the system clock. asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the EXAMPLE 12-1: CALCULATING BAUD BRG16 bit of the BAUDCTL register selects 16-bit RATE ERROR mode. For a device with FOSC of 16 MHz, desired baud rate The SPBRGH, SPBRG register pair determines the of 9600, Asynchronous mode, 8-bit BRG: period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate Desired Baud Rate = ----------------------------F----O----S---C------------------------------ 64[SPBRGH:SPBRG]+1 period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCTL register. In Solving for SPBRGH:SPBRG: Synchronous mode, the BRGH bit is ignored. FOSC --------------------------------------------- Table12-3 contains the formulas for determining the Desired Baud Rate X = ---------------------------------------------–1 baud rate. Example12-1 provides a sample calculation 64 for determining the baud rate and baud rate error. 16000000 ------------------------ Typical baud rates and error values for various 9600 = ------------------------–1 asynchronous modes have been computed for your 64 convenience and are shown in Table12-3. It may be = 25.042 = 25 advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate Calculated Baud Rate = --1---6---0---0---0---0---0---0---- 6425+1 error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. = 9615 Writing a new value to the SPBRGH, SPBRG register Calc. Baud Rate–Desired Baud Rate pair causes the BRG timer to be reset (or cleared). This Error = -------------------------------------------------------------------------------------------- Desired Baud Rate ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. 9615–9600 = ---------------------------------- = 0.16% 9600 TABLE 12-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH, SPBRG register pair TABLE 12-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 159 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 158 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 160 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 160 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 157 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator. DS40001291H-page 160  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 1202 0.16 103 2400 2404 0.16 129 2400 0.00 119 2400 0.00 71 2404 0.16 51 9600 9470 -1.36 32 9600 0.00 29 9600 0.00 17 9615 0.16 12 10417 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 10417 0.00 11 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 — — — 57.6k — — — 57.60k 0.00 7 57.60k 0.00 2 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300 0.16 207 300 0.00 191 300 0.16 103 300 0.16 51 1200 1202 0.16 51 1200 0.00 47 1202 0.16 25 1202 0.16 12 2400 2404 0.16 25 2400 0.00 23 2404 0.16 12 — — — 9600 — — — 9600 0.00 5 — — — — — — 10417 10417 0.00 5 — — — 10417 0.00 2 — — — 19.2k — — — 19.20k 0.00 2 — — — — — — 57.6k — — — 57.60k 0.00 0 — — — — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — 2404 0.16 207 9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51 10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19231 0.16 25 57.6k 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8 115.2k 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —  2006-2015 Microchip Technology Inc. DS40001291H-page 161

PIC16F882/883/884/886/887 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51 2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25 9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — — 10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5 19.2k 19.23k 0.16 12 19.2k 0.00 11 — — — — — — 57.6k — — — 57.60k 0.00 3 — — — — — — 115.2k — — — 115.2k 0.00 1 — — — — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 299.9 -0.02 1666 1200 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 1199 -0.08 416 2400 2399 -0.03 520 2400 0.00 479 2400 0.00 287 2404 0.16 207 9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51 10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19.23k 0.16 25 57.6k 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8 115.2k 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.1 0.04 832 300.0 0.00 767 299.8 -0.108 416 300.5 0.16 207 1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51 2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25 9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — — 10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5 19.2k 19.23k 0.16 12 19.20k 0.00 11 — — — — — — 57.6k — — — 57.60k 0.00 3 — — — — — — 115.2k — — — 115.2k 0.00 1 — — — — — — DS40001291H-page 162  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 300.0 0.00 6666 1200 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 1200 -0.02 1666 2400 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 2401 0.04 832 9600 9597 -0.03 520 9600 0.00 479 9600 0.00 287 9615 0.16 207 10417 10417 0.00 479 10425 0.08 441 10433 0.16 264 10417 0 191 19.2k 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 19.23k 0.16 103 57.6k 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 57.14k -0.79 34 115.2k 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 117.6k 2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.01 3332 300.0 0.00 3071 299.9 -0.02 1666 300.1 0.04 832 1200 1200 0.04 832 1200 0.00 767 1199 -0.08 416 1202 0.16 207 2400 2398 0.08 416 2400 0.00 383 2404 0.16 207 2404 0.16 103 9600 9615 0.16 103 9600 0.00 95 9615 0.16 51 9615 0.16 25 10417 10417 0.00 95 10473 0.53 87 10417 0.00 47 10417 0.00 23 19.2k 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 25 19.23k 0.16 12 57.6k 58.82k 2.12 16 57.60k 0.00 15 55.56k -3.55 8 — — — 115.2k 111.1k -3.55 8 115.2k 0.00 7 — — — — — —  2006-2015 Microchip Technology Inc. DS40001291H-page 163

PIC16F882/883/884/886/887 12.3.1 AUTO-BAUD DETECT and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. Note1: If the WUE bit is set with the ABDEN bit, In the Auto-Baud Detect (ABD) mode, the clock to the auto-baud detection will occur on the byte BRG is reversed. Rather than the BRG clocking the following the Break character (see incoming RX signal, the RX signal is timing the BRG. Section12.3.2 “Auto-Wake-up on The Baud Rate Generator is used to time the period of Break”). a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the that it has five rising edges including the Stop bit edge. incoming character baud rate is within the range of the selected BRG clock source. Setting the ABDEN bit of the BAUDCTL register starts Some combinations of oscillator frequency the auto-baud calibration sequence (Figure12-6). and EUSART baud rates are not possible. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of 3: During the auto-baud process, the auto- the receive line, after the Start bit, the SPBRG begins baud counter starts counting at 1. Upon counting up using the BRG counter clock as shown in completion of the auto-baud sequence, to Table12-6. The fifth rising edge will occur on the RX pin achieve maximum accuracy, subtract 1 at the end of the eighth bit period. At that time, an from the SPBRGH:SPBRG register pair. accumulated value totaling the proper BRG period is left in the SPBRGH, SPBRG register pair, the ABDEN TABLE 12-6: BRG COUNTER CLOCK RATES bit is automatically cleared and the RCIF interrupt flag BRG Base BRG ABD is set. The value in the RCREG needs to be read to BRG16 BRGH Clock Clock clear the RCIF interrupt. RCREG content should be discarded. When calibrating for modes that do not use 0 0 FOSC/64 FOSC/512 the SPBRGH register the user can verify that the SPBRG register did not overflow by checking for 00h in 0 1 FOSC/16 FOSC/128 the SPBRGH register. 1 0 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 1 1 FOSC/4 FOSC/32 and BRGH bits as shown in Table12-6. During ABD, Note: During the ABD sequence, SPBRG and both the SPBRGH and SPBRG registers are used as a SPBRGH registers are both used as a 16-bit 16-bit counter, independent of the BRG16 bit setting. counter, independent of BRG16 setting. While calibrating the baud rate period, the SPBRGH FIGURE 12-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRG XXh 1Ch SPBRGH XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode DS40001291H-page 164  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 12.3.2 AUTO-WAKE-UP ON BREAK 12.3.2.1 Special Considerations During Sleep mode, all clocks to the EUSART are Break Character suspended. Because of this, the Baud Rate Generator To avoid character errors or character fragments during is inactive and a proper character reception cannot be a wake-up event, the wake-up character must be all performed. The Auto-Wake-up feature allows the zeros. controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. When the wake-up is enabled the function works independent of the low time on the data stream. If the The Auto-Wake-up feature is enabled by setting the WUE bit is set and a valid non-zero character is WUE bit of the BAUDCTL register. Once set, the normal received, the low time from the Start bit to the first rising receive sequence on RX/DT is disabled, and the edge will be interpreted as the wake-up event. The EUSART remains in an Idle state, monitoring for a wake- remaining bits in the character will be received as a up event independent of the CPU mode. A wake-up fragmented character and subsequent characters can event consists of a high-to-low transition on the RX/DT result in framing or overrun errors. line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) Therefore, the initial character in the transmission must be all ‘0’s. This must be 10 or more bit times, 13-bit The EUSART module generates an RCIF interrupt times recommended for LIN bus, or any number of bit coincident with the wake-up event. The interrupt is times for standard RS-232 devices. generated synchronously to the Q clocks in normal CPU operating modes (Figure12-7), and asynchronously if Oscillator Startup Time the device is in Sleep mode (Figure12-8). The interrupt Oscillator start-up time must be considered, especially condition is cleared by reading the RCREG register. in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync The WUE bit is automatically cleared by the low-to-high Break (or wake-up signal) character must be of transition on the RX line at the end of the Break. This sufficient length, and be followed by a sufficient signals to the user that the Break event is over. At this interval, to allow enough time for the selected oscillator point, the EUSART module is in Idle mode waiting to to start and provide proper initialization of the EUSART. receive the next character. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. FIGURE 12-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set.  2006-2015 Microchip Technology Inc. DS40001291H-page 165

PIC16F882/883/884/886/887 FIGURE 12-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RX/DT Line Note 1 RCIF Cleared due to User Read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. 12.3.3 BREAK CHARACTER SEQUENCE 12.3.4 RECEIVING A BREAK CHARACTER The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break special Break character sequences that are required by character in two ways. the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the Received data To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is bits of the TXSTA register. The Break character trans- assumed to have been initialized to the expected baud mission is then initiated by a write to the TXREG. The rate. value of data written to TXREG will be ignored and all A Break character has been received when; ‘0’s will be transmitted. • RCIF bit is set The SENDB bit is automatically reset by hardware after • FERR bit is set the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte • RCREG = 00h following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature character in the LIN specification). described in Section12.3.2 “Auto-Wake-up on The TRMT bit of the TXSTA register indicates when the Break”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an transmit operation is active or Idle, just as it does during RCIF interrupt, and receive the next data byte followed normal transmission. See Figure12-9 for the timing of by another interrupt. the Break character sequence. Note that following a Break character, the user will 12.3.3.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature. The following sequence will start a message frame For both methods, the user can set the ABDEN bit of header made up of a Break, followed by an auto-baud the BAUDCTL register before placing the EUSART in Sync byte. This sequence is typical of a LIN bus Sleep mode. master. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to enable the Break sequence. 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. DS40001291H-page 166  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 12-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit)  2006-2015 Microchip Technology Inc. DS40001291H-page 167

PIC16F882/883/884/886/887 12.4 EUSART Synchronous Mode 12.4.1.2 Clock Polarity Synchronous serial communications are typically used A clock polarity option is provided for Microwire in systems with a single master and one or more compatibility. Clock polarity is selected with the SCKP slaves. The master device contains the necessary bit of the BAUDCTL register. Setting the SCKP bit sets circuitry for baud rate generation and supplies the clock the clock Idle state as high. When the SCKP bit is set, for all devices in the system. Slave devices can take the data changes on the falling edge of each clock. advantage of the master clock by eliminating the Clearing the SCKP bit sets the Idle state as low. When internal clock generation circuitry. the SCKP bit is cleared, the data changes on the rising edge of each clock. There are two signal lines in Synchronous mode: a bidi- rectional data line and a clock line. Slaves use the 12.4.1.3 Synchronous Master Transmission external clock supplied by the master to shift the serial Data is transferred out of the device on the RX/DT pin. data into and out of their respective receive and trans- The RX/DT and TX/CK pin output drivers are automat- mit shift registers. Since the data line is bidirectional, ically enabled when the EUSART is configured for synchronous operation is half-duplex only. Half-duplex synchronous master transmit operation. refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. A transmission is initiated by writing a character to the The EUSART can operate as either a master or slave TXREG register. If the TSR still contains all or part of a device. previous character the new character data is held in the TXREG until the last bit of the previous character has Start and Stop bits are not used in synchronous been transmitted. If this is the first character, or the transmissions. previous character has been completely flushed from 12.4.1 SYNCHRONOUS MASTER MODE the TSR, the data in the TXREG is immediately trans- ferred to the TSR. The transmission of the character The following bits are used to configure the EUSART commences immediately following the transfer of the for Synchronous Master operation: data to the TSR from the TXREG. • SYNC = 1 Each data bit changes on the leading edge of the • CSRC = 1 master clock and remains valid until the subsequent • SREN = 0 (for transmit); SREN = 1 (for receive) leading clock edge. • CREN = 0 (for transmit); CREN = 1 (for receive) Note: The TSR register is not mapped in data • SPEN = 1 memory, so it is not available to the user. Setting the SYNC bit of the TXSTA register configures 12.4.1.4 Synchronous Master Transmission the device for synchronous operation. Setting the CSRC Setup: bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA 1. Initialize the SPBRGH, SPBRG register pair and register ensures that the device is in the Transmit mode, the BRGH and BRG16 bits to achieve the otherwise the device will be configured to receive. Setting desired baud rate (see Section12.3 “EUSART the SPEN bit of the RCSTA register enables the Baud Rate Generator (BRG)”). EUSART. If the RX/DT or TX/CK pins are shared with an 2. Enable the synchronous master serial port by analog peripheral the analog I/O functions must be setting bits SYNC, SPEN, and CSRC. disabled by clearing the corresponding ANSEL bits. 3. Disable Receive mode by clearing bits SREN 12.4.1.1 Master Clock and CREN. 4. Enable Transmit mode by setting the TXEN bit. Synchronous data transfers use a separate clock line, which is synchronous with the data. A device config- 5. If 9-bit transmission is desired, set the TX9 bit. ured as a master transmits the clock on the TX/CK line. 6. If interrupts are desired, set the TXIE bit of the The TX/CK pin output driver is automatically enabled PIE1 register and the GIE and PEIE bits of the when the EUSART is configured for synchronous INTCON register. transmit or receive operation. Serial data bits change 7. If 9-bit transmission is selected, the ninth bit on the leading edge to ensure they are valid at the trail- should be loaded in the TX9D bit. ing edge of each clock. One clock cycle is generated 8. Start transmission by loading data to the TXREG for each data bit. Only as many clock cycles are register. generated as there are data bits. DS40001291H-page 168  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 12-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. FIGURE 12-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 12-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 159 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 RCREG EUSART Receive Data Register 155 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 158 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 160 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 160 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 54 TXREG EUSART Transmit Data Register 150 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 157 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.  2006-2015 Microchip Technology Inc. DS40001291H-page 169

PIC16F882/883/884/886/887 12.4.1.5 Synchronous Master Reception 12.4.1.7 Receive Overrun Error Data is received at the RX/DT pin. The RX/DT pin The receive FIFO buffer can hold two characters. An output driver is automatically disabled when the overrun error will be generated if a third character, in its EUSART is configured for synchronous master receive entirety, is received before RCREG is read to access operation. the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will In Synchronous mode, reception is enabled by setting not be overwritten. The two characters in the FIFO either the Single Receive Enable bit (SREN of the buffer can be read, however, no additional characters RCSTA register) or the Continuous Receive Enable bit will be received until the error is cleared. The OERR bit (CREN of the RCSTA register). can only be cleared by clearing the overrun condition. When SREN is set and CREN is clear, only as many If the overrun error occurred when the SREN bit is set clock cycles are generated as there are data bits in a and CREN is clear then the error is cleared by reading single character. The SREN bit is automatically cleared RCREG. If the overrun occurred when the CREN bit is at the completion of one character. When CREN is set, set then the error condition is cleared by either clearing clocks are continuously generated until CREN is the CREN bit of the RCSTA register or by clearing the cleared. If CREN is cleared in the middle of a character SPEN bit which resets the EUSART. the CK clock stops immediately and the partial charac- ter is discarded. If SREN and CREN are both set, then 12.4.1.8 Receiving 9-Bit Characters SREN is cleared at the completion of the first character The EUSART supports 9-bit character reception. When and CREN takes precedence. the RX9 bit of the RCSTA register is set the EUSART To initiate reception, set either SREN or CREN. Data is will shift nine bits into the RSR for each character sampled at the RX/DT pin on the trailing edge of the received. The RX9D bit of the RCSTA register is the TX/CK clock pin and is shifted into the Receive Shift ninth, and Most Significant, data bit of the top unread Register (RSR). When a complete character is character in the receive FIFO. When reading 9-bit data received into the RSR, the RCIF bit is set and the char- from the receive FIFO buffer, the RX9D data bit must acter is automatically transferred to the two character be read before reading the eight Least Significant bits receive FIFO. The Least Significant eight bits of the top from the RCREG. character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are un-read 12.4.1.9 Synchronous Master Reception characters in the receive FIFO. Setup: 12.4.1.6 Slave Clock 1. Initialize the SPBRGH, SPBRG register pair for the appropriate baud rate. Set or clear the Synchronous data transfers use a separate clock line, BRGH and BRG16 bits, as required, to achieve which is synchronous with the data. A device configured the desired baud rate. as a slave receives the clock on the TX/CK line. The TX/ 2. Enable the synchronous master serial port by CK pin output driver is automatically disabled when the setting bits SYNC, SPEN and CSRC. device is configured for synchronous slave transmit or 3. Ensure bits CREN and SREN are clear. receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each 4. If interrupts are desired, set the RCIE bit of the clock. One data bit is transferred for each clock cycle. PIE1 register and the GIE and PEIE bits of the Only as many clock cycles should be received as there INTCON register. are data bits. 5. If 9-bit reception is desired, set bit RX9. 6. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 7. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. DS40001291H-page 170  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 12-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 159 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 RCREG EUSART Receive Data Register 155 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 158 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 160 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 160 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 54 TXREG EUSART Transmit Data Register 150 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 157 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.  2006-2015 Microchip Technology Inc. DS40001291H-page 171

PIC16F882/883/884/886/887 12.4.2 SYNCHRONOUS SLAVE MODE 12.4.2.1 EUSART Synchronous Slave Transmit The following bits are used to configure the EUSART for Synchronous slave operation: The operation of the Synchronous Master and Slave • SYNC = 1 modes are identical (see Section12.4.1.3 “Synchronous Master Transmission”), except in the • CSRC = 0 case of the Sleep mode. • SREN = 0 (for transmit); SREN = 1 (for receive) If two words are written to the TXREG and then the • CREN = 0 (for transmit); CREN = 1 (for receive) SLEEP instruction is executed, the following will occur: • SPEN = 1 1. The first character will immediately transfer to Setting the SYNC bit of the TXSTA register configures the the TSR register and transmit. device for synchronous operation. Clearing the CSRC bit 2. The second word will remain in TXREG register. of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register 3. The TXIF bit will not be set. ensures that the device is in the Transmit mode, 4. After the first character has been shifted out of otherwise the device will be configured to receive. Setting TSR, the TXREG register will transfer the second the SPEN bit of the RCSTA register enables the character to the TSR and the TXIF bit will now be EUSART. If the RX/DT or TX/CK pins are shared with an set. analog peripheral the analog I/O functions must be 5. If the PEIE and TXIE bits are set, the interrupt disabled by clearing the corresponding ANSEL bits. will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. 12.4.2.2 Synchronous Slave Transmission Setup: 1. Set the SYNC and SPEN bits and clear the CSRC bit. 2. Clear the CREN and SREN bits. 3. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 4. If 9-bit transmission is desired, set the TX9 bit. 5. Enable transmission by setting the TXEN bit. 6. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 7. Start transmission by writing the Least Significant eight bits to the TXREG register. TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 159 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 RCREG EUSART Receive Data Register 155 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 158 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 160 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 160 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 54 TXREG EUSART Transmit Data Register 150 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 157 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. DS40001291H-page 172  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 12.4.2.3 EUSART Synchronous Slave 12.4.2.4 Synchronous Slave Reception Reception Setup: The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the modes is identical (Section12.4.1.5 “Synchronous CSRC bit. Master Reception”), with the following exceptions: 2. If interrupts are desired, set the RCIE bit of the • Sleep PIE1 register and the GIE and PEIE bits of the INTCON register. • CREN bit is always set, therefore the receiver is never Idle 3. If 9-bit reception is desired, set the RX9 bit. • SREN bit, which is a “don’t care” in Slave mode 4. Set the CREN bit to enable reception. 5. The RCIF bit will be set when reception is A character may be received while in Sleep mode by complete. An interrupt will be generated if the setting the CREN bit prior to entering Sleep. Once the RCIE bit was set. word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the 6. If 9-bit mode is enabled, retrieve the Most interrupt generated will wake the device from Sleep Significant bit from the RX9D bit of the RCSTA and execute the next instruction. If the GIE bit is also register. set, the program will branch to the interrupt vector. 7. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. 8. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 159 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 RCREG EUSART Receive Data Register 155 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 158 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 160 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 160 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 54 TXREG EUSART Transmit Data Register 150 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 157 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.  2006-2015 Microchip Technology Inc. DS40001291H-page 173

PIC16F882/883/884/886/887 12.5 EUSART Operation During Sleep 12.5.2 SYNCHRONOUS TRANSMIT DURING SLEEP The EUSART WILL remain active during Sleep only in the Synchronous Slave mode. All other modes require To transmit during Sleep, all the following conditions the system clock and therefore cannot generate the must be met before entering Sleep mode: necessary signals to run the Transmit or Receive Shift • RCSTA and TXSTA Control registers must be registers during Sleep. configured for Synchronous Slave Transmission Synchronous Slave mode uses an externally generated (see Section12.4.2.2 “Synchronous Slave clock to run the Transmit and Receive Shift registers. Transmission Setup:”). • The TXIF interrupt flag must be cleared by writing 12.5.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the SLEEP TSR and transmit buffer. To receive during Sleep, all the following conditions 9. If interrupts are desired, set the TXIE bit of the must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON register. • RCSTA and TXSTA Control registers must be • Interrupt enable bits TXIE of the PIE1 register and configured for Synchronous Slave Reception (see PEIE of the INTCON register must set. Section12.4.2.4 “Synchronous Slave Reception Setup:”). Upon entering Sleep mode, the device will be ready to • If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the PIE1 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been INTCON register. completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and • The RCIF interrupt flag must be cleared by read- the TXIF flag will be set. Thereby, waking the processor ing RCREG to unload any pending characters in from Sleep. At this point, the TXREG is available to the receive buffer. accept another character for transmission, which will Upon entering Sleep mode, the device will be ready to clear the TXIF flag. accept data and clocks on the RX/DT and TX/CK pins, Upon waking from Sleep, the instruction following the respectively. When the data word has been completely SLEEP instruction will be executed. If the GIE global clocked in by the external device, the RCIF interrupt interrupt enable bit is also set then the Interrupt Service flag bit of the PIR1 register will be set. Thereby, waking Routine at address 0004h will be called. the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. DS40001291H-page 174  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 13.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 13.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated CircuitTM (I2CTM) - Full Master mode - Slave mode (with general address call). The I2C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode. 13.2 Control Registers The MSSP module has three associated registers. These include a STATUS register and two control registers. Register13-1 shows the MSSP STATUS register (SSPSTAT), Register13-2 shows the MSSP Control Register 1 (SSPCON), and Register13-3 shows the MSSP Control Register 2 (SSPCON2).  2006-2015 Microchip Technology Inc. DS40001291H-page 175

PIC16F882/883/884/886/887 REGISTER 13-1: SSPSTAT: SSP STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I 2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit CKP = 0: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK CKP = 1: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I 2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty DS40001291H-page 176  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 REGISTER 13-2: SSPCON: SSP CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register (must be cleared in software). 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I 2 C Slave mode: SCK release control 1 = Release clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C Master mode: Unused in this mode bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1)) 1001 = Load Mask function 1010 = Reserved 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled  2006-2015 Microchip Technology Inc. DS40001291H-page 177

PIC16F882/883/884/886/887 REGISTER 13-3: SSPCON2: SSP CONTROL REGISTER 2 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C Master mode only) In Master Transmit mode: 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (in I2C Master mode only) In Master Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCK Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). DS40001291H-page 178  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 13.3 SPI Mode FIGURE 13-1: MSSP BLOCK DIAGRAM (SPIMODE) The SPI mode allows eight bits of data to be synchronously transmitted and received, Internal Data Bus simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are Read Write used: • Serial Data Out (SDO) – RC5/SDO SSPBUF Reg • Serial Data In (SDI) – RC4/SDI/SDA • Serial Clock (SCK) – RC3/SCK/SCL Additionally, a fourth pin may be used when in any SSPSR Reg Slave mode of operation: SDI bit 0 Shift Clock • Slave Select (SS) – RA5/SS/AN4 SDO 13.3.1 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate SS Control Enable control bits SSPCON<5:0> and SSPSTAT<7:6>. These control bits allow the following to be specified: SS Edge Select • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) 2 • Clock polarity (Idle state of SCK) Clock Select • Data input sample phase (middle or end of data SSPM<3:0> output time) SMP:CKE • Clock edge (output data on rising/falling edge of 2 4 ( T M R 2 2 O u tp u t) SCK) Edge • Clock rate (Master mode only) Select Prescaler TOSC • Slave Select mode (Slave mode only) SCK 4, 16, 64 Figure13-1 shows the block diagram of the MSSP Data to TX/RX in SSPSR module, when in SPI mode. TRIS bit Note: I/O pins have diode protection to VDD and VSS. The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPBUF register. Then, the buffer full-detect bit BF of the SSPSTAT register and the interrupt flag bit SSPIF of the PIR1 register are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit WCOL of the SSPCON register will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully.  2006-2015 Microchip Technology Inc. DS40001291H-page 179

PIC16F882/883/884/886/887 When the application software is expecting to receive 13.3.2 ENABLING SPI I/O valid data, the SSPBUF should be read before the next To enable the serial port, SSP Enable bit SSPEN of the byte of data to transfer is written to the SSPBUF. The SSPCON register must be set. To reset or reconfigure buffer full bit BF of the SSPSTAT register indicates SPI mode, clear the SSPEN bit, re-initialize the when SSPBUF has been loaded with the received data SSPCON registers, and then set the SSPEN bit. This (transmission is complete). When the SSPBUF is read, configures the SDI, SDO, SCK and SS pins as serial the BF bit is cleared. This data may be irrelevant if the port pins. For the pins to behave as the serial port SPI is only a transmitter. Generally, the MSSP Interrupt function, some must have their data direction bits (in is used to determine when the transmission/reception the TRIS register) appropriately programmed. That is: has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, • SDI is automatically controlled by the SPI module then software polling can be done to ensure that a write • SDO must have TRISC<5> bit cleared collision does not occur. Example13-1 shows the • SCK (Master mode) must have TRISC<3> bit loading of the SSPBUF (SSPSR) for data transmission. cleared The SSPSR is not directly readable or writable, and • SCK (Slave mode) must have TRISC<3> bit set can only be accessed by addressing the SSPBUF • SS must have TRISA<5> bit set register. Additionally, the MSSP STATUS register Any serial port function that is not desired may be (SSPSTAT register) indicates the various status overridden by programming the corresponding data conditions. direction (TRIS) register to the opposite value. EXAMPLE 13-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)? GOTO LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS40001291H-page 180  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 13.3.3 MASTER MODE The clock polarity is selected by appropriately program- ming the CKP bit of the SSPCON register. This, then, The master can initiate the data transfer at any time would give waveforms for SPI communication as because it controls the SCK. The master determines shown in Figure13-2, Figure13-4 and Figure13-5, when the slave is to broadcast data by the software where the MSb is transmitted first. In Master mode, the protocol. SPI clock rate (bit rate) is user programmable to be one In Master mode, the data is transmitted/received as of the following: soon as the SSPBUF register is written to. If the SPI is • FOSC/4 (or TCY) only going to receive, the SDO output could be dis- • FOSC/16 (or 4 • TCY) abled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin • FOSC/64 (or 16 • TCY) at the programmed clock rate. As each byte is • Timer2 output/2 received, it will be loaded into the SSPBUF register as This allows a maximum data rate (at 40 MHz) of a normal received byte (interrupts and Status bits 10.00Mbps. appropriately set). This could be useful in receiver Figure13-2 shows the waveforms for Master mode. applications as a “Line Activity Monitor” mode. When the CKE bit of the SSPSTAT register is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit of the SSPSTAT register. The time when the SSPBUF is loaded with the received data is shown. FIGURE 13-2: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2 SSPBUF  2006-2015 Microchip Technology Inc. DS40001291H-page 181

PIC16F882/883/884/886/887 13.3.4 SLAVE MODE the SDO pin is no longer driven, even if in the mid- dle of a transmitted byte, and becomes a floating In Slave mode, the data is transmitted and received as output. External pull-up/pull-down resistors may be the external clock pulses appear on SCK. When the desirable, depending on the application. last bit is latched, the SSPIF interrupt flag bit of the PIR1 register is set. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = While in Slave mode, the external clock is supplied by 0100), the SPI module will reset if the SS the external clock source on the SCK pin. This external pin is set to VDD. clock must meet the minimum high and low times, as specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE set (SSPSTAT register), then the SS pin While in Sleep mode, the slave can transmit/receive control must be enabled. data. When a byte is received, the device will wake-up from Sleep. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to 13.3.5 SLAVE SELECT a high level, or clearing the SSPEN bit. SYNCHRONIZATION To emulate two-wire communication, the SDO pin can The SS pin allows a Synchronous Slave mode. The be connected to the SDI pin. When the SPI needs to SPI must be in Slave mode with SS pin control operate as a receiver, the SDO pin can be configured enabled (SSPCON<3:0> = 04h). The pin must not as an input. This disables transmissions from the SDO. be driven low for the SS pin to function as an input. The SDI can always be left as an input (SDI function), The Data Latch must be high. When the SS pin is since it cannot create a bus conflict. low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, FIGURE 13-3: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Next Q4 Cycle SSPSR to after Q2 SSPBUF DS40001291H-page 182  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 13-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Next Q4 Cycle SSPSR to after Q2 SSPBUF FIGURE 13-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Required SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Next Q4 Cycle after Q2 SSPSR to SSPBUF  2006-2015 Microchip Technology Inc. DS40001291H-page 183

PIC16F882/883/884/886/887 13.3.6 SLEEP OPERATION 13.3.8 BUS MODE COMPATIBILITY In Master mode, all module clocks are halted, and the Table13-1 shows the compatibility between the transmission/reception will remain in that state until the standard SPI modes and the states of the CKP and device wakes from Sleep. After the device returns to CKE control bits. normal mode, the module will continue to transmit/ receive data. TABLE 13-1: SPI BUS MODES In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This allows the Standard SPI Mode Control Bits State device to be placed in Sleep mode and data to be Terminology CKP CKE shifted into the SPI transmit/receive shift register. 0, 0 0 1 When all eight bits have been received, the MSSP interrupt flag bit will be set and, if enabled, will wake the 0, 1 0 0 device from Sleep. 1, 0 1 1 1, 1 1 0 13.3.7 EFFECTS OF A RESET There is also a SMP bit that controls when the data will A Reset disables the MSSP module and terminates the be sampled. current transfer. TABLE 13-2: REGISTERS ASSOCIATED WITH SPI OPERATION Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page INTCON GIE/GIEH PEIE/GIEL T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 179 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 177 SSPSTAT SMP CKE D/A P S R/W UA BF 176 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 40 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 54 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. DS40001291H-page 184  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 13.4 MSSP I2C Operation The SSPCON register allows control of the I2C operation. The SSPM<3:0> mode selection bits The MSSP module in I2C mode, fully implements all (SSPCON register) allow one of the following I2C modes master and slave functions (including general call to be selected: support) and provides interrupts on Start and Stop bits in • I2C Master mode, clock = OSC/4 (SSPADD +1) hardware, to determine a free bus (Multi-Master mode). The MSSP module implements the standard mode • I2C Slave mode (7-bit address) specifications, as well as 7-bit and 10-bit addressing. • I2C Slave mode (10-bit address) Two pins are used for data transfer. These are the • I2C Slave mode (7-bit address), with Start and RC3/SCK/SCL pin, which is the clock (SCL), and the Stop bit interrupts enabled RC4/SDI/SDA pin, which is the data (SDA). The user • I2C Slave mode (10-bit address), with Start and must configure these pins as inputs or outputs through Stop bit interrupts enabled the TRISC<4:3> bits. • I2C firmware controlled master operation, slave is The MSSP module functions are enabled by setting idle MSSP Enable bit SSPEN of the SSPCON register. Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, FIGURE 13-6: MSSP BLOCK DIAGRAM provided these pins are programmed to be inputs by (I2C MODE) setting the appropriate TRISC bits. 13.4.1 SLAVE MODE Internal Data Bus In Slave mode, the SCL and SDA pins must be Read Write configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data SSPBUF Reg when required (slave-transmitter). RC3/SCK/SCL When an address is matched, or the data transfer after Shift an address match is received, the hardware Clock automatically will generate the Acknowledge (ACK) SSPSR Reg pulse and load the SSPBUF register with the received RC4/ MSb LSb value currently in the SSPSR register. SDI/ SDA If either or both of the following conditions are true, the Match Detect Addr Match MSSP module will not give this ACK pulse: a) The buffer full bit BF (SSPCON register) was set before the transfer was received. SSPMSK Reg b) The overflow bit SSPOV (SSPCON register) was set before the transfer was received. SSPADD Reg In this event, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF of the PIR1 register is Start and Set, Reset set. The BF bit is cleared by reading the SSPBUF Stop bit Detect S, P bits (SSPSTAT Reg) register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and Note: I/O pins have diode protection to VDD and VSS. low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter #100 The MSSP module has these six registers for I2C and parameter #101. operation: • MSSP Control Register 1 (SSPCON) • MSSP Control Register 2 (SSPCON2) • MSSP STATUS register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible • MSSP Address register (SSPADD) • MSSP Mask register (SSPMSK)  2006-2015 Microchip Technology Inc. DS40001291H-page 185

PIC16F882/883/884/886/887 13.4.1.1 Addressing 13.4.1.2 Reception Once the MSSP module has been enabled, it waits for When the R/W bit of the address byte is clear and an a Start condition to occur. Following the Start condition, address match occurs, the R/W bit of the SSPSTAT the eight bits are shifted into the SSPSR register. All register is cleared. The received address is loaded into incoming bits are sampled with the rising edge of the the SSPBUF register. clock (SCL) line. The value of register SSPSR<7:1> is When the address byte overflow condition exists, then compared to the value of the SSPADD register. The no Acknowledge (ACK) pulse is given. An overflow address is compared on the falling edge of the eighth condition is defined as either bit BF (SSPSTAT register) clock (SCL) pulse. If the addresses match, and the BF is set, or bit SSPOV (SSPCON register) is set. and SSPOV bits are clear, the following events occur: An MSSP interrupt is generated for each data transfer a) The SSPSR register value is loaded into the byte. Flag bit SSPIF of the PIR1 register must be SSPBUF register. cleared in software. The SSPSTAT register is used to b) The buffer full bit BF is set. determine the status of the byte. c) An ACK pulse is generated. 13.4.1.3 Transmission d) MSSP interrupt flag bit, SSPIF of the PIR1 register, is set on the falling edge of the ninth When the R/W bit of the incoming address byte is set SCL pulse (interrupt is generated, if enabled). and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is In 10-bit address mode, two address bytes need to be loaded into the SSPBUF register. The ACK pulse will received by the slave. The five Most Significant bits be sent on the ninth bit and pin RC3/SCK/SCL is held (MSb) of the first address byte specify if this is a 10-bit low. The transmit data must be loaded into the address. The R/W bit (SSPSTAT register) must specify SSPBUF register, which also loads the SSPSR regis- a write so the slave device will receive the second ter. Then pin RC3/SCK/SCL should be enabled by set- address byte. For a 10-bit address, the first byte would ting bit CKP (SSPCON register). The master must equal ‘1111 0 A9 A8 0’, where A9 and A8 are the monitor the SCL pin prior to asserting another clock two MSb’s of the address. pulse. The slave devices may be holding off the master The sequence of events for 10-bit addressing is as by stretching the clock. The eight data bits are shifted follows, with steps 7-9 for slave-transmitter: out on the falling edge of the SCL input. This ensures 1. Receive first (high) byte of address (bit SSPIF of that the SDA signal is valid during the SCL high time the PIR1 register and bits BF and UA of the (Figure13-8). SSPSTAT register are set). An MSSP interrupt is generated for each data transfer 2. Update the SSPADD register with second (low) byte. The SSPIF bit must be cleared in software and byte of address (clears bit UA and releases the the SSPSTAT register is used to determine the status SCL line). of the byte. The SSPIF bit is set on the falling edge of 3. Read the SSPBUF register (clears bit BF) and the ninth clock pulse. clear flag bit SSPIF. As a slave-transmitter, the ACK pulse from the master- 4. Receive second (low) byte of address (bits receiver is latched on the rising edge of the ninth SCL SSPIF, BF, and UA are set). input pulse. If the SDA line is high (not ACK), then the 5. Update the SSPADD register with the first (high) data transfer is complete. When the ACK is latched by byte of address. If match releases SCL line, this the slave, the slave logic is reset and the slave moni- will clear bit UA. tors for another occurrence of the Start bit. If the SDA line was low (ACK), the transmit data must be loaded 6. Read the SSPBUF register (clears bit BF) and into the SSPBUF register, which also loads the SSPSR clear flag bit SSPIF. register. Pin RC3/SCK/SCL should be enabled by 7. Receive Repeated Start condition. setting bit CKP. 8. Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. DS40001291H-page 186  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 13-7: I2C™ SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address R/W = 0 Receiving Data ACK Receiving Data Not ACK ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF Bus Master Terminates Transfer BF Cleared in software SSPBUF register is read SSPOV Bit SSPOV is set because the SSPBUF register is still full ACK is not sent FIGURE 13-8: I2C™ SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) R/W = 0 Receiving Address R/W = 1 Transmitting Data Not ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Data in SCL held low Sampled while CPU responds to SSPIF SSPIF BF Cleared in software From SSP Interrupt SSPBUF is written in software Service Routine CKP Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set)  2006-2015 Microchip Technology Inc. DS40001291H-page 187

PIC16F882/883/884/886/887 13.4.2 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the The addressing procedure for the I2C bus is such that, SSPIF interrupt flag bit is set. the first byte after the Start condition usually deter- When the interrupt is serviced, the source for the inter- mines which device will be the slave addressed by the rupt can be checked by reading the contents of the master. The exception is the general call address, SSPBUF. The value can be used to determine if the which can address all devices. When this address is address was device specific or a general call address. used, all devices should, in theory, respond with an Acknowledge. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match, and the UA The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT register). If the general call address is sampled when the GCEN bit is set, and while the consists of all 0’s with R/W = 0. slave is configured in 10-bit address mode, then the The general call address is recognized (enabled) when second half of the address is not necessary. The UA bit the General Call Enable (GCEN) bit is set (SSPCON2 will not be set, and the slave will begin receiving data register). Following a Start bit detect, eight bits are after the Acknowledge (Figure13-9). shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 13-9: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF Cleared in software SSPBUF is read SSPOV ‘0’ GCEN ‘1’ DS40001291H-page 188  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 13.4.3 MASTER MODE 13.4.4 I2C™ MASTER MODE SUPPORT Master mode of operation is supported by interrupt Master mode is enabled by setting and clearing the generation on the detection of the Start and Stop appropriate SSPM bits in SSPCON and by setting the conditions. The Stop (P) and Start (S) bits are cleared SSPEN bit. Once Master mode is enabled, the user from a Reset, or when the MSSP module is disabled. has the following six options: Control of the I2C bus may be taken when the P bit is 1. Assert a Start condition on SDA and SCL. set, or the bus is idle, with both the S and P bits clear. 2. Assert a Repeated Start condition on SDA and In Master mode, the SCL and SDA lines are manipu- SCL. lated by the MSSP hardware. 3. Write to the SSPBUF register initiating The following events will cause SSP Interrupt Flag bit, transmission of data/address. SSPIF, to be set (SSP Interrupt if enabled): 4. Generate a Stop condition on SDA and SCL. • Start condition 5. Configure the I2C port to receive data. • Stop condition 6. Generate an Acknowledge condition at the end • Data transfer byte transmitted/received of a received byte of data. • Acknowledge transmit • Repeated Start condition Note: The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to imitate transmission, before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. 2 FIGURE 13-10: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM<3:0> Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA SDA In CSlhoicftk ect SSPSR Dete) MSb LSb OL urc able WCk so SCL Receive En StAacrGtk enbnoit,ew Srlaettodepg ebit, Clock Cntl ck Arbitrate/hold off cloc o( Cl Start bit Detect Stop bit Detect SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT) Clock Arbitration Set SSPIF, BCLIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) End of XMIT/RCV Note: I/O pins have diode protection to VDD and VSS.  2006-2015 Microchip Technology Inc. DS40001291H-page 189

PIC16F882/883/884/886/887 13.4.4.1 I2C™ Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock a) The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable (SEN) bit (SSPCON2 register). ended with a Stop condition or with a Repeated Start b) SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. c) The user loads the SSPBUF with the address to In Master Transmitter mode, serial data is output transmit. through SDA, while SCL outputs the serial clock. The d) Address is shifted out the SDA pin until all eight first byte transmitted contains the slave address of the bits are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. e) The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted eight bits at a time. After each byte is trans- ACKSTAT bit (SSPCON2 register). mitted, an Acknowledge bit is received. Start and Stop f) The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. bit. In Master Receive mode, the first byte transmitted con- g) The user loads the SSPBUF with eight bits of tains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be h) Data is shifted out the SDA pin until all eight bits logic ‘1’. Thus, the first byte transmitted is a 7-bit slave are transmitted. address followed by a ‘1’ to indicate receive bit. Serial i) The MSSP module shifts in the ACK bit from the data is received via SDA, while SCL outputs the serial slave device and writes its value into the clock. Serial data is received eight bits at a time. After ACKSTAT bit (SSPCON2 register). each byte is received, an Acknowledge bit is transmit- ted. Start and Stop conditions indicate the beginning j) The MSSP module generates an interrupt at the and end of transmission. end of the ninth clock cycle by setting the SSPIF bit. The Baud Rate Generator used for the SPI mode oper- k) The user generates a Stop condition by setting ation is now used to set the SCL clock frequency for either 100 kHz, 400 kHz, or 1 MHz I2C operation. The the Stop Enable bit PEN (SSPCON2 register). Baud Rate Generator reload value is contained in the l) Interrupt is generated once the Stop condition is lower seven bits of the SSPADD register. The Baud complete. Rate Generator will automatically begin counting on a write to the SSPBUF. Once the given operation is com- plete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. DS40001291H-page 190  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 13.4.5 BAUD RATE GENERATOR In I2C Master mode, the reload value for the BRG is located in the lower seven bits of the SSPADD register (Figure13-11). When the BRG is loaded with this value, the BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. If clock arbitration is taking place, for instance, the BRG will be reloaded when the SCL pin is sampled high (Figure13-12). FIGURE 13-11: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPADD<6:0> SSPM<3:0> Reload Reload SCL Control CLKOUT BRG Down Counter FOSC/4 FIGURE 13-12: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL de-asserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload  2006-2015 Microchip Technology Inc. DS40001291H-page 191

PIC16F882/883/884/886/887 13.4.6 I2C™ MASTER MODE START 13.4.6.1 WCOL Status Flag CONDITION TIMING If the user writes the SSPBUF when a Start sequence To initiate a Start condition, the user sets the Start is in progress, the WCOL is set and the contents of the Condition Enable bit SEN of the SSPCON2 register. If buffer are unchanged (the write does not occur). the SDA and SCL pins are sampled high, the Baud Note: Because queuing of events is not allowed, Rate Generator is reloaded with the contents of writing to the lower five bits of SSPCON2 SSPADD<6:0> and starts its count. If SCL and SDA are is disabled until the Start condition is both sampled high when the Baud Rate Generator complete. times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low, while SCL is high, is the Start condition, and causes the S bit of the SSPSTAT register to be set. Following this, the Baud Rate Gener- ator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPCON2 register will be automatically cleared by hardware, the Baud Rate Generator is suspended leaving the SDA line held low and the Start condition is complete. Note: If, at the beginning of the Start condition, the SDA and SCL pins are already sam- pled low, or if during the Start condition the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted, and the I2C module is reset into its Idle state. FIGURE 13-13: FIRST START BIT TIMING Set S bit (SSPSTAT) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st Bit 2nd Bit SDA TBRG SCL TBRG S DS40001291H-page 192  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 13.4.7 I2C™ MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other A Repeated Start condition occurs when the RSEN bit event is in progress, it will not take effect. (SSPCON2 register) is programmed high and the I2C 2: A bus collision during the Repeated Start logic module is in the Idle state. When the RSEN bit is condition occurs if: set, the SCL pin is asserted low. When the SCL pin is • SDA is sampled low when SCL goes sampled low, the Baud Rate Generator is loaded with from low-to-high. the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one Baud • SCL goes low before SDA is Rate Generator count (TBRG). When the Baud Rate asserted low. This may indicate that Generator times out, if SDA is sampled high, the SCL another master is attempting to pin will be de-asserted (brought high). When SCL is transmit a data “1”. sampled high, the Baud Rate Generator is reloaded Immediately following the SSPIF bit getting set, the with the contents of SSPADD<6:0> and begins count- user may write the SSPBUF with the 7-bit address in ing. SDA and SCL must be sampled high for one TBRG. 7-bit mode, or the default first address in 10-bit mode. This action is then followed by assertion of the SDA pin After the first eight bits are transmitted and an ACK is (SDA = 0) for one TBRG, while SCL is high. Following received, the user may then transmit an additional eight this, the RSEN bit (SSPCON2 register) will be automat- bits of address (10-bit mode), or eight bits of data (7-bit ically cleared and the Baud Rate Generator will not be mode). reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, 13.4.7.1 WCOL Status Flag the S bit (SSPSTAT register) will be set. The SSPIF bit If the user writes the SSPBUF when a Repeated Start will not be set until the Baud Rate Generator has timed sequence is in progress, the WCOL is set and the out. contents of the buffer are unchanged (the write does not occur). Note: Because queuing of events is not allowed, writing of the lower five bits of SSPCON2 is disabled until the Repeated Start condition is complete. FIGURE 13-14: REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 SDA = 1, occurs here, At completion of Start bit, SDA = 1, SCL = 1 hardware clear RSEN bit SCL (no change) and set SSPIF TBRG TBRG TBRG 1st bit SDA Falling edge of ninth clock Write to SSPBUF occurs here End of Xmit TBRG SCL TBRG Sr = Repeated Start  2006-2015 Microchip Technology Inc. DS40001291H-page 193

PIC16F882/883/884/886/887 13.4.8 I2C™ MASTER MODE 13.4.8.3 ACKSTAT Status Flag TRANSMISSION In Transmit mode, the ACKSTAT bit (SSPCON2 Transmission of a data byte, a 7-bit address, or the register) is cleared when the slave has sent an other half of a 10-bit address, is accomplished by sim- Acknowledge (ACK = 0), and is set when the slave ply writing a value to the SSPBUF register. This action does not Acknowledge (ACK = 1). A slave sends an will set the Buffer Full bit, BF, and allow the Baud Rate Acknowledge when it has recognized its address Generator to begin counting and start the next trans- (including a general call), or when the slave has mission. Each bit of address/data will be shifted out properly received its data. onto the SDA pin after the falling edge of SCL is 13.4.9 I2C™ MASTER MODE RECEPTION asserted (see data hold time specification, parameter 106). SCL is held low for one Baud Rate Generator roll- Master mode reception is enabled by programming the over count (TBRG). Data should be valid before SCL is Receive Enable bit, RCEN (SSPCON2 register). released high (see data setup time specification, parameter 107). When the SCL pin is released high, it Note: The MSSP module must be in an Idle state is held that way for TBRG. The data on the SDA pin before the RCEN bit is set, or the RCEN bit must remain stable for that duration and some hold will be disregarded. time after the next falling edge of SCL. After the eighth The Baud Rate Generator begins counting, and on bit is shifted out (the falling edge of the eighth clock), each rollover, the state of the SCL pin changes (high- the BF bit is cleared and the master releases SDA, to-low/low-to-high) and data is shifted into the SSPSR. allowing the slave device being addressed to respond After the falling edge of the eighth clock, the RCEN bit with an ACK bit during the ninth bit time, if an address is automatically cleared, the contents of the SSPSR are match occurs, or if data was received properly. The loaded into the SSPBUF, the BF bit is set, the SSPIF status of ACK is written into the ACKDT bit on the fall- flag bit is set and the Baud Rate Generator is sus- ing edge of the ninth clock. If the master receives an pended from counting, holding SCL low. The MSSP is Acknowledge, the Acknowledge Status bit, ACKSTAT, now in Idle state, awaiting the next command. When is cleared. If not, the bit is set. After the ninth clock, the the buffer is read by the CPU, the BF bit is automati- SSPIF bit is set and the master clock (Baud Rate Gen- cally cleared. The user can then send an Acknowledge erator) is suspended until the next data byte is loaded bit at the end of reception, by setting the Acknowledge into the SSPBUF, leaving SCL low and SDA Sequence Enable bit ACKEN (SSPCON2 register). unchanged (Figure13-15). 13.4.9.1 BF Status Flag After the write to the SSPBUF, each bit of the address will be shifted out on the falling edge of SCL, until all In receive operation, the BF bit is set when an address seven address bits and the R/W bit, are completed. On or data byte is loaded into SSPBUF from SSPSR. It is the falling edge of the eighth clock, the master will de- cleared when the SSPBUF register is read. assert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, 13.4.9.2 SSPOV Status Flag the master will sample the SDA pin to see if the address In receive operation, the SSPOV bit is set when eight was recognized by a slave. The status of the ACK bit is bits are received into the SSPSR and the BF bit is loaded into the ACKSTAT Status bit (SSPCON2 regis- already set from a previous reception. ter). Following the falling edge of the ninth clock trans- mission of the address, the SSPIF is set, the BF bit is 13.4.9.3 WCOL Status Flag cleared and the Baud Rate Generator is turned off, until If the user writes the SSPBUF when a receive is another write to the SSPBUF takes place, holding SCL already in progress (i.e., SSPSR is still shifting in a data low and allowing SDA to float. byte), the WCOL bit is set and the contents of the buffer 13.4.8.1 BF Status Flag are unchanged (the write does not occur). In Transmit mode, the BF bit (SSPSTAT register) is set when the CPU writes to SSPBUF, and is cleared when all eight bits are shifted out. 13.4.8.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buf- fer are unchanged (the write does not occur). WCOL must be cleared in software. DS40001291H-page 194  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 13-15: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A > slave, clear ACKSTAT bit SSPCON2<6 Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1D0 2345678 Cleared in software service routineFrom SSP interrupt SSPBUF is written in software From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to CK re W = 0 A W 9 ware. R/ A1 ss and R/ 78 d by hard ave A2 ddre 6 eare PCON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPBUF written with 7-bit astart transmit 12345 Cleared in software SSPBUF written After Start condition, SEN cl Sn Write SStart co S F SDA SCL SSPI BF SEN PEN R/W  2006-2015 Microchip Technology Inc. DS40001291H-page 195

PIC16F882/883/884/886/887 FIGURE 13-16: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) KEN start Acknowledge sequenceSDA = ACKDT = 1 PEN bit = 1N clearedwritten herematically D0ACK Bus MasterACK is not sentterminatestransfer98PSet SSPIF at endLKof receiveSet SSPIF interruptat end of Acknow-ledge sequence Set P bit (SSPSTAT<4>)Cleared insoftwareand SSPIF SSPOV is set becauseSSPBUF is still full Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACACK from Masterer configured as a receiverSDA = ACKDT = 0ogramming SSPCON2<3>, (RCEN = )1RCEN = startRCE1RCEN clearednext receiveautoautomatically Receiving Data from SlaveReceiving Data from SlaveACKD2D5D2D5D1D3D4D6D7D3D4D6D7D1D0 6789756512343124 Data shifted in on falling edge of C Set SSPIF interruptSet SSPIF interruptat end of receiveat end of Acknowledgesequence Cleared in softwareCleared in softwareCleared in software Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF stpr Maby m Slave W = 1ACK 9 hereACK fro aveR/A1 78 Write to SSPCON2<0>(SEN = )1Begin Start Condition SEN = 0Write to SSPBUF occurs Start XMIT Transmit Address to SlA7A6A5A4A3A2SDA 361245SCLS SSPIF Cleared in softwareSDA = , SCL = 01while CPU responds to SSPIF BF SSPOV ACKEN DS40001291H-page 196  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 13.4.10 ACKNOWLEDGE SEQUENCE TIMING 13.4.11 STOP CONDITION TIMING An Acknowledge sequence is enabled by setting the A Stop bit is asserted on the SDA pin at the end of a Acknowledge Sequence Enable bit, ACKEN (SSPCON2 receive/transmit by setting the Stop Sequence Enable register). When this bit is set, the SCL pin is pulled low bit, PEN (SSPCON2 register). At the end of a receive/ and the contents of the Acknowledge Data bit (ACKDT) transmit, the SCL line is held low after the falling edge is presented on the SDA pin. If the user wishes to gener- of the ninth clock. When the PEN bit is set, the master ate an Acknowledge, then the ACKDT bit should be will assert the SDA line low. When the SDA line is sam- cleared. If not, the user should set the ACKDT bit before pled low, the Baud Rate Generator is reloaded and starting an Acknowledge sequence. The Baud Rate counts down to 0. When the Baud Rate Generator Generator then counts for one rollover period (TBRG) and times out, the SCL pin will be brought high, and one the SCL pin is de-asserted (pulled high). When the SCL TBRG (Baud Rate Generator rollover count) later, the pin is sampled high (clock arbitration), the Baud Rate SDA pin will be de-asserted. When the SDA pin is sam- Generator counts for TBRG. The SCL pin is then pulled pled high while SCL is high, the P bit (SSPSTAT regis- low. Following this, the ACKEN bit is automatically ter) is set. A TBRG later, the PEN bit is cleared and the cleared, the Baud Rate Generator is turned off and the SSPIF bit is set (Figure13-18). MSSP module then goes into Idle mode (Figure13-17). 13.4.11.1 WCOL Status Flag 13.4.10.1 WCOL Status Flag If the user writes the SSPBUF when a Stop sequence If the user writes the SSPBUF when an Acknowledge is in progress, then the WCOL bit is set and the sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does contents of the buffer are unchanged (the write does not not occur). occur). FIGURE 13-17: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared Write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Set SSPIF at the end Cleared in Cleared in of receive software software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period.  2006-2015 Microchip Technology Inc. DS40001291H-page 197

PIC16F882/883/884/886/887 FIGURE 13-18: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2 SCL = 1 for TBRG, followed by SDA = 1 for TBRG Set PEN after SDA sampled high, P bit (SSPSTAT) is set Falling edge of PEN bit (SSPCON2) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. 13.4.12 CLOCK ARBITRATION 13.4.13 SLEEP OPERATION Clock arbitration occurs when the master, during any While in Sleep mode, the I2C module can receive receive, transmit or Repeated Start/Stop condition, de- addresses or data, and when an address match or asserts the SCL pin (SCL allowed to float high). When complete byte transfer occurs, wake the processor the SCL pin is allowed to float high, the Baud Rate Gen- from Sleep (if the MSSP interrupt is enabled). erator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sam- 13.4.14 EFFECT OF A RESET pled high, the Baud Rate Generator is reloaded with A Reset disables the MSSP module and terminates the the contents of SSPADD<6:0> and begins counting. current transfer. This ensures that the SCL high time will always be at least one BRG rollover count, in the event that the clock is held low by an external device (Figure13-19). FIGURE 13-19: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE BRG overflow, Release SCL, If SCL = 1, load BRG with SSPADD<6:0>, and start count BRG overflow occurs, to measure high time interval Release SCL, Slave device holds SCL low SCL = 1, BRG starts counting clock high interval SCL SCL line sampled once every machine cycle (TOSC*4), Hold off BRG until SCL is sampled high SDA TBRG TBRG TBRG DS40001291H-page 198  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 13.4.15 MULTI-MASTER MODE SDA is a ‘1’ and the data sampled on the SDA pin = 0, then a bus collision has taken place. The master will set In Multi-Master mode, the interrupt generation on the the Bus Collision Interrupt Flag (BCLIF) and reset the detection of the Start and Stop conditions allows the I2C port to its Idle state (Figure13-20). determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset, or when the If a transmit was in progress when the bus collision MSSP module is disabled. Control of the I2C bus may occurred, the transmission is halted, the BF bit is be taken when the P bit (SSPSTAT register) is set, or cleared, the SDA and SCL lines are de-asserted, and the bus is idle with both the S and P bits clear. When the SSPBUF can be written to. When the user services the bus is busy, enabling the SSP Interrupt will gener- the bus collision interrupt service routine, and if the I2C bus is free, the user can resume communication by ate the interrupt when the Stop condition occurs. asserting a Start condition. In Multi-Master operation, the SDA line must be moni- tored for arbitration, to see if the signal level is the If a Start, Repeated Start, Stop, or Acknowledge condition was in progress when the bus collision expected output level. This check is performed in hard- ware, with the result placed in the BCLIF bit. occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in Arbitration can be lost in the following states: the SSPCON2 register are cleared. When the user • Address transfer services the bus collision interrupt service routine, and • Data transfer if the I2C bus is free, the user can resume communication by asserting a Start condition. • A Start condition • A Repeated Start condition The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit will be • An Acknowledge condition set. 13.4.16 MULTI -MASTER A write to the SSPBUF will start the transmission of COMMUNICATION, BUS data at the first data bit, regardless of where the trans- COLLISION, AND BUS mitter left off when the bus collision occurred. ARBITRATION In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the Multi-Master mode support is achieved by bus arbitra- determination of when the bus is free. Control of the I2C tion. When the master outputs address/data bits onto bus can be taken when the P bit is set in the SSPSTAT the SDA pin, arbitration takes place when the master register, or the bus is idle and the S and P bits are outputs a ‘1’ on SDA, by letting SDA float high and cleared. another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on FIGURE 13-20: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE SDA line pulled low Sample SDA, Data changes by another source While SCL is high, data does not while SCL = 0 match what is driven by the master, Bus collision has occurred SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF  2006-2015 Microchip Technology Inc. DS40001291H-page 199

PIC16F882/883/884/886/887 13.4.16.1 Bus Collision During a Start while SDA is high, a bus collision occurs, because it is Condition assumed that another master is attempting to drive a data ‘1’ during the Start condition. During a Start condition, a bus collision occurs if: If the SDA pin is sampled low during this count, the a) SDA or SCL are sampled low at the beginning of BRG is reset and the SDA line is asserted early the Start condition (Figure13-21). (Figure13-23). If, however, a ‘1’ is sampled on the SDA b) SCL is sampled low before SDA is asserted low pin, the SDA pin is asserted low at the end of the BRG (Figure13-22). count. The Baud Rate Generator is then reloaded and During a Start condition, both the SDA and the SCL counts down to 0, and during this time, if the SCL pin is pins are monitored, if: sampled as ‘0’, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. the SDA pin is already low, or the SCL pin is already low, Note: The reason that bus collision is not a factor during a Start condition, is that no two bus then: masters can assert a Start condition at the the Start condition is aborted, exact same time. Therefore, one master and the BCLIF flag is set, will always assert SDA before the other. and the MSSP module is reset to its Idle state This condition does not cause a bus (Figure13-21). collision, because the two masters must The Start condition begins with the SDA and SCL pins be allowed to arbitrate the first address de-asserted. When the SDA pin is sampled high, the following the Start condition. If the address Baud Rate Generator is loaded from SSPADD<6:0> is the same, arbitration must be allowed to and counts down to 0. If the SCL pin is sampled low continue into the data portion, Repeated Start or Stop conditions. FIGURE 13-21: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1. SSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software. S SSPIF SSPIF and BCLIF are cleared in software. DS40001291H-page 200  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 13-22: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA SCL Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, Bus collision occurs, set BCLIF SEN SCL =0 before BRG time-out, Bus collision occurs, set BCLIF BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 13-23: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master Reset BRG and assert SDA SCL S SCL pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1 Interrupts cleared Set SSPIF in software  2006-2015 Microchip Technology Inc. DS40001291H-page 201

PIC16F882/883/884/886/887 13.4.16.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e, another Start Condition master is attempting to transmit a data ‘0’, see Figure13-24). If SDA is sampled high, the BRG is During a Repeated Start condition, a bus collision reloaded and begins counting. If SDA goes from high- occurs if: to-low before the BRG times out, no bus collision a) A low level is sampled on SDA when SCL goes occurs because no two masters can assert SDA at from low level to high level. exactly the same time. b) SCL goes low before SDA is asserted low, If SCL goes from high-to-low before the BRG times out indicating that another master is attempting to and SDA has not already been asserted, a bus collision transmit a data ’1’. occurs. In this case, another master is attempting to When the user de-asserts SDA and the pin is allowed transmit a data ‘1’ during the Repeated Start condition to float high, the BRG is loaded with SSPADD<6:0> (Figure13-25). and counts down to 0. The SCL pin is then de-asserted, If at the end of the BRG time-out, both SCL and SDA are and when sampled high, the SDA pin is sampled. still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 13-24: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high, If SDA = 0, set BCLIF and release SDA and SCL RSEN BCLIF Cleared in software S ‘0’ SSPIF ‘0’ FIGURE 13-25: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF Set BCLIF, release SDA and SCL Interrupt cleared in software RSEN S ‘0’ SSPIF DS40001291H-page 202  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 13.4.16.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<6:0> a) After the SDA pin has been de-asserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is de-asserted, SCL is drive a data ‘0’ (Figure13-26). If the SCL pin is sampled low before SDA goes high. sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure13-27). FIGURE 13-26: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 13-27: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’  2006-2015 Microchip Technology Inc. DS40001291H-page 203

PIC16F882/883/884/886/887 13.4.17 SSP MASK REGISTER This register must be initiated prior to setting An SSP Mask (SSPMSK) register is available in I2C SSPM<3:0> bits to select the I2C Slave mode (7-bit or 10-bit address). Slave mode as a mask for the value held in the SSPSR register during an address comparison This register can only be accessed when the appropriate operation. A zero (‘0’) bit in the SSPMSK register has mode is selected by bits (SSPM<3:0> of SSPCON). the effect of making the corresponding bit in the The SSP Mask register is active during: SSPSR register a “don’t care”. • 7-bit Address mode: address compare of A<7:1>. This register is reset to all ‘1’s upon any Reset • 10-bit Address mode: address compare of A<7:0> condition and, therefore, has no effect on standard only. The SSP mask has no effect during the SSP operation until written with a mask value. reception of the first (high) byte of the address. REGISTER 13-4: SSPMSK: SSP MASK REGISTER(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address(2) I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111): 1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match Note1: When SSPCON bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK register. 2: In all other SSP modes, this bit has no effect. DS40001291H-page 204  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 14.0 SPECIAL FEATURES OF THE CPU The PIC16F882/883/884/886/887 devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Oscillator selection • Sleep • Code protection • ID Locations • In-Circuit Serial Programming™ • Low-voltage In-Circuit Serial Programming™ The PIC16F882/883/884/886/887 devices have two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power-up Timer to provide at least a 64ms Reset. With these three functions-on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through: • External Reset • Watchdog Timer Wake-up • An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register14-3).  2006-2015 Microchip Technology Inc. DS40001291H-page 205

PIC16F882/883/884/886/887 14.1 Configuration Bits Note: Address 2007h and 2008h are beyond the The Configuration bits can be programmed (read as user program memory space. It belongs to ‘0’), or left unprogrammed (read as ‘1’) to select various the special configuration memory space device configurations as shown in Register14-1. (2000h-3FFFh), which can be accessed These bits are mapped in program memory location only during programming. See “PIC16F88X 2007h and 2008h, respectively. Memory Programming Specification” (DS41287) for more information. REGISTER DEFINITIONS: CONFIGURATION WORDS REGISTER 14-1: CONFIG1: CONFIGURATION WORD REGISTER 1 DEBUG LVP FCMEN IESO BOREN<1:0> bit 13 bit 8 CPD CP MCLRE PWRTE WDTE FOSC<2:0> bit 7 bit 0 bit 13 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger bit 12 LVP: Low Voltage Programming Enable bit 1 = RB3/PGM pin has PGM function, low voltage programming enabled 0 = RB3 pin is digital I/O, HV on MCLR must be used for programming bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 10 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR disabled bit 7 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 6 CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 5 MCLRE: RE3/MCLR pin function select bit(4) 1 = RE3/MCLR pin function is MCLR 0 = RE3/MCLR pin function is digital input, MCLR internally tied to VDD bit 4 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled and can be enabled by SWDTEN bit of the WDTCON register bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN 110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off. 3: The entire program memory will be erased when the code protection is turned off. 4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. DS40001291H-page 206  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 REGISTER 14-2: CONFIG2: CONFIGURATION WORD REGISTER 2 — — — WRT<1:0> BOR4V bit 13 bit 8 — — — — — — — — bit 7 bit 0 bit 13-11 Unimplemented: Read as ‘1’ bit 10-9 WRT<1:0>: Flash Program Memory Self Write Enable bits PIC16F883/PIC16F884 00 = 0000h to 07FFh write protected, 0800h to 0FFFh may be modified by EECON control 01 = 0000h to 03FFh write protected, 0400h to 0FFFh may be modified by EECON control 10 = 0000h to 00FFh write protected, 0100h to 0FFFh may be modified by EECON control 11 = Write protection off PIC16F886/PIC16F887 00 = 0000h to 0FFFh write protected, 1000h to 1FFFh may be modified by EECON control 01 = 0000h to 07FFh write protected, 0800h to 1FFFh may be modified by EECON control 10 = 0000h to 00FFh write protected, 0100h to 1FFFh may be modified by EECON control 11 = Write protection off PIC16F882 00 = 0000h to 03FFh write protected, 0400h to 07FFh may be modified by EECON control 01 = 0000h to 00FFh write protected, 0100h to 07FFh may be modified by EECON control 11 = Write protection off bit 8 BOR4V: Brown-out Reset Selection bit 0 = Brown-out Reset set to 2.1V 1 = Brown-out Reset set to 4.0V bit 7-0 Unimplemented: Read as ‘1’  2006-2015 Microchip Technology Inc. DS40001291H-page 207

PIC16F882/883/884/886/887 14.2 Reset They are not affected by a WDT Wake-up since this is viewed as the resumption of normal operation. TO and The PIC16F882/883/884/886/887 devices differentiate PD bits are set or cleared differently in different Reset between various kinds of Reset: situations, as indicated in Table14-2. These bits are a) Power-on Reset (POR) used in software to determine the nature of the Reset. b) WDT Reset during normal operation See Table14-5 for a full description of Reset states of all registers. c) WDT Reset during Sleep d) MCLR Reset during normal operation A simplified block diagram of the On-Chip Reset Circuit is shown in Figure14-1. e) MCLR Reset during Sleep f) Brown-out Reset (BOR) The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section17.0 “Electrical Some registers are not affected in any Reset condition; Specifications” for pulse-width specifications. their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on: • Power-on Reset • MCLR Reset • MCLR Reset during Sleep • WDT Reset • Brown-out Reset (BOR) FIGURE 14-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/VPP pin Sleep WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out(1) Reset BOREN SBOREN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1/ CLKI pin PWRT LFINTOSC 11-bit Ripple Counter Enable PWRT Enable OST Note 1: Refer to the Configuration Word Register 1 (Register14-1). DS40001291H-page 208  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 14.2.1 POWER-ON RESET (POR) FIGURE 14-2: RECOMMENDED MCLR CIRCUIT The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. A maximum rise time for VDD is required. See VDD PIC16F886 Section17.0 “Electrical Specifications” for details. If the BOR is enabled, the maximum rise time specification R1 1kor greater) does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section14.2.4 MCLR “Brown-out Reset (BOR)”). Note: The POR circuit does not produce an C1 internal Reset when VDD declines. To 0.1 F (optional, not critical) re-enable the POR, VDD must reach Vss for a minimum of 100s. When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., 14.2.3 POWER-UP TIMER (PWRT) voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the The Power-up Timer provides a fixed 64ms (nominal) device must be held in Reset until the operating time-out on power-up only, from POR or Brown-out conditions are met. Reset. The Power-up Timer operates from the 31kHz LFINTOSC oscillator. For more information, see For additional information, refer to Application Note Section4.5 “Internal Clock Modes”. The chip is kept AN607, “Power-up Trouble Shooting” (DS00607). in Reset as long as PWRT is active. The PWRT delay 14.2.2 MCLR allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable PIC16F882/883/884/886/887 have a noise filter in the (if cleared or programmed) the Power-up Timer. The MCLR Reset path. The filter will detect and ignore Power-up Timer should be enabled when Brown-out small pulses. Reset is enabled, although it is not required. It should be noted that a WDT Reset does not drive The Power-up Timer delay will vary from chip-to-chip MCLR pin low. and vary due to: The behavior of the ESD protection on the MCLR pin • VDD variation has been altered from early devices of this family. • Temperature variation Voltages applied to the pin that exceed its specification • Process variation can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. See DC parameters for details (Section17.0 “Electrical For this reason, Microchip recommends that the MCLR Specifications”). pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure14-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word Register 1. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RA3/MCLR pin becomes an external Reset input. In this mode, the RA3/MCLR pin has a weak pull-up to VDD.  2006-2015 Microchip Technology Inc. DS40001291H-page 209

PIC16F882/883/884/886/887 14.2.4 BROWN-OUT RESET (BOR) On any Reset (Power-on, Brown-out Reset, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises The BOREN0 and BOREN1 bits in the Configuration above VBOR (see Figure14-3). The Power-up Timer Word Register 1 select one of four BOR modes. Two will now be invoked, if enabled and will keep the chip in modes have been added to allow software or hardware Reset an additional 64ms. control of the BOR enable. When BOREN<1:0>=01, the SBOREN bit (PCON<4>) enables/disables the Note: The Power-up Timer is enabled by the BOR allowing it to be controlled in software. By PWRTE bit in the Configuration Word selecting BOREN<1:0>, the BOR is automatically Register 1. disabled in Sleep to conserve power and enabled on wake-up. In this mode, the SBOREN bit is disabled. If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset See Register14-3 for the Configuration Word definition. and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a The BOR4V bit in the Configuration Word Register 2 64ms Reset. selects one of two Brown-out Reset voltages. When BOR4B = 1, VBOR is set to 4V. When BOR4V = 0, VBOR is set to 2.1V. If VDD falls below VBOR for greater than parameter (TBOR) (see Section17.0 “Electrical Specifications”), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not insured to occur if VDD falls below VBOR for less than parameter (TBOR). FIGURE 14-3: BROWN-OUT SITUATIONS VDD VBOR Internal Reset 64 ms(1) VDD VBOR Internal < 64 ms Reset 64 ms(1) VDD VBOR Internal Reset 64 ms(1) Note 1: 64ms delay only if PWRTE bit is programmed to ‘0’. DS40001291H-page 210  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 14.2.5 TIME-OUT SEQUENCE 14.2.6 POWER CONTROL (PCON) REGISTER On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then The Power Control register PCON (address 8Eh) has OST is activated after the PWRT time-out has expired. two Status bits to indicate what type of Reset that last The total time-out will vary based on oscillator occurred. configuration and PWRTE bit status. For example, in Bit0 is BOR (Brown-out Reset). BOR is unknown on EC mode with PWRTE bit erased (PWRT disabled), Power-on Reset. It must then be set by the user and there will be no time-out at all. Figures14-4,14-5 checked on subsequent Resets to see if BOR = 0, and14-6 depict time-out sequences. The device can indicating that a brown-out has occurred. The BOR execute code from the INTOSC while OST is active by Status bit is a “don’t care” and is not necessarily enabling Two-Speed Start-up or Fail-Safe Monitor (see predictable if the brown-out circuit is disabled Section4.7.2 “Two-Speed Start-up Sequence” and (BOREN<1:0> =00 in the Configuration Word Section4.8 “Fail-Safe Clock Monitor”). Register 1). Since the time-outs occur from the POR pulse, if MCLR Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on is kept low long enough, the time-outs will expire. Then, Reset and unaffected otherwise. The user must write a bringing MCLR high will begin execution immediately ‘1’ to this bit following a Power-on Reset. On a (see Figure14-5). This is useful for testing purposes or subsequent Reset, if POR is ‘0’, it will indicate that a to synchronize more than one Power-on Reset has occurred (i.e., VDD may have PIC16F882/883/884/886/887 device operating in par- gone too low). allel. For more information, see Section3.2.2 “Ultra Table14-5 shows the Reset conditions for some Low-Power Wake-up” and Section14.2.4 special registers, while Table14-4 shows the Reset “Brown-out Reset (BOR)”. conditions for all the registers. TABLE 14-1: TIME-OUT IN VARIOUS SITUATIONS Power-up Brown-out Reset Wake-up from Oscillator Configuration Sleep PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 XT, HS, LP TPWRT + 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC 1024 • TOSC 1024 • TOSC LP, T1OSCIN = 1 TPWRT — TPWRT — — RC, EC, INTOSC TPWRT — TPWRT — — TABLE 14-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 x 1 1 Power-on Reset u 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown TABLE 14-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page PCON — — ULPWUE SBOREN — — POR BOR 37 STATUS IRP RP1 RPO TO PD Z DC C 30 Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.  2006-2015 Microchip Technology Inc. DS40001291H-page 211

PIC16F882/883/884/886/887 FIGURE 14-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 14-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS40001291H-page 212  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER Wake-up from Sleep through MCLR Reset Power-on Interrupt Register Address WDT Reset Reset Wake-up from Sleep through Brown-out Reset(1) WDT Time-out W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/10 xxxx xxxx xxxx xxxx uuuu uuuu 0h/180h TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/10 0000 0000 0000 0000 PC + 1(3) 2h/182h STATUS 03h/83h/10 0001 1xxx 000q quuu(4) uuuq quuu(4) 3h/183h FSR 04h/84h/10 xxxx xxxx uuuu uuuu uuuu uuuu 4h/184h PORTA 05h xxxx xxxx 0000 0000 uuuu uuuu PORTB 06h/106h xxxx xxxx 0000 0000 uuuu uuuu PORTC 07h xxxx xxxx 0000 0000 uuuu uuuu PORTD 08h xxxx xxxx 0000 0000 uuuu uuuu PORTE 09h ---- xxxx ---- 0000 ---- uuuu PCLATH 0Ah/8Ah/10 ---0 0000 ---0 0000 ---u uuuu Ah/18Ah INTCON 0Bh/8Bh/10 0000 000x 0000 000u uuuu uuuu(2) Bh/18Bh PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2) PIR2 0Dh 0000 0000 0000 0000 uuuu uuuu(2) TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu TMR2 11h 0000 0000 0000 0000 uuuu uuuu T2CON 12h -000 0000 -000 0000 -uuu uuuu SSPBUF 13h xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 14h 0000 0000 0000 0000 uuuu uuuu CCPR1L 15h xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 16h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 17h 0000 0000 0000 0000 uuuu uuuu RCSTA 18h 0000 000x 0000 0000 uuuu uuuu TXREG 19h 0000 0000 0000 0000 uuuu uuuu RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu CCPR2L 1Bh xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table14-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. 6: Accessible only when SSPCON register bits SSPM<3:0> = 1001.  2006-2015 Microchip Technology Inc. DS40001291H-page 213

PIC16F882/883/884/886/887 TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER (CONTINUED) Wake-up from Sleep through MCLR Reset Power-on Interrupt Register Address WDT Reset (Continued) Reset Wake-up from Sleep through Brown-out Reset(1) WDT Time-out (Continued) CCPR2H 1Ch xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 1Dh --00 0000 --00 0000 --uu uuuu ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1Fh 00-0 0000 00-0 0000 uu-u uuuu OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu TRISA 85h 1111 1111 1111 1111 uuuu uuuu TRISB 86h/186h 1111 1111 1111 1111 uuuu uuuu TRISC 87h 1111 1111 1111 1111 uuuu uuuu TRISD 88h 1111 1111 1111 1111 uuuu uuuu TRISE 89h ---- 1111 ---- 1111 ---- uuuu PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu PIE2 8Dh 0000 0000 0000 0000 uuuu uuuu PCON 8Eh --01 --0x --0u --uu(1, 5) --uu --uu OSCCON 8Fh -110 q000 -110 q000 -uuu uuuu OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu SSPCON2 91h 0000 0000 0000 0000 uuuu uuuu PR2 92h 1111 1111 1111 1111 1111 1111 SSPADD(6) 93h 0000 0000 0000 0000 uuuu uuuu SSPMSK(6) 93h 1111 1111 1111 1111 1111 1111 SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu WPUB 95h 1111 1111 1111 1111 uuuu uuuu IOCB 96h 0000 0000 0000 0000 uuuu uuuu VRCON 97h 0000 0000 0000 0000 uuuu uuuu TXSTA 98h 0000 -010 0000 -010 uuuu -uuu SPBRG 99h 0000 0000 0000 0000 uuuu uuuu SPBRGH 9Ah 0000 0000 0000 0000 uuuu uuuu PWM1CON 9Bh 0000 0000 0000 0000 uuuu uuuu ECCPAS 9Ch 0000 0000 0000 0000 uuuu uuuu PSTRCON 9Dh ---0 0001 ---0 0001 ---u uuuu ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 9Fh 0-00 ---- 0-00 ---- u-uu ---- WDTCON 105h ---0 1000 ---0 1000 ---u uuuu CM1CON0 107h 0000 0-00 0000 0-00 uuuu u-uu CM2CON0 108h 0000 0-00 0000 0-00 uuuu u-uu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table14-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. 6: Accessible only when SSPCON register bits SSPM<3:0> = 1001. DS40001291H-page 214  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER (CONTINUED) Wake-up from Sleep through MCLR Reset Power-on Interrupt Register Address WDT Reset (Continued) Reset Wake-up from Sleep through Brown-out Reset(1) WDT Time-out (Continued) CM2CON1 109h 0000 0--0 0000 0--0 uuuu u--u EEDAT 10Ch 0000 0000 0000 0000 uuuu uuuu EEADR 10Dh 0000 0000 0000 0000 uuuu uuuu EEDATH 10Eh --00 0000 --00 0000 --uu uuuu EEADRH 10Fh ---0 0000 ---0 0000 ---u uuuu SRCON 185h 0000 00-0 0000 00-0 uuuu uu-u BAUDCTL 187h 01-0 0-00 01-0 0-00 uu-u u-uu ANSEL 188h 1111 1111 1111 1111 uuuu uuuu ANSELH 189h 1111 1111 1111 1111 uuuu uuuu EECON1 18Ch ---- x000 ---- q000 ---- uuuu EECON2 18Dh ---- ---- ---- ---- ---- ---- Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table14-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. 6: Accessible only when SSPCON register bits SSPM<3:0> = 1001. TABLE 14-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Status PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx --01 --0x MCLR Reset during normal operation 000h 000u uuuu --0u --uu MCLR Reset during Sleep 000h 0001 0uuu --0u --uu WDT Reset 000h 0000 uuuu --0u --uu WDT Wake-up PC + 1 uuu0 0uuu --uu --uu Brown-out Reset 000h 0001 1uuu --01 --u0 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu --uu --uu Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.  2006-2015 Microchip Technology Inc. DS40001291H-page 215

PIC16F882/883/884/886/887 14.3 Interrupts The following interrupt flags are contained in the PIR2 register: The PIC16F882/883/884/886/887 devices have • Fail-Safe Clock Monitor Interrupt multiple interrupt sources: • 2 Comparator Interrupts • External Interrupt RB0/INT • EEPROM Data Write Interrupt • Timer0 Overflow Interrupt • Ultra Low-Power Wake-up Interrupt • PORTB Change Interrupts • CCP2 Interrupt • 2 Comparator Interrupts When an interrupt is serviced: • A/D Interrupt • Timer1 Overflow Interrupt • The GIE is cleared to disable any further interrupt. • Timer2 Match Interrupt • The return address is pushed onto the stack. • EEPROM Data Write Interrupt • The PC is loaded with 0004h. • Fail-Safe Clock Monitor Interrupt For external interrupt events, such as the INT pin, • Enhanced CCP Interrupt PORTB change interrupts, the interrupt latency will be three or four instruction cycles. The exact latency • EUSART Receive and Transmit Interrupts depends upon when the interrupt event occurs (see • Ultra Low-Power Wake-up Interrupt Figure14-8). The latency is the same for one or • MSSP Interrupt two-cycle instructions. Once in the Interrupt Service The Interrupt Control register (INTCON) and Peripheral Routine, the source(s) of the interrupt can be Interrupt Request Register 1 (PIR1) record individual determined by polling the interrupt flag bits. The interrupt requests in flag bits. The INTCON register interrupt flag bit(s) must be cleared in software before also has individual and global interrupt enable bits. re-enabling interrupts to avoid multiple interrupt requests. A Global Interrupt Enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts, or disables (if Note1: Individual interrupt flag bits are set, cleared) all interrupts. Individual interrupts can be regardless of the status of their disabled through their corresponding enable bits in the corresponding mask bit or the GIE bit. INTCON, PIE1 and PIE2 registers, respectively. GIE is 2: When an instruction that clears the GIE cleared on Reset. bit is executed, any interrupts that were The Return from Interrupt instruction, RETFIE, exits pending for execution in the next cycle the interrupt routine, as well as sets the GIE bit, which are ignored. The interrupts, which were re-enables unmasked interrupts. ignored, are still pending to be serviced The following interrupt flags are contained in the when the GIE bit is set again. INTCON register: For additional information on Timer1, Timer2, • INT Pin Interrupt comparators, A/D, data EEPROM, EUSART, MSSP or • PORTB Change Interrupts Enhanced CCP modules, refer to the respective peripheral section. • Timer0 Overflow Interrupt The peripheral interrupt flags are contained in the PIR1 14.3.1 RB0/INT INTERRUPT and PIR2 registers. The corresponding interrupt enable External interrupt on RB0/INT pin is edge-triggered; bits are contained in PIE1 and PIE2 registers. either rising if the INTEDG bit (OPTION_REG<6>) is The following interrupt flags are contained in the PIR1 set, or falling, if the INTEDG bit is clear. When a valid register: edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by • A/D Interrupt clearing the INTE control bit (INTCON<4>). The INTF • EUSART Receive and Transmit Interrupts bit must be cleared in software in the Interrupt Service • Timer1 Overflow Interrupt Routine before re-enabling this interrupt. The RB0/INT • Synchronous Serial Port (SSP) Interrupt interrupt can wake-up the processor from Sleep, if the • Enhanced CCP1 Interrupt INTE bit was set prior to going into Sleep. The status of • Timer1 Overflow Interrupt the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up • Timer2 Match Interrupt (0004h). See Section14.6 “Power-Down Mode (Sleep)” for details on Sleep and Figure14-10 for timing of wake-up from Sleep through RB0/INT interrupt. DS40001291H-page 216  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 14.3.2 TIMER0 INTERRUPT 14.3.3 PORTB INTERRUPT An overflow (FFh  00h) in the TMR0 register will set An input change on PORTB change sets the RBIF the T0IF (INTCON<2>) bit. The interrupt can be (INTCON<0>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) enabled/disabled by setting/clearing the RBIE bit. See Section5.0 “Timer0 Module” for operation of (INTCON<3>) bit. Plus, individual pins can be the Timer0 module. configured through the IOCB register. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. See Section3.4.3 “Interrupt-on-Change” for more information. FIGURE 14-7: INTERRUPT LOGIC IOC-RB0 IOCB0 IOC-RB1 IOCB1 IOC-RB2 BCLIF IOCB2 BCLIE IOC-RB3 SSPIF IOCB3 SSPIE IOC-RB4 TXIF IOCB4 TXIE IOC-RB5 RCIF IOCB5 RCIE Wake-up (If in Sleep mode)(1) T0IF IOC-RB6 TMR2IF T0IE Interrupt to CPU IOCB6 TMR2IE INTF INTE IOC-RB7 TMR1IF RBIF IOCB7 TMR1IE RBIE C1IF C1IE PEIE C2IF GIE C2IE ADIF ADIE EEIF EEIE Note 1: Some peripherals depend upon the OSFIF system clock for operation. Since the OSFIE system clock is suspended during Sleep, these peripherals will not wake CCP1IF the part from Sleep. See Section14.6.1 CCP1IE “Wake-up from Sleep”. CCP2IF CCP2IE ULPWUIF ULPWUIE  2006-2015 Microchip Technology Inc. DS40001291H-page 217

PIC16F882/883/884/886/887 FIGURE 14-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 (3) CLKOUT (4) INT pin (1) (1) (2) INTF flag (5) Interrupt Latency (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section17.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. TABLE 14-6: SUMMARY OF INTERRUPT REGISTERS Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 32 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 33 PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 34 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 35 PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 36 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the interrupt module. DS40001291H-page 218  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 14.4 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Since the upper 16 bytes of all GPR banks are common in the PIC16F882/883/884/886/887 (see Figures2-2 and 2-3), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, make it easier to context save and restore. The same code shown in Example14-1 can be used to: • Store the W register • Store the STATUS register • Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register Note: The PIC16F882/883/884/886/887 devices normally do not require saving the PCLATH. However, if computed GOTOs are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR. EXAMPLE 14-1: SAVING STATUS AND W REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W ;Swaps are used because they do not affect the status bits MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W  2006-2015 Microchip Technology Inc. DS40001291H-page 219

PIC16F882/883/884/886/887 14.5 Watchdog Timer (WDT) 14.5.2 WDT CONTROL The WDT has the following features: The WDTE bit is located in the Configuration Word Register 1. When set, the WDT runs continuously. • Operates from the LFINTOSC (31 kHz) When the WDTE bit in the Configuration Word • Contains a 16-bit prescaler Register1 is set, the SWDTEN bit of the WDTCON • Shares an 8-bit prescaler with Timer0 register has no effect. If WDTE is clear, then the • Time-out period is from 1 ms to 268 seconds SWDTEN bit can be used to enable and disable the • Configuration bit and software controlled WDT. Setting the bit will enable it and clearing the bit will disable it. WDT is cleared under certain conditions described in Table14-7. The PSA and PS<2:0> bits of the OPTION register have the same function as in previous versions of the 14.5.1 WDT OSCILLATOR PIC16F882/883/884/886/887 family of microcontrol- The WDT derives its time base from the 31kHz lers. See Section5.0 “Timer0 Module” for more LFINTOSC. The LTS bit of the OSCCON register does information. not reflect that the LFINTOSC is enabled. The value of WDTCON is ‘---0 1000’ on all Resets. This gives a nominal time base of 17ms. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled). FIGURE 14-9: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source 0 Prescaler(1) 16-bit WDT Prescaler 1 8 PSA PS<2:0> 31kHz WDTPS<3:0> LFINTOSC Clock 0 1 PSA WDTE from the Configuration Word Register 1 SWDTEN from WDTCON WDT Time-out Note 1: This is the shared Timer0/WDT prescaler. See Section5.1.3 “Software Programmable Prescaler” for more information. TABLE 14-7: WDT STATUS Conditions WDT WDTE = 0 Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST DS40001291H-page 220  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 REGISTER 14-3: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note1: If WDTE Configuration bit=1, then WDT is always enabled, irrespective of this control bit. If WDTE Configuration bit=0, then it is possible to turn WDT on/off with this control bit. TABLE 14-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 31 WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN 221 Legend: Shaded cells are not used by the Watchdog Timer. TABLE 14-9: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH WATCHDOG TIMER Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page CONFIG1(1) 13:8 — — DEBUG LVP FCMEN IESO BOREN 1 BOREN0 206 7:0 CPD CP MCLRE PWRTE WDTE FOSC 2 FOSC 1 FOSC 0 Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by the Watchdog Timer. Note 1: See Configuration Word Register 1 (Register14-1) for operation of all register bits.  2006-2015 Microchip Technology Inc. DS40001291H-page 221

PIC16F882/883/884/886/887 14.6 Power-Down Mode (Sleep) When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to The Power-Down mode is entered by executing a wake-up through an interrupt event, the corresponding SLEEP instruction. interrupt enable bit must be set (enabled). Wake-up If the Watchdog Timer is enabled: occurs regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at • WDT will be cleared but keeps running. the instruction after the SLEEP instruction. If the GIE bit • PD bit in the STATUS register is cleared. is set (enabled), the device executes the instruction • TO bit is set. after the SLEEP instruction, then branches to the inter- • Oscillator driver is turned off. rupt address (0004h). In cases where the execution of • I/O ports maintain the status they had before the instruction following SLEEP is not desirable, the SLEEP was executed (driving high, low or user should have a NOP after the SLEEP instruction. high-impedance). Note: If the global interrupts are disabled (GIE is For lowest current consumption in this mode, all I/O pins cleared), but any interrupt source has both should be either at VDD or VSS, with no external circuitry its interrupt enable bit and the drawing current from the I/O pin and the comparators corresponding interrupt flag bits set, the and CVREF should be disabled. I/O pins that are device will immediately wake-up from high-impedance inputs should be pulled high or low Sleep. The SLEEP instruction is completely externally to avoid switching currents caused by floating executed. inputs. The T0CKI input should also be at VDD or VSS for The WDT is cleared when the device wakes up from lowest current consumption. The contribution from Sleep, regardless of the source of wake-up. on-chip pull-ups on PORTA should be considered. The MCLR pin must be at a logic high level. 14.6.2 WAKE-UP USING INTERRUPTS Note: It should be noted that a Reset generated When global interrupts are disabled (GIE cleared) and by a WDT time-out does not drive MCLR any interrupt source has both its interrupt enable bit pin low. and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a 14.6.1 WAKE-UP FROM SLEEP SLEEP instruction, the SLEEP instruction will The device can wake-up from Sleep through one of the complete as a NOP. Therefore, the WDT and WDT following events: prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit 1. External Reset input on MCLR pin. will not be cleared. 2. Watchdog Timer Wake-up (if WDT was enabled). • If the interrupt occurs during or after the execu- 3. Interrupt from RB0/INT pin, PORTB change or a tion of a SLEEP instruction, the device will imme- peripheral interrupt. diately wake-up from Sleep. The SLEEP The first event will cause a device Reset. The two latter instruction will be completely executed before the events are considered a continuation of program exe- wake-up. Therefore, the WDT and WDT prescaler cution. The TO and PD bits in the STATUS register can and postscaler (if enabled) will be cleared, the TO be used to determine the cause of device Reset. The bit will be set and the PD bit will be cleared. PD bit, which is set on power-up, is cleared when Sleep Even if the flag bits were checked before executing a is invoked. TO bit is cleared if WDT Wake-up occurred. SLEEP instruction, it may be possible for flag bits to The following peripheral interrupts can wake the device become set before the SLEEP instruction completes. To from Sleep: determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction 1. TMR1 interrupt. Timer1 must be operating as an was executed as a NOP. asynchronous counter. 2. ECCP Capture mode interrupt. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. 3. A/D conversion (when A/D clock source is FRC). 4. EEPROM write operation completion. 5. Comparator output changes state. 6. Interrupt-on-change. 7. External Interrupt from INT pin. 8. EUSART Break detect, I2C slave. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. DS40001291H-page 222  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 14-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency(3) GIE bit Processor in (INTCON<7>) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC – 1) Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. 3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. 4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference. 14.7 Code Protection 14.9 In-Circuit Serial Programming™ If the code protection bit(s) have not been The PIC16F882/883/884/886/887 microcontrollers can programmed, the on-chip program memory can be be serially programmed while in the end application read out using ICSP™ for verification purposes. circuit. This is simply done with two lines for clock and data and three other lines for: Note: The entire data EEPROM and Flash program memory will be erased when the • power code protection is switched from on to off. • ground See the “PIC16F88X Memory • programming voltage Programming Specification” (DS41287) for This allows customers to manufacture boards with more information. unprogrammed devices and then program the micro- controller just before shipping the product. This also 14.8 ID Locations allows the most recent firmware or a custom firmware to be programmed. Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or The device is placed into a Program/Verify mode by other code identification numbers. These locations are holding the RB6/ICSPCLK and RB7/ICSPDAT pins low, not accessible during normal execution but are readable while raising the MCLR (VPP) pin from VIL to VIHH. See and writable during Program/Verify mode. Only the the “PIC16F88X Memory Programming Specification” Least Significant seven bits of the ID locations are used. (DS41287) for more information. RB7 becomes the programming data and RB6 becomes the programming clock. Both RB7 and RB6 are Schmitt Trigger inputs in this mode. After Reset, to place the device into Program/Verify mode, the Program Counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a Load or a Read. For complete details of serial programming, please refer to the “PIC16F88X Memory Programming Specification” (DS41287). A typical In-Circuit Serial Programming connection is shown in Figure14-11.  2006-2015 Microchip Technology Inc. DS40001291H-page 223

PIC16F882/883/884/886/887 FIGURE 14-11: TYPICAL IN-CIRCUIT 14.10 Low-Voltage (Single-Supply) ICSP SERIAL Programming PROGRAMMING™ The LVP bit of the Configuration Word enables CONNECTION low-voltage ICSP programming. This mode allows the microcontroller to be programmed via ICSP using a To Normal Connections VDD source in the operating voltage range. This only External means that VPP does not have to be brought to VIHH but Connector * PIC16F882/883/ can instead be left at the normal operating voltage. In Signals 884/886/887 this mode, the RB3/PGM pin is dedicated to the programming function and ceases to be a general +5V VDD purpose I/O pin. During programming, VDD is applied to 0V VSS the MCLR pin. To enter Programming mode, VDD must VPP RE3/MCLR/VPP be applied to the RB3/PGM provided the LVP bit is set. CLK RB6 The LVP bit defaults to on (‘1’) from the factory. Data I/O RB7 Note1: The High-Voltage Programming mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. 2: While in Low-Voltage ICSP mode, the * * * RB3 pin can no longer be used as a general purpose I/O pin. To Normal 3: When using Low-Voltage ICSP Program- Connections ming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register * Isolation devices (as required) must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device. 4: RB3 should not be allowed to float if LVP is enabled. An external pull-down device should be used to default the device to normal operating mode. If RB3 floats high, the PIC16F882/883/884/886/887 devices will enter Programming mode. 5: LVP mode is enabled by default on all devices shipped from Microchip. It can be disabled by clearing the LVP bit in the CONFIG register. If Low-Voltage Programming mode is not used, the LVP bit can be programmed to a ‘0’ and RB3/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed when programming is entered with VIHH on MCLR. The LVP bit can only be charged when using high voltage on MCLR. It should be noted, that once the LVP bit is programmed to ‘0’, only the High-Voltage Programming mode is available and only High-Voltage Programming mode can be used to program the device. When using low-voltage ICSP, the part must be supplied at 4.5V to 5.5V if a bulk erase will be executed. This includes reprogramming of the code-protect bits from an on state to an off state. For all other cases of low-voltage ICSP, the part may be programmed at the normal operating voltage. This means calibration values, unique user IDs or user code can be reprogrammed or added. DS40001291H-page 224  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 14.11 In-Circuit Debugger For more information, see “Using MPLAB® ICD 2” (DS51265), available on Microchip’s web site The PIC16F882/883/884/886/887-ICD can be used in (www.microchip.com). any of the package types. The devices will be mounted on the target application board, which in turn has a 3 or 14.11.1 ICD PINOUT 4-wire connection to the ICD tool. The devices in the MemHigh family carry the circuitry When the debug bit in the Configuration Word for the In-Circuit Debugger on-chip and on existing (CONFIG<13>) is programmed to a ‘0’, the In-Circuit device pins. This eliminates the need for a separate Debugger functionality is enabled. This function allows die or package for the ICD device. The pinout for the simple debugging functions when used with MPLAB® ICD device is the same as the devices (see ICD 2. When the microcontroller has this feature Section1.0 “Device Overview” for complete pinout enabled, some of the resources are not available for and pin descriptions). Table14-10 shows the location general use. See Table14-10 for more detail. and function of the ICD related pins on the 28 and 40 pin devices. Note: The user’s application must have the circuitry required to support ICD functionality. Once the ICD circuitry is enabled, normal device pin functions on RB6/ICSPCLK and RB7/ICSPDAT will not be usable. The ICD circuitry uses these pins for communication with the ICD2 external debugger. TABLE 14-10: PIC16F883/884/886/887-ICD PIN DESCRIPTIONS Pin (PDIP) Name Type Pull-up Description PIC16F884/887 PIC16F882/883/886 40 28 ICDDATA TTL — In-Circuit Debugger Bidirectional data 39 27 ICDCLK ST — In-Circuit Debugger Bidirectional clock 1 1 MCLR/VPP HV — Programming voltage 11,32 20 VDD P — 12,31 8,19 VSS P — Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, P = Power, HV = High Voltage  2006-2015 Microchip Technology Inc. DS40001291H-page 225

PIC16F882/883/884/886/887 15.0 INSTRUCTION SET SUMMARY TABLE 15-1: OPCODE FIELD DESCRIPTIONS The PIC16F882/883/884/886/887 instruction set is highly orthogonal and is comprised of three basic Field Description categories: f Register file address (0x00 to 0x7F) • Byte-oriented operations W Working register (accumulator) • Bit-oriented operations b Bit address within an 8-bit file register • Literal and control operations k Literal field, constant data or label Each PIC16 instruction is a 14-bit word divided into an x Don’t care location (= 0 or 1). opcode, which specifies the instruction type and one or The assembler will generate code with x = 0. more operands, which further specify the operation of It is the recommended form of use for the instruction. The formats for each of the categories compatibility with all Microchip software tools. is presented in Figure15-1, while the various opcode d Destination select; d = 0: store result in W, fields are summarized in Table15-1. d = 1: store result in file register f. Table15-2 lists the instructions recognized by the Default is d = 1. MPASMTM assembler. PC Program Counter For byte-oriented instructions, ‘f’ represents a file TO Time-out bit register designator and ‘d’ represents a destination C Carry bit designator. The file register designator specifies which file register is to be used by the instruction. DC Digit carry bit The destination designator specifies where the result of Z Zero bit the operation is to be placed. If ‘d’ is zero, the result is PD Power-down bit placed in the W register. If ‘d’ is one, the result is placed in the file register specified in the instruction. FIGURE 15-1: GENERAL FORMAT FOR For bit-oriented instructions, ‘b’ represents a bit field INSTRUCTIONS designator, which selects the bit affected by the operation, while ‘f’ represents the address of the file in Byte-oriented file register operations which the bit is located. 13 8 7 6 0 OPCODE d f (FILE #) For literal and control operations, ‘k’ represents an 8-bit or 11-bit constant, or literal value. d = 0 for destination W d = 1 for destination f One instruction cycle consists of four oscillator periods; f = 7-bit file register address for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1s. All instructions are Bit-oriented file register operations executed within a single instruction cycle, unless a 13 10 9 7 6 0 conditional test is true, or the program counter is OPCODE b (BIT #) f (FILE #) changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the b = 3-bit bit address second cycle executed as a NOP. f = 7-bit file register address All instruction examples use the format ‘0xhh’ to Literal and control operations represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. General 13 8 7 0 15.1 Read-Modify-Write Operations OPCODE k (literal) Any instruction that specifies a file register as part of k = 8-bit immediate value the instruction performs a Read-Modify-Write (RMW) operation. The register is read, the data is modified, CALL and GOTO instructions only and the result is stored according to either the instruc- 13 11 10 0 tion, or the destination designator ‘d’. A read operation OPCODE k (literal) is performed on a register even if the instruction writes to that register. k = 11-bit immediate value For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag. DS40001291H-page 226  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 15-2: PIC16F882/883/884/886/887 INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP – No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call Subroutine 2 10 0kkk kkkk kkkk CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE – Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.  2006-2015 Microchip Technology Inc. DS40001291H-page 227

PIC16F882/883/884/886/887 15.2 Instruction Descriptions ADDLW Add literal and W BCF Bit Clear f Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b Operands: 0  k  255 Operands: 0  f  127 0  b  7 Operation: (W) + k  (W) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: The contents of the W register are added to the 8-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared. and the result is placed in the W register. ADDWF Add W and f BSF Bit Set f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b Operands: 0  f  127 Operands: 0  f  127 d 0,1 0  b  7 Operation: (W) + (f)  (destination) Operation: 1  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set. with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSC f,b Operands: 0  k  255 Operands: 0  f  127 0  b  7 Operation: (W) .AND. (k)  (W) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: The contents of W register are AND’ed with the 8-bit literal ‘k’. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next The result is placed in the W reg- instruction is executed. ister. If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. ANDWF AND W with f Syntax: [ label ] ANDWF f,d Operands: 0  f  127 d 0,1 Operation: (W) .AND. (f)  (destination) Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001291H-page 228  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0  f  127 Operands: None 0  b < 7 Operation: 00h  WDT Operation: skip if (f<b>) = 1 0  WDT prescaler, 1  TO Status Affected: None 1  PD Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Status Affected: TO, PD instruction is executed. If bit ‘b’ is ‘1’, then the next Description: CLRWDT instruction resets the instruction is discarded and a NOP Watchdog Timer. It also resets is executed instead, making this a the prescaler of the WDT. 2-cycle instruction. Status bits TO and PD are set. CALL Call Subroutine COMF Complement f Syntax: [ label ] CALL k Syntax: [ label ] COMF f,d Operands: 0  k  2047 Operands: 0  f  127 Operation: (PC)+ 1 TOS, d  [0,1] k  PC<10:0>, Operation: (f)  (destination) (PCLATH<4:3>)  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are Description: Call Subroutine. First, return complemented. If ‘d’ is ‘0’, the address (PC + 1) is pushed onto result is stored in W. If ‘d’ is ‘1’, the stack. The 11-bit immediate the result is stored back in address is loaded into PC bits register ‘f’. <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a 2-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Decrement register ‘f’. If ‘d’ is ‘0’, cleared and the Z bit is set. the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h  (W) 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set.  2006-2015 Microchip Technology Inc. DS40001291H-page 229

PIC16F882/883/884/886/887 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. If the result is ‘1’, the next If the result is ‘1’, the next instruction is executed. If the instruction is executed. If the result is ‘0’, then a NOP is result is ‘0’, a NOP is executed executed instead, making it a instead, making it a 2-cycle 2-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<4:3>  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the 8-bit literal ‘k’. The The 11-bit immediate value is result is placed in the W register. loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. IORWF Inclusive OR W with f INCF Increment f Syntax: [ label ] IORWF f,d Syntax: [ label ] INCF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (W) .OR. (f)  (destination) Operation: (f) + 1  (destination) Status Affected: Z Status Affected: Z Description: Inclusive OR the W register with Description: The contents of register ‘f’ are register ‘f’. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. DS40001291H-page 230  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 MOVF Move f MOVWF Move W to f Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: (W)  (f) Operation: (f)  (dest) Status Affected: None Status Affected: Z Description: Move data from W register to Description: The contents of register ‘f’ is register ‘f’. moved to a destination dependent Words: 1 upon the status of ‘d’. If d = 0, Cycles: 1 destination is W register. If d = 1, the destination is file register ‘f’ Example: MOVW OPTION itself. d = 1 is useful to test a file F register since status flag Z is Before Instruction affected. OPTION= 0xFF Words: 1 W = 0x4F After Instruction Cycles: 1 OPTION= 0x4F Example: MOVF FSR, 0 W = 0x4F After Instruction W = value in FSR register Z = 1 MOVLW Move literal to W NOP No Operation Syntax: [ label ] MOVLW k Syntax: [ label ] NOP Operands: 0  k  255 Operands: None Operation: k  (W) Operation: No operation Status Affected: None Status Affected: None Description: The 8-bit literal ‘k’ is loaded into W Description: No operation. register. The “don’t cares” will Words: 1 assemble as ‘0’s. Cycles: 1 Words: 1 Example: NOP Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A  2006-2015 Microchip Technology Inc. DS40001291H-page 231

PIC16F882/883/884/886/887 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k Operands: None Operands: 0  k  255 Operation: TOS  PC, Operation: k  (W); 1  GIE TOS  PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is Description: The W register is loaded with the POPed and Top-of-Stack (TOS) 8-bit literal ‘k’. The program is loaded in the PC. Interrupts are counter is loaded from the top of enabled by setting Global the stack (the return address). Interrupt Enable bit, GIE This is a 2-cycle instruction. (INTCON<7>). This is a 2-cycle Words: 1 instruction. Cycles: 2 Words: 1 Example: CALL TABLE;W contains Cycles: 2 table Example: RETFIE ;offset value TABLE • ;W now has After Interrupt • ;table value PC = TOS • GIE= 1 • ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ;End of table Before Instruction W = 0x07 After Instruction W = value of k8 RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS  PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a 2-cycle instruc- tion. DS40001291H-page 232  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP Operands: 0  f  127 Operands: None d  [0,1] Operation: 00h  WDT, Operation: See description below 0  WDT prescaler, 1  TO, Status Affected: C 0  PD Description: The contents of register ‘f’ are Status Affected: TO, PD rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD result is placed in the W register. is cleared. Time-out Status bit, If ‘d’ is ‘1’, the result is stored TO is set. Watchdog Timer and back in register ‘f’. its prescaler are cleared. The processor is put into Sleep C Register f mode with the oscillator stopped. Words: 1 Cycles: 1 SUBLW Subtract W from literal Example: RLF REG1,0 Syntax: [ label ] SUBLW k Before Instruction Operands: 0 k 255 REG1 = 1110 0110 C = 0 Operation: k - (W) W) After Instruction Status Affected: C, DC, Z REG1 = 1110 0110 W = 1100 1100 Description: The W register is subtracted (2’s C = 1 complement method) from the 8-bit literal ‘k’. The result is placed in the W register. RRF Rotate Right f through Carry C = 0 W  k Syntax: [ label ] RRF f,d C = 1 W  k Operands: 0  f  127 DC = 0 W<3:0>  k<3:0> d  [0,1] DC = 1 W<3:0>  k<3:0> Operation: See description below Status Affected: C Description: The contents of register ‘f’ are SUBWF Subtract W from f rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the Syntax: [ label ] SUBWF f,d result is placed in the W register. Operands: 0 f 127 If ‘d’ is ‘1’, the result is placed d  [0,1] back in register ‘f’. Operation: (f) - (W) destination) C Register f Status Affected: C, DC, Z Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. C = 0 W  f C = 1 W  f DC = 0 W<3:0>  f<3:0> DC = 1 W<3:0>  f<3:0>  2006-2015 Microchip Technology Inc. DS40001291H-page 233

PIC16F882/883/884/886/887 SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands: 0  f  127 d  [0,1] Operation: (f<3:0>)  (destination<7:4>), (f<7:4>)  (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the 8-bit literal ‘k’. The result is placed in the W register. XORWF Exclusive OR W with f Syntax: [ label ] XORWF f,d Operands: 0  f  127 d  [0,1] Operation: (W) .XOR. (f) destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001291H-page 234  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 16.0 DEVELOPMENT SUPPORT 16.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2006-2015 Microchip Technology Inc. DS40001291H-page 235

PIC16F882/883/884/886/887 16.2 MPLAB XC Compilers 16.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 16.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 16.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001291H-page 236  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 16.6 MPLAB X SIM Software Simulator 16.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 16.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 16.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 16.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2006-2015 Microchip Technology Inc. DS40001291H-page 237

PIC16F882/883/884/886/887 16.11 Demonstration/Development 16.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001291H-page 238  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 17.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ...............................................................................................-0.3V to +13.5V Voltage on all other pins with respect to VSS ...........................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)...............................................................................................................................800 mW Maximum current out of VSS pin...................................................................................................................... 95 mA Maximum current into VDD pin......................................................................................................................... 95 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)20 mA Maximum output current sunk by any I/O pin....................................................................................................25 mA Maximum output current sourced by any I/O pin..............................................................................................25 mA Maximum output current sunk by any I/O PIN................................................................................................... 25 mA Maximum output current sourced by any I/O pin............................................................................................. 25 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.  2006-2015 Microchip Technology Inc. DS40001291H-page 239

PIC16F882/883/884/886/887 FIGURE 17-1: PIC16F882/883/884/886/887 VOLTAGE-FREQUENCY GRAPH, -40°C  TA  +125°C 5.5 5.0 4.5 V) 4.0 ( D D V 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 17-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 C) ± 2% ° 60 ( e r u at r e p 25 ± 1% m e T 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001291H-page 240  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 17.1 DC Characteristics: PIC16F882/883/884/886/887-I (Industrial) PIC16F882/883/884/886/887-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VDD Supply Voltage 2.0 — 5.5 V FOSC < = 8 MHz: HFINTOSC, EC D001 2.0 — 5.5 V FOSC < = 4 MHz D001C 3.0 — 5.5 V FOSC < = 10 MHz D001D 4.5 — 5.5 V FOSC < = 20 MHz D002* VDR RAM Data Retention 1.5 — — V Device in Sleep mode Voltage(1) D003 VPOR VDD Start Voltage to — VSS — V See Section14.2.1 “Power-on Reset ensure internal Power-on (POR)” for details. Reset signal D004* SVDD VDD Rise Rate to ensure 0.05 — — V/ms See Section14.2.1 “Power-on Reset internal Power-on Reset (POR)” for details. signal * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.  2006-2015 Microchip Technology Inc. DS40001291H-page 241

PIC16F882/883/884/886/887 17.2 DC Characteristics: PIC16F882/883/884/886/887-I (Industrial) PIC16F882/883/884/886/887-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Characteristics Min. Typ† Max. Units No. VDD Note D010 Supply Current (IDD)(1, 2) — 13 19 A 2.0 FOSC = 32kHz — 22 30 A 3.0 LP Oscillator mode — 33 60 A 5.0 D011* — 180 250 A 2.0 FOSC = 1MHz — 290 400 A 3.0 XT Oscillator mode — 490 650 A 5.0 D012 — 280 380 A 2.0 FOSC = 4MHz — 480 670 A 3.0 XT Oscillator mode — 0.9 1.4 mA 5.0 D013* — 170 295 A 2.0 FOSC = 1MHz — 280 480 A 3.0 EC Oscillator mode — 470 690 A 5.0 D014 — 290 450 A 2.0 FOSC = 4MHz — 490 720 A 3.0 EC Oscillator mode — 0.85 1.3 mA 5.0 D015 — 8 20 A 2.0 FOSC = 31kHz — 16 40 A 3.0 LFINTOSC mode — 31 65 A 5.0 D016* — 416 520 A 2.0 FOSC = 4MHz — 640 840 A 3.0 HFINTOSC mode — 1.13 1.6 mA 5.0 D017 — 0.65 0.9 mA 2.0 FOSC = 8MHz — 1.01 1.3 mA 3.0 HFINTOSC mode — 1.86 2.3 mA 5.0 D018 — 340 580 A 2.0 FOSC = 4MHz EXTRC mode(3) — 550 900 A 3.0 — 0.92 1.4 mA 5.0 D019 — 3.8 4.7 mA 4.5 FOSC = 20MHz — 4.0 4.8 mA 5.0 HS Oscillator mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k DS40001291H-page 242  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 17.3 DC Characteristics: PIC16F882/883/884/886/887-I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial Conditions Param Device Characteristics Min. Typ† Max. Units No. VDD Note D020 Power-down Base — 0.05 1.2 A 2.0 WDT, BOR, Comparators, VREF and Current(IPD)(2) — 0.15 1.5 A 3.0 T1OSC disabled — 0.35 1.8 A 5.0 — 150 500 nA 3.0 -40°C  TA  +25°C D021 — 1.0 2.2 A 2.0 WDT Current(1) — 2.0 4.0 A 3.0 — 3.0 7.0 A 5.0 D022 — 42 60 A 3.0 BOR Current(1) — 85 122 A 5.0 D023 — 32 45 A 2.0 Comparator Current(1), both — 60 78 A 3.0 comparators enabled — 120 160 A 5.0 D024 — 30 36 A 2.0 CVREF Current(1) (high range) — 45 55 A 3.0 — 75 95 A 5.0 D025* — 39 47 A 2.0 CVREF Current(1) (low range) — 59 72 A 3.0 — 98 124 A 5.0 D026 — 2.0 5.0 A 2.0 T1OSC Current(1), 32.768kHz — 2.5 5.5 A 3.0 — 3.0 7.0 A 5.0 D027 — 0.30 1.6 A 3.0 A/D Current(1), no conversion in — 0.36 1.9 A 5.0 progress D028 — 90 125 A 3.0 VP6 Reference Current — 125 162 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.  2006-2015 Microchip Technology Inc. DS40001291H-page 243

PIC16F882/883/884/886/887 17.4 DC Characteristics: PIC16F882/883/884/886/887-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +125°C for extended Conditions Param Device Characteristics Min. Typ† Max. Units No. VDD Note D020E Power-down Base — 0.05 9 A 2.0 WDT, BOR, Comparators, VREF and Current (IPD)(2) — 0.15 11 A 3.0 T1OSC disabled — 0.35 15 A 5.0 D021E — 1 28 A 2.0 WDT Current(1) — 2 30 A 3.0 — 3 35 A 5.0 D022E — 42 65 A 3.0 BOR Current(1) — 85 127 A 5.0 D023E — 32 45 A 2.0 Comparator Current(1), both — 60 78 A 3.0 comparators enabled — 120 160 A 5.0 D024E — 30 70 A 2.0 CVREF Current(1) (high range) — 45 90 A 3.0 — 75 120 A 5.0 D025E* — 39 91 A 2.0 CVREF Current(1) (low range) — 59 117 A 3.0 — 98 156 A 5.0 D026E — 3.5 18 A 2.0 T1OSC Current(1), 32.768kHz — 4.0 21 A 3.0 — 5.0 24 A 5.0 D027E — 0.30 12 A 3.0 A/D Current(1), no conversion in — 0.36 16 A 5.0 progress D028E — 90 130 A 3.0 VP6 Reference Current — 125 170 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. DS40001291H-page 244  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 17.5 DC Characteristics: PIC16F882/883/884/886/887-I (Industrial) PIC16F882/883/884/886/887-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage I/O Port: D030 with TTL buffer Vss — 0.8 V 4.5V  VDD  5.5V D030A Vss — 0.15 VDD V 2.0V  VDD  4.5V D031 with Schmitt Trigger buf- Vss — 0.2 VDD V 2.0V  VDD  5.5V fer D032 MCLR, OSC1 (RC mode)(1) VSS — 0.2 VDD V D033 OSC1 (XT and LP modes) VSS — 0.3 V D033A OSC1 (HS mode) VSS — 0.3 VDD V VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V 4.5V  VDD 5.5V D040A 0.25 VDD + 0.8 — VDD V 2.0V  VDD  4.5V D041 with Schmitt Trigger buffer 0.8 VDD — VDD V 2.0V  VDD  5.5V D042 MCLR 0.8 VDD — VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V D043A OSC1 (HS mode) 0.7 VDD — VDD V D043B OSC1 (RC mode) 0.9 VDD — VDD V (Note 1) IIL Input Leakage Current(2) D060 I/O ports — 0.1 1 A VSS VPIN VDD, Pin at high-impedance D061 MCLR(3) — 0.1 5 A VSS VPIN VDD D063 OSC1 — 0.1 5 A VSS VPIN VDD, XT, HS and LP oscillator configuration D070* IPUR PORTB Weak Pull-up Cur- 50 250 400 A VDD = 5.0V, VPIN = VSS rent VOL Output Low Voltage(5) D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.) VOH Output High Voltage(5) D090 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.) * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section10.3.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode.  2006-2015 Microchip Technology Inc. DS40001291H-page 245

PIC16F882/883/884/886/887 17.5 DC Characteristics: PIC16F882/883/884/886/887-I (Industrial) PIC16F882/883/884/886/887-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. D100 IULP Ultra Low-Power Wake-Up — 200 — nA See Application Note AN879, Current “Using the Microchip Ultra Low-Power Wake-up Module” (DS00879) Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A CIO All I/O pins — — 50 pF * Data EEPROM Memory D120 ED Byte Endurance 100K 1M — E/W -40°C  TA +85°C D120A ED Byte Endurance 10K 100K — E/W +85°C  TA +125°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON1 to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 5 6 ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C  TA +85°C Cycles before Refresh(4) Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C  TA +85°C D130A ED Cell Endurance 1K 10K — E/W +85°C  TA +125°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VPEW VDD for Row Erase/Write VMIN — 5.5 V VDD for Bulk Erase Opera- 4.5 — 5.5 V tions D133 TPEW Erase/Write cycle time — 2 2.5 ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section10.3.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode. DS40001291H-page 246  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 17.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance 47.2 C/W 40-pin PDIP package Junction to Ambient 24.4 C/W 44-pin QFN package 45.8 C/W 44-pin TQFP package 60.2 C/W 28-pin PDIP package 80.2 C/W 28-pin SOIC package 89.4 C/W 28-pin SSOP package 29 C/W 28-pin QFN package TH02 JC Thermal Resistance 24.7 C/W 40-pin PDIP package Junction to Case 20.0 C/W 44-pin QFN package 14.5 C/W 44-pin TQFP package 29 C/W 28-pin PDIP package 23.8 C/W 28-pin SOIC package 23.9 C/W 28-pin SSOP package 20.0 C/W 28-pin QFN package TH03 TJ Junction Temperature 150 C For derated power calculations TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD (Note 1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = (TJ - TA)/JA (Note 2, 3) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature. 3: Maximum allowable power dissipation is the lower value of either the absolute maximum total power dissipation or derated power (PDER).  2006-2015 Microchip Technology Inc. DS40001291H-page 247

PIC16F882/883/884/886/887 17.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O PORT t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 17-3: LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins 15 pF for OSC2 output DS40001291H-page 248  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 17.8 AC Characteristics: PIC16F882/883/884/886/887 (Industrial, Extended) FIGURE 17-4: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 17-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode DC — 4 MHz XT Oscillator mode DC — 20 MHz HS Oscillator mode DC — 20 MHz EC Oscillator mode Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 20 MHz HS Oscillator mode DC — 4 MHz RC Oscillator mode OS02 TOSC External CLKIN Period(1) 27 — • s LP Oscillator mode 250 — • ns XT Oscillator mode 50 — • ns HS Oscillator mode 50 — • ns EC Oscillator mode Oscillator Period(1) — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC OS04* TosH, External CLKIN High, 2 — — s LP oscillator TosL External CLKIN Low 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TosR, External CLKIN Rise, 0 — • ns LP oscillator TosF External CLKIN Fall 0 — • ns XT oscillator 0 — • ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.  2006-2015 Microchip Technology Inc. DS40001291H-page 249

PIC16F882/883/884/886/887 TABLE 17-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Freq. Sym. Characteristic Min. Typ† Max. Units Conditions No. Tolerance OS06 TWARM Internal Oscillator Switch — — — 2 TOSC Slowest clock when running(3) OS07 TSC Fail-Safe Sample Clock — — 21 — ms LFINTOSC/64 Period(1) OS08 HFOSC Internal Calibrated 1% 7.92 8.0 8.08 MHz VDD = 3.5V, 25°C HFINTOSC Frequency(2) 2% 7.84 8.0 8.16 MHz 2.5V VDD  5.5V, 0°C  TA  +85°C 5% 7.60 8.0 8.40 MHz 2.0V VDD  5.5V, -40°C  TA  +85°C (Ind.), -40°C  TA  +125°C (Ext.) OS09* LFOSC Internal Uncalibrated — 15 31 45 kHz LFINTOSC Frequency OS10* TIOSC HFINTOSC Oscillator — 5.5 12 24 s VDD = 2.0V, -40°C to +85°C ST Wake-up from Sleep — 3.5 7 14 s VDD = 3.0V, -40°C to +85°C Start-up Time — 3 6 11 s VDD = 5.0V, -40°C to +85°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. 3: By design. DS40001291H-page 250  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 17-5: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19 TABLE 17-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS11 TOSH2CKL FOSC to CLKOUT (1) — — 70 ns VDD = 5.0V OS12 TOSH2CKH FOSC to CLKOUT (1) — — 72 ns VDD = 5.0V OS13 TCKL2IOV CLKOUT to Port out valid(1) — — 20 ns OS14 TIOV2CKH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns OS15* TOSH2IOV FOSC (Q1 cycle) to Port out valid — 50 70 ns VDD = 5.0V OS16 TOSH2IOI FOSC (Q2 cycle) to Port input invalid 50 — — ns VDD = 5.0V (I/O in hold time) OS17 TIOV2OSH Port input valid to FOSC(Q2 cycle) 20 — — ns (I/O in setup time) OS18 TIOR Port output rise time(2) — 15 72 ns VDD = 2.0V — 40 32 VDD = 5.0V OS19 TIOF Port output fall time(2) — 28 55 ns VDD = 2.0V — 15 30 VDD = 5.0V OS20* TINP INT pin input high or low time 25 — — ns OS21* TRAP PORTA interrupt-on-change new TCY — — ns input level time * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode.  2006-2015 Microchip Technology Inc. DS40001291H-page 251

PIC16F882/883/884/886/887 FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 17-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33* (due to BOR) * 64 ms delay only if PWRTE bit in the Configuration Word Register 1 is programmed to ‘0’. DS40001291H-page 252  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +85°C 5 — — s VDD = 5V 31 TWDT Watchdog Timer Time-out 10 16 29 ms VDD = 5V, -40°C to +85°C Period (No Prescaler) 10 16 31 ms VDD = 5V 32 TOST Oscillation Start-up Timer — 1024 — TOSC (Note 3) Period(1, 2) 33* TPWRT Power-up Timer Period 40 65 140 ms 34* TIOZ I/O High-impedance from — — 2.0 s MCLR Low or Watchdog Timer Reset 35 VBOR Brown-out Reset Voltage 2.0 — 2.2 V BOR4V bit = 0 (Note 4) 3.6 4.0 4.4 V BOR4V bit = 1, -40°C to +85°C (Note 4) 3.6 4.0 4.5 V BOR4V bit = 1, -40°C to +125°C (Note 4) 36* VHYST Brown-out Reset Hysteresis — 50 — mV 37* TBOR Brown-out Reset Minimum 100 — — s VDD  VBOR Detection Period * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper- ation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended.  2006-2015 Microchip Technology Inc. DS40001291H-page 253

PIC16F882/883/884/886/887 FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value Period 30 or TCY + 40 (1, 2, 4, 8) N Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range — 32.768 — kHz (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync Increment mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001291H-page 254  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (ECCP) CCP1 (Capture mode) CC01 CC02 CC03 Note: Refer to Figure17-3 for load conditions. TABLE 17-6: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCP1 Input Period 3TCY + 40 — — ns N = prescale N value (1, 4 or 16) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2006-2015 Microchip Technology Inc. DS40001291H-page 255

PIC16F882/883/884/886/887 TABLE 17-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristics Min. Typ† Max. Units Comments No. CM01 VOS Input Offset Voltage —  5.0  10 mV (VDD - 1.5)/2 CM02 VCM Input Common Mode Voltage 0 — VDD - 1.5 V CM03* CMRR Common Mode Rejection Ratio +55 — — dB CM04* TRT Response Time Falling — 150 600 ns (Note 1) Rising — 200 1000 ns CM05* TMC2COV Comparator Mode Change to — — 10 s Output Valid * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD-1.5)/2-100mV to (VDD-1.5)/2+20mV. TABLE 17-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristics Min. Typ† Max. Units Comments No. CV01* CLSB Step Size(2) — VDD/24 — V Low Range (VRR = 1) — VDD/32 — V High Range (VRR = 0) CV02* CACC Absolute Accuracy — —  1/2 LSb Low Range (VRR = 1) — — 1/2 LSb High Range (VRR = 0) CV03* CR Unit Resistor Value (R) — 2k —  CV04* CST Settling Time(1) — — 10 s * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guid- ance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. 2: See Section8.10 “Comparator Voltage Reference” for more information. TABLE 17-9: VOLTAGE (VR) REFERENCE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VR Voltage Reference Specifications Operating temperature -40°C  TA  +125°C Param Symbol Characteristics Min. Typ. Max. Units Comments No. VR01 VROUT VR voltage output 0.5 0.6 0.7 V VR02* TSTABLE Settling Time — 10 100* s * These parameters are characterized but not tested. DS40001291H-page 256  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 17-10: PIC16F882/883/884/886/887 A/D CONVERTER (ADC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD01 NR Resolution — — 10 bits bit AD02 EIL Integral Error — — ±1 LSb VREF = 5.12V AD03 EDL Differential Error — — ±1 LSb No missing codes to 10 bits VREF = 5.12V AD04 EOFF Offset Error 0 +1.5 +3.0 LSb VREF = 5.12V AD07 EGN Gain Error — — ±1 LSb VREF = 5.12V AD06 VREF Reference Voltage(3) 2.2 — — V AD06A 2.7 VDD Absolute minimum to ensure 1LSb accuracy AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended — — 10 k Impedance of Analog Voltage Source AD09* IREF VREF Input Current(3) 10 — 1000 A During VAIN acquisition. Based on differential of VHOLD to VAIN. — — 50 A During A/D conversion cycle. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input. 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module.  2006-2015 Microchip Technology Inc. DS40001291H-page 257

PIC16F882/883/884/886/887 TABLE 17-11: PIC16F882/883/884/886/887 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD130* TAD A/D Clock Period 1.6 — 9.0 s TOSC-based, VREF 3.0V 3.0 — 9.0 s TOSC-based, VREF full range A/D Internal RC ADCS<1:0> = 11 (ADRC mode) Oscillator Period 3.0 6.0 9.0 s At VDD = 2.5V 1.6 4.0 6.0 s At VDD = 5.0V AD131 TCNV Conversion Time — 11 — TAD Set GO/DONE bit to new data in A/D (not including Result register Acquisition Time)(1) AD132* TACQ Acquisition Time 11.5 — s AD133* TAMP Amplifier Settling Time — — 5 s AD134 TGO Q4 to A/D Clock Start — TOSC/2 — — — TOSC/2 + TCY — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Section9.3 “A/D Acquisition Requirements” for minimum conditions. DS40001291H-page 258  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 17-10: PIC16F882/883/884/886/887 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 (TOSC/2(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. FIGURE 17-11: PIC16F882/883/884/886/887 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.  2006-2015 Microchip Technology Inc. DS40001291H-page 259

PIC16F882/883/884/886/887 FIGURE 17-12: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure17-3 for load conditions. TABLE 17-12: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. 120 TCKH2DTV SYNC XMIT (Master & Slave) — 40 ns Clock high to data-out valid 121 TCKRF Clock out rise time and fall time (Master mode) — 20 ns 122 TDTRF Data-out rise time and fall time — 20 ns FIGURE 17-13: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure17-3 for load conditions. TABLE 17-13: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. 125 TDTV2CKL SYNC RCV (Master & Slave) Data-hold before CK  (DT hold time) 10 — ns 126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns DS40001291H-page 260  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 17-14: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure17-3 for load conditions. FIGURE 17-15: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure17-3 for load conditions.  2006-2015 Microchip Technology Inc. DS40001291H-page 261

PIC16F882/883/884/886/887 FIGURE 17-16: SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure17-3 for load conditions. FIGURE 17-17: SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure17-3 for load conditions. DS40001291H-page 262  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 17-14: SPI MODE REQUIREMENTS Param Symbol Characteristic Min. Typ† Max. Units Conditions No. 70* TSSL2SCH, SS to SCK or SCK input TCY — — ns TSSL2SCL 71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns 72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns 73* TDIV2SCH, Setup time of SDI data input to SCK edge 100 — — ns TDIV2SCL 74* TSCH2DIL, Hold time of SDI data input to SCK edge 100 — — ns TSCL2DIL 75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns 2.0-5.5V — 25 50 ns 76* TDOF SDO data output fall time — 10 25 ns 77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns 78* TSCR SCK output rise time 3.0-5.5V — 10 25 ns (Master mode) 2.0-5.5V — 25 50 ns 79* TSCF SCK output fall time (Master mode) — 10 25 ns 80* TSCH2DOV, SDO data output valid after 3.0-5.5V — — 50 ns TSCL2DOV SCK edge 2.0-5.5V — — 145 ns 81* TDOV2SCH, SDO data output setup to SCK edge Tcy — — ns TDOV2SCL 82* TSSL2DOV SDO data output valid after SS edge — — 50 ns 83* TSCH2SSH, SS after SCK edge 1.5TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 17-18: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure17-3 for load conditions.  2006-2015 Microchip Technology Inc. DS40001291H-page 263

PIC16F882/883/884/886/887 TABLE 17-15: I2C™ BUS START/STOP BITS REQUIREMENTS Param Unit Symbol Characteristic Min. Typ. Max. Conditions No. s 90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — Start condition 91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first Hold time 400 kHz mode 600 — — clock pulse is generated 92* TSU:STO Stop condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO Stop condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. FIGURE 17-19: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure17-3 for load conditions. DS40001291H-page 264  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 17-16: I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP Module 1.5TCY — 101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP Module 1.5TCY — 102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF 103* TF SDA and SCL fall 100 kHz mode — 300 ns time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF 90* TSU:STA Start condition 100 kHz mode 4.7 — s Only relevant for setup time 400 kHz mode 0.6 — s Repeated Start condition 91* THD:STA Start condition hold 100 kHz mode 4.0 — s After this period the first time 400 kHz mode 0.6 — s clock pulse is generated 106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2) time 400 kHz mode 100 — ns 92* TSU:STO Stop condition 100 kHz mode 4.7 — s setup time 400 kHz mode 0.6 — s 109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns 110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free before a new transmission 400 kHz mode 1.3 — s can start CB Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT=1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released.  2006-2015 Microchip Technology Inc. DS40001291H-page 265

PIC16F882/883/884/886/887 17.9 High Temperature Operation Note1: Writes are not allowed for Flash This section outlines the specifications for the following program memory above 125°C. devices operating in the high temperature range between -40°C and 150°C.(4) 2: The temperature range indicator in the catalog part number and device marking • PIC16F886 is “H” for -40°C to 150°C. • PIC16F887 Example: PIC16F887T-H/PT indicates When the value of any parameter is identical for both the device is shipped in a Tape and reel the 125°C Extended and the 150°C High Temp. configuration, in the TQFP package, and temperature ranges, then that value will be found in the is rated for operation from -40°C to standard specification tables shown earlier in this 150°C. chapter, under the fields listed for the 125°C Extended 3: The +150°C version of the PIC16F886 temperature range. If the value of any parameter is and PIC16F887 will not be offered in unique to the 150°C High Temp. temperature range, PDIP. It will only be offered in SSOP, then it will be listed here, in this section of the data SOIC, QFN and TQFP. sheet. 4: AEC-Q100 reliability testing for devices If a Silicon Errata exists for the product and it lists a intended to operate at 150°C is 1,000 modification to the 125°C Extended temperature range hours. Any design in which the total oper- value, one that is also shared at the 150°C high temp. ating time from 125°C to 150°C will be temperature range, then that modified value will apply greater than 1,000 hours is not warranted to both temperature ranges. without prior written approval from Microchip Technology Inc. TABLE 17-17: ABSOLUTE MAXIMUM RATINGS Parameter Source/Sink Value Units Max. Current: VDD Source 20 mA Max. Current: VSS Sink 50 mA Max. Current: Pin Source 5 mA Max. Current: Pin Sink 10 mA Max. Pin Current: at VOH Source 3 mA Max. Pin Current: at VOL Sink 8.5 mA Max. Port Current: A, B, and C Source 20 mA combined Max. Port Current: A, B, and C Sink 50 mA combined Max. Junction Temperature 155 °C Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001291H-page 266  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 17-20: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 150 ± 6% 125 ± 5% 85 C) ± 2% ° 60 ( e r u t a r e p 25 ± 1% m e T 0 -40 2.1 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) TABLE 17-18: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V, VREF > 2.5V) ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns 250 ns 500 ns 2.0 s Fosc/8 001 400 ns 1.0 s 2.0 s 8.0 s Fosc/32 010 1.6 s 4.0 s 8.0 s 32.0 s Frc x11 2-6 s 2-6 s 2-6 s 2-6 s Legend: Shaded cells should not be used for conversions at temperatures above +125°C. Note 1: TAD must be between 1.6 s and 6.0 s.  2006-2015 Microchip Technology Inc. DS40001291H-page 267

PIC16F882/883/884/886/887 TABLE 17-19: DC CHARACTERISTICS FOR IDD SPECIFICATIONS FOR PIC16F886/7-H (High Temp.) Condition Param Device Min. Typ. Max. Units No. Characteristics VDD Note D001 VDD 2.1 — 5.5 V — FOSC  8 MHz: HFINTOSC, EC 2.1 — 5.5 V — FOSC  4 MHz TABLE 17-20: DC CHARACTERISTICS FOR IPD SPECIFICATIONS FOR PIC16F886/7-H (High Temp.) Condition Param Device Units Min. Typ. Max. No. Characteristics VDD Note D020E Power Down Base — — 27 2.1 IPD Base: WDT, BOR, Current (IPD) — — 29 A 3.0 Comparators, VREF and — — 32 5.0 T1OSC disabled D021E — — 55 2.1 — — 59 A 3.0 WDT Current — — 69 5.0 D022E — — 75 3.0 A BOR Current — — 147 5.0 D023E — — 73 2.1 Comparator current, both — — 117 A 3.0 comparators enabled — — 235 5.0 D024E — — 102 2.1 — — 128 A 3.0 CVREF current, high range — — 170 5.0 D024AE — — 133 2.1 — — 167 A 3.0 CVREF current, low range — — 222 5.0 D025E — — 36 2.1 — — 41 A 3.0 T1OSC current, 32 kHz — — 47 5.0 D026E — — 22 3.0 Analog-to-Digital current, A — — 24 5.0 no conversion in progress D027E — — 189 3.0 VP6 current (Fixed Voltage A — — 250 5.0 Reference) TABLE 17-21: LEAKAGE CURRENT SPECIFICATIONS FOR PIC16F886/7-H (High Temp.) Param Sym. Characteristic Min. Typ. Max. Units Conditions No. D061 IIL Input Leakage Current(1) — ±0.5 ±5.0 µA VSS VPIN VDD (RA3/MCLR) D062 IIL Input Leakage Current(2) 50 250 400 µA VDD = 5.0V (RA3/MCLR) Note 1: This specification applies when RA3/MCLR is configured as an input with the pull-up disabled. The leakage current for the RA3/MCLR pin is higher than for the standard I/O port pins. 2: This specification applies when RA3/MCLR is configured as the MCLR reset pin function with the weak pull-up enabled. DS40001291H-page 268  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 TABLE 17-22: DATA EEPROM MEMORY ENDURANCE SPECIFICATIONS FOR PIC16F886/7-H (High Temp.) Param Sym. Characteristic Min. Typ. Max. Units Conditions No. D120A ED Byte Endurance 5K 50K — E/W 126°C TA 150°C TABLE 17-23: OSCILLATOR PARAMETERS FOR PIC16F886/7-H (High Temp.) Param Frequency Sym. Characteristic Min. Typ. Max. Units Conditions No. Tolerance OS08 INTOSC Int. Calibrated INTOSC ±7.5% 7.4 8.0 8.6 MHz 2.1V VDD 5.5V Freq.(1) -40°C TA 150°C Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended. TABLE 17-24: WATCHDOG TIMER SPECIFICATIONS FOR PIC16F886/7-H (High Temp.) Param Sym. Characteristic Min. Typ. Max. Units Conditions No. 31 TWDT Watchdog Timer Time-out Period 10 20 70 ms 150°C Temperature (No Prescaler) TABLE 17-25: COMPARATOR SPECIFICATIONS FOR PIC16F886/7-H (High Temp.) Param Sym. Characteristic Min. Typ. Max. Units Conditions No. CM01 VOS Input Offset Voltage — ±5 ±20 mV (VDD - 1.5)/2 TABLE 17-26: ADC SPECIFICATIONS FOR PIC16F886/7-H (High Temp.) Param Sym. Characteristic Min. Typ. Max. Units Conditions No. AD02 EIL Integral Error — — ±1.5 LSb VDD = 5.12V AD07 EGN Gain Error — — ±1.5 LSb VDD = 5.12V  2006-2015 Microchip Technology Inc. DS40001291H-page 269

PIC16F882/883/884/886/887 18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.” represents (mean+3) or (mean-3) respectively, where  is a standard deviation, over each tem- perature range. DS40001291H-page 270  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-1: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) Typical 2V 3V 4V 5V 5.5V 1Mhz 0.086 0.153 0.22E0C Mode0.277 0.310 2Mhz 0.150 0.2596 0.3718 0.4681 0.5236 4Mhz 0.279 0.472 0.675 0.850 0.951 4.0 6Mhz 0.382 0.635 0.903 1.135 1.269 8Mhz Typical: Statis0t.i4c8a6l Mean @02.759°C8 1.132 1.420 1.587 10Mhz 0.589 0.961 1.360 1.706 1.905 5.5V 3.5 Maximum: Mean (Worst-case Temp) + 3 12Mhz 0.696 1.126 1.596 2.005 2.241 (-40°C to 125°C) 14Mhz 0.802 1.291 1.832 2.304 2.577 16Mhz 0.908 1.457 2.068 2.603 2.913 5V 3.0 18Mhz 1.017 1.602 2.268 2.848 3.185 20Mhz 1.126 1.748 2.469 3.093 3.458 2.5 4V A) Maxm 2.0 2V 3V 4V 5V 5.5V (D 1Mhz 0.168 0.236 0.315 0.412 0.452 ID 2Mhz 0.261 0.394 0.537 0.704 0.780 3V 14.5Mhz 0.449 0.710 0.981 1.287 1.435 6Mhz 0.577 0.972 1.331 1.739 1.950 8Mhz 0.705 1.233 1.682 2.191 2.465 2V 11.00Mhz 0.833 1.495 2.032 2.642 2.979 12Mhz 0.956 1.711 2.372 3.101 3.506 14Mhz 1.078 1.926 2.713 3.560 4.032 01.65Mhz 1.201 2.142 3.054 4.018 4.558 18Mhz 1.305 2.326 3.295 4.324 4.887 20Mhz 1.409 2.510 3.536 4.630 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz VDD (V) FIGURE 18-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 6.0 Typical: Statistical Mean @25°C 5.5V 5.0 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 5V 4.0 4V A) m 3.0 (D ID 3V 2.0 2V 1.0 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz VDD (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 271

PIC16F882/883/884/886/887 FIGURE 18-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) HS Mode 5.0 Typical: Statistical Mean @25°C 4.5 Maximum: Mean (Worst-case Temp) + 3 5.5V (-40°C to 125°C) 4.0 5V 4.5V 3.5 3.0 A) m 2.5 (D 3V 3.5V 4V 4.5V 5V 5.5V ID 2.0 0.567660978 0.6909750.8211857610.9883470541.0462473761.119615457 1.1610564131.4069334781.6664380432.0030751092.1193190652.268818804 4V 2.8830885873.03554863 3.23775 1.5 3.5V 3.741393.967407543 3V 1.0 0.5 0.0 4 MHz 10 MHz 16 MHz 20 Mhz FOSC FIGURE 18-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) HS Mode 5.5 5.0 Typic3aVl: Statistical 3M.5eVan @25°C4V 4.5V 5V 5.5V 5.5V Maxim0u.m88: 6M8e6a0n8 6(W41o.0rs6t9-c3a0s4e3 1T6e1m.2p6) 4+5 3617521.4868166111.5076394231.520959608 5V 4.5 (-40°C1 t.o6 1172653°C71)031.96236425 92.3355493582.7630868222.8139211682.849632041 4.5V 3.8375797553.9157601913.967889512 4.0 4.685048474 4.78069621 3.5 A) 3.0 m (D 2.5 D 4V I 2.0 3.5V 3V 1.5 1.0 0.5 0.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC DS40001291H-page 272  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-5: TYPICAL IDD vs. VDD OVER FOSC (XT MODE) XT Mode 1,200 2 2.5 3 3.5 4 4.5 5 5.5 TTyypipcailc: Sa1tal8:t i0sSt.i1ctaa7l M7ti4seatnic @2a32l55 M×.C0e6a83n @28295.9°C592 337.753 385.547 436.866 488.184 554.8964 Maximum: Mean (Worst Case Temp) + 3 (M-40a×xCi mto2 1u823m5×.7C: )3M33ean 3(8W2o.4r8s4t-c4a8s1e. 2T3e4m7p)5 7+7 3.923 674.6106 783.831 893.052 1033.15 1,000 (-40°C to 125°C) Vdd 2 2.5 3 3.5 4 4.5 5 5.5 800 244.8837 320.7132 396.5426 461.707 526.8719 587.642 648.412 724.0755 375.529 522.3721 669.2152 822.619 976.0232 1163.67 1351.32 A) (uD 600 4 MHz D I 400 1 MHz 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE) XT Mode 1,800 Typical: Statistical Mean @25°C 1,600 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 1,400 1,200 A) 1,000 u 4 MHz (DD 800 I 600 1 MHz 400 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 273

PIC16F882/883/884/886/887 FIGURE 18-7: TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE) (EXTRC Mode) 1,800 Typical: Statistical Mean @25°C 1,600 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 1,400 1,200 4 MHz A) 1,000 u (D D 800 I 1 MHz 600 400 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-8: MAXIMUM IDD vs. VDD (EXTRC MODE) 2,000 1,800 TTypyipciacla: lS: Stattaistitsictiacla Ml Meaena n@ @252°5C×C MMaxaixmimumum: M: Meaena n( W(Worosrts-tc aC saes eT eTmemp)p +) +3 3 (-40×C to 125×C) 1,600 (-40°C to 125°C) 1,400 4 MHz 1,200 A) u 1,000 (D D I 800 1 MHz 600 400 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001291H-page 274  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-9: IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz) LFINTOSC Mode, 31KHZ 80 Typical: Statistical Mean @25°C 70 Maximum: Mean (Worst-c ase Temp) + 3 (-40°C to 125°C) 60 50 Maximum A) (D 40 D I 30 Typical 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-10: IDD vs. VDD (LP MODE) 80 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3 70 (-40°C to 125°C) 60 A) 50 u 32 kHz Maximum (D D 40 I 30 32 kHz Typical 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 275

PIC16F882/883/884/886/887 FIGURE 18-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 4V 5V 5.5V 2,500 197.9192604299.82617395.019496.999574.901 TyTpyipciacla: lS: tSattaistitsict2iac1la 0Ml .M9e1ae2na4 n@6 @82852°35C2×4C.4079431.721544.182 620.66 MM(a-4xai0xm×imuCmu tm:o M :1 Me2a5en×a2 Cn3(W )9(W.o9r7os0rts-7ct7 aC0s a8e3s 6Te9 eT.m7e7pm8)p 0+)9 3+4 931.538623.314717.723 5.5V 298.6634479460.30461619.714793.635901.409 2,000 (-40°C to 125°C) 414.3997292639.99889 878.131127.53 1275.6 5V 649.86985881014.40021421.211858.972097.71 1,500 A) 4V u (D D I 1,000 3V 2V 500 2V 3V 4V 5V 5.5V 0 125 kHz 25 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz VDD (V) FIGURE 18-12: MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 3,000 Typical: Statistical Mean @25°C 5.5V Maximum: Mean (Worst-case Temp) + 3 2,500 (-40°C to 125°C) 5V 2,000 4V A) (uD 1,500 D I 3V 1,000 2V 500 0 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz VDD (V) DS40001291H-page 276  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 0.35 0.30 A) 0.25 u (D P 0.20 I 0.15 0.10 0.05 0.00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-14: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18 Typical: Statistical Mean @25°C 16 MMaaxxiimmuumm:: MMeeaann +(W 3orst-case Temp) + 3 (-40°C to 125°C) 14 Max. 125°C 12 A) 10  (D P 8 I 6 4 Max. 85°C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 277

PIC16F882/883/884/886/887 FIGURE 18-15: COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED) 180 Typical: Statistical Mean @25°C 160 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 140 120 Maximum A) 100 u (PD 80 I Typical 60 Typical Max 40 31.9 43.9 45.6 60.8 59.3 2077.7 73.0 95.8 86.7 113.8 0 100.4 131.8 114.1 149.9 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 127.7 VDD (V) FIGURE 18-16: BOR IPD vs. VDD OVER TEMPERATURE 160 Typical: Statistical Mean @25°C 140 Maximum: Mean (Worst-ca se Temp) + 3 (-40°C to 125°C) 120 100 Maximum A)  (D 80 P I Typical 60 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001291H-page 278  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-17: TYPICAL WDT IPD vs. VDD (25°C) 3.0 2.5 TypicalT: ySptiactaisltical MMeaaxn 8@5×25C°CMax 125×C 21.007 2.140 27.702 2.51.146 2.711 29.079 31.285 3.282 30.08 2.0 3.51.449 3.899 31.347 41.612 4.515 32.238 4.51.924 5.401 33.129 A) 52.237 6.288 34.02 u 1.5 5.52.764 7.776 (D P I 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE 40.0 Maximum: Mean + 3 Maximum: Mean + 3 35.0 Max. 125°C 30.0 25.0 A) u 20.0 (D P I 15.0 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 279

PIC16F882/883/884/886/887 FIGURE 18-19: WDT PERIOD vs. VDD OVER TEMPERATURE WDT Time-out Period 32 30 Maximum: Mean + 3(-40°C to 125°C) 28 Max. (125°C) 26 Max. (85°C) 24 s) m 22 e ( m 20 Ti Typical 18 16 14 12 Minimum 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-20: WDT PERIOD vs. TEMPERATURE (VDD = 5.0V) Vdd = 5V 30 Typical: Statistical Mean @25°C 28 Maximum: Mean (Worst-case Temp) + 3 26 Maximum 24 22 s) m e ( 20 m Typical Ti 18 16 14 Minimum 12 10 -40°C 25°C 85°C 125°C Temperature (°C) DS40001291H-page 280  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-21: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE) High Range 140 Max 85×C Max 125×C T3y5p.8ical: Stat6is8t.i0cal Mean @25°C M44a.x8imum: M7e7a.3n (Worst-case Temp) + 3 120 53.8 86.5 (-40°C to 125°C) 62.8 94.3 71.8 102.1 81.0 109.8 100 Max. 125°C 90.1 117.6 99.2 125.1 80 A) (uD Max. 85°C IP 60 Typical 40 Max 85×C Max 125×C 20 46.5 86.4 58.3 98.1 70.0 109.9 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-22: CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE) low Range 180 Typical: Statistical Mean @25°C 160 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 140 Max. 125°C 120 A) 100 u Max. 85°C (D P 80 I Typical 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 281

PIC16F882/883/884/886/887 FIGURE 18-23: TYPICAL VP6 REFERENCE IPD vs. VDD (25°C) VP6 Reference IPD vs. VDD (25×C) 160 140 120 100 Typical ) A u (D 80 P I 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-24: MAXIMUM VP6 REFERENCE IPD vs. VDD OVER TEMPERATURE Max VP6 Reference IPD vs. VDD Over Temperature 180 160 140 Max 125C 120 A) 100 Max 85C u ( D P 80 I 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001291H-page 282  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-25: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz) 30 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3 25 (-40°C to 125°C) Max. 125°C 20 A) u 15 (D Typ 25×C Max 85×C Max 125×C P I 2 2.022 4.98 17.54 2.5 2.247 5.23 19.02 10 3 2.472 5.49 20.29 3.5 2.453 5.79 21.50 Max. 85°C 4 2.433 6.08 22.45 4.5 2.711 6.54 23.30 5 5 2.989 7.00 24.00 5.5 3.112 7.34 Typ. 25°C 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-26: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean + 3 Max. 125°C 0.6 0.5 Max. 85°C V) (L 0.4 O V 0.3 Typical 25°C 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA)  2006-2015 Microchip Technology Inc. DS40001291H-page 283

PIC16F882/883/884/886/887 FIGURE 18-27: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C 0.40 MaximTuympi:c aMl:e Santa +tis 3tical Mean Maximum: Means + 3 Max. 125°C 0.35 Max. 85°C 0.30 0.25 V) (L Typ. 25°C O V 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 18-28: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C 2.0 V) (H O V 1.5 Typical: Statistical Mean @25°C 1.0 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) DS40001291H-page 284  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-29: VOH vs. IOH OVER TE(MPERAT, URE (VDD = 5).0V) 5.5 5.0 Max. -40°C Typ. 25°C 4.5 V) Min. 125°C (H O V 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) FIGURE 18-30: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (TTL Input, -40×C TO 125×C) 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) Max. -40°C 1.3 Typ. 25°C V) (N 1.1 VI Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 285

PIC16F882/883/884/886/887 FIGURE 18-31: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) VIH Min. -40°C 3.0 2.5 V) (N VI 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-32: COMPARATOR RESPONSE TIME (RISING EDGE) 4 200 278 639 846 5.5 1V40+ input 2=0 V2CM 531 V- input = Transition from VCM + 100MV to VCM - 20MV 1,000 900 800 Max. (125°C) 700 S) n e ( 600 Note: VCM = VDD - 1.5V)/2 m Ti V+ input = VCM se 500 V- input = Transition from VCM + 100MV to VCM - 20MV Max. (85°C) n po 400 s e R 300 200 Typ. (25°C) Min. (-40°C) 100 0 2.0 2.5 4.0 5.5 VDD (Volts) DS40001291H-page 286  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-33: COMPARATOR RESPONSE TIME (FALLING EDGE) Vdd -40×C 25×C 85×C 125×C 2 279 327 547 557 620.50 226 267 425 440 4 172 204 304 319 5.5 119 142 182 500 S) 400 n e ( m Ti e 300 s n o p s Re 200 Max. (125°C) Max. (85°C) Note: VCM = VDD - 1.5V)/2 Typ. (25°C) 100 V+ input = VCM Min. (-40°C) V- input = Transition from VCM - 100MV to VCM + 20MV 0 2.0 2.5 4.0 5.5 VDD (Volts) FIGURE 18-34: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz) LFINTOSC 31Khz 45,000 40,000 Max. -40°C 35,000 Typ. 25°C 30,000 z) H y ( 25,000 c n e qu 20,000 Min. 85°C e r F Min. 125°C 15,000 10,000 Typical: Statistical Mean @25°C 5,000 Maximum: Mean (Worst-case) + 3 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 287

PIC16F882/883/884/886/887 FIGURE 18-35: ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3 125°C (-40°C to 125°C) 6 85°C s)  25°C e ( 4 m Ti -40°C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-36: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 16 Typical: Statistical Mean @25°C 14 Maximum: Mean (Worst-case) + 3 85°C 12 25°C 10 s) -40°C  e ( 8 m Ti 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001291H-page 288  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-37: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 25 Typical: Statistical Mean @25°C 20 Maximum: Mean (Worst-case) + 3 15 s) 85°C  e ( m Ti 25°C 10 -40°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-38: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 10 9 Typical: Statistical Mean @25°C 8 Maximum: Mean (Worst-case Temp) + 3 7 85°C 6 s) 25°C  e ( 5 m Ti -40°C 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 289

PIC16F882/883/884/886/887 FIGURE 18-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 3 2 %) n ( 1 o ati br 0 ali m C -1 o e fr -2 g n a -3 h C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-40: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C) 5 4 3 %) n ( 2 o ati 1 r b Cali 0 m o -1 r e f ng -2 a h C -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001291H-page 290  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-41: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 3 %) 2 n ( o 1 ati r alib 0 C m -1 o r e f -2 g n ha -3 C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD ( V) FIGURE 18-42: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 3 %) 2 n ( o 1 ati r b 0 ali C m -1 o r e f -2 g n ha -3 C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD ( V)  2006-2015 Microchip Technology Inc. DS40001291H-page 291

PIC16F882/883/884/886/887 FIGURE 18-43: TYPICAL VP6 REFERENCE VOLTAGE vs. VDD (25°C) VP6 Reference Voltage vs. VDD (25×C) 0.65 0.64 0.63 0.62 0.61 ) V ( 6 0.60 P V 0.59 Typical 0.58 0.57 0.56 0.55 2 3 4 5 5.5 VDD (V) FIGURE 18-44: VP6 DRIFT OVER TEMPERATURE NORMALIZED AT 25°C (VDD 5V) 4 3 2 % n al i n mi 1 o N m o e fr 0 g n a h C -1 -2 -40 0 25 85 125 Temperature in Degrees C DS40001291H-page 292  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-45: VP6 DRIFT OVER TEMPERATURE NORMALIZED AT 25°C (VDD 3V) 4 3 2 % n al i n mi 1 o N m o e fr 0 g n a h C -1 -2 -40 0 25 85 125 Temperature in Degrees C FIGURE 18-46: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 25°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 25×C) 35 Parts=118 30 25 s t r a P of 20 r e b m 15 u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 293

PIC16F882/883/884/886/887 FIGURE 18-47: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 85°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 85×C) 40 35 Parts=118 30 s t r a P 25 f o r e 20 b m u N 15 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V) FIGURE 18-48: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 125°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 125×C) 40 35 Parts=118 30 s rt a P 25 of r e 20 b m u N 15 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V) DS40001291H-page 294  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-49: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, -40°C) Typical VP6 Reference Voltage Distribution (VDD=3V, -40×C) 30 Parts=118 25 s rt 20 a P of r e 15 b m u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V) FIGURE 18-50: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 25°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C) 30 25 Parts=118 s rt 20 a P of r e 15 b m u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 295

PIC16F882/883/884/886/887 FIGURE 18-51: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 85°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 85×C) 35 30 Parts=118 25 s rt a P of 20 r e b m 15 u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V) FIGURE 18-52: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 125°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C) 30 25 Parts=118 s rt 20 a P of r e 15 b m u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V) DS40001291H-page 296  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 FIGURE 18-53: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, -40°C) Typical VP6 Reference Voltage Distribution (VDD=5V, -40×C) 30 25 Parts=118 s rt 20 a P of r e 15 b m u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V)  2006-2015 Microchip Technology Inc. DS40001291H-page 297

PIC16F882/883/884/886/887 19.0 PACKAGING INFORMATION 19.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC16F883 -I/P e3 1231220 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX PIC16F886/SO e3 XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 1231220 28-Lead SSOP (5.30 mm) Example PIC16F883 -I/SSe3 1231220 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS40001291H-page 298  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 19.1 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 XXXXXXXX 16F886 XXXXXXXX /ML e3 YYWWNNN 1231220 40-Lead PDIP (600 mil) Example XXXXXXXXXXXXXXXXXX PIC16F885 XXXXXXXXXXXXXXXXXX -I/Pe3 XXXXXXXXXXXXXXXXXX YYWWNNN 1231220 44-Lead QFN (8x8x0.9 mm) Example PIN 1 PIN 1 XXXXXXXXXXX PIC16F887 XXXXXXXXXXX -I/ML e3 XXXXXXXXXXX YYWWNNN 1231220 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2006-2015 Microchip Technology Inc. DS40001291H-page 299

PIC16F882/883/884/886/887 19.1 Package Marking Information (Continued) 44-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX PIC16F887 XXXXXXXXXX -I/PT e3 XXXXXXXXXX YYWWNNN 1231220 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS40001291H-page 300  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 19.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)(cid:26)(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1  2006-2015 Microchip Technology Inc. DS40001291H-page 301

PIC16F882/883/884/886/887 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001291H-page 302  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2006-2015 Microchip Technology Inc. DS40001291H-page 303

PIC16F882/883/884/886/887 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001291H-page 304  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)#$(cid:12)(cid:13)(cid:11)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)%(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:10)(cid:24)(cid:9)(cid:25)(cid:9)&’(cid:26)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:10)%(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:30)(cid:4)(cid:20)(cid:3)(cid:4) (cid:30)(cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)-1  2006-2015 Microchip Technology Inc. DS40001291H-page 305

PIC16F882/883/884/886/887 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001291H-page 306  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887  2006-2015 Microchip Technology Inc. DS40001291H-page 307

PIC16F882/883/884/886/887 DS40001291H-page 308  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)((cid:21)(cid:7)(cid:8)(cid:9))(cid:16)(cid:7)(cid:18)*(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)+(cid:6)(cid:9)(cid:23),(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)-.-(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)()! /(cid:12)(cid:18)#(cid:9)(cid:27)’&&(cid:9)(cid:28)(cid:28)(cid:9)0(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13)+(cid:18)# !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2006-2015 Microchip Technology Inc. DS40001291H-page 309

PIC16F882/883/884/886/887 1(cid:27)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)-(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c b1 A1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:29) = (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:29)(cid:24)(cid:4) = (cid:20)?(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:23)<(cid:29) = (cid:20)(cid:29)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)(cid:24)<(cid:4) = (cid:3)(cid:20)(cid:4)(cid:24)(cid:29) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) = (cid:20)(cid:3)(cid:4)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< = (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)-(cid:4) = (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) = (cid:20)(cid:4)(cid:3)- : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:5)(cid:4)(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)?1 DS40001291H-page 310  2006-2015 Microchip Technology Inc.

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PIC16F882/883/884/886/887 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A D1 B NOTE 2 (DATUM A) (DATUM B) E1 E A A NOTE 1 2X N 0.20 H A B 2X 1 2 3 0.20 H A B TOP VIEW 4X 11 TIPS 0.20 C A B A A2 C SEATING PLANE 0.10 C A1 SIDE VIEW 1 2 3 N NOTE 1 44 X b 0.20 C A B e BOTTOM VIEW Microchip Technology Drawing C04-076C Sheet 1 of 2 DS40001291H-page 314  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging H c θ L (L1) SECTION A-A Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 44 Lead Pitch e 0.80 BSC Overall Height A - - 1.20 Standoff A1 0.05 - 0.15 Molded Package Thickness A2 0.95 1.00 1.05 Overall Width E 12.00 BSC Molded Package Width E1 10.00 BSC Overall Length D 12.00 BSC Molded Package Length D1 10.00 BSC Lead Width b 0.30 0.37 0.45 Lead Thickness c 0.09 - 0.20 Lead Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle θ 0° 3.5° 7° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Exact shape of each corner is optional. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076C Sheet 2 of 2  2006-2015 Microchip Technology Inc. DS40001291H-page 315

PIC16F882/883/884/886/887 44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 44 1 2 G C2 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.80 BSC Contact Pad Spacing C1 11.40 Contact Pad Spacing C2 11.40 Contact Pad Width (X44) X1 0.55 Contact Pad Length (X44) Y1 1.50 Distance Between Pads G 0.25 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2076B DS40001291H-page 316  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 APPENDIX A: DATA SHEET Revision G (10/2012) REVISION HISTORY Updated data sheet to new format; Updated Register 13-1 and Register 13-2; Updated the Packaging Revision A (5/2006) Information section; Updated the Product Identification System section; Other minor corrections. Initial release of this data sheet. Revision H (04/2015) Revision B (7/2006) Added Section 17.9: High Temperature Operation in Pin Diagrams (44-Pin QFN drawing); Revised Table the Electrical Specifications section. 2-1, Addr. 1DH (CCP2CON); Section 3.0, 3.1; Section 3.4.4.6; Table 3; Table 3-1 (ANSEL); Table 3-3 (CCP2CON); Register 3-1; Register 3.2; Register 3-3; Register 3-4; Register 3-9; Register 3-10; Register 3-11; Register 3-12; Register 3-14; Table 3-5 (ANSEL); Figure 3-5; Figure 3-11; Figure 8-2; Figure 8-3; Figure 9-1; Register 9-1; Section 9.1.4; Example 10-4; Figure 11-5; Table 11-5 (P1M); Section 11.5.2; Section 11.5.7, Number 4; Table 11-7 (CCP2CON); Section 12.3.1 (Para. 3); Figure 12-6 (Title); Sections 14.2, 14.3 and 14.4 DC Characteristics (Max); Table 14-4 (OSCCON); Section 14.3 (TMR0); Section 14.3.2 (TMR0). Revision C Section 19.0 Packaging Information: Replaced package drawings and added note. Added PIC16F882 part number. Replaced PICmicro with PIC. Revision D Replaced Package Drawings (Rev. AM); Replaced Development Support Section; Revised Product ID Section. Revision E (01/2008) Added Char Data; Removed Preliminary status; Revised Device Table (PIC16F882, I/O); Revised the following: Pin Diagram 44 TQFP, pin 30; Table 5, I/O RA7; Table 1-1, RA1 and RA4; Section 2.2.1; Register 2-3, INTCON; Example 3-1; Section 3.2.2; Example 3-2; Figure 6-1; Section 6.2.2; Section 6.6; Section 8.10.3; Table 9-1; Equation 11-1; Added Figure 11-14 and renumbered remaining Figures; Register 11-3; Register 13-3; Section 14.0; Section 14.1; Section 14.9; Section 14.10; Section 17.0; Updated Package Drawings. Revision F (04/2009) Revised Product ID: Removed ‘F’ (std. voltage range) from part numbers; Revised Figure 6-1: Timer1 Block Diagram; Revised Figure 8-3, Comparator C2 Block Diagram; Added note to Section 8.10.3; Revised Section 8.10.7.  2006-2015 Microchip Technology Inc. DS40001291H-page 317

PIC16F882/883/884/886/887 APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This discusses some of the issues in migrating from other PIC devices to the PIC16F88X Family of devices. B.1 PIC16F87X to PIC16F88X TABLE B-1: FEATURE COMPARISON Feature PIC16F87X PIC16F88X Max Operating Speed 20MHz 20MHz Max Program 8192 8192 Memory (Words) SRAM (bytes) 368 368 A/D Resolution 10-bit 10-bit Data EEPROM (Bytes) 256 256 Timers (8/16-bit) 2/1 2/1 Oscillator Modes 4 8 Brown-out Reset Y Y (2.1V/4V) Software Control Option N Y of WDT/BOR Internal Pull-ups RB<7:4> RB<7:0>, MCLR Interrupt-on-change RB<7:4> RB<7:0> Comparator 2 2 References CVREF CVREF and VP6 ECCP/CCP 0/2 1/1 Ultra Low-Power N Y Wake-Up Extended WDT N Y INTOSC Frequencies N 32kHz-8MHz Clock Switching N Y MSSP Standard w/Slave Address Mask USART AUSART EUSART ADC Channels 8 14 Note: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. DS40001291H-page 318  2006-2015 Microchip Technology Inc.

PIC16F882/883/884/886/887 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://www.microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2006-2015 Microchip Technology Inc. DS40001291H-page 319

PIC16F882/883/884/886/887 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) - X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC16F883-E/P 301 = Extended Temp., PDIP Option Range package, 20 MHz, QTP pattern #301 b) PIC16F883-I/SO = Industrial Temp., SOIC package, 20 MHz Device: PIC16F883, PIC16F883T(1), PIC16F884, PIC16F884T(1), PIC16F886, PIC16F886T(1), PIC16F887, PIC16F887T(1), VDD range 2.0V to 5.5V Tape and Reel Blank = Standard packaging (tube or tray) Option: T = Tape and Reel(1) Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Package:(2) ML = Quad Flat No Leads (QFN) Note1: Tape and Reel identifier only appears in the P = Plastic DIP catalog part number description. This PT = Plastic Thin-Quad Flatpack (TQFP) identifier is used for ordering purposes and is SO = Plastic Small Outline (SOIC) (7.50 mm) not printed on the device package. Check SP = Skinny Plastic DIP with your Microchip Sales Office for package SS = Plastic Shrink Small Outline availability with the Tape and Reel option. 2: For other small form-factor package availability and marking information, please Pattern: QTP, SQTP, Code or Special Requirements visit www.microchip.com/packaging or (blank otherwise) contact your local sales office. DS40001291H-page 320  2006-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2006-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-237-4 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2006-2015 Microchip Technology Inc. DS40001291H-page 321

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16F883-E/ML PIC16F883-E/SO PIC16F883-E/SP PIC16F883-E/SS PIC16F883-I/ML PIC16F883-I/SO PIC16F883-I/SP PIC16F883-I/SS PIC16F883T-I/ML PIC16F883T-I/SO PIC16F883T-I/SS PIC16F884-E/ML PIC16F884-E/P PIC16F884-E/PT PIC16F884-I/ML PIC16F884-I/P PIC16F884-I/PT PIC16F884T-I/ML PIC16F884T- I/PT PIC16F886-E/ML PIC16F886-E/SO PIC16F886-E/SP PIC16F886-E/SS PIC16F886-I/ML PIC16F886-I/SO PIC16F886-I/SP PIC16F886-I/SS PIC16F886T-I/ML PIC16F886T-I/SO PIC16F886T-I/SS PIC16F887-E/ML PIC16F887-E/P PIC16F887-E/PT PIC16F887-I/ML PIC16F887-I/P PIC16F887-I/PT PIC16F887T-I/ML PIC16F887T- I/PT PIC16F882-I/SO PIC16F882-I/SS PIC16F882-I/SP PIC16F882-E/ML PIC16F882-E/SO PIC16F882-E/SP PIC16F882-E/SS PIC16F882-I/ML PIC16F882T-I/ML PIC16F882T-I/SO PIC16F882T-I/SS