PIC16F87XA 28/40/44-Pin Enhanced Flash Microcontrollers Devices Included in this Data Sheet: Analog Features: • PIC16F873A • PIC16F876A • 10-bit, up to 8-channel Analog-to-Digital • PIC16F874A • PIC16F877A Converter (A/D) • Brown-out Reset (BOR) High-Performance RISC CPU: • Analog Comparator module with: - Two analog comparators • Only 35 single-word instructions to learn - Programmable on-chip voltage reference • All single-cycle instructions except for program (VREF) module branches, which are two-cycle - Programmable input multiplexing from device • Operating speed: DC – 20 MHz clock input inputs and internal voltage reference DC – 200 ns instruction cycle - Comparator outputs are externally accessible • Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bytes of Data Memory (RAM), Special Microcontroller Features: Up to 256 x 8 bytes of EEPROM Data Memory • Pinout compatible to other 28-pin or 40/44-pin • 100,000 erase/write cycle Enhanced Flash PIC16CXXX and PIC16FXXX microcontrollers program memory typical • 1,000,000 erase/write cycle Data EEPROM Peripheral Features: memory typical • Data EEPROM Retention > 40 years • Timer0: 8-bit timer/counter with 8-bit prescaler • Self-reprogrammable under software control • Timer1: 16-bit timer/counter with prescaler, • In-Circuit Serial Programming™ (ICSP™) can be incremented during Sleep via external via two pins crystal/clock • Single-supply 5V In-Circuit Serial Programming • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Two Capture, Compare, PWM modules • Programmable code protection - Capture is 16-bit, max. resolution is 12.5 ns • Power saving Sleep mode - Compare is 16-bit, max. resolution is 200 ns • Selectable oscillator options - PWM max. resolution is 10-bit • In-Circuit Debug (ICD) via two pins • Synchronous Serial Port (SSP) with SPI (Master mode) and I2C™(Master/Slave) CMOS Technology: • Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address • Low-power, high-speed Flash/EEPROM detection technology • Parallel Slave Port (PSP) – 8 bits wide with • Fully static design external RD, WR and CS controls (40/44-pin only) • Wide operating voltage range (2.0V to 5.5V) • Brown-out detection circuitry for • Commercial and Industrial temperature ranges Brown-out Reset (BOR) • Low-power consumption Program Memory MSSP Data EEPROM 10-bit CCP Timers Device SRAM I/O USART Comparators # Single Word (Bytes) A/D (ch) (PWM) Master 8/16-bit Bytes Instructions (Bytes) SPI I2C PIC16F873A 7.2K 4096 192 128 22 5 2 Yes Yes Yes 2/1 2 PIC16F874A 7.2K 4096 192 128 33 8 2 Yes Yes Yes 2/1 2 PIC16F876A 14.3K 8192 368 256 22 5 2 Yes Yes Yes 2/1 2 PIC16F877A 14.3K 8192 368 256 33 8 2 Yes Yes Yes 2/1 2  2001-2013 Microchip Technology Inc. DS39582C-page 1

PIC16F87XA Pin Diagrams 28-Pin PDIP, SOIC, SSOP MCLR/VPP 1 28 RB7/PGD RA0/AN0 2 27 RB6/PGC RA1/AN1 3 26 RB5 RA2/AN2/VREF-/CVREF 4 A 25 RB4 RA3/AN3/VREF+ 5 76 24 RB3/PGM RA4/T0CKI/C1OUT 6 A/8 23 RB2 RA5/AN4/SS/C2OUT 7 3 22 RB1 VSS 8 87 21 RB0/INT OSC1/CLKI 9 F 20 VDD 6 OSC2/CLKO 10 1 19 VSS C RC0/T1OSO/T1CKI 11 PI 18 RC7/RX/DT RC1/T1OSI/CCP2 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA P 28-Pin QFN N1N0 VPGDGC AA R/PP A1/A0/ CLB7/B6/B5B4 RR MRRRR 8765432 2222222 RA2/AN2/VREF-/CVREF 1 21 RB3/PGM RA3/AN3/VREF+ 2 20 RB2 RA4/T0CKI/C1OUT 3 PIC16F873A 19 RB1 RA5/AN4/SS/C2OUT 4 18 RB0/INT PIC16F876A VSS 5 17 VDD OSC1/CLKI 6 16 VSS OSC2/CLKO 7 15 RC7/RX/DT 01234 8911111 44-Pin QFN 6/TX/CK5/SDO4/SDI/SDA3/PSP32/PSP21/PSP10/PSP03/SCK/SCL2/CCP11/T1OSI/CCP20/T1OSO/T1CKI RC0/T1OSO/T1CKIRC1/T1OSI/CCP2RC2/CCP1RC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX/CK CCCDDDDCCCC RRRRRRRRRRR 43210987654 RC7/RX/DT 1 4444433333333 OSC2/CLKO RD4/PSP4 2 32 OSC1/CLKI RD5/PSP5 3 31 VSS RD6/PSP6 4 30 VSS RD7/PSP7 5 PIC16F874A 29 VDD VSS 6 28 VDD VDD 7 PIC16F877A 27 RE2/CS/AN7 VDD 8 26 RE1/WR/AN6 RB0/INT 9 25 RE0/RD/AN5 RB1 10 24 RA5/AN4/SS/C2OUT RB2 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 MC45CDP01 F+ RB3/PGNRBRBRB6/PGRB7/PGMCLR/VPRA0/ANRA1/AN-/CVREFREAN3/VREF 2/VA3/ NR A 2/ A R DS39582C-page 2  2001-2013 Microchip Technology Inc.

PIC16F87XA Pin Diagrams (Continued) 40-Pin PDIP MCLR/VPP 1 40 RB7/PGD RA0/AN0 2 39 RB6/PGC RA1/AN1 3 38 RB5 RA2/AN2/VREF-/CVREF 4 37 RB4 RA3/AN3/VREF+ 5 36 RB3/PGM RA4/T0CKI/C1OUT 6 35 RB2 RA5/AN4/SS/C2OUT 7 A 34 RB1 7 RE0/RD/AN5 8 7 33 RB0/INT 8 RE1/WR/AN6 9 A/ 32 VDD RE2/CS/AN7 10 4 31 VSS VDD 11 87 30 RD7/PSP7 VSS 12 F 29 RD6/PSP6 6 OSC1/CLKI 13 1 28 RD5/PSP5 OSC2/CLKO 14 PIC 27 RD4/PSP4 REF RC0/T1OSO/T1CKI 15 26 RC7/RX/DT V C RC1R/TC13RRO/SCDSC20I//K/CCP/CCSSCPPP201L 11116789 22225432 RRRRCCCD6453////TSSPXDDS/PIOC/S3KDA AN3/V+REFAN2/V-/REFAN1AN0R/VPP PGDPGC RD1/PSP1 20 21 RD2/PSP2 A3/A2/A1/A0/CLCB7/B6/B5B4C RRRRMNRRRRN 44-Pin PLCC 65432143210 RA4/T0CKI/C1OUT 7 4444439 RB3/PGM RA5/AN4/SS/C2OUT 8 38 RB2 RE0/RD/AN5 9 37 RB1 RE1/WR/AN6 10 36 RB0/INT RE2/CS/AN7 11 PIC16F874A 35 VDD VDD 12 PIC16F877A 34 VSS VSS 13 33 RD7/PSP7 OSC1/CLKI 14 32 RD6/PSP6 OSC2/CLKO 15 31 RD5/PSP5 RC0/T1OSO/T1CK1 16 30 RD4/PSP4 NC 17 29 RC7/RX/DT 89012345678 2 11222222222 P 44-Pin TQFP RC6/TX/CKRC5/SDORC4/SDI/SDARD3/PSP3RD2/PSP2RD1/PSP1RD0/PSP0RC3/SCK/SCLRC2/CCP1RC1/T1OSI/CCNC 1/T1OSI/CCP2RC2/CCP1RC3/SCK/SCLRD0/PSP0RD1/PSP1RD2/PSP2RD3/PSP3RC4/SDI/SDARC5/SDORC6/TX/CKNC C R 43210987654 44444333333 RC7/RX/DT 1 33 NC RD4/PSP4 2 32 RC0/T1OSO/T1CKI RD5/PSP5 3 31 OSC2/CLKO RD6/PSP6 4 30 OSC1/CLKI RD7/PSP7 5 PIC16F874A 29 VSS VSS 6 PIC16F877A 28 VDD VDD 7 27 RE2/CS/AN7 RB0/INT 8 26 RE1/WR/AN6 RB1 9 25 RE0/RD/AN5 RB2 10 24 RA5/AN4/SS/C2OUT RB3/PGM 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 CC45CDP01F+ NNRBRBRB6/PGRB7/PGMCLR/VPRA0/ANRA1/AN-/CVREFREAN3/VREF 2/VA3/ NR A 2/ A R  2001-2013 Microchip Technology Inc. DS39582C-page 3

PIC16F87XA Table of Contents 1.0 Device Overview......................................................................................................................................................................... 5 2.0 Memory Organization................................................................................................................................................................ 15 3.0 Data EEPROM and Flash Program Memory............................................................................................................................ 33 4.0 I/O Ports.................................................................................................................................................................................... 41 5.0 Timer0 Module.......................................................................................................................................................................... 53 6.0 Timer1 Module.......................................................................................................................................................................... 57 7.0 Timer2 Module.......................................................................................................................................................................... 61 8.0 Capture/Compare/PWM Modules............................................................................................................................................. 63 9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................................... 71 10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)............................................................ 111 11.0 Analog-to-Digital Converter (A/D) Module.............................................................................................................................. 127 12.0 Comparator Module................................................................................................................................................................ 135 13.0 Comparator Voltage Reference Module................................................................................................................................. 141 14.0 Special Features of the CPU.................................................................................................................................................. 143 15.0 Instruction Set Summary......................................................................................................................................................... 159 16.0 Development Support............................................................................................................................................................. 167 17.0 Electrical Characteristics......................................................................................................................................................... 173 18.0 DC and AC Characteristics Graphs and Tables..................................................................................................................... 197 19.0 Packaging Information............................................................................................................................................................ 209 Appendix A:Revision History............................................................................................................................................................ 219 Appendix B:Device Differences........................................................................................................................................................ 219 Appendix C:Conversion Considerations........................................................................................................................................... 220 Index................................................................................................................................................................................................. 221 On-Line Support................................................................................................................................................................................ 229 Systems Information and Upgrade Hot Line..................................................................................................................................... 229 Reader Response............................................................................................................................................................................. 230 PIC16F87XA Product Identification System...................................................................................................................................... 231 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current information on all of our products. DS39582C-page 4  2001-2013 Microchip Technology Inc.

PIC16F87XA 1.0 DEVICE OVERVIEW The available features are summarized in Table1-1. Block diagrams of the PIC16F873A/876A and This document contains device specific information PIC16F874A/877A devices are provided in Figure1-1 about the following devices: and Figure1-2, respectively. The pinouts for these • PIC16F873A device families are listed in Table1-2 and Table1-3. • PIC16F874A Additional information may be found in the PIC® Mid- • PIC16F876A Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative • PIC16F877A or downloaded from the Microchip web site. The Refer- PIC16F873A/876A devices are available only in 28-pin ence Manual should be considered a complementary packages, while PIC16F874A/877A devices are avail- document to this data sheet and is highly recommended able in 40-pin and 44-pin packages. All devices in the reading for a better understanding of the device architec- PIC16F87XA family share common architecture with ture and operation of the peripheral modules. the following differences: • The PIC16F873A and PIC16F874A have one-half of the total on-chip memory of the PIC16F876A and PIC16F877A • The 28-pin devices have three I/O ports, while the 40/44-pin devices have five • The 28-pin devices have fourteen interrupts, while the 40/44-pin devices have fifteen • The 28-pin devices have five A/D input channels, while the 40/44-pin devices have eight • The Parallel Slave Port is implemented only on the 40/44-pin devices TABLE 1-1: PIC16F87XA DEVICE FEATURES Key Features PIC16F873A PIC16F874A PIC16F876A PIC16F877A Operating Frequency DC – 20 MHz DC – 20 MHz DC – 20 MHz DC – 20 MHz Resets (and Delays) POR, BOR POR, BOR POR, BOR POR, BOR (PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST) Flash Program Memory 4K 4K 8K 8K (14-bit words) Data Memory (bytes) 192 192 368 368 EEPROM Data Memory (bytes) 128 128 256 256 Interrupts 14 15 14 15 I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E Timers 3 3 3 3 Capture/Compare/PWM modules 2 2 2 2 Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART Parallel Communications — PSP — PSP 10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels Analog Comparators 2 2 2 2 Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions Packages 28-pin PDIP 40-pin PDIP 28-pin PDIP 40-pin PDIP 28-pin SOIC 44-pin PLCC 28-pin SOIC 44-pin PLCC 28-pin SSOP 44-pin TQFP 28-pin SSOP 44-pin TQFP 28-pin QFN 44-pin QFN 28-pin QFN 44-pin QFN  2001-2013 Microchip Technology Inc. DS39582C-page 5

PIC16F87XA FIGURE 1-1: PIC16F873A/876A BLOCK DIAGRAM 13 Data Bus 8 PORTA Program Counter RA0/AN0 Flash RA1/AN1 Program RA2/AN2/VREF-/CVREF Memory 8 Level Stack RAM RA3/AN3/VREF+ File RA4/T0CKI/C1OUT (13-bit) Registers RA5/AN4/SS/C2OUT Program Bus 14 RAM Addr(1) 9 Addr MUX Instruction reg Direct Addr 7 Indirect PORTB 8 Addr RB0/INT FSR reg RB1 RB2 RB3/PGM Status reg 8 RB4 RB5 RB6/PGC Power-up 3 MUX RB7/PGD Timer Instruction Oscillator Decode & Start-up Timer ALU Control Power-on Reset 8 PORTC Timing Watchdog RC0/T1OSO/T1CKI Generation Timer W reg RC1/T1OSI/CCP2 OSC1/CLKI Brown-out RC2/CCP1 OSC2/CLKO Reset RC3/SCK/SCL In-Circuit RC4/SDI/SDA Debugger RC5/SDO Low-Voltage RC6/TX/CK Programming RC7/RX/DT MCLR VDD, VSS Timer0 Timer1 Timer2 10-bit A/D Synchronous Voltage Data EEPROM CCP1,2 Serial Port USART Comparator Reference Device Program Flash Data Memory Data EEPROM PIC16F873A 4K words 192 Bytes 128 Bytes PIC16F876A 8K words 368 Bytes 256 Bytes Note 1: Higher order bits are from the Status register. DS39582C-page 6  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 1-2: PIC16F874A/877A BLOCK DIAGRAM 13 Data Bus 8 PORTA Program Counter RA0/AN0 Flash RA1/AN1 Program RA2/AN2/VREF-/CVREF Memory 8 Level Stack RAM RA3/AN3/VREF+ (13-bit) File RA4/T0CKI/C1OUT Registers RA5/AN4/SS/C2OUT Program Bus 14 RAM Addr(1) 9 PORTB RB0/INT Instruction reg Addr MUX RB1 RB2 Direct Addr 7 8 InAddirderct RB3/PGM RB4 FSR reg RB5 RB6/PGC Status reg RB7/PGD 8 PORTC RC0/T1OSO/T1CKI Power-up 3 MUX RC1/T1OSI/CCP2 Timer RC2/CCP1 RC3/SCK/SCL Instruction Oscillator RC4/SDI/SDA DCecoondtreo l& Start-up Timer ALU RC5/SDO PoRweesre-otn 8 RC6/TX/CK RC7/RX/DT Timing Watchdog W reg Generation Timer PORTD OSC1/CLKI Brown-out RD0/PSP0 OSC2/CLKO Reset RD1/PSP1 In-Circuit RD2/PSP2 Debugger RD3/PSP3 Low-Voltage RD4/PSP4 Programming RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE MCLR VDD, VSS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 Timer0 Timer1 Timer2 10-bit A/D Parallel Slave Port Synchronous Voltage Data EEPROM CCP1,2 Serial Port USART Comparator Reference Device Program Flash Data Memory Data EEPROM PIC16F874A 4K words 192 Bytes 128 Bytes PIC16F877A 8K words 368 Bytes 256 Bytes Note 1: Higher order bits are from the Status register.  2001-2013 Microchip Technology Inc. DS39582C-page 7

PIC16F87XA TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION PDIP, SOIC, QFN I/O/P Buffer Pin Name Description SSOP Pin# Pin# Type Type OSC1/CLKI 9 6 ST/CMOS(3) Oscillator crystal or external clock input. OSC1 I Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. CLKI I External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). OSC2/CLKO 10 7 — Oscillator crystal or clock output. OSC2 O Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. MCLR/VPP 1 26 ST Master Clear (input) or programming voltage (output). MCLR I Master Clear (Reset) input. This pin is an active low Reset to the device. VPP P Programming voltage input. PORTA is a bidirectional I/O port. RA0/AN0 2 27 TTL RA0 I/O Digital I/O. AN0 I Analog input 0. RA1/AN1 3 28 TTL RA1 I/O Digital I/O. AN1 I Analog input 1. RA2/AN2/VREF-/ 4 1 TTL CVREF I/O Digital I/O. RA2 I Analog input 2. AN2 I A/D reference voltage (Low) input. VREF- O Comparator VREF output. CVREF RA3/AN3/VREF+ 5 2 TTL RA3 I/O Digital I/O. AN3 I Analog input 3. VREF+ I A/D reference voltage (High) input. RA4/T0CKI/C1OUT 6 3 ST RA4 I/O Digital I/O – Open-drain when configured as output. T0CKI I Timer0 external clock input. C1OUT O Comparator 1 output. RA5/AN4/SS/C2OUT 7 4 TTL RA5 I/O Digital I/O. AN4 I Analog input 4. SS I SPI slave select input. C2OUT O Comparator 2 output. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. DS39582C-page 8  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED) PDIP, SOIC, QFN I/O/P Buffer Pin Name Description SSOP Pin# Pin# Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT 21 18 TTL/ST(1) RB0 I/O Digital I/O. INT I External interrupt. RB1 22 19 I/O TTL Digital I/O. RB2 23 20 I/O TTL Digital I/O. RB3/PGM 24 21 TTL RB3 I/O Digital I/O. PGM I Low-voltage (single-supply) ICSP programming enable pin. RB4 25 22 I/O TTL Digital I/O. RB5 26 23 I/O TTL Digital I/O. RB6/PGC 27 24 TTL/ST(2) RB6 I/O Digital I/O. PGC I In-circuit debugger and ICSP programming clock. RB7/PGD 28 25 TTL/ST(2) RB7 I/O Digital I/O. PGD I/O In-circuit debugger and ICSP programming data. PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI 11 8 ST RC0 I/O Digital I/O. T1OSO O Timer1 oscillator output. T1CKI I Timer1 external clock input. RC1/T1OSI/CCP2 12 9 ST RC1 I/O Digital I/O. T1OSI I Timer1 oscillator input. CCP2 I/O Capture2 input, Compare2 output, PWM2 output. RC2/CCP1 13 10 ST RC2 I/O Digital I/O. CCP1 I/O Capture1 input, Compare1 output, PWM1 output. RC3/SCK/SCL 14 11 ST RC3 I/O Digital I/O. SCK I/O Synchronous serial clock input/output for SPI mode. SCL I/O Synchronous serial clock input/output for I2C mode. RC4/SDI/SDA 15 12 ST RC4 I/O Digital I/O. SDI I SPI data in. SDA I/O I2C data I/O. RC5/SDO 16 13 ST RC5 I/O Digital I/O. SDO O SPI data out. RC6/TX/CK 17 14 ST RC6 I/O Digital I/O. TX O USART asynchronous transmit. CK I/O USART1 synchronous clock. RC7/RX/DT 18 15 ST RC7 I/O Digital I/O. RX I USART asynchronous receive. DT I/O USART synchronous data. VSS 8, 19 5, 6 P — Ground reference for logic and I/O pins. VDD 20 17 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.  2001-2013 Microchip Technology Inc. DS39582C-page 9

PIC16F87XA TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION PDIP PLCC TQFP QFN I/O/P Buffer Pin Name Description Pin# Pin# Pin# Pin# Type Type OSC1/CLKI 13 14 30 32 ST/CMOS(4) Oscillator crystal or external clock input. OSC1 I Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. CLKI I External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). OSC2/CLKO 14 15 31 33 — Oscillator crystal or clock output. OSC2 O Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. MCLR/VPP 1 2 18 18 ST Master Clear (input) or programming voltage (output). MCLR I Master Clear (Reset) input. This pin is an active low Reset to the device. VPP P Programming voltage input. PORTA is a bidirectional I/O port. RA0/AN0 2 3 19 19 TTL RA0 I/O Digital I/O. AN0 I Analog input 0. RA1/AN1 3 4 20 20 TTL RA1 I/O Digital I/O. AN1 I Analog input 1. RA2/AN2/VREF-/CVREF 4 5 21 21 TTL RA2 I/O Digital I/O. AN2 I Analog input 2. VREF- I A/D reference voltage (Low) input. CVREF O Comparator VREF output. RA3/AN3/VREF+ 5 6 22 22 TTL RA3 I/O Digital I/O. AN3 I Analog input 3. VREF+ I A/D reference voltage (High) input. RA4/T0CKI/C1OUT 6 7 23 23 ST RA4 I/O Digital I/O – Open-drain when configured as output. T0CKI I Timer0 external clock input. C1OUT O Comparator 1 output. RA5/AN4/SS/C2OUT 7 8 24 24 TTL RA5 I/O Digital I/O. AN4 I Analog input 4. SS I SPI slave select input. C2OUT O Comparator 2 output. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. DS39582C-page 10  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED) PDIP PLCC TQFP QFN I/O/P Buffer Pin Name Description Pin# Pin# Pin# Pin# Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 33 36 8 9 TTL/ST(1) RB0 I/O Digital I/O. INT I External interrupt. RB1 34 37 9 10 I/O TTL Digital I/O. RB2 35 38 10 11 I/O TTL Digital I/O. RB3/PGM 36 39 11 12 TTL RB3 I/O Digital I/O. PGM I Low-voltage ICSP programming enable pin. RB4 37 41 14 14 I/O TTL Digital I/O. RB5 38 42 15 15 I/O TTL Digital I/O. RB6/PGC 39 43 16 16 TTL/ST(2) RB6 I/O Digital I/O. PGC I In-circuit debugger and ICSP programming clock. RB7/PGD 40 44 17 17 TTL/ST(2) RB7 I/O Digital I/O. PGD I/O In-circuit debugger and ICSP programming data. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.  2001-2013 Microchip Technology Inc. DS39582C-page 11

PIC16F87XA TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED) PDIP PLCC TQFP QFN I/O/P Buffer Pin Name Description Pin# Pin# Pin# Pin# Type Type PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI 15 16 32 34 ST RC0 I/O Digital I/O. T1OSO O Timer1 oscillator output. T1CKI I Timer1 external clock input. RC1/T1OSI/CCP2 16 18 35 35 ST RC1 I/O Digital I/O. T1OSI I Timer1 oscillator input. CCP2 I/O Capture2 input, Compare2 output, PWM2 output. RC2/CCP1 17 19 36 36 ST RC2 I/O Digital I/O. CCP1 I/O Capture1 input, Compare1 output, PWM1 output. RC3/SCK/SCL 18 20 37 37 ST RC3 I/O Digital I/O. SCK I/O Synchronous serial clock input/output for SPI mode. SCL I/O Synchronous serial clock input/output for I2C mode. RC4/SDI/SDA 23 25 42 42 ST RC4 I/O Digital I/O. SDI I SPI data in. SDA I/O I2C data I/O. RC5/SDO 24 26 43 43 ST RC5 I/O Digital I/O. SDO O SPI data out. RC6/TX/CK 25 27 44 44 ST RC6 I/O Digital I/O. TX O USART asynchronous transmit. CK I/O USART1 synchronous clock. RC7/RX/DT 26 29 1 1 ST RC7 I/O Digital I/O. RX I USART asynchronous receive. DT I/O USART synchronous data. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. DS39582C-page 12  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED) PDIP PLCC TQFP QFN I/O/P Buffer Pin Name Description Pin# Pin# Pin# Pin# Type Type PORTD is a bidirectional I/O port or Parallel Slave Port when interfacing to a microprocessor bus. RD0/PSP0 19 21 38 38 ST/TTL(3) RD0 I/O Digital I/O. PSP0 I/O Parallel Slave Port data. RD1/PSP1 20 22 39 39 ST/TTL(3) RD1 I/O Digital I/O. PSP1 I/O Parallel Slave Port data. RD2/PSP2 21 23 40 40 ST/TTL(3) RD2 I/O Digital I/O. PSP2 I/O Parallel Slave Port data. RD3/PSP3 22 24 41 41 ST/TTL(3) RD3 I/O Digital I/O. PSP3 I/O Parallel Slave Port data. RD4/PSP4 27 30 2 2 ST/TTL(3) RD4 I/O Digital I/O. PSP4 I/O Parallel Slave Port data. RD5/PSP5 28 31 3 3 ST/TTL(3) RD5 I/O Digital I/O. PSP5 I/O Parallel Slave Port data. RD6/PSP6 29 32 4 4 ST/TTL(3) RD6 I/O Digital I/O. PSP6 I/O Parallel Slave Port data. RD7/PSP7 30 33 5 5 ST/TTL(3) RD7 I/O Digital I/O. PSP7 I/O Parallel Slave Port data. PORTE is a bidirectional I/O port. RE0/RD/AN5 8 9 25 25 ST/TTL(3) RE0 I/O Digital I/O. RD I Read control for Parallel Slave Port. AN5 I Analog input 5. RE1/WR/AN6 9 10 26 26 ST/TTL(3) RE1 I/O Digital I/O. WR I Write control for Parallel Slave Port. AN6 I Analog input 6. RE2/CS/AN7 10 11 27 27 ST/TTL(3) RE2 I/O Digital I/O. CS I Chip select control for Parallel Slave Port. AN7 I Analog input 7. VSS 12, 31 13, 34 6, 29 6, 30, P — Ground reference for logic and I/O pins. 31 VDD 11, 32 12, 35 7, 28 7, 8, P — Positive supply for logic and I/O pins. 28, 29 NC — 1, 17, 12,13, 13 — — These pins are not internally connected. These pins 28, 40 33, 34 should be left unconnected. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.  2001-2013 Microchip Technology Inc. DS39582C-page 13

PIC16F87XA NOTES: DS39582C-page 14  2001-2013 Microchip Technology Inc.

PIC16F87XA 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization There are three memory blocks in each of the The PIC16F87XA devices have a 13-bit program coun- PIC16F87XA devices. The program memory and data ter capable of addressing an 8K word x 14 bit program memory have separate buses so that concurrent memory space. The PIC16F876A/877A devices have access can occur and is detailed in this section. The 8K words x 14 bits of Flash program memory, while EEPROM data memory block is detailed in Section3.0 PIC16F873A/874A devices have 4Kwords x 14 bits. “Data EEPROM and Flash Program Memory”. Accessing a location above the physically implemented address will cause a wraparound. Additional information on device memory may be found in the PIC® Mid-Range MCU Family Reference Manual The Reset vector is at 0000h and the interrupt vector is (DS33023). at 0004h. FIGURE 2-2: PIC16F873A/874A FIGURE 2-1: PIC16F876A/877A PROGRAM MEMORY MAP PROGRAM MEMORY MAP AND STACK AND STACK PC<12:0> PC<12:0> CALL, RETURN 13 RETFIE, RETLW CALL, RETURN 13 RETFIE, RETLW Stack Level 1 Stack Level 1 Stack Level 2 Stack Level 2 Stack Level 8 Stack Level 8 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h Interrupt Vector 0004h 0005h 0005h On-Chip Page 0 07FFh Page 0 Program 07FFh Memory 0800h Page 1 0800h Page 1 0FFFh On-Chip 0FFFh 1000h Program Memory 1000h Page 2 17FFh 1800h Page 3 1FFFh 1FFFh  2001-2013 Microchip Technology Inc. DS39582C-page 15

PIC16F87XA 2.2 Data Memory Organization Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special The data memory is partitioned into multiple banks Function Registers. Above the Special Function Regis- which contain the General Purpose Registers and the ters are General Purpose Registers, implemented as Special Function Registers. Bits RP1 (Status<6>) and static RAM. All implemented banks contain Special RP0 (Status<5>) are the bank select bits. Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. RP1:RP0 Bank Note: The EEPROM data memory description can 00 0 be found in Section3.0 “Data EEPROM 01 1 and Flash Program Memory” of this data 10 2 sheet. 11 3 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly, through the File Select Register (FSR). DS39582C-page 16  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 2-3: PIC16F876A/877A REGISTER FILE MAP File File File File Address Address Address Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h 107h 187h PORTD(1) 08h TRISD(1) 88h 108h 188h PORTE(1) 09h TRISE(1) 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDATA 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved(2) 18Eh TMR1H 0Fh 8Fh EEADRH 10Fh Reserved(2) 18Fh T1CON 10h 90h 110h 190h TMR2 11h SSPCON2 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPR1L 15h 95h 115h 195h CCPR1H 16h 96h 116h 196h CCP1CON 17h 97h General 117h General 197h Purpose Purpose RCSTA 18h TXSTA 98h Register 118h Register 198h TXREG 19h SPBRG 99h 16 Bytes 119h 16 Bytes 199h RCREG 1Ah 9Ah 11Ah 19Ah CCPR2L 1Bh 9Bh 11Bh 19Bh CCPR2H 1Ch CMCON 9Ch 11Ch 19Ch CCP2CON 1Dh CVRCON 9Dh 11Dh 19Dh ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh 20h A0h 120h 1A0h General General General Purpose Purpose Purpose General Register Register Register Purpose Register 80 Bytes 80 Bytes 80 Bytes 96 Bytes EFh 16Fh 1EFh accesses F0h accesses 170h accesses 1F0h 70h-7Fh 70h-7Fh 70h - 7Fh 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. * Not a physical register. Note 1: These registers are not implemented on the PIC16F876A. 2: These registers are reserved; maintain these registers clear.  2001-2013 Microchip Technology Inc. DS39582C-page 17

PIC16F87XA FIGURE 2-4: PIC16F873A/874A REGISTER FILE MAP File File File File Address Address Address Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h 107h 187h PORTD(1) 08h TRISD(1) 88h 108h 188h PORTE(1) 09h TRISE(1) 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDATA 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved(2) 18Eh TMR1H 0Fh 8Fh EEADRH 10Fh Reserved(2) 18Fh T1CON 10h 90h 110h 190h TMR2 11h SSPCON2 91h T2CON 12h PR2 92h SSPBUF 13h SSPADD 93h SSPCON 14h SSPSTAT 94h CCPR1L 15h 95h CCPR1H 16h 96h CCP1CON 17h 97h RCSTA 18h TXSTA 98h TXREG 19h SPBRG 99h RCREG 1Ah 9Ah CCPR2L 1Bh 9Bh CCPR2H 1Ch CMCON 9Ch CCP2CON 1Dh CVRCON 9Dh ADRESH 1Eh ADRESL 9Eh ADCON0 1Fh ADCON1 9Fh 120h 1A0h 20h A0h General General Purpose Purpose accesses accesses Register Register 20h-7Fh A0h - FFh 96 Bytes 96 Bytes 16Fh 1EFh 170h 1F0h 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. * Not a physical register. Note 1: These registers are not implemented on the PIC16F873A. 2: These registers are reserved; maintain these registers clear. DS39582C-page 18  2001-2013 Microchip Technology Inc.

PIC16F87XA 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers The Special Function Registers are registers used by associated with the core functions are described in the CPU and peripheral modules for controlling the detail in this section. Those related to the operation of desired operation of the device. These registers are the peripheral features are described in detail in the implemented as static RAM. A list of these registers is peripheral features section. given in Table2-1. TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY Value on: Details Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: Bank 0 00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150 01h TMR0 Timer0 Module Register xxxx xxxx 55, 150 02h(3) PCL Program Counter (PC) Least Significant Byte 0000 0000 30, 150 03h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 22, 150 04h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 31, 150 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 43, 150 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 45, 150 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 47, 150 08h(4) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx 48, 150 09h(4) PORTE — — — — — RE2 RE1 RE0 ---- -xxx 49, 150 0Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150 0Bh(3) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150 0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 26, 150 0Dh PIR2 — CMIF — EEIF BCLIF — — CCP2IF -0-0 0--0 28, 150 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 60, 150 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 60, 150 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 57, 150 11h TMR2 Timer2 Module Register 0000 0000 62, 150 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 61, 150 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 79, 150 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 82, 82, 150 15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx 63, 150 16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx 63, 150 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 64, 150 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 112, 150 19h TXREG USART Transmit Data Register 0000 0000 118, 150 1Ah RCREG USART Receive Data Register 0000 0000 118, 150 1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx 63, 150 1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx 63, 150 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 64, 150 1Eh ADRESH A/D Result Register High Byte xxxx xxxx 133, 150 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 127, 150 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’. 5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.  2001-2013 Microchip Technology Inc. DS39582C-page 19

PIC16F87XA TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on: Details Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: Bank 1 80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23, 150 82h(3) PCL Program Counter (PC) Least Significant Byte 0000 0000 30, 150 83h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 22, 150 84h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 31, 150 85h TRISA — — PORTA Data Direction Register --11 1111 43, 150 86h TRISB PORTB Data Direction Register 1111 1111 45, 150 87h TRISC PORTC Data Direction Register 1111 1111 47, 150 88h(4) TRISD PORTD Data Direction Register 1111 1111 48, 151 89h(4) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 50, 151 8Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150 8Bh(3) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150 8Ch PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 25, 151 8Dh PIE2 — CMIE — EEIE BCLIE — — CCP2IE -0-0 0--0 27, 151 8Eh PCON — — — — — — POR BOR ---- --qq 29, 151 8Fh — Unimplemented — — 90h — Unimplemented — — 91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 83, 151 92h PR2 Timer2 Period Register 1111 1111 62, 151 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 79, 151 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 79, 151 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 111, 151 99h SPBRG Baud Rate Generator Register 0000 0000 113, 151 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 135, 151 9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 141, 151 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 133, 151 9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 128, 151 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’. 5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices. DS39582C-page 20  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on: Details Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: Bank 2 100h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150 101h TMR0 Timer0 Module Register xxxx xxxx 55, 150 102h(3) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30, 150 103h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 22, 150 104h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 31, 150 105h — Unimplemented — — 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 45, 150 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150 10Bh(3) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150 10Ch EEDATA EEPROM Data Register Low Byte xxxx xxxx 39, 151 10Dh EEADR EEPROM Address Register Low Byte xxxx xxxx 39, 151 10Eh EEDATH — — EEPROM Data Register High Byte --xx xxxx 39, 151 10Fh EEADRH — — — —(5) EEPROM Address Register High Byte ---- xxxx 39, 151 Bank 3 180h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23, 150 182h(3) PCL Program Counter (PC) Least Significant Byte 0000 0000 30, 150 183h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 22, 150 184h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 31, 150 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 45, 150 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150 18Bh(3) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150 18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 34, 151 18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 39, 151 18Eh — Reserved; maintain clear 0000 0000 — 18Fh — Reserved; maintain clear 0000 0000 — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’. 5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.  2001-2013 Microchip Technology Inc. DS39582C-page 21

PIC16F87XA 2.2.2.1 Status Register For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the Status register as The Status register contains the arithmetic status of the 000u u1uu (where u = unchanged). ALU, the Reset status and the bank select bits for data memory. It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the The Status register can be the destination for any Status register because these instructions do not affect instruction, as with any other register. If the Status reg- the Z, C or DC bits from the Status register. For other ister is the destination for an instruction that affects the instructions not affecting any status bits, see Z, DC or C bits, then the write to these three bits is dis- Section15.0 “Instruction Set Summary”. abled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not Note: The C and DC bits operate as a borrow writable, therefore, the result of an instruction with the and digit borrow bit, respectively, in sub- Status register as destination may be different than traction. See the SUBLW and SUBWF intended. instructions for examples. REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) Each bank is 128 bytes. bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high, or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39582C-page 22  2001-2013 Microchip Technology Inc.

PIC16F87XA 2.2.2.2 OPTION_REG Register Note: To achieve a 1:1 prescaler assignment for The OPTION_REG Register is a readable and writable the TMR0 register, assign the prescaler to register, which contains various control bits to configure the Watchdog Timer. the TMR0 prescaler/WDT postscaler (single assign- able register known also as the prescaler), the external INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device  2001-2013 Microchip Technology Inc. DS39582C-page 23

PIC16F87XA 2.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt The INTCON register is a readable and writable regis- condition occurs regardless of the state of its ter, which contains various enable and flag bits for the corresponding enable bit or the global TMR0 register overflow, RB port change and external enable bit, GIE (INTCON<7>). User software RB0/INT pin interrupts. should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF bit 7 bit 0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software). 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39582C-page 24  2001-2013 Microchip Technology Inc.

PIC16F87XA 2.2.2.4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to The PIE1 register contains the individual enable bits for enable any peripheral interrupt. the peripheral interrupts. REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt Note1: PSPIE is reserved on PIC16F873A/876A devices; always maintain this bit clear. bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39582C-page 25

PIC16F87XA 2.2.2.5 PIR1 Register Note: Interrupt flag bits are set when an interrupt The PIR1 register contains the individual flag bits for condition occurs regardless of the state of its the peripheral interrupts. corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred Note1: PSPIF is reserved on PIC16F873A/876A devices; always maintain this bit clear. bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The SSP interrupt condition has occurred and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are: • SPI – A transmission/reception has taken place. • I2C Slave – A transmission/reception has taken place. • I2C Master - A transmission/reception has taken place. - The initiated Start condition was completed by the SSP module. - The initiated Stop condition was completed by the SSP module. - The initiated Restart condition was completed by the SSP module. - The initiated Acknowledge condition was completed by the SSP module. - A Start condition occurred while the SSP module was Idle (multi-master system). - A Stop condition occurred while the SSP module was Idle (multi-master system). 0 = No SSP interrupt condition has occurred bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39582C-page 26  2001-2013 Microchip Technology Inc.

PIC16F87XA 2.2.2.6 PIE2 Register Note: Bit PEIE (INTCON<6>) must be set to The PIE2 register contains the individual enable bits for enable any peripheral interrupt. the CCP2 peripheral interrupt, the SSP bus collision interrupt, EEPROM write operation interrupt and the comparator interrupt. REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh) U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — CMIE — EEIE BCLIE — — CCP2IE bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disable the comparator interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit 1 = Enable EEPROM write interrupt 0 = Disable EEPROM write interrupt bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enable bus collision interrupt 0 = Disable bus collision interrupt bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39582C-page 27

PIC16F87XA 2.2.2.7 PIR2 Register Note: Interrupt flag bits are set when an interrupt The PIR2 register contains the flag bits for the CCP2 condition occurs regardless of the state of interrupt, the SSP bus collision interrupt, EEPROM its corresponding enable bit or the global write operation interrupt and the comparator interrupt. enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh) U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — CMIF — EEIF BCLIF — — CCP2IF bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIF: Comparator Interrupt Flag bit 1 = The comparator input has changed (must be cleared in software) 0 = The comparator input has not changed bit 5 Unimplemented: Read as ‘0’ bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision has occurred in the SSP when configured for I2C Master mode 0 = No bus collision has occurred bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39582C-page 28  2001-2013 Microchip Technology Inc.

PIC16F87XA 2.2.2.8 PCON Register Note: BOR is unknown on Power-on Reset. It The Power Control (PCON) register contains flag bits must be set by the user and checked on to allow differentiation between a Power-on Reset subsequent Resets to see if BOR is clear, (POR), a Brown-out Reset (BOR), a Watchdog Reset indicating a brown-out has occurred. The (WDT) and an external MCLR Reset. BOR status bit is a “don’t care” and is not predictable if the brown-out circuit is dis- abled (by clearing the BODEN bit in the configuration word). REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1 — — — — — — POR BOR bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39582C-page 29

PIC16F87XA 2.3 PCL and PCLATH Note1: There are no status bits to indicate stack The Program Counter (PC) is 13 bits wide. The low overflow or stack underflow conditions. byte comes from the PCL register which is a readable 2: There are no instructions/mnemonics and writable register. The upper bits (PC<12:8>) are called PUSH or POP. These are actions not readable, but are indirectly writable through the that occur from the execution of the CALL, PCLATH register. On any Reset, the upper bits of the RETURN, RETLW and RETFIE instructions PC will be cleared. Figure2-5 shows the two situations or the vectoring to an interrupt address. for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL 2.4 Program Memory Paging (PCLATH<4:0>  PCH). The lower example in the figure shows how the PC is loaded during a CALL or All PIC16F87XA devices are capable of addressing a GOTO instruction (PCLATH<4:3>  PCH). continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of FIGURE 2-5: LOADING OF PC IN address to allow branching within any 2K program DIFFERENT SITUATIONS memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruc- PCH PCL tion, the user must ensure that the page select bits are 12 8 7 0 Instruction with programmed so that the desired program memory PC PCL as page is addressed. If a return from a CALL instruction Destination PCLATH<4:0> 8 (or interrupt) is executed, the entire 13-bit PC is popped 5 ALU off the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the RETURN PCLATH instructions (which POPs the address from the stack). PCH PCL Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE 12 11 10 8 7 0 instruction is executed. The user must PC GOTO,CALL rewrite the contents of the PCLATH regis- 2 PCLATH<4:3> 11 ter for any subsequent subroutine calls or Opcode <10:0> GOTO instructions. PCLATH Example2-1 shows the calling of a subroutine in page1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt 2.3.1 COMPUTED GOTO Service Routine (if interrupts are used). A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a EXAMPLE 2-1: CALL OF A SUBROUTINE table read using a computed GOTO method, care IN PAGE 1 FROM PAGE 0 should be exercised if the table location crosses a PCL ORG 0x500 memory boundary (each 256-byte block). Refer to the BCF PCLATH,4 application note, AN556, “Implementing a Table Read” BSF PCLATH,3 ;Select page 1 (DS00556). ;(800h-FFFh) CALL SUB1_P1 ;Call subroutine in 2.3.2 STACK : ;page 1 (800h-FFFh) : The PIC16F87XA family has an 8-level deep x 13-bit ORG 0x900 ;page 1 (800h-FFFh) wide hardware stack. The stack space is not part of SUB1_P1 either program or data space and the stack pointer is not : ;called subroutine readable or writable. The PC is PUSHed onto the stack ;page 1 (800h-FFFh) when a CALL instruction is executed, or an interrupt : causes a branch. The stack is POP’ed in the event of a RETURN ;return to RETURN, RETLW or a RETFIE instruction execution. ;Call subroutine ;in page 0 PCLATH is not affected by a PUSH or POP operation. ;(000h-7FFh) The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). DS39582C-page 30  2001-2013 Microchip Technology Inc.

PIC16F87XA 2.5 Indirect Addressing, INDF and A simple program to clear RAM locations 20h-2Fh FSR Registers using indirect addressing is shown in Example2-2. The INDF register is not a physical register. Addressing EXAMPLE 2-2: INDIRECT ADDRESSING the INDF register will cause indirect addressing. MOVLW 0x20 ;initialize pointer Indirect addressing is possible by using the INDF reg- MOVWF FSR ;to RAM ister. Any instruction using the INDF register actually NEXT CLRF INDF ;clear INDF register accesses the register pointed to by the File Select Reg- INCF FSR,F ;inc pointer BTFSS FSR,4 ;all done? ister, FSR. Reading the INDF register itself, indirectly GOTO NEXT ;no clear next (FSR = 0) will read 00h. Writing to the INDF register CONTINUE indirectly results in a no operation (although status bits : ;yes continue may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (Status<7>) as shown in Figure2-6. FIGURE 2-6: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1:RP0 6 From Opcode 0 IRP 7 FSR Register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 80h 100h 180h Data Memory(1) 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note1: For register file map detail, see Figure2-3.  2001-2013 Microchip Technology Inc. DS39582C-page 31

PIC16F87XA NOTES: DS39582C-page 32  2001-2013 Microchip Technology Inc.

PIC16F87XA 3.0 DATA EEPROM AND FLASH 3.1 EEADR and EEADRH PROGRAM MEMORY The EEADRH:EEADR register pair can address up to a maximum of 256 bytes of data EEPROM or up to a The data EEPROM and Flash program memory is read- maximum of 8K words of program EEPROM. When able and writable during normal operation (over the full selecting a data address value, only the LSByte of the VDD range). This memory is not directly mapped in the address is written to the EEADR register. When select- register file space. Instead, it is indirectly addressed ing a program address value, the MSByte of the through the Special Function Registers. There are six address is written to the EEADRH register and the SFRs used to read and write this memory: LSByte is written to the EEADR register. • EECON1 If the device contains less memory than the full address • EECON2 reach of the address register pair, the Most Significant • EEDATA bits of the registers are not implemented. For example, • EEDATH if the device has 128 bytes of data EEPROM, the Most • EEADR Significant bit of EEADR is not implemented on access • EEADRH to data EEPROM. When interfacing to the data memory block, EEDATA 3.2 EECON1 and EECON2 Registers holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. EECON1 is the control register for memory accesses. These devices have 128 or 256 bytes of data EEPROM Control bit, EEPGD, determines if the access will be a (depending on the device), with an address range from program or data memory access. When clear, as it is 00h to FFh. On devices with 128 bytes, addresses from when reset, any subsequent operations will operate on 80h to FFh are unimplemented and will wraparound to the data memory. When set, any subsequent the beginning of data EEPROM memory. When writing operations will operate on the program memory. to unimplemented locations, the on-chip charge pump will be turned off. Control bits, RD and WR, initiate read and write or erase, respectively. These bits cannot be cleared, only When interfacing the program memory block, the set, in software. They are cleared in hardware at com- EEDATA and EEDATH registers form a two-byte word pletion of the read or write operation. The inability to that holds the 14-bit data for read/write and the EEADR clear the WR bit in software prevents the accidental, and EEADRH registers form a two-byte word that holds premature termination of a write operation. the 13-bit address of the program memory location being accessed. These devices have 4 or 8K words of The WREN bit, when set, will allow a write or erase program Flash, with an address range from 0000h to operation. On power-up, the WREN bit is clear. The 0FFFh for the PIC16F873A/874A and 0000h to 1FFFh WRERR bit is set when a write (or erase) operation is for the PIC16F876A/877A. Addresses above the range interrupted by a MCLR or a WDT Time-out Reset dur- of the respective device will wraparound to the ing normal operation. In these situations, following beginning of program memory. Reset, the user can check the WRERR bit and rewrite the location. The data and address will be unchanged The EEPROM data memory allows single-byte read and in the EEDATA and EEADRregisters. write. The Flash program memory allows single-word reads and four-word block writes. Program memory Interrupt flag bit, EEIF in the PIR2 register, is set when write operations automatically perform an erase-before- the write is complete. It must be cleared in software. write on blocks of four words. A byte write in data EECON2 is not a physical register. Reading EECON2 EEPROM memory automatically erases the location will read all ‘0’s. The EECON2 register is used and writes the new data (erase-before-write). exclusively in the EEPROM write sequence. The write time is controlled by an on-chip timer. The Note: The self-programming mechanism for Flash write/erase voltages are generated by an on-chip program memory has been changed. On charge pump, rated to operate over the voltage range previous PIC16F87X devices, Flash pro- of the device for byte or word operations. gramming was done in single-word erase/ When the device is code-protected, the CPU may write cycles. The newer PIC18F87XA continue to read and write the data EEPROM memory. devices use a four-word erase/write Depending on the settings of the write-protect bits, the cycle.See Section3.6 “Writing to Flash device may or may not be able to write certain blocks Program Memory” for more information. of the program memory; however, reads of the program memory are allowed. When code-protected, the device programmer can no longer access data or program memory; this does NOT inhibit internal reads or writes.  2001-2013 Microchip Technology Inc. DS39582C-page 33

PIC16F87XA REGISTER 3-1: EECON1 REGISTER (ADDRESS 18Ch) R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — — WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress. bit 6-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during normal operation) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39582C-page 34  2001-2013 Microchip Technology Inc.

PIC16F87XA 3.3 Reading Data EEPROM Memory The steps to write to EEPROM data memory are: 1. If step 10 is not implemented, check the WR bit To read a data memory location, the user must write the to see if a write is in progress. address to the EEADR register, clear the EEPGD con- trol bit (EECON1<7>) and then set control bit RD 2. Write the address to EEADR. Make sure that the (EECON1<0>). The data is available in the very next address is not larger than the memory size of cycle in the EEDATA register; therefore, it can be read the device. in the next instruction (see Example3-1). EEDATA will 3. Write the 8-bit data value to be programmed in hold this value until another read or until it is written to the EEDATA register. by the user (during a write operation). 4. Clear the EEPGD bit to point to EEPROM data The steps to reading the EEPROM data memory are: memory. 5. Set the WREN bit to enable program operations. 1. Write the address to EEADR. Make sure that the address is not larger than the memory size of 6. Disable interrupts (if enabled). the device. 7. Execute the special five instruction sequence: 2. Clear the EEPGD bit to point to EEPROM data • Write 55h to EECON2 in two steps (first memory. to W, then to EECON2) 3. Set the RD bit to start the read operation. • Write AAh to EECON2 in two steps (first 4. Read the data from the EEDATA register. to W, then to EECON2) • Set the WR bit EXAMPLE 3-1: DATA EEPROM READ 8. Enable interrupts (if using interrupts). BSF STATUS,RP1 ; 9. Clear the WREN bit to disable program BCF STATUS,RP0 ; Bank 2 operations. MOVF DATA_EE_ADDR,W ; Data Memory 10. At the completion of the write cycle, the WR bit MOVWF EEADR ; Address to read is cleared and the EEIF interrupt flag bit is set. BSF STATUS,RP0 ; Bank 3 (EEIF must be cleared by firmware.) If step 1 is BCF EECON1,EEPGD ; Point to Data not implemented, then firmware should check ; memory BSF EECON1,RD ; EE Read for EEIF to be set, or WR to clear, to indicate the BCF STATUS,RP0 ; Bank 2 end of the program cycle. MOVF EEDATA,W ; W = EEDATA EXAMPLE 3-2: DATA EEPROM WRITE BSF STATUS,RP1 ; 3.4 Writing to Data EEPROM Memory BSF STATUS,RP0 To write an EEPROM data location, the user must first BTFSC EECON1,WR ;Wait for write GOTO $-1 ;to complete write the address to the EEADR register and the data to BCF STATUS, RP0 ;Bank 2 the EEDATA register. Then the user must follow a MOVF DATA_EE_ADDR,W ;Data Memory specific write sequence to initiate the write for each byte. MOVWF EEADR ;Address to write The write will not initiate if the write sequence is not MOVF DATA_EE_DATA,W ;Data Memory Value exactly followed (write 55h to EECON2, write AAh to MOVWF EEDATA ;to write EECON2, then set WR bit) for each byte. We strongly BSF STATUS,RP0 ;Bank 3 BCF EECON1,EEPGD ;Point to DATA recommend that interrupts be disabled during this ;memory codesegment (see Example3-2). BSF EECON1,WREN ;Enable writes Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental BCF INTCON,GIE ;Disable INTs. writes to data EEPROM due to errant (unexpected) MOVLW 55h ; ckueopeddpea tietnhxgee cEWuEtRioPEnR NO(i .Meb.i.t, lcTolshetea rp rWaotgR raEalmlN t sim)b.i etT shi,s e e nuxcoseet pr cts lehwaohrueelndd RequiredSequence MMMBOOOSVVVFWLWFWF EEAEEEAEChCCOOONNN221,WR ;;;; WWSrreiittt eeW R5A 5Abhhit to byhardware ;begin write After a write sequence has been initiated, clearing the BSF INTCON,GIE ;Enable INTs. WREN bit will not affect this write cycle. The WR bit will BCF EECON1,WREN ;Disable writes be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.  2001-2013 Microchip Technology Inc. DS39582C-page 35

PIC16F87XA 3.5 Reading Flash Program Memory ing the “BSF EECON1,RD” instruction to be ignored. The data is available in the very next cycle in the To read a program memory location, the user must write EEDATA and EEDATH registers; therefore, it can be two bytes of the address to the EEADR and EEADRH read as two bytes in the following instructions. EEDATA registers, set the EEPGD control bit (EECON1<7>) and and EEDATH registers will hold this value until another then set control bit RD (EECON1<0>). Once the read read or until it is written to by the user (during a write control bit is set, the program memory Flash controller operation). will use the next two instruction cycles to read the data. This causes these two instructions immediately follow- EXAMPLE 3-3: FLASH PROGRAM READ BSF STATUS, RP1 ; BCF STATUS, RP0 ; Bank 2 MOVLW MS_PROG_EE_ADDR ; MOVWF EEADRH ; MS Byte of Program Address to read MOVLW LS_PROG_EE_ADDR ; MOVWF EEADR ; LS Byte of Program Address to read BSF STATUS, RP0 ; Bank 3 BSF EECON1, EEPGD ; Point to PROGRAM memory BSF EECON1, RD ; EE Read RequiredSequence ; NNOOPP ; Any instructions here are ignored as program ; memory is read in second cycle after BSF EECON1,RD ; BCF STATUS, RP0 ; Bank 2 MOVF EEDATA, W ; W = LS Byte of Program EEDATA MOVWF DATAL ; MOVF EEDATH, W ; W = MS Byte of Program EEDATA MOVWF DATAH ; DS39582C-page 36  2001-2013 Microchip Technology Inc.

PIC16F87XA 3.6 Writing to Flash Program Memory To transfer data from the buffer registers to the program memory, the EEADR and EEADRH must point to the last Flash program memory may only be written to if the location in the four-word block (EEADR<1:0> = 11). destination address is in a segment of memory that is Then the following sequence of events must be not write-protected, as defined in bits WRT1:WRT0 of executed: the device configuration word (Register14-1). Flash 1. Set the EEPGD control bit (EECON1<7>). program memory must be written in four-word blocks. A block consists of four words with sequential addresses, 2. Write 55h, then AAh, to EECON2 (Flash with a lower boundary defined by an address, where programming sequence). EEADR<1:0> = 00. At the same time, all block writes to 3. Set control bit WR (EECON1<1>) to begin the program memory are done as erase and write opera- write operation. tions. The write operation is edge-aligned and cannot The user must follow the same specific sequence to ini- occur across boundaries. tiate the write for each word in the program block, writ- To write program data, it must first be loaded into the ing each program word in sequence (00,01,10,11). buffer registers (see Figure3-1). This is accomplished When the write is performed on the last word by first writing the destination address to EEADR and (EEADR<1:0> = 11), the block of four words are EEADRH and then writing the data to EEDATA and automatically erased and the contents of the buffer EEDATH. After the address and data have been set up, registers are written into the program memory. then the following sequence of events must be After the “BSF EECON1,WR” instruction, the processor executed: requires two cycles to set up the erase/write operation. 1. Set the EEPGD control bit (EECON1<7>). The user must place two NOP instructions after the WR 2. Write 55h, then AAh, to EECON2 (Flash bit is set. Since data is being written to buffer registers, programming sequence). the writing of the first three words of the block appears to occur immediately. The processor will halt internal 3. Set the WR control bit (EECON1<1>). operations for the typical 4ms, only during the cycle in All four buffer register locations MUST be written to with which the erase takes place (i.e., the last word of the correct data. If only one, two or three words are being four-word block). This is not Sleep mode as the clocks written to in the block of four words, then a read from and peripherals will continue to run. After the write the program memory location(s) not being written to cycle, the processor will resume operation with the third must be performed. This takes the data from the pro- instruction after the EECON1 write instruction. If the gram location(s) not being written and loads it into the sequence is performed to any other location, the action EEDATA and EEDATH registers. Then the sequence of is ignored. events to transfer data to the buffer registers must be executed. FIGURE 3-1: BLOCK WRITES TO FLASH PROGRAM MEMORY 7 5 0 7 0 Four words of EEDATH EEDATA Flash are erased, then all buffers 6 8 are transferred to Flash automatically First word of block after this word to be written is written 14 14 14 14 EEADR<1:0> = 00 EEADR<1:0> = 01 EEADR<1:0> = 10 EEADR<1:0> = 11 Buffer Register Buffer Register Buffer Register Buffer Register Program Memory  2001-2013 Microchip Technology Inc. DS39582C-page 37

PIC16F87XA An example of the complete four-word write sequence is shown in Example3-4. The initial address is loaded into the EEADRH:EEADR register pair; the four words of data are loaded using indirect addressing. EXAMPLE 3-4: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; ; 1. A valid starting address (the least significant bits = ‘00’)is loaded in ADDRH:ADDRL ; 2. The 8 bytes of data are loaded, starting at the address in DATADDR ; 3. ADDRH, ADDRL and DATADDR are all located in shared data memory 0x70 - 0x7f ; BSF STATUS,RP1 ; BCF STATUS,RP0 ; Bank 2 MOVF ADDRH,W ; Load initial address MOVWF EEADRH ; MOVF ADDRL,W ; MOVWF EEADR ; MOVF DATAADDR,W ; Load initial data address MOVWF FSR ; LOOP MOVF INDF,W ; Load first data byte into lower MOVWF EEDATA ; INCF FSR,F ; Next byte MOVF INDF,W ; Load second data byte into upper MOVWF EEDATH ; INCF FSR,F ; BSF STATUS,RP0 ; Bank 3 BSF EECON1,EEPGD ; Point to program memory BSF EECON1,WREN ; Enable writes BCF INTCON,GIE ; Disable interrupts (if using) MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h MOVLW AAh ; RequiredSequence MBNOSOVFPWF EEEECCOONN12,WR ;;; AWSnreyit t ieWn RsA tAbrhiutc ttioo nbse ghienr ew rairtee ignored as processor ; halts to begin write sequence NOP ; processor will stop here and wait for write complete ; after write processor continues with 3rd instruction BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts (if using) BCF STATUS,RP0 ; Bank 2 INCF EEADR,F ; Increment address MOVF EEADR,W ; Check if lower two bits of address are ‘00’ ANDLW 0x03 ; Indicates when four words have been programmed XORLW 0x03 ; BTFSC STATUS,Z ; Exit if more than four words, GOTO LOOP ; Continue if less than four words DS39582C-page 38  2001-2013 Microchip Technology Inc.

PIC16F87XA 3.7 Protection Against Spurious Write 3.8 Operation During Code-Protect There are conditions when the device should not write When the data EEPROM is code-protected, the micro- to the data EEPROM or Flash program memory. To controller can read and write to the EEPROM normally. protect against spurious writes, various mechanisms However, all external access to the EEPROM is have been built-in. On power-up, WREN is cleared. disabled. External write access to the program memory Also, the Power-up Timer (72ms duration) prevents an is also disabled. EEPROM write. When program memory is code-protected, the microcon- The write initiate sequence and the WREN bit together troller can read and write to program memory normally, help prevent an accidental write during brown-out, as well as execute instructions. Writes by the device may power glitch or software malfunction. be selectively inhibited to regions of the memory depend- ing on the setting of bits WR1:WR0 of the configuration word (see Section14.1 “Configuration Bits” for addi- tional information). External access to the memory is also disabled. TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND FLASH PROGRAM MEMORIES Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on all other Reset Resets 10Ch EEDATA EEPROM/Flash Data Register Low Byte xxxx xxxx uuuu uuuu 10Dh EEADR EEPROM/Flash Address Register Low Byte xxxx xxxx uuuu uuuu 10Eh EEDATH — — EEPROM/Flash Data Register High Byte xxxx xxxx ---0 q000 10Fh EEADRH — — — EEPROM/Flash Address Register High Byte xxxx xxxx ---- ---- 18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 ---0 q000 18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---- 0Dh PIR2 — CMIF — EEIF BCLIF — — CCP2IF -0-0 0--0 -0-0 0--0 8Dh PIE2 — CMIE — EEIE BCLIE — — CCP2IE -0-0 0--0 -0-0 0--0 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends upon condition. Shaded cells are not used by data EEPROM or Flash program memory.  2001-2013 Microchip Technology Inc. DS39582C-page 39

PIC16F87XA NOTES: DS39582C-page 40  2001-2013 Microchip Technology Inc.

PIC16F87XA 4.0 I/O PORTS EXAMPLE 4-1: INITIALIZING PORTA BCF STATUS, RP0 ; Some pins for these I/O ports are multiplexed with an BCF STATUS, RP1 ; Bank0 alternate function for the peripheral features on the CLRF PORTA ; Initialize PORTA by device. In general, when a peripheral is enabled, that ; clearing output pin may not be used as a general purpose I/O pin. ; data latches BSF STATUS, RP0 ; Select Bank 1 Additional information on I/O ports may be found in the PIC® Mid-Range Reference Manual (DS33023). MOVLW 0x06 ; Configure all pins MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to 4.1 PORTA and the TRISA Register ; initialize data ; direction PORTA is a 6-bit wide, bidirectional port. The corre- MOVWF TRISA ; Set RA<3:0> as inputs sponding data direction register is TRISA. Setting a ; RA<5:4> as outputs TRISA bit (= 1) will make the corresponding PORTA pin ; TRISA<7:6>are always an input (i.e., put the corresponding output driver in a ; read as '0'. High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). FIGURE 4-1: BLOCK DIAGRAM OF RA3:RA0 PINS Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All Data Data Latch write operations are read-modify-write operations. Bus D Q Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port VDD WR data latch. PORTA CK Q P I/O pin(1) Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI TRIS Latch pin is a Schmitt Trigger input and an open-drain output. N D Q All other PORTA pins have TTL input levels and full CMOS output drivers. WR Other PORTA pins are multiplexed with analog inputs TRISA CK Q VSS Analog and the analog VREF input for both the A/D converters Input and the comparators. The operation of each pin is Mode selected by clearing/setting the appropriate control bits in the ADCON1 and/or CMCON registers. RD TRISA TTL Note: On a Power-on Reset, these pins are con- Input figured as analog inputs and read as ‘0’. Buffer The comparators are in the off (digital) Q D state. The TRISA register controls the direction of the port EN pins even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are RD PORTA maintained set when using them as analog inputs. To A/D Converter or Comparator Note 1: I/O pins have protection diodes to VDD and VSS.  2001-2013 Microchip Technology Inc. DS39582C-page 41

PIC16F87XA FIGURE 4-2: BLOCK DIAGRAM OF RA4/T0CKI PIN CMCON<2:0> = x01 or 011 C1OUT Data Latch Data Bus 1 D Q I/O pin(1) WR PORTA N CK Q 0 TRIS Latch VSS D Q WR TRISA Schmitt CK Q Trigger Input Buffer RD TRISA Q D ENEN RD PORTA TMR0 Clock Input Note1: I/O pin has protection diodes to VSS only. FIGURE 4-3: BLOCK DIAGRAM OF RA5 PIN CMCON<2:0> = 011 or 101 C2OUT Data Latch Data Bus 1 VDD D Q WR PORTA P CK Q 0 TRIS Latch N I/O pin(1) D Q Analog IIP Mode WR TRISA CK Q VSS TTL Input Buffer RD TRISA Q D ENEN RD PORTA A/D Converter or SS Input Note1: I/O pin has protection diodes to VDD and VSS. DS39582C-page 42  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 4-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit 0 TTL Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF-/CVREF bit 2 TTL Input/output or analog input or VREF- or CVREF. RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+. RA4/T0CKI/C1OUT bit 4 ST Input/output or external clock input for Timer0 or comparator output. Output is open-drain type. RA5/AN4/SS/C2OUT bit 5 TTL Input/output or analog input or slave select input for synchronous serial port or comparator output. Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111 9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000 9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of the following modes, where PCFG3:PCFG0 = 0100, 0101, 011x, 1101, 1110, 1111.  2001-2013 Microchip Technology Inc. DS39582C-page 43

PIC16F87XA 4.2 PORTB and the TRISB Register This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the PORTB is an 8-bit wide, bidirectional port. The corre- interrupt in the following manner: sponding data direction register is TRISB. Setting a a) Any read or write of PORTB. This will end the TRISB bit (= 1) will make the corresponding PORTB mismatch condition. pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) b) Clear flag bit RBIF. will make the corresponding PORTB pin an output (i.e., A mismatch condition will continue to set flag bit RBIF. put the contents of the output latch on the selected pin). Reading PORTB will end the mismatch condition and Three pins of PORTB are multiplexed with the In-Circuit allow flag bit RBIF to be cleared. Debugger and Low-Voltage Programming function: The interrupt-on-change feature is recommended for RB3/PGM, RB6/PGC and RB7/PGD. The alternate wake-up on key depression operation and operations functions of these pins are described in Section14.0 where PORTB is only used for the interrupt-on-change “Special Features of the CPU”. feature. Polling of PORTB is not recommended while Each of the PORTB pins has a weak internal pull-up. A using the interrupt-on-change feature. single control bit can turn on all the pull-ups. This is per- This interrupt-on-mismatch feature, together with soft- formed by clearing bit RBPU (OPTION_REG<7>). The ware configurable pull-ups on these four pins, allow weak pull-up is automatically turned off when the port easy interface to a keypad and make it possible for pin is configured as an output. The pull-ups are wake-up on key depression. Refer to the application disabled on a Power-on Reset. note, AN552, “Implementing Wake-up on Key Stroke” (DS00552). FIGURE 4-4: BLOCK DIAGRAM OF RB0/INT is an external interrupt input pin and is RB3:RB0 PINS configured using the INTEDG bit (OPTION_REG<6>). VDD RB0/INT is discussed in detail in Section14.11.1 “INT RBPU(2) Weak Interrupt”. P Pull-up Data Latch Data Bus FIGURE 4-5: BLOCK DIAGRAM OF D Q I/O pin(1) RB7:RB4 PINS WR Port CK VDD TRIS Latch RBPU(2) D Q P Weak TTL Pull-up WR TRIS Input Data Latch CK Buffer Data Bus D Q I/O pin(1) WR Port CK RD TRIS TRIS Latch D Q Q D RD Port WR TRIS TTL CK EN Input Buffer ST Buffer RB0/INT RB3/PGM RD TRIS Latch Schmitt Trigger RD Port Buffer Q D RD Port Note 1: I/O pins have diode protection to VDD and VSS. EN Q1 2: To enable weak pull-ups, set the appropriate TRIS Set RBIF bit(s) and clear the RBPU bit (OPTION_REG<7>). Q D Four of the PORTB pins, RB7:RB4, have an interrupt- From other RD Port on-change feature. Only pins configured as inputs can RB7:RB4 pins EN cause this interrupt to occur (i.e., any RB7:RB4 pin Q3 configured as an output is excluded from the interrupt- RB7:RB6 on-change comparison). The input pins (of RB7:RB4) In Serial Programming Mode are compared with the old value latched on the last Note 1: I/O pins have diode protection to VDD and VSS. read of PORTB. The “mismatch” outputs of RB7:RB4 2: To enable weak pull-ups, set the appropriate TRIS are OR’ed together to generate the RB port change bit(s) and clear the RBPU bit (OPTION_REG<7>). interrupt with flag bit RBIF (INTCON<0>). DS39582C-page 44  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 4-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit 0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit 1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit 2 TTL Input/output pin. Internal software programmable weak pull-up. RB3/PGM(3) bit 3 TTL Input/output pin or programming pin in LVP mode. Internal software programmable weak pull-up. RB4 bit 4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5 bit 5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB6/PGC bit 6 TTL/ST(2) Input/output pin (with interrupt-on-change) or in-circuit debugger pin. Internal software programmable weak pull-up. Serial programming clock. RB7/PGD bit 7 TTL/ST(2) Input/output pin (with interrupt-on-change) or in-circuit debugger pin. Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode or in-circuit debugger. 3: Low-Voltage ICSP Programming (LVP) is enabled by default which disables the RB3 I/O function. LVP must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and 40-pin mid-range devices. TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.  2001-2013 Microchip Technology Inc. DS39582C-page 45

PIC16F87XA 4.3 PORTC and the TRISC Register FIGURE 4-7: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT PORTC is an 8-bit wide, bidirectional port. The corre- OVERRIDE) RC<4:3> sponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC Port/Peripheral Select(2) pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) Peripheral Data Out 0 will make the corresponding PORTC pin an output (i.e., VDD Data Bus put the contents of the output latch on the selected pin). D Q P PORTC is multiplexed with several peripheral functions WR Port CK Q 1 (Table4-5). PORTC pins have Schmitt Trigger input Data Latch buffers. I/O D Q pin(1) When the I2C module is enabled, the PORTC<4:3> pins can be configured with normal I2C levels, or with WR TRIS CK Q N SMBus levels, by using the CKE bit (SSPSTAT<6>). TRIS Latch When enabling peripheral functions, care should be VSS taken in defining TRIS bits for each PORTC pin. Some RD TRIS Schmitt peripherals override the TRIS bit to make a pin an Trigger output, while other peripherals override the TRIS bit to Peripheral make a pin an input. Since the TRIS bit override is in OE(3) Q D Schmitt effect while the peripheral is enabled, read-modify- Trigger EN with write instructions (BSF, BCF, XORWF) with TRISC as the SMBus RD Port 0 Levels destination, should be avoided. The user should refer SSP Input to the corresponding peripheral section for the correct TRIS bit settings. 1 CKE FIGURE 4-6: PORTC BLOCK DIAGRAM SSPSTAT<6> (PERIPHERAL OUTPUT Note 1: I/O pins have diode protection to VDD and VSS. OVERRIDE) RC<2:0>, 2: Port/Peripheral Select signal selects between port data RC<7:5> and peripheral output. 3: Peripheral OE (Output Enable) is only activated if Port/Peripheral Select(2) Peripheral Select is active. Peripheral Data Out 0 VDD Data Bus D Q P WR Port CK Q 1 Data Latch I/O D Q pin(1) WR TRIS CK Q N TRIS Latch VSS RD TRIS Schmitt Trigger Peripheral OE(3) Q D EN RD Port Peripheral Input Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral Select signal selects between port data and peripheral output. 3: Peripheral OE (Output Enable) is only activated if Peripheral Select is active. DS39582C-page 46  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 4-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit 0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit 1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. RC2/CCP1 bit 2 ST Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit 4 ST RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode). RC5/SDO bit 5 ST Input/output port pin or Synchronous Serial Port data output. RC6/TX/CK bit 6 ST Input/output port pin or USART asynchronous transmit or synchronous clock. RC7/RX/DT bit 7 ST Input/output port pin or USART asynchronous receive or synchronous data. Legend: ST = Schmitt Trigger input TABLE 4-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged  2001-2013 Microchip Technology Inc. DS39582C-page 47

PIC16F87XA 4.4 PORTD and TRISD Registers FIGURE 4-8: PORTD BLOCK DIAGRAM (IN I/O PORT MODE) Note: PORTD and TRISD are not implemented on the 28-pin devices. Data Data Latch Bus D Q PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input WR I/O pin(1) Port CK or output. PORTD can be configured as an 8-bit wide TRIS Latch microprocessor port (Parallel Slave Port) by setting D Q control bit, PSPMODE (TRISE<4>). In this mode, the WR input buffers are TTL. TRIS CK Schmitt Trigger Input Buffer RD TRIS Q D ENEN RD Port Note 1: I/O pins have protection diodes to VDD and VSS. TABLE 4-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0 bit 0 ST/TTL(1) Input/output port pin or Parallel Slave Port bit 0. RD1/PSP1 bit 1 ST/TTL(1) Input/output port pin or Parallel Slave Port bit 1. RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or Parallel Slave Port bit 2. RD3/PSP3 bit 3 ST/TTL(1) Input/output port pin or Parallel Slave Port bit 3. RD4/PSP4 bit 4 ST/TTL(1) Input/output port pin or Parallel Slave Port bit 4. RD5/PSP5 bit 5 ST/TTL(1) Input/output port pin or Parallel Slave Port bit 5. RD6/PSP6 bit 6 ST/TTL(1) Input/output port pin or Parallel Slave Port bit 6. RD7/PSP7 bit 7 ST/TTL(1) Input/output port pin or Parallel Slave Port bit 7. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. TABLE 4-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. DS39582C-page 48  2001-2013 Microchip Technology Inc.

PIC16F87XA 4.5 PORTE and TRISE Register FIGURE 4-9: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) Note: PORTE and TRISE are not implemented on the 28-pin devices. Data Data Latch Bus PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6 D Q and RE2/CS/AN7) which are individually configurable WR I/O pin(1) Port as inputs or outputs. These pins have Schmitt Trigger CK input buffers. TRIS Latch The PORTE pins become the I/O control inputs for the D Q microprocessor port when bit PSPMODE (TRISE<4>) is WR set. In this mode, the user must make certain that the TRIS CK Schmitt TRISE<2:0> bits are set and that the pins are configured Trigger as digital inputs. Also, ensure that ADCON1 is config- Input Buffer ured for digital I/O. In this mode, the input buffers are RD TTL. TRIS Register4-1 shows the TRISE register which also controls the Parallel Slave Port operation. Q D PORTE pins are multiplexed with analog inputs. When selected for analog input, these pins will read as ‘0’s. ENEN TRISE controls the direction of the RE pins, even when RD Port they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note 1: I/O pins have protection diodes to VDD and VSS. Note: On a Power-on Reset, these pins are configured as analog inputs and read as ‘0’. TABLE 4-9: PORTE FUNCTIONS Name Bit# Buffer Type Function I/O port pin or read control input in Parallel Slave Port mode or analog input: RD RE0/RD/AN5 bit 0 ST/TTL(1) 1 = Idle 0 = Read operation. Contents of PORTD register are output to PORTD I/O pins (if chip selected). I/O port pin or write control input in Parallel Slave Port mode or analog input: WR RE1/WR/AN6 bit 1 ST/TTL(1) 1 = Idle 0 = Write operation. Value of PORTD I/O pins is latched into PORTD register (if chip selected). I/O port pin or chip select control input in Parallel Slave Port mode or analog input: RE2/CS/AN7 bit 2 ST/TTL(1) CS 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.  2001-2013 Microchip Technology Inc. DS39582C-page 49

PIC16F87XA TABLE 4-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. REGISTER 4-1: TRISE REGISTER (ADDRESS 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — Bit 2 Bit 1 Bit 0 bit 7 bit 0 Parallel Slave Port Status/Control Bits: bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = PORTD functions in Parallel Slave Port mode 0= PORTD functions in general purpose I/O mode bit 3 Unimplemented: Read as ‘0’ PORTE Data Direction Bits: bit 2 Bit 2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output bit 1 Bit 1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0 Bit 0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39582C-page 50  2001-2013 Microchip Technology Inc.

PIC16F87XA 4.6 Parallel Slave Port When not in PSP mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previously set, it The Parallel Slave Port (PSP) is not implemented on must be cleared in firmware. the PIC16F873A or PIC16F876A. An interrupt is generated and latched into flag bit PORTD operates as an 8-bit wide Parallel Slave Port, PSPIF when a read or write operation is completed. or microprocessor port, when control bit PSPMODE PSPIF must be cleared by the user in firmware and the (TRISE<4>) is set. In Slave mode, it is asynchronously interrupt can be disabled by clearing the interrupt readable and writable by the external world through RD enable bit PSPIE (PIE1<7>). control input pin, RE0/RD/AN5, and WR control input pin, RE1/WR/AN6. FIGURE 4-10: PORTD AND PORTE The PSP can directly interface to an 8-bit BLOCK DIAGRAM microprocessor data bus. The external microprocessor (PARALLEL SLAVE PORT) can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD/AN5 to be the RD input, RE1/WR/AN6 to be the WR input and Data Bus RE2/CS/AN7 to be the CS (Chip Select) input. For this D Q functionality, the corresponding data direction bits of WR RDx pin Port the TRISE register (TRISE<2:0>) must be configured CK as inputs (set). The A/D port configuration bits, TTL PCFG3:PCFG0 (ADCON1<3:0>), must be set to Q D configure pins RE2:RE0 as digital I/O. There are actually two 8-bit latches: one for data output RD Port ENEN and one for data input. The user writes 8-bit data to the PORTD data latch and reads data from the port pin latch (note that they have the same address). In this One bit of PORTD mode, the TRISD register is ignored since the external Set Interrupt Flag device is controlling the direction of data flow. PSPIF (PIR1<7>) A write to the PSP occurs when both the CS and WR lines are first detected low. When either the CS or WR lines become high (level triggered), the Input Buffer Full (IBF) status flag bit (TRISE<7>) is set on the Q4 clock Read TTL RD cycle, following the next Q2 cycle, to signal the write is complete (Figure4-11). The interrupt flag bit, PSPIF Chip Select (PIR1<7>), is also set on the same Q4 clock cycle. IBF TTL CS can only be cleared by reading the PORTD input latch. Write The Input Buffer Overflow (IBOV) status flag bit TTL WR (TRISE<5>) is set if a second write to the PSP is attempted when the previous byte has not been read Note 1: I/O pins have protection diodes to VDD and VSS. out of the buffer. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full (OBF) status flag bit (TRISE<6>) is cleared immediately (Figure4-12), indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware.  2001-2013 Microchip Technology Inc. DS39582C-page 51

PIC16F87XA FIGURE 4-11: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 4-12: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 4-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 08h PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873A/876A; always maintain these bits clear. DS39582C-page 52  2001-2013 Microchip Technology Inc.

PIC16F87XA 5.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will The Timer0 module timer/counter has the following increment either on every rising or falling edge of pin features: RA4/T0CKI. The incrementing edge is determined by • 8-bit timer/counter the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the ris- • Readable and writable ing edge. Restrictions on the external clock input are • 8-bit software programmable prescaler discussed in detail in Section5.2 “Using Timer0 with • Internal or external clock select an External Clock”. • Interrupt on overflow from FFh to 00h The prescaler is mutually exclusively shared between • Edge select for external clock the Timer0 module and the Watchdog Timer. The Figure5-1 is a block diagram of the Timer0 module and prescaler is not readable or writable. Section5.3 the prescaler shared with the WDT. “Prescaler” details the operation of the prescaler. Additional information on the Timer0 module is 5.1 Timer0 Interrupt available in the PIC® Mid-Range MCU Family Refer- ence Manual (DS33023). The TMR0 interrupt is generated when the TMR0 Timer mode is selected by clearing bit T0CS register overflows from FFh to 00h. This overflow sets (OPTION_REG<5>). In Timer mode, the Timer0 bit TMR0IF (INTCON<2>). The interrupt can be module will increment every instruction cycle (without masked by clearing bit TMR0IE (INTCON<5>). Bit prescaler). If the TMR0 register is written, the incre- TMR0IF must be cleared in software by the Timer0 ment is inhibited for the following two instruction cycles. module Interrupt Service Routine before re-enabling The user can work around this by writing an adjusted this interrupt. The TMR0 interrupt cannot awaken the value to the TMR0 register. processor from Sleep since the timer is shut-off during Sleep. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKO (= FOSC/4) Data Bus 8 M 0 1 RA4/T0CKI U M Sync pin 1 X 0 U 2 TMR0 Reg X Cycles T0SE T0CS PSA Set Flag bit TMR0IF on Overflow PRESCALER 0 8-bit Prescaler M U Watchdog 1 X 8 Timer 8-to-1 MUX PS2:PS0 PSA WDT Enable bit 0 1 MUX PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).  2001-2013 Microchip Technology Inc. DS39582C-page 53

PIC16F87XA 5.2 Using Timer0 with an External Timer0 module means that there is no prescaler for the Clock Watchdog Timer and vice versa. This prescaler is not readable or writable (see Figure5-1). When no prescaler is used, the external clock input is The PSA and PS2:PS0 bits (OPTION_REG<3:0>) the same as the prescaler output. The synchronization determine the prescaler assignment and prescale ratio. of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and When assigned to the Timer0 module, all instructions Q4 cycles of the internal phase clocks. Therefore, it is writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, necessary for T0CKI to be high for at least 2 TOSC (and BSF 1,x....etc.) will clear the prescaler. When assigned a small RC delay of 20 ns) and low for at least 2 TOSC to WDT, a CLRWDT instruction will clear the prescaler (and a small RC delay of 20 ns). Refer to the electrical along with the Watchdog Timer. The prescaler is not specification of the desired device. readable or writable. Note: Writing to TMR0 when the prescaler is 5.3 Prescaler assigned to Timer0 will clear the prescaler count, but will not change the prescaler There is only one prescaler available which is mutually assignment. exclusively shared between the Timer0 module and the Watchdog Timer. A prescaler assignment for the REGISTER 5-1: OPTION_REG REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU bit 6 INTEDG bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: To avoid an unintended device Reset, the instruction sequence shown in the PIC® Mid-Range MCU Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. DS39582C-page 54  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 01h,101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.  2001-2013 Microchip Technology Inc. DS39582C-page 55

PIC16F87XA NOTES: DS39582C-page 56  2001-2013 Microchip Technology Inc.

PIC16F87XA 6.0 TIMER1 MODULE In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising The Timer1 module is a 16-bit timer/counter consisting edge of the external clock input. of two 8-bit registers (TMR1H and TMR1L) which are Timer1 can be enabled/disabled by setting/clearing readable and writable. The TMR1 register pair control bit, TMR1ON (T1CON<0>). (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, Timer1 also has an internal “Reset input”. This Reset is generated on overflow which is latched in interrupt can be generated by either of the two CCP modules flag bit, TMR1IF (PIR1<0>). This interrupt can be (Section8.0 “Capture/Compare/PWM Modules”). enabled/disabled by setting/clearing TMR1 interrupt Register6-1 shows the Timer1 Control register. enable bit, TMR1IE (PIE1<0>). When the Timer1 oscillator is enabled (T1OSCEN is Timer1 can operate in one of two modes: set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is • As a Timer ignored and these pins read as ‘0’. • As a Counter Additional information on timer modules is available in The operating mode is determined by the clock select the PIC® Mid-Range MCU Family Reference Manual bit, TMR1CS (T1CON<1>). (DS33023). REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39582C-page 57

PIC16F87XA 6.1 Timer1 Operation in Timer Mode 6.2 Timer1 Counter Operation Timer mode is selected by clearing the TMR1CS Timer1 may operate in either a Synchronous, or an (T1CON<1>) bit. In this mode, the input clock to the Asynchronous mode, depending on the setting of the timer is FOSC/4. The synchronize control bit, T1SYNC TMR1CS bit. (T1CON<2>), has no effect since the internal clock is When Timer1 is being incremented via an external always in sync. source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment. FIGURE 6-1: TIMER1 INCREMENTING EDGE T1CKI (Default High) T1CKI (Default Low) Note: Arrows indicate counter increments. 6.3 Timer1 Operation in Synchronized If T1SYNC is cleared, then the external clock input is Counter Mode synchronized with internal phase clocks. The synchro- nization is done after the prescaler stage. The Counter mode is selected by setting bit TMR1CS. In prescaler stage is an asynchronous ripple counter. this mode, the timer increments on every rising edge of In this configuration, during Sleep mode, Timer1 will not clock input on pin RC1/T1OSI/CCP2 when bit increment even if the external clock is present since the T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when synchronization circuit is shut-off. The prescaler, bit T1OSCEN is cleared. however, will continue to increment. FIGURE 6-2: TIMER1 BLOCK DIAGRAM Set Flag bit TMR1IF on Overflow Synchronized TMR1 0 Clock Input TMR1H TMR1L 1 TMR1ON On/Off T1SYNC T1OSC RC0/T1OSO/T1CKI 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 RC1/T1OSI/CCP2(2) Oscillator(1) Clock 2 Q Clock T1CKPS1:T1CKPS0 TMR1CS Note1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. DS39582C-page 58  2001-2013 Microchip Technology Inc.

PIC16F87XA 6.4 Timer1 Operation in TABLE 6-1: CAPACITOR SELECTION FOR Asynchronous Counter Mode THE TIMER1 OSCILLATOR If control bit T1SYNC (T1CON<2>) is set, the external Osc Type Freq. C1 C2 clock input is not synchronized. The timer continues to LP 32 kHz 33 pF 33 pF increment asynchronous to the internal phase clocks. 100 kHz 15 pF 15 pF The timer will continue to run during Sleep and can generate an interrupt-on-overflow which will wake-up 200 kHz 15 pF 15 pF the processor. However, special precautions in These values are for design guidance only. software are needed to read/write the timer. Crystals Tested: In Asynchronous Counter mode, Timer1 cannot be 32.768 kHz Epson C-001R32.768K-A ± 20 PPM used as a time base for capture or compare operations. 100 kHz Epson C-2 100.00 KC-P ± 20 PPM 6.4.1 READING AND WRITING TIMER1 IN 200 kHz STD XTL 200.000 kHz ± 20 PPM ASYNCHRONOUS COUNTER MODE Note 1: Higher capacitance increases the stability Reading TMR1H or TMR1L while the timer is running of oscillator but also increases the start-up from an external asynchronous clock will ensure a valid time. read (taken care of in hardware). However, the user 2: Since each resonator/crystal has its own should keep in mind that reading the 16-bit timer in two characteristics, the user should consult 8-bit values itself, poses certain problems, since the the resonator/crystal manufacturer for timer may overflow between the reads. appropriate values of external For writes, it is recommended that the user simply stop components. the timer and write the desired values. A write conten- tion may occur by writing to the timer registers while the 6.6 Resetting Timer1 Using a CCP register is incrementing. This may produce an Trigger Output unpredictable value in the timer register. Reading the 16-bit value requires some care. If the CCP1 or CCP2 module is configured in Compare Examples 12-2 and 12-3 in the PIC® Mid-Range MCU mode to generate a “special event trigger” Family Reference Manual (DS33023) show how to (CCP1M3:CCP1M0 = 1011), this signal will reset read and write Timer1 when it is running in Timer1. Asynchronous mode. Note: The special event triggers from the CCP1 and CCP2 modules will not set interrupt 6.5 Timer1 Oscillator flag bit, TMR1IF (PIR1<0>). A crystal oscillator circuit is built-in between pins T1OSI Timer1 must be configured for either Timer or Synchro- (input) and T1OSO (amplifier output). It is enabled by nized Counter mode to take advantage of this feature. setting control bit, T1OSCEN (T1CON<3>). The oscil- If Timer1 is running in Asynchronous Counter mode, lator is a low-power oscillator, rated up to 200 kHz. It this Reset operation may not work. will continue to run during Sleep. It is primarily intended In the event that a write to Timer1 coincides with a for use with a 32 kHz crystal. Table6-1 shows the special event trigger from CCP1 or CCP2, the write will capacitor selection for the Timer1 oscillator. take precedence. The Timer1 oscillator is identical to the LP oscillator. In this mode of operation, the CCPRxH:CCPRxL regis- The user must provide a software time delay to ensure ter pair effectively becomes the period register for proper oscillator start-up. Timer1.  2001-2013 Microchip Technology Inc. DS39582C-page 59

PIC16F87XA 6.7 Resetting of Timer1 Register Pair 6.8 Timer1 Prescaler (TMR1H, TMR1L) The prescaler counter is cleared on writes to the TMR1H and TMR1L registers are not reset to 00h on a TMR1H or TMR1L registers. POR, or any other Reset, except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other Resets, the register is unaffected. TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. DS39582C-page 60  2001-2013 Microchip Technology Inc.

PIC16F87XA 7.0 TIMER2 MODULE Register7-1 shows the Timer2 Control register. Additional information on timer modules is available in Timer2 is an 8-bit timer with a prescaler and a the PIC® Mid-Range MCU Family Reference Manual postscaler. It can be used as the PWM time base for the (DS33023). PWM mode of the CCP module(s). The TMR2 register is readable and writable and is cleared on any device FIGURE 7-1: TIMER2 BLOCK DIAGRAM Reset. The input clock (FOSC/4) has a prescale option of Sets Flag TMR2 1:1, 1:4 or 1:16, selected by control bits bit TMR2IF Output(1) T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. Reset TMR2 Reg 1:P1,r e1s:4c,a 1le:r16 FOSC/4 Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is Postscaler Comparator 2 a readable and writable register. The PR2 register is 1:1 to 1:16 EQ T2CKPS1: initialized to FFh upon Reset. 4 PR2 Reg T2CKPS0 The match output of TMR2 goes through a 4-bit T2OUTPS3: postscaler (which gives a 1:1 to 1:16 scaling inclusive) T2OUTPS0 to generate a TMR2 interrupt (latched in flag bit, Note1: TMR2 register output can be software selected by the TMR2IF (PIR1<1>)). SSP module as a baud clock. Timer2 can be shut-off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale • • • 1111 = 1:16 postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39582C-page 61

PIC16F87XA 7.1 Timer2 Prescaler and Postscaler 7.2 Output of TMR2 The prescaler and postscaler counters are cleared The output of TMR2 (before the postscaler) is fed to the when any of the following occurs: SSP module, which optionally uses it to generate the shift clock. • a write to the TMR2 register • a write to the T2CON register • any device Reset (POR, MCLR Reset, WDT Reset or BOR) TMR2 is not cleared when T2CON is written. TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear. DS39582C-page 62  2001-2013 Microchip Technology Inc.

PIC16F87XA 8.0 CAPTURE/COMPARE/PWM CCP2 Module: MODULES Capture/Compare/PWM Register 2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and Each Capture/Compare/PWM (CCP) module contains CCPR2H (high byte). The CCP2CON register controls a 16-bit register which can operate as a: the operation of CCP2. The special event trigger is • 16-bit Capture register generated by a compare match and will reset Timer1 • 16-bit Compare register and start an A/D conversion (if the A/D module is enabled). • PWM Master/Slave Duty Cycle register Additional information on CCP modules is available in Both the CCP1 and CCP2 modules are identical in the PIC® Mid-Range MCU Family Reference Manual operation, with the exception being the operation of the (DS33023) and in application note AN594, “Using the special event trigger. Table8-1 and Table8-2 show the CCP Module(s)” (DS00594). resources and interactions of the CCP module(s). In the following sections, the operation of a CCP module TABLE 8-1: CCP MODE – TIMER is described with respect to CCP1. CCP2 operates the RESOURCES REQUIRED same as CCP1 except where noted. CCP1 Module: CCP Mode Timer Resource Capture/Compare/PWM Register 1 (CCPR1) is com- Capture Timer1 prised of two 8-bit registers: CCPR1L (low byte) and Compare Timer1 CCPR1H (high byte). The CCP1CON register controls PWM Timer2 the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1. TABLE 8-2: INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture Same TMR1 time base Capture Compare The compare should be configured for the special event trigger which clears TMR1 Compare Compare The compare(s) should be configured for the special event trigger which clears TMR1 PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt) PWM Capture None PWM Compare None  2001-2013 Microchip Technology Inc. DS39582C-page 63

PIC16F87XA REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS 17h/1Dh) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits 0000 =Capture/Compare/PWM disabled (resets CCPx module) 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, set output on match (CCPxIF bit is set) 1001 =Compare mode, clear output on match (CCPxIF bit is set) 1010 =Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 =Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx =PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39582C-page 64  2001-2013 Microchip Technology Inc.

PIC16F87XA 8.1 Capture Mode 8.1.2 TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode, or Synchro- 16-bit value of the TMR1 register when an event occurs nized Counter mode, for the CCP module to use the on pin RC2/CCP1. An event is defined as one of the capture feature. In Asynchronous Counter mode, the following: capture operation may not work. • Every falling edge 8.1.3 SOFTWARE INTERRUPT • Every rising edge When the Capture mode is changed, a false capture • Every 4th rising edge interrupt may be generated. The user should keep bit • Every 16th rising edge CCP1IE (PIE1<2>) clear to avoid false interrupts and The type of event is configured by control bits, should clear the flag bit, CCP1IF, following any such change in operating mode. CCP1M3:CCP1M0 (CCPxCON<3:0>). When a cap- ture is made, the interrupt request flag bit, CCP1IF 8.1.4 CCP PRESCALER (PIR1<2>), is set. The interrupt flag must be cleared in software. If another capture occurs before the value in There are four prescaler settings, specified by bits register CCPR1 is read, the old captured value is CCP1M3:CCP1M0. Whenever the CCP module is overwritten by the new value. turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear 8.1.1 CCP PIN CONFIGURATION the prescaler counter. In Capture mode, the RC2/CCP1 pin should be Switching from one capture prescaler to another may configured as an input by setting the TRISC<2> bit. generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from Note: If the RC2/CCP1 pin is configured as an a non-zero prescaler. Example8-1 shows the recom- output, a write to the port can cause a mended method for switching between capture Capture condition. prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. FIGURE 8-1: CAPTURE MODE OPERATION BLOCK EXAMPLE 8-1: CHANGING BETWEEN DIAGRAM CAPTURE PRESCALERS CLRF CCP1CON ; Turn CCP module off Set Flag bit CCP1IF (PIR1<2>) MOVLW NEW_CAPT_PS ; Load the W reg with Prescaler ; the new prescaler  1, 4, 16 ; move value and CCP ON RC2/CCP1 pin CCPR1H CCPR1L MOVWF CCP1CON ; Load CCP1CON with this ; value and Capture Edge Detect Enable TMR1H TMR1L CCP1CON<3:0> Qs  2001-2013 Microchip Technology Inc. DS39582C-page 65

PIC16F87XA 8.2 Compare Mode 8.2.2 TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is Timer1 must be running in Timer mode, or Synchro- constantly compared against the TMR1 register pair nized Counter mode, if the CCP module is using the value. When a match occurs, the RC2/CCP1 pin is: compare feature. In Asynchronous Counter mode, the compare operation may not work. • Driven high • Driven low 8.2.3 SOFTWARE INTERRUPT MODE • Remains unchanged When Generate Software Interrupt mode is chosen, the The action on the pin is based on the value of control CCP1 pin is not affected. The CCPIF bit is set, causing bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the a CCP interrupt (if enabled). same time, interrupt flag bit CCP1IF is set. 8.2.4 SPECIAL EVENT TRIGGER FIGURE 8-2: COMPARE MODE In this mode, an internal hardware trigger is generated OPERATION BLOCK which may be used to initiate an action. DIAGRAM The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>) effectively be a 16-bit programmable period register for and set bit GO/DONE (ADCON0<2>). Timer1. Special Event Trigger The special event trigger output of CCP2 resets the TMR1 register pair and starts an A/D conversion (if the Set Flag bit CCP1IF A/D module is enabled). (PIR1<2>) RC2/CCP1 CCPR1H CCPR1L Note: The special event trigger from the CCP1 pin and CCP2 modules will not set interrupt Q S Output R Logic Match Comparator flag bit TMR1IF (PIR1<0>). TRISC<2> TMR1H TMR1L Output Enable CCP1CON<3:0> Mode Select 8.2.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch. DS39582C-page 66  2001-2013 Microchip Technology Inc.

PIC16F87XA 8.3 PWM Mode (PWM) 8.3.1 PWM PERIOD In Pulse Width Modulation mode, the CCPx pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the the CCP1 pin is multiplexed with the PORTC data latch, following formula: the TRISC<2> bit must be cleared to make the CCP1 PWM Period = [(PR2) + 1] • 4 • TOSC • pin an output. (TMR2 Prescale Value) Note: Clearing the CCP1CON register will force PWM frequency is defined as 1/[PWM period]. the CCP1 PWM output latch to the default When TMR2 is equal to PR2, the following three events low level. This is not the PORTC I/O data occur on the next increment cycle: latch. • TMR2 is cleared Figure8-3 shows a simplified block diagram of the • The CCP1 pin is set (exception: if PWM duty CCP module in PWM mode. cycle=0%, the CCP1 pin will not be set) For a step-by-step procedure on how to set up the CCP • The PWM duty cycle is latched from CCPR1L into module for PWM operation, see Section8.3.3 “Setup CCPR1H for PWM Operation”. Note: The Timer2 postscaler (see Section7.1 “Timer2 Prescaler and Postscaler”) is FIGURE 8-3: SIMPLIFIED PWM BLOCK not used in the determination of the PWM DIAGRAM frequency. The postscaler could be used to have a servo update rate at a different CCP1CON<5:4> Duty Cycle Registers frequency than the PWM output. CCPR1L 8.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up CCPR1H (Slave) to 10-bit resolution is available. The CCPR1L contains RC2/CCP1 the eight MSbs and the CCP1CON<5:4> contains the Comparator R Q two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: TMR2 (Note 1) S PWM Duty Cycle =(CCPR1L:CCP1CON<5:4>) • TOSC • (TMR2 Prescale Value) Comparator TRISC<2> Clear Timer, CCPR1L and CCP1CON<5:4> can be written to at any CCP1 pin and time, but the duty cycle value is not latched into latch D.C. PR2 CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, Note 1: The 8-bit timer is concatenated with 2-bit internal Q CCPR1H is a read-only register. clock, or 2 bits of the prescaler, to create 10-bit time base. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This A PWM output (Figure8-4) has a time base (period) double-buffering is essential for glitch-free PWM and a time that the output stays high (duty cycle). The operation. frequency of the PWM is the inverse of the period (1/period). When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. FIGURE 8-4: PWM OUTPUT The maximum PWM resolution (bits) for a given PWM Period frequency is given by the following formula. EQUATION 8-1: Duty Cycle (FOSC ) log Resolution = FPWM bits TMR2 = PR2 log(2) TMR2 = Duty Cycle Note: If the PWM duty cycle value is longer than TMR2 = PR2 the PWM period, the CCP1 pin will not be cleared.  2001-2013 Microchip Technology Inc. DS39582C-page 67

PIC16F87XA 8.3.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 register. 2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. 4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. 5. Configure the CCP1 module for PWM operation. TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFFh 0xFFh 0xFFh 0x3Fh 0x1Fh 0x17h Maximum Resolution (bits) 10 10 10 8 7 5.5 TABLE 8-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. Note 1: The PSP is not implemented on 28-pin devices; always maintain these bits clear. DS39582C-page 68  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 8-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x0000 000u 10Bh, 18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 00000000 0000 0Dh PIR2 — — — — — — — CCP2IF ---- ---0---- ---0 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 00000000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0---- ---0 87h TRISC PORTC Data Direction Register 1111 11111111 1111 11h TMR2 Timer2 Module’s Register 0000 00000000 0000 92h PR2 Timer2 Module’s Period Register 1111 11111111 1111 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000-000 0000 15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxxuuuu uuuu 16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxxuuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000--00 0000 1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxxuuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxxuuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000--00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.  2001-2013 Microchip Technology Inc. DS39582C-page 69

PIC16F87XA NOTES: DS39582C-page 70  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.0 MASTER SYNCHRONOUS FIGURE 9-1: MSSP BLOCK DIAGRAM SERIAL PORT (MSSP) (SPIMODE) MODULE Internal Data Bus Read Write 9.1 Master SSP (MSSP) Module Overview SSPBUF reg The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, SSPSR reg display drivers, A/D converters, etc. The MSSP module RC4/SDI/SDA bit0 Shift can operate in one of two modes: Clock • Serial Peripheral Interface (SPI) RC5/SDO Peripheral OE • Inter-Integrated Circuit (I2C) - Full Master mode SS Control - Slave mode (with general address call) Enable The I2C interface supports the following modes in RA5/AN4/ hardware: SS/C2OUT Edge Select • Master mode • Multi-Master mode 2 • Slave mode Clock Select SSPM3:SSPM0 9.2 Control Registers SMP:CKE 4 TMR2 Output 2  2 The MSSP module has three associated registers. Edge These include a status register (SSPSTAT) and two Select Prescaler TOSC control registers (SSPCON and SSPCON2). The use RC3/SCK/SCL 4, 16, 64 of these registers and their individual configuration bits differ significantly, depending on whether the MSSP Data to TX/RX in SSPSR module is operated in SPI or I2C mode. TRIS bit Additional details are provided under the individual sections. Note: When the SPI is in Slave mode with SS pin 9.3 SPI Mode control enabled (SSPCON<3:0> = 0100), the state of the SS pin can affect the state The SPI mode allows 8 bits of data to be synchronously read back from the TRISC<5> bit. The transmitted and received simultaneously. All four Peripheral OE signal from the SSP mod- modes of SPI are supported. To accomplish ule in PORTC controls the state that is communication, typically three pins are used: read back from the TRISC<5> bit (see • Serial Data Out (SDO) – RC5/SDO Section4.3 “PORTC and the TRISC • Serial Data In (SDI) – RC4/SDI/SDA Register” for information on PORTC). If Read-Modify-Write instructions, such as • Serial Clock (SCK) – RC3/SCK/SCL BSF, are performed on the TRISC register Additionally, a fourth pin may be used when in a Slave while the SS pin is high, this will cause the mode of operation: TRISC<5> bit to be set, thus disabling the • Slave Select (SS) – RA5/AN4/SS/C2OUT SDO output. Figure9-1 shows the block diagram of the MSSP module when operating in SPI mode.  2001-2013 Microchip Technology Inc. DS39582C-page 71

PIC16F87XA 9.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes The MSSP module has four registers for SPI mode are written to or read from. operation. These are: In receive operations, SSPSR and SSPBUF together • MSSP Control Register (SSPCON) create a double-buffered receiver. When SSPSR • MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF • Serial Receive/Transmit Buffer Register and the SSPIF interrupt is set. (SSPBUF) During transmission, the SSPBUF is not double- • MSSP Shift Register (SSPSR) – Not directly buffered. A write to SSPBUF will write to both SSPBUF accessible and SSPSR. SSPCON and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON regis- ter is readable and writable. The lower six bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 9-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>). bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write bit information Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39582C-page 72  2001-2013 Microchip Technology Inc.

PIC16F87XA REGISTER 9-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be cleared in software.) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. (Must be cleared in software.) 0 = No overflow Note: In Master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by writing to the SSPBUF register. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39582C-page 73

PIC16F87XA 9.3.2 OPERATION SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL When initializing the SPI, several options need to be (SSPCON<7>), will be set. User software must clear specified. This is done by programming the appropriate the WCOL bit so that it can be determined if the follow- control bits (SSPCON<5:0> and SSPSTAT<7:6>). ing write(s) to the SSPBUF register completed These control bits allow the following to be specified: successfully. • Master mode (SCK is the clock output) When the application software is expecting to receive • Slave mode (SCK is the clock input) valid data, the SSPBUF should be read before the next • Clock Polarity (Idle state of SCK) byte of data to transfer is written to the SSPBUF. Buffer • Data Input Sample Phase (middle or end of data Full bit, BF (SSPSTAT<0>), indicates when SSPBUF output time) has been loaded with the received data (transmission • Clock Edge (output data on rising/falling edge of is complete). When the SSPBUF is read, the BF bit is SCK) cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to • Clock Rate (Master mode only) determine when the transmission/reception has com- • Slave Select mode (Slave mode only) pleted. The SSPBUF must be read and/or written. If the The MSSP consists of a transmit/receive shift register interrupt method is not going to be used, then software (SSPSR) and a buffer register (SSPBUF). The SSPSR polling can be done to ensure that a write collision does shifts the data in and out of the device, MSb first. The not occur. Example9-1 shows the loading of the SSPBUF holds the data that was written to the SSPSR SSPBUF (SSPSR) for data transmission. until the received data is ready. Once the eight bits of The SSPSR is not directly readable or writable and can data have been received, that byte is moved to the only be accessed by addressing the SSPBUF register. SSPBUF register. Then, the Buffer Full detect bit, BF Additionally, the MSSP Status register (SSPSTAT) (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are indicates the various status conditions. set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the EXAMPLE 9-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS39582C-page 74  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.3.3 ENABLING SPI I/O 9.3.4 TYPICAL CONNECTION To enable the serial port, SSP Enable bit, SSPEN Figure9-2 shows a typical connection between two (SSPCON<5>), must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1) SPI mode, clear the SSPEN bit, re-initialize the initiates the data transfer by sending the SCK signal. SSPCON registers and then set the SSPEN bit. This Data is shifted out of both shift registers on their configures the SDI, SDO, SCK and SS pins as serial programmed clock edge and latched on the opposite port pins. For the pins to behave as the serial port func- edge of the clock. Both processors should be tion, some must have their data direction bits (in the programmed to the same Clock Polarity (CKP), then TRIS register) appropriately programmed. That is: both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy • SDI is automatically controlled by the SPI module data) depends on the application software. This leads • SDO must have TRISC<5> bit cleared to three scenarios for data transmission: • SCK (Master mode) must have TRISC<3> bit • Master sends data–Slave sends dummy data cleared • Master sends data–Slave sends data • SCK (Slave mode) must have TRISC<3> bit set • Master sends dummy data–Slave sends data • SS must have TRISC<4> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 9-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2  2001-2013 Microchip Technology Inc. DS39582C-page 75

PIC16F87XA 9.3.5 MASTER MODE Figure9-3, Figure9-5 and Figure9-6, where the MSB is transmitted first. In Master mode, the SPI clock rate The master can initiate the data transfer at any time (bit rate) is user programmable to be one of the because it controls the SCK. The master determines following: when the slave (Processor 2, Figure9-2) is to broadcast data by the software protocol. • FOSC/4 (or TCY) In Master mode, the data is transmitted/received as • FOSC/16 (or 4 • TCY) soon as the SSPBUF register is written to. If the SPI is • FOSC/64 (or 16 • TCY) only going to receive, the SDO output could be • Timer2 output/2 disabled (programmed as an input). The SSPSR This allows a maximum data rate (at 40 MHz) of register will continue to shift in the signal present on the 10.00Mbps. SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as Figure9-3 shows the waveforms for Master mode. if a normal received byte (interrupts and status bits When the CKE bit is set, the SDO data is valid before appropriately set). This could be useful in receiver there is a clock edge on SCK. The change of the input applications as a “Line Activity Monitor” mode. sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received The clock polarity is selected by appropriately program- data is shown. ming the CKP bit (SSPCON<4>). This then, would give waveforms for SPI communication as shown in FIGURE 9-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2 SSPBUF DS39582C-page 76  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.3.6 SLAVE MODE the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes In Slave mode, the data is transmitted and received as a floating output. External pull-up/pull-down resistors the external clock pulses appear on SCK. When the may be desirable, depending on the application. last bit is latched, the SSPIF interrupt flag bit is set. Note 1: When the SPI is in Slave mode with SS pin While in Slave mode, the external clock is supplied by control enabled (SSPCON<3:0> = 0100), the external clock source on the SCK pin. This external the SPI module will reset if the SS pin is set clock must meet the minimum high and low times as specified in the electrical specifications. to VDD. 2: If the SPI is used in Slave Mode with CKE While in Sleep mode, the slave can transmit/receive set, then the SS pin control must be data. When a byte is received, the device will wake-up enabled. from Sleep. When the SPI module resets, the bit counter is forced 9.3.7 SLAVE SELECT to ‘0’. This can be done by either forcing the SS pin to SYNCHRONIZATION a high level or clearing the SSPEN bit. The SS pin allows a Synchronous Slave mode. The To emulate two-wire communication, the SDO pin can SPI must be in Slave mode with SS pin control enabled be connected to the SDI pin. When the SPI needs to (SSPCON<3:0> = 04h). The pin must not be driven low operate as a receiver, the SDO pin can be configured for the SS pin to function as an input. The data latch as an input. This disables transmissions from the SDO. must be high. When the SS pin is low, transmission and The SDI can always be left as an input (SDI function) reception are enabled and the SDO pin is driven. When since it cannot create a bus conflict. FIGURE 9-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2 SSPBUF  2001-2013 Microchip Technology Inc. DS39582C-page 77

PIC16F87XA FIGURE 9-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2 SSPBUF FIGURE 9-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF DS39582C-page 78  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.3.8 SLEEP OPERATION 9.3.10 BUS MODE COMPATIBILITY In Master mode, all module clocks are halted and the Table9-1 shows the compatibility between the transmission/reception will remain in that state until the standard SPI modes and the states of the CKP and device wakes from Sleep. After the device returns to CKE control bits. normal mode, the module will continue to transmit/ receive data. TABLE 9-1: SPI BUS MODES In Slave mode, the SPI Transmit/Receive Shift register Control Bits State Standard SPI Mode operates asynchronously to the device. This allows the Terminology device to be placed in Sleep mode and data to be CKP CKE shifted into the SPI Transmit/Receive Shift register. 0, 0 0 1 When all 8 bits have been received, the MSSP interrupt 0, 1 0 0 flag bit will be set and if enabled, will wake the device from Sleep. 1, 0 1 1 1, 1 1 0 9.3.9 EFFECTS OF A RESET There is also a SMP bit which controls when the data is A Reset disables the MSSP module and terminates the sampled. current transfer. TABLE 9-2: REGISTERS ASSOCIATED WITH SPI OPERATION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 TRISC PORTC Data Direction Register 1111 1111 1111 1111 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 TRISA — PORTA Data Direction Register --11 1111 --11 1111 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on 28-pin devices; always maintain these bits clear.  2001-2013 Microchip Technology Inc. DS39582C-page 79

PIC16F87XA 9.4 I2C Mode 9.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call sup- These are: port) and provides interrupts on Start and Stop bits in • MSSP Control Register (SSPCON) hardware to determine a free bus (multi-master func- • MSSP Control Register 2 (SSPCON2) tion). The MSSP module implements the standard • MSSP Status Register (SSPSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPBUF) Two pins are used for data transfer: • MSSP Shift Register (SSPSR) – Not directly • Serial clock (SCL) – RC3/SCK/SCL accessible • Serial data (SDA) – RC4/SDI/SDA • MSSP Address Register (SSPADD) The user must configure these pins as inputs or outputs SSPCON, SSPCON2 and SSPSTAT are the control through the TRISC<4:3> bits. and status registers in I2C mode operation. The SSPCON and SSPCON2 registers are readable and FIGURE 9-7: MSSP BLOCK DIAGRAM writable. The lower six bits of the SSPSTAT are (I2C MODE) read-only. The upper two bits of the SSPSTAT are read/write. Internal SSPSR is the shift register used for shifting data in or Data Bus out. SSPBUF is the buffer register to which data bytes Read Write are written to or read from. SSPADD register holds the slave device address RC3/SCK/SCL SSPBUF reg when the SSP is configured in I2C Slave mode. When the SSP is configured in Master mode, the lower Shift seven bits of SSPADD act as the baud rate generator Clock reload value. SSPSR reg In receive operations, SSPSR and SSPBUF together RC4/SDI/ MSb LSb create a double-buffered receiver. When SSPSR SDA receives a complete byte, it is transferred to SSPBUF Match Detect Addr Match and the SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF SSPADD reg and SSPSR. Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT reg) DS39582C-page 80  2001-2013 Microchip Technology Inc.

PIC16F87XA REGISTER 9-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high-speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 3 S: Start bit 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 2 R/W: Read/Write bit information (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty In Receive mode: 1 = Data Transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data Transmit complete (does not include the ACK and Stop bits), SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39582C-page 81

PIC16F87XA REGISTER 9-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started. (Must be cleared in software.) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be cleared in software.) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. (Must be cleared in software.) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables the serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as input or output. bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In Master mode: Unused in this mode. bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39582C-page 82  2001-2013 Microchip Technology Inc.

PIC16F87XA REGISTER 9-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) (ADDRESS 91h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enabled/Stretch Enabled bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is enabled for slave transmit only (PIC16F87X compatibility) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).  2001-2013 Microchip Technology Inc. DS39582C-page 83

PIC16F87XA 9.4.2 OPERATION 9.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPCON<5>). a Start condition to occur. Following the Start condition, The SSPCON register allows control of the I2C opera- the 8 bits are shifted into the SSPSR register. All incom- ing bits are sampled with the rising edge of the clock tion. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: (SCL) line. The value of register SSPSR<7:1> is com- pared to the value of the SSPADD register. The • I2C Master mode, clock = OSC/4 (SSPADD + 1) address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match, and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) with Start and 1. The SSPSR register value is loaded into the Stop bit interrupts enabled SSPBUF register. • I2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is 4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is Idle set (interrupt is generated if enabled) on the Selection of any I2C mode, with the SSPEN bit set, falling edge of the ninth SCL pulse. forces the SCL and SDA pins to be open-drain, pro- In 10-bit Address mode, two address bytes need to be vided these pins are programmed to inputs by setting received by the slave. The five Most Significant bits the appropriate TRISC bits. To ensure proper operation (MSbs) of the first address byte specify if this is a 10-bit of the module, pull-up resistors must be provided address. Bit R/W (SSPSTAT<2>) must specify a write externally to the SCL and SDA pins. so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal 9.4.3 SLAVE MODE ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two In Slave mode, the SCL and SDA pins must be config- MSbs of the address. The sequence of events for ured as inputs (TRISC<4:3> set). The MSSP module 10-bit address is as follows, with steps 7 through 9 for will override the input state with the output data when the slave-transmitter: required (slave-transmitter). 1. Receive first (high) byte of address (bits SSPIF, The I2C Slave mode hardware will always generate an BF and bit UA (SSPSTAT<1>) are set). interrupt on an address match. Through the mode 2. Update the SSPADD register with second (low) select bits, the user can also choose to interrupt on byte of address (clears bit UA and releases the Start and Stop bits SCL line). When an address is matched, or the data transfer after 3. Read the SSPBUF register (clears bit BF) and an address match is received, the hardware automati- clear flag bit SSPIF. cally will generate the Acknowledge (ACK) pulse and 4. Receive second (low) byte of address (bits load the SSPBUF register with the received value SSPIF, BF and UA are set). currently in the SSPSR register. 5. Update the SSPADD register with the first (high) Any combination of the following conditions will cause byte of address. If match releases SCL line, this the MSSP module not to give this ACK pulse: will clear bit UA. • The buffer full bit, BF (SSPSTAT<0>), was set 6. Read the SSPBUF register (clears bit BF) and before the transfer was received. clear flag bit SSPIF. • The overflow bit, SSPOV (SSPCON<6>), was set 7. Receive Repeated Start condition. before the transfer was received. 8. Receive first (high) byte of address (bits SSPIF and BF are set). In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The 9. Read the SSPBUF register (clears bit BF) and BF bit is cleared by reading the SSPBUF register, while clear flag bit SSPIF. bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter #100 and parameter #101. DS39582C-page 84  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.4.3.2 Reception 9.4.3.3 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPSTAT register is set. The received address is loaded the SSPBUF register and the SDA line is held low into the SSPBUF register. The ACK pulse will be sent on (ACK). the ninth bit and pin RC3/SCK/SCL is held low regard- less of SEN (see Section9.4.4 “Clock Stretching” for When the address byte overflow condition exists, then more detail). By stretching the clock, the master will be the No Acknowledge (ACK) pulse is given. An overflow unable to assert another clock pulse until the slave is condition is defined as either bit BF (SSPSTAT<0>) is done preparing the transmit data. The transmit data set or bit SSPOV (SSPCON<6>) is set. must be loaded into the SSPBUF register, which also An MSSP interrupt is generated for each data transfer loads the SSPSR register. Then pin RC3/SCK/SCL byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- should be enabled by setting bit CKP (SSPCON<4>). ware. The SSPSTAT register is used to determine the The eight data bits are shifted out on the falling edge of status of the byte. the SCL input. This ensures that the SDA signal is valid If SEN is enabled (SSPCON<0> = 1), RC3/SCK/SCL during the SCL high time (Figure9-9). will be held low (clock stretch) following each data trans- The ACK pulse from the master-receiver is latched on fer. The clock must be released by setting bit CKP the rising edge of the ninth SCL input pulse. If the SDA (SSPCON<4>). See Section9.4.4 “Clock Stretching” line is high (not ACK), then the data transfer is com- for more detail. plete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT regis- ter) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse.  2001-2013 Microchip Technology Inc. DS39582C-page 85

PIC16F87XA FIGURE 9-8: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e Receiving D6D5D4 234 Cleared in softwarSSPBUF is read 7 D 1 K 9 0= AC W 8 R/ A1 7 2 0) A 6 = ddress A3 5 n SEN A e Receiving A5A4 34 0set to ‘’ wh e ot r A6 2 s n e o A7 1 0>) ON<6>) (CKP d SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP DS39582C-page 86  2001-2013 Microchip Technology Inc.

PIC16F87XA 2 FIGURE 9-9: I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S ACK 9 PIF I S D0 8 m S o ata D1 7 Fr D Transmitting D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software KP is set in software C D7 1 R ACK 9 PIF IS S D0 8 m S o 1 Fr D 7 a g Dat D2 6 ware Transmittin D6D5D4D3 2345 Cleared in software SSPBUF is written in soft CKP is set in software D7 1 PIF S SCL held lowwhile CPUresponds to S K C A 9 1 = W 8 R/ 1 A 7 2 ess A 6 Addr A3 5 g eivin A4 4 ec R A5 3 A6A7 12 Data in sampled >) 0>) 3 < < T 1 A R T DA CL S SPIF (PI F (SSPS KP S S S B C  2001-2013 Microchip Technology Inc. DS39582C-page 87

PIC16F87XA FIGURE 9-10: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. 0 D 8 1 D 7 e a Byte D3D2 56 n softwar ceive Dat D5D4 34 Cleared i e R 6 D 2 7 D 1 K AC 9 0 D 8 untilD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPADD is updated with highbyte of address d low SPAD D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPADD has taken place Receive First Byte of AddressReceive Second Byte of Address0R/W = ACK11110A9A8A7A6A5A4A3A2A1 1234567891234567 Cleared in softwareCleared in software AT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag PCON<6>) AT<1>) UA is set indicating thatCleared by hardwarethe SSPADD needs to bewhen SSPADD is updatedupdatedwith low byte of address UA is set indicating thatSSPADD needs to beupdated 00(CKP does not reset to ‘’ when SEN = ) SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C DS39582C-page 88  2001-2013 Microchip Technology Inc.

PIC16F87XA 2 FIGURE 9-11: I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are holding SCL low w Clock is held low untilupdate of SSPADD has Clock is held low untiltaken place1CKP is set to ‘’ Receive First Byte of AddressTransmitting Data ByteR/W=1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPBUFWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address CKP is set in software CKP is automatically cleared in hard 0 8 Clock is held low untilupdate of SSPADD has taken place 0Receive Second Byte of Address A7A6A5A4A3A2A1AK 91234567 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address UA is set indicating thatSSPADD needs to beupdated R/W = e First Byte of Address 110A9A8AC 345678 SSPBUF is written withcontents of SSPSR UA is set indicating thatthe SSPADD needs to beupdated Receiv 11 12 AT<0>) AT<1>) ON<4>) SDA SCLS SSPIF (PIR1<3>) BF (SSPST UA (SSPST CKP (SSPC  2001-2013 Microchip Technology Inc. DS39582C-page 89

PIC16F87XA 9.4.4 CLOCK STRETCHING 9.4.4.3 Clock Stretching for 7-bit Slave Transmit Mode Both 7 and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. 7-bit Slave Transmit mode implements clock stretching The SEN bit (SSPCON2<0>) allows clock stretching to by clearing the CKP bit after the falling edge of the ninth clock, if the BF bit is clear. This occurs regardless of the be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line 9.4.4.1 Clock Stretching for 7-bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPBUF before the master device can In 7-bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure9-9). ninth clock at the end of the ACK sequence, if the BF Note1: If the user loads the contents of SSPBUF, bit is set, the CKP bit in the SSPCON register is setting the BF bit before the falling edge of automatically cleared, forcing the SCL output to be the ninth clock, the CKP bit will not be held low. The CKP bit being cleared to ‘0’ will assert cleared and clock stretching will not occur. the SCL line low. The CKP bit must be set in the user’s 2: The CKP bit can be set in software ISR before reception is allowed to continue. By holding regardless of the state of the BF bit. the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the 9.4.4.4 Clock Stretching for 10-bit Slave master device can initiate another receive sequence. Transmit Mode This will prevent buffer overruns from occurring (see Figure9-13). In 10-bit Slave Transmit mode, clock stretching is con- trolled during the first two address sequences by the Note1: If the user reads the contents of the state of the UA bit, just as it is in 10-bit Slave Receive SSPBUF before the falling edge of the mode. The first two addresses are followed by a third ninth clock, thus clearing the BF bit, the address sequence, which contains the high order bits CKP bit will not be cleared and clock of the 10-bit address and the R/W bit set to ‘1’. After stretching will not occur. the third address sequence is performed, the UA bit is 2: The CKP bit can be set in software not set, the module is now configured in Transmit regardless of the state of the BF bit. The mode and clock stretching is controlled by the BF flag user should be careful to clear the BF bit as in 7-bit Slave Transmit mode (see Figure9-11). in the ISR before the next receive sequence in order to prevent an overflow condition. 9.4.4.2 Clock Stretching for 10-bit Slave Receive Mode (SEN = 1) In 10-bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address, with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching, on the basis of the state of the BF bit, only occurs during a data sequence, not an address sequence. DS39582C-page 90  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.4.4.5 Clock Synchronization and the CKP Bit When the CKP bit is cleared, the SCL output is forced to ‘0’; however, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure9-12). FIGURE 9-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX-1 SCL Master device asserts clock CKP Master device deasserts clock WR SSPCON  2001-2013 Microchip Technology Inc. DS39582C-page 91

PIC16F87XA FIGURE 9-13: I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lo1because ACK = ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 e Clock is held low until1CKP is set to ‘’ ACK D0D7D6 8912 CKPwritten1to ‘’ insoftwarBF is set after falling edge of the 9th clock,0CKP is reset to ‘’ andclock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be reset0to ‘’ and no clockstretching will occur S K 9 0 C = A W 8 R/ A1 7 2 A 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 A6 2 >) A7 1 <6 0>) ON SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP DS39582C-page 92  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 9-14: I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) w ent. Clock is not held lo1because ACK = ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not s D 8 1 D 7 e yte D2 6 war Clock is held low untilClock is held low untilupdate of SSPADD has update of SSPADD has Clock is held low untiltaken placetaken place1CKP is set to ‘’ Receive Second Byte of AddressReceive Data ByteReceive Data B0ACKACKA7A6A5A4A3A2A1A0D7D6D5D4D3D1D0D2D7D6D5D4D3K 912345678912345789612345 Cleared in softwareCleared in softCleared in software Dummy read of SSPBUFDummy read of SSPBUFto clear BF flagto clear BF flag Cleared by hardware whenCleared by hardware whenSSPADD is updated with highSSPADD is updated with lowbyte of address after falling edgebyte of address after falling edgeof ninth clockof ninth clock UA is set indicating thatSSPADD needs to beupdated Note:An update of the SSPADD registerbefore the falling edge of the ninth clockwill have no effect on UA and UA will1CKP written to ‘’remain set. in software Note:An update of the SSPADD registerbefore the falling edge of the ninth clockwill have no effect on UA, and UA willremain set. Receive First Byte of AddressR/W = 1110A9A8AC 2345678 Cleared in software >) SSPBUF is written withcontents of SSPSR N<6>) >) UA is set indicating thatSSPADD needs to beupdated 1 1 AT<0 PCO AT<1 SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C  2001-2013 Microchip Technology Inc. DS39582C-page 93

PIC16F87XA 9.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the The addressing procedure for the I2C bus is such that SSPIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by the master. When the interrupt is serviced, the source for the inter- The exception is the general call address which can rupt can be checked by reading the contents of the address all devices. When this address is used, all SSPBUF. The value can be used to determine if the devices should, in theory, respond with an Acknowledge. address was device specific or a general call address. The general call address is one of eight addresses In 10-bit mode, the SSPADD is required to be updated reserved for specific purposes by the I2C protocol. It for the second half of the address to match and the UA consists of all ‘0’s with R/W = 0. bit is set (SSPSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is The general call address is recognized when the Gen- configured in 10-bit Address mode, then the second eral Call Enable bit (GCEN) is enabled (SSPCON2<7> half of the address is not necessary, the UA bit will not set). Following a Start bit detect, 8 bits are shifted into be set and the slave will begin receiving data after the the SSPSR and the address is compared against the Acknowledge (Figure9-15). SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 9-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to general call address. After ACK, set interrupt. R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’ DS39582C-page 94  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPCON and by setting the of events. For instance, the user is not SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and are manipulated by the MSSP hardware. immediately write the SSPBUF register to initiate transmission before the Start condi- Master mode of operation is supported by interrupt tion is complete. In this case, the SSPBUF generation on the detection of the Start and Stop con- will not be written to and the WCOL bit will ditions. The Stop (P) and Start (S) bits are cleared from be set, indicating that a write to the a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set or the SSPBUF did not occur. bus is Idle, with both the S and P bits clear. The following events will cause SSP Interrupt Flag bit, In Firmware Controlled Master mode, user code SSPIF, to be set (SSP interrupt if enabled): conducts all I2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options. • Acknowledge transmit 1. Assert a Start condition on SDA and SCL. • Repeated Start 2. Assert a Repeated Start condition on SDA and SCL. 3. Write to the SSPBUF register, initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. 2 FIGURE 9-16: MSSP BLOCK DIAGRAM (I C MASTER MODE) Internal SSPM3:SSPM0 Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock ect SSPSR Dete) able MSb LSb WCOL k sourc SCL Receive En StAarcGtk beninot,ew Srlateotdepg beit, Clock Cntl ock Arbitrate/(hold off cloc Cl Start bit Detect Stop bit Detect SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT) Clock Arbitration Set SSPIF, BCLIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV  2001-2013 Microchip Technology Inc. DS39582C-page 95

PIC16F87XA 9.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required Start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDA while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPCON2 register (SSPCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. bit. In Master Receive mode, the first byte transmitted con- 7. The user loads the SSPBUF with eight bits of tains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDA pin until all 8 bits are logic ‘1’. Thus, the first byte transmitted is a 7-bit slave transmitted. address followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDA while SCL outputs the slave device and writes its value into the serial clock. Serial data is received 8 bits at a time. After SSPCON2 register (SSPCON2<6>). each byte is received, an Acknowledge bit is transmit- ted. Start and Stop conditions indicate the beginning 10. The MSSP module generates an interrupt at the and end of transmission. end of the ninth clock cycle by setting the SSPIF bit. The baud rate generator used for the SPI mode opera- 11. The user generates a Stop condition by setting tion is used to set the SCL clock frequency for either 100kHz, 400kHz or 1MHz I2C operation. See the Stop Enable bit, PEN (SSPCON2<2>). Section9.4.7 “Baud Rate Generator” for more detail. 12. Interrupt is generated once the Stop condition is complete. DS39582C-page 96  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.4.7 BAUD RATE GENERATOR Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal In I2C Master mode, the Baud Rate Generator (BRG) clock will automatically stop counting and the SCL pin reload value is placed in the lower 7 bits of the will remain in its last state. SSPADD register (Figure9-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically Table9-3 demonstrates clock rates based on begin counting. The BRG counts down to 0 and stops instruction cycles and the BRG value loaded into until another reload has taken place. The BRG count is SSPADD. decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. FIGURE 9-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 Reload Reload SCL Control CLKO BRG Down Counter FOSC/4 TABLE 9-3: I2C CLOCK RATE W/BRG FSCL FCY FCY*2 BRG Value (2 Rollovers of BRG) 10 MHz 20 MHz 19h 400 kHz(1) 10 MHz 20 MHz 20h 312.5 kHz 10 MHz 20 MHz 3Fh 100 kHz 4 MHz 8 MHz 0Ah 400 kHz(1) 4 MHz 8 MHz 0Dh 308 kHz 4 MHz 8 MHz 28h 100 kHz 1 MHz 2 MHz 03h 333 kHz(1) 1 MHz 2 MHz 0Ah 100 kHz 1 MHz 2 MHz 00h 1 MHz(1) Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application.  2001-2013 Microchip Technology Inc. DS39582C-page 97

PIC16F87XA 9.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCL high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count, in the deasserts the SCL pin (SCL allowed to float high). event that the clock is held low by an external device When the SCL pin is allowed to float high, the Baud (Figure9-17). Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 9-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload DS39582C-page 98  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.4.8 I2C MASTER MODE START 9.4.8.1 WCOL Status Flag CONDITION TIMING If the user writes the SSPBUF when a Start sequence To initiate a Start condition, the user sets the Start con- is in progress, the WCOL is set and the contents of the dition enable bit, SEN (SSPCON2<0>). If the SDA and buffer are unchanged (the write doesn’t occur). SCL pins are sampled high, the Baud Rate Generator Note: Because queueing of events is not is reloaded with the contents of SSPADD<6:0> and allowed, writing to the lower 5 bits of starts its count. If SCL and SDA are both sampled high SSPCON2 is disabled until the Start when the Baud Rate Generator times out (TBRG), the condition is complete. SDA pin is driven low. The action of the SDA being driven low, while SCL is high, is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the con- tents of SSPADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hard- ware, the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note: If at the beginning of the Start condition, the SDA and SCL pins are already sam- pled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag (BCLIF) is set, the Start condition is aborted and the I2C module is reset into its Idle state. FIGURE 9-19: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st Bit 2nd Bit SDA TBRG SCL TBRG S  2001-2013 Microchip Technology Inc. DS39582C-page 99

PIC16F87XA 9.4.9 I2C MASTER MODE REPEATED Immediately following the SSPIF bit getting set, the user START CONDITION TIMING may write the SSPBUF with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. After A Repeated Start condition occurs when the RSEN bit the first eight bits are transmitted and an ACK is (SSPCON2<1>) is programmed high and the I2C logic received, the user may then transmit an additional eight module is in the Idle state. When the RSEN bit is set, bits of address (10-bit mode) or eight bits of data (7-bit the SCL pin is asserted low. When the SCL pin is sam- mode). pled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The 9.4.9.1 WCOL Status Flag SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Genera- If the user writes the SSPBUF when a Repeated Start tor times out, if SDA is sampled high, the SCL pin will sequence is in progress, the WCOL is set and the con- be deasserted (brought high). When SCL is sampled tents of the buffer are unchanged (the write doesn’t high, the Baud Rate Generator is reloaded with the occur). contents of SSPADD<6:0> and begins counting. SDA Note: Because queueing of events is not and SCL must be sampled high for one TBRG. This allowed, writing of the lower 5 bits of action is then followed by assertion of the SDA pin SSPCON2 is disabled until the Repeated (SDA = 0) for one TBRG while SCL is high. Following Start condition is complete. this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. Note1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low to high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. FIGURE 9-20: REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 SDA = 1, occurs here, At completion of Start bit, SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change) and sets SSPIF TBRG TBRG TBRG 1st Bit SDA Falling edge of ninth clock, Write to SSPBUF occurs here end of Xmit TBRG SCL TBRG Sr = Repeated Start DS39582C-page 100  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.4.10 I2C MASTER MODE 9.4.10.3 ACKSTAT Status Flag TRANSMISSION In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is Transmission of a data byte, a 7-bit address or the cleared when the slave has sent an Acknowledge other half of a 10-bit address is accomplished by simply (ACK=0) and is set when the slave does Not Acknowl- writing a value to the SSPBUF register. This action will edge (ACK=1). A slave sends an Acknowledge when set the Buffer Full flag bit, BF, and allow the Baud Rate it has recognized its address (including a general call) Generator to begin counting and start the next trans- or when the slave has properly received its data. mission. Each bit of address/data will be shifted out 9.4.11 I2C MASTER MODE RECEPTION onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification, parameter Master mode reception is enabled by programming the #106). SCL is held low for one Baud Rate Generator Receive Enable bit, RCEN (SSPCON2<3>). rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification, Note: The MSSP module must be in an Idle state parameter #107). When the SCL pin is released high, it before the RCEN bit is set or the RCEN bit is held that way for TBRG. The data on the SDA pin will be disregarded. must remain stable for that duration and some hold The Baud Rate Generator begins counting and on each time after the next falling edge of SCL. After the eighth rollover, the state of the SCL pin changes (high to low/ bit is shifted out (the falling edge of the eighth clock), low to high) and data is shifted into the SSPSR. After the the BF flag is cleared and the master releases SDA. falling edge of the eighth clock, the receive enable flag This allows the slave device being addressed to is automatically cleared, the contents of the SSPSR are respond with an ACK bit during the ninth bit time, if an loaded into the SSPBUF, the BF flag bit is set, the address match occurred or if data was received prop- SSPIF flag bit is set and the Baud Rate Generator is erly. The status of ACK is written into the ACKDT bit on suspended from counting, holding SCL low. The MSSP the falling edge of the ninth clock. If the master receives is now in Idle state, awaiting the next command. When an Acknowledge, the Acknowledge Status bit, the buffer is read by the CPU, the BF flag bit is automat- ACKSTAT, is cleared. If not, the bit is set. After the ninth ically cleared. The user can then send an Acknowledge clock, the SSPIF bit is set and the master clock (Baud bit at the end of reception by setting the Acknowledge Rate Generator) is suspended until the next data byte Sequence Enable bit, ACKEN (SSPCON2<4>). is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure9-21). 9.4.11.1 BF Status Flag After the write to the SSPBUF, each bit of address will In receive operation, the BF bit is set when an address be shifted out on the falling edge of SCL, until all seven or data byte is loaded into SSPBUF from SSPSR. It is address bits and the R/W bit are completed. On the fall- cleared when the SSPBUF register is read. ing edge of the eighth clock, the master will deassert the SDA pin, allowing the slave to respond with an 9.4.11.2 SSPOV Status Flag Acknowledge. On the falling edge of the ninth clock, the In receive operation, the SSPOV bit is set when 8 bits master will sample the SDA pin to see if the address are received into the SSPSR and the BF flag bit is was recognized by a slave. The status of the ACK bit is already set from a previous reception. loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmis- 9.4.11.3 WCOL Status Flag sion of the address, the SSPIF is set, the BF flag is If the user writes the SSPBUF when a receive is cleared and the Baud Rate Generator is turned off until already in progress (i.e., SSPSR is still shifting in a data another write to the SSPBUF takes place, holding SCL byte), the WCOL bit is set and the contents of the buffer low and allowing SDA to float. are unchanged (the write doesn’t occur). 9.4.10.1 BF Status Flag In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all eight bits are shifted out. 9.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software.  2001-2013 Microchip Technology Inc. DS39582C-page 101

PIC16F87XA FIGURE 9-21: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A > Slave, clear ACKSTAT bit SSPCON2<6 Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1D0 2345678 Cleared in software service routinefrom SSP interrupt SSPBUF is written in software From D7 1 w SPIF o S 0= SCL held lwhile CPUsponds to CK re 0 A 9 W = W. are R/ave A2A1 ddress and R/ 678 ared by hardw s to Sl A3 7-bit a 5 are EN cle 1PCON2<0> SEN = dition begins 0SEN = Transmit Addres A7A6A5A4 SSPBUF written with Start transmit. 1234 Cleared in softw SSPBUF written After Start condition, S Sn Write SStart co S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W DS39582C-page 102  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 9-22: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Set ACKEN, start Acknowledge sequence,1SDA = ACKDT = 1PEN bit = N clearedwritten herematically D0ACK Bus masterACK is not sentterminatestransfer98PSet SSPIF at endCLKof receiveSet SSPIF interruptat end of Acknow-ledge sequence Set P bit (SSPSTAT<4>)Cleared inand SSPIFsoftware SSPOV is set becauseSSPBUF is still full RCEauto ave D1 7 e of Write to SSPCON2<4>to start Acknowledge sequence,0SDA = ACKDT (SSPCON2<5>) = er configured as a receiverACK from master1ogramming SSPCON2<3> (RCEN = )0SDA = ACKDT = RCEN cleared1RCEN = , startnext receiveautomatically Receiving Data from SlReceiving Data from SlaveACKD2D5D2D5D3D4D6D7D3D4D6D7D1D0 678956512343124 Data shifted in on falling edg Set SSPIF interruptSet SSPIF interruptat end of receiveat end of Acknowledgesequence Cleared in softwareCleared in softwareCleared in software Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF stpr Maby ve CK om Sla 1W = A 9 K fr R/ 8 e, AC A1 7 1Write to SSPCON2<0> (SEN = ),begin Start condition 0SEN = Write to SSPBUF occurs herstart XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 631245SCLS SSPIF Cleared in software01SDA = , SCL = while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN  2001-2013 Microchip Technology Inc. DS39582C-page 103

PIC16F87XA 9.4.12 ACKNOWLEDGE SEQUENCE 9.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/ (SSPCON2<4>). When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge pulled low and the contents of the Acknowledge data bit of the ninth clock. When the PEN bit is set, the master are presented on the SDA pin. If the user wishes to gen- will assert the SDA line low. When the SDA line is sam- erate an Acknowledge, then the ACKDT bit should be pled low, the Baud Rate Generator is reloaded and cleared. If not, the user should set the ACKDT bit before counts down to 0. When the Baud Rate Generator starting an Acknowledge sequence. The Baud Rate times out, the SCL pin will be brought high and one Generator then counts for one rollover period (TBRG) TBRG (Baud Rate Generator rollover count) later, the and the SCL pin is deasserted (pulled high). When the SDA pin will be deasserted. When the SDA pin is sam- SCL pin is sampled high (clock arbitration), the Baud pled high while SCL is high, the P bit (SSPSTAT<4>) is Rate Generator counts for TBRG. The SCL pin is then set. A TBRG later, the PEN bit is cleared and the SSPIF pulled low. Following this, the ACKEN bit is automatically bit is set (Figure9-24). cleared, the baud rate generator is turned off and the 9.4.13.1 WCOL Status Flag MSSP module then goes into Idle mode (Figure9-23). If the user writes the SSPBUF when a Stop sequence 9.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the con- If the user writes the SSPBUF when an Acknowledge tents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the occur). contents of the buffer are unchanged (the write doesn’t occur). FIGURE 9-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in Set SSPIF at the end of receive Cleared in software software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 9-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS39582C-page 104  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.4.14 SLEEP OPERATION 9.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or com- plete byte transfer occurs, wake the processor from Multi-Master mode support is achieved by bus arbitra- Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 9.4.15 EFFECT OF A RESET outputs a ‘1’ on SDA by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0, 9.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set In Multi-Master mode, the interrupt generation on the the Bus Collision Interrupt Flag, BCLIF, and reset the detection of the Start and Stop conditions allows the I2C port to its Idle state (Figure9-25). determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit (SSPSTAT<4>) is set, or the SSPBUF can be written to. When the user services the bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the SSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge condition monitored for arbitration to see if the signal level is at was in progress when the bus collision occurred, the con- the expected output level. This check is performed in dition is aborted, the SDA and SCL lines are deasserted hardware with the result placed in the BCLIF bit. and the respective control bits in the SSPCON2 register The states where arbitration can be lost are: are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the • Address Transfer user can resume communication by asserting a Start • Data Transfer condition. • A Start Condition The Master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determi- nation of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register or the bus is Idle and the S and P bits are cleared. FIGURE 9-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes SDA line pulled low Sample SDA. While SCL is high, while SCL = 0 by another source data doesn’t match what is driven by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF  2001-2013 Microchip Technology Inc. DS39582C-page 105

PIC16F87XA 9.4.17.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure9-28). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure9-26). counts down to 0 and during this time, if the SCL pin is b) SCL is sampled low before SDA is asserted low sampled as ‘0’, a bus collision does not occur. At the (Figure9-27). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a factor pins are monitored. during a Start condition is that no two bus masters can assert a Start condition at the If the SDA pin is already low, or the SCL pin is already exact same time. Therefore, one master low, then all of the following occur: will always assert SDA before the other. • the Start condition is aborted, This condition does not cause a bus colli- • the BCLIF flag is set and sion because the two masters must be • the MSSP module is reset to its Idle state allowed to arbitrate the first address fol- (Figure9-26). lowing the Start condition. If the address is The Start condition begins with the SDA and SCL pins the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded from SSPADD<6:0> Start or Stop conditions. and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 9-26: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software DS39582C-page 106  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 9-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA SCL Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 9-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF in software  2001-2013 Microchip Technology Inc. DS39582C-page 107

PIC16F87XA 9.4.17.2 Bus Collision During a Repeated reloaded and begins counting. If SDA goes from high to Start Condition low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the During a Repeated Start condition, a bus collision same time. occurs if: If SCL goes from high to low before the BRG times out a) A low level is sampled on SDA when SCL goes and SDA has not already been asserted, a bus collision from low level to high level. occurs. In this case, another master is attempting to b) SCL goes low before SDA is asserted low, transmit a data ‘1’ during the Repeated Start condition indicating that another master is attempting to (Figure9-30). transmit a data ‘1’. If at the end of the BRG time-out, both SCL and SDA When the user deasserts SDA and the pin is allowed to are still high, the SDA pin is driven low and the BRG is float high, the BRG is loaded with SSPADD<6:0> and reloaded and begins counting. At the end of the count, counts down to 0. The SCL pin is then deasserted and regardless of the status of the SCL pin, the SCL pin is when sampled high, the SDA pin is sampled. driven low and the Repeated Start condition is If SDA is low, a bus collision has occurred (i.e., another complete. master is attempting to transmit a data ‘0’, see Figure9-29). If SDA is sampled high, the BRG is FIGURE 9-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S ‘0’ SSPIF ‘0’ FIGURE 9-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S ‘0’ SSPIF DS39582C-page 108  2001-2013 Microchip Technology Inc.

PIC16F87XA 9.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<6:0> a) After the SDA pin has been deasserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure9-31). If the SCL pin is sampled low before SDA goes high. low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure9-32). FIGURE 9-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 9-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’  2001-2013 Microchip Technology Inc. DS39582C-page 109

PIC16F87XA NOTES: DS39582C-page 110  2001-2013 Microchip Technology Inc.

PIC16F87XA 10.0 ADDRESSABLE UNIVERSAL The USART can be configured in the following modes: SYNCHRONOUS • Asynchronous (full-duplex) ASYNCHRONOUS RECEIVER • Synchronous – Master (half-duplex) TRANSMITTER (USART) • Synchronous – Slave (half-duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be The Universal Synchronous Asynchronous Receiver set in order to configure pins RC6/TX/CK and RC7/RX/DT Transmitter (USART) module is one of the two serial as the Universal Synchronous Asynchronous Receiver I/O modules. (USART is also known as a Serial Transmitter. Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that The USART module also has a multi-processor can communicate with peripheral devices, such as communication capability using 9-bit address detection. CRT terminals and personal computers, or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as ‘0’ bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data, can be Parity bit Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39582C-page 111

PIC16F87XA REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39582C-page 112  2001-2013 Microchip Technology Inc.

PIC16F87XA 10.1 USART Baud Rate Generator It may be advantageous to use the high baud rate (BRG) (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16 (X + 1)) equation can reduce the The BRG supports both the Asynchronous and Syn- baud rate error in some cases. chronous modes of the USART. It is a dedicated 8-bit Writing a new value to the SPBRG register causes the baud rate generator. The SPBRG register controls the BRG timer to be reset (or cleared). This ensures the period of a free running 8-bit timer. In Asynchronous BRG does not wait for a timer overflow before mode, bit BRGH (TXSTA<2>) also controls the baud outputting the new baud rate. rate. In Synchronous mode, bit BRGH is ignored. Table10-1 shows the formula for computation of the 10.1.1 SAMPLING baud rate for different USART modes which only apply in Master mode (internal clock). The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a Given the desired baud rate and FOSC, the nearest low level is present at the RX pin. integer value for the SPBRG register can be calculated using the formula in Table10-1. From this, the error in baud rate can be determined. TABLE 10-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64 (X + 1)) Baud Rate = FOSC/(16 (X + 1)) 1 (Synchronous) Baud Rate = FOSC/(4 (X + 1)) N/A Legend: X = value in SPBRG (0 to 255) TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.  2001-2013 Microchip Technology Inc. DS39582C-page 113

PIC16F87XA TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz BAUD RATE % SPBRG % SPBRG % SPBRG (K) KBAUD ERROR value KBAUD ERROR value KBAUD ERROR value (decimal) (decimal) (decimal) 0.3 - - - - - - - - - 1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129 2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64 9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15 19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7 28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4 33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4 57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2 HIGH 1.221 - 255 0.977 - 255 0.610 - 255 LOW 312.500 - 0 250.000 - 0 156.250 - 0 FOSC = 4 MHz FOSC = 3.6864 MHz BAUD RATE % SPBRG % SPBRG (K) ERROR value ERROR value KBAUD (decimal) KBAUD (decimal) 0.3 0.300 0 207 0.3 0 191 1.2 1.202 0.17 51 1.2 0 47 2.4 2.404 0.17 25 2.4 0 23 9.6 8.929 6.99 6 9.6 0 5 19.2 20.833 8.51 2 19.2 0 2 28.8 31.250 8.51 1 28.8 0 1 33.6 - - - - - - 57.6 62.500 8.51 0 57.6 0 0 HIGH 0.244 - 255 0.225 - 255 LOW 62.500 - 0 57.6 - 0 TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz BAUD RATE % SPBRG % SPBRG % SPBRG (K) KBAUD ERROR value KBAUD ERROR value KBAUD ERROR value (decimal) (decimal) (decimal) 0.3 - - - - - - - - - 1.2 - - - - - - - - - 2.4 - - - - - - 2.441 1.71 255 9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64 19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31 28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21 33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18 57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10 HIGH 4.883 - 255 3.906 - 255 2.441 - 255 LOW 1250.000 - 0 1000.000 0 625.000 - 0 FOSC = 4 MHz FOSC = 3.6864 MHz BAUD RATE % SPBRG % SPBRG (K) ERROR value ERROR value KBAUD (decimal) KBAUD (decimal) 0.3 - - - - - - 1.2 1.202 0.17 207 1.2 0 191 2.4 2.404 0.17 103 2.4 0 95 9.6 9.615 0.16 25 9.6 0 23 19.2 19.231 0.16 12 19.2 0 11 28.8 27.798 3.55 8 28.8 0 7 33.6 35.714 6.29 6 32.9 2.04 6 57.6 62.500 8.51 3 57.6 0 3 HIGH 0.977 - 255 0.9 - 255 LOW 250.000 - 0 230.4 - 0 DS39582C-page 114  2001-2013 Microchip Technology Inc.

PIC16F87XA 10.2 USART Asynchronous Mode enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the In this mode, the USART uses standard Non-Return- state of enable bit TXIE and cannot be cleared in soft- to-Zero (NRZ) format (one Start bit, eight or nine data ware. It will reset only when new data is loaded into the bits and one Stop bit). The most common data format TXREG register. While flag bit TXIF indicates the status is 8 bits. An on-chip, dedicated, 8-bit Baud Rate of the TXREG register, another bit, TRMT (TXSTA<1>), Generator can be used to derive standard baud rate shows the status of the TSR register. Status bit TRMT frequencies from the oscillator. The USART transmits is a read-only bit which is set when the TSR register is and receives the LSb first. The transmitter and receiver empty. No interrupt logic is tied to this bit so the user are functionally independent but use the same data has to poll this bit in order to determine if the TSR format and baud rate. The baud rate generator register is empty. produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not Note1: The TSR register is not mapped in data supported by the hardware but can be implemented in memory so it is not available to the user. software (and stored as the ninth data bit). 2: Flag bit TXIF is set when enable bit TXEN Asynchronous mode is stopped during Sleep. is set. TXIF is cleared by loading TXREG. Asynchronous mode is selected by clearing bit SYNC Transmission is enabled by setting enable bit, TXEN (TXSTA<4>). (TXSTA<5>). The actual transmission will not occur The USART Asynchronous module consists of the until the TXREG register has been loaded with data following important elements: and the Baud Rate Generator (BRG) has produced a shift clock (Figure10-2). The transmission can also be • Baud Rate Generator started by first loading the TXREG register and then • Sampling Circuit setting enable bit TXEN. Normally, when transmission • Asynchronous Transmitter is first started, the TSR register is empty. At that point, • Asynchronous Receiver transfer to the TXREG register will result in an immedi- ate transfer to TSR, resulting in an empty TXREG. A 10.2.1 USART ASYNCHRONOUS back-to-back transfer is thus possible (Figure10-3). TRANSMITTER Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the The USART transmitter block diagram is shown in transmitter. As a result, the RC6/TX/CK pin will revert Figure10-1. The heart of the transmitter is the Transmit to high-impedance. (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer, TXREG. In order to select 9-bit transmission, transmit bit TX9 The TXREG register is loaded with data in software. (TXSTA<6>) should be set and the ninth bit should be The TSR register is not loaded until the Stop bit has written to TX9D (TXSTA<0>). The ninth bit must be been transmitted from the previous load. As soon as written before writing the 8-bit data to the TXREG reg- the Stop bit is transmitted, the TSR is loaded with new ister. This is because a data write to the TXREG regis- data from the TXREG register (if available). Once the ter can result in an immediate transfer of the data to the TXREG register transfers the data to the TSR register TSR register (if the TSR is empty). In such a case, an (occurs in one TCY), the TXREG register is empty and incorrect ninth data bit may be loaded in the TSR flag bit, TXIF (PIR1<4>), is set. This interrupt can be register. FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8)  0 Pin Buffer and Control TSR Register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG Baud Rate Generator TX9 TX9D  2001-2013 Microchip Technology Inc. DS39582C-page 115

PIC16F87XA When setting up an Asynchronous Transmission, 5. Enable the transmission by setting bit TXEN, follow these steps: which will also set bit TXIF. 1. Initialize the SPBRG register for the appropriate 6. If 9-bit transmission is selected, the ninth bit baud rate. If a high-speed baud rate is desired, should be loaded in bit TX9D. set bit BRGH (Section10.1 “USART Baud 7. Load data to the TXREG register (starts Rate Generator (BRG)”). transmission). 2. Enable the asynchronous serial port by clearing 8. If using interrupts, ensure that GIE and PEIE bit SYNC and setting bit SPEN. (bits 7 and 6) of the INTCON register are set. 3. If interrupts are desired, then set enable bit TXIE. 4. If 9-bit transmission is desired, then set transmit bit TX9. FIGURE 10-2: ASYNCHRONOUS MASTER TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK (pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 10-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) RC6/TX/CK (pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit Start Bit Bit 0 TXIF bit Word 1 Word 2 (Interrupt Reg. Flag) T(RTReragMn. TsE mmbiitpt tSyh Fifltag) TWraonrds m1it Shift Reg. WTraonrds m2it Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear. DS39582C-page 116  2001-2013 Microchip Technology Inc.

PIC16F87XA 10.2.2 USART ASYNCHRONOUS is possible for two bytes of data to be received and RECEIVER transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of The receiver block diagram is shown in Figure10-4. the Stop bit of the third byte, if the RCREG register is The data is received on the RC7/RX/DT pin and drives still full, the Overrun Error bit, OERR (RCSTA<1>), will the data recovery block. The data recovery block is be set. The word in the RSR will be lost. The RCREG actually a high-speed shifter, operating at x16 times the register can be read twice to retrieve the two bytes in baud rate; whereas the main receive serial shifter the FIFO. Overrun bit OERR has to be cleared in soft- operates at the bit rate or at FOSC. ware. This is done by resetting the receive logic (CREN Once Asynchronous mode is selected, reception is is cleared and then set). If bit OERR is set, transfers enabled by setting bit CREN (RCSTA<4>). from the RSR register to the RCREG register are inhib- The heart of the receiver is the Receive (Serial) Shift ited and no further data will be received. It is, therefore, Register (RSR). After sampling the Stop bit, the essential to clear error bit OERR if it is set. Framing received data in the RSR is transferred to the RCREG error bit, FERR (RCSTA<2>), is set if a Stop bit is register (if it is empty). If the transfer is complete, flag detected as clear. Bit FERR and the 9th receive bit are bit, RCIF (PIR1<5>), is set. The actual interrupt can be buffered the same way as the receive data. Reading enabled/disabled by setting/clearing enable bit, RCIE the RCREG will load bits RX9D and FERR with new (PIE1<5>). Flag bit RCIF is a read-only bit which is values, therefore, it is essential for the user to read the cleared by the hardware. It is cleared when the RCREG RCSTA register before reading the RCREG register in order not to lose the old FERR and RX9D information. register has been read and is empty. The RCREG is a double-buffered register (i.e., it is a two-deep FIFO). It FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN FOSC SPBRG 64 MSb RSR Register LSb or Baud Rate Generator 16 Stop (8) 7  1 0 Start RC7/RX/DT Pin Buffer Data RX9 and Control Recovery SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF Data Bus RCIE  2001-2013 Microchip Technology Inc. DS39582C-page 117

PIC16F87XA FIGURE 10-5: ASYNCHRONOUS RECEPTION RX (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word, causing the OERR (Overrun Error) bit to be set. When setting up an Asynchronous Reception, follow 6. Flag bit RCIF will be set when reception is com- these steps: plete and an interrupt will be generated if enable bit RCIE is set. 1. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, 7. Read the RCSTA register to get the ninth bit (if set bit BRGH (Section10.1 “USART Baud enabled) and determine if any error occurred Rate Generator (BRG)”). during reception. 2. Enable the asynchronous serial port by clearing 8. Read the 8-bit received data by reading the bit SYNC and setting bit SPEN. RCREG register. 3. If interrupts are desired, then set enable bit 9. If any error occurred, clear the error by clearing RCIE. enable bit CREN. 4. If 9-bit reception is desired, then set bit RX9. 10. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. 5. Enable the reception by setting bit CREN. TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear. DS39582C-page 118  2001-2013 Microchip Technology Inc.

PIC16F87XA 10.2.3 SETTING UP 9-BIT MODE WITH • Flag bit RCIF will be set when reception is ADDRESS DETECT complete, and an interrupt will be generated if enable bit RCIE was set. When setting up an Asynchronous Reception with • Read the RCSTA register to get the ninth bit and address detect enabled: determine if any error occurred during reception. • Initialize the SPBRG register for the appropriate • Read the 8-bit received data by reading the baud rate. If a high-speed baud rate is desired, RCREG register to determine if the device is set bit BRGH. being addressed. • Enable the asynchronous serial port by clearing • If any error occurred, clear the error by clearing bit SYNC and setting bit SPEN. enable bit CREN. • If interrupts are desired, then set enable bit RCIE. • If the device has been addressed, clear the • Set bit RX9 to enable 9-bit reception. ADDEN bit to allow data bytes and address bytes • Set ADDEN to enable address detect. to be read into the receive buffer and interrupt the • Enable the reception by setting enable bit CREN. CPU. FIGURE 10-6: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN FOSC SPBRG  64 MSb RSR Register LSb or Baud Rate Generator  16 Stop (8) 7  1 0 Start RC7/RX/DT Pin Buffer Data RX9 and Control Recovery 8 SPEN RX9 Enable ADDEN Load of Receive RX9 Buffer ADDEN RSR<8> 8 RX9D RCREG Register FIFO 8 Interrupt RCIF Data Bus RCIE  2001-2013 Microchip Technology Inc. DS39582C-page 119

PIC16F87XA FIGURE 10-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT RC7/RX(p/DinT) Sbtaitrt bit 0 bit 1 bit 8 Stop Sbtaitrt bit 0 bit 8 Stop bit bit Load RSR Bit 8 = 0, Data Byte Bit 8 = 1, Address Byte Word 1 RCREG Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADDEN = 1. FIGURE 10-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST RC7/RX(p/DinT) Sbtaitrt bit 0 bit 1 bit 8 Stop Sbtaitrt bit 0 bit 8 Stop bit bit Load RSR Bit 8 = 1, Address Byte Bit 8 = 0, Data Byte Word 1 RCREG Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADDEN was not updated and still = 0. TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear. DS39582C-page 120  2001-2013 Microchip Technology Inc.

PIC16F87XA 10.3 USART Synchronous Clearing enable bit TXEN during a transmission will Master Mode cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to high- In Synchronous Master mode, the data is transmitted in impedance. If either bit CREN or bit SREN is set during a half-duplex manner (i.e., transmission and reception a transmission, the transmission is aborted and the DT do not occur at the same time). When transmitting data, pin reverts to a high-impedance state (for a reception). the reception is inhibited and vice versa. Synchronous The CK pin will remain an output if bit CSRC is set mode is entered by setting bit, SYNC (TXSTA<4>). In (internal clock). The transmitter logic, however, is not addition, enable bit, SPEN (RCSTA<7>), is set in order reset, although it is disconnected from the pins. In order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to reset the transmitter, the user has to clear bit TXEN. to CK (clock) and DT (data) lines, respectively. The If bit SREN is set (to interrupt an on-going transmission Master mode indicates that the processor transmits the and receive a single word), then after the single word is master clock on the CK line. The Master mode is received, bit SREN will be cleared and the serial port entered by setting bit, CSRC (TXSTA<7>). will revert back to transmitting since bit TXEN is still set. The DT line will immediately switch from High- 10.3.1 USART SYNCHRONOUS MASTER Impedance Receive mode to transmit and start driving. TRANSMISSION To avoid this, bit TXEN should be cleared. The USART transmitter block diagram is shown in In order to select 9-bit transmission, the TX9 Figure10-6. The heart of the transmitter is the Transmit (TXSTA<6>) bit should be set and the ninth bit should (Serial) Shift Register (TSR). The shift register obtains be written to bit TX9D (TXSTA<0>). The ninth bit must its data from the Read/Write Transmit Buffer register, be written before writing the 8-bit data to the TXREG TXREG. The TXREG register is loaded with data in register. This is because a data write to the TXREG can software. The TSR register is not loaded until the last result in an immediate transfer of the data to the TSR bit has been transmitted from the previous load. As register (if the TSR is empty). If the TSR was empty and soon as the last bit is transmitted, the TSR is loaded the TXREG was written before writing the “new” TX9D, with new data from the TXREG (if available). Once the the “present” value of bit TX9D is loaded. TXREG register transfers the data to the TSR register Steps to follow when setting up a Synchronous Master (occurs in one TCYCLE), the TXREG is empty and inter- Transmission: rupt bit, TXIF (PIR1<4>), is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE 1. Initialize the SPBRG register for the appropriate (PIE1<4>). Flag bit TXIF will be set regardless of the baud rate (Section10.1 “USART Baud Rate state of enable bit TXIE and cannot be cleared in soft- Generator (BRG)”). ware. It will reset only when new data is loaded into the 2. Enable the synchronous master serial port by TXREG register. While flag bit TXIF indicates the status setting bits SYNC, SPEN and CSRC. of the TXREG register, another bit, TRMT (TXSTA<1>), 3. If interrupts are desired, set enable bit TXIE. shows the status of the TSR register. TRMT is a read- 4. If 9-bit transmission is desired, set bit TX9. only bit which is set when the TSR is empty. No inter- 5. Enable the transmission by setting bit TXEN. rupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. The 6. If 9-bit transmission is selected, the ninth bit TSR is not mapped in data memory so it is not available should be loaded in bit TX9D. to the user. 7. Start transmission by loading data to the TXREG register. Transmission is enabled by setting enable bit, TXEN (TXSTA<5>). The actual transmission will not occur 8. If using interrupts, ensure that GIE and PEIE until the TXREG register has been loaded with data. (bits 7 and 6) of the INTCON register are set. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock (Figure10-9). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure10-10). This is advantageous when slow baud rates are selected since the BRG is kept in Reset when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally, when transmission is first started, the TSR register is empty so a transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible.  2001-2013 Microchip Technology Inc. DS39582C-page 121

PIC16F87XA TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear. FIGURE 10-9: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX/CK pin Write to TXREG reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words. FIGURE 10-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit DS39582C-page 122  2001-2013 Microchip Technology Inc.

PIC16F87XA 10.3.2 USART SYNCHRONOUS MASTER data. Reading the RCREG register will load bit RX9D RECEPTION with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG in Once Synchronous mode is selected, reception is order not to lose the old RX9D information. enabled by setting either enable bit, SREN (RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data When setting up a Synchronous Master Reception: is sampled on the RC7/RX/DT pin on the falling edge of 1. Initialize the SPBRG register for the appropriate the clock. If enable bit SREN is set, then only a single baud rate (Section10.1 “USART Baud Rate word is received. If enable bit CREN is set, the recep- Generator (BRG)”). tion is continuous until CREN is cleared. If both bits are 2. Enable the synchronous master serial port by set, CREN takes precedence. After clocking the last bit, setting bits SYNC, SPEN and CSRC. the received data in the Receive Shift Register (RSR) 3. Ensure bits CREN and SREN are clear. is transferred to the RCREG register (if it is empty). When the transfer is complete, interrupt flag bit, RCIF 4. If interrupts are desired, then set enable bit (PIR1<5>), is set. The actual interrupt can be enabled/ RCIE. disabled by setting/clearing enable bit, RCIE 5. If 9-bit reception is desired, then set bit RX9. (PIE1<5>). Flag bit RCIF is a read-only bit which is 6. If a single reception is required, set bit SREN. reset by the hardware. In this case, it is reset when the For continuous reception, set bit CREN. RCREG register has been read and is empty. The 7. Interrupt flag bit RCIF will be set when reception RCREG is a double-buffered register (i.e., it is a two- is complete and an interrupt will be generated if deep FIFO). It is possible for two bytes of data to be enable bit RCIE was set. received and transferred to the RCREG FIFO and a 8. Read the RCSTA register to get the ninth bit (if third byte to begin shifting into the RSR register. On the enabled) and determine if any error occurred clocking of the last bit of the third byte, if the RCREG during reception. register is still full, then Overrun Error bit, OERR 9. Read the 8-bit received data by reading the (RCSTA<1>), is set. The word in the RSR will be lost. RCREG register. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in 10. If any error occurred, clear the error by clearing software (by clearing bit CREN). If bit OERR is set, bit CREN. transfers from the RSR to the RCREG are inhibited so 11. If using interrupts, ensure that GIE and PEIE it is essential to clear bit OERR if it is set. The ninth (bits 7 and 6) of the INTCON register are set. receive bit is buffered the same way as the receive TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.  2001-2013 Microchip Technology Inc. DS39582C-page 123

PIC16F87XA FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0. 10.4 USART Synchronous Slave Mode When setting up a Synchronous Slave Transmission, follow these steps: Synchronous Slave mode differs from the Master mode 1. Enable the synchronous slave serial port by set- in the fact that the shift clock is supplied externally at ting bits SYNC and SPEN and clearing bit the RC6/TX/CK pin (instead of being supplied internally CSRC. in Master mode). This allows the device to transfer or receive data while in Sleep mode. Slave mode is 2. Clear bits CREN and SREN. entered by clearing bit, CSRC (TXSTA<7>). 3. If interrupts are desired, then set enable bit TXIE. 10.4.1 USART SYNCHRONOUS SLAVE 4. If 9-bit transmission is desired, then set bit TX9. TRANSMIT 5. Enable the transmission by setting enable bit The operation of the Synchronous Master and Slave TXEN. modes is identical, except in the case of the Sleep mode. 6. If 9-bit transmission is selected, the ninth bit If two words are written to the TXREG and then the should be loaded in bit TX9D. SLEEP instruction is executed, the following will occur: 7. Start transmission by loading data to the TXREG register. a) The first word will immediately transfer to the TSR register and transmit. 8. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. b) The second word will remain in TXREG register. c) Flag bit TXIF will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. e) If enable bit TXIE is set, the interrupt will wake the chip from Sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). DS39582C-page 124  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear. 10.4.2 USART SYNCHRONOUS SLAVE When setting up a Synchronous Slave Reception, RECEPTION follow these steps: The operation of the Synchronous Master and Slave 1. Enable the synchronous master serial port by modes is identical, except in the case of the Sleep setting bits SYNC and SPEN and clearing bit mode. Bit SREN is a “don't care” in Slave mode. CSRC. 2. If interrupts are desired, set enable bit RCIE. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during 3. If 9-bit reception is desired, set bit RX9. Sleep. On completely receiving the word, the RSR reg- 4. To enable reception, set enable bit CREN. ister will transfer the data to the RCREG register and if 5. Flag bit RCIF will be set when reception is enable bit RCIE bit is set, the interrupt generated will complete and an interrupt will be generated if wake the chip from Sleep. If the global interrupt is enable bit RCIE was set. enabled, the program will branch to the interrupt vector 6. Read the RCSTA register to get the ninth bit (if (0004h). enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register. 8. If any error occurred, clear the error by clearing bit CREN. 9. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.  2001-2013 Microchip Technology Inc. DS39582C-page 125

PIC16F87XA NOTES: DS39582C-page 126  2001-2013 Microchip Technology Inc.

PIC16F87XA 11.0 ANALOG-TO-DIGITAL The A/D module has four registers. These registers are: CONVERTER (A/D) MODULE • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) The Analog-to-Digital (A/D) Converter module has five • A/D Control Register 0 (ADCON0) inputs for the 28-pin devices and eight for the 40/44-pin devices. • A/D Control Register 1 (ADCON1) The conversion of an analog input signal results in a The ADCON0 register, shown in Register11-1, con- corresponding 10-bit digital number. The A/D module trols the operation of the A/D module. The ADCON1 has high and low-voltage reference input that is soft- register, shown in Register11-2, configures the func- ware selectable to some combination of VDD, VSS, RA2 tions of the port pins. The port pins can be configured or RA3. as analog inputs (RA3 can also be the voltage reference) or as digital I/O. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To Additional information on using the A/D module can be operate in Sleep, the A/D clock must be derived from found in the PIC® Mid-Range MCU Family Reference the A/D’s internal RC oscillator. Manual (DS33023). REGISTER 11-1: ADCON0 REGISTER (ADDRESS 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold) ADCON1 ADCON0 Clock Conversion <ADCS2> <ADCS1:ADCS0> 0 00 FOSC/2 0 01 FOSC/8 0 10 FOSC/32 0 11 FRC (clock derived from the internal A/D RC oscillator) 1 00 FOSC/4 1 01 FOSC/16 1 10 FOSC/64 1 11 FRC (clock derived from the internal A/D RC oscillator) bit 5-3 CHS2:CHS0: Analog Channel Select bits 000 = Channel 0 (AN0) 001 = Channel 1 (AN1) 010 = Channel 2 (AN2) 011 = Channel 3 (AN3) 100 = Channel 4 (AN4) 101 = Channel 5 (AN5) 110 = Channel 6 (AN6) 111 = Channel 7 (AN7) Note: The PIC16F873A/876A devices only implement A/D channels 0 through 4; the unimplemented selections are reserved. Do not select any unimplemented channels with these devices. bit 2 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared by hardware when the A/D conversion is complete) 0 = A/D conversion not in progress bit 1 Unimplemented: Read as ‘0’ bit 0 ADON: A/D On bit 1 = A/D converter module is powered up 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39582C-page 127

PIC16F87XA REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’. bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in shaded area and in bold) ADCON1 ADCON0 Clock Conversion <ADCS2> <ADCS1:ADCS0> 0 00 FOSC/2 0 01 FOSC/8 0 10 FOSC/32 0 11 FRC (clock derived from the internal A/D RC oscillator) 1 00 FOSC/4 1 01 FOSC/16 1 10 FOSC/64 1 11 FRC (clock derived from the internal A/D RC oscillator) bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits PCFG AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+ VREF- C/R <3:0> 0000 A A A A A A A A VDD VSS 8/0 0001 A A A A VREF+ A A A AN3 VSS 7/1 0010 D D D A A A A A VDD VSS 5/0 0011 D D D A VREF+ A A A AN3 VSS 4/1 0100 D D D D A D A A VDD VSS 3/0 0101 D D D D VREF+ D A A AN3 VSS 2/1 011x D D D D D D D D — — 0/0 1000 A A A A VREF+ VREF- A A AN3 AN2 6/2 1001 D D A A A A A A VDD VSS 6/0 1010 D D A A VREF+ A A A AN3 VSS 5/1 1011 D D A A VREF+ VREF- A A AN3 AN2 4/2 1100 D D D A VREF+ VREF- A A AN3 AN2 3/2 1101 D D D D VREF+ VREF- A A AN3 AN2 2/2 1110 D D D D D D D A VDD VSS 1/0 1111 D D D D VREF+ VREF- D A AN3 AN2 1/2 A = Analog input D = Digital I/O C/R = # of analog input channels/# of A/D voltage references Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: On any device Reset, the port pins that are multiplexed with analog functions (ANx) are forced to be an analog input. DS39582C-page 128  2001-2013 Microchip Technology Inc.

PIC16F87XA The ADRESH:ADRESL registers contain the 10-bit 2. Configure A/D interrupt (if desired): result of the A/D conversion. When the A/D conversion • Clear ADIF bit is complete, the result is loaded into this A/D Result • Set ADIE bit register pair, the GO/DONE bit (ADCON0<2>) is cleared • Set PEIE bit and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure11-1. • Set GIE bit 3. Wait the required acquisition time. After the A/D module has been configured as desired, the selected channel must be acquired before the con- 4. Start conversion: version is started. The analog input channels must • Set GO/DONE bit (ADCON0) have their corresponding TRIS bits selected as inputs. 5. Wait for A/D conversion to complete by either: To determine sample time, see Section11.1 “A/D • Polling for the GO/DONE bit to be cleared Acquisition Requirements”. After this acquisition (interrupts disabled); OR time has elapsed, the A/D conversion can be started. • Waiting for the A/D interrupt To do an A/D Conversion, follow these steps: 6. Read A/D Result register pair (ADRESH:ADRESL), clear bit ADIF if required. 1. Configure the A/D module: 7. For the next conversion, go to step 1 or step 2 • Configure analog pins/voltage reference and as required. The A/D conversion time per bit is digital I/O (ADCON1) defined as TAD. • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) FIGURE 11-1: A/D BLOCK DIAGRAM CHS2:CHS0 111 RE2/AN7(1) 110 RE1/AN6(1) 101 RE0/AN5(1) 100 RA5/AN4 VAIN 011 (Input Voltage) RA3/AN3/VREF+ A/D 010 Converter RA2/AN2/VREF- 001 VDD RA1/AN1 000 VREF+ RA0/AN0 (Reference Voltage) PCFG3:PCFG0 VREF- (Reference Voltage) VSS PCFG3:PCFG0 Note 1: Not available on 28-pin devices.  2001-2013 Microchip Technology Inc. DS39582C-page 129

PIC16F87XA 11.1 A/D Acquisition Requirements decreased. After the analog input channel is selected (changed), this acquisition must be done before the For the A/D converter to meet its specified accuracy, conversion can be started. the charge holding capacitor (CHOLD) must be allowed To calculate the minimum acquisition time, to fully charge to the input channel voltage level. The Equation11-1 may be used. This equation assumes analog input model is shown in Figure11-2. The source that 1/2 LSb error is used (1024 steps for the A/D). The impedance (RS) and the internal sampling switch 1/2 LSb error is the maximum error allowed for the A/D impedance (RSS) directly affect the time required to to meet its specified resolution. charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD); To calculate the minimum acquisition time, TACQ, see see Figure11-2. The maximum recommended the PIC® Mid-Range MCU Family Reference Manual impedance for analog sources is 2.5 k. As the (DS33023). impedance is decreased, the acquisition time may be EQUATION 11-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2 s + TC + [(Temperature – 25°C)(0.05 s/°C)] TC = CHOLD (RIC + RSS + RS) In(1/2047) = - 120 pF (1 k + 7 k + 10 k) In(0.0004885) = 16.47 s TACQ = 2 s + 16.47 s + [(50°C – 25C)(0.05 s/C) = 19.72 s Note1: The reference voltage (VREF) has no effect on the equation since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 2.5 k. This is required to meet the pin leakage specification. FIGURE 11-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC  1K SS RSS CHOLD VA C5 PpIFN VT = 0.6V I±L E5A0K0A nGAE == D12A0C p CFapacitance VSS Legend: CPIN = input capacitance 6V VT = threshold voltage 5V ILEAKAGE = leakage current at the pin due to VDD4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5 6 7 891011 Sampling Switch (k) DS39582C-page 130  2001-2013 Microchip Technology Inc.

PIC16F87XA 11.2 Selecting the A/D Conversion 11.3 Configuring Analog Port Pins Clock The ADCON1 and TRIS registers control the operation The A/D conversion time per bit is defined as TAD. The of the A/D port pins. The port pins that are desired as A/D conversion requires a minimum 12 TAD per 10-bit analog inputs must have their corresponding TRIS bits conversion. The source of the A/D conversion clock is set (input). If the TRIS bit is cleared (output), the digital software selected. The seven possible options for TAD output level (VOH or VOL) will be converted. are: The A/D operation is independent of the state of the • 2 TOSC CHS2:CHS0 bits and the TRIS bits. • 4 TOSC Note 1: When reading the port register, any pin • 8 TOSC configured as an analog input channel will • 16 TOSC read as cleared (a low level). Pins config- ured as digital inputs will convert an analog • 32 TOSC input. Analog levels on a digitally config- • 64 TOSC ured input will not affect the conversion • Internal A/D module RC oscillator (2-6 s) accuracy. For correct A/D conversions, the A/D conversion clock 2: Analog levels on any pin that is defined as (TAD) must be selected to ensure a minimum TAD time a digital input (including the AN7:AN0 of 1.6 s. pins) may cause the input buffer to con- Table11-1 shows the resultant TAD times derived from sume current that is out of the device the device operating frequencies and the A/D clock specifications. source selected. TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (F)) AD Clock Source (TAD) Maximum Device Frequency Operation ADCS2:ADCS1:ADCS0 2 TOSC 000 1.25 MHz 4 TOSC 100 2.5 MHz 8 TOSC 001 5 MHz 16 TOSC 101 10 MHz 32 TOSC 010 20 MHz 64 TOSC 110 20 MHz RC(1, 2, 3) x11 (Note 1) Note 1: The RC source has a typical TAD time of 4 s but can vary between 2-6 s. 2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for Sleep operation. 3: For extended voltage devices (LF), please refer to Section17.0 “Electrical Characteristics”.  2001-2013 Microchip Technology Inc. DS39582C-page 131

PIC16F87XA 11.4 A/D Conversions is aborted, the next acquisition on the selected channel is automatically started. The GO/DONE bit can then be Clearing the GO/DONE bit during a conversion will set to start the conversion. abort the current conversion. The A/D Result register In Figure11-3, after the GO bit is set, the first time pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL segment has a minimum of TCY and a maximum of TAD. registers will continue to contain the value of the last Note: The GO/DONE bit should NOT be set in completed conversion (or the last value written to the the same instruction that turns on the A/D. ADRESH:ADRESL registers). After the A/D conversion FIGURE 11-3: A/D CONVERSION TAD CYCLES TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit ADRES is loaded GO bit is cleared ADIF bit is set Holding capacitor is connected to analog input 11.4.1 A/D RESULT REGISTERS Format Select bit (ADFM) controls this justification. Figure11-4 shows the operation of the A/D result The ADRESH:ADRESL register pair is the location justification. The extra bits are loaded with ‘0’s. When where the 10-bit A/D result is loaded at the completion an A/D result will not overwrite these locations (A/D dis- of the A/D conversion. This register pair is 16 bits wide. able), these registers may be used as two general The A/D module gives the flexibility to left or right justify purpose 8-bit registers. the 10-bit result in the 16-bit result register. The A/D FIGURE 11-4: A/D RESULT JUSTIFICATION 10-bit Result ADFM = 1 ADFM = 0 7 2 1 0 7 0 7 0 7 6 5 0 0000 00 0000 00 ADRESH ADRESL ADRESH ADRESL 10-bit Result 10-bit Result Right Justified Left Justified DS39582C-page 132  2001-2013 Microchip Technology Inc.

PIC16F87XA 11.5 A/D Operation During Sleep Note: For the A/D module to operate in Sleep, the A/D clock source must be set to RC The A/D module can operate during Sleep mode. This (ADCS1:ADCS0 = 11). To allow the con- requires that the A/D clock source be set to RC version to occur during Sleep, ensure the (ADCS1:ADCS0 = 11). When the RC clock source is SLEEP instruction immediately follows the selected, the A/D module waits one instruction cycle instruction that sets the GO/DONE bit. before starting the conversion. This allows the SLEEP instruction to be executed which eliminates all digital 11.6 Effects of a Reset switching noise from the conversion. When the conver- sion is completed, the GO/DONE bit will be cleared and A device Reset forces all registers to their Reset state. the result loaded into the ADRES register. If the A/D This forces the A/D module to be turned off and any interrupt is enabled, the device will wake-up from conversion is aborted. All A/D input pins are configured Sleep. If the A/D interrupt is not enabled, the A/D mod- as analog inputs. ule will then be turned off, although the ADON bit will The value that is in the ADRESH:ADRESL registers is remain set. not modified for a Power-on Reset. The When the A/D clock source is another clock option (not ADRESH:ADRESL registers will contain unknown data RC), a SLEEP instruction will cause the present conver- after a Power-on Reset. sion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. TABLE 11-2: REGISTERS/BITS ASSOCIATED WITH A/D Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 89h(1) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 09h(1) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These registers are not available on 28-pin devices.  2001-2013 Microchip Technology Inc. DS39582C-page 133

PIC16F87XA NOTES: DS39582C-page 134  2001-2013 Microchip Technology Inc.

PIC16F87XA 12.0 COMPARATOR MODULE The CMCON register (Register12-1) controls the com- parator input and output multiplexers. A block diagram The comparator module contains two analog compara- of the various comparator configurations is shown in tors. The inputs to the comparators are multiplexed Figure12-1. with I/O port pins RA0 through RA3, while the outputs are multiplexed to pins RA4 and RA5. The on-chip volt- age reference (Section13.0 “Comparator Voltage Reference Module”) can also be an input to the comparators. REGISTER 12-1: CMCON REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RA3/AN3 C2 VIN- connects to RA2/AN2 0 = C1 VIN- connects to RA0/AN0 C2 VIN- connects to RA1/AN1 bit 2 CM2:CM0: Comparator Mode bits Figure12-1 shows the Comparator modes and CM2:CM0 bit settings. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39582C-page 135

PIC16F87XA 12.1 Comparator Configuration mode is changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Section17.0 “Electrical Characteristics”. tors. The CMCON register is used to select these modes. Figure12-1 shows the eight possible modes. Note: Comparator interrupts should be disabled The TRISA register controls the data direction of the during a Comparator mode change. comparator pins for each mode. If the Comparator Otherwise, a false interrupt may occur. FIGURE 12-1: COMPARATOR I/O OPERATING MODES Comparators Reset Comparators Off (POR Default Value) CM2:CM0 = 000 CM2:CM0 = 111 RA0/AN0 A VIN- RA0/AN0 D VIN- RA3/AN3 A VIN+ C1 Off (Read as ‘0’) RA3/AN3 D VIN+ C1 Off (Read as ‘0’) RA1/AN1 A VIN- RA1/AN1 D VIN- RA2/AN2 A VIN+ C2 Off (Read as ‘0’) RA2/AN2 D VIN+ C2 Off (Read as ‘0’) Two Independent Comparators with Outputs Two Independent Comparators CM2:CM0 = 011 CM2:CM0 = 010 RA0/AN0 A VIN- RA0/AN0 A VIN- RA3/AN3 A VIN+ C1 C1OUT RA3/AN3 A VIN+ C1 C1OUT RA4/T0CKI/C1OUT RA1/AN1 A VIN- RA1/AN1 A VIN- RA2/AN2 A VIN+ C2 C2OUT RA2/AN2 A VIN+ C2 C2OUT RA5/AN4/SS/C2OUT Two Common Reference Comparators Two Common Reference Comparators with Outputs CM2:CM0 = 100 CM2:CM0 = 101 RA0/AN0 A VIN- RA0/AN0 A VIN- RA3/AN3 A VIN+ C1 C1OUT RA3/AN3 A VIN+ C1 C1OUT RA4/T0CKI/C1OUT RA1/AN1 A VIN- RA2/AN2 D VIN+ C2 C2OUT RA1/AN1 A VIN- RA2/AN2 D VIN+ C2 C2OUT RA5/AN4/SS/C2OUT One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM2:CM0 = 001 CM2:CM0 = 110 RA0/AN0 A VIN- RA0/AN0 A CIS = 0 VIN- RA3/AN3 A VIN+ C1 C1OUT RA3/AN3 A CIS = 1 VIN+ C1 C1OUT RA4/T0CKI/C1OUT A RA1/AN1 CIS = 0 VIN- RA1/AN1 D VIN- RA2/AN2 A CIS = 1 VIN+ C2 C2OUT RA2/AN2 D VIN+ C2 Off (Read as ‘0’) CVREF From Comparator VREF Module A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch. DS39582C-page 136  2001-2013 Microchip Technology Inc.

PIC16F87XA 12.2 Comparator Operation 12.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure12-2 along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference for the compara- the digital output. When the analog input at VIN+ is less tors. Section13.0 “Comparator Voltage Reference than the analog input VIN-, the output of the comparator Module” contains a detailed description of the Compar- is a digital low level. When the analog input at VIN+ is ator Voltage Reference module that provides this signal. greater than the analog input VIN-, the output of the The internal reference signal is used when comparators comparator is a digital high level. The shaded areas of are in mode, CM<2:0>=110 (Figure12-1). In this the output of the comparator in Figure12-2 represent mode, the internal voltage reference is applied to the the uncertainty due to input offsets and response time. VIN+ pin of both comparators. 12.3 Comparator Reference 12.4 Comparator Response Time An external or internal reference signal may be used Response time is the minimum time, after selecting a depending on the comparator operating mode. The new reference voltage or input source, before the com- analog signal present at VIN- is compared to the signal parator output has a valid level. If the internal reference at VIN+ and the digital output of the comparator is is changed, the maximum delay of the internal voltage adjusted accordingly (Figure12-2). reference must be considered when using the compar- ator outputs. Otherwise, the maximum delay of the comparators should be used (Section17.0 “Electrical FIGURE 12-2: SINGLE COMPARATOR Characteristics”). 12.5 Comparator Outputs VIN+ + Output The comparator outputs are read through the CMCON VIN- – register. These bits are read-only. The comparator outputs may also be directly output to the RA4 and RA5 I/O pins. When enabled, multiplexors in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the com- parator. The uncertainty of each of the comparators is VIVNI-N– related to the input offset voltage and the response time VIVNIN++ given in the specifications. Figure12-3 shows the comparator output block diagram. The TRISA bits will still function as an output enable/ disable for the RA4 and RA5 pins while in this mode. Output Output The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>). Note1: When reading the Port register, all pins 12.3.1 EXTERNAL REFERENCE SIGNAL configured as analog inputs will read as a When external voltage references are used, the ‘0’. Pins configured as digital inputs will comparator module can be configured to have the com- convert an analog input according to the parators operate from the same or different reference Schmitt Trigger input specification. sources. However, threshold detector applications may 2: Analog levels on any pin defined as a dig- require the same reference. The reference signal must ital input may cause the input buffer to be between VSS and VDD and can be applied to either consume more current than is specified. pin of the comparator(s). 3: RA4 is an open collector I/O pin. When used as an output, a pull-up resistor is required.  2001-2013 Microchip Technology Inc. DS39582C-page 137

PIC16F87XA FIGURE 12-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + - CxINV To RA4 or RA5 Pin Bus Q D Data Read CMCON EN Set CMIF Q D bit From Other EN Comparator CL Read CMCON Reset 12.6 Comparator Interrupts Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a The comparator interrupt flag is set whenever there is read operation is being executed (start of a change in the output value of either comparator. the Q2 cycle), then the CMIF (PIR Software will need to maintain information about the registers) interrupt flag may not get set. status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF The user, in the Interrupt Service Routine, can clear the bit (PIR registers) is the Comparator Interrupt Flag. The interrupt in the following manner: CMIF bit must be reset by clearing it (‘0’). Since it is a) Any read or write of CMCON will end the also possible to write a ‘1’ to this register, a simulated mismatch condition. interrupt may be initiated. b) Clear flag bit CMIF. The CMIE bit (PIE registers) and the PEIE bit (INTCON A mismatch condition will continue to set flag bit CMIF. register) must be set to enable the interrupt. In addition, Reading CMCON will end the mismatch condition and the GIE bit must also be set. If any of these bits are allow flag bit CMIF to be cleared. clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. DS39582C-page 138  2001-2013 Microchip Technology Inc.

PIC16F87XA 12.7 Comparator Operation During 12.9 Analog Input Connection Sleep Considerations When a comparator is active and the device is placed A simplified circuit for an analog input is shown in in Sleep mode, the comparator remains active and the Figure12-4. Since the analog pins are connected to a interrupt is functional if enabled. This interrupt will digital output, they have reverse biased diodes to VDD wake-up the device from Sleep mode when enabled. and VSS. The analog input, therefore, must be between While the comparator is powered up, higher Sleep VSS and VDD. If the input voltage deviates from this currents than shown in the power-down current range by more than 0.6V in either direction, one of the specification will occur. Each operational comparator diodes is forward biased and a latch-up condition may will consume additional current as shown in the com- occur. A maximum source impedance of 10k is rec- parator specifications. To minimize power consumption ommended for the analog sources. Any external com- while in Sleep mode, turn off the comparators, ponent connected to an analog input pin, such as a CM<2:0>=111, before entering Sleep. If the device capacitor or a Zener diode, should have very little wakes up from Sleep, the contents of the CMCON leakage current. register are not affected. 12.8 Effects of a Reset A device Reset forces the CMCON register to its Reset state, causing the comparator module to be in the Comparator Off mode, CM<2:0>=111. This ensures compatibility to the PIC16F87X devices. FIGURE 12-4: ANALOG INPUT MODEL VDD RS < 10K VT = 0.6 V RIC AIN VA C5 PpIFN VT = 0.6 V I±L5E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage  2001-2013 Microchip Technology Inc. DS39582C-page 139

PIC16F87XA TABLE 12-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR Resets 9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111 9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000 0Bh, 8Bh, INTCON GIE/ PEIE/ TMR0IE INTIE RBIE TMR0IF INTIF RBIF 0000 000x 0000 000u 10Bh,18Bh GIEH GIEL 0Dh PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000 8Dh PIE2 — CMIE — — BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. DS39582C-page 140  2001-2013 Microchip Technology Inc.

PIC16F87XA 13.0 COMPARATOR VOLTAGE supply voltage (also referred to as CVRSRC) comes REFERENCE MODULE directly from VDD. It should be noted, however, that the voltage at the top of the ladder is CVRSRC – VSAT, The Comparator Voltage Reference Generator is a where VSAT is the saturation voltage of the power 16-tap resistor ladder network that provides a fixed switch transistor. This reference will only be as voltage reference when the comparators are in mode accurate as the values of CVRSRC and VSAT. ‘110’. A programmable register controls the function of The output of the reference generator may be con- the reference generator. Register13-1 lists the bit nected to the RA2/AN2/VREF-/CVREF pin. This can be functions of the CVRCON register. used as a simple D/A function by the user if a very high- As shown in Figure13-1, the resistor ladder is seg- impedance load is used. The primary purpose of this mented to provide two ranges of CVREF values and has function is to provide a test path for testing the a power-down function to conserve power when the reference generator function. reference is not being used. The comparator reference REGISTER 13-1: CVRCON CONTROL REGISTER (ADDRESS 9Dh) R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on RA2/AN2/VREF-/CVREF pin 0 = CVREF voltage level is disconnected from RA2/AN2/VREF-/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.75 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size bit 4 Unimplemented: Read as ‘0’ bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits 0  VR3:VR0  15 When CVRR = 1: CVREF = (VR<3:0>/ 24)  (CVRSRC) When CVRR = 0: CVREF = 1/4  (CVRSRC) + (VR3:VR0/ 32)  (CVRSRC) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39582C-page 141

PIC16F87XA FIGURE 13-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VDD 16 Stages CVREN 8R R R R R 8R CVRR RA2/AN2/VREF-/CVREF CVROE CVR3 CVREF 16:1 Analog MUX CVR2 Input to CVR1 Comparator CVR0 TABLE 13-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR Resets 9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000 9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference. DS39582C-page 142  2001-2013 Microchip Technology Inc.

PIC16F87XA 14.0 SPECIAL FEATURES OF THE Sleep mode is designed to offer a very low current CPU power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer wake-up or All PIC16F87XA devices have a host of features through an interrupt. intended to maximize system reliability, minimize cost Several oscillator options are also made available to through elimination of external components, provide allow the part to fit the application. The RC oscillator power saving operating modes and offer code option saves system cost while the LP crystal option protection. These are: saves power. A set of configuration bits is used to • Oscillator Selection select various options. • Reset Additional information on special features is available - Power-on Reset (POR) in the PIC® Mid-Range MCU Family Reference Manual - Power-up Timer (PWRT) (DS33023). - Oscillator Start-up Timer (OST) 14.1 Configuration Bits - Brown-out Reset (BOR) • Interrupts The configuration bits can be programmed (read as ‘0’), • Watchdog Timer (WDT) or left unprogrammed (read as ‘1’) to select various device configurations. The erased or unprogrammed • Sleep value of the Configuration Word register is 3FFFh. • Code Protection These bits are mapped in program memory location • ID Locations 2007h. • In-Circuit Serial Programming It is important to note that address 2007h is beyond the • Low-Voltage In-Circuit Serial Programming user program memory space which can be accessed • In-Circuit Debugger only during programming. PIC16F87XA devices have a Watchdog Timer which can be shut-off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscil- lator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nomi- nal) on power-up only. It is designed to keep the part in Reset while the power supply stabilizes. With these two timers on-chip, most applications need no external Reset circuitry.  2001-2013 Microchip Technology Inc. DS39582C-page 143

PIC16F87XA REGISTER 14-1: CONFIGURATION WORD (ADDRESS 2007h)(1) R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 CP — DEBUG WRT1 WRT0 CPD LVP BOREN — — PWRTEN WDTEN FOSC1 FOSC0 bit 13 bit0 bit 13 CP: Flash Program Memory Code Protection bit 1 = Code protection off 0 = All program memory code-protected bit 12 Unimplemented: Read as ‘1’ bit 11 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger bit 10-9 WRT1:WRT0 Flash Program Memory Write Enable bits For PIC16F876A/877A: 11 = Write protection off; all program memory may be written to by EECON control 10 = 0000h to 00FFh write-protected; 0100h to 1FFFh may be written to by EECON control 01 = 0000h to 07FFh write-protected; 0800h to 1FFFh may be written to by EECON control 00 = 0000h to 0FFFh write-protected; 1000h to 1FFFh may be written to by EECON control For PIC16F873A/874A: 11 = Write protection off; all program memory may be written to by EECON control 10 = 0000h to 00FFh write-protected; 0100h to 0FFFh may be written to by EECON control 01 = 0000h to 03FFh write-protected; 0400h to 0FFFh may be written to by EECON control 00 = 0000h to 07FFh write-protected; 0800h to 0FFFh may be written to by EECON control bit 8 CPD: Data EEPROM Memory Code Protection bit 1 = Data EEPROM code protection off 0 = Data EEPROM code-protected bit 7 LVP: Low-Voltage (Single-Supply) In-Circuit Serial Programming Enable bit 1 = RB3/PGM pin has PGM function; low-voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming bit 6 BOREN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled bit 5-4 Unimplemented: Read as ‘1’ bit 3 PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state Note1: The erased (unprogrammed) value of the Configuration Word is 3FFFh. DS39582C-page 144  2001-2013 Microchip Technology Inc.

PIC16F87XA 14.2 Oscillator Configurations FIGURE 14-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR 14.2.1 OSCILLATOR TYPES LP OSC CONFIGURATION) The PIC16F87XA can be operated in four different oscillator modes. The user can program two configura- tion bits (FOSC1 and FOSC0) to select one of these four Clock from OSC1 modes: Ext. System PIC16F87XA • LP Low-Power Crystal Open OSC2 • XT Crystal/Resonator • HS High-Speed Crystal/Resonator • RC Resistor/Capacitor 14.2.2 CRYSTAL OSCILLATOR/CERAMIC TABLE 14-1: CERAMIC RESONATORS RESONATORS Ranges Tested: In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKI and OSC2/CLKO pins Mode Freq. OSC1 OSC2 to establish oscillation (Figure14-1). The PIC16F87XA XT 455 kHz 68-100 pF 68-100 pF oscillator design requires the use of a parallel cut crys- tal. Use of a series cut crystal may give a frequency out 2.0 MHz 15-68 pF 15-68 pF 4.0 MHz 15-68 pF 15-68 pF of the crystal manufacturer’s specifications. When in XT, LP or HS modes, the device can have an external HS 8.0 MHz 10-68 pF 10-68 pF clock source to drive the OSC1/CLKI pin (Figure14-2). 16.0 MHz 10-22 pF 10-22 pF These values are for design guidance only. FIGURE 14-1: CRYSTAL/CERAMIC See notes following Table14-2. RESONATOR OPERATION Resonators Used: (HS, XT OR LP OSC CONFIGURATION) 2.0 MHz Murata Erie CSA2.00MG  0.5% 4.0 MHz Murata Erie CSA4.00MG  0.5% C1(1) OSC1 8.0 MHz Murata Erie CSA8.00MT  0.5% To 16.0 MHz Murata Erie CSA16.00MX  0.5% Internal XTAL RF(3) Logic All resonators used did not have built-in capacitors. OSC2 Sleep R (2) s C2(1) PIC16F87XA Note1: See Table14-1 and Table14-2 for recommended values of C1 and C2. 2: A series resistor (R ) may be required for AT s strip cut crystals. 3: RF varies with the crystal chosen.  2001-2013 Microchip Technology Inc. DS39582C-page 145

PIC16F87XA TABLE 14-2: CAPACITOR SELECTION FOR 14.2.3 RC OSCILLATOR CRYSTAL OSCILLATOR For timing insensitive applications, the “RC” device Crystal Cap. Range Cap. Range option offers additional cost savings. The RC oscillator Osc Type Freq. C1 C2 frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the LP 32 kHz 33 pF 33 pF operating temperature. In addition to this, the oscillator 200 kHz 15 pF 15 pF frequency will vary from unit to unit due to normal pro- cess parameter variation. Furthermore, the difference XT 200 kHz 47-68 pF 47-68 pF in lead frame capacitance between package types will 1 MHz 15 pF 15 pF also affect the oscillation frequency, especially for low 4 MHz 15 pF 15 pF CEXT values. The user also needs to take into account HS 4 MHz 15 pF 15 pF variation due to tolerance of external R and C components used. Figure14-3 shows how the R/C 8 MHz 15-33 pF 15-33 pF combination is connected to the PIC16F87XA. 20 MHz 15-33 pF 15-33 pF These values are for design guidance only. FIGURE 14-3: RC OSCILLATOR MODE See notes following this table. VDD Crystals Used 32 kHz Epson C-001R32.768K-A ± 20 PPM REXT Internal 200 kHz STD XTL 200.000KHz ± 20 PPM OSC1 Clock 1 MHz ECS ECS-10-13-1 ± 50 PPM CEXT PIC16F87XA 4 MHz ECS ECS-40-20-1 ± 50 PPM VSS 8 MHz EPSON CA-301 8.000M-C ± 30 PPM OSC2/CLKO 20 MHz EPSON CA-301 20.000M-C ± 30 PPM FOSC/4 Recommended values: 3 k  REXT  100 k CEXT > 20 pF Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: R may be required in HS mode, as well s as XT mode, to avoid overdriving crystals with low drive level specification. 4: When migrating from other PIC® devices, oscillator performance should be verified. DS39582C-page 146  2001-2013 Microchip Technology Inc.

PIC16F87XA 14.3 Reset state” on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR Reset during Sleep and Brown- The PIC16F87XA differentiates between various kinds out Reset (BOR). They are not affected by a WDT of Reset: wake-up which is viewed as the resumption of normal • Power-on Reset (POR) operation. The TO and PD bits are set or cleared differ- ently in different Reset situations as indicated in • MCLR Reset during normal operation Table14-4. These bits are used in software to deter- • MCLR Reset during Sleep mine the nature of the Reset. See Table14-6 for a full • WDT Reset (during normal operation) description of Reset states of all registers. • WDT Wake-up (during Sleep) A simplified block diagram of the on-chip Reset circuit • Brown-out Reset (BOR) is shown in Figure14-4. Some registers are not affected in any Reset condition. Their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset FIGURE 14-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR Sleep WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out Reset BODEN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1 (1) PWRT On-chip RC OSC 10-bit Ripple Counter Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.  2001-2013 Microchip Technology Inc. DS39582C-page 147

PIC16F87XA 14.4 MCLR 14.6 Power-up Timer (PWRT) PIC16F87XA devices have a noise filter in the MCLR The Power-up Timer provides a fixed 72 ms nominal Reset path. The filter will detect and ignore small time-out on power-up only from the POR. The Power- pulses. up Timer operates on an internal RC oscillator. The chip is kept in Reset as long as the PWRT is active. The It should be noted that a WDT Reset does not drive MCLR pin low. PWRT’s time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable or The behavior of the ESD protection on the MCLR pin disable the PWRT. differs from previous devices of this family. Voltages The power-up time delay will vary from chip to chip due applied to the pin that exceed its specification can result in both Resets and current consumption outside to VDD, temperature and process variation. See Section17.0 “Electrical Characteristics” for details of device specification during the Reset event. For this reason, Microchip recommends that the MCLR pin no (TPWRT, parameter #33). longer be tied directly to VDD. The use of an RCR 14.7 Oscillator Start-up Timer (OST) network, as shown in Figure14-5, is suggested. The Oscillator Start-up Timer (OST) provides a delay of FIGURE 14-5: RECOMMENDED MCLR 1024 oscillator cycles (from OSC1 input) after the CIRCUIT PWRT delay is over (if PWRT is enabled). This helps to ensure that the crystal oscillator or resonator has VDD PIC16F87XA started and stabilized. The OST time-out is invoked only for XT, LP and HS R1(1) modes and only on Power-on Reset or wake-up from Sleep. MCLR R2(2) 14.8 Brown-out Reset (BOR) C1 The configuration bit, BODEN, can enable or disable the Brown-out Reset circuit. If VDD falls below VBOR (parameter D005, about 4V) for longer than TBOR (parameter #35, about 100S), the brown-out situation Note 1: R1 < 40k is recommended to make sure that the voltage drop across R does will reset the device. If VDD falls below VBOR for less not violate the device’s electrical than TBOR, a Reset may not occur. specification. Once the brown-out occurs, the device will remain in 2: R2 > than 1K will limit any current Brown-out Reset until VDD rises above VBOR. The flowing into MCLR from the external Power-up Timer then keeps the device in Reset for capacitor C, in the event of MCLR/VPP TPWRT (parameter #33, about 72mS). If VDD should breakdown due to Electrostatic Discharge (ESD) or Electrical fall below VBOR during TPWRT, the Brown-out Reset Overstress (EOS). process will restart when VDD rises above VBOR with the Power-up Timer Reset. The Power-up Timer is always enabled when the Brown-out Reset circuit is 14.5 Power-on Reset (POR) enabled, regardless of the state of the PWRT configuration bit. A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V-1.7V). To take 14.9 Time-out Sequence advantage of the POR, tie the MCLR pin to VDD through an RC network, as described in Section14.4 On power-up, the time-out sequence is as follows: the “MCLR”. A maximum rise time for VDD is specified. PWRT delay starts (if enabled) when a POR Reset See Section17.0 “Electrical Characteristics” for occurs. Then, OST starts counting 1024 oscillator details. cycles when PWRT ends (LP, XT, HS). When the OST ends, the device comes out of Reset. When the device starts normal operation (exits the Reset condition), device operating parameters (volt- If MCLR is kept low long enough, the time-outs will age, frequency, temperature, etc.) must be met to expire. Bringing MCLR high will begin execution ensure operation. If these conditions are not met, the immediately. This is useful for testing purposes or to device must be held in Reset until the operating condi- synchronize more than one PIC16F87XA device tions are met. Brown-out Reset may be used to meet operating in parallel. the start-up conditions. For additional information, refer Table14-5 shows the Reset conditions for the Status, to application note, AN607, “Power-up Trouble PCON and PC registers, while Table14-6 shows the Shooting” (DS00607). Reset conditions for all the registers. DS39582C-page 148  2001-2013 Microchip Technology Inc.

PIC16F87XA 14.10 Power Control/Status Register When the Brown-out Reset is disabled, the state of the (PCON) BOR bit is unpredictable and is, therefore, not valid at any time. The Power Control/Status Register, PCON, has up to Bit 1 is the Power-on Reset Status bit, POR. It is two bits depending upon the device. cleared on a Power-on Reset and unaffected other- Bit 0 is the Brown-out Reset Status bit, BOR. The BOR wise. The user must set this bit following a Power-on bit is unknown on a Power-on Reset. It must then be set Reset. by the user and checked on subsequent Resets to see if it has been cleared, indicating that a BOR has occurred. TABLE 14-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Wake-up from Oscillator Configuration Brown-out PWRTE = 0 PWRTE = 1 Sleep XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC RC 72 ms — 72 ms — TABLE 14-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during Sleep or Interrupt Wake-up from Sleep Legend: x = don’t care, u = unchanged TABLE 14-5: RESET CONDITIONS FOR SPECIAL REGISTERS Program Status PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --u0 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).  2001-2013 Microchip Technology Inc. DS39582C-page 149

PIC16F87XA TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, MCLR Resets, Wake-up via WDT or Register Devices Brown-out Reset WDT Reset Interrupt W 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu INDF 73A 74A 76A 77A N/A N/A N/A TMR0 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu PCL 73A 74A 76A 77A 0000 0000 0000 0000 PC + 1(2) STATUS 73A 74A 76A 77A 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu PORTA 73A 74A 76A 77A --0x 0000 --0u 0000 --uu uuuu PORTB 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu PORTC 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu PORTD 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu PORTE 73A 74A 76A 77A ---- -xxx ---- -uuu ---- -uuu PCLATH 73A 74A 76A 77A ---0 0000 ---0 0000 ---u uuuu INTCON 73A 74A 76A 77A 0000 000x 0000 000u uuuu uuuu(1) 73A 74A 76A 77A r000 0000 r000 0000 ruuu uuuu(1) PIR1 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu(1) PIR2 73A 74A 76A 77A -0-0 0--0 -0-0 0--0 -u-u u--u(1) TMR1L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu T1CON 73A 74A 76A 77A --00 0000 --uu uuuu --uu uuuu TMR2 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu T2CON 73A 74A 76A 77A -000 0000 -000 0000 -uuu uuuu SSPBUF 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu CCPR1L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 73A 74A 76A 77A --00 0000 --00 0000 --uu uuuu RCSTA 73A 74A 76A 77A 0000 000x 0000 000x uuuu uuuu TXREG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu RCREG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu CCPR2L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu ADRESH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 73A 74A 76A 77A 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu TRISA 73A 74A 76A 77A --11 1111 --11 1111 --uu uuuu TRISB 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu TRISC 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition, r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table14-5 for Reset value for specific condition. DS39582C-page 150  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, MCLR Resets, Wake-up via WDT or Register Devices Brown-out Reset WDT Reset Interrupt TRISD 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu TRISE 73A 74A 76A 77A 0000 -111 0000 -111 uuuu -uuu 73A 74A 76A 77A r000 0000 r000 0000 ruuu uuuu PIE1 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu PIE2 73A 74A 76A 77A -0-0 0--0 -0-0 0--0 -u-u u--u PCON 73A 74A 76A 77A ---- --qq ---- --uu ---- --uu SSPCON2 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu PR2 73A 74A 76A 77A 1111 1111 1111 1111 1111 1111 SSPADD 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu SSPSTAT 73A 74A 76A 77A --00 0000 --00 0000 --uu uuuu TXSTA 73A 74A 76A 77A 0000 -010 0000 -010 uuuu -uuu SPBRG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu CMCON 73A 974 76A 77A 0000 0111 0000 0111 uuuu uuuu CVRCON 73A 74A 76A 77A 000- 0000 000- 0000 uuu- uuuu ADRESL 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 73A 74A 76A 77A 00-- 0000 00-- 0000 uu-- uuuu EEDATA 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu EEADR 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu EEDATH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu EEADRH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu EECON1 73A 74A 76A 77A x--- x000 u--- u000 u--- uuuu EECON2 73A 74A 76A 77A ---- ---- ---- ---- ---- ---- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition, r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table14-5 for Reset value for specific condition. FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset  2001-2013 Microchip Technology Inc. DS39582C-page 151

PIC16F87XA FIGURE 14-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 14-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 14-9: SLOW RISE TIME (MCLR TIED TO VDD VIA RC NETWORK) 5V VDD 0V 1V MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS39582C-page 152  2001-2013 Microchip Technology Inc.

PIC16F87XA 14.11 Interrupts The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in The PIC16F87XA family has up to 15 sources of the INTCON register. interrupt. The Interrupt Control register (INTCON) The peripheral interrupt flags are contained in the records individual interrupt requests in flag bits. It also Special Function Registers, PIR1 and PIR2. The has individual and global interrupt enable bits. corresponding interrupt enable bits are contained in Note: Individual interrupt flag bits are set regard- Special Function Registers, PIE1 and PIE2, and the less of the status of their corresponding peripheral interrupt enable bit is contained in Special mask bit or the GIE bit. Function Register, INTCON. A global interrupt enable bit, GIE (INTCON<7>), When an interrupt is responded to, the GIE bit is enables (if set) all unmasked interrupts or disables (if cleared to disable any further interrupt, the return cleared) all interrupts. When bit GIE is enabled and an address is pushed onto the stack and the PC is loaded interrupt’s flag bit and mask bit are set, the interrupt will with 0004h. Once in the Interrupt Service Routine, the vector immediately. Individual interrupts can be source(s) of the interrupt can be determined by polling disabled through their corresponding enable bits in the interrupt flag bits. The interrupt flag bit(s) must be various registers. Individual interrupt bits are set cleared in software before re-enabling interrupts to regardless of the status of the GIE bit. The GIE bit is avoid recursive interrupts. cleared on Reset. For external interrupt events, such as the INT pin or The “return from interrupt” instruction, RETFIE, exits PORTB change interrupt, the interrupt latency will be the interrupt routine, as well as sets the GIE bit, which three or four instruction cycles. The exact latency re-enables interrupts. depends when the interrupt event occurs. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit, PEIE bit or GIE bit. FIGURE 14-10: INTERRUPT LOGIC EEIF EEIE PSPIF(1) PSPIE(1) ADIF ADIE Wake-up (If in Sleep mode) RCIF TMR0IF RCIE TMR0IE INTF TXIF INTE TXIE Interrupt to CPU RBIF SSPIF RBIE SSPIE CCP1IF PEIE CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE BCLIF BCLIE CMIF CMIE Note 1: PSP interrupt is implemented only on PIC16F874A/877A devices.  2001-2013 Microchip Technology Inc. DS39582C-page 153

PIC16F87XA 14.11.1 INT INTERRUPT 14.12 Context Saving During Interrupts External interrupt on the RB0/INT pin is edge triggered, During an interrupt, only the return PC value is saved either rising if bit INTEDG (OPTION_REG<6>) is set or on the stack. Typically, users may wish to save key reg- falling if the INTEDG bit is clear. When a valid edge isters during an interrupt (i.e., W register and Status appears on the RB0/INT pin, flag bit, INTF register). This will have to be implemented in software. (INTCON<1>), is set. This interrupt can be disabled by For the PIC16F873A/874A devices, the register clearing enable bit, INTE (INTCON<4>). Flag bit INTF W_TEMP must be defined in both Banks 0 and 1 and must be cleared in software in the Interrupt Service must be defined at the same offset from the bank base Routine before re-enabling this interrupt. The INT address (i.e., If W_TEMP is defined at 0x20 in Bank 0, interrupt can wake-up the processor from Sleep if bit it must also be defined at 0xA0 in Bank 1). The regis- INTE was set prior to going into Sleep. The status of ters, PCLATH_TEMP and STATUS_TEMP, are only global interrupt enable bit, GIE, decides whether or not defined in Bank 0. the processor branches to the interrupt vector following wake-up. See Section14.14 “Power-down Mode Since the upper 16 bytes of each bank are common in (Sleep)” for details on Sleep mode. the PIC16F876A/877A devices, temporary holding reg- isters, W_TEMP, STATUS_TEMP and PCLATH_TEMP, 14.11.2 TMR0 INTERRUPT should be placed in here. These 16 locations don’t An overflow (FFh  00h) in the TMR0 register will set require banking and therefore, make it easier for con- flag bit, TMR0IF (INTCON<2>). The interrupt can be text save and restore. The same code shown in enabled/disabled by setting/clearing enable bit, Example14-1 can be used. TMR0IE (INTCON<5>). See Section5.0 “Timer0 Module”. 14.11.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<4>). See Section4.2 “PORTB and the TRISB Register”. EXAMPLE 14-1: SAVING STATUS, W AND PCLATH REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ;Save PCLATH into W CLRF PCLATH ;Page zero, regardless of current page : :(ISR) ;(Insert user code here) : MOVF PCLATH_TEMP, W ;Restore PCLATH MOVWF PCLATH ;Move W into PCLATH SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W DS39582C-page 154  2001-2013 Microchip Technology Inc.

PIC16F87XA 14.13 Watchdog Timer (WDT) WDT time-out period values may be found in Section17.0 “Electrical Characteristics” under The Watchdog Timer is a free running, on-chip RC parameter #31. Values for the WDT prescaler (actually oscillator which does not require any external a postscaler but shared with the Timer0 prescaler) may components. This RC oscillator is separate from the be assigned using the OPTION_REG register. RC oscillator of the OSC1/CLKI pin. That means that the WDT will run even if the clock on the OSC1/CLKI Note1: The CLRWDT and SLEEP instructions and OSC2/CLKO pins of the device has been stopped, clear the WDT and the postscaler, if for example, by execution of a SLEEP instruction. assigned to the WDT and prevent it from timing out and generating a device Reset During normal operation, a WDT time-out generates a condition. device Reset (Watchdog Timer Reset). If the device is in Sleep mode, a WDT time-out causes the device to 2: When a CLRWDT instruction is executed wake-up and continue with normal operation (Watch- and the prescaler is assigned to the WDT, dog Timer Wake-up). The TO bit in the Status register the prescaler count will be cleared but the will be cleared upon a Watchdog Timer time-out. prescaler assignment is not changed. The WDT can be permanently disabled by clearing configuration bit, WDTE (Section14.1 “Configuration Bits”). FIGURE 14-11: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure5-1) 0 M Postscaler 1 WDT Timer U X 8 8-to-1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure5-1) 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register. TABLE 14-7: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register14-1 for operation of these bits.  2001-2013 Microchip Technology Inc. DS39582C-page 155

PIC16F87XA 14.14 Power-down Mode (Sleep) When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to Power-down mode is entered by executing a SLEEP wake-up through an interrupt event, the corresponding instruction. interrupt enable bit must be set (enabled). Wake-up is If enabled, the Watchdog Timer will be cleared but regardless of the state of the GIE bit. If the GIE bit is keeps running, the PD bit (Status<3>) is cleared, the clear (disabled), the device continues execution at the TO (Status<4>) bit is set and the oscillator driver is instruction after the SLEEP instruction. If the GIE bit is turned off. The I/O ports maintain the status they had set (enabled), the device executes the instruction after before the SLEEP instruction was executed (driving the SLEEP instruction and then branches to the inter- high, low or high-impedance). rupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the For lowest current consumption in this mode, place all user should have a NOP after the SLEEP instruction. I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power- 14.14.2 WAKE-UP USING INTERRUPTS down the A/D and disable external clocks. Pull all I/O pins that are high-impedance inputs, high or low When global interrupts are disabled (GIE cleared) and externally, to avoid switching currents caused by any interrupt source has both its interrupt enable bit floating inputs. The T0CKI input should also be at VDD and interrupt flag bit set, one of the following will occur: or VSS for lowest current consumption. The • If the interrupt occurs before the execution of a contribution from on-chip pull-ups on PORTB should SLEEP instruction, the SLEEP instruction will also be considered. complete as a NOP. Therefore, the WDT and WDT The MCLR pin must be at a logic high level (VIHMC). postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. 14.14.1 WAKE-UP FROM SLEEP • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will The device can wake-up from Sleep through one of the immediately wake-up from Sleep. The SLEEP following events: instruction will be completely executed before the 1. External Reset input on MCLR pin. wake-up. Therefore, the WDT and WDT 2. Watchdog Timer wake-up (if WDT was enabled). postscaler will be cleared, the TO bit will be set 3. Interrupt from INT pin, RB port change or and the PD bit will be cleared. peripheral interrupt. Even if the flag bits were checked before executing a External MCLR Reset will cause a device Reset. All other SLEEP instruction, it may be possible for flag bits to events are considered a continuation of program execu- become set before the SLEEP instruction completes. To tion and cause a “wake-up”. The TO and PD bits in the determine whether a SLEEP instruction executed, test Status register can be used to determine the cause of the PD bit. If the PD bit is set, the SLEEP instruction device Reset. The PD bit, which is set on power-up, is was executed as a NOP. cleared when Sleep is invoked. The TO bit is cleared if a To ensure that the WDT is cleared, a CLRWDT WDT time-out occurred and caused wake-up. instruction should be executed before a SLEEP The following peripheral interrupts can wake the device instruction. from Sleep: 1. PSP read or write (PIC16F874/877 only). 2. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 3. CCP Capture mode interrupt. 4. Special event trigger (Timer1 in Asynchronous mode using an external clock). 5. SSP (Start/Stop) bit detect interrupt. 6. SSP transmit or receive in Slave mode (SPI/I2C). 7. USART RX or TX (Synchronous Slave mode). 8. A/D conversion (when A/D clock source is RC). 9. EEPROM write operation completion. 10. Comparator output changes state. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. DS39582C-page 156  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 14-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKO(4) TOST(2) INT pin INTF Flag (INTCON<1>) Interrupt Latency(2) GIE bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h Instruction Fetched Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC - 1) Sleep Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Oscillator mode. 3: GIE = 1 assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. 4: CLKO is not available in these oscillator modes but shown here for timing reference. 14.15 In-Circuit Debugger 14.16 Program Verification/Code Protection When the DEBUG bit in the configuration word is pro- grammed to a ‘0’, the in-circuit debugger functionality is If the code protection bit(s) have not been enabled. This function allows simple debugging programmed, the on-chip program memory can be functions when used with MPLAB® ICD. When the read out for verification purposes. microcontroller has this feature enabled, some of the resources are not available for general use. Table14-8 14.17 ID Locations shows which features are consumed by the background debugger. Four memory locations (2000h-2003h) are designated as ID locations, where the user can store checksum or TABLE 14-8: DEBUGGER RESOURCES other code identification numbers. These locations are not accessible during normal execution but are I/O pins RB6, RB7 readable and writable during program/verify. It is Stack 1 level recommended that only the 4 Least Significant bits of Program Memory Address 0000h must be NOP the ID location are used. Last 100h words Data Memory 0x070 (0x0F0, 0x170, 0x1F0) 0x1EB-0x1EF To use the in-circuit debugger function of the microcon- troller, the design must implement In-Circuit Serial Pro- gramming connections to MCLR/VPP, VDD, GND, RB7 and RB6. This will interface to the in-circuit debugger module available from Microchip or one of the third party development tool companies.  2001-2013 Microchip Technology Inc. DS39582C-page 157

PIC16F87XA 14.18 In-Circuit Serial Programming Note1: The High-Voltage Programming mode is always available, regardless of the state PIC16F87XA microcontrollers can be serially pro- grammed while in the end application circuit. This is of the LVP bit, by applying VIHH to the MCLR pin. simply done with two lines for clock and data and three other lines for power, ground and the programming 2: While in Low-Voltage ICSP mode, the voltage. This allows customers to manufacture boards RB3 pin can no longer be used as a with unprogrammed devices and then program the general purpose I/O pin. microcontroller just before shipping the product. This 3: When using Low-Voltage ICSP Program- also allows the most recent firmware or a custom ming (LVP) and the pull-ups on PORTB firmware to be programmed. are enabled, bit 3 in the TRISB register When using ICSP, the part must be supplied at 4.5V to must be cleared to disable the pull-up on 5.5V if a bulk erase will be executed. This includes RB3 and ensure the proper operation of reprogramming of the code-protect, both from an on the device. state to an off state. For all other cases of ICSP, the part 4: RB3 should not be allowed to float if LVP may be programmed at the normal operating voltages. is enabled. An external pull-down device This means calibration values, unique user IDs or user should be used to default the device to code can be reprogrammed or added. normal operating mode. If RB3 floats For complete details of serial programming, please high, the PIC16F87XA device will enter refer to the “PIC16F87XA Flash Memory Programming Programming mode. Specification” (DS39589). 5: LVP mode is enabled by default on all devices shipped from Microchip. It can be 14.19 Low-Voltage (Single-Supply) disabled by clearing the LVP bit in the ICSP Programming CONFIG register. The LVP bit of the configuration word enables low- 6: Disabling LVP will provide maximum voltage ICSP programming. This mode allows the compatibility to other PIC16CXXX microcontroller to be programmed via ICSP using a devices. VDD source in the operating voltage range. This only means that VPP does not have to be brought to VIHH but If Low-Voltage Programming mode is not used, the LVP can instead be left at the normal operating voltage. In bit can be programmed to a ‘0’ and RB3/PGM becomes this mode, the RB3/PGM pin is dedicated to the pro- a digital I/O pin. However, the LVP bit may only be pro- gramming function and ceases to be a general purpose grammed when programming is entered with VIHH on I/O pin. During programming, VDD is applied to the MCLR. The LVP bit can only be charged when using MCLR pin. To enter Programming mode, VDD must be high voltage on MCLR. applied to the RB3/PGM provided the LVP bit is set. It should be noted, that once the LVP bit is programmed The LVP bit defaults to on (‘1’) from the factory. to ‘0’, only the High-Voltage Programming mode is available and only High-Voltage Programming mode can be used to program the device. When using low-voltage ICSP, the part must be supplied at 4.5V to 5.5V if a bulk erase will be executed. This includes reprogramming of the code-protect bits from an on state to an off state. For all other cases of low-voltage ICSP, the part may be programmed at the normal oper- ating voltage. This means calibration values, unique user IDs or user code can be reprogrammed or added. DS39582C-page 158  2001-2013 Microchip Technology Inc.

PIC16F87XA 15.0 INSTRUCTION SET SUMMARY For example, a “CLRF PORTB” instruction will read PORTB, clear all the data bits, then write the result The PIC16 instruction set is highly orthogonal and is back to PORTB. This example would have the unin- comprised of three basic categories: tended result that the condition that sets the RBIF flag • Byte-oriented operations would be cleared. • Bit-oriented operations TABLE 15-1: OPCODE FIELD • Literal and control operations DESCRIPTIONS Each PIC16 instruction is a 14-bit word divided into an Field Description opcode which specifies the instruction type and one or more operands which further specify the operation of f Register file address (0x00 to 0x7F) the instruction. The formats for each of the categories W Working register (accumulator) is presented in Figure15-1, while the various opcode b Bit address within an 8-bit file register fields are summarized in Table15-1. k Literal field, constant data or label Table15-2 lists the instructions recognized by the x Don't care location (= 0 or 1). MPASM™ Assembler. A complete description of each instruction is also available in the PIC® Mid-Range MCU The assembler will generate code with x = 0. It is the recommended form of use for Family Reference Manual (DS33023). compatibility with all Microchip software tools. For byte-oriented instructions, ‘f’ represents a file d Destination select; d = 0: store result in W, register designator and ‘d’ represents a destination d = 1: store result in file register f. designator. The file register designator specifies which Default is d = 1. file register is to be used by the instruction. PC Program Counter The destination designator specifies where the result of TO Time-out bit the operation is to be placed. If ‘d’ is zero, the result is placed in the W register. If ‘d’ is one, the result is placed PD Power-down bit in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field FIGURE 15-1: GENERAL FORMAT FOR designator which selects the bit affected by the opera- INSTRUCTIONS tion, while ‘f’ represents the address of the file in which the bit is located. Byte-oriented file register operations 13 8 7 6 0 For literal and control operations, ‘k’ represents an OPCODE d f (FILE #) eight or eleven-bit constant or literal value d = 0 for destination W One instruction cycle consists of four oscillator periods; d = 1 for destination f for an oscillator frequency of 4 MHz, this gives a normal f = 7-bit file register address instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a Bit-oriented file register operations conditional test is true, or the program counter is 13 10 9 7 6 0 changed as a result of an instruction. When this occurs, OPCODE b (BIT #) f (FILE #) the execution takes two instruction cycles with the second cycle executed as a NOP. b = 3-bit bit address f = 7-bit file register address Note: To maintain upward compatibility with future PIC16F87XA products, do not use Literal and control operations the OPTION and TRIS instructions. General All instruction examples use the format ‘0xhh’ to 13 8 7 0 represent a hexadecimal number, where ‘h’ signifies a OPCODE k (literal) hexadecimal digit. k = 8-bit immediate value 15.1 READ-MODIFY-WRITE OPERATIONS CALL and GOTO instructions only 13 11 10 0 Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) OPCODE k (literal) operation. The register is read, the data is modified, k = 11-bit immediate value and the result is stored according to either the instruc- tion or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.  2001-2013 Microchip Technology Inc. DS39582C-page 159

PIC16F87XA TABLE 15-2: PIC16F87XA INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add Literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND Literal with W 1 11 1001 kkkk kkkk Z CALL k Call Subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to Address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR Literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move Literal to W 1 11 00xx kkkk kkkk RETFIE - Return from Interrupt 2 00 0000 0000 1001 RETLW k Return with Literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into Standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from Literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR Literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Note: Additional information on the mid-range instruction set is available in the PIC® Mid-Range MCU Family Ref- erence Manual (DS33023). DS39582C-page 160  2001-2013 Microchip Technology Inc.

PIC16F87XA 15.2 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b Operands: 0  k  255 Operands: 0  f  127 0  b  7 Operation: (W) + k  (W) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: The contents of the W register are added to the eight-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared. and the result is placed in the W register. ADDWF Add W and f BSF Bit Set f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b Operands: 0  f  127 Operands: 0  f  127 d  0  b  7 Operation: (W) + (f)  (destination) Operation: 1  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set. with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND Literal with W BTFSS Bit Test f, Skip if Set Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSS f,b Operands: 0  k  255 Operands: 0  f  127 0  b < 7 Operation: (W) .AND. (k)  (W) Operation: skip if (f<b>) = 1 Status Affected: Z Status Affected: None Description: The contents of W register are AND’ed with the eight-bit literal Description: If bit ‘b’ in register ‘f’ is ‘0’, the next ‘k’. The result is placed in the W instruction is executed. register. If bit ‘b’ is ‘1’, then the next instruc- tion is discarded and a NOP is executed instead, making this a 2TCY instruction. ANDWF AND W with f BTFSC Bit Test, Skip if Clear Syntax: [ label ] ANDWF f,d Syntax: [ label ] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 d  0  b  7 Operation: (W) .AND. (f)  (destination) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: AND the W register with register Description: If bit ‘b’ in register ‘f’ is ‘1’, the next ‘f’. If ‘d’ is ‘0’, the result is stored in instruction is executed. the W register. If ‘d’ is ‘1’, the If bit ‘b’ in register ‘f’ is ‘0’, the next result is stored back in register ‘f’. instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.  2001-2013 Microchip Technology Inc. DS39582C-page 161

PIC16F87XA CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<4:3>)  PC<12:11> 1  TO 1  PD Status Affected: None Status Affected: TO, PD Description: Call Subroutine. First, return address (PC+1) is pushed onto Description: CLRWDT instruction resets the the stack. The eleven-bit Watchdog Timer. It also resets the immediate address is loaded into prescaler of the WDT. Status bits, PC bits <10:0>. The upper bits of TO and PD, are set. the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f COMF Complement f Syntax: [ label ] CLRF f Syntax: [ label ] COMF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are cleared and the Z bit is set. complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W DECF Decrement f Syntax: [ label ] CLRW Syntax: [ label ] DECF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: 00h  (W) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: W register is cleared. Zero bit (Z) Description: Decrement register ‘f’. If ‘d’ is ‘0’, is set. the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS39582C-page 162  2001-2013 Microchip Technology Inc.

PIC16F87XA DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. If the result is ‘1’, the next instruc- If the result is ‘1’, the next instruc- tion is executed. If the result is ‘0’, tion is executed. If the result is ‘0’, then a NOP is executed instead, a NOP is executed instead, making making it a 2 TCY instruction. it a 2 TCY instruction. GOTO Unconditional Branch IORLW Inclusive OR Literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<4:3>  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the eight-bit literal ‘k’. The eleven-bit immediate value is The result is placed in the W loaded into PC bits <10:0>. The register. upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Inclusive OR the W register with incremented. If ‘d’ is ‘0’, the result register ‘f’. If ‘d’ is ‘0’, the result is is placed in the W register. If ‘d’ is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’.  2001-2013 Microchip Technology Inc. DS39582C-page 163

PIC16F87XA RLF Rotate Left f through Carry SLEEP Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP Operands: 0  f  127 Operands: None d  [0,1] Operation: 00h  WDT, Operation: See description below 0  WDT prescaler, 1  TO, Status Affected: C 0  PD Description: The contents of register ‘f’ are Status Affected: TO, PD rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is Description: The power-down status bit, PD, placed in the W register. If ‘d’ is ‘1’, is cleared. Time-out status bit, the result is stored back in register ‘f’. TO, is set. Watchdog Timer and its prescaler are cleared. C Register f The processor is put into Sleep mode with the oscillator stopped. RETURN Return from Subroutine SUBLW Subtract W from Literal Syntax: [ label ] RETURN Syntax: [ label ] SUBLW k Operands: None Operands: 0 k 255 Operation: TOS  PC Operation: k - (W) W) Status Affected: None Status Affected: C, DC, Z Description: Return from subroutine. The stack Description: The W register is subtracted (2’s is POPed and the top of the stack complement method) from the (TOS) is loaded into the program eight-bit literal ‘k’. The result is counter. This is a two-cycle placed in the W register. instruction. RRF Rotate Right f through Carry SUBWF Subtract W from f Syntax: [ label ] RRF f,d Syntax: [ label ] SUBWF f,d Operands: 0  f  127 Operands: 0 f 127 d  [0,1] d  [0,1] Operation: See description below Operation: (f) - (W) destination) Status Affected: C Status C, DC, Z Affected: Description: The contents of register ‘f’ are rotated one bit to the right through Description: Subtract (2’s complement method) the Carry flag. If ‘d’ is ‘0’, the W register from register ‘f’. If ‘d’ is result is placed in the W register. ‘0’, the result is stored in the W If ‘d’ is ‘1’, the result is placed register. If ‘d’ is ‘1’, the result is back in register ‘f’. stored back in register ‘f’. C Register f DS39582C-page 164  2001-2013 Microchip Technology Inc.

PIC16F87XA SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f<3:0>)  (destination<7:4>), Operation: (W) .XOR. (f) destination) (f<7:4>)  (destination<3:0>) Status Affected: Z Status Affected: None Description: Exclusive OR the contents of the Description: The upper and lower nibbles of W register with register ‘f’. If ‘d’ is register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is stored in the W ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. placed in register ‘f’. XORLW Exclusive OR Literal with W Syntax: [ label ] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.  2001-2013 Microchip Technology Inc. DS39582C-page 165

PIC16F87XA NOTES: DS39582C-page 166  2001-2013 Microchip Technology Inc.

PIC16F87XA 16.0 DEVELOPMENT SUPPORT 16.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- • Integrated Development Environment controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software based application that contains: • Assemblers/Compilers/Linkers • An interface to debugging tools - MPASMTM Assembler - simulator - MPLAB C17 and MPLAB C18 C Compilers - programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - emulator (sold separately) - MPLAB C30 C Compiler - in-circuit debugger (sold separately) - MPLAB ASM30 Assembler/Linker/Library • A full-featured editor with color coded context • Simulators • A multiple project manager - MPLAB SIM Software Simulator • Customizable data windows with direct edit of contents - MPLAB dsPIC30 Software Simulator • High level source code debugging • Emulators • Mouse over variable inspection - MPLAB ICE 2000 In-Circuit Emulator • Extensive on-line help - MPLAB ICE 4000 In-Circuit Emulator • In-Circuit Debugger The MPLAB IDE allows you to: - MPLAB ICD 2 • Edit your source files (either assembly or C) • Device Programmers • One touch assemble (or compile) and download - PRO MATE® II Universal Device Programmer to PIC MCU emulator and simulator tools (automatically updates all project information) - PICSTART® Plus Development Programmer • Debug using: • Low Cost Demonstration Boards - source files (assembly or C) - PICDEMTM 1 Demonstration Board - absolute listing file (mixed assembly and C) - PICDEM.netTM Demonstration Board - machine code - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective - PICDEM 4 Demonstration Board simulators, through low cost in-circuit debuggers, to - PICDEM 17 Demonstration Board full-featured emulators. This eliminates the learning - PICDEM 18R Demonstration Board curve when upgrading to tools with increasing flexibility - PICDEM LIN Demonstration Board and power. - PICDEM USB Demonstration Board 16.2 MPASM Assembler • Evaluation Kits - KEELOQ® The MPASM assembler is a full-featured, universal - PICDEM MSC macro assembler for all PIC MCUs. - microID® The MPASM assembler generates relocatable object - CAN files for the MPLINK object linker, Intel® standard HEX - PowerSmart® files, MAP files to detail memory usage and symbol ref- erence, absolute LST files that contain source lines and - Analog generated machine code and COFF files for debugging. The MPASM assembler features include: • Integration into MPLAB IDE projects • User defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process  2001-2013 Microchip Technology Inc. DS39582C-page167

PIC16F87XA 16.3 MPLAB C17 and MPLAB C18 16.6 MPLAB ASM30 Assembler, Linker, C Compilers and Librarian The MPLAB C17 and MPLAB C18 Code Development MPLAB ASM30 assembler produces relocatable Systems are complete ANSI C compilers for machine code from symbolic assembly language for Microchip’s PIC17CXXX and PIC18CXXX family of dsPIC30F devices. MPLAB C30 compiler uses the microcontrollers. These compilers provide powerful assembler to produce it’s object file. The assembler integration capabilities, superior code optimization and generates relocatable object files that can then be ease of use not found with other compilers. archived or linked with other relocatable object files and archives to create an executable file. Notable features For easy source level debugging, the compilers provide of the assembler include: symbol information that is optimized to the MPLAB IDE debugger. • Support for the entire dsPIC30F instruction set • Support for fixed-point and floating-point data 16.4 MPLINK Object Linker/ • Command line interface MPLIB Object Librarian • Rich directive set The MPLINK object linker combines relocatable • Flexible macro language objects created by the MPASM assembler and the • MPLAB IDE compatibility MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from precompiled libraries, using 16.7 MPLAB SIM Software Simulator directives from a linker script. The MPLAB SIM software simulator allows code devel- The MPLIB object librarian manages the creation and opment in a PC hosted environment by simulating the modification of library files of pre-compiled code. When PIC series microcontrollers on an instruction level. On a routine from a library is called from a source file, only any given instruction, the data areas can be examined the modules that contain that routine will be linked in or modified and stimuli can be applied from a file, or with the application. This allows large libraries to be user defined key press, to any pin. The execution can used efficiently in many different applications. be performed in Single-Step, Execute Until Break, or The object linker/library features include: Trace mode. • Efficient linking of single libraries instead of many The MPLAB SIM simulator fully supports symbolic smaller files debugging using the MPLAB C17 and MPLAB C18 • Enhanced code maintainability by grouping CCompilers, as well as the MPASM assembler. The related modules together software simulator offers the flexibility to develop and debug code outside of the laboratory environment, • Flexible creation of libraries with easy module making it an excellent, economical software listing, replacement, deletion and extraction development tool. 16.5 MPLAB C30 C Compiler 16.8 MPLAB SIM30 Software Simulator The MPLAB C30 C compiler is a full-featured, ANSI The MPLAB SIM30 software simulator allows code compliant, optimizing compiler that translates standard development in a PC hosted environment by simulating ANSI C programs into dsPIC30F assembly language the dsPIC30F series microcontrollers on an instruction source. The compiler also supports many command- level. On any given instruction, the data areas can be line options and language extensions to take full examined or modified and stimuli can be applied from advantage of the dsPIC30F device hardware capabili- a file, or user defined key press, to any of the pins. ties, and afford fine control of the compiler code generator. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB C30 is distributed with a complete ANSI C MPLAB ASM30 assembler. The simulator runs in either standard library. All library functions have been vali- a Command Line mode for automated tasks, or from dated and conform to the ANSI C library standard. The MPLAB IDE. This high speed simulator is designed to library includes functions for string manipulation, debug, analyze and optimize time intensive DSP dynamic memory allocation, data conversion, time- routines. keeping, and math functions (trigonometric, exponen- tial and hyperbolic). The compiler provides symbolic information for high level source debugging with the MPLAB IDE. DS39582C-page 168  2001-2013 Microchip Technology Inc.

PIC16F87XA 16.9 MPLAB ICE 2000 16.11 MPLAB ICD 2 In-Circuit Debugger High Performance Universal Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 universal in-circuit emulator is USB interface. This tool is based on the Flash PIC intended to provide the product development engineer MCUs and can be used to develop for these and other with a complete microcontroller design tool set for PIC PIC microcontrollers. The MPLAB ICD2 utilizes the in- microcontrollers. Software control of the MPLAB ICE circuit debugging capability built into the Flash devices. 2000 in-circuit emulator is advanced by the MPLAB This feature, along with Microchip’s In-Circuit Serial Integrated Development Environment, which allows ProgrammingTM (ICSPTM) protocol, offers cost effective editing, building, downloading and source debugging in-circuit Flash debugging from the graphical user inter- from a single environment. face of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator sys- Environment. This enables a designer to develop and tem with enhanced trace, trigger and data monitoring debug source code by setting breakpoints, single- features. Interchangeable processor modules allow the stepping and watching variables, CPU status and system to be easily reconfigured for emulation of differ- peripheral registers. Running at full speed enables test- ent processors. The universal architecture of the ing hardware and applications in real-time. MPLAB MPLAB ICE in-circuit emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 in-circuit emulator system has 16.12 PRO MATE II Universal Device been designed as a real-time emulation system with advanced features that are typically found on more Programmer expensive development tools. The PC platform and Microsoft® Windows 32-bit operating system were The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at chosen to best make these features available in a simple, unified application. VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages 16.10 MPLAB ICE 4000 and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the High Performance Universal PROMATE II device programmer can read, verify, and In-Circuit Emulator program PIC devices without a PC connection. It can The MPLAB ICE 4000 universal in-circuit emulator is also set code protection in this mode. intended to provide the product development engineer 16.13 PICSTART Plus Development with a complete microcontroller design tool set for high- Programmer end PIC microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the The PICSTART Plus development programmer is an MPLAB Integrated Development Environment, which easy-to-use, low-cost, prototype programmer. It con- allows editing, building, downloading and source nects to the PC via a COM (RS-232) port. MPLAB debugging from a single environment. Integrated Development Environment software makes The MPLAB ICD 4000 is a premium emulator system, using the programmer simple and efficient. The providing the features of MPLAB ICE 2000, but with PICSTART Plus development programmer supports increased emulation memory and high speed perfor- most PIC devices up to 40 pins. Larger pin count mance for dsPIC30F and PIC18XXXX devices. Its devices, such as the PIC16C92X and PIC17C76X, advanced emulator features include complex triggering may be supported with an adapter socket. The and timing, up to 2 Mb of emulation memory, and the PICSTART Plus development programmer is CE ability to view variables in real-time. compliant. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application.  2001-2013 Microchip Technology Inc. DS39582C-page169

PIC16F87XA 16.14 PICDEM 1 PIC MCU 16.17 PICDEM 3 PIC16C92X Demonstration Board Demonstration Board The PICDEM 1 demonstration board demonstrates the The PICDEM 3 demonstration board supports the capabilities of the PIC16C5X (PIC16C54 to PIC16C923 and PIC16C924 in the PLCC package. All PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, the necessary hardware and software is included to run PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All the demonstration programs. necessary hardware and software is included to run basic demo programs. The sample microcontrollers 16.18 PICDEM 4 8/14/18-Pin provided with the PICDEM 1 demonstration board can Demonstration Board be programmed with a PRO MATE II device program- mer, or a PICSTART Plus development programmer. The PICDEM 4 can be used to demonstrate the capa- bilities of the 8, 14, and 18-pin PIC16XXXX and The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing. A pro- PIC18XXXX MCUs, including the PIC16F818/819, PIC16F87/88, PIC16F62XA and the PIC18F1320 fam- totype area extends the circuitry for additional applica- ily of microcontrollers. PICDEM 4 is intended to show- tion components. Features include an RS-232 case the many features of these low pin count parts, interface, a potentiometer for simulated analog input, including LIN and Motor Control using ECCP. Special push button switches and eight LEDs. provisions are made for low power operation with the 16.15 PICDEM.net Internet/Ethernet supercapacitor circuit, and jumpers allow on-board Demonstration Board hardware to be disabled to eliminate current draw in this mode. Included on the demo board are provisions The PICDEM.net demonstration board is an Internet/ for Crystal, RC or Canned Oscillator modes, a five volt Ethernet demonstration board using the PIC18F452 regulator for use with a nine volt wall adapter or battery, microcontroller and TCP/IP firmware. The board DB-9 RS-232 interface, ICD connector for program- supports any 40-pin DIP device that conforms to the ming via ICSP and development with MPLAB ICD 2, standard pinout used by the PIC16F877 or 2x16 liquid crystal display, PCB footprints for H-Bridge PIC18C452. This kit features a user friendly TCP/IP motor driver, LIN transceiver and EEPROM. Also stack, web server with HTML, a 24L256 Serial included are: header for expansion, eight LEDs, four EEPROM for Xmodem download to web pages into potentiometers, three push buttons and a prototyping Serial EEPROM, ICSP/MPLAB ICD 2 interface con- area. Included with the kit is a PIC16F627A and a nector, an Ethernet interface, RS-232 interface, and a PIC18F1320. Tutorial firmware is included along with 16 x 2 LCD display. Also included is the book and the User’s Guide. CD-ROM “TCP/IP Lean, Web Servers for Embedded Systems,” by Jeremy Bentham. 16.19 PICDEM 17 Demonstration Board 16.16 PICDEM 2 Plus The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Demonstration Board Microchip microcontrollers, including PIC17C752, The PICDEM 2 Plus demonstration board supports PIC17C756A, PIC17C762 and PIC17C766. A pro- many 18-, 28-, and 40-pin microcontrollers, including grammed sample is included. The PRO MATE II device PIC16F87X and PIC18FXX2 devices. All the neces- programmer, or the PICSTART Plus development pro- sary hardware and software is included to run the dem- grammer, can be used to reprogram the device for user onstration programs. The sample microcontrollers tailored application development. The PICDEM 17 provided with the PICDEM 2 demonstration board can demonstration board supports program download and be programmed with a PRO MATE II device program- execution from external on-board Flash memory. A mer, PICSTART Plus development programmer, or generous prototype area is available for user hardware MPLAB ICD 2 with a Universal Programmer Adapter. expansion. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2x16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs, and sample PIC18F452 and PIC16F877 Flash microcontrollers. DS39582C-page 170  2001-2013 Microchip Technology Inc.

PIC16F87XA 16.20 PICDEM 18R PIC18C601/801 16.23 PICDEM USB PIC16C7X5 Demonstration Board Demonstration Board The PICDEM 18R demonstration board serves to assist The PICDEM USB Demonstration Board shows off the development of the PIC18C601/801 family of Microchip capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. It provides hardware implementation microcontrollers. This board provides the basis for of both 8-bit Multiplexed/Demultiplexed and 16-bit future USB products. Memory modes. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory, as well as 16.24 Evaluation and serial EEPROM, allowing access to the wide range of Programming Tools memory types supported by the PIC18C601/801. In addition to the PICDEM series of circuits, Microchip 16.21 PICDEM LIN PIC16C43X has a line of evaluation kits and demonstration software Demonstration Board for these products. • KEELOQ evaluation and programming tools for The powerful LIN hardware and software kit includes a Microchip’s HCS Secure Data Products series of boards and three PIC microcontrollers. The • CAN developers kit for automotive network small footprint PIC16C432 and PIC16C433 are used applications as slaves in the LIN communication and feature on- board LIN transceivers. A PIC16F874 Flash microcon- • Analog design boards and filter design software troller serves as the master. All three microcontrollers • PowerSmart battery charging evaluation/ are programmed with firmware to provide LIN bus com- calibration kits munication. • IrDA® development kit • microID development and rfLabTM development 16.22 PICkitTM 1 Flash Starter Kit software A complete “development system in a box”, the PICkit • SEEVAL® designer kit for memory evaluation and Flash Starter Kit includes a convenient multi-section endurance calculations board for programming, evaluation and development of • PICDEM MSC demo boards for Switching mode 8/14-pin Flash PIC® microcontrollers. Powered via power supply, high power IR driver, delta sigma USB, the board operates under a simple Windows GUI. ADC, and flow rate sensor The PICkit 1 Starter Kit includes the user's guide (on Check the Microchip web page and the latest Product CD ROM), PICkit 1 tutorial software and code for vari- Line Card for the complete list of demonstration and ous applications. Also included are MPLAB® IDE (Inte- evaluation kits. grated Development Environment) software, software and hardware “Tips 'n Tricks for 8-pin Flash PIC® Microcontrollers” Handbook and a USB Interface Cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices.  2001-2013 Microchip Technology Inc. DS39582C-page171

PIC16F87XA NOTES: DS39582C-page 172  2001-2013 Microchip Technology Inc.

PIC16F87XA 17.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias.................................................................................................................-55 to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4).........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +14V Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)20mA Output clamp current, IOK (VO < 0 or VO > VDD)20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk byPORTA, PORTB and PORTE (combined) (Note 3)....................................................200mA Maximum current sourced by PORTA, PORTB and PORTE (combined) (Note 3)...............................................200mA Maximum current sunk by PORTC and PORTD (combined) (Note 3).................................................................200mA Maximum current sourced by PORTC and PORTD (combined) (Note 3)............................................................200mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD - VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. 3: PORTD and PORTE are not implemented on PIC16F873A/876A devices. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2001-2013 Microchip Technology Inc. DS39582C-page 173

PIC16F87XA FIGURE 17-1: PIC16F87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V 5.0V PIC16F87XA 4.5V e g a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 20 MHz Frequency FIGURE 17-2: PIC16LF87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V 4.5V e g 4.0V PIC16LF87XA a t l o 3.5V V 3.0V 2.5V 2.0V 4 MHz 10 MHz Frequency FMAX = (6.0 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application. Note 2: FMAX has a maximum frequency of 10 MHz. DS39582C-page 174  2001-2013 Microchip Technology Inc.

PIC16F87XA 17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) PIC16LF873A/874A/876A/877A Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC16F873A/874A/876A/877A Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Characteristic/ Symbol Min Typ† Max Units Conditions No. Device VDD Supply Voltage D001 16LF87XA 2.0 — 5.5 V All configurations (DC to 10 MHz) D001 16F87XA 4.0 — 5.5 V All configurations D001A VBOR 5.5 V BOR enabled, FMAX = 14 MHz(7) D002 VDR RAM Data Retention — 1.5 — V Voltage(1) D003 VPOR VDD Start Voltage to — VSS — V See Section14.5 “Power-on ensure internal Power-on Reset (POR)” for details Reset signal D004 SVDD VDD Rise Rate to ensure 0.05 — — V/ms See Section14.5 “Power-on internal Power-on Reset Reset (POR)” for details signal D005 VBOR Brown-out Reset 3.65 4.0 4.35 V BODEN bit in configuration word Voltage enabled Legend: Rows with standard voltage device data only are shaded for improved readability. † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.  2001-2013 Microchip Technology Inc. DS39582C-page 175

PIC16F87XA 17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) PIC16LF873A/874A/876A/877A Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC16F873A/874A/876A/877A Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Characteristic/ Symbol Min Typ† Max Units Conditions No. Device IDD Supply Current(2,5) D010 16LF87XA — 0.6 2.0 mA XT, RC osc configurations, FOSC = 4 MHz, VDD = 3.0V D010 16F87XA — 1.6 4 mA XT, RC osc configurations, FOSC = 4 MHz, VDD = 5.5V D010A 16LF87XA — 20 35 A LP osc configuration, FOSC = 32 kHz, VDD = 3.0V, WDT disabled D013 16F87XA — 7 15 mA HS osc configuration, FOSC = 20MHz, VDD = 5.5V D015 IBOR Brown-out — 85 200 A BOR enabled, VDD = 5.0V Reset Current(6) Legend: Rows with standard voltage device data only are shaded for improved readability. † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. DS39582C-page 176  2001-2013 Microchip Technology Inc.

PIC16F87XA 17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) PIC16LF873A/874A/876A/877A Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC16F873A/874A/876A/877A Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Characteristic/ Symbol Min Typ† Max Units Conditions No. Device IPD Power-down Current(3,5) D020 16LF87XA — 7.5 30 A VDD = 3.0V, WDT enabled, -40C to +85C D020 16F87XA — 10.5 42 A VDD = 4.0V, WDT enabled, -40C to +85C 60 A VDD = 4.0V, WDT enabled, -40C to +125C (extended) D021 16LF87XA — 0.9 5 A VDD = 3.0V, WDT disabled, 0C to +70C D021 16F87XA — 1.5 16 A VDD = 4.0V, WDT disabled, -40C to +85C 20 A VDD = 4.0V, WDT disabled, -40C to +125C (extended) D021A 16LF87XA 0.9 5 A VDD = 3.0V, WDT disabled, -40C to +85C D021A 16F87XA 1.5 19 A VDD = 4.0V, WDT disabled, -40C to +85C D023 IBOR Brown-out — 85 200 A BOR enabled, VDD = 5.0V Reset Current(6) Legend: Rows with standard voltage device data only are shaded for improved readability. † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.  2001-2013 Microchip Technology Inc. DS39582C-page 177

PIC16F87XA 17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial DC CHARACTERISTICS -40°C  TA  +125°C for extended Operating voltage VDD range as described in DC specification (Section17.1) Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS — 0.15 VDD V For entire VDD range D030A VSS — 0.8V V 4.5V  VDD 5.5V D031 with Schmitt Trigger buffer VSS — 0.2 VDD V D032 MCLR, OSC1 (in RC mode) VSS — 0.2 VDD V D033 OSC1 (in XT and LP modes) VSS — 0.3V V (Note 1) OSC1 (in HS mode) VSS — 0.3 VDD V Ports RC3 and RC4: — D034 with Schmitt Trigger buffer VSS — 0.3 VDD V For entire VDD range D034A with SMBus -0.5 — 0.6 V For VDD = 4.5 to 5.5V VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V 4.5V  VDD 5.5V D040A 0.25 VDD — VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8 VDD — VDD V For entire VDD range D042 MCLR 0.8 VDD — VDD V D042A OSC1 (in XT and LP modes) 1.6V — VDD V (Note 1) OSC1 (in HS mode) 0.7 VDD — VDD V D043 OSC1 (in RC mode) 0.9 VDD — VDD V Ports RC3 and RC4: D044 with Schmitt Trigger buffer 0.7 VDD — VDD V For entire VDD range D044A with SMBus 1.4 — 5.5 V For VDD = 4.5 to 5.5V D070 IPURB PORTB Weak Pull-up Current 50 250 400 A VDD = 5V, VPIN = VSS, -40°C TO +85°C IIL Input Leakage Current(2, 3) D060 I/O ports — — 1 A VSS VPIN VDD, pin at high-impedance D061 MCLR, RA4/T0CKI — — 5 A VSS VPIN VDD D063 OSC1 — — 5 A VSS VPIN VDD, XT, HS and LP osc configuration * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F87XA be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS39582C-page 178  2001-2013 Microchip Technology Inc.

PIC16F87XA 17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial DC CHARACTERISTICS -40°C  TA  +125°C for extended Operating voltage VDD range as described in DC specification (Section17.1) Param Sym Characteristic Min Typ† Max Units Conditions No. VOL Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKO (RC osc config) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C VOH Output High Voltage D090 I/O ports(3) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D092 OSC2/CLKO (RC osc config) VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C D150* VOD Open-Drain High Voltage — — 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 (RC mode) — — 50 pF D102 CB SCL, SDA (I2C mode) — — 400 pF Data EEPROM Memory D120 ED Endurance 100K 1M — E/W -40C to +85C D121 VDRW VDD for read/write VMIN — 5.5 V Using EECON to read/write, VMIN = min. operating voltage D122 TDEW Erase/write cycle time — 4 8 ms Program Flash Memory D130 EP Endurance 10K 100K — E/W -40C to +85C D131 VPR VDD for read VMIN — 5.5 V VMIN = min. operating voltage D132A VDD for erase/write VMIN — 5.5 V Using EECON to read/write, VMIN = min. operating voltage D133 TPEW Erase/Write cycle time — 4 8 ms * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F87XA be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2001-2013 Microchip Technology Inc. DS39582C-page 179

PIC16F87XA TABLE 17-1: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated) 4.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV D301 VICM Input Common Mode Voltage* 0 - VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio* 55 - — dB 300 TRESP Response Time*(1) — 150 400 ns PIC16F87XA 300A 600 ns PIC16LF87XA 301 TMC2OV Comparator Mode Change to — — 10 s Output Valid* * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from VSS to VDD. TABLE 17-2: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated) 4.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated) Spec Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb Low Range (VRR = 1) — — 1/2 LSb High Range (VRR = 0) D312 VRUR Unit Resistor Value (R)* — 2k —  310 TSET Settling Time*(1) — — 10 s * These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. DS39582C-page 180  2001-2013 Microchip Technology Inc.

PIC16F87XA 17.3 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT Data input hold STO Stop condition STA Start condition FIGURE 17-3: LOAD CONDITIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464 CL = 50pF for all pins except OSC2, but including PORTD and PORTE outputs as ports, 15pF for OSC2 output Note: PORTD and PORTE are not implemented on PIC16F873A/876A devices.  2001-2013 Microchip Technology Inc. DS39582C-page 181

PIC16F87XA FIGURE 17-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 17-3: EXTERNAL CLOCK TIMING REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. FOSC External CLKI Frequency DC — 1 MHz XT and RC Osc mode (Note 1) DC — 20 MHz HS Osc mode DC — 32 kHz LP Osc mode Oscillator Frequency DC — 4 MHz RC Osc mode (Note 1) 0.1 — 4 MHz XT Osc mode 4 — 20 MHz HS Osc mode 5 — 200 kHz LP Osc mode 1 TOSC External CLKI Period 1000 — — ns XT and RC Osc mode (Note 1) 50 — — ns HS Osc mode 5 — — s LP Osc mode Oscillator Period 250 — — ns RC Osc mode (Note 1) 250 — 1 s XT Osc mode 100 — 250 ns HS Osc mode 50 — 250 ns HS Osc mode 31.25 — — s LP Osc mode 2 TCY Instruction Cycle Time 200 TCY DC ns TCY = 4/FOSC (Note 1) 3 TOSL, External Clock in (OSC1) High or 100 — — ns XT oscillator TOSH Low Time 2.5 — — s LP oscillator 15 — — ns HS oscillator 4 TOSR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TOSF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS39582C-page 182  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 17-5: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 18 12 14 19 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure17-3 for load conditions. TABLE 17-4: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 10* TOSH2CKL OSC1  to CLKO  — 75 200 ns (Note 1) 11* TOSH2CKH OSC1  to CLKO  — 75 200 ns (Note 1) 12* TCKR CLKO Rise Time — 35 100 ns (Note 1) 13* TCKF CLKO Fall Time — 35 100 ns (Note 1) 14* TCKL2IOV CLKO  to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15* TIOV2CKH Port In Valid before CLKO  TOSC + 200 — — ns (Note 1) 16* TCKH2IOI Port In Hold after CLKO  0 — — ns (Note 1) 17* TOSH2IOV OSC1  (Q1 cycle) to Port Out Valid — 100 255 ns 18* TOSH2IOI OSC1  (Q2 cycle) to Port Input Standard (F) 100 — — ns Invalid (I/O in hold time) Extended (LF) 200 — — ns 19* TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 0 — — ns 20* TIOR Port Output Rise Time Standard (F) — 10 40 ns Extended (LF) — — 145 ns 21* TIOF Port Output Fall Time Standard (F) — 10 40 ns Extended (LF) — — 145 ns 22††* TINP INT pin High or Low Time TCY — — ns 23††* TRBP RB7:RB4 Change INT High or Low Time TCY — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode where CLKO output is 4 x TOSC.  2001-2013 Microchip Technology Inc. DS39582C-page 183

PIC16F87XA FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure17-3 for load conditions. FIGURE 17-7: BROWN-OUT RESET TIMING VDD VBOR 35 TABLE 17-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +85°C 31* TWDT Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +85°C (no prescaler) 32 TOST Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33* TPWRT Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C 34 TIOZ I/O High-Impedance from MCLR Low — — 2.1 s or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 100 — — s VDD  VBOR (D005) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS39582C-page 184  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure17-3 for load conditions. TABLE 17-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* TT0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4,..., 256) N 45* TT1H T1CKI High Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet Time Synchronous, Standard(F) 15 — — ns parameter 47 Prescaler = 2, 4, 8 Extended(LF) 25 — — ns Asynchronous Standard(F) 30 — — ns Extended(LF) 50 — — ns 46* TT1L T1CKI Low Time Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet Synchronous, Standard(F) 15 — — ns parameter 47 Prescaler = 2, 4, 8 Extended(LF) 25 — — ns Asynchronous Standard(F) 30 — — ns Extended(LF) 50 — — ns 47* TT1P T1CKI Input Synchronous Standard(F) Greater of: — — ns N = prescale value Period 30 or TCY + 40 (1, 2, 4, 8) N Extended(LF) Greater of: N = prescale value 50 or TCY + 40 (1, 2, 4, 8) N Asynchronous Standard(F) 60 — — ns Extended(LF) 100 — — ns FT1 Timer1 Oscillator Input Frequency Range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZTMR1 Delay from External Clock Edge to Timer Increment 2 TOSC — 7 TOSC — * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2001-2013 Microchip Technology Inc. DS39582C-page 185

PIC16F87XA FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure17-3 for load conditions. TABLE 17-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param Symbol Characteristic Min Typ† Max Units Conditions No. 50* TCCL CCP1 and CCP2 No Prescaler 0.5 TCY + 20 — — ns Input Low Time Standard(F) 10 — — ns With Prescaler Extended(LF) 20 — — ns 51* TCCH CCP1 and CCP2 No Prescaler 0.5 TCY + 20 — — ns Input High Time Standard(F) 10 — — ns With Prescaler Extended(LF) 20 — — ns 52* TCCP CCP1 and CCP2 Input Period 3 TCY + 40 — — ns N = prescale value N (1, 4 or 16) 53* TCCR CCP1 and CCP2 Output Rise Time Standard(F) — 10 25 ns Extended(LF) — 25 50 ns 54* TCCF CCP1 and CCP2 Output Fall Time Standard(F) — 10 25 ns Extended(LF) — 25 45 ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS39582C-page 186  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 17-10: PARALLEL SLAVE PORT TIMING (PIC16F874A/877A ONLY) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure17-3 for load conditions. TABLE 17-8: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874A/877A ONLY) Param Symbol Characteristic Min Typ† Max Units Conditions No. 62 TDTV2WRH Data In Valid before WR  or CS  (setup time) 20 — — ns 63* TWRH2DTI WR  or CS  to Data–in Invalid Standard(F) 20 — — ns (hold time) Extended(LF) 35 — — ns 64 TRDL2DTV RD  and CS  to Data–out Valid — — 80 ns 65 TRDH2DTI RD  or CS  to Data–out Invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2001-2013 Microchip Technology Inc. DS39582C-page 187

PIC16F87XA FIGURE 17-11: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb Bit 6 - - - - - -1 LSb 75, 76 SDI MSb In Bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure17-3 for load conditions. FIGURE 17-12: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb Bit 6 - - - - - -1 LSb 75, 76 SDI MSb In Bit 6 - - - -1 LSb In 74 Note: Refer to Figure17-3 for load conditions. DS39582C-page 188  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 17-13: SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb Bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In Bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure17-3 for load conditions. FIGURE 17-14: SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb Bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In Bit 6 - - - -1 LSb In 74 Note: Refer to Figure17-3 for load conditions.  2001-2013 Microchip Technology Inc. DS39582C-page 189

PIC16F87XA TABLE 17-9: SPI MODE REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 70* TSSL2SCH, SS  to SCK  or SCK  Input TCY — — ns TSSL2SCL 71* TSCH SCK Input High Time (Slave mode) TCY + 20 — — ns 72* TSCL SCK Input Low Time (Slave mode) TCY + 20 — — ns 73* TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — — ns TDIV2SCL 74* TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — — ns TSCL2DIL 75* TDOR SDO Data Output Rise Time Standard(F) — 10 25 ns Extended(LF) — 25 50 ns 76* TDOF SDO Data Output Fall Time — 10 25 ns 77* TSSH2DOZ SS  to SDO Output High-Impedance 10 — 50 ns 78* TSCR SCK Output Rise Time Standard(F) — 10 25 ns (Master mode) Extended(LF) — 25 50 ns 79* TSCF SCK Output Fall Time (Master mode) — 10 25 ns 80* TSCH2DOV, SDO Data Output Valid after Standard(F) — — 50 ns TSCL2DOV SCK Edge Extended(LF) — — 145 81* TDOV2SCH, SDO Data Output Setup to SCK Edge TCY — — ns TDOV2SCL 82* TSSL2DOV SDO Data Output Valid after SS  Edge — — 50 ns 83* TSCH2SSH, SS after SCK Edge 1.5 TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 17-15: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure17-3 for load conditions. DS39582C-page 190  2001-2013 Microchip Technology Inc.

PIC16F87XA TABLE 17-10: I2C BUS START/STOP BITS REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 90 TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Start Setup time 400 kHz mode 600 — — condition 91 THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first clock pulse Hold time 400 kHz mode 600 — — is generated 92 TSU:STO Stop condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO Stop condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — FIGURE 17-16: I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure17-3 for load conditions.  2001-2013 Microchip Technology Inc. DS39582C-page 191

PIC16F87XA TABLE 17-11: I2C BUS DATA REQUIREMENTS Param Sym Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s SSP Module 0.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s SSP Module 0.5 TCY — 102 TR SDA and SCL Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1 CB 300 ns Cb is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup 100 kHz mode 4.7 — s Only relevant for Repeated Start Time 400 kHz mode 0.6 — s condition 91 THD:STA Start Condition Hold 100 kHz mode 4.0 — s After this period, the first clock Time 400 kHz mode 0.6 — s pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup 100 kHz mode 4.7 — s Time 400 kHz mode 0.6 — s 109 TAA Output Valid from 100 kHz mode — 3500 ns (Note 1) Clock 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before 400 kHz mode 1.3 — s a new transmission can start CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement that, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR MAX. + TSU:DAT=1000+250=1250ns (according to the standard mode I2C bus specification), before the SCL line is released. DS39582C-page 192  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 17-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK 121 pin 121 RC7/RX/DT pin 120 122 Note: Refer to Figure17-3 for load conditions. TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid Standard(F) — — 80 ns Extended(LF) — — 100 ns 121 TCKRF Clock Out Rise Time and Fall Time Standard(F) — — 45 ns (Master mode) Extended(LF) — — 50 ns 122 TDTRF Data Out Rise Time and Fall Time Standard(F) — — 45 ns Extended(LF) — — 50 ns † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 17-18: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure17-3 for load conditions. TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Setup before CK  (DT setup time) 15 — — ns 126 TCKL2DTL Data Hold after CK  (DT hold time) 15 — — ns † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.  2001-2013 Microchip Technology Inc. DS39582C-page 193

PIC16F87XA TABLE 17-14: A/D CONVERTER CHARACTERISTICS:PIC16F873A/874A/876A/877A (INDUSTRIAL) PIC16LF873A/874A/876A/877A (INDUSTRIAL) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 10-bits bit VREF = VDD = 5.12V, VSS  VAIN  VREF A03 EIL Integral Linearity Error — — < ± 1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A04 EDL Differential Linearity Error — — < ± 1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A06 EOFF Offset Error — — < ± 2 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A07 EGN Gain Error — — < ± 1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A10 — Monotonicity — guaranteed(3) — — VSS  VAIN  VREF A20 VREF Reference Voltage (VREF+ – VREF-) 2.0 — VDD + 0.3 V A21 VREF+ Reference Voltage High AVDD – 2.5V AVDD + 0.3V V A22 VREF- Reference Voltage Low AVSS – 0.3V VREF+ – 2.0V V A25 VAIN Analog Input Voltage VSS – 0.3V — VREF + 0.3V V A30 ZAIN Recommended Impedance of — — 2.5 k (Note 4) Analog Voltage Source A40 IAD A/D Conversion PIC16F87XA — 220 — A Average current Current (VDD) PIC16LF87XA — 90 — A consumption when A/D is on (Note 1) A50 IREF VREF Input Current (Note 2) — — 5 A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section11.1 “A/D Acquisition Requirements”. — — 150 A During A/D conversion cycle * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 4: Maximum allowed impedance for analog voltage source is 10 kThis requires higher acquisition time. DS39582C-page 194  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 17-19: A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 132 A/D DATA 9 8 7   2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE Sampling Stopped SAMPLE Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 17-15: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D Clock Period PIC16F87XA 1.6 — — s TOSC based, VREF  3.0V PIC16LF87XA 3.0 — — s TOSC based, VREF  2.0V PIC16F87XA 2.0 4.0 6.0 s A/D RC mode PIC16LF87XA 3.0 6.0 9.0 s A/D RC mode 131 TCNV Conversion Time (not including S/H time) — 12 TAD (Note 1) 132 TACQ Acquisition Time (Note 2) 40 — s 10* — — s The minimum time is the amplifier settling time. This may be used if the “new” input volt- age has not changed by more than 1 LSb (i.e., 20.0mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D Clock Start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section11.1 “A/D Acquisition Requirements” for minimum conditions.  2001-2013 Microchip Technology Inc. DS39582C-page 195

PIC16F87XA NOTES: DS39582C-page 196  2001-2013 Microchip Technology Inc.

PIC16F87XA 18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean+3) or (mean–3) respectively, where  is a standard deviation, over the whole temperature range. FIGURE 18-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) 7 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 6 Minimum: mean – 3 (-40°C to +125°C) 5.5V 5 5.0V 4.5V 4 mA) 4.0V (D D I 3 3.5V 3.0V 2 2.5V 2.0V 1 0 4 6 8 10 12 14 16 18 20 FOSC (MHz) FIGURE 18-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) 8 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 7 Minimum: mean – 3 (-40°C to +125°C) 5.5V 6 5.0V 4.5V 5 A) 4.0V m (D 4 3.5V D I 3.0V 3 2.5V 2 2.0V 1 0 4 6 8 10 12 14 16 18 20 FOSC (MHz)  2001-2013 Microchip Technology Inc. DS39582C-page 197

PIC16F87XA FIGURE 18-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.5V 1.4 5.0V 1.2 4.5V 4.0V A) 1.0 m (D 3.5V ID 0.8 3.0V 2.5V 0.6 2.0V 0.4 0.2 0.0 0 500 1000 1500 2000 2500 3000 3500 4000 FOSC (MHz) FIGURE 18-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 2.5 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.0 5.5V 5.0V 1.5 4.5V A) m 4.0V (D D I 3.5V 1.0 3.0V 2.5V 2.0V 0.5 0.0 0 500 1000 1500 2000 2500 3000 3500 4000 FOSC (MHz) DS39582C-page 198  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 18-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 70 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 60 Minimum: mean – 3 (-40°C to +125°C) 5.5V 50 5.0V 4.5V 40 A) 4.0V u (DD 3.5V I 30 3.0V 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 18-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 120 Typical: statistical mean @ 25°C 5.5V Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 100 5.0V 4.5V 80 4.0V A) (uD 60 3.5V D I 3.0V 2.5V 40 2.0V 20 0 20 30 40 50 60 70 80 90 100 FOSC (kHz)  2001-2013 Microchip Technology Inc. DS39582C-page 199

PIC16F87XA FIGURE 18-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, +25C) 4.5 Operation above 4 MHz is not recommended 4.0 5.1 kOhm 3.5 3.0 z) 2.5 MH 10 kOhm q ( e Fr 2.0 1.5 1.0 0.5 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, +25C) 2.5 2.0 3.3 kOhm 1.5 z) 5.1 kOhm H M q ( e Fr 1.0 10 kOhm 0.5 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39582C-page 200  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 18-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300pF, +25C) 0.9 0.8 3.3 kOhm 0.7 0.6 5.1 kOhm z) 0.5 H M q ( e Fr 0.4 10 kOhm 0.3 0.2 0.1 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-10: IPD vs. VDD, -40C TO +125C (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Max (125°C) 10 Max (85°C) 1 A) u (D P I 0.1 0.01 Typ (25°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2001-2013 Microchip Technology Inc. DS39582C-page 201

PIC16F87XA FIGURE 18-11: TYPICAL AND MAXIMUMITMR1 vs. VDD OVER TEMPERATURE (-10C TO +70C, TIMER1 WITH OSCILLATOR, XTAL = 32kHz, C1 AND C2 = 47pF) 14 Typical: statistical mean @ 25°C 12 Maximum: mean + 3 (-10°C to +70°C) Minimum: mean – 3 (-10°C to +70°C) MMaaxx ( +(7700C°C)) 10 8 A)A) u TTypyp ( +(2255C°C)) ( (DD PP II 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-12: TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED) 100 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) Max (+125°C) 10 Max (+85°C) A) u (D Typ (+25°C) P I 1 0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39582C-page 202  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 18-13: IBOR vs. VDD OVER TEMPERATURE 1,000 Max (125°C) Typ (25°C) Device in Indeterminant Sleep State Device in Reset A) (D 100 D I Note: Device current in Reset Max (125°C) depends on oscillator mode, frequency and circuit. Typical: statistical mean @ 25°C Typ (25°C) Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO +125C) 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 40 Minimum: mean – 3 (-40°C to +125°C) 35 Max (125°C) s) 30 m d ( o eri 25 T P Typ D (25°C) W 20 Min 15 (-40°C) 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2001-2013 Microchip Technology Inc. DS39582C-page 203

PIC16F87XA FIGURE 18-15: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40C TO +125C) 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 40 125°C 35 85°C s) 30 m od ( 25°C eri 25 P T D W 20 -40°C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C) 5.5 5.0 4.5 4.0 Max 3.5 Typ (25°C) V) 3.0 (H O V 2.5 Min 2.0 Typical: statistical mean @ 25°C 1.5 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) DS39582C-page 204  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 18-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C) 3.5 Typical: statistical mean @ 25°C 3.0 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.5 Max 2.0 (V)H Typ (25°C) O V 1.5 Min 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 18-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C) 1.0 0.9 Max (125°C) Typical: statistical mean @ 25°C 0.8 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.7 0.6 Max (85°C) V) (L 0.5 O V Typ (25°C) 0.4 0.3 Min (-40°C) 0.2 0.1 0.0 0 5 10 15 20 25 IOL (-mA)  2001-2013 Microchip Technology Inc. DS39582C-page 205

PIC16F87XA FIGURE 18-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C) 3.0 Max (125°C) 2.5 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.0 V) (L 1.5 O V Max (85°C) 1.0 Typ (25°C) 0.5 Min (-40°C) 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 18-20: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C) 1.5 1.4 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.3 VTH Max (-40°C) 1.2 1.1 VTH Typ (25°C) V) (N 1.0 VI 0.9 VTH Min (125°C) 0.8 0.7 0.6 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39582C-page 206  2001-2013 Microchip Technology Inc.

PIC16F87XA FIGURE 18-21: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C) 4.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 3.5 Minimum: mean – 3 (-40°C to +125°C) VIH Max (125°C) 3.0 2.5 VIH Min (-40°C) V) (N 2.0 VI VIL Max (-40°C) 1.5 1.0 VIL Min (125°C) 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-22: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C) 3.5 VIH Max Typical: statistical mean @ 25°C 3.0 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.5 2.0 VVIILL MMaaxx V) (N VI VIH Min 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2001-2013 Microchip Technology Inc. DS39582C-page 207

PIC16F87XA FIGURE 18-23: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C) 4 3.5 -4-400°CC SB) 3 L arity ( +2255C°C e 2.5 n nli No +8855C°C al 2 gr e nt al or I 1.5 nti e er Diff 1 0.5 1+2152C5°C 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD and VREFH (V) FIGURE 18-24: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40C TO +125C) 3 2.5 B) S L y ( arilt 2 e n nli o N al 1.5 gr e nt or I MMaaxx ((--4400°CC t oto 1 +2152C5)°C) al nti 1 e er TTyypp ((+2255C°)C) Diff 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V) DS39582C-page 208  2001-2013 Microchip Technology Inc.

PIC16F87XA 19.0 PACKAGING INFORMATION 19.1 Package Marking Information 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX PIC16F877A/P XXXXXXXXXXXXXXXXXX 0310017 XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP Example XXXXXXXXXX PIC16F877A XXXXXXXXXX /PT XXXXXXXXXX 0310017 YYWWNNN 44-Lead PLCC Example XXXXXXXXXX PIC16F877A XXXXXXXXXX -20/L XXXXXXXXXX 0310017 YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2001-2013 Microchip Technology Inc. DS39582C-page 209

PIC16F87XA Package Marking Information (Cont’d) 44-Lead QFN Example XXXXXXXXXX PIC16F877A XXXXXXXXXX -I/ML XXXXXXXXXX 0310017 YYWWNNN 28-Lead PDIP (Skinny DIP) Example XXXXXXXXXXXXXXXXX PIC16F876A/SP XXXXXXXXXXXXXXXXX 0310017 YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC16F876A/SO XXXXXXXXXXXXXXXXXXXX 0310017 XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP Example XXXXXXXXXXXX PIC16F876A/ XXXXXXXXXXXX SS YYWWNNN 0310017 28-Lead QFN Example XXXXXXXX 16F873A XXXXXXXX -I/ML YYWWNNN 0310017 DS39582C-page 210  2001-2013 Microchip Technology Inc.

PIC16F87XA 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2  n 1 E A A2 L c B1  A1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 40 40 Pitch p .100 2.54 Top to Seating Plane A .160 .175 .190 4.06 4.45 4.83 Molded Package Thickness A2 .140 .150 .160 3.56 3.81 4.06 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .595 .600 .625 15.11 15.24 15.88 Molded Package Width E1 .530 .545 .560 13.46 13.84 14.22 Overall Length D 2.045 2.058 2.065 51.94 52.26 52.45 Tip to Seating Plane L .120 .130 .135 3.05 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .030 .050 .070 0.76 1.27 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .620 .650 .680 15.75 16.51 17.27 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016  2001-2013 Microchip Technology Inc. DS39582C-page 211

PIC16F87XA 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45  A c   A1 A2 L (F) Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .031 0.80 Pins per Side n1 11 11 Overall Height A .039 .043 .047 1.00 1.10 1.20 Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Foot Length L .018 .024 .030 0.45 0.60 0.75 Footprint (Reference) (F) .039 1.00 Foot Angle  0 3.5 7 0 3.5 7 Overall Width E .463 .472 .482 11.75 12.00 12.25 Overall Length D .463 .472 .482 11.75 12.00 12.25 Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10 Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .012 .015 .017 0.30 0.38 0.44 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076 DS39582C-page 212  2001-2013 Microchip Technology Inc.

PIC16F87XA 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 1 2 CH2 x 45 CH1 x 45 A3  A2 A 35 B1 c B A1  p E2 D2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .050 1.27 Pins per Side n1 11 11 Overall Height A .165 .173 .180 4.19 4.39 4.57 Molded Package Thickness A2 .145 .153 .160 3.68 3.87 4.06 Standoff § A1 .020 .028 .035 0.51 0.71 0.89 Side 1 Chamfer Height A3 .024 .029 .034 0.61 0.74 0.86 Corner Chamfer 1 CH1 .040 .045 .050 1.02 1.14 1.27 Corner Chamfer (others) CH2 .000 .005 .010 0.00 0.13 0.25 Overall Width E .685 .690 .695 17.40 17.53 17.65 Overall Length D .685 .690 .695 17.40 17.53 17.65 Molded Package Width E1 .650 .653 .656 16.51 16.59 16.66 Molded Package Length D1 .650 .653 .656 16.51 16.59 16.66 Footprint Width E2 .590 .620 .630 14.99 15.75 16.00 Footprint Length D2 .590 .620 .630 14.99 15.75 16.00 Lead Thickness c .008 .011 .013 0.20 0.27 0.33 Upper Lead Width B1 .026 .029 .032 0.66 0.74 0.81 Lower Lead Width B .013 .020 .021 0.33 0.51 0.53 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-048  2001-2013 Microchip Technology Inc. DS39582C-page 213

PIC16F87XA 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E EXPOSED METAL PAD p D D2 2 B 1 n OPTIONAL PIN 1 PIN 1 INDEX ON INDEX ON E2 TOP MARKING EXPOSED PAD L TOP VIEW BOTTOM VIEW A A1 A3 Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .026 BSC 0.65 BSC Overall Height A .031 .035 .039 0.80 0.90 1.00 Standoff A1 .000 .001 .002 0 0.02 0.05 Base Thickness A3 .010 REF 0.25 REF Overall Width E .315 BSC 8.00 BSC Exposed Pad Width E2 .262 .268 .274 6.65 6.80 6.95 Overall Length D .315 BSC 8.00 BSC Exposed Pad Length D2 .262 .268 .274 6.65 6.80 6.95 Lead Width B .012 .013 .013 0.30 0.33 0.35 Lead Length L .014 .016 .018 0.35 0.40 0.45 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: M0-220 Drawing No. C04-103 DS39582C-page 214  2001-2013 Microchip Technology Inc.

PIC16F87XA 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1  E A2 A L c  A1 B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 8.26 Molded Package Width E1 .275 .285 .295 6.99 7.24 7.49 Overall Length D 1.345 1.365 1.385 34.16 34.67 35.18 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .040 .053 .065 1.02 1.33 1.65 Lower Lead Width B .016 .019 .022 0.41 0.48 0.56 Overall Row Spacing § eB .320 .350 .430 8.13 8.89 10.92 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070  2001-2013 Microchip Technology Inc. DS39582C-page 215

PIC16F87XA 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1 h  45 c A A2   L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .288 .295 .299 7.32 7.49 7.59 Overall Length D .695 .704 .712 17.65 17.87 18.08 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle Top  0 4 8 0 4 8 Lead Thickness c .009 .011 .013 0.23 0.28 0.33 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top  0 12 15 0 12 15 Mold Draft Angle Bottom  0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 DS39582C-page 216  2001-2013 Microchip Technology Inc.

PIC16F87XA 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1  A c A2  A1 L  Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .026 0.65 Overall Height A .068 .073 .078 1.73 1.85 1.98 Molded Package Thickness A2 .064 .068 .072 1.63 1.73 1.83 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Overall Width E .299 .309 .319 7.59 7.85 8.10 Molded Package Width E1 .201 .207 .212 5.11 5.25 5.38 Overall Length D .396 .402 .407 10.06 10.20 10.34 Foot Length L .022 .030 .037 0.56 0.75 0.94 Lead Thickness c .004 .007 .010 0.10 0.18 0.25 Foot Angle  0 4 8 0.00 101.60 203.20 Lead Width B .010 .013 .015 0.25 0.32 0.38 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073  2001-2013 Microchip Technology Inc. DS39582C-page 217

PIC16F87XA 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Punch Singulated (QFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E EXPOSED METAL E1 PADS Q D1 D D2 p 2 1 B n R E2 CH X 45° L TOP VIEW BOTTOM VIEW α A2 A A1 A3 Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .026 BSC 0.65 BSC Overall Height A .033 .039 0.85 1.00 Molded Package Thickness A2 .026 .031 0.65 0.80 Standoff A1 .000 .0004 .002 0.00 0.01 0.05 Base Thickness A3 .008 REF 0.20 REF Overall Width E .236 BSC 6.00 BSC Molded Package Width E1 .226 BSC 5.75 BSC Exposed Pad Width E2 .140 .146 .152 3.55 3.70 3.85 Overall Length D .236 BSC 6.00 BSC Molded Package Length D1 .226 BSC 5.75 BSC Exposed Pad Length D2 .140 .146 .152 3.55 3.70 3.85 Lead Width B .009 .011 .014 0.23 0.28 0.35 Lead Length L .020 .024 .030 0.50 0.60 0.75 Tie Bar Width R .005 .007 .010 0.13 0.17 0.23 Tie Bar Length Q .012 .016 .026 0.30 0.40 0.65 Chamfer CH .009 .017 .024 0.24 0.42 0.60 Mold Draft Angle Top α 12° 12° *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: mMO-220 Drawing No. C04-114 DS39582C-page 218  2001-2013 Microchip Technology Inc.

PIC16F87XA APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (November 2001) The differences between the devices in this data sheet Original data sheet for PIC16F87XA devices. The are listed in TableB-1. devices presented are enhanced versions of the PIC16F87X microcontrollers discussed in the “PIC16F87X Data Sheet” (DS30292). Revision B (October 2003) This revision includes the DC and AC Characteristics Graphs and Tables. The Electrical Specifications in Section17.0 “Electrical Characteristics” have been updated and there have been minor corrections to the data sheet text. Revision C (January 2013) Added a note to each package outline drawing. TABLE B-1: DIFFERENCES BETWEEN DEVICES IN THE PIC16F87XA FAMILY PIC16F873A PIC16F874A PIC16F876A PIC16F877A Flash Program Memory 4K 4K 8K 8K (14-bit words) Data Memory (bytes) 192 192 368 368 EEPROM Data Memory (bytes) 128 128 256 256 Interrupts 14 15 14 15 I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART Parallel Slave Port No Yes No Yes 10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels Packages 28-pin PDIP 40-pin PDIP 28-pin PDIP 40-pin PDIP 28-pin SOIC 44-pin PLCC 28-pin SOIC 44-pin PLCC 28-pin SSOP 44-pin TQFP 28-pin SSOP 44-pin TQFP 28-pin QFN 44-pin QFN 28-pin QFN 44-pin QFN  2001-2013 Microchip Technology Inc. DS39582C-page 219

PIC16F87XA APPENDIX C: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in TableC-1. TABLE C-1: CONVERSION CONSIDERATIONS Characteristic PIC16C7X PIC16F87X PIC16F87XA Pins 28/40 28/40 28/40 Timers 3 3 3 Interrupts 11 or 12 13 or 14 14 or 15 Communication PSP, USART, SSP PSP, USART, SSP PSP, USART, SSP (SPI, I2C Slave) (SPI, I2C Master/Slave) (SPI, I2C Master/Slave) Frequency 20 MHz 20 MHz 20 MHz Voltage 2.5V-5.5V 2.2V-5.5V 2.0V-5.5V A/D 8-bit, 10-bit, 10-bit, 4 conversion clock selects 4 conversion clock selects 7 conversion clock selects CCP 2 2 2 Comparator — — 2 Comparator Voltage — — Yes Reference Program Memory 4K, 8K EPROM 4K, 8K Flash 4K, 8K Flash (Erase/Write on (Erase/Write on single-word) four-word blocks) RAM 192, 368 bytes 192, 368 bytes 192, 368 bytes EEPROM Data None 128, 256 bytes 128, 256 bytes Code Protection On/Off Segmented, starting at end On/Off of program memory Program Memory — On/Off Segmented, starting at Write Protection beginning of program memory Other  In-Circuit Debugger, In-Circuit Debugger, Low-Voltage Programming Low-Voltage Programming DS39582C-page 220  2001-2013 Microchip Technology Inc.

PIC16F87XA INDEX A Interrupt Logic ..........................................................153 MSSP (I2C Mode) ......................................................80 A/D ...................................................................................127 MSSP (SPI Mode) .....................................................71 Acquisition Requirements ........................................130 On-Chip Reset Circuit ..............................................147 ADCON0 Register ....................................................127 PIC16F873A/PIC16F876A Architecture ......................6 ADCON1 Register ....................................................127 PIC16F874A/PIC16F877A Architecture ......................7 ADIF Bit ....................................................................129 PORTC ADRESH Register ....................................................127 Peripheral Output Override ADRESL Register ....................................................127 (RC2:0, RC7:5) Pins ..................................46 Analog Port Pins ..................................................49, 51 Peripheral Output Override (RC4:3) Pins ..........46 Associated Registers and Bits .................................133 PORTD (in I/O Port Mode) .........................................48 Calculating Acquisition Time ....................................130 PORTD and PORTE (Parallel Slave Port) .................51 Configuring Analog Port Pins ...................................131 PORTE (In I/O Port Mode) .........................................49 Configuring the Interrupt ..........................................129 RA3:RA0 Pins ............................................................41 Configuring the Module ............................................129 RA4/T0CKI Pin ..........................................................42 Conversion Clock .....................................................131 RA5 Pin .....................................................................42 Conversions .............................................................132 RB3:RB0 Pins ............................................................44 Converter Characteristics ........................................194 RB7:RB4 Pins ............................................................44 Effects of a Reset .....................................................133 RC Oscillator Mode ..................................................146 GO/DONE Bit ...........................................................129 Recommended MCLR Circuit ..................................148 Internal Sampling Switch (Rss) Impedance .............130 Simplified PWM Mode ...............................................67 Operation During Sleep ...........................................133 Timer0/WDT Prescaler ..............................................53 Result Registers .......................................................132 Timer1 .......................................................................58 Source Impedance ...................................................130 Timer2 .......................................................................61 A/D Conversion Requirements .........................................195 USART Receive ................................................117, 119 Absolute Maximum Ratings .............................................173 USART Transmit ......................................................115 ACKSTAT .........................................................................101 Watchdog Timer ......................................................155 ADCON0 Register ..............................................................19 BOR. See Brown-out Reset. ADCON1 Register ..............................................................20 BRG. See Baud Rate Generator. Addressable Universal Synchronous Asynchronous BRGH Bit .........................................................................113 Receiver Transmitter. See USART. Brown-out Reset (BOR) ....................143, 147, 148, 149, 150 ADRESH Register ..............................................................19 BOR Status (BOR Bit) ...............................................29 ADRESL Register ..............................................................20 Bus Collision During a Repeated Start Condition ............108 Analog-to-Digital Converter. See A/D. Bus Collision During a Start Condition .............................106 Application Notes Bus Collision During a Stop Condition .............................109 AN552 (Implementing Wake-up Bus Collision Interrupt Flag bit, BCLIF ...............................28 on Key Stroke) ...................................................44 AN556 (Implementing a Table Read) ........................30 C Assembler C Compilers MPASM Assembler ..................................................167 MPLAB C17 .............................................................168 Asynchronous Reception MPLAB C18 .............................................................168 Associated Registers .......................................118, 120 MPLAB C30 .............................................................168 Asynchronous Transmission Capture/Compare/PWM (CCP) .........................................63 Associated Registers ...............................................116 Associated Registers B Capture, Compare and Timer1 ..........................68 PWM and Timer2 ...............................................69 Banking, Data Memory .................................................16, 22 Capture Mode ............................................................65 Baud Rate Generator .........................................................97 CCP1IF ..............................................................65 Associated Registers ...............................................113 Prescaler ...........................................................65 BCLIF .................................................................................28 CCP Timer Resources ...............................................63 BF .....................................................................................101 Compare Block Diagrams Special Event Trigger Output of CCP1 ..............66 A/D ...........................................................................129 Special Event Trigger Output of CCP2 ..............66 Analog Input Model ..........................................130, 139 Compare Mode ..........................................................66 Baud Rate Generator .................................................97 Software Interrupt Mode ....................................66 Capture Mode Operation ...........................................65 Special Event Trigger ........................................66 Comparator I/O Operating Modes ............................136 Interaction of Two CCP Modules (table) ....................63 Comparator Output ..................................................138 PWM Mode ................................................................67 Comparator Voltage Reference ...............................142 Duty Cycle .........................................................67 Compare Mode Operation .........................................66 Example Frequencies/Resolutions (table) .........68 Crystal/Ceramic Resonator Operation PWM Period ......................................................67 (HS, XT or LP Osc Configuration) ....................145 Special Event Trigger and A/D Conversions .............66 External Clock Input Operation (HS, XT or LP Osc Configuration) ....................145  2001-2013 Microchip Technology Inc. DS39582C-page 221

PIC16F87XA Capture/Compare/PWM Requirements Data EEPROM Memory (CCP1 and CCP2) ....................................................186 Associated Registers .................................................39 CCP. See Capture/Compare/PWM. EEADR Register ........................................................33 CCP1CON Register ...........................................................19 EEADRH Register .....................................................33 CCP2CON Register ...........................................................19 EECON1 Register ......................................................33 CCPR1H Register ........................................................19, 63 EECON2 Register ......................................................33 CCPR1L Register .........................................................19, 63 Operation During Code-Protect .................................39 CCPR2H Register ........................................................19, 63 Protection Against Spurious Writes ...........................39 CCPR2L Register .........................................................19, 63 Reading .....................................................................35 CCPxM0 Bit ........................................................................64 Write Complete Flag Bit (EEIF) .................................33 CCPxM1 Bit ........................................................................64 Writing ........................................................................35 CCPxM2 Bit ........................................................................64 Data Memory .....................................................................16 CCPxM3 Bit ........................................................................64 Bank Select (RP1:RP0 Bits) .................................16, 22 CCPxX Bit ..........................................................................64 General Purpose Registers .......................................16 CCPxY Bit ..........................................................................64 Register File Map ..................................................17, 18 CLKO and I/O Timing Requirements ...............................183 Special Function Registers ........................................19 CMCON Register ...............................................................20 DC and AC Characteristics Graphs and Tables ..............197 Code Examples DC Characteristics ....................................................175–179 Call of a Subroutine in Page 1 from Page 0 ...............30 Demonstration Boards Indirect Addressing ....................................................31 PICDEM 1 ................................................................170 Initializing PORTA ......................................................41 PICDEM 17 ..............................................................170 Loading the SSPBUF (SSPSR) Register ...................74 PICDEM 18R PIC18C601/801 .................................171 Reading Data EEPROM .............................................35 PICDEM 2 Plus ........................................................170 Reading Flash Program Memory ...............................36 PICDEM 3 PIC16C92X ............................................170 Saving Status, W and PCLATH Registers PICDEM 4 ................................................................170 in RAM ............................................................154 PICDEM LIN PIC16C43X ........................................171 Writing to Data EEPROM ...........................................35 PICDEM USB PIC16C7X5 ......................................171 Writing to Flash Program Memory .............................38 PICDEM.net Internet/Ethernet .................................170 Code Protection .......................................................143, 157 Development Support ......................................................167 Comparator Module .........................................................135 Device Differences ...........................................................219 Analog Input Connection Device Overview ..................................................................5 Considerations .................................................139 Direct Addressing ...............................................................31 Associated Registers ...............................................140 E Configuration ............................................................136 Effects of a Reset .....................................................139 EEADR Register ...........................................................21, 33 Interrupts ..................................................................138 EEADRH Register .........................................................21, 33 Operation .................................................................137 EECON1 Register .........................................................21, 33 Operation During Sleep ............................................139 EECON2 Register .........................................................21, 33 Outputs .....................................................................137 EEDATA Register ..............................................................21 Reference .................................................................137 EEDATH Register ..............................................................21 Response Time ........................................................137 Electrical Characteristics ..................................................173 Comparator Specifications ...............................................180 Errata ...................................................................................4 Comparator Voltage Reference .......................................141 Evaluation and Programming Tools .................................171 Associated Registers ...............................................142 External Clock Timing Requirements ...............................182 Computed GOTO ...............................................................30 External Interrupt Input (RB0/INT). See Interrupt Sources. Configuration Bits .............................................................143 External Reference Signal ...............................................137 Configuration Word ..........................................................144 F Conversion Considerations ..............................................220 CVRCON Register .............................................................20 Firmware Instructions .......................................................159 Flash Program Memory D Associated Registers .................................................39 Data EEPROM and Flash Program Memory EECON1 Register ......................................................33 EEADR Register ........................................................33 EECON2 Register ......................................................33 EEADRH Register ......................................................33 Reading .....................................................................36 EECON1 Register ......................................................33 Writing ........................................................................37 EECON2 Register ......................................................33 FSR Register ..........................................................19, 20, 31 EEDATA Register ......................................................33 G EEDATH Register ......................................................33 General Call Address Support ...........................................94 DS39582C-page 222  2001-2013 Microchip Technology Inc.

PIC16F87XA I RRF .........................................................................164 SLEEP .....................................................................164 I/O Ports .............................................................................41 SUBLW ....................................................................164 I2C Bus Data Requirements ............................................192 I2C Bus Start/Stop Bits Requirements .............................191 SUBWF ....................................................................164 I2C Mode SWAPF ....................................................................165 XORLW ...................................................................165 Registers ....................................................................80 I2C Mode ............................................................................80 XORWF ...................................................................165 Summary Table .......................................................160 ACK Pulse ............................................................84, 85 INT Interrupt (RB0/INT). See Interrupt Sources. Acknowledge Sequence Timing ...............................104 INTCON Register ...............................................................24 Baud Rate Generator .................................................97 GIE Bit .......................................................................24 Bus Collision INTE Bit .....................................................................24 Repeated Start Condition .................................108 INTF Bit .....................................................................24 Start Condition .................................................106 PEIE Bit .....................................................................24 Stop Condition .................................................109 RBIE Bit .....................................................................24 Clock Arbitration .........................................................98 RBIF Bit ................................................................24, 44 Effect of a Reset ......................................................105 TMR0IE Bit ................................................................24 General Call Address Support ...................................94 TMR0IF Bit .................................................................24 Master Mode ..............................................................95 Inter-Integrated Circuit. See I2C. Operation ...........................................................96 Internal Reference Signal ................................................137 Repeated Start Timing .....................................100 Internal Sampling Switch (Rss) Impedance .....................130 Master Mode Reception ...........................................101 Interrupt Sources ......................................................143, 153 Master Mode Start Condition .....................................99 Interrupt-on-Change (RB7:RB4) ................................44 Master Mode Transmission ......................................101 RB0/INT Pin, External .....................................9, 11, 154 Multi-Master Communication, Bus Collision TMR0 Overflow ........................................................154 and Arbitration ..................................................105 USART Receive/Transmit Complete .......................111 Multi-Master Mode ...................................................105 Interrupts Read/Write Bit Information (R/W Bit) ...................84, 85 Bus Collision Interrupt ................................................28 Serial Clock (RC3/SCK/SCL) .....................................85 Synchronous Serial Port Interrupt ..............................26 Slave Mode ................................................................84 Interrupts, Context Saving During ....................................154 Addressing .........................................................84 Interrupts, Enable Bits Reception ...........................................................85 Global Interrupt Enable (GIE Bit) ........................24, 153 Transmission ......................................................85 Interrupt-on-Change (RB7:RB4) Sleep Operation .......................................................105 Enable (RBIE Bit) .......................................24, 154 Stop Condition Timing ..............................................104 Peripheral Interrupt Enable (PEIE Bit) .......................24 ID Locations .............................................................143, 157 RB0/INT Enable (INTE Bit) ........................................24 In-Circuit Debugger ..................................................143, 157 TMR0 Overflow Enable (TMR0IE Bit) ........................24 Resources ................................................................157 Interrupts, Flag Bits In-Circuit Serial Programming (ICSP) ......................143, 158 Interrupt-on-Change (RB7:RB4) Flag INDF Register .........................................................19, 20, 31 (RBIF Bit) ..............................................24, 44, 154 Indirect Addressing ............................................................31 RB0/INT Flag (INTF Bit) ............................................24 FSR Register .............................................................16 TMR0 Overflow Flag (TMR0IF Bit) .....................24, 154 Instruction Format ............................................................159 Instruction Set ..................................................................159 L ADDLW ....................................................................161 Loading of PC ....................................................................30 ADDWF ....................................................................161 Low-Voltage ICSP Programming .....................................158 ANDLW ....................................................................161 Low-Voltage In-Circuit Serial Programming .....................143 ANDWF ....................................................................161 BCF ..........................................................................161 M BSF ..........................................................................161 Master Clear (MCLR) ...........................................................8 BTFSC .....................................................................161 MCLR Reset, Normal Operation ...............147, 149, 150 BTFSS .....................................................................161 MCLR Reset, Sleep ..................................147, 149, 150 CALL ........................................................................162 Master Synchronous Serial Port (MSSP). See MSSP. CLRF ........................................................................162 MCLR ...............................................................................148 CLRW ......................................................................162 MCLR/VPP .........................................................................10 CLRWDT ..................................................................162 Memory Organization ........................................................15 COMF ......................................................................162 Data EEPROM Memory .............................................33 DECF .......................................................................162 Data Memory .............................................................16 DECFSZ ...................................................................163 Flash Program Memory .............................................33 GOTO ......................................................................163 Program Memory .......................................................15 INCF .........................................................................163 MPLAB ASM30 Assembler, Linker, Librarian ..................168 INCFSZ ....................................................................163 MPLAB ICD 2 In-Circuit Debugger ..................................169 IORLW .....................................................................163 MPLAB ICE 2000 High-Performance Universal IORWF .....................................................................163 In-Circuit Emulator ...................................................169 RETURN ..................................................................164 RLF ..........................................................................164  2001-2013 Microchip Technology Inc. DS39582C-page 223

PIC16F87XA MPLAB ICE 4000 High-Performance Universal PICSTART Plus Development Programmer ....................169 In-Circuit Emulator ...................................................169 PIE1 Register ................................................................20, 25 MPLAB Integrated Development PIE2 Register ................................................................20, 27 Environment Software ..............................................167 Pinout Descriptions MPLINK Object Linker/MPLIB Object Librarian ...............168 PIC16F873A/PIC16F876A ...........................................8 MSSP .................................................................................71 PIR1 Register ...............................................................19, 26 I2C Mode. See I2C. PIR2 Register ...............................................................19, 28 SPI Mode ...................................................................71 POP ...................................................................................30 SPI Mode. See SPI. POR. See Power-on Reset. MSSP Module PORTA ...........................................................................8, 10 Clock Stretching .........................................................90 Associated Registers .................................................43 Clock Synchronization and the CKP Bit .....................91 Functions ...................................................................43 Control Registers (General) .......................................71 PORTA Register ...................................................19, 41 Operation ...................................................................84 TRISA Register ..........................................................41 Overview ....................................................................71 PORTB ...........................................................................9, 11 SPI Master Mode .......................................................76 Associated Registers .................................................45 SPI Slave Mode .........................................................77 Functions ...................................................................45 SSPBUF .....................................................................76 PORTB Register ...................................................19, 44 SSPSR .......................................................................76 Pull-up Enable (RBPU Bit) .........................................23 Multi-Master Mode ...........................................................105 RB0/INT Edge Select (INTEDG Bit) ..........................23 RB0/INT Pin, External .....................................9, 11, 154 O RB7:RB4 Interrupt-on-Change ................................154 Opcode Field Descriptions ...............................................159 RB7:RB4 Interrupt-on-Change Enable OPTION_REG Register .....................................................23 (RBIE Bit) ....................................................24, 154 INTEDG Bit ................................................................23 RB7:RB4 Interrupt-on-Change Flag PS2:PS0 Bits ..............................................................23 (RBIF Bit) ..............................................24, 44, 154 PSA Bit .......................................................................23 TRISB Register .....................................................21, 44 RBPU Bit ....................................................................23 PORTB Register ................................................................21 T0CS Bit .....................................................................23 PORTC ...........................................................................9, 12 T0SE Bit .....................................................................23 Associated Registers .................................................47 OSC1/CLKI Pin ..............................................................8, 10 Functions ...................................................................47 OSC2/CLKO Pin ............................................................8, 10 PORTC Register ...................................................19, 46 Oscillator Configuration RC3/SCK/SCL Pin .....................................................85 HS ....................................................................145, 149 RC6/TX/CK Pin ........................................................112 LP .....................................................................145, 149 RC7/RX/DT Pin .................................................112, 113 RC ............................................................145, 146, 149 TRISC Register ...................................................46, 111 XT .....................................................................145, 149 PORTD .........................................................................13, 51 Oscillator Selection ..........................................................143 Associated Registers .................................................48 Oscillator Start-up Timer (OST) ...............................143, 148 Functions ...................................................................48 Oscillator, WDT ................................................................155 Parallel Slave Port (PSP) Function ............................48 Oscillators PORTD Register ...................................................19, 48 Capacitor Selection ..................................................146 TRISD Register ..........................................................48 Ceramic Resonator Selection ..................................145 PORTE ..............................................................................13 Crystal and Ceramic Resonators .............................145 Analog Port Pins ...................................................49, 51 RC ............................................................................146 Associated Registers .................................................50 Functions ...................................................................49 P Input Buffer Full Status (IBF Bit) ................................50 Package Information Input Buffer Overflow (IBOV Bit) ................................50 Marking ....................................................................209 Output Buffer Full Status (OBF Bit) ...........................50 Packaging Information .....................................................209 PORTE Register ...................................................19, 49 Paging, Program Memory ..................................................30 PSP Mode Select (PSPMODE Bit) ...........48, 49, 50, 51 Parallel Slave Port (PSP) .......................................13, 48, 51 RE0/RD/AN5 Pin ..................................................49, 51 Associated Registers .................................................52 RE1/WR/AN6 Pin ..................................................49, 51 RE0/RD/AN5 Pin ..................................................49, 51 RE2/CS/AN7 Pin ...................................................49, 51 RE1/WR/AN6 Pin .................................................49, 51 TRISE Register ..........................................................49 RE2/CS/AN7 Pin ..................................................49, 51 Postscaler, WDT Select (PSPMODE Bit) ..............................48, 49, 50, 51 Assignment (PSA Bit) ................................................23 Parallel Slave Port Requirements Rate Select (PS2:PS0 Bits) .......................................23 (PIC16F874A/ 877A Only) .......................................187 Power-down Mode. See Sleep. PCL Register ..........................................................19, 20, 30 Power-on Reset (POR) .....................143, 147, 148, 149, 150 PCLATH Register ...................................................19, 20, 30 POR Status (POR Bit) ...............................................29 PCON Register ....................................................20, 29, 149 Power Control (PCON) Register ..............................149 BOR Bit ......................................................................29 Power-down (PD Bit) ..........................................22, 147 POR Bit ......................................................................29 Power-up Timer (PWRT) .........................................143 PIC16F87XA Product Identification System .....................231 Time-out (TO Bit) ................................................22, 147 PICkit 1 Flash Starter Kit ..................................................171 DS39582C-page 224  2001-2013 Microchip Technology Inc.

PIC16F87XA Power-up Timer (PWRT) ..................................................148 RE0/RD/AN5 Pin ...............................................................13 PR2 Register ................................................................20, 61 RE1/WR/AN6 Pin ...............................................................13 Prescaler, Timer0 RE2/CS/AN7 Pin ................................................................13 Assignment (PSA Bit) ................................................23 Read-Modify-Write Operations ........................................159 Rate Select (PS2:PS0 Bits) .......................................23 Register File .......................................................................16 PRO MATE II Universal Device Programmer ..................169 Register File Map (PIC16F873A/874A) .............................18 Program Counter Register File Map (PIC16F876A/877A) .............................17 Reset Conditions ......................................................149 Registers Program Memory ...............................................................15 ADCON0 (A/D Control 0) .........................................127 Interrupt Vector ..........................................................15 ADCON1 (A/D Control 1) .........................................128 Paging ........................................................................30 CCP1CON/CCP2CON (CCP Control 1 Program Memory Map and Stack and CCP Control 2) ...........................................64 (PIC16F873A/874A) ...........................................15 CMCON (Comparator Control) ................................135 Program Memory Map and Stack CVRCON (Comparator Voltage (PIC16F876A/877A) ...........................................15 Reference Control) ..........................................141 Reset Vector ..............................................................15 EECON1 (EEPROM Control 1) .................................34 Program Verification .........................................................157 FSR ...........................................................................31 Programming Pin (VPP) ........................................................8 INTCON .....................................................................24 Programming, Device Instructions ...................................159 OPTION_REG ......................................................23, 54 PSP. See Parallel Slave Port. PCON (Power Control) ..............................................29 Pulse Width Modulation. See Capture/Compare/PWM, PIE1 (Peripheral Interrupt Enable 1) ..........................25 PWM Mode. PIE2 (Peripheral Interrupt Enable 2) ..........................27 PUSH .................................................................................30 PIR1 (Peripheral Interrupt Request 1) .......................26 PIR2 (Peripheral Interrupt Request 2) .......................28 R RCSTA (Receive Status and Control) .....................112 RA0/AN0 Pin ..................................................................8, 10 Special Function, Summary .......................................19 RA1/AN1 Pin ..................................................................8, 10 SSPCON (MSSP Control 1, I2C Mode) .....................82 RA2/AN2/VREF-/CVREF Pin ............................................8, 10 SSPCON (MSSP Control 1, SPI Mode) .....................73 RA3/AN3/VREF+ Pin .......................................................8, 10 SSPCON2 (MSSP Control 2, I2C Mode) ...................83 RA4/T0CKI/C1OUT Pin ..................................................8, 10 SSPSTAT (MSSP Status, I2C Mode) ........................81 RA5/AN4/SS/C2OUT Pin ...............................................8, 10 SSPSTAT (MSSP Status, SPI Mode) ........................72 RAM. See Data Memory. Status ........................................................................22 RB0/INT Pin ...................................................................9, 11 T1CON (Timer1 Control) ...........................................57 RB1 Pin ..........................................................................9, 11 T2CON (Timer2 Control) ...........................................61 RB2 Pin ..........................................................................9, 11 TRISE Register ..........................................................50 RB3/PGM Pin .................................................................9, 11 TXSTA (Transmit Status and Control) .....................111 RB4 Pin ..........................................................................9, 11 Reset ........................................................................143, 147 RB5 Pin ..........................................................................9, 11 Brown-out Reset (BOR). See Brown-out Reset (BOR). RB6/PGC Pin .................................................................9, 11 MCLR Reset. See MCLR. RB7/PGD Pin .................................................................9, 11 Power-on Reset (POR). See Power-on Reset (POR). RC0/T1OSO/T1CKI Pin .................................................9, 12 Reset Conditions for PCON Register ......................149 RC1/T1OSI/CCP2 Pin ....................................................9, 12 Reset Conditions for Program Counter ....................149 RC2/CCP1 Pin ...............................................................9, 12 Reset Conditions for Status Register .......................149 RC3/SCK/SCL Pin .........................................................9, 12 WDT Reset. See Watchdog Timer (WDT). RC4/SDI/SDA Pin ..........................................................9, 12 Reset, Watchdog Timer, Oscillator Start-up Timer, RC5/SDO Pin .................................................................9, 12 Power-up Timer and Brown-out Reset RC6/TX/CK Pin ..............................................................9, 12 Requirements ..........................................................184 RC7/RX/DT Pin ..............................................................9, 12 Revision History ...............................................................219 RCREG Register ................................................................19 S RCSTA Register .................................................................19 ADDEN Bit ...............................................................112 SCI. See USART. CREN Bit ..................................................................112 SCK ...................................................................................71 FERR Bit ..................................................................112 SDI .....................................................................................71 OERR Bit .................................................................112 SDO ...................................................................................71 RX9 Bit .....................................................................112 Serial Clock, SCK ..............................................................71 RX9D Bit ..................................................................112 Serial Communication Interface. See USART. SPEN Bit ..........................................................111, 112 Serial Data In, SDI .............................................................71 SREN Bit ..................................................................112 Serial Data Out, SDO ........................................................71 RD0/PSP0 Pin ....................................................................13 Serial Peripheral Interface. See SPI. RD1/PSP1 Pin ....................................................................13 Slave Select Synchronization ............................................77 RD2/PSP2 Pin ....................................................................13 Slave Select, SS ................................................................71 RD3/PSP3 Pin ....................................................................13 Sleep .................................................................143, 147, 156 RD4/PSP4 Pin ....................................................................13 Software Simulator (MPLAB SIM) ...................................168 RD5/PSP5 Pin ....................................................................13 Software Simulator (MPLAB SIM30) ...............................168 RD6/PSP6 Pin ....................................................................13 SPBRG Register ................................................................20 RD7/PSP7 Pin ....................................................................13 Special Features of the CPU ...........................................143  2001-2013 Microchip Technology Inc. DS39582C-page 225

PIC16F87XA Special Function Registers ................................................19 Timer0 ................................................................................53 Special Function Registers (SFRs) ....................................19 Associated Registers .................................................55 Speed, Operating .................................................................1 Clock Source Edge Select (T0SE Bit) .......................23 SPI Mode .....................................................................71, 77 Clock Source Select (T0CS Bit) .................................23 Associated Registers .................................................79 External Clock ............................................................54 Bus Mode Compatibility .............................................79 Interrupt .....................................................................53 Effects of a Reset .......................................................79 Overflow Enable (TMR0IE Bit) ...................................24 Enabling SPI I/O .........................................................75 Overflow Flag (TMR0IF Bit) ................................24, 154 Master Mode ..............................................................76 Overflow Interrupt ....................................................154 Master/Slave Connection ...........................................75 Prescaler ....................................................................54 Serial Clock ................................................................71 T0CKI .........................................................................54 Serial Data In .............................................................71 Timer0 and Timer1 External Clock Requirements ...........185 Serial Data Out ...........................................................71 Timer1 ................................................................................57 Slave Select ...............................................................71 Associated Registers .................................................60 Slave Select Synchronization .....................................77 Asynchronous Counter Mode ....................................59 Sleep Operation .........................................................79 Reading and Writing to ......................................59 SPI Clock ...................................................................76 Counter Operation .....................................................58 Typical Connection .....................................................75 Operation in Timer Mode ...........................................58 SPI Mode Requirements ..................................................190 Oscillator ....................................................................59 SS ......................................................................................71 Capacitor Selection ............................................59 SSP Prescaler ....................................................................60 SPI Master/Slave Connection ....................................75 Resetting of Timer1 Registers ...................................60 SSPADD Register ..............................................................20 Resetting Timer1 Using a CCP Trigger Output .........59 SSPBUF Register ..............................................................19 Synchronized Counter Mode .....................................58 SSPCON Register ..............................................................19 TMR1H ......................................................................59 SSPCON2 Register ............................................................20 TMR1L .......................................................................59 SSPIF .................................................................................26 Timer2 ................................................................................61 SSPOV .............................................................................101 Associated Registers .................................................62 SSPSTAT Register ............................................................20 Output ........................................................................62 R/W Bit .................................................................84, 85 Postscaler ..................................................................61 Stack ..................................................................................30 Prescaler ....................................................................61 Overflows ...................................................................30 Prescaler and Postscaler ...........................................62 Underflow ...................................................................30 Timing Diagrams Status Register A/D Conversion ........................................................195 C Bit ...........................................................................22 Acknowledge Sequence ..........................................104 DC Bit .........................................................................22 Asynchronous Master Transmission ........................116 IRP Bit ........................................................................22 Asynchronous Master Transmission PD Bit .................................................................22, 147 (Back to Back) .................................................116 RP1:RP0 Bits .............................................................22 Asynchronous Reception .........................................118 TO Bit .................................................................22, 147 Asynchronous Reception with Z Bit ............................................................................22 Address Byte First ...........................................120 Synchronous Master Reception Asynchronous Reception with Associated Registers ...............................................123 Address Detect ................................................120 Synchronous Master Transmission Baud Rate Generator with Clock Arbitration ..............98 Associated Registers ...............................................122 BRG Reset Due to SDA Arbitration During Synchronous Serial Port Interrupt ......................................26 Start Condition .................................................107 Synchronous Slave Reception Brown-out Reset ......................................................184 Associated Registers ...............................................125 Bus Collision During a Repeated Synchronous Slave Transmission Start Condition (Case 1) ..................................108 Associated Registers ...............................................125 Bus Collision During Repeated Start Condition (Case 2) ..................................108 T Bus Collision During Start Condition T1CKPS0 Bit ......................................................................57 (SCL = 0) .........................................................107 T1CKPS1 Bit ......................................................................57 Bus Collision During Start Condition T1CON Register .................................................................19 (SDA Only) .......................................................106 T1OSCEN Bit .....................................................................57 Bus Collision During Stop Condition T1SYNC Bit ........................................................................57 (Case 1) ...........................................................109 T2CKPS0 Bit ......................................................................61 Bus Collision During Stop Condition T2CKPS1 Bit ......................................................................61 (Case 2) ...........................................................109 T2CON Register .................................................................19 Bus Collision for Transmit and Acknowledge ..........105 TAD ...................................................................................131 Capture/Compare/PWM (CCP1 and CCP2) ............186 Time-out Sequence ..........................................................148 CLKO and I/O ..........................................................183 Clock Synchronization ...............................................91 External Clock ..........................................................182 First Start Bit ..............................................................99 DS39582C-page 226  2001-2013 Microchip Technology Inc.

PIC16F87XA I2C Bus Data ............................................................191 TRISB Register ..................................................................20 I2C Bus Start/Stop Bits .............................................190 TRISC Register ..................................................................20 I2C Master Mode (Reception, 7-bit Address) ...........103 TRISD Register ..................................................................20 I2C Master Mode (Transmission, TRISE Register ..................................................................20 7 or 10-bit Address) .........................................102 IBF Bit ........................................................................50 I2C Slave Mode (Transmission, 10-bit Address) ........89 IBOV Bit .....................................................................50 I2C Slave Mode (Transmission, 7-bit Address) ..........87 OBF Bit ......................................................................50 I2C Slave Mode with SEN = 1 (Reception, PSPMODE Bit ...........................................48, 49, 50, 51 10-bit Address) ...................................................93 TXREG Register ................................................................19 I2C Slave Mode with SEN = 0 (Reception, TXSTA Register .................................................................20 10-bit Address) ...................................................88 BRGH Bit .................................................................111 I2C Slave Mode with SEN = 0 (Reception, CSRC Bit .................................................................111 7-bit Address) .....................................................86 SYNC Bit .................................................................111 I2C Slave Mode with SEN = 1 (Reception, TRMT Bit ..................................................................111 7-bit Address) .....................................................92 TX9 Bit .....................................................................111 Parallel Slave Port (PIC16F874A/877A Only) ..........187 TX9D Bit ..................................................................111 Parallel Slave Port (PSP) Read .................................52 TXEN Bit ..................................................................111 Parallel Slave Port (PSP) Write .................................52 U Repeat Start Condition .............................................100 Reset, Watchdog Timer, Start-up Timer USART .............................................................................111 and Power-up Timer ........................................184 Address Detect Enable (ADDEN Bit) .......................112 Slave Mode General Call Address Sequence Asynchronous Mode ................................................115 (7 or 10-bit Address Mode) ................................94 Asynchronous Receive (9-bit Mode) ........................119 Slave Synchronization ...............................................77 Asynchronous Receive with Address Detect. Slow Rise Time (MCLR Tied to VDD via See Asynchronous Receive (9-bit Mode). RC Network) ....................................................152 Asynchronous Receiver ...........................................117 SPI Master Mode (CKE = 0, SMP = 0) ....................188 Asynchronous Reception .........................................118 SPI Master Mode (CKE = 1, SMP = 1) ....................188 Asynchronous Transmitter .......................................115 SPI Mode (Master Mode) ...........................................76 Baud Rate Generator (BRG) ...................................113 SPI Mode (Slave Mode with CKE = 0) .......................78 Baud Rate Formula .........................................113 SPI Mode (Slave Mode with CKE = 1) .......................78 Baud Rates, Asynchronous Mode SPI Slave Mode (CKE = 0) ......................................189 (BRGH = 0) ..............................................114 SPI Slave Mode (CKE = 1) ......................................189 Baud Rates, Asynchronous Mode Stop Condition Receive or Transmit Mode ..............104 (BRGH = 1) ..............................................114 Synchronous Reception High Baud Rate Select (BRGH Bit) .................111 (Master Mode, SREN) ......................................124 Sampling ..........................................................113 Synchronous Transmission ......................................122 Clock Source Select (CSRC Bit) ..............................111 Synchronous Transmission (Through TXEN) ..........122 Continuous Receive Enable (CREN Bit) ..................112 Time-out Sequence on Power-up Framing Error (FERR Bit) ........................................112 (MCLR Not Tied to VDD) Mode Select (SYNC Bit) ..........................................111 Case 1 ..............................................................152 Overrun Error (OERR Bit) ........................................112 Case 2 ..............................................................152 Receive Data, 9th Bit (RX9D Bit) .............................112 Time-out Sequence on Power-up (MCLR Tied Receive Enable, 9-bit (RX9 Bit) ...............................112 to VDD via RC Network) ...................................151 Serial Port Enable (SPEN Bit) ..........................111, 112 Timer0 and Timer1 External Clock ..........................185 Single Receive Enable (SREN Bit) ..........................112 USART Synchronous Receive Synchronous Master Mode ......................................121 (Master/Slave) ..................................................193 Synchronous Master Reception ...............................123 USART Synchronous Transmission Synchronous Master Transmission .........................121 (Master/Slave) ..................................................193 Synchronous Slave Mode ........................................124 Wake-up from Sleep via Interrupt ............................157 Synchronous Slave Reception .................................125 Timing Parameter Symbology ..........................................181 Synchronous Slave Transmit ...................................124 TMR0 Register ...................................................................19 Transmit Data, 9th Bit (TX9D) .................................111 TMR1CS Bit .......................................................................57 Transmit Enable (TXEN Bit) ....................................111 TMR1H Register ................................................................19 Transmit Enable, 9-bit (TX9 Bit) ..............................111 TMR1L Register .................................................................19 Transmit Shift Register Status (TRMT Bit) ..............111 TMR1ON Bit .......................................................................57 USART Synchronous Receive Requirements .................193 TMR2 Register ...................................................................19 V TMR2ON Bit .......................................................................61 TMRO Register ..................................................................21 VDD Pin ...........................................................................9, 13 TOUTPS0 Bit .....................................................................61 Voltage Reference Specifications ....................................180 TOUTPS1 Bit .....................................................................61 VSS Pin ...........................................................................9, 13 TOUTPS2 Bit .....................................................................61 TOUTPS3 Bit .....................................................................61 TRISA Register ..................................................................20  2001-2013 Microchip Technology Inc. DS39582C-page 227

PIC16F87XA W Wake-up from Sleep ................................................143, 156 Interrupts ..........................................................149, 150 MCLR Reset .............................................................150 WDT Reset ...............................................................150 Wake-up Using Interrupts ................................................156 Watchdog Timer Register Summary ...................................................155 Watchdog Timer (WDT) ...........................................143, 155 Enable (WDTE Bit) ...................................................155 Postscaler. See Postscaler, WDT. Programming Considerations ...................................155 RC Oscillator ............................................................155 Time-out Period ........................................................155 WDT Reset, Normal Operation ................147, 149, 150 WDT Reset, Sleep ...................................147, 149, 150 WCOL ................................................................99, 101, 104 WCOL Status Flag .............................................................99 WWW, On-Line Support .......................................................4 DS39582C-page 228  2001-2013 Microchip Technology Inc.

PIC16F87XA THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or field application engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2001-2013 Microchip Technology Inc. DS39582C-page 229

PIC16F87XA READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16F87XA Literature Number: DS39582C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39582C-page 230  2001-2013 Microchip Technology Inc.

PIC16F87XA PIC16F87XA PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F873A-I/P 301 = Industrial temp., PDIP Range package, normal VDD limits, QTP pattern #301. b) PIC16LF876A-I/SO = Industrial temp., SOIC package, Extended VDD limits. Device PPIICC1166FLF878X7XAA(1()1, )P, PICIC1166FL8F78X7AXTA(2T);( 2V);D VDD rDa nrgaen g4e.0 2V.0 tVo 5to.5 5V.5V c) P10IC M1H6Fz8, 7n7oArm-Ia/Pl V=D DIn ldimusittsri.al temp., PDIP package, Temperature Range I = -40C to +85C (Industrial) Package ML = QFN (Metal Lead Frame) PT = TQFP (Thin Quad Flatpack) SO = SOIC SP = Skinny Plastic DIP P = PDIP L = PLCC S = SSOP Note 1: F = CMOS Flash LF = Low-Power CMOS Flash 2: T = in tape and reel - SOIC, PLCC, TQFP packages only  2001-2013 Microchip Technology Inc. DS39582C-page 231

PIC16F87XA NOTES:  2001-2013 Microchip Technology Inc. DS39582C-page 232

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2001-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769621 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2001-2013 Microchip Technology Inc. DS39582C-page 233

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