PIC16F87X 28/40-Pin 8-Bit CMOS FLASH Microcontrollers Devices Included in this Data Sheet: Pin Diagram • PIC16F873 • PIC16F876 PDIP • PIC16F874 • PIC16F877 MCLR/VPP 1 40 RB7/PGD RA0/AN0 2 39 RB6/PGC Microcontroller Core Features: RA1/AN1 3 38 RB5 RA2/AN2/VREF- 4 37 RB4 • High performance RISC CPU RA3/AN3/VREF+ 5 36 RB3/PGM • Only 35 single word instructions to learn RA4/T0CKI 6 35 RB2 RA5/AN4/SS 7 34 RB1 • All single cycle instructions except for program 4 RE0/RD/AN5 8 7 33 RB0/INT branches which are two cycle 8 RE1/WR/AN6 9 7/ 32 VDD • Operating speed: DC - 20 MHz clock input RE2/CS/AN7 10 7 31 VSS DC - 200 ns instruction cycle VDD 11 F8 30 RD7/PSP7 VSS 12 6 29 RD6/PSP6 • Up to 8K x 14 words of FLASH Program Memory, OSC1/CLKIN 13 C1 28 RD5/PSP5 Up to 368 x 8 bytes of Data Memory (RAM) OSC2/CLKOUT 14 PI 27 RD4/PSP4 Up to 256 x 8 bytes of EEPROM Data Memory RC0/T1OSO/T1CKI 15 26 RC7/RX/DT RC1/T1OSI/CCP2 16 25 RC6/TX/CK • Pinout compatible to the PIC16C73B/74B/76/77 RC2/CCP1 17 24 RC5/SDO • Interrupt capability (up to 14 sources) RC3/SCK/SCL 18 23 RC4/SDI/SDA • Eight level deep hardware stack RD0/PSP0 19 22 RD3/PSP3 RD1/PSP1 20 21 RD2/PSP2 • Direct, indirect and relative addressing modes • Power-on Reset (POR) • Power-up Timer (PWRT) and Peripheral Features: Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC • Timer0: 8-bit timer/counter with 8-bit prescaler oscillator for reliable operation • Timer1: 16-bit timer/counter with prescaler, • Programmable code protection can be incremented during SLEEP via external • Power saving SLEEP mode crystal/clock • Selectable oscillator options • Timer2: 8-bit timer/counter with 8-bit period • Low power, high speed CMOS FLASH/EEPROM register, prescaler and postscaler technology • Two Capture, Compare, PWM modules • Fully static design - Capture is 16-bit, max. resolution is 12.5 ns • In-Circuit Serial Programming(ICSP)via two - Compare is 16-bit, max. resolution is 200 ns pins - PWM max. resolution is 10-bit • Single 5V In-Circuit Serial Programming capability • 10-bit multi-channel Analog-to-Digital converter • In-Circuit Debugging via two pins • Synchronous Serial Port (SSP) with SPI (Master • Processor read/write access to program memory mode) and I2C(Master/Slave) • Wide operating voltage range: 2.0V to 5.5V • Universal Synchronous Asynchronous Receiver • High Sink/Source Current: 25mA Transmitter (USART/SCI) with 9-bit address detection • Commercial, Industrial and Extended temperature ranges • Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only) • Low-power consumption: • Brown-out detection circuitry for - < 0.6 mA typical @ 3V, 4 MHz Brown-out Reset (BOR) - 20 A typical @ 3V, 32 kHz - < 1 A typical standby current  1998-2013 Microchip Technology Inc. DS30292D-page 1

PIC16F87X Pin Diagrams PDIP, SOIC MCLR/VPP 1 28 RB7/PGD RA0/AN0 2 27 RB6/PGC RA1/AN1 3 26 RB5 3 RA2/AN2/VREF- 4 7 25 RB4 RA3/AN3/VREF+ 5 6/8 24 RB3/PGM RA4/T0CKI 6 7 23 RB2 RA5/AN4/SS 7 8 22 RB1 F VSS 8 6 21 RB0/INT OSC1/CLKIN 9 C1 20 VDD OSC2/CLKOUT 10 PI 19 VSS RC0/T1OSO/T1CKI 11 18 RC7/RX/DT RC1/T1OSI/CCP2 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA +F-F EE RR N3/VN2/VN1N0VPP GDGC AAAAR/ PP PLCC A3/A2/A1/A0/CLCB7/B6/B5B4C RRRRMNRRRRN 65432143210 RA4/T0CKI 7 4444439 RB3/PGM RA5/AN4/SS 8 38 RB2 RE0/RD/AN5 9 37 RB1 RE1/WR/AN6 10 36 RB0/INT RE2/CS/AN7 11 PIC16F877 35 VDD VDD 12 PIC16F874 34 VSS VSS 13 33 RD7/PSP7 OSC1/CLKIN 14 32 RD6/PSP6 OSC2/CLKOUT 15 31 RD5/PSP5 RC0/T1OSO/T1CK1 16 30 RD4/PSP4 NC 17 29 RC7/RX/DT 89012345678 11222222222 2 P QFP RC6/TX/CKRC5/SDORC4/SDI/SDARD3/PSP3RD2/PSP2RD1/PSP1RD0/PSP0RC3/SCK/SCLRC2/CCP1RC1/T1OSI/CCNC 1/T1OSI/CCP2RC2/CCP1RC3/SCK/SCLRD0/PSP0RD1/PSP1RD2/PSP2RD3/PSP3RC4/SDI/SDARC5/SDORC6/TX/CKNC C R 43210987654 44444333333 RC7/RX/DT 1 33 NC RD4/PSP4 2 32 RC0/T1OSO/T1CKI RD5/PSP5 3 31 OSC2/CLKOUT RD6/PSP6 4 30 OSC1/CLKIN RD7/PSP7 5 PIC16F877 29 VSS VSS 6 PIC16F874 28 VDD VDD 7 27 RE2/AN7/CS RB0/INT 8 26 RE1/AN6/WR RB1 9 25 RE0/AN5/RD RB2 10 24 RA5/AN4/SS RB3/PGM 11 23 RA4/T0CKI 23456789012 11111111222 NCNCRB4RB5RB6/PGCRB7/PGDMCLR/VPPRA0/AN0RA1/AN1RA2/AN2/V-REFRA3/AN3/V+REF DS30292D-page 2  1998-2013 Microchip Technology Inc.

PIC16F87X Key Features PIC® MCU Mid-Range Reference PIC16F873 PIC16F874 PIC16F876 PIC16F877 Manual (DS33023) Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz RESETS (and Delays) POR, BOR POR, BOR POR, BOR POR, BOR (PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST) FLASH Program Memory 4K 4K 8K 8K (14-bit words) Data Memory (bytes) 192 192 368 368 EEPROM Data Memory 128 128 256 256 Interrupts 13 14 13 14 I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E Timers 3 3 3 3 Capture/Compare/PWM Modules 2 2 2 2 Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART Parallel Communications — PSP — PSP 10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels Instruction Set 35 instructions 35 instructions 35 instructions 35 instructions  1998-2013 Microchip Technology Inc. DS30292D-page 3

PIC16F87X Table of Contents 1.0 Device Overview................................................................................................................................................... 5 2.0 Memory Organization.......................................................................................................................................... 11 3.0 I/O Ports.............................................................................................................................................................. 29 4.0 Data EEPROM and FLASH Program Memory.................................................................................................... 41 5.0 Timer0 Module.................................................................................................................................................... 47 6.0 Timer1 Module.................................................................................................................................................... 51 7.0 Timer2 Module.................................................................................................................................................... 55 8.0 Capture/Compare/PWM Modules....................................................................................................................... 57 9.0 Master Synchronous Serial Port (MSSP) Module............................................................................................... 65 10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)........................................ 95 11.0 Analog-to-Digital Converter (A/D) Module......................................................................................................... 111 12.0 Special Features of the CPU............................................................................................................................. 119 13.0 Instruction Set Summary................................................................................................................................... 135 14.0 Development Support....................................................................................................................................... 143 15.0 Electrical Characteristics................................................................................................................................... 149 16.0 DC and AC Characteristics Graphs and Tables................................................................................................ 177 17.0 Packaging Information...................................................................................................................................... 189 Appendix A: Revision History .................................................................................................................................... 197 Appendix B: Device Differences................................................................................................................................ 197 Appendix C:Conversion Considerations................................................................................................................... 198 Index.......................................................................................................................................................................... 199 On-Line Support......................................................................................................................................................... 207 Reader Response...................................................................................................................................................... 208 PIC16F87X Product Identification System................................................................................................................. 209 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS30292D-page 4  1998-2013 Microchip Technology Inc.

PIC16F87X 1.0 DEVICE OVERVIEW There are four devices (PIC16F873, PIC16F874, PIC16F876 and PIC16F877) covered by this data This document contains device specific information. sheet. The PIC16F876/873 devices come in 28-pin Additional information may be found in the PIC® MCU packages and the PIC16F877/874 devices come in Mid-Range Reference Manual (DS33023), which may 40-pin packages. The Parallel Slave Port is not be obtained from your local Microchip Sales Represen- implemented on the 28-pin devices. tative or downloaded from the Microchip website. The The following device block diagrams are sorted by pin Reference Manual should be considered a complemen- number; 28-pin for Figure1-1 and 40-pin for Figure1-2. tary document to this data sheet, and is highly recom- The 28-pin and 40-pin pinouts are listed in Table1-1 mended reading for a better understanding of the device and Table1-2, respectively. architecture and operation of the peripheral modules. FIGURE 1-1: PIC16F873 AND PIC16F876 BLOCK DIAGRAM Program Data Device Data Memory FLASH EEPROM PIC16F873 4K 192 Bytes 128 Bytes PIC16F876 8K 368 Bytes 256 Bytes 13 Data Bus 8 PORTA Program Counter RA0/AN0 FLASH RA1/AN1 Program RA2/AN2/VREF- Memory 8 Level Stack RFAileM RRAA43//TA0NC3K/VIREF+ (13-bit) Registers RA5/AN4/SS Program Bus 14 RAM Addr(1) 9 PORTB RB0/INT Instruction reg Addr MUX RB1 RB2 Direct Addr 7 8 InAddirderct RB3/PGM RB4 FSR reg RB5 RB6/PGC STATUS reg RB7/PGD 8 PORTC RC0/T1OSO/T1CKI Power-up 3 MUX RC1/T1OSI/CCP2 Timer RC2/CCP1 Instruction Oscillator RC3/SCK/SCL Decode & Start-up Timer RC4/SDI/SDA ALU Control Power-on RC5/SDO Reset 8 RC6/TX/CK RC7/RX/DT Timing Watchdog Generation Timer W reg OSC1/CLKIN Brown-out OSC2/CLKOUT Reset In-Circuit Debugger Low Voltage Programming MCLR VDD, VSS Timer0 Timer1 Timer2 10-bit A/D Synchronous Data EEPROM CCP1,2 USART Serial Port Note 1: Higher order bits are from the STATUS register.  1998-2013 Microchip Technology Inc. DS30292D-page 5

PIC16F87X FIGURE 1-2: PIC16F874 AND PIC16F877 BLOCK DIAGRAM Program Data Device Data Memory FLASH EEPROM PIC16F874 4K 192 Bytes 128 Bytes PIC16F877 8K 368 Bytes 256 Bytes 13 Data Bus 8 PORTA Program Counter FLASH RA0/AN0 RA1/AN1 Program Memory RAM RA2/AN2/VREF- 8 Level Stack RA3/AN3/VREF+ (13-bit) RegFiisleters RA4/T0CKI RA5/AN4/SS Program Bus 14 RAM Addr(1) 9 PORTB RB0/INT Instruction reg Addr MUX RB1 RB2 Direct Addr 7 8 InAddirderct RB3/PGM RB4 FSR reg RB5 RB6/PGC STATUS reg RB7/PGD 8 PORTC RC0/T1OSO/T1CKI Power-up 3 MUX RC1/T1OSI/CCP2 Timer RC2/CCP1 RC3/SCK/SCL Instruction Oscillator RC4/SDI/SDA Decode & Start-up Timer Control ALU RC5/SDO PoRweesre-ton 8 RC6/TX/CK RC7/RX/DT Timing Watchdog Generation Timer W reg PORTD OSC1/CLKIN Brown-out RD0/PSP0 OSC2/CLKOUT Reset RD1/PSP1 In-Circuit RD2/PSP2 Debugger RD3/PSP3 Low-Voltage RD4/PSP4 Programming Parallel Slave Port RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE MCLR VDD, VSS RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS Timer0 Timer1 Timer2 10-bit A/D Synchronous Data EEPROM CCP1,2 USART Serial Port Note 1: Higher order bits are from the STATUS register. DS30292D-page 6  1998-2013 Microchip Technology Inc.

PIC16F87X TABLE 1-1: PIC16F873 AND PIC16F876 PINOUT DESCRIPTION DIP SOIC I/O/P Buffer Pin Name Description Pin# Pin# Type Type OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input. OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 1 I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0/AN0 2 2 I/O TTL RA0 can also be analog input0. RA1/AN1 3 3 I/O TTL RA1 can also be analog input1. RA2/AN2/VREF- 4 4 I/O TTL RA2 can also be analog input2 or negative analog reference voltage. RA3/AN3/VREF+ 5 5 I/O TTL RA3 can also be analog input3 or positive analog reference voltage. RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5/SS/AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 22 22 I/O TTL RB2 23 23 I/O TTL RB3/PGM 24 24 I/O TTL RB3 can also be the low voltage programming input. RB4 25 25 I/O TTL Interrupt-on-change pin. RB5 26 26 I/O TTL Interrupt-on-change pin. RB6/PGC 27 27 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming clock. RB7/PGD 28 28 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins. VDD 20 20 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.  1998-2013 Microchip Technology Inc. DS30292D-page 7

PIC16F87X TABLE 1-2: PIC16F874 AND PIC16F877 PINOUT DESCRIPTION DIP PLCC QFP I/O/P Buffer Pin Name Description Pin# Pin# Pin# Type Type OSC1/CLKIN 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input. OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 18 I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0. RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1. RA2/AN2/VREF- 4 5 21 I/O TTL RA2 can also be analog input2 or negative analog reference voltage. RA3/AN3/VREF+ 5 6 22 I/O TTL RA3 can also be analog input3 or positive analog reference voltage. RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5/SS/AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be soft- ware programmed for internal weak pull-up on all inputs. RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 34 37 9 I/O TTL RB2 35 38 10 I/O TTL RB3/PGM 36 39 11 I/O TTL RB3 can also be the low voltage programming input. RB4 37 41 14 I/O TTL Interrupt-on-change pin. RB5 38 42 15 I/O TTL Interrupt-on-change pin. RB6/PGC 39 43 16 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming clock. RB7/PGD 40 44 17 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming data. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. DS30292D-page 8  1998-2013 Microchip Technology Inc.

PIC16F87X TABLE 1-2: PIC16F874 AND PIC16F877 PINOUT DESCRIPTION (CONTINUED) DIP PLCC QFP I/O/P Buffer Pin Name Description Pin# Pin# Pin# Type Type PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/ output for both SPI and I2C modes. RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus. RD0/PSP0 19 21 38 I/O ST/TTL(3) RD1/PSP1 20 22 39 I/O ST/TTL(3) RD2/PSP2 21 23 40 I/O ST/TTL(3) RD3/PSP3 22 24 41 I/O ST/TTL(3) RD4/PSP4 27 30 2 I/O ST/TTL(3) RD5/PSP5 28 31 3 I/O ST/TTL(3) RD6/PSP6 29 32 4 I/O ST/TTL(3) RD7/PSP7 30 33 5 I/O ST/TTL(3) PORTE is a bi-directional I/O port. RE0/RD/AN5 8 9 25 I/O ST/TTL(3) RE0 can also be read control for the parallel slave port, or analog input5. RE1/WR/AN6 9 10 26 I/O ST/TTL(3) RE1 can also be write control for the parallel slave port, or analog input6. RE2/CS/AN7 10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave port, or analog input7. VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins. VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins. NC — 1,17,28, 12,13, — These pins are not internally connected. These pins 40 33,34 should be left unconnected. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.  1998-2013 Microchip Technology Inc. DS30292D-page 9

PIC16F87X NOTES: DS30292D-page 10  1998-2013 Microchip Technology Inc.

PIC16F87X 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization There are three memory blocks in each of the The PIC16F87X devices have a 13-bit program counter PIC16F87X MCUs. The Program Memory and Data capable of addressing an 8K x 14 program memory Memory have separate buses so that concurrent space. The PIC16F877/876 devices have 8K x 14 access can occur and is detailed in this section. The words of FLASH program memory, and the EEPROM data memory block is detailed in Section4.0. PIC16F873/874 devices have 4K x 14. Accessing a location above the physically implemented address will Additional information on device memory may be found in the PIC® MCU Mid-Range Reference Manual, cause a wraparound. (DS33023). The RESET vector is at 0000h and the interrupt vector is at 0004h. FIGURE 2-1: PIC16F877/876 PROGRAM MEMORY MAP AND FIGURE 2-2: PIC16F874/873 PROGRAM STACK MEMORY MAP AND STACK PC<12:0> PC<12:0> CALL, RETURN 13 CALL, RETURN 13 RETFIE, RETLW RETFIE, RETLW Stack Level 1 Stack Level 1 Stack Level 2 Stack Level 2 Stack Level 8 Stack Level 8 RESET Vector 0000h RESET Vector 0000h Interrupt Vector 0004h Interrupt Vector 0004h 0005h 0005h Page 0 Page 0 07FFh On-Chip 07FFh Program 0800h Memory 0800h Page 1 Page 1 On-Chip 0FFFh Program 0FFFh Memory 1000h 1000h Page 2 17FFh 1800h Page 3 1FFFh 1FFFh  1998-2013 Microchip Technology Inc. DS30292D-page 11

PIC16F87X 2.2 Data Memory Organization Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special The data memory is partitioned into multiple banks Function Registers. Above the Special Function Regis- which contain the General Purpose Registers and the ters are General Purpose Registers, implemented as Special Function Registers. Bits RP1 (STATUS<6>) static RAM. All implemented banks contain Special and RP0 (STATUS<5>) are the bank select bits. Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. RP1:RP0 Bank Note: EEPROM Data Memory description can be 00 0 found in Section 4.0 of this data sheet. 01 1 2.2.1 GENERAL PURPOSE REGISTER 10 2 FILE 11 3 The register file can be accessed either directly, or indi- rectly through the File Select Register (FSR). DS30292D-page 12  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP FFiillee File File File AAddddrreessss Address Address Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h 107h 187h PORTD(1) 08h TRISD(1) 88h 108h 188h PORTE(1) 09h TRISE(1) 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDATA 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved(2) 18Eh TMR1H 0Fh 8Fh EEADRH 10Fh Reserved(2) 18Fh T1CON 10h 90h 110h 190h TMR2 11h SSPCON2 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPR1L 15h 95h 115h 195h CCPR1H 16h 96h 116h 196h CCP1CON 17h 97h General 117h General 197h Purpose Purpose RCSTA 18h TXSTA 98h Register 118h Register 198h TXREG 19h SPBRG 99h 16 Bytes 119h 16 Bytes 199h RCREG 1Ah 9Ah 11Ah 19Ah CCPR2L 1Bh 9Bh 11Bh 19Bh CCPR2H 1Ch 9Ch 11Ch 19Ch CCP2CON 1Dh 9Dh 11Dh 19Dh ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh 20h A0h 120h 1A0h General General General General Purpose Purpose Purpose Purpose Register Register Register Register 80 Bytes 80 Bytes 80 Bytes 96 Bytes EFh 16Fh 1EFh accesses F0h accesses 170h accesses 1F0h 70h-7Fh 70h-7Fh 70h - 7Fh 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are not implemented on the PIC16F876. 2: These registers are reserved, maintain these registers clear.  1998-2013 Microchip Technology Inc. DS30292D-page 13

PIC16F87X FIGURE 2-4: PIC16F874/873 REGISTER FILE MAP File File File File Address Address Address Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h 107h 187h PORTD(1) 08h TRISD(1) 88h 108h 188h PORTE(1) 09h TRISE(1) 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDATA 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved(2) 18Eh TMR1H 0Fh 8Fh EEADRH 10Fh Reserved(2) 18Fh T1CON 10h 90h 110h 190h TMR2 11h SSPCON2 91h T2CON 12h PR2 92h SSPBUF 13h SSPADD 93h SSPCON 14h SSPSTAT 94h CCPR1L 15h 95h CCPR1H 16h 96h CCP1CON 17h 97h RCSTA 18h TXSTA 98h TXREG 19h SPBRG 99h RCREG 1Ah 9Ah CCPR2L 1Bh 9Bh CCPR2H 1Ch 9Ch CCP2CON 1Dh 9Dh ADRESH 1Eh ADRESL 9Eh ADCON0 1Fh ADCON1 9Fh 120h 1A0h 20h A0h General General Purpose Purpose accesses accesses Register Register 20h-7Fh A0h - FFh 96 Bytes 96 Bytes 16Fh 1EFh 170h 1F0h 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are not implemented on the PIC16F873. 2: These registers are reserved, maintain these registers clear. DS30292D-page 14  1998-2013 Microchip Technology Inc.

PIC16F87X 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers The Special Function Registers are registers used by associated with the core functions are described in the CPU and peripheral modules for controlling the detail in this section. Those related to the operation of desired operation of the device. These registers are the peripheral features are described in detail in the implemented as static RAM. A list of these registers is peripheral features section. given in Table2-1. TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY Value on: Details Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, on BOR page: Bank 0 00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27 01h TMR0 Timer0 Module Register xxxx xxxx 47 02h(3) PCL Program Counter (PC) Least Significant Byte 0000 0000 26 03h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18 04h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 27 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 29 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 33 08h(4) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx 35 09h(4) PORTE — — — — — RE2 RE1 RE0 ---- -xxx 36 0Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26 0Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20 0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 22 0Dh PIR2 — (5) — EEIF BCLIF — — CCP2IF -r-0 0--0 24 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 52 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 52 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 51 11h TMR2 Timer2 Module Register 0000 0000 55 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 55 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 70, 73 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 67 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx 57 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx 57 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 58 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 96 19h TXREG USART Transmit Data Register 0000 0000 99 1Ah RCREG USART Receive Data Register 0000 0000 101 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx 57 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx 57 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 58 1Eh ADRESH A/D Result Register High Byte xxxx xxxx 116 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 111 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’. 5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS30292D-page 15

PIC16F87X TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on: Details Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, on BOR page: Bank 1 80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19 82h(3) PCL Program Counter (PC) Least Significant Byte 0000 0000 26 83h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18 84h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 27 85h TRISA — — PORTA Data Direction Register --11 1111 29 86h TRISB PORTB Data Direction Register 1111 1111 31 87h TRISC PORTC Data Direction Register 1111 1111 33 88h(4) TRISD PORTD Data Direction Register 1111 1111 35 89h(4) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 37 8Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26 8Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20 8Ch PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 21 8Dh PIE2 — (5) — EEIE BCLIE — — CCP2IE -r-0 0--0 23 8Eh PCON — — — — — — POR BOR ---- --qq 25 8Fh — Unimplemented — — 90h — Unimplemented — — 91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 68 92h PR2 Timer2 Period Register 1111 1111 55 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 73, 74 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 66 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 95 99h SPBRG Baud Rate Generator Register 0000 0000 97 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 116 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 112 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’. 5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear. DS30292D-page 16  1998-2013 Microchip Technology Inc.

PIC16F87X TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on: Details Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, on BOR page: Bank 2 100h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27 101h TMR0 Timer0 Module Register xxxx xxxx 47 102h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 26 103h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18 104h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 27 105h — Unimplemented — — 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26 10Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20 10Ch EEDATA EEPROM Data Register Low Byte xxxx xxxx 41 10Dh EEADR EEPROM Address Register Low Byte xxxx xxxx 41 10Eh EEDATH — — EEPROM Data Register High Byte xxxx xxxx 41 10Fh EEADRH — — — EEPROM Address Register High Byte xxxx xxxx 41 Bank 3 180h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19 182h(3) PCL Program Counter (PC) Least Significant Byte 0000 0000 26 183h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18 184h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 27 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 31 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26 18Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20 18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 41, 42 18Dh EECON2 EEPROM Control Register2 (not a physical register) ---- ---- 41 18Eh — Reserved maintain clear 0000 0000 — 18Fh — Reserved maintain clear 0000 0000 — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’. 5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS30292D-page 17

PIC16F87X 2.2.2.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register contains the arithmetic status of as 000u u1uu (where u = unchanged). the ALU, the RESET status and the bank select bits for data memory. It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the The STATUS register can be the destination for any STATUS register, because these instructions do not instruction, as with any other register. If the STATUS affect the Z, C or DC bits from the STATUS register. For register is the destination for an instruction that affects other instructions not affecting any status bits, see the the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary." disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not Note: The C and DC bits operate as a borrow writable, therefore, the result of an instruction with the and digit borrow bit, respectively, in sub- STATUS register as destination may be different than traction. See the SUBLW and SUBWF intended. instructions for examples. REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high, or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30292D-page 18  1998-2013 Microchip Technology Inc.

PIC16F87X 2.2.2.2 OPTION_REG Register Note: To achieve a 1:1 prescaler assignment for The OPTION_REG Register is a readable and writable the TMR0 register, assign the prescaler to register, which contains various control bits to configure the Watchdog Timer. the TMR0 prescaler/WDT postscaler (single assign- able register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper oper- ation of the device  1998-2013 Microchip Technology Inc. DS30292D-page 19

PIC16F87X 2.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt The INTCON Register is a readable and writable regis- condition occurs, regardless of the state of ter, which contains various enable and flag bits for the its corresponding enable bit or the global TMR0 register overflow, RB Port change and External enable bit, GIE (INTCON<7>). User soft- RB0/INT pin interrupts. ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit 7 bit 0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software). 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30292D-page 20  1998-2013 Microchip Technology Inc.

PIC16F87X 2.2.2.4 PIE1 Register The PIE1 register contains the individual enable bits for Note: Bit PEIE (INTCON<6>) must be set to the peripheral interrupts. enable any peripheral interrupt. REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PSPIE is reserved on PIC16F873/876 devices; always maintain this bit clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30292D-page 21

PIC16F87X 2.2.2.5 PIR1 Register Note: Interrupt flag bits are set when an interrupt The PIR1 register contains the individual flag bits for condition occurs, regardless of the state of the peripheral interrupts. its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate interrupt bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag 1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are: • SPI - A transmission/reception has taken place. • I2C Slave - A transmission/reception has taken place. • I2C Master - A transmission/reception has taken place. - The initiated START condition was completed by the SSP module. - The initiated STOP condition was completed by the SSP module. - The initiated Restart condition was completed by the SSP module. - The initiated Acknowledge condition was completed by the SSP module. - A START condition occurred while the SSP module was idle (Multi-Master system). - A STOP condition occurred while the SSP module was idle (Multi-Master system). 0 = No SSP interrupt condition has occurred. bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: PSPIF is reserved on PIC16F873/876 devices; always maintain this bit clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30292D-page 22  1998-2013 Microchip Technology Inc.

PIC16F87X 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write operation interrupt. REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh) U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — Reserved — EEIE BCLIE — — CCP2IE bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6 Reserved: Always maintain this bit clear bit 5 Unimplemented: Read as '0' bit 4 EEIE: EEPROM Write Operation Interrupt Enable 1 = Enable EE Write Interrupt 0 = Disable EE Write Interrupt bit 3 BCLIE: Bus Collision Interrupt Enable 1 = Enable Bus Collision Interrupt 0 = Disable Bus Collision Interrupt bit 2-1 Unimplemented: Read as '0' bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30292D-page 23

PIC16F87X 2.2.2.7 PIR2 Register . Note: Interrupt flag bits are set when an interrupt The PIR2 register contains the flag bits for the CCP2 condition occurs, regardless of the state of interrupt, the SSP bus collision interrupt and the its corresponding enable bit or the global EEPROM write operation interrupt. enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh) U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — Reserved — EEIF BCLIF — — CCP2IF bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6 Reserved: Always maintain this bit clear bit 5 Unimplemented: Read as '0' bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision has occurred in the SSP, when configured for I2C Master mode 0 = No bus collision has occurred bit 2-1 Unimplemented: Read as '0' bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30292D-page 24  1998-2013 Microchip Technology Inc.

PIC16F87X 2.2.2.8 PCON Register Note: BOR is unknown on POR. It must be set by The Power Control (PCON) Register contains flag bits the user and checked on subsequent to allow differentiation between a Power-on Reset RESETS to see if BOR is clear, indicating (POR), a Brown-out Reset (BOR), a Watchdog Reset a brown-out has occurred. The BOR status (WDT), and an external MCLR Reset. bit is a “don’t care” and is not predictable if the brown-out circuit is disabled (by clear- ing the BODEN bit in the configuration word). REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1 — — — — — — POR BOR bit 7 bit 0 bit 7-2 Unimplemented: Read as '0' bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30292D-page 25

PIC16F87X 2.3 PCL and PCLATH Note 1: There are no status bits to indicate stack The program counter (PC) is 13-bits wide. The low byte overflow or stack underflow conditions. comes from the PCL register, which is a readable and 2: There are no instructions/mnemonics writable register. The upper bits (PC<12:8>) are not called PUSH or POP. These are actions readable, but are indirectly writable through the that occur from the execution of the PCLATH register. On any RESET, the upper bits of the CALL, RETURN, RETLW and RETFIE PC will be cleared. Figure2-5 shows the two situations instructions, or the vectoring to an inter- for the loading of the PC. The upper example in the fig- rupt address. ure shows how the PC is loaded on a write to PCL (PCLATH<4:0>  PCH). The lower example in the fig- 2.4 Program Memory Paging ure shows how the PC is loaded during a CALL or GOTO All PIC16F87X devices are capable of addressing a instruction (PCLATH<4:3>  PCH). continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of FIGURE 2-5: LOADING OF PC IN address to allow branching within any 2K program DIFFERENT SITUATIONS memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCH PCL PCLATH<4:3>. When doing a CALL or GOTO instruc- 12 8 7 0 Instruction with tion, the user must ensure that the page select bits are PC PCL as programmed so that the desired program memory Destination page is addressed. If a return from a CALL instruction PCLATH<4:0> 8 5 ALU (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the return instruc- PCLATH tions (which POPs the address from the stack). PCH PCL Note: The contents of the PCLATH register are 12 11 10 8 7 0 unchanged after a RETURN or RETFIE PC GOTO,CALL instruction is executed. The user must PCLATH<4:3> 11 rewrite the contents of the PCLATH regis- 2 Opcode <10:0> ter for any subsequent subroutine calls or GOTO instructions. PCLATH Example2-1 shows the calling of a subroutine in page1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt 2.3.1 COMPUTED GOTO Service Routine (if interrupts are used). A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a EXAMPLE 2-1: CALL OF A SUBROUTINE table read using a computed GOTO method, care IN PAGE 1 FROM PAGE 0 should be exercised if the table location crosses a PCL ORG 0x500 memory boundary (each 256 byte block). Refer to the BCF PCLATH,4 application note, “Implementing a Table Read" BSF PCLATH,3 ;Select page 1 (AN556). ;(800h-FFFh) CALL SUB1_P1 ;Call subroutine in 2.3.2 STACK : ;page 1 (800h-FFFh) : The PIC16F87X family has an 8-level deep x 13-bit wide ORG 0x900 ;page 1 (800h-FFFh) hardware stack. The stack space is not part of either pro- SUB1_P1 gram or data space and the stack pointer is not readable : ;called subroutine or writable. The PC is PUSHed onto the stack when a ;page 1 (800h-FFFh) CALL instruction is executed, or an interrupt causes a : RETURN ;return to branch. The stack is POPed in the event of a ;Call subroutine RETURN,RETLW or a RETFIE instruction execution. ;in page 0 PCLATH is not affected by a PUSH or POP operation. ;(000h-7FFh) The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). DS30292D-page 26  1998-2013 Microchip Technology Inc.

PIC16F87X 2.5 Indirect Addressing, INDF and A simple program to clear RAM locations 20h-2Fh FSR Registers using indirect addressing is shown in Example2-2. The INDF register is not a physical register. Addressing EXAMPLE 2-2: INDIRECT ADDRESSING the INDF register will cause indirect addressing. MOVLW 0x20 ;initialize pointer Indirect addressing is possible by using the INDF reg- MOVWF FSR ;to RAM ister. Any instruction using the INDF register actually NEXT CLRF INDF ;clear INDF register accesses the register pointed to by the File Select Reg- INCF FSR,F ;inc pointer BTFSS FSR,4 ;all done? ister, FSR. Reading the INDF register itself, indirectly GOTO NEXT ;no clear next (FSR = '0') will read 00h. Writing to the INDF register CONTINUE indirectly results in a no operation (although status bits : ;yes continue may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure2-6. FIGURE 2-6: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1:RP0 6 From Opcode 0 IRP 7 FSR register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 80h 100h 180h Data Memory(1) 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note1: For register file map detail, see Figure2-3.  1998-2013 Microchip Technology Inc. DS30292D-page 27

PIC16F87X NOTES: DS30292D-page 28  1998-2013 Microchip Technology Inc.

PIC16F87X 3.0 I/O PORTS FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the Data Data Latch device. In general, when a peripheral is enabled, that Bus D Q pin may not be used as a general purpose I/O pin. VDD WR Additional information on I/O ports may be found in the Port PIC® MCU Mid-Range Reference Manual, (DS33023). CK Q P I/O pin(1) 3.1 PORTA and the TRISA Register TRIS Latch N D Q PORTA is a 6-bit wide, bi-directional port. The corre- sponding data direction register is TRISA. Setting a WR TRISA bit (= 1) will make the corresponding PORTA pin TRIS CK Q VSS an input (i.e., put the corresponding output driver in a Analog Hi-Impedance mode). Clearing a TRISA bit (= 0) will Input Mode make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). RD Reading the PORTA register reads the status of the TRIS TTL pins, whereas writing to it will write to the port latch. All Input write operations are read-modify-write operations. Buffer Q D Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. EN Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI RD Port pin is a Schmitt Trigger input and an open drain output. All other PORTA pins have TTL input levels and full To A/D Converter CMOS output drivers. Other PORTA pins are multiplexed with analog inputs Note 1: I/O pins have protection diodes to VDD and VSS. and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the FIGURE 3-2: BLOCK DIAGRAM OF ADCON1 register (A/D Control Register1). RA4/T0CKI PIN Note: On a Power-on Reset, these pins are con- figured as analog inputs and read as '0'. Data Data Latch Bus D Q The TRISA register controls the direction of the RA WR pins, even when they are being used as analog inputs. Port The user must ensure the bits in the TRISA register are CK Q I/O pin(1) N maintained set when using them as analog inputs. TRIS Latch D Q VSS EXAMPLE 3-1: INITIALIZING PORTA WR TRIS BCF STATUS, RP0 ; CK Q Schmitt Trigger BCF STATUS, RP1 ; Bank0 Input CLRF PORTA ; Initialize PORTA by Buffer ; clearing output RD ; data latches TRIS BSF STATUS, RP0 ; Select Bank 1 MOVLW 0x06 ; Configure all pins MOVWF ADCON1 ; as digital inputs Q D MOVLW 0xCF ; Value used to ; initialize data ENEN ; direction RD Port MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6>are always TMR0 Clock Input ; read as '0'. Note 1: I/O pin has protection diodes to VSS only.  1998-2013 Microchip Technology Inc. DS30292D-page 29

PIC16F87X TABLE 3-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2 bit2 TTL Input/output or analog input. RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF. RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input. Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of the following modes, where PCFG3:PCFG0 = 0100,0101, 011x, 1101, 1110, 1111. DS30292D-page 30  1998-2013 Microchip Technology Inc.

PIC16F87X 3.2 PORTB and the TRISB Register This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the PORTB is an 8-bit wide, bi-directional port. The corre- interrupt in the following manner: sponding data direction register is TRISB. Setting a a) Any read or write of PORTB. This will end the TRISB bit (= 1) will make the corresponding PORTB pin mismatch condition. an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will b) Clear flag bit RBIF. make the corresponding PORTB pin an output (i.e., put A mismatch condition will continue to set flag bit RBIF. the contents of the output latch on the selected pin). Reading PORTB will end the mismatch condition and Three pins of PORTB are multiplexed with the Low allow flag bit RBIF to be cleared. Voltage Programming function: RB3/PGM, RB6/PGC The interrupt-on-change feature is recommended for and RB7/PGD. The alternate functions of these pins wake-up on key depression operation and operations are described in the Special Features Section. where PORTB is only used for the interrupt-on-change Each of the PORTB pins has a weak internal pull-up. A feature. Polling of PORTB is not recommended while single control bit can turn on all the pull-ups. This is per- using the interrupt-on-change feature. formed by clearing bit RBPU (OPTION_REG<7>). The This interrupt-on-mismatch feature, together with soft- weak pull-up is automatically turned off when the port ware configureable pull-ups on these four pins, allow pin is configured as an output. The pull-ups are dis- easy interface to a keypad and make it possible for abled on a Power-on Reset. wake-up on key depression. Refer to the Embedded Control Handbook, “Implementing Wake-up on Key FIGURE 3-3: BLOCK DIAGRAM OF Strokes” (AN552). RB3:RB0 PINS RB0/INT is an external interrupt input pin and is config- VDD ured using the INTEDG bit (OPTION_REG<6>). RBPU(2) Weak RB0/INT is discussed in detail in Section12.10.1. PPull-up Data Latch Data Bus FIGURE 3-4: BLOCK DIAGRAM OF D Q I/O RB7:RB4 PINS WR Port CK pin(1) VDD TRIS Latch RBPU(2) D Q P Weak TTL Pull-up WR TRIS Input Data Latch CK Buffer Data Bus D Q I/O WR Port CK pin(1) RD TRIS TRIS Latch D Q Q D RD Port WR TRIS TTL CK EN Input Buffer ST Buffer RB0/INT RB3/PGM RD TRIS Latch Schmitt Trigger RD Port Buffer Q D RD Port Note 1: I/O pins have diode protection to VDD and VSS. EN Q1 2: To enable weak pull-ups, set the appropriate TRIS Set RBIF bit(s) and clear the RBPU bit (OPTION_REG<7>). Q D Four of the PORTB pins, RB7:RB4, have an interrupt- From other RD Port on-change feature. Only pins configured as inputs can RB7:RB4 pins EN cause this interrupt to occur (i.e., any RB7:RB4 pin Q3 configured as an output is excluded from the interrupt- RB7:RB6 on-change comparison). The input pins (of RB7:RB4) In Serial Programming Mode are compared with the old value latched on the last Note 1: I/O pins have diode protection to VDD and VSS. read of PORTB. The “mismatch” outputs of RB7:RB4 2: To enable weak pull-ups, set the appropriate TRIS are OR’ed together to generate the RB Port Change bit(s) and clear the RBPU bit (OPTION_REG<7>). Interrupt with flag bit RBIF (INTCON<0>).  1998-2013 Microchip Technology Inc. DS30292D-page 31

PIC16F87X TABLE 3-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3/PGM(3) bit3 TTL Input/output pin or programming pin in LVP mode. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB6/PGC bit6 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming clock. RB7/PGD bit7 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB3 I/O function. LVP must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and 40-pin mid-range devices. TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30292D-page 32  1998-2013 Microchip Technology Inc.

PIC16F87X 3.3 PORTC and the TRISC Register FIGURE 3-6: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT PORTC is an 8-bit wide, bi-directional port. The corre- OVERRIDE) RC<4:3> sponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC Port/Peripheral Select(2) pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will Peripheral Data Out 0 make the corresponding PORTC pin an output (i.e., put VDD Data Bus the contents of the output latch on the selected pin). WR D Q P I/O PORTC is multiplexed with several peripheral functions Port CK Q 1 pin(1) (Table3-5). PORTC pins have Schmitt Trigger input Data Latch buffers. D Q When the I2C module is enabled, the PORTC<4:3> WR pins can be configured with normal I2C levels, or with TRIS CK Q N SMBus levels by using the CKE bit (SSPSTAT<6>). TRIS Latch When enabling peripheral functions, care should be RD Vss taken in defining TRIS bits for each PORTC pin. Some TRIS Schmitt peripherals override the TRIS bit to make a pin an out- Trigger put, while other peripherals override the TRIS bit to Peripheral make a pin an input. Since the TRIS bit override is in OE(3) Q D Schmitt effect while the peripheral is enabled, read-modify- Trigger EN with write instructions (BSF, BCF, XORWF) with TRISC as RD SMBus Port 0 levels destination, should be avoided. The user should refer SSPl Input to the corresponding peripheral section for the correct TRIS bit settings. 1 CKE FIGURE 3-5: PORTC BLOCK DIAGRAM SSPSTAT<6> (PERIPHERAL OUTPUT Note 1: I/O pins have diode protection to VDD and VSS. OVERRIDE) RC<2:0>, 2: Port/Peripheral select signal selects between port data RC<7:5> and peripheral output. 3: Peripheral OE (output enable) is only activated if Port/Peripheral Select(2) peripheral select is active. Peripheral Data Out 0 VDD Data Bus D Q WR P I/O Port CK Q 1 pin(1) Data Latch D Q WR TRIS CK Q N TRIS Latch VSS RD TRIS Schmitt Trigger Peripheral OE(3) Q D EN RD Port Peripheral Input Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active.  1998-2013 Microchip Technology Inc. DS30292D-page 33

PIC16F87X TABLE 3-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output. RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive or Synchronous Data. Legend: ST = Schmitt Trigger input TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged DS30292D-page 34  1998-2013 Microchip Technology Inc.

PIC16F87X 3.4 PORTD and TRISD Registers FIGURE 3-7: PORTD BLOCK DIAGRAM (IN I/O PORT MODE) PORTD and TRISD are not implemented on the PIC16F873 or PIC16F876. Data Data Latch I/O pin(1) Bus PORTD is an 8-bit port with Schmitt Trigger input buff- D Q ers. Each pin is individually configureable as an input or WR Port output. CK PORTD can be configured as an 8-bit wide micropro- TRIS Latch cessor port (parallel slave port) by setting control bit D Q PSPMODE (TRISE<4>). In this mode, the input buffers WR are TTL. TRIS CK Schmitt Trigger Input Buffer RD TRIS Q D ENEN RD Port Note 1: I/O pins have protection diodes to VDD and VSS. TABLE 3-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0. RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1. RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2. RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3. RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4. RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5. RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6. RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. TABLE 3-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.  1998-2013 Microchip Technology Inc. DS30292D-page 35

PIC16F87X 3.5 PORTE and TRISE Register FIGURE 3-8: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) PORTE and TRISE are not implemented on the PIC16F873 or PIC16F876. Data Data Latch I/O pin(1) PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6, Bus D Q and RE2/CS/AN7) which are individually configureable WR as inputs or outputs. These pins have Schmitt Trigger Port CK input buffers. TRIS Latch The PORTE pins become the I/O control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is D Q set. In this mode, the user must make certain that the WR TRISE<2:0> bits are set, and that the pins are configured TRIS CK Schmitt Trigger as digital inputs. Also ensure that ADCON1 is configured Input for digital I/O. In this mode, the input buffers are TTL. Buffer RD Register3-1 shows the TRISE register, which also con- TRIS trols the parallel slave port operation. PORTE pins are multiplexed with analog inputs. When Q D selected for analog input, these pins will read as '0's. TRISE controls the direction of the RE pins, even when ENEN they are being used as analog inputs. The user must RD Port make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, these pins are con- Note 1: I/O pins have protection diodes to VDD and VSS. figured as analog inputs, and read as ‘0’. TABLE 3-9: PORTE FUNCTIONS Name Bit# Buffer Type Function I/O port pin or read control input in Parallel Slave Port mode or analog input: RD RE0/RD/AN5 bit0 ST/TTL(1) 1 = Idle 0 = Read operation. Contents of PORTD register are output to PORTD I/O pins (if chip selected) I/O port pin or write control input in Parallel Slave Port mode or analog input: WR RE1/WR/AN6 bit1 ST/TTL(1) 1 = Idle 0 = Write operation. Value of PORTD I/O pins is latched into PORTD register (if chip selected) I/O port pin or chip select control input in Parallel Slave Port mode or analog input: CS RE2/CS/AN7 bit2 ST/TTL(1) 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. TABLE 3-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE. DS30292D-page 36  1998-2013 Microchip Technology Inc.

PIC16F87X REGISTER 3-1: TRISE REGISTER (ADDRESS 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — Bit2 Bit1 Bit0 bit 7 bit 0 Parallel Slave Port Status/Control Bits: bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = PORTD functions in Parallel Slave Port mode 0= PORTD functions in general purpose I/O mode bit 3 Unimplemented: Read as '0' PORTE Data Direction Bits: bit 2 Bit2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output bit 1 Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0 Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30292D-page 37

PIC16F87X 3.6 Parallel Slave Port When not in PSP mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previously set, it The Parallel Slave Port (PSP) is not implemented on must be cleared in firmware. the PIC16F873 or PIC16F876. An interrupt is generated and latched into flag bit PORTD operates as an 8-bit wide Parallel Slave Port or PSPIF when a read or write operation is completed. microprocessor port, when control bit PSPMODE PSPIF must be cleared by the user in firmware and the (TRISE<4>) is set. In Slave mode, it is asynchronously interrupt can be disabled by clearing the interrupt readable and writable by the external world through RD enable bit PSPIE (PIE1<7>). control input pin RE0/RD and WR control input pin RE1/WR. FIGURE 3-9: PORTD AND PORTE The PSP can directly interface to an 8-bit microproces- BLOCK DIAGRAM sor data bus. The external microprocessor can read or (PARALLEL SLAVE write the PORTD latch as an 8-bit latch. Setting bit PORT) PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the cor- Data Bus responding data direction bits of the TRISE register D Q (TRISE<2:0>) must be configured as inputs (set). The WR RDx Port A/D port configuration bits PCFG3:PCFG0 CK pin (ADCON1<3:0>) must be set to configure pins TTL RE2:RE0 as digital I/O. Q D There are actually two 8-bit latches: one for data out- put, and one for data input. The user writes 8-bit data RD ENEN to the PORTD data latch and reads data from the port Port pin latch (note that they have the same address). In this mode, the TRISD register is ignored, since the external One bit of PORTD device is controlling the direction of data flow. Set Interrupt Flag A write to the PSP occurs when both the CS and WR PSPIF(PIR1<7>) lines are first detected low. When either the CS or WR lines become high (level triggered), the Input Buffer Full (IBF) status flag bit (TRISE<7>) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is Read TTL RD complete (Figure3-10). The interrupt flag bit PSPIF (PIR1<7>) is also set on the same Q4 clock cycle. IBF Chip Select can only be cleared by reading the PORTD input latch. TTL CS The Input Buffer Overflow (IBOV) status flag bit Write (TRISE<5>) is set if a second write to the PSP is TTL WR attempted when the previous byte has not been read out of the buffer. Note 1: I/O pins have protection diodes to VDD and VSS. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full (OBF) status flag bit (TRISE<6>) is cleared immedi- ately (Figure3-11), indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the inter- rupt flag bit PSPIF is set on the Q4 clock cycle, follow- ing the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware. DS30292D-page 38  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 3-10: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 3-11: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 3-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 08h PORTD Port Data Latch when written: Port pins when read xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS30292D-page 39

PIC16F87X NOTES: DS30292D-page 40  1998-2013 Microchip Technology Inc.

PIC16F87X 4.0 DATA EEPROM AND FLASH The EEPROM data memory allows byte read and write PROGRAM MEMORY operations without interfering with the normal operation of the microcontroller. When interfacing to EEPROM The Data EEPROM and FLASH Program Memory are data memory, the EEADR register holds the address to readable and writable during normal operation over the be accessed. Depending on the operation, the EEDATA entire VDD range. These operations take place on a sin- register holds the data to be written, or the data read, at gle byte for Data EEPROM memory and a single word the address in EEADR. The PIC16F873/874 devices for Program memory. A write operation causes an have 128 bytes of EEPROM data memory and there- erase-then-write operation to take place on the speci- fore, require that the MSb of EEADR remain clear. The fied byte or word. A bulk erase operation may not be EEPROM data memory on these devices do not wrap issued from user code (which includes removing code around to 0, i.e., 0x80 in the EEADR does not map to protection). 0x00. The PIC16F876/877 devices have 256 bytes of EEPROM data memory and therefore, uses all 8-bits of Access to program memory allows for checksum calcu- the EEADR. lation. The values written to program memory do not need to be valid instructions. Therefore, up to 14-bit The FLASH program memory allows non-intrusive numbers can be stored in memory for use as calibra- read access, but write operations cause the device to tion parameters, serial numbers, packed 7-bit ASCII, stop executing instructions, until the write completes. etc. Executing a program memory location containing When interfacing to the program memory, the data that form an invalid instruction, results in the exe- EEADRH:EEADR registers form a two-byte word, cution of a NOP instruction. which holds the 13-bit address of the memory location being accessed. The register combination of The EEPROM Data memory is rated for high erase/ EEDATH:EEDATA holds the 14-bit data for writes, or write cycles (specification D120). The FLASH program reflects the value of program memory after a read oper- memory is rated much lower (specification D130), ation. Just as in EEPROM data memory accesses, the because EEPROM data memory can be used to store value of the EEADRH:EEADR registers must be within frequently updated values. An on-chip timer controls the valid range of program memory, depending on the the write time and it will vary with voltage and tempera- device: 0000h to 1FFFh for the PIC16F873/874, or ture, as well as from chip to chip. Please refer to the 0000h to 3FFFh for the PIC16F876/877. Addresses specifications for exact limits (specifications D122 and outside of this range do not wrap around to 0000h (i.e., D133). 4000h does not map to 0000h on the PIC16F877). A byte or word write automatically erases the location and writes the new value (erase before write). Writing 4.1 EECON1 and EECON2 Registers to EEPROM data memory does not impact the opera- The EECON1 register is the control register for config- tion of the device. Writing to program memory will uring and initiating the access. The EECON2 register is cease the execution of instructions until the write is not a physically implemented register, but is used complete. The program memory cannot be accessed exclusively in the memory write sequence to prevent during the write. During the write operation, the oscilla- inadvertent writes. tor continues to run, the peripherals continue to func- tion and interrupt events will be detected and There are many bits used to control the read and write essentially “queued” until the write is complete. When operations to EEPROM data and FLASH program the write completes, the next instruction in the pipeline memory. The EEPGD bit determines if the access will is executed and the branch to the interrupt vector will be a program or data memory access. When clear, any take place, if the interrupt is enabled and occurred dur- subsequent operations will work on the EEPROM data ing the write. memory. When set, all subsequent operations will operate in the program memory. Read and write access to both memories take place indirectly through a set of Special Function Registers Read operations only use one additional bit, RD, which (SFR). The six SFRs used are: initiates the read operation from the desired memory location. Once this bit is set, the value of the desired • EEDATA memory location will be available in the data registers. • EEDATH This bit cannot be cleared by firmware. It is automati- • EEADR cally cleared at the end of the read operation. For • EEADRH EEPROM data memory reads, the data will be avail- • EECON1 able in the EEDATA register in the very next instruction • EECON2 cycle after the RD bit is set. For program memory reads, the data will be loaded into the EEDATH:EEDATA registers, following the second instruction after the RD bit is set.  1998-2013 Microchip Technology Inc. DS30292D-page 41

PIC16F87X Write operations have two control bits, WR and WREN, cute instructions. The desired memory location pointed and two status bits, WRERR and EEIF. The WREN bit to by EEADRH:EEADR will be erased. Then, the data is used to enable or disable the write operation. When value in EEDATH:EEDATA will be programmed. When WREN is clear, the write operation will be disabled. complete, the EEIF flag bit will be set and the microcon- Therefore, the WREN bit must be set before executing troller will continue to execute code. a write operation. The WR bit is used to initiate the write The WRERR bit is used to indicate when the operation. It also is automatically cleared at the end of PIC16F87X device has been reset during a write oper- the write operation. The interrupt flag EEIF is used to ation. WRERR should be cleared after Power-on determine when the memory write completes. This flag Reset. Thereafter, it should be checked on any other must be cleared in software before setting the WR bit. RESET. The WRERR bit is set when a write operation For EEPROM data memory, once the WREN bit and is interrupted by a MCLR Reset, or a WDT Time-out the WR bit have been set, the desired memory address Reset, during normal operation. In these situations, fol- in EEADR will be erased, followed by a write of the data lowing a RESET, the user should check the WRERR bit in EEDATA. This operation takes place in parallel with and rewrite the memory location, if set. The contents of the microcontroller continuing to execute normally. the data registers, address registers and EEPGD bit When the write is complete, the EEIF flag bit will be set. are not affected by either MCLR Reset, or WDT Time- For program memory, once the WREN bit and the WR out Reset, during normal operation. bit have been set, the microcontroller will cease to exe- REGISTER 4-1: EECON1 REGISTER (ADDRESS 18Ch) R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — — WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory (This bit cannot be changed while a read or write operation is in progress) bit 6-4 Unimplemented: Read as '0' bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset or any WDT Reset during normal operation) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read. (RD is cleared in hardware. The RD bit can only be set (not cleared) in software.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30292D-page 42  1998-2013 Microchip Technology Inc.

PIC16F87X 4.2 Reading the EEPROM Data The steps to write to EEPROM data memory are: Memory 1. If step 10 is not implemented, check the WR bit to see if a write is in progress. Reading EEPROM data memory only requires that the 2. Write the address to EEADR. Make sure that the desired address to access be written to the EEADR address is not larger than the memory size of register and clear the EEPGD bit. After the RD bit is set, the PIC16F87X device. data will be available in the EEDATA register on the very next instruction cycle. EEDATA will hold this value 3. Write the 8-bit data value to be programmed in until another read operation is initiated or until it is writ- the EEDATA register. ten by firmware. 4. Clear the EEPGD bit to point to EEPROM data memory. The steps to reading the EEPROM data memory are: 5. Set the WREN bit to enable program operations. 1. Write the address to EEDATA. Make sure that 6. Disable interrupts (if enabled). the address is not larger than the memory size of the PIC16F87X device. 7. Execute the special five instruction sequence: 2. Clear the EEPGD bit to point to EEPROM data • Write 55h to EECON2 in two steps (first to W, memory. then to EECON2) 3. Set the RD bit to start the read operation. • Write AAh to EECON2 in two steps (first to W, then to EECON2) 4. Read the data from the EEDATA register. • Set the WR bit EXAMPLE 4-1: EEPROM DATA READ 8. Enable interrupts (if using interrupts). BSF STATUS, RP1 ; 9. Clear the WREN bit to disable program opera- BCF STATUS, RP0 ;Bank 2 tions. MOVF ADDR, W ;Write address 10. At the completion of the write cycle, the WR bit MOVWF EEADR ;to read from is cleared and the EEIF interrupt flag bit is set. BSF STATUS, RP0 ;Bank 3 (EEIF must be cleared by firmware.) If step 1 is BCF EECON1, EEPGD ;Point to Data memory not implemented, then firmware should check BSF EECON1, RD ;Start read operation for EEIF to be set, or WR to clear, to indicate the BCF STATUS, RP0 ;Bank 2 end of the program cycle. MOVF EEDATA, W ;W = EEDATA EXAMPLE 4-2: EEPROM DATA WRITE BSF STATUS, RP1 ; 4.3 Writing to the EEPROM Data BSF STATUS, RP0 ;Bank 3 BTFSC EECON1, WR ;Wait for Memory GOTO $-1 ;write to finish BCF STATUS, RP0 ;Bank 2 There are many steps in writing to the EEPROM data MOVF ADDR, W ;Address to memory. Both address and data values must be written MOVWF EEADR ;write to to the SFRs. The EEPGD bit must be cleared, and the MOVF VALUE, W ;Data to WREN bit must be set, to enable writes. The WREN bit MOVWF EEDATA ;write should be kept clear at all times, except when writing to BSF STATUS, RP0 ;Bank 3 the EEPROM data. The WR bit can only be set if the BCF EECON1, EEPGD ;Point to Data memory WREN bit was set in a previous operation, i.e., they BSF EECON1, WREN ;Enable writes both cannot be set in the same operation. The WREN ;Only disable interrupts bit should then be cleared by firmware after the write. BCF INTCON, GIE ;if already enabled, ;otherwise discard Clearing the WREN bit before the write actually com- MOVLW 0x55 ;Write 55h to pletes will not terminate the write in progress. MOVWF EECON2 ;EECON2 Writes to EEPROM data memory must also be pref- MOVLW 0xAA ;Write AAh to aced with a special sequence of instructions, that pre- MOVWF EECON2 ;EECON2 vent inadvertent write operations. This is a sequence of BSF EECON1, WR ;Start write operation five instructions that must be executed without interrup- ;Only enable interrupts BSF INTCON, GIE ;if using interrupts, tions. The firmware should verify that a write is not in ;otherwise discard progress, before starting another cycle. BCF EECON1, WREN ;Disable writes  1998-2013 Microchip Technology Inc. DS30292D-page 43

PIC16F87X 4.4 Reading the FLASH Program 4.5 Writing to the FLASH Program Memory Memory Reading FLASH program memory is much like that of Writing to FLASH program memory is unique, in that EEPROM data memory, only two NOP instructions must the microcontroller does not execute instructions while be inserted after the RD bit is set. These two instruction programming is taking place. The oscillator continues cycles that the NOP instructions execute, will be used to run and all peripherals continue to operate and by the microcontroller to read the data out of program queue interrupts, if enabled. Once the write operation memory and insert the value into the completes (specification D133), the processor begins EEDATH:EEDATA registers. Data will be available fol- executing code from where it left off. The other impor- lowing the second NOP instruction. EEDATH and tant difference when writing to FLASH program mem- EEDATA will hold their value until another read opera- ory, is that the WRT configuration bit, when clear, tion is initiated, or until they are written by firmware. prevents any writes to program memory (see Table4-1). The steps to reading the FLASH program memory are: Just like EEPROM data memory, there are many steps in writing to the FLASH program memory. Both address 1. Write the address to EEADRH:EEADR. Make and data values must be written to the SFRs. The sure that the address is not larger than the mem- EEPGD bit must be set, and the WREN bit must be set ory size of the PIC16F87X device. to enable writes. The WREN bit should be kept clear at 2. Set the EEPGD bit to point to FLASH program all times, except when writing to the FLASH Program memory. memory. The WR bit can only be set if the WREN bit 3. Set the RD bit to start the read operation. was set in a previous operation, i.e., they both cannot 4. Execute two NOP instructions to allow the micro- be set in the same operation. The WREN bit should controller to read out of program memory. then be cleared by firmware after the write. Clearing the 5. Read the data from the EEDATH:EEDATA WREN bit before the write actually completes will not registers. terminate the write in progress. Writes to program memory must also be prefaced with EXAMPLE 4-3: FLASH PROGRAM READ a special sequence of instructions that prevent inad- BSF STATUS, RP1 ; vertent write operations. This is a sequence of five BCF STATUS, RP0 ;Bank 2 instructions that must be executed without interruption MOVF ADDRL, W ;Write the for each byte written. These instructions must then be MOVWF EEADR ;address bytes followed by two NOP instructions to allow the microcon- MOVF ADDRH,W ;for the desired troller to setup for the write operation. Once the write is MOVWF EEADRH ;address to read complete, the execution of instructions starts with the BSF STATUS, RP0 ;Bank 3 instruction after the second NOP. BSF EECON1, EEPGD ;Point to Program memory BSF EECON1, RD ;Start read operation The steps to write to program memory are: NOP ;Required two NOPs 1. Write the address to EEADRH:EEADR. Make NOP ; sure that the address is not larger than the mem- BCF STATUS, RP0 ;Bank 2 ory size of the PIC16F87X device. MOVF EEDATA, W ;DATAL = EEDATA MOVWF DATAL ; 2. Write the 14-bit data value to be programmed in MOVF EEDATH,W ;DATAH = EEDATH the EEDATH:EEDATA registers. MOVWF DATAH ; 3. Set the EEPGD bit to point to FLASH program memory. 4. Set the WREN bit to enable program operations. 5. Disable interrupts (if enabled). 6. Execute the special five instruction sequence: • Write 55h to EECON2 in two steps (first to W, then to EECON2) • Write AAh to EECON2 in two steps (first to W, then to EECON2) • Set the WR bit 7. Execute two NOP instructions to allow the micro- controller to setup for write operation. 8. Enable interrupts (if using interrupts). 9. Clear the WREN bit to disable program operations. DS30292D-page 44  1998-2013 Microchip Technology Inc.

PIC16F87X At the completion of the write cycle, the WR bit is 4.7 Protection Against Spurious cleared and the EEIF interrupt flag bit is set. (EEIF Writes must be cleared by firmware.) Since the microcontroller does not execute instructions during the write cycle, the There are conditions when the device may not want to firmware does not necessarily have to check either write to the EEPROM data memory or FLASH program EEIF, or WR, to determine if the write had finished. memory. To protect against these spurious write condi- tions, various mechanisms have been built into the EXAMPLE 4-4: FLASH PROGRAM WRITE PIC16F87X devices. On power-up, the WREN bit is cleared and the Power-up Timer (if enabled) prevents BSF STATUS, RP1 ; writes. BCF STATUS, RP0 ;Bank 2 MOVF ADDRL, W ;Write address The write initiate sequence, and the WREN bit MOVWF EEADR ;of desired together, help prevent any accidental writes during MOVF ADDRH, W ;program memory brown-out, power glitches, or firmware malfunction. MOVWF EEADRH ;location MOVF VALUEL, W ;Write value to 4.8 Operation While Code Protected MOVWF EEDATA ;program at MOVF VALUEH, W ;desired memory The PIC16F87X devices have two code protect mecha- MOVWF EEDATH ;location nisms, one bit for EEPROM data memory and two bits for BSF STATUS, RP0 ;Bank 3 FLASH program memory. Data can be read and written BSF EECON1, EEPGD ;Point to Program memory to the EEPROM data memory, regardless of the state of BSF EECON1, WREN ;Enable writes the code protection bit, CPD. When code protection is ;Only disable interrupts enabled and CPD cleared, external access via ICSP is BCF INTCON, GIE ;if already enabled, ;otherwise discard disabled, regardless of the state of the program memory MOVLW 0x55 ;Write 55h to code protect bits. This prevents the contents of EEPROM MOVWF EECON2 ;EECON2 data memory from being read out of the device. MOVLW 0xAA ;Write AAh to The state of the program memory code protect bits, MOVWF EECON2 ;EECON2 CP0 and CP1, do not affect the execution of instruc- BSF EECON1, WR ;Start write operation tions out of program memory. The PIC16F87X devices NOP ;Two NOPs to allow micro NOP ;to setup for write can always read the values in program memory, ;Only enable interrupts regardless of the state of the code protect bits. How- BSF INTCON, GIE ;if using interrupts, ever, the state of the code protect bits and the WRT bit ;otherwise discard will have different effects on writing to program mem- ory. Table 4-1 shows the effect of the code protect bits BCF EECON1, WREN ;Disable writes and the WRT bit on program memory. 4.6 Write Verify Once code protection has been enabled for either EEPROM data memory or FLASH program memory, The PIC16F87X devices do not automatically verify the only a full erase of the entire device will disable code value written during a write operation. Depending on protection. the application, good programming practice may dic- tate that the value written to memory be verified against the original value. This should be used in applications where excessive writes can stress bits near the speci- fied endurance limits.  1998-2013 Microchip Technology Inc. DS30292D-page 45

PIC16F87X 4.9 FLASH Program Memory Write Protection The configuration word contains a bit that write protects the FLASH program memory, called WRT. This bit can only be accessed when programming the PIC16F87X device via ICSP. Once write protection is enabled, only an erase of the entire device will disable it. When enabled, write protection prevents any writes to FLASH program memory. Write protection does not affect pro- gram memory reads. TABLE 4-1: READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY Configuration Bits Internal Internal Memory Location ICSP Read ICSP Write Read Write CP1 CP0 WRT 0 0 x All program memory Yes No No No 0 1 0 Unprotected areas Yes No Yes No 0 1 0 Protected areas Yes No No No 0 1 1 Unprotected areas Yes Yes Yes No 0 1 1 Protected areas Yes No No No 1 0 0 Unprotected areas Yes No Yes No 1 0 0 Protected areas Yes No No No 1 0 1 Unprotected areas Yes Yes Yes No 1 0 1 Protected areas Yes No No No 1 1 0 All program memory Yes No Yes Yes 1 1 1 All program memory Yes Yes Yes Yes TABLE 4-2: REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 10Dh EEADR EEPROM Address Register, Low Byte xxxx xxxx uuuu uuuu 10Fh EEADRH — — — EEPROM Address, High Byte xxxx xxxx uuuu uuuu 10Ch EEDATA EEPROM Data Register, Low Byte xxxx xxxx uuuu uuuu 10Eh EEDATH — — EEPROM Data Register, High Byte xxxx xxxx uuuu uuuu 18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 x--- u000 18Dh EECON2 EEPROM Control Register2 (not a physical register) — — 8Dh PIE2 — (1) — EEIE BCLIE — — CCP2IE -r-0 0--0 -r-0 0--0 0Dh PIR2 — (1) — EEIF BCLIF — — CCP2IF -r-0 0--0 -r-0 0--0 Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'. Shaded cells are not used during FLASH/EEPROM access. Note 1: These bits are reserved; always maintain these bits clear. DS30292D-page 46  1998-2013 Microchip Technology Inc.

PIC16F87X 5.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will The Timer0 module timer/counter has the following fea- increment either on every rising, or falling edge of pin tures: RA4/T0CKI. The incrementing edge is determined by • 8-bit timer/counter the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the ris- • Readable and writable ing edge. Restrictions on the external clock input are • 8-bit software programmable prescaler discussed in detail in Section5.2. • Internal or external clock select The prescaler is mutually exclusively shared between • Interrupt on overflow from FFh to 00h the Timer0 module and the Watchdog Timer. The pres- • Edge select for external clock caler is not readable or writable. Section5.3 details the Figure5-1 is a block diagram of the Timer0 module and operation of the prescaler. the prescaler shared with the WDT. 5.1 Timer0 Interrupt Additional information on the Timer0 module is avail- able in the PIC® MCU Mid-Range Family Reference The TMR0 interrupt is generated when the TMR0 reg- Manual (DS33023). ister overflows from FFh to 00h. This overflow sets bit Timer mode is selected by clearing bit T0CS T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be (OPTION_REG<5>). In Timer mode, the Timer0 mod- ule will increment every instruction cycle (without pres- cleared in software by the Timer0 module Interrupt Ser- vice Routine before re-enabling this interrupt. The caler). If the TMR0 register is written, the increment is TMR0 interrupt cannot awaken the processor from inhibited for the following two instruction cycles. The SLEEP, since the timer is shut-off during SLEEP. user can work around this by writing an adjusted value to the TMR0 register. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKOUT (= FOSC/4) Data Bus 8 M 0 1 RA4/T0CKI U M SYNC pin 1 X 0 U 2 TMR0 Reg X Cycles T0SE T0CS PSA Set Flag Bit T0IF on Overflow PRESCALER 0 8-bit Prescaler M U Watchdog 1 X 8 Timer 8 - to - 1MUX PS2:PS0 PSA 0 1 WDT Enable bit M U X PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).  1998-2013 Microchip Technology Inc. DS30292D-page 47

PIC16F87X 5.2 Using Timer0 with an External Timer0 module means that there is no prescaler for the Clock Watchdog Timer, and vice-versa. This prescaler is not readable or writable (see Figure5-1). When no prescaler is used, the external clock input is The PSA and PS2:PS0 bits (OPTION_REG<3:0>) the same as the prescaler output. The synchronization determine the prescaler assignment and prescale ratio. of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and When assigned to the Timer0 module, all instructions Q4 cycles of the internal phase clocks. Therefore, it is writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, necessary for T0CKI to be high for at least 2Tosc (and BSF 1,x....etc.) will clear the prescaler. When assigned a small RC delay of 20 ns) and low for at least 2Tosc to WDT, a CLRWDT instruction will clear the prescaler (and a small RC delay of 20 ns). Refer to the electrical along with the Watchdog Timer. The prescaler is not specification of the desired device. readable or writable. Note: Writing to TMR0, when the prescaler is 5.3 Prescaler assigned to Timer0, will clear the prescaler There is only one prescaler available, which is mutually count, but will not change the prescaler exclusively shared between the Timer0 module and the assignment. Watchdog Timer. A prescaler assignment for the REGISTER 5-1: OPTION_REG REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU bit 6 INTEDG bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: To avoid an unintended device RESET, the instruction sequence shown in the PIC® MCU Mid-Range Fam- ily Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. DS30292D-page 48  1998-2013 Microchip Technology Inc.

PIC16F87X TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 01h,101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.  1998-2013 Microchip Technology Inc. DS30292D-page 49

PIC16F87X NOTES: DS30292D-page 50  1998-2013 Microchip Technology Inc.

PIC16F87X 6.0 TIMER1 MODULE In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising The Timer1 module is a 16-bit timer/counter consisting edge of the external clock input. of two 8-bit registers (TMR1H and TMR1L), which are Timer1 can be enabled/disabled by setting/clearing readable and writable. The TMR1 Register pair control bit TMR1ON (T1CON<0>). (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, Timer1 also has an internal “RESET input”. This is generated on overflow, which is latched in interrupt RESET can be generated by either of the two CCP flag bit TMR1IF (PIR1<0>). This interrupt can be modules (Section8.0). Register6-1 shows the Timer1 enabled/disabled by setting/clearing TMR1 interrupt control register. enable bit TMR1IE (PIE1<0>). When the Timer1 oscillator is enabled (T1OSCEN is Timer1 can operate in one of two modes: set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is • As a timer ignored, and these pins read as ‘0’. • As a counter Additional information on timer modules is available in The operating mode is determined by the clock select the PIC® MCU Mid-Range Family Reference Manual bit, TMR1CS (T1CON<1>). (DS33023). REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30292D-page 51

PIC16F87X 6.1 Timer1 Operation in Timer Mode 6.2 Timer1 Counter Operation Timer mode is selected by clearing the TMR1CS Timer1 may operate in either a Synchronous, or an (T1CON<1>) bit. In this mode, the input clock to the Asynchronous mode, depending on the setting of the timer is FOSC/4. The synchronize control bit T1SYNC TMR1CS bit. (T1CON<2>) has no effect, since the internal clock is When Timer1 is being incremented via an external always in sync. source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment. FIGURE 6-1: TIMER1 INCREMENTING EDGE T1CKI (Default High) T1CKI (Default Low) Note: Arrows indicate counter increments. 6.3 Timer1 Operation in Synchronized If T1SYNC is cleared, then the external clock input is Counter Mode synchronized with internal phase clocks. The synchro- nization is done after the prescaler stage. The Counter mode is selected by setting bit TMR1CS. In prescaler stage is an asynchronous ripple-counter. this mode, the timer increments on every rising edge of In this configuration, during SLEEP mode, Timer1 will clock input on pin RC1/T1OSI/CCP2, when bit not increment even if the external clock is present, T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when since the synchronization circuit is shut-off. The bit T1OSCEN is cleared. prescaler, however, will continue to increment. FIGURE 6-2: TIMER1 BLOCK DIAGRAM Set Flag bit TMR1IF on Overflow Synchronized TMR1 0 Clock Input TMR1H TMR1L 1 TMR1ON On/Off T1SYNC T1OSC RC0/T1OSO/T1CKI 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 RC1/T1OSI/CCP2(2) Oscillator(1) Clock 2 Q Clock T1CKPS1:T1CKPS0 TMR1CS Note1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. DS30292D-page 52  1998-2013 Microchip Technology Inc.

PIC16F87X 6.4 Timer1 Operation in TABLE 6-1: CAPACITOR SELECTION FOR Asynchronous Counter Mode THE TIMER1 OSCILLATOR If control bit T1SYNC (T1CON<2>) is set, the external Osc Type Freq. C1 C2 clock input is not synchronized. The timer continues to LP 32 kHz 33 pF 33 pF increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can 100 kHz 15 pF 15 pF generate an interrupt-on-overflow, which will wake-up 200 kHz 15 pF 15 pF the processor. However, special precautions in soft- These values are for design guidance only. ware are needed to read/write the timer (Section6.4.1). Crystals Tested: In Asynchronous Counter mode, Timer1 cannot be 32.768 kHz Epson C-001R32.768K-A ± 20 PPM used as a time-base for capture or compare opera- 100 kHz Epson C-2 100.00 KC-P ± 20 PPM tions. 200 kHz STD XTL 200.000 kHz ± 20 PPM 6.4.1 READING AND WRITING TIMER1 IN Note 1: Higher capacitance increases the stability ASYNCHRONOUS COUNTER of oscillator, but also increases the start-up MODE time. 2: Since each resonator/crystal has its own Reading TMR1H or TMR1L while the timer is running characteristics, the user should consult the from an external asynchronous clock, will guarantee a resonator/crystal manufacturer for appro- valid read (taken care of in hardware). However, the priate values of external components. user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since 6.6 Resetting Timer1 using a CCP the timer may overflow between the reads. Trigger Output For writes, it is recommended that the user simply stop If the CCP1 or CCP2 module is configured in Compare the timer and write the desired values. A write conten- mode to generate a “special event trigger” tion may occur by writing to the timer registers, while (CCP1M3:CCP1M0 = 1011), this signal will reset the register is incrementing. This may produce an Timer1. unpredictable value in the timer register. Reading the 16-bit value requires some care. Exam- Note: The special event triggers from the CCP1 ples 12-2 and 12-3 in the PIC® MCU Mid-Range Family and CCP2 modules will not set interrupt Reference Manual (DS33023) show how to read and flag bit TMR1IF (PIR1<0>). write Timer1 when it is running in Asynchronous mode. Timer1 must be configured for either Timer or Synchro- nized Counter mode to take advantage of this feature. 6.5 Timer1 Oscillator If Timer1 is running in Asynchronous Counter mode, A crystal oscillator circuit is built-in between pins T1OSI this RESET operation may not work. (input) and T1OSO (amplifier output). It is enabled by In the event that a write to Timer1 coincides with a spe- setting control bit T1OSCEN (T1CON<3>). The oscilla- cial event trigger from CCP1 or CCP2, the write will tor is a low power oscillator, rated up to 200 kHz. It will take precedence. continue to run during SLEEP. It is primarily intended In this mode of operation, the CCPRxH:CCPRxL regis- for use with a 32 kHz crystal. Table6-1 shows the ter pair effectively becomes the period register for capacitor selection for the Timer1 oscillator. Timer1. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.  1998-2013 Microchip Technology Inc. DS30292D-page 53

PIC16F87X 6.7 Resetting of Timer1 Register Pair 6.8 Timer1 Prescaler (TMR1H, TMR1L) The prescaler counter is cleared on writes to the TMR1H and TMR1L registers are not reset to 00h on a TMR1H or TMR1L registers. POR, or any other RESET, except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected. TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear. DS30292D-page 54  1998-2013 Microchip Technology Inc.

PIC16F87X 7.0 TIMER2 MODULE Register7-1 shows the Timer2 control register. Additional information on timer modules is available in Timer2 is an 8-bit timer with a prescaler and a the PIC® MCU Mid-Range Family Reference Manual postscaler. It can be used as the PWM time-base for (DS33023). the PWM mode of the CCP module(s). The TMR2 reg- ister is readable and writable, and is cleared on any FIGURE 7-1: TIMER2 BLOCK DIAGRAM device RESET. The input clock (FOSC/4) has a prescale option of 1:1, Sets Flag TMR2 1:4, or 1:16, selected by control bits bit TMR2IF Output(1) T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. RESET TMR2 Reg Prescaler FOSC/4 1:1, 1:4, 1:16 Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is Postscaler Comparator 2 a readable and writable register. The PR2 register is 1:1 to 1:16 EQ T2CKPS1: initialized to FFh upon RESET. 4 PR2 Reg T2CKPS0 The match output of TMR2 goes through a 4-bit T2OUTPS3: postscaler (which gives a 1:1 to 1:16 scaling inclusive) T2OUTPS0 to generate a TMR2 interrupt (latched in flag bit Note 1:TMR2 register output can be software selected by the TMR2IF, (PIR1<1>)). SSP module as a baud clock. Timer2 can be shut-off by clearing control bit TMR2ON (T2CON<2>), to minimize power consumption. REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30292D-page 55

PIC16F87X 7.1 Timer2 Prescaler and Postscaler 7.2 Output of TMR2 The prescaler and postscaler counters are cleared The output of TMR2 (before the postscaler) is fed to the when any of the following occurs: SSP module, which optionally uses it to generate shift clock. • a write to the TMR2 register • a write to the T2CON register • any device RESET (POR, MCLR Reset, WDT Reset, or BOR) TMR2 is not cleared when T2CON is written. TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module. Note1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear. DS30292D-page 56  1998-2013 Microchip Technology Inc.

PIC16F87X 8.0 CAPTURE/COMPARE/PWM CCP2 Module: MODULES Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and Each Capture/Compare/PWM (CCP) module contains CCPR2H (high byte). The CCP2CON register controls a 16-bit register which can operate as a: the operation of CCP2. The special event trigger is • 16-bit Capture register generated by a compare match and will reset Timer1 • 16-bit Compare register and start an A/D conversion (if the A/D module is enabled). • PWM Master/Slave Duty Cycle register Additional information on CCP modules is available in Both the CCP1 and CCP2 modules are identical in the PIC® MCU Mid-Range Family Reference Manual operation, with the exception being the operation of the (DS33023) and in application note AN594, “Using the special event trigger. Table8-1 and Table8-2 show the CCP Modules” (DS00594). resources and interactions of the CCP module(s). In the following sections, the operation of a CCP module TABLE 8-1: CCP MODE - TIMER is described with respect to CCP1. CCP2 operates the RESOURCES REQUIRED same as CCP1, except where noted. CCP1 Module: CCP Mode Timer Resource Capture/Compare/PWM Register1 (CCPR1) is com- Capture Timer1 prised of two 8-bit registers: CCPR1L (low byte) and Compare Timer1 CCPR1H (high byte). The CCP1CON register controls PWM Timer2 the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1. TABLE 8-2: INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture Same TMR1 time-base Capture Compare The compare should be configured for the special event trigger, which clears TMR1 Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1 PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt) PWM Capture None PWM Compare None  1998-2013 Microchip Technology Inc. DS30292D-page 57

PIC16F87X REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1Dh) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits 0000 =Capture/Compare/PWM disabled (resets CCPx module) 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, set output on match (CCPxIF bit is set) 1001 =Compare mode, clear output on match (CCPxIF bit is set) 1010 =Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 =Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx =PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30292D-page 58  1998-2013 Microchip Technology Inc.

PIC16F87X 8.1 Capture Mode 8.1.2 TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode, or Synchro- 16-bit value of the TMR1 register when an event occurs nized Counter mode, for the CCP module to use the on pin RC2/CCP1. An event is defined as one of the fol- capture feature. In Asynchronous Counter mode, the lowing: capture operation may not work. • Every falling edge 8.1.3 SOFTWARE INTERRUPT • Every rising edge When the Capture mode is changed, a false capture • Every 4th rising edge interrupt may be generated. The user should keep bit • Every 16th rising edge CCP1IE (PIE1<2>) clear to avoid false interrupts and The type of event is configured by control bits should clear the flag bit CCP1IF, following any such CCP1M3:CCP1M0 (CCPxCON<3:0>). When a cap- change in operating mode. ture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. The interrupt flag must be cleared in 8.1.4 CCP PRESCALER software. If another capture occurs before the value in There are four prescaler settings, specified by bits register CCPR1 is read, the old captured value is over- CCP1M3:CCP1M0. Whenever the CCP module is written by the new value. turned off, or the CCP module is not in Capture mode, 8.1.1 CCP PIN CONFIGURATION the prescaler counter is cleared. Any RESET will clear the prescaler counter. In Capture mode, the RC2/CCP1 pin should be config- Switching from one capture prescaler to another may ured as an input by setting the TRISC<2> bit. generate an interrupt. Also, the prescaler counter will Note: If the RC2/CCP1 pin is configured as an not be cleared, therefore, the first capture may be from output, a write to the port can cause a cap- a non-zero prescaler. Example8-1 shows the recom- ture condition. mended method for switching between capture pres- calers. This example also clears the prescaler counter and will not generate the “false” interrupt. FIGURE 8-1: CAPTURE MODE OPERATION BLOCK DIAGRAM EXAMPLE 8-1: CHANGING BETWEEN CAPTURE PRESCALERS RC2/CCP1 Set Flag bit CCP1IF pin (PIR1<2>) CLRF CCP1CON ; Turn CCP module off Prescaler MOVLW NEW_CAPT_PS ; Load the W reg with  1, 4, 16 ; the new prescaler CCPR1H CCPR1L ; move value and CCP ON MOVWF CCP1CON ; Load CCP1CON with this and Capture ; value edge detect Enable TMR1H TMR1L CCP1CON<3:0> Qs  1998-2013 Microchip Technology Inc. DS30292D-page 59

PIC16F87X 8.2 Compare Mode 8.2.2 TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is Timer1 must be running in Timer mode, or Synchro- constantly compared against the TMR1 register pair nized Counter mode, if the CCP module is using the value. When a match occurs, the RC2/CCP1 pin is: compare feature. In Asynchronous Counter mode, the compare operation may not work. • Driven high • Driven low 8.2.3 SOFTWARE INTERRUPT MODE • Remains unchanged When Generate Software Interrupt mode is chosen, the The action on the pin is based on the value of control CCP1 pin is not affected. The CCPIF bit is set, causing bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the a CCP interrupt (if enabled). same time, interrupt flag bit CCP1IF is set. 8.2.4 SPECIAL EVENT TRIGGER FIGURE 8-2: COMPARE MODE In this mode, an internal hardware trigger is generated, OPERATION BLOCK which may be used to initiate an action. DIAGRAM The special event trigger output of CCP1 resets the Special event trigger will: TMR1 register pair. This allows the CCPR1 register to reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>). effectively be a 16-bit programmable period register for Timer1. Special Event Trigger The special event trigger output of CCP2 resets the Set Flag bit CCP1IF TMR1 register pair and starts an A/D conversion (if the (PIR1<2>) A/D module is enabled). RC2/CCP1 CCPR1H CCPR1L pin Note: The special event trigger from the Q S Output CCP1and CCP2 modules will not set inter- R Logic Match Comparator rupt flag bit TMR1IF (PIR1<0>). TRISC<2> TMR1H TMR1L Output Enable CCP1CON<3:0> Mode Select 8.2.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an out- put by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch. DS30292D-page 60  1998-2013 Microchip Technology Inc.

PIC16F87X 8.3 PWM Mode (PWM) 8.3.1 PWM PERIOD In Pulse Width Modulation mode, the CCPx pin pro- The PWM period is specified by writing to the PR2 reg- duces up to a 10-bit resolution PWM output. Since the ister. The PWM period can be calculated using the fol- CCP1 pin is multiplexed with the PORTC data latch, lowing formula: the TRISC<2> bit must be cleared to make the CCP1 PWM period =[(PR2) + 1] • 4 (cid:129) TOSC (cid:129) pin an output. (TMR2 prescale value) Note: Clearing the CCP1CON register will force PWM frequency is defined as 1 / [PWM period]. the CCP1 PWM output latch to the default When TMR2 is equal to PR2, the following three events low level. This is not the PORTC I/O data occur on the next increment cycle: latch. • TMR2 is cleared Figure8-3 shows a simplified block diagram of the • The CCP1 pin is set (exception: if PWM duty CCP module in PWM mode. cycle=0%, the CCP1 pin will not be set) For a step-by-step procedure on how to set up the CCP • The PWM duty cycle is latched from CCPR1L into module for PWM operation, see Section8.3.3. CCPR1H FIGURE 8-3: SIMPLIFIED PWM BLOCK Note: The Timer2 postscaler (see Section7.1) is DIAGRAM not used in the determination of the PWM frequency. The postscaler could be used CCP1CON<5:4> Duty Cycle Registers to have a servo update rate at a different CCPR1L frequency than the PWM output. 8.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1H (Slave) CCPR1L register and to the CCP1CON<5:4> bits. Up RC2/CCP1 to 10-bit resolution is available. The CCPR1L contains Comparator R Q the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is TMR2 (Note 1) S used to calculate the PWM duty cycle in time: PWM duty cycle =(CCPR1L:CCP1CON<5:4>) (cid:129) Comparator TRISC<2> Clear Timer, TOSC (cid:129) (TMR2 prescale value) CCP1 pin and CCPR1L and CCP1CON<5:4> can be written to at any latch D.C. PR2 time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 Note 1: The 8-bit timer is concatenated with 2-bit internal Q occurs (i.e., the period is complete). In PWM mode, clock, or 2 bits of the prescaler, to create 10-bit time- CCPR1H is a read-only register. base. The CCPR1H register and a 2-bit internal latch are A PWM output (Figure8-4) has a time-base (period) used to double buffer the PWM duty cycle. This double and a time that the output stays high (duty cycle). The buffering is essential for glitch-free PWM operation. frequency of the PWM is the inverse of the period (1/period). When the CCPR1H and 2-bit latch match TMR2, con- catenated with an internal 2-bit Q clock, or 2 bits of the FIGURE 8-4: PWM OUTPUT TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM Period frequency is given by the formula: (FOSC ) log Resolution = FPWM bits Duty Cycle log(2) TMR2 = PR2 Note: If the PWM duty cycle value is longer than TMR2 = Duty Cycle the PWM period, the CCP1 pin will not be cleared. TMR2 = PR2  1998-2013 Microchip Technology Inc. DS30292D-page 61

PIC16F87X 8.3.3 SETUP FOR PWM OPERATION 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. The following steps should be taken when configuring 4. Set the TMR2 prescale value and enable Timer2 the CCP module for PWM operation: by writing to T2CON. 1. Set the PWM period by writing to the PR2 5. Configure the CCP1 module for PWM operation. register. 2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFFh 0xFFh 0xFFh 0x3Fh 0x1Fh 0x17h Maximum Resolution (bits) 10 10 10 8 7 5.5 TABLE 8-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: The PSP is not implemented on the PIC16F873/876; always maintain these bits clear. DS30292D-page 62  1998-2013 Microchip Technology Inc.

PIC16F87X TABLE 8-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000 92h PR2 Timer2 Module’s Period Register 1111 1111 1111 1111 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS30292D-page 63

PIC16F87X NOTES: DS30292D-page 64  1998-2013 Microchip Technology Inc.

PIC16F87X 9.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) Figure9-1 shows a block diagram for the SPI mode, while Figure9-5 and Figure9-9 show the block dia- grams for the two different I2C modes of operation. The Application Note AN734, “Using the PIC® MCU SSP for Slave I2CTM Communication” describes the slave operation of the MSSP module on the PIC16F87X devices. AN735, “Using the PIC® MCU MSSP Module for I2CTM Communications” describes the master operation of the MSSP module on the PIC16F87X devices.  1998-2013 Microchip Technology Inc. DS30292D-page 65

PIC16F87X REGISTER 9-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in slave mode In I 2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select (Figure9-2, Figure9-3 and Figure9-4) SPI mode: For CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK For CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK In I 2 C Master or Slave mode: 1 = Input levels conform to SMBus spec 0 = Input levels conform to I2C specs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: STOP bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a STOP bit has been detected last (this bit is '0' on RESET) 0 = STOP bit was not detected last bit 3 S: START bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a START bit has been detected last (this bit is '0' on RESET) 0 = START bit was not detected last bit 2 R/W: Read/Write bit Information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Logical OR of this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode. bit 1 UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I 2 C mode only): 1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30292D-page 66  1998-2013 Microchip Technology Inc.

PIC16F87X REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to SSPBUF was attempted while the I2C conditions were not valid 0 = No collision Slave mode: 1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid overflows. In Master mode, the overflow bit is not set, since each operation is initiated by writing to the SSPBUF register. (Must be cleared in software.) 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in Transmit mode. (Must be cleared in software.) 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In SPI mode, When enabled, these pins must be properly configured as input or output 1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode, When enabled, these pins must be properly configured as input or output 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I 2 C Slave mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C Master mode: Unused in this mode bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1)) 1011 = I2C Firmware Controlled Master mode (slave idle) 1110 = I2C Firmware Controlled Master mode, 7-bit address with START and STOP bit interrupts enabled 1111 = I2C Firmware Controlled Master mode, 10-bit address with START and STOP bit interrupts enabled 1001, 1010, 1100, 1101 = Reserved Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30292D-page 67

PIC16F87X REGISTER 9-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (In I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (In I2C Master mode only) In Master Transmit mode: 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (In I2C Master mode only) In Master Receive mode: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (In I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: STOP Condition Enable bit (In I2C Master mode only) SCK Release Control: 1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0 = STOP condition idle bit 1 RSEN: Repeated START Condition Enable bit (In I2C Master mode only) 1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated START condition idle bit 0 SEN: START Condition Enable bit (In I2C Master mode only) 1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = START condition idle Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling), and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30292D-page 68  1998-2013 Microchip Technology Inc.

PIC16F87X 9.1 SPI Mode Any serial port function that is not desired may be overridden by programming the corresponding data The SPI mode allows 8 bits of data to be synchronously direction (TRIS) register to the opposite value. transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communi- FIGURE 9-1: MSSP BLOCK DIAGRAM cation, typically three pins are used: (SPIMODE) • Serial Data Out (SDO) • Serial Data In (SDI) Internal Data Bus • Serial Clock (SCK) Read Write Additionally, a fourth pin may be used when in a Slave mode of operation: SSPBUF Reg • Slave Select (SS) When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>). SSPSR Reg These control bits allow the following to be specified: SDI bit0 Shift Clock • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) SDO • Clock Polarity (Idle state of SCK) • Data input sample phase SS Control (middle or end of data output time) Enable • Clock edge SS Edge (output data on rising/falling edge of SCK) Select • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) 2 Clock Select Figure9-4 shows the block diagram of the MSSP mod- ule when in SPI mode. SSPM3:SSPM0 To enable the serial port, MSSP Enable bit, SSPEN SMP:CKE 4 TMR2 Output (SSPCON<5>) must be set. To reset or reconfigure SPI 2 2 mode, clear bit SSPEN, re-initialize the SSPCON reg- Edge isters, and then set bit SSPEN. This configures the Select Prescaler TOSC SCK 4, 16, 64 SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must Data to TX/RX in SSPSR have their data direction bits (in the TRIS register) Data Direction bit appropriately programmed. That is: • SDI is automatically controlled by the SPI module • SDO must have TRISC<5> cleared • SCK (Master mode) must have TRISC<3> cleared • SCK (Slave mode) must have TRISC<3> set • SS must have TRISA<5> set and register ADCON1 (see Section11.0: A/D Module) must be set in a way that pin RA5 is configured as a digital I/O  1998-2013 Microchip Technology Inc. DS30292D-page 69

PIC16F87X 9.1.1 MASTER MODE Figure9-6, Figure9-8 and Figure9-9, where the MSb is transmitted first. In Master mode, the SPI clock rate (bit The master can initiate the data transfer at any time rate) is user programmable to be one of the following: because it controls the SCK. The master determines when the slave (Processor 2, Figure9-5) is to broad- • FOSC/4 (or TCY) cast data by the software protocol. • FOSC/16 (or 4 • TCY) In Master mode, the data is transmitted/received as • FOSC/64 (or 16 • TCY) soon as the SSPBUF register is written to. If the SPI • Timer2 output/2 module is only going to receive, the SDO output could This allows a maximum bit clock frequency (at 20 MHz) be disabled (programmed as an input). The SSPSR of 5.0 MHz. register will continue to shift in the signal present on the Figure9-6 shows the waveforms for Master mode. SDI pin at the programmed clock rate. As each byte is When CKE=1, the SDO data is valid before there is a received, it will be loaded into the SSPBUF register as clock edge on SCK. The change of the input sample is if a normal received byte (interrupts and status bits shown based on the state of the SMP bit. The time appropriately set). This could be useful in receiver when the SSPBUF is loaded with the received data is applications as a “line activity monitor”. shown. The clock polarity is selected by appropriately program- ming bit CKP (SSPCON<4>). This then, would give waveforms for SPI communication as shown in FIGURE 9-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF DS30292D-page 70  1998-2013 Microchip Technology Inc.

PIC16F87X 9.1.2 SLAVE MODE While in SLEEP mode, the slave can transmit/receive data. When a byte is received, the device will wake-up In Slave mode, the data is transmitted and received as from SLEEP. the external clock pulses appear on SCK. When the last bit is latched, the interrupt flag bit SSPIF (PIR1<3>) is set. Note 1: When the SPI module is in Slave mode with SS pin control enabled While in Slave mode, the external clock is supplied by (SSPCON<3:0> = 0100), the SPI module the external clock source on the SCK pin. This external will reset if the SS pin is set to VDD. clock must meet the minimum high and low times as specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE='1', then SS pin control must be enabled. FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE=0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE=1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF  1998-2013 Microchip Technology Inc. DS30292D-page 71

PIC16F87X TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION Value on: Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: These bits are reserved on PCI16F873/876 devices; always maintain these bits clear. DS30292D-page 72  1998-2013 Microchip Technology Inc.

PIC16F87X 9.2 MSSP I2C Operation The SSPCON register allows control of the I2C opera- tion. Four mode selection bits (SSPCON<3:0>) allow The MSSP module in I2C mode, fully implements all one of the following I2C modes to be selected: master and slave functions (including general call sup- • I2C Slave mode (7-bit address) port) and provides interrupts on START and STOP bits in hardware, to determine a free bus (multi-master func- • I2C Slave mode (10-bit address) tion). The MSSP module implements the standard mode • I2C Master mode, clock = OSC/4 (SSPADD +1) specifications, as well as 7-bit and 10-bit addressing. • I2C firmware modes (provided for compatibility to Refer to Application Note AN578, "Use of the SSP other mid-range products) Module in the I2C Multi-Master Environment." Before selecting any I2C mode, the SCL and SDA pins A "glitch" filter is on the SCL and SDA pins when the pin must be programmed to inputs by setting the appropri- is an input. This filter operates in both the 100 kHz and ate TRIS bits. Selecting an I2C mode by setting the 400 kHz modes. In the 100 kHz mode, when these pins SSPEN bit, enables the SCL and SDA pins to be used are an output, there is a slew rate control of the pin that as the clock and data lines in I2C mode. Pull-up resis- is independent of device frequency. tors must be provided externally to the SCL and SDA pins for the proper operation of the I2C module. FIGURE 9-5: I2C SLAVE MODE BLOCK The CKE bit (SSPSTAT<6:7>) sets the levels of the DIAGRAM SDA and SCL pins in either Master or Slave mode. When CKE = 1, the levels will conform to the SMBus Internal specification. When CKE = 0, the levels will conform to Data Bus the I2C specification. Read Write The SSPSTAT register gives the status of the data transfer. This information includes detection of a SCL SSPBUF Reg START (S) or STOP (P) bit, specifies if the received byte was data or address, if the next byte is the com- Shift pletion of 10-bit address, and if this will be a read or Clock write data transfer. SSPSR Reg SSPBUF is the register to which the transfer data is SDA MSb LSb written to, or read from. The SSPSR register shifts the data in or out of the device. In receive operations, the Match Detect Addr Match SSPBUF and SSPSR create a doubled buffered receiver. This allows reception of the next byte to begin before reading the last byte of received data. When the SSPADD Reg complete byte is received, it is transferred to the SSPBUF register and flag bit SSPIF is set. If another START and Set, Reset complete byte is received before the SSPBUF register STOP bit Detect S, P bits is read, a receiver overflow has occurred and bit (SSPSTAT Reg) SSPOV (SSPCON<6>) is set and the byte in the SSPSR is lost. Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SDA pin, which is the The SSPADD register holds the slave address. In data. The SDA and SCL pins are automatically config- 10-bit mode, the user needs to write the high byte of the ured when the I2C mode is enabled. The SSP module address (1111 0 A9 A8 0). Following the high byte functions are enabled by setting SSP Enable bit address match, the low byte of the address needs to be SSPEN (SSPCON<5>). loaded (A7:A0). The MSSP module has six registers for I2C operation. They are the: • SSP Control Register (SSPCON) • SSP Control Register2 (SSPCON2) • SSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) - Not directly accessible • SSP Address Register (SSPADD)  1998-2013 Microchip Technology Inc. DS30292D-page 73

PIC16F87X 9.2.1 SLAVE MODE For a 10-bit address, the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs In Slave mode, the SCL and SDA pins must be config- of the address. The sequence of events for a 10-bit ured as inputs. The MSSP module will override the address is as follows, with steps 7-9 for slave-transmitter: input state with the output data, when required (slave- transmitter). 1. Receive first (high) byte of Address (bits SSPIF, BF and UA (SSPSTAT<1>) are set). When an address is matched, or the data transfer after 2. Update the SSPADD register with the second an address match is received, the hardware automati- (low) byte of Address (clears bit UA and cally will generate the Acknowledge (ACK) pulse, and releases the SCL line). then load the SSPBUF register with the received value currently in the SSPSR register. 3. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. There are certain conditions that will cause the MSSP 4. Receive second (low) byte of Address (bits module not to give this ACK pulse. These are if either SSPIF, BF and UA are set). (or both): 5. Update the SSPADD register with the first (high) a) The buffer full bit BF (SSPSTAT<0>) was set byte of Address. This will clear bit UA and before the transfer was received. release the SCL line. b) The overflow bit SSPOV (SSPCON<6>) was set 6. Read the SSPBUF register (clears bit BF) and before the transfer was received. clear flag bit SSPIF. If the BF bit is set, the SSPSR register value is not 7. Receive Repeated Start condition. loaded into the SSPBUF, but bit SSPIF and SSPOV are 8. Receive first (high) byte of Address (bits SSPIF set. Table9-2 shows what happens when a data trans- and BF are set). fer byte is received, given the status of bits BF and 9. Read the SSPBUF register (clears bit BF) and SSPOV. The shaded cells show the condition where clear flag bit SSPIF. user software did not properly clear the overflow condi- tion. Flag bit BF is cleared by reading the SSPBUF reg- Note: Following the Repeated START condition ister, while bit SSPOV is cleared through software. (step 7) in 10-bit mode, the user only needs to match the first 7-bit address. The The SCL clock input must have a minimum high and user does not update the SSPADD for the low time for proper operation. The high and low times of the I2C specification, as well as the requirement of second half of the address. the MSSP module, is shown in timing parameter #100 9.2.1.2 Slave Reception and parameter #101 of the electrical specifications. When the R/W bit of the address byte is clear and an 9.2.1.1 Addressing address match occurs, the R/W bit of the SSPSTAT Once the MSSP module has been enabled, it waits for register is cleared. The received address is loaded into a START condition to occur. Following the START con- the SSPBUF register. dition, the 8-bits are shifted into the SSPSR register. All When the address byte overflow condition exists, then incoming bits are sampled with the rising edge of the no Acknowledge (ACK) pulse is given. An overflow clock (SCL) line. The value of register SSPSR<7:1> is condition is defined as either bit BF (SSPSTAT<0>) is compared to the value of the SSPADD register. The set, or bit SSPOV (SSPCON<6>) is set. This is an error address is compared on the falling edge of the eighth condition due to user firmware. clock (SCL) pulse. If the addresses match, and the BF An SSP interrupt is generated for each data transfer and SSPOV bits are clear, the following events occur: byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- a) The SSPSR register value is loaded into the ware. The SSPSTAT register is used to determine the SSPBUF register on the falling edge of the 8th status of the received byte. SCL pulse. Note: The SSPBUF will be loaded if the SSPOV b) The buffer full bit, BF, is set on the falling edge bit is set and the BF flag is cleared. If a of the 8th SCL pulse. read of the SSPBUF was performed, but c) An ACK pulse is generated. the user did not clear the state of the d) SSP interrupt flag bit, SSPIF (PIR1<3>), is set SSPOV bit before the next receive (interrupt is generated if enabled) on the falling occurred, the ACK is not sent and the edge of the 9th SCL pulse. SSPBUF is updated. In 10-bit address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. DS30292D-page 74  1998-2013 Microchip Technology Inc.

PIC16F87X TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Set bit SSPIF Generate ACK Transfer is Received SSPSR SSPBUF (SSP Interrupt occurs Pulse BF SSPOV if enabled) 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 Yes No Yes Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition. 9.2.1.3 Slave Transmission An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in software When the R/W bit of the incoming address byte is set and the SSPSTAT register is used to determine the sta- and an address match occurs, the R/W bit of the tus of the byte transfer. The SSPIF flag bit is set on the SSPSTAT register is set. The received address is falling edge of the ninth clock pulse. loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and the SCL pin is held low. As a slave-transmitter, the ACK pulse from the master The transmit data must be loaded into the SSPBUF receiver is latched on the rising edge of the ninth SCL register, which also loads the SSPSR register. Then, input pulse. If the SDA line is high (not ACK), then the the SCL pin should be enabled by setting bit CKP data transfer is complete. When the not ACK is latched (SSPCON<4>). The master must monitor the SCL pin by the slave, the slave logic is reset and the slave then prior to asserting another clock pulse. The slave monitors for another occurrence of the START bit. If the devices may be holding off the master by stretching the SDA line was low (ACK), the transmit data must be clock. The eight data bits are shifted out on the falling loaded into the SSPBUF register, which also loads the edge of the SCL input. This ensures that the SDA sig- SSPSR register. Then the SCL pin should be enabled nal is valid during the SCL high time (Figure9-7). by setting the CKP bit. FIGURE 9-6: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) R/W=0 Not Receiving Address ACK Receiving Data ACK Receiving Data ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF Bus Master Terminates Transfer BF (SSPSTAT<0>) Cleared in software SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.  1998-2013 Microchip Technology Inc. DS30292D-page 75

PIC16F87X FIGURE 9-7: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) R/W = 1 R/W = 0 Receiving Address ACK Transmitting Data Not ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Data in SCL held low sampled while CPU responds to SSPIF SSPIF BF (SSPSTAT<0>) Cleared in software From SSP Interrupt SSPBUF is written in software Service Routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written to, before the CKP bit can be set) 9.2.2 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), The addressing procedure for the I2C bus is such that the SSPIF flag is set. the first byte after the START condition usually deter- When the interrupt is serviced, the source for the inter- mines which device will be the slave addressed by the rupt can be checked by reading the contents of the master. The exception is the general call address, which SSPBUF to determine if the address was device spe- can address all devices. When this address is used, all cific, or a general call address. devices should, in theory, respond with an acknowledge. In 10-bit mode, the SSPADD is required to be updated The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It for the second half of the address to match, and the UA bit is set (SSPSTAT<1>). If the general call address is consists of all 0’s with R/W = 0. sampled when GCEN is set, while the slave is config- The general call address is recognized when the Gen- ured in 10-bit address mode, then the second half of eral Call Enable bit (GCEN) is enabled (SSPCON2<7> the address is not necessary, the UA bit will not be set, is set). Following a START bit detect, 8 bits are shifted and the slave will begin receiving data after the into SSPSR and the address is compared against Acknowledge (Figure9-8). SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 9-8: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE) Address is compared to General Call Address after ACK, set interrupt flag R/W = 0 Receiving data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV '0' (SSPCON<6>) GCEN (SSPCON2<7>) '1' DS30292D-page 76  1998-2013 Microchip Technology Inc.

PIC16F87X 9.2.3 SLEEP OPERATION 9.2.4 EFFECTS OF A RESET While in SLEEP mode, the I2C module can receive A RESET disables the SSP module and terminates the addresses or data. When an address match or com- current transfer. plete byte transfer occurs, wake the processor from SLEEP (if the SSP interrupt is enabled). TABLE 9-3: REGISTERS ASSOCIATED WITH I2C OPERATION Value on: Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCLR, POR, BOR WDT 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Dh PIR2 — (2) — EEIF BCLIF — — CCP2IF -r-0 0--0 -r-0 0--0 8Dh PIE2 — (2) — EEIE BCLIE — — CCP2IE -r-0 0--0 -r-0 0--0 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 93h SSPADD I2C Slave Address/Master Baud Rate Register 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in I2C mode. Note 1: These bits are reserved on PIC16F873/876 devices; always maintain these bits clear. 2: These bits are reserved on these devices; always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS30292D-page 77

PIC16F87X 9.2.5 MASTER MODE The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (an SSP interrupt will occur if Master mode of operation is supported by interrupt enabled): generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are • START condition cleared from a RESET, or when the MSSP module is • STOP condition disabled. Control of the I2C bus may be taken when the • Data transfer byte transmitted/received P bit is set, or the bus is idle, with both the S and P bits • Acknowledge transmit clear. • Repeated START In Master mode, the SCL and SDA lines are manipu- lated by the MSSP hardware. 2 FIGURE 9-9: SSP BLOCK DIAGRAM (I C MASTER MODE) Internal SSPM3:SSPM0, Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA in Clock ct e SSPSR ete) Dc MSb LSb L ur e Oo SCL Receive Enabl STAARcTGk enbnoitew, rSlaeTtdeOgPe bit, Clock Cntl ck Arbitrate/WC(hold off clock s o Cl START bit Detect, STOP bit Detect SCL in Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT) Bus Collision Clock Arbitration Set SSPIF, BCLIF State Counter for Reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV 9.2.6 MULTI-MASTER MODE In Multi-Master operation, the SDA line must be moni- tored for arbitration to see if the signal level is the In Multi-Master mode, the interrupt generation on the expected output level. This check is performed in hard- detection of the START and STOP conditions allows ware, with the result placed in the BCLIF bit. the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET or The states where arbitration can be lost are: when the MSSP module is disabled. Control of the I2C • Address Transfer bus may be taken when bit P (SSPSTAT<4>) is set, or • Data Transfer the bus is idle with both the S and P bits clear. When • A START Condition the bus is busy, enabling the SSP Interrupt will gener- • A Repeated START Condition ate the interrupt when the STOP condition occurs. • An Acknowledge Condition DS30292D-page 78  1998-2013 Microchip Technology Inc.

PIC16F87X 9.2.7 I2C MASTER MODE SUPPORT SSPBUF. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the Master mode is enabled by setting and clearing the internal clock will automatically stop counting and the appropriate SSPM bits in SSPCON and by setting the SCL pin will remain in its last state. SSPEN bit. Once Master mode is enabled, the user has six options: A typical transmit sequence would go as follows: • Assert a START condition on SDA and SCL. a) User generates a START condition by setting the START enable bit (SEN) in SSPCON2. • Assert a Repeated START condition on SDA and SCL. b) SSPIF is set. The module will wait the required start time before any other operation takes place. • Write to the SSPBUF register initiating transmis- sion of data/address. c) User loads SSPBUF with address to transmit. • Generate a STOP condition on SDA and SCL. d) Address is shifted out the SDA pin until all 8 bits • Configure the I2C port to receive data. are transmitted. e) MSSP module shifts in the ACK bit from the • Generate an Acknowledge condition at the end of slave device and writes its value into the a received byte of data. SSPCON2 register (SSPCON2<6>). Note: The MSSP Module, when configured in I2C f) MSSP module generates an interrupt at the end Master mode, does not allow queueing of of the ninth clock cycle by setting SSPIF. events. For instance, the user is not g) User loads SSPBUF with eight bits of data. allowed to initiate a START condition and immediately write the SSPBUF register to h) DATA is shifted out the SDA pin until all 8 bits are initiate transmission before the START transmitted. condition is complete. In this case, the i) MSSP module shifts in the ACK bit from the SSPBUF will not be written to and the slave device, and writes its value into the WCOL bit will be set, indicating that a write SSPCON2 register (SSPCON2<6>). to the SSPBUF did not occur. j) MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 9.2.7.1 I2C Master Mode Operation k) User generates a STOP condition by setting the The master device generates all of the serial clock STOP enable bit, PEN, in SSPCON2. pulses and the START and STOP conditions. A trans- l) Interrupt is generated once the STOP condition fer is ended with a STOP condition or with a Repeated is complete. START condition. Since the Repeated START condi- tion is also the beginning of the next serial transfer, the 9.2.8 BAUD RATE GENERATOR I2C bus will not be released. In I2C Master mode, the reload value for the BRG is In Master Transmitter mode, serial data is output through located in the lower 7 bits of the SSPADD register SDA, while SCL outputs the serial clock. The first byte (Figure9-10). When the BRG is loaded with this value, transmitted contains the slave address of the receiving the BRG counts down to 0 and stops until another reload device (7 bits) and the Read/Write (R/W) bit. In this case, has taken place. The BRG count is decremented twice the R/W bit will be logic '0'. Serial data is transmitted 8 bits per instruction cycle (TCY), on the Q2 and Q4 clock. at a time. After each byte is transmitted, an Acknowledge In I2C Master mode, the BRG is reloaded automatically. If bit is received. START and STOP conditions are output clock arbitration is taking place, the BRG will be reloaded to indicate the beginning and the end of a serial transfer. when the SCL pin is sampled high (Figure9-11). In Master Receive mode, the first byte transmitted con- tains the slave address of the transmitting device Note: Baud Rate = FOSC / (4 * (SSPADD + 1) ) (7bits) and the R/W bit. In this case, the R/W bit will be logic '1'. Thus, the first byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. Serial FIGURE 9-10: BAUD RATE GENERATOR data is received via SDA, while SCL outputs the serial BLOCK DIAGRAM clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. SSPM3:SSPM0 SSPADD<6:0> START and STOP conditions indicate the beginning and end of transmission. The baud rate generator used for SPI mode operation SSPM3:SSPM0 Reload Reload is now used to set the SCL clock frequency for either SCL Control 100 kHz, 400 kHz, or 1 MHz I2C operation. The baud rate generator reload value is contained in the lower 7 FOSC/4 bits of the SSPADD register. The baud rate generator CLKOUT BRG Down Counter will automatically begin counting on a write to the  1998-2013 Microchip Technology Inc. DS30292D-page 79

PIC16F87X FIGURE 9-11: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL de-asserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements (on Q2 and Q4 cycles) BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place, and BRG starts its count BRG Reload 9.2.9 I2C MASTER MODE START CONDITION TIMING Note: If, at the beginning of START condition, the SDA and SCL pins are already sampled To initiate a START condition, the user sets the START low, or if during the START condition the condition enable bit, SEN (SSPCON2<0>). If the SDA SCL line is sampled low before the SDA and SCL pins are sampled high, the baud rate genera- line is driven low, a bus collision occurs, tor is reloaded with the contents of SSPADD<6:0> and the Bus Collision Interrupt Flag (BCLIF) is starts its count. If SCL and SDA are both sampled high set, the START condition is aborted, and when the baud rate generator times out (TBRG), the the I2C module is reset into its IDLE state. SDA pin is driven low. The action of the SDA being driven low while SCL is high is the START condition, 9.2.9.1 WCOL Status Flag and causes the S bit (SSPSTAT<3>) to be set. Follow- If the user writes the SSPBUF when a START ing this, the baud rate generator is reloaded with the sequence is in progress, then WCOL is set and the contents of SSPADD<6:0> and resumes its count. contents of the buffer are unchanged (the write doesn’t When the baud rate generator times out (TBRG), the occur). SEN bit (SSPCON2<0>) will be automatically cleared by hardware. The baud rate generator is suspended, Note: Because queueing of events is not leaving the SDA line held low, and the START condition allowed, writing to the lower 5 bits of is complete. SSPCON2 is disabled until the START condition is complete. FIGURE 9-12: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of START bit, SCL = 1 Hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st Bit 2nd Bit SDA TBRG SCL TBRG S DS30292D-page 80  1998-2013 Microchip Technology Inc.

PIC16F87X 9.2.10 I2C MASTER MODE REPEATED Immediately following the SSPIF bit getting set, the START CONDITION TIMING user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. A Repeated START condition occurs when the RSEN After the first eight bits are transmitted and an ACK is bit (SSPCON2<1>) is programmed high and the I2C received, the user may then transmit an additional eight module is in the IDLE state. When the RSEN bit is set, bits of address (10-bit mode), or eight bits of data (7-bit the SCL pin is asserted low. When the SCL pin is sam- mode). pled low, the baud rate generator is loaded with the contents of SSPADD<6:0> and begins counting. The 9.2.10.1 WCOL Status Flag SDA pin is released (brought high) for one baud rate If the user writes the SSPBUF when a Repeated generator count (TBRG). When the baud rate generator START sequence is in progress, then WCOL is set and times out, if SDA is sampled high, the SCL pin will be the contents of the buffer are unchanged (the write de-asserted (brought high). When SCL is sampled high doesn’t occur). the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL Note: Because queueing of events is not must be sampled high for one TBRG. This action is then allowed, writing of the lower 5 bits of followed by assertion of the SDA pin (SDA is low) for SSPCON2 is disabled until the Repeated one TBRG, while SCL is high. Following this, the RSEN START condition is complete. bit in the SSPCON2 register will be automatically cleared and the baud rate generator will not be reloaded, leaving the SDA pin held low. As soon as a START condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the baud rate generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated START condition occurs if: • SDA is sampled low when SCL goes from low to high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". FIGURE 9-13: REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 occurs here SDA = 1, At completion of START bit, SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change) and sets SSPIF TBRG TBRG TBRG 1st bit SDA Falling edge of ninth clock Write to SSPBUF occurs here End of Xmit TBRG SCL TBRG Sr = Repeated START  1998-2013 Microchip Technology Inc. DS30292D-page 81

PIC16F87X 9.2.11 I2C MASTER MODE 9.2.11.1 BF Status Flag TRANSMISSION In Transmit mode, the BF bit (SSPSTAT<0>) is set Transmission of a data byte, a 7-bit address, or either when the CPU writes to SSPBUF and is cleared when half of a 10-bit address, is accomplished by simply writ- all 8 bits are shifted out. ing a value to SSPBUF register. This action will set the 9.2.11.2 WCOL Status Flag Buffer Full flag (BF) and allow the baud rate generator to begin counting and start the next transmission. Each If the user writes the SSPBUF when a transmit is bit of address/data will be shifted out onto the SDA pin already in progress (i.e., SSPSR is still shifting out a after the falling edge of SCL is asserted (see data hold data byte), then WCOL is set and the contents of the time spec). SCL is held low for one baud rate generator buffer are unchanged (the write doesn’t occur). rollover count (TBRG). Data should be valid before SCL WCOL must be cleared in software. is released high (see data setup time spec). When the SCL pin is released high, it is held that way for TBRG. 9.2.11.3 ACKSTAT Status Flag The data on the SDA pin must remain stable for that In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is duration and some hold time after the next falling edge cleared when the slave has sent an Acknowledge of SCL. After the eighth bit is shifted out (the falling (ACK= 0), and is set when the slave does not Acknowl- edge of the eighth clock), the BF flag is cleared and the edge (ACK = 1). A slave sends an Acknowledge when master releases SDA allowing the slave device being it has recognized its address (including a general call), addressed to respond with an ACK bit during the ninth or when the slave has properly received its data. bit time, if an address match occurs or if data was received properly. The status of ACK is read into the ACKDT on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit (ACKSTAT) is cleared. If not, the bit is set. After the ninth clock, the SSPIF is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure9-14). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL, until all seven address bits and the R/W bit are completed. On the fall- ing edge of the eighth clock, the master will de-assert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmis- sion of the address, the SSPIF is set, the BF flag is cleared, and the baud rate generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. DS30292D-page 82  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 9-14: I2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A <6> D0 8 e 2 n AT bit SSPCON or Second Half D3D2D1 567 are service routiupt en in software slave clear ACKST Transmitting Data of 10-bit address D6D5D4 234 Cleared in softwFrom SSP interr SSPBUF is writt From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to 0 ACK 9 re are. = w R/W d R/W 8 y hard n b A1 s a 7 ed PCON2<0> SEN = 1ondition begins SEN = 0 Transmit Address to Slave A7A6A5A4A3A2 SSPBUF written with 7-bit addresstart transmit 123456 Cleared in software SSPBUF written After START condition SEN, clear Sc ST Write STAR S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W  1998-2013 Microchip Technology Inc. DS30292D-page 83

PIC16F87X 9.2.12 I2C MASTER MODE RECEPTION 9.2.12.1 BF Status Flag Master mode reception is enabled by programming the In receive operation, BF is set when an address or data Receive Enable bit, RCEN (SSPCON2<3>). byte is loaded into SSPBUF from SSPSR. It is cleared when SSPBUF is read. Note: The SSP module must be in an IDLE state before the RCEN bit is set, or the RCEN bit 9.2.12.2 SSPOV Status Flag will be disregarded. In receive operation, SSPOV is set when 8 bits are The baud rate generator begins counting, and on each received into the SSPSR, and the BF flag is already set rollover, the state of the SCL pin changes (high to low/ from a previous reception. low to high), and data is shifted into the SSPSR. After 9.2.12.3 WCOL Status Flag the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the If the user writes the SSPBUF when a receive is SSPSR are loaded into the SSPBUF, the BF flag is set, already in progress (i.e., SSPSR is still shifting in a data the SSPIF is set, and the baud rate generator is sus- byte), then WCOL is set and the contents of the buffer pended from counting, holding SCL low. The SSP is are unchanged (the write doesn’t occur). now in IDLE state, awaiting the next command. When the buffer is read by the CPU, the BF flag is automati- cally cleared. The user can then send an Acknowledge bit at the end of reception, by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2<4>). DS30292D-page 84  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 9-15: I2C MASTER MODE TIMING (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN to start Acknowledge sequenceACK from Masterer configured as a receiverSDA = ACKDT = 1 SDA = ACKDT = 0 ogramming SSPCON2<3>, (RCEN = 1)PEN bit = 1RCEN = 1 startRCEN clearedRCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK Bus MasterACK is not sentterminatestransfer967898756512343124PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Mastby pr Slave ACK CK from R/W = 1 98 A 1 A 7 Write to SSPCON2<0>(SEN = 1)Begin START Condition SEN = 0Write to SSPBUF occurs hereStart XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 361245SCLS SSPIF Cleared in softwareSDA = 0, SCL = 1while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN  1998-2013 Microchip Technology Inc. DS30292D-page 85

PIC16F87X 9.2.13 ACKNOWLEDGE SEQUENCE rate generator counts for TBRG. The SCL pin is then TIMING pulled low. Following this, the ACKEN bit is automati- cally cleared, the baud rate generator is turned off, An Acknowledge sequence is enabled by setting the and the SSP module then goes into IDLE mode Acknowledge Sequence Enable bit, ACKEN (Figure9-16). (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit 9.2.13.1 WCOL Status Flag is presented on the SDA pin. If the user wishes to gen- If the user writes the SSPBUF when an Acknowledge erate an Acknowledge, the ACKDT bit should be sequence is in progress, the WCOL is set and the con- cleared. If not, the user should set the ACKDT bit tents of the buffer are unchanged (the write doesn’t before starting an Acknowledge sequence. The baud occur). rate generator then counts for one rollover period (TBRG), and the SCL pin is de-asserted high. When the SCL pin is sampled high (clock arbitration), the baud FIGURE 9-16: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, Write to SSPCON2 ACKEN automatically cleared ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Set SSPIF at the end Cleared in Cleared in of receive software software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one baud rate generator period. DS30292D-page 86  1998-2013 Microchip Technology Inc.

PIC16F87X 9.2.14 STOP CONDITION TIMING while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is A STOP bit is asserted on the SDA pin at the end of a set (Figure9-17). receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ Whenever the firmware decides to take control of the transmit, the SCL line is held low after the falling edge bus, it will first determine if the bus is busy by checking of the ninth clock. When the PEN bit is set, the master the S and P bits in the SSPSTAT register. If the bus is will assert the SDA line low. When the SDA line is sam- busy, then the CPU can be interrupted (notified) when pled low, the baud rate generator is reloaded and a STOP bit is detected (i.e., bus is free). counts down to 0. When the baud rate generator times 9.2.14.1 WCOL Status Flag out, the SCL pin will be brought high, and one TBRG (baud rate generator rollover count) later, the SDA pin If the user writes the SSPBUF when a STOP sequence will be de-asserted. When the SDA pin is sampled high is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 9-17: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG Write to SSPCON2 after SDA sampled high. P bit (SSPSTAT<4>) is set. Set PEN Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup STOP condition Note: TBRG = one baud rate generator period.  1998-2013 Microchip Technology Inc. DS30292D-page 87

PIC16F87X 9.2.15 CLOCK ARBITRATION 9.2.16 SLEEP OPERATION Clock arbitration occurs when the master, during any While in SLEEP mode, the I2C module can receive receive, transmit, or Repeated START/STOP condi- addresses or data, and when an address match or tion, de-asserts the SCL pin (SCL allowed to float high). complete byte transfer occurs, wake the processor When the SCL pin is allowed to float high, the baud rate from SLEEP (if the SSP interrupt is enabled). generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is 9.2.17 EFFECTS OF A RESET sampled high, the baud rate generator is reloaded with A RESET disables the SSP module and terminates the the contents of SSPADD<6:0> and begins counting. current transfer. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure9-18). FIGURE 9-18: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE BRG overflow, Release SCL, If SCL = 1, Load BRG with SSPADD<6:0>, and start count BRG overflow occurs, to measure high time interval Release SCL, Slave device holds SCL low SCL = 1, BRG starts counting clock high interval SCL SCL line sampled once every machine cycle (TOSC  4). Hold off BRG until SCL is sampled high. SDA TBRG TBRG TBRG DS30292D-page 88  1998-2013 Microchip Technology Inc.

PIC16F87X 9.2.18 MULTI -MASTER If a START, Repeated START, STOP, or Acknowledge COMMUNICATION, condition was in progress when the bus collision BUS COLLISION, AND occurred, the condition is aborted, the SDA and SCL BUS ARBITRATION lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user ser- Multi-Master mode support is achieved by bus arbitra- vices the bus collision Interrupt Service Routine, and if tion. When the master outputs address/data bits onto the I2C bus is free, the user can resume communication the SDA pin, arbitration takes place when the master by asserting a START condition. outputs a '1' on SDA, by letting SDA float high and The master will continue to monitor the SDA and SCL another master asserts a '0'. When the SCL pin floats pins and if a STOP condition occurs, the SSPIF bit will high, data should be stable. If the expected data on be set. SDA is a '1' and the data sampled on the SDA pin = '0', a bus collision has taken place. The master will set the A write to the SSPBUF will start the transmission of Bus Collision Interrupt Flag, BCLIF and reset the I2C data at the first data bit, regardless of where the trans- port to its IDLE state (Figure9-19). mitter left off when the bus collision occurred. If a transmit was in progress when the bus collision In Multi-Master mode, the interrupt generation on the occurred, the transmission is halted, the BF flag is detection of START and STOP conditions allows the cleared, the SDA and SCL lines are de-asserted, and determination of when the bus is free. Control of the I2C the SSPBUF can be written to. When the user services bus can be taken when the P bit is set in the SSPSTAT the bus collision Interrupt Service Routine, and if the register, or the bus is idle and the S and P bits are I2C bus is free, the user can resume communication by cleared. asserting a START condition. FIGURE 9-19: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE SDA line pulled low Sample SDA. While SCL is high, Data changes by another source data doesn’t match what is driven while SCL = 0 by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt BCLIF  1998-2013 Microchip Technology Inc. DS30292D-page 89

PIC16F87X 9.2.18.1 Bus Collision During a START If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure9-22). If, however, a '1' is sampled on the SDA During a START condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The baud rate generator is then reloaded and the START condition (Figure9-20). counts down to 0. During this time, if the SCL pins are b) SCL is sampled low before SDA is asserted low sampled as '0', a bus collision does not occur. At the (Figure9-21). end of the BRG count, the SCL pin is asserted low. During a START condition, both the SDA and the SCL pins are monitored. If either the SDA pin or the SCL pin Note: The reason that bus collision is not a factor is already low, then these events all occur: during a START condition is that no two • the START condition is aborted, bus masters can assert a START condition • and the BCLIF flag is set, at the exact same time. Therefore, one • and the SSP module is reset to its IDLE state master will always assert SDA before the (Figure9-20). other. This condition does not cause a bus collision, because the two masters must be The START condition begins with the SDA and SCL allowed to arbitrate the first address follow- pins de-asserted. When the SDA pin is sampled high, ing the START condition. If the address is the baud rate generator is loaded from SSPADD<6:0> the same, arbitration must be allowed to and counts down to 0. If the SCL pin is sampled low continue into the data portion, Repeated while SDA is high, a bus collision occurs, because it is START, or STOP conditions. assumed that another master is attempting to drive a data '1' during the START condition. FIGURE 9-20: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable START SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP module reset into IDLE state. SEN SDA sampled low before START condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software DS30292D-page 90  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 9-21: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable START SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, Bus collision occurs, Set BCLIF SEN SCL = 0 before BRG time-out, Bus collision occurs, Set BCLIF BCLIF Interrupts cleared in software S '0' '0' SSPIF '0' '0' FIGURE 9-22: BRG RESET DUE TO SDA COLLISION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL s SCL pulled low after BRG Time-out SEN Set SEN, enable START sequence if SDA = 1, SCL = 1 BCLIF '0' S SSPIF SDA = 0, SCL = 1 Interrupts cleared Set SSPIF in software  1998-2013 Microchip Technology Inc. DS30292D-page 91

PIC16F87X 9.2.18.2 Bus Collision During a Repeated SDA is sampled high, the BRG is reloaded and begins START Condition counting. If SDA goes from high to low before the BRG times out, no bus collision occurs, because no two During a Repeated START condition, a bus collision masters can assert SDA at exactly the same time. occurs if: If, however, SCL goes from high to low before the BRG a) A low level is sampled on SDA when SCL goes times out and SDA has not already been asserted, a from low level to high level. bus collision occurs. In this case, another master is b) SCL goes low before SDA is asserted low, indi- attempting to transmit a data’1’ during the Repeated cating that another master is attempting to trans- START condition. mit a data ’1’. If at the end of the BRG time-out, both SCL and SDA When the user de-asserts SDA and the pin is allowed are still high, the SDA pin is driven low, the BRG is to float high, the BRG is loaded with SSPADD<6:0> reloaded and begins counting. At the end of the count, and counts down to 0. The SCL pin is then de-asserted, regardless of the status of the SCL pin, the SCL pin is and when sampled high, the SDA pin is sampled. If driven low and the Repeated START condition is SDA is low, a bus collision has occurred (i.e., another complete (Figure9-23). master is attempting to transmit a data’0’). If, however, FIGURE 9-23: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S '0' '0' SSPIF '0' '0' FIGURE 9-24: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF Set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S '0' '0' '0' '0' SSPIF DS30292D-page 92  1998-2013 Microchip Technology Inc.

PIC16F87X 9.2.18.3 Bus Collision During a STOP The STOP condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a STOP condition if: the baud rate generator is loaded with SSPADD<6:0> a) After the SDA pin has been de-asserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is de-asserted, SCL is sam- drive a data '0'. If the SCL pin is sampled low before pled low before SDA goes high. SDA is allowed to float high, a bus collision occurs. This is a case of another master attempting to drive a data '0' (Figure9-25). FIGURE 9-25: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, Set BCLIF SDA SDA asserted low SCL PEN BCLIF P '0' '0' SSPIF '0' '0' FIGURE 9-26: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA Set BCLIF SCL PEN BCLIF P '0' SSPIF '0'  1998-2013 Microchip Technology Inc. DS30292D-page 93

PIC16F87X 9.3 Connection Considerations for example, with a supply voltage of VDD = 5V±10% and I2C Bus VOL max = 0.4V at 3mA, Rp min = (5.5-0.4)/0.003 = 1.7k VDD as a function of Rp is shown in Figure9-27. The For standard-mode I2C bus devices, the values of desired noise margin of 0.1VDD for the low level limits resistors Rp and Rs in Figure9-27 depend on the fol- the maximum value of Rs. Series resistors are optional lowing parameters: and used to improve ESD susceptibility. • Supply voltage The bus capacitance is the total capacitance of wire, • Bus capacitance connections, and pins. This capacitance limits the max- • Number of connected devices imum value of Rp due to the specified rise time (Figure9-27). (input current + leakage current) The supply voltage limits the minimum value of resistor The SMP bit is the slew rate control enabled bit. This bit R ,due to the specified minimum sink current of 3mA at is in the SSPSTAT register, and controls the slew rate VOpL max = 0.4V, for the specified output stages. For of the I/O pins when in I2C mode (master or slave). FIGURE 9-27: SAMPLE DEVICE CONFIGURATION FOR I2C BUS VDD + 10% DEVICE R R p p R R s s SDA SCL C =10 - 400 pF b Note: I2C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also connected. DS30292D-page 94  1998-2013 Microchip Technology Inc.

PIC16F87X 10.0 ADDRESSABLE UNIVERSAL The USART can be configured in the following modes: SYNCHRONOUS • Asynchronous (full duplex) ASYNCHRONOUS RECEIVER • Synchronous - Master (half duplex) TRANSMITTER (USART) • Synchronous - Slave (half duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to The Universal Synchronous Asynchronous Receiver be set in order to configure pins RC6/TX/CK and Transmitter (USART) module is one of the two serial RC7/RX/DT as the Universal Synchronous Asynchro- I/O modules. (USART is also known as a Serial Com- nous Receiver Transmitter. munications Interface or SCI.) The USART can be con- figured as a full duplex asynchronous system that can The USART module also has a multi-processor com- communicate with peripheral devices such as CRT ter- munication capability using 9-bit address detection. minals and personal computers, or it can be configured as a half duplex synchronous system that can commu- nicate with peripheral devices such as A/D or D/A inte- grated circuits, serial EEPROMs etc. REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as '0' bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data, can be parity bit Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30292D-page 95

PIC16F87X REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode - master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - slave: Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 =Enables address detection, enables interrupt and load of the receive buffer when RSR<8> is set 0 =Disables address detection, all bytes are received, and ninth bit can be used as parity bit bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30292D-page 96  1998-2013 Microchip Technology Inc.

PIC16F87X 10.1 USART Baud Rate Generator It may be advantageous to use the high baud rate (BRG) (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the The BRG supports both the Asynchronous and Syn- baud rate error in some cases. chronous modes of the USART. It is a dedicated 8-bit Writing a new value to the SPBRG register causes the baud rate generator. The SPBRG register controls the BRG timer to be reset (or cleared). This ensures the period of a free running 8-bit timer. In Asynchronous BRG does not wait for a timer overflow before output- mode, bit BRGH (TXSTA<2>) also controls the baud ting the new baud rate. rate. In Synchronous mode, bit BRGH is ignored. Table10-1 shows the formula for computation of the 10.1.1 SAMPLING baud rate for different USART modes which only apply in Master mode (internal clock). The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a Given the desired baud rate and FOSC, the nearest low level is present at the RX pin. integer value for the SPBRG register can be calculated using the formula in Table10-1. From this, the error in baud rate can be determined. TABLE 10-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate = FOSC/(16(X+1)) 1 (Synchronous) Baud Rate = FOSC/(4(X+1)) N/A X = value in SPBRG (0 to 255) TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.  1998-2013 Microchip Technology Inc. DS30292D-page 97

PIC16F87X TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz BAUD RATE SPBRG SPBRG SPBRG % % % (K) value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) 0.3 - - - - - - - - - 1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129 2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64 9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15 19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7 28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4 33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4 57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2 HIGH 1.221 - 255 0.977 - 255 0.610 - 255 LOW 312.500 - 0 250.000 - 0 156.250 - 0 FOSC = 4 MHz FOSC = 3.6864 MHz BAUD RATE SPBRG SPBRG % % (K) value value ERROR ERROR KBAUD (decimal) KBAUD (decimal) 0.3 0.300 0 207 0.3 0 191 1.2 1.202 0.17 51 1.2 0 47 2.4 2.404 0.17 25 2.4 0 23 9.6 8.929 6.99 6 9.6 0 5 19.2 20.833 8.51 2 19.2 0 2 28.8 31.250 8.51 1 28.8 0 1 33.6 - - - - - - 57.6 62.500 8.51 0 57.6 0 0 HIGH 0.244 - 255 0.225 - 255 LOW 62.500 - 0 57.6 - 0 TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz BAUD RATE SPBRG SPBRG SPBRG % % % (K) value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) 0.3 - - - - - - - - - 1.2 - - - - - - - - - 2.4 - - - - - - 2.441 1.71 255 9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64 19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31 28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21 33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18 57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10 HIGH 4.883 - 255 3.906 - 255 2.441 - 255 LOW 1250.000 - 0 1000.000 0 625.000 - 0 FOSC = 4 MHz FOSC = 3.6864 MHz BAUD RATE SPBRG SPBRG % % (K) value value ERROR ERROR KBAUD (decimal) KBAUD (decimal) 0.3 - - - - - - 1.2 1.202 0.17 207 1.2 0 191 2.4 2.404 0.17 103 2.4 0 95 9.6 9.615 0.16 25 9.6 0 23 19.2 19.231 0.16 12 19.2 0 11 28.8 27.798 3.55 8 28.8 0 7 33.6 35.714 6.29 6 32.9 2.04 6 57.6 62.500 8.51 3 57.6 0 3 HIGH 0.977 - 255 0.9 - 255 LOW 250.000 - 0 230.4 - 0 DS30292D-page 98  1998-2013 Microchip Technology Inc.

PIC16F87X 10.2 USART Asynchronous Mode enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the In this mode, the USART uses standard non-return-to- state of enable bit TXIE and cannot be cleared in soft- zero (NRZ) format (one START bit, eight or nine data ware. It will reset only when new data is loaded into the bits, and one STOP bit). The most common data format TXREG register. While flag bit TXIF indicates the status is 8-bits. An on-chip, dedicated, 8-bit baud rate gener- of the TXREG register, another bit TRMT (TXSTA<1>) ator can be used to derive standard baud rate frequen- shows the status of the TSR register. Status bit TRMT cies from the oscillator. The USART transmits and is a read only bit, which is set when the TSR register is receives the LSb first. The transmitter and receiver are empty. No interrupt logic is tied to this bit, so the user functionally independent, but use the same data format has to poll this bit in order to determine if the TSR reg- and baud rate. The baud rate generator produces a ister is empty. clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by Note 1: The TSR register is not mapped in data the hardware, but can be implemented in software (and memory, so it is not available to the user. stored as the ninth data bit). Asynchronous mode is 2: Flag bit TXIF is set when enable bit TXEN stopped during SLEEP. is set. TXIF is cleared by loading TXREG. Asynchronous mode is selected by clearing bit SYNC Transmission is enabled by setting enable bit TXEN (TXSTA<4>). (TXSTA<5>). The actual transmission will not occur The USART Asynchronous module consists of the fol- until the TXREG register has been loaded with data lowing important elements: and the baud rate generator (BRG) has produced a shift clock (Figure10-2). The transmission can also be • Baud Rate Generator started by first loading the TXREG register and then • Sampling Circuit setting enable bit TXEN. Normally, when transmission • Asynchronous Transmitter is first started, the TSR register is empty. At that point, • Asynchronous Receiver transfer to the TXREG register will result in an immedi- ate transfer to TSR, resulting in an empty TXREG. A 10.2.1 USART ASYNCHRONOUS back-to-back transfer is thus possible (Figure10-3). TRANSMITTER Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the The USART transmitter block diagram is shown in transmitter. As a result, the RC6/TX/CK pin will revert Figure10-1. The heart of the transmitter is the transmit to hi-impedance. (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The In order to select 9-bit transmission, transmit bit TX9 TXREG register is loaded with data in software. The (TXSTA<6>) should be set and the ninth bit should be TSR register is not loaded until the STOP bit has been written to TX9D (TXSTA<0>). The ninth bit must be transmitted from the previous load. As soon as the written before writing the 8-bit data to the TXREG reg- STOP bit is transmitted, the TSR is loaded with new ister. This is because a data write to the TXREG regis- data from the TXREG register (if available). Once the ter can result in an immediate transfer of the data to the TXREG register transfers the data to the TSR register TSR register (if the TSR is empty). In such a case, an (occurs in one TCY), the TXREG register is empty and incorrect ninth data bit may be loaded in the TSR flag bit TXIF (PIR1<4>) is set. This interrupt can be register. FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8)  0 Pin Buffer and Control TSR Register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D  1998-2013 Microchip Technology Inc. DS30292D-page 99

PIC16F87X When setting up an Asynchronous Transmission, 5. Enable the transmission by setting bit TXEN, follow these steps: which will also set bit TXIF. 1. Initialize the SPBRG register for the appropriate 6. If 9-bit transmission is selected, the ninth bit baud rate. If a high speed baud rate is desired, should be loaded in bit TX9D. set bit BRGH (Section10.1). 7. Load data to the TXREG register (starts trans- 2. Enable the asynchronous serial port by clearing mission). bit SYNC and setting bit SPEN. 8. If using interrupts, ensure that GIE and PEIE 3. If interrupts are desired, then set enable bit (bits 7 and 6) of the INTCON register are set. TXIE. 4. If 9-bit transmission is desired, then set transmit bit TX9. FIGURE 10-2: ASYNCHRONOUS MASTER TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK (pin) START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit Word 1 (Transmit Shift Transmit Shift Reg Reg. Empty Flag) FIGURE 10-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) RC6/TX/CK (pin) START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit START Bit Bit 0 TXIF bit Word 1 Word 2 (Interrupt Reg. Flag) T(RTReragMn. TsE mmbiitpt tSyh Fifltag) TWraonrds m1it Shift Reg. WTraonrds m2it Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear. DS30292D-page 100  1998-2013 Microchip Technology Inc.

PIC16F87X 10.2.2 USART ASYNCHRONOUS is possible for two bytes of data to be received and RECEIVER transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of The receiver block diagram is shown in Figure10-4. the STOP bit of the third byte, if the RCREG register is The data is received on the RC7/RX/DT pin and drives still full, the overrun error bit OERR (RCSTA<1>) will be the data recovery block. The data recovery block is set. The word in the RSR will be lost. The RCREG reg- actually a high speed shifter, operating at x16 times the ister can be read twice to retrieve the two bytes in the baud rate; whereas, the main receive serial shifter FIFO. Overrun bit OERR has to be cleared in software. operates at the bit rate or at FOSC. This is done by resetting the receive logic (CREN is Once Asynchronous mode is selected, reception is cleared and then set). If bit OERR is set, transfers from enabled by setting bit CREN (RCSTA<4>). the RSR register to the RCREG register are inhibited, and no further data will be received. It is therefore, The heart of the receiver is the receive (serial) shift reg- essential to clear error bit OERR if it is set. Framing ister (RSR). After sampling the STOP bit, the received error bit FERR (RCSTA<2>) is set if a STOP bit is data in the RSR is transferred to the RCREG register (if detected as clear. Bit FERR and the 9th receive bit are it is empty). If the transfer is complete, flag bit RCIF buffered the same way as the receive data. Reading (PIR1<5>) is set. The actual interrupt can be enabled/ the RCREG will load bits RX9D and FERR with new disabled by setting/clearing enable bit RCIE values, therefore, it is essential for the user to read the (PIE1<5>). Flag bit RCIF is a read only bit, which is RCSTA register before reading the RCREG register in cleared by the hardware. It is cleared when the RCREG order not to lose the old FERR and RX9D information. register has been read and is empty. The RCREG is a double buffered register (i.e., it is a two deep FIFO). It FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN FOSC SPBRG 64 MSb RSR Register LSb or Baud Rate Generator 16 STOP (8) 7  1 0 START RC7/RX/DT Pin Buffer Data and Control Recovery RX9 SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF Data Bus RCIE  1998-2013 Microchip Technology Inc. DS30292D-page 101

PIC16F87X FIGURE 10-5: ASYNCHRONOUS RECEPTION RX (pin) START START START bit bit0 bit1 bit7/8 STOP bit bit0 bit7/8 STOP bit bit7/8 STOP bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. When setting up an Asynchronous Reception, follow 6. Flag bit RCIF will be set when reception is com- these steps: plete and an interrupt will be generated if enable bit RCIE is set. 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, 7. Read the RCSTA register to get the ninth bit (if set bit BRGH (Section10.1). enabled) and determine if any error occurred during reception. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 8. Read the 8-bit received data by reading the RCREG register. 3. If interrupts are desired, then set enable bit RCIE. 9. If any error occurred, clear the error by clearing enable bit CREN. 4. If 9-bit reception is desired, then set bit RX9. 10. If using interrupts, ensure that GIE and PEIE 5. Enable the reception by setting bit CREN. (bits 7 and 6) of the INTCON register are set. TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. DS30292D-page 102  1998-2013 Microchip Technology Inc.

PIC16F87X 10.2.3 SETTING UP 9-BIT MODE WITH • Flag bit RCIF will be set when reception is com- ADDRESS DETECT plete, and an interrupt will be generated if enable bit RCIE was set. When setting up an Asynchronous Reception with • Read the RCSTA register to get the ninth bit and Address Detect Enabled: determine if any error occurred during reception. • Initialize the SPBRG register for the appropriate • Read the 8-bit received data by reading the baud rate. If a high speed baud rate is desired, set RCREG register, to determine if the device is bit BRGH. being addressed. • Enable the asynchronous serial port by clearing • If any error occurred, clear the error by clearing bit SYNC and setting bit SPEN. enable bit CREN. • If interrupts are desired, then set enable bit RCIE. • If the device has been addressed, clear the • Set bit RX9 to enable 9-bit reception. ADDEN bit to allow data bytes and address bytes • Set ADDEN to enable address detect. to be read into the receive buffer, and interrupt the • Enable the reception by setting enable bit CREN. CPU. FIGURE 10-6: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN FOSC SPBRG  64 MSb RSR Register LSb or Baud Rate Generator  16 STOP (8) 7  1 0 START RC7/RX/DT Pin Buffer Data and Control Recovery RX9 8 SPEN RX9 Enable ADDEN Load of Receive RX9 Buffer ADDEN RSR<8> 8 RX9D RCREG Register FIFO 8 Interrupt RCIF Data Bus RCIE  1998-2013 Microchip Technology Inc. DS30292D-page 103

PIC16F87X FIGURE 10-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT RC7/RX/DT (pin) START START bit bit0 bit1 bit8 STOP bit bit0 bit8 STOP bit bit Load RSR Bit8 = 0, Data Byte Bit8 = 1, Address Byte Word 1 RCREG Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN = 1. FIGURE 10-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST RC7/RX/DT (pin) START START bit bit0 bit1 bit8 STOP bit bit0 bit8 STOP bit bit Load RSR Bit8 = 1, Address Byte Bit8 = 0, Data Byte Word 1 RCREG Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN was not updated and still = 0. TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. DS30292D-page 104  1998-2013 Microchip Technology Inc.

PIC16F87X 10.3 USART Synchronous Clearing enable bit TXEN during a transmission will Master Mode cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to hi- In Synchronous Master mode, the data is transmitted in impedance. If either bit CREN or bit SREN is set during a half-duplex manner (i.e., transmission and reception a transmission, the transmission is aborted and the DT do not occur at the same time). When transmitting data, pin reverts to a hi-impedance state (for a reception). the reception is inhibited and vice versa. Synchronous The CK pin will remain an output if bit CSRC is set mode is entered by setting bit SYNC (TXSTA<4>). In (internal clock). The transmitter logic, however, is not addition, enable bit SPEN (RCSTA<7>) is set in order reset, although it is disconnected from the pins. In order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to reset the transmitter, the user has to clear bit TXEN. to CK (clock) and DT (data) lines, respectively. The If bit SREN is set (to interrupt an on-going transmission Master mode indicates that the processor transmits the and receive a single word), then after the single word is master clock on the CK line. The Master mode is received, bit SREN will be cleared and the serial port entered by setting bit CSRC (TXSTA<7>). will revert back to transmitting, since bit TXEN is still set. The DT line will immediately switch from hi- 10.3.1 USART SYNCHRONOUS MASTER impedance Receive mode to transmit and start driving. TRANSMISSION To avoid this, bit TXEN should be cleared. The USART transmitter block diagram is shown in In order to select 9-bit transmission, the TX9 Figure10-6. The heart of the transmitter is the transmit (TXSTA<6>) bit should be set and the ninth bit should (serial) shift register (TSR). The shift register obtains its be written to bit TX9D (TXSTA<0>). The ninth bit must data from the read/write transmit buffer register be written before writing the 8-bit data to the TXREG TXREG. The TXREG register is loaded with data in register. This is because a data write to the TXREG can software. The TSR register is not loaded until the last result in an immediate transfer of the data to the TSR bit has been transmitted from the previous load. As register (if the TSR is empty). If the TSR was empty and soon as the last bit is transmitted, the TSR is loaded the TXREG was written before writing the “new” TX9D, with new data from the TXREG (if available). Once the the “present” value of bit TX9D is loaded. TXREG register transfers the data to the TSR register Steps to follow when setting up a Synchronous Master (occurs in one Tcycle), the TXREG is empty and inter- Transmission: rupt bit TXIF (PIR1<4>) is set. The interrupt can be 1. Initialize the SPBRG register for the appropriate enabled/disabled by setting/clearing enable bit TXIE baud rate (Section10.1). (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in soft- 2. Enable the synchronous master serial port by ware. It will reset only when new data is loaded into the setting bits SYNC, SPEN and CSRC. TXREG register. While flag bit TXIF indicates the status 3. If interrupts are desired, set enable bit TXIE. of the TXREG register, another bit TRMT (TXSTA<1>) 4. If 9-bit transmission is desired, set bit TX9. shows the status of the TSR register. TRMT is a read 5. Enable the transmission by setting bit TXEN. only bit which is set when the TSR is empty. No inter- 6. If 9-bit transmission is selected, the ninth bit rupt logic is tied to this bit, so the user has to poll this should be loaded in bit TX9D. bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not 7. Start transmission by loading data to the TXREG available to the user. register. 8. If using interrupts, ensure that GIE and PEIE Transmission is enabled by setting enable bit TXEN (bits 7 and 6) of the INTCON register are set. (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is sta- ble around the falling edge of the synchronous clock (Figure10-9). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure10-10). This is advantageous when slow baud rates are selected, since the BRG is kept in RESET when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally, when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible.  1998-2013 Microchip Technology Inc. DS30292D-page 105

PIC16F87X TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. FIGURE 10-9: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX/CK pin Write to TXREG reg Write Word1 Write Word2 TXIF bit (Interrupt Flag) TRMT bit '1' '1' TXEN bit Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words. FIGURE 10-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit0 bit1 bit2 bit6 bit7 RC6/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit DS30292D-page 106  1998-2013 Microchip Technology Inc.

PIC16F87X 10.3.2 USART SYNCHRONOUS MASTER receive bit is buffered the same way as the receive RECEPTION data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user Once synchronous mode is selected, reception is to read the RCSTA register before reading RCREG in enabled by setting either enable bit SREN order not to lose the old RX9D information. (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is When setting up a Synchronous Master Reception: sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single 1. Initialize the SPBRG register for the appropriate word is received. If enable bit CREN is set, the recep- baud rate (Section10.1). tion is continuous until CREN is cleared. If both bits are 2. Enable the synchronous master serial port by set, CREN takes precedence. After clocking the last bit, setting bits SYNC, SPEN and CSRC. the received data in the Receive Shift Register (RSR) 3. Ensure bits CREN and SREN are clear. is transferred to the RCREG register (if it is empty). 4. If interrupts are desired, then set enable bit When the transfer is complete, interrupt flag bit RCIF RCIE. (PIR1<5>) is set. The actual interrupt can be enabled/ disabled by setting/clearing enable bit RCIE 5. If 9-bit reception is desired, then set bit RX9. (PIE1<5>). Flag bit RCIF is a read only bit, which is 6. If a single reception is required, set bit SREN. reset by the hardware. In this case, it is reset when the For continuous reception, set bit CREN. RCREG register has been read and is empty. The 7. Interrupt flag bit RCIF will be set when reception RCREG is a double buffered register (i.e., it is a two is complete and an interrupt will be generated if deep FIFO). It is possible for two bytes of data to be enable bit RCIE was set. received and transferred to the RCREG FIFO and a 8. Read the RCSTA register to get the ninth bit (if third byte to begin shifting into the RSR register. On the enabled) and determine if any error occurred clocking of the last bit of the third byte, if the RCREG during reception. register is still full, then overrun error bit OERR 9. Read the 8-bit received data by reading the (RCSTA<1>) is set. The word in the RSR will be lost. RCREG register. The RCREG register can be read twice to retrieve the 10. If any error occurred, clear the error by clearing two bytes in the FIFO. Bit OERR has to be cleared in bit CREN. software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, so 11. If using interrupts, ensure that GIE and PEIE it is essential to clear bit OERR if it is set. The ninth (bits 7 and 6) of the INTCON register are set. TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS30292D-page 107

PIC16F87X FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRG = '0'. 10.4 USART Synchronous Slave Mode e) If enable bit TXIE is set, the interrupt will wake the chip from SLEEP and if the global interrupt Synchronous Slave mode differs from the Master mode is enabled, the program will branch to the inter- in the fact that the shift clock is supplied externally at rupt vector (0004h). the RC6/TX/CK pin (instead of being supplied internally When setting up a Synchronous Slave Transmission, in Master mode). This allows the device to transfer or follow these steps: receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 1. Enable the synchronous slave serial port by set- ting bits SYNC and SPEN and clearing bit 10.4.1 USART SYNCHRONOUS SLAVE CSRC. TRANSMIT 2. Clear bits CREN and SREN. The operation of the Synchronous Master and Slave 3. If interrupts are desired, then set enable bit modes is identical, except in the case of the SLEEP mode. TXIE. 4. If 9-bit transmission is desired, then set bit TX9. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 5. Enable the transmission by setting enable bit TXEN. a) The first word will immediately transfer to the 6. If 9-bit transmission is selected, the ninth bit TSR register and transmit. should be loaded in bit TX9D. b) The second word will remain in TXREG register. 7. Start transmission by loading data to the TXREG c) Flag bit TXIF will not be set. register. d) When the first word has been shifted out of TSR, 8. If using interrupts, ensure that GIE and PEIE the TXREG register will transfer the second word (bits 7 and 6) of the INTCON register are set. to the TSR and flag bit TXIF will now be set. TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on all Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. DS30292D-page 108  1998-2013 Microchip Technology Inc.

PIC16F87X 10.4.2 USART SYNCHRONOUS SLAVE 2. If interrupts are desired, set enable bit RCIE. RECEPTION 3. If 9-bit reception is desired, set bit RX9. 4. To enable reception, set enable bit CREN. The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP 5. Flag bit RCIF will be set when reception is com- mode. Bit SREN is a “don't care” in Slave mode. plete and an interrupt will be generated, if enable bit RCIE was set. If receive is enabled by setting bit CREN prior to the 6. Read the RCSTA register to get the ninth bit (if SLEEP instruction, then a word may be received during enabled) and determine if any error occurred SLEEP. On completely receiving the word, the RSR during reception. register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated 7. Read the 8-bit received data by reading the will wake the chip from SLEEP. If the global interrupt is RCREG register. enabled, the program will branch to the interrupt vector 8. If any error occurred, clear the error by clearing (0004h). bit CREN. When setting up a Synchronous Slave Reception, fol- 9. If using interrupts, ensure that GIE and PEIE low these steps: (bits 7 and 6) of the INTCON register are set. 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices, always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS30292D-page 109

PIC16F87X NOTES: DS30292D-page 110  1998-2013 Microchip Technology Inc.

PIC16F87X 11.0 ANALOG-TO-DIGITAL The A/D module has four registers. These registers CONVERTER (A/D) MODULE are: • A/D Result High Register (ADRESH) The Analog-to-Digital (A/D) Converter module has five • A/D Result Low Register (ADRESL) inputs for the 28-pin devices and eight for the other • A/D Control Register0 (ADCON0) devices. • A/D Control Register1 (ADCON1) The analog input charges a sample and hold capacitor. The output of the sample and hold capacitor is the input The ADCON0 register, shown in Register11-1, con- into the converter. The converter then generates a dig- trols the operation of the A/D module. The ADCON1 ital result of this analog level via successive approxima- register, shown in Register11-2, configures the func- tion. The A/D conversion of the analog input signal tions of the port pins. The port pins can be configured results in a corresponding 10-bit digital number. The as analog inputs (RA3 can also be the voltage refer- A/D module has high and low voltage reference input ence), or as digital I/O. that is software selectable to some combination of VDD, Additional information on using the A/D module can be VSS, RA2, or RA3. found in the PIC® MCU Mid-Range Family Reference The A/D converter has a unique feature of being able Manual (DS33023). to operate while the device is in SLEEP mode. To oper- ate in SLEEP, the A/D clock must be derived from the A/D’s internal RC oscillator. REGISTER 11-1: ADCON0 REGISTER (ADDRESS: 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal A/D module RC oscillator) bit 5-3 CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) 101 = channel 5, (RE0/AN5)(1) 110 = channel 6, (RE1/AN6)(1) 111 = channel 7, (RE2/AN7)(1) bit 2 GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete) bit 1 Unimplemented: Read as '0' bit 0 ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Note 1: These channels are not available on PIC16F873/876 devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30292D-page 111

PIC16F87X REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’. bit 6-4 Unimplemented: Read as '0' bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits: PCFG3: AN7(1) AN6(1) AN5(1) AN4 AN3 AN2 AN1 AN0 CHAN/ PCFG0 RE2 RE1 RE0 RA5 RA3 RA2 RA1 RA0 VREF+ VREF- Refs(2) 0000 A A A A A A A A VDD VSS 8/0 0001 A A A A VREF+ A A A RA3 VSS 7/1 0010 D D D A A A A A VDD VSS 5/0 0011 D D D A VREF+ A A A RA3 VSS 4/1 0100 D D D D A D A A VDD VSS 3/0 0101 D D D D VREF+ D A A RA3 VSS 2/1 011x D D D D D D D D VDD VSS 0/0 1000 A A A A VREF+ VREF- A A RA3 RA2 6/2 1001 D D A A A A A A VDD VSS 6/0 1010 D D A A VREF+ A A A RA3 VSS 5/1 1011 D D A A VREF+ VREF- A A RA3 RA2 4/2 1100 D D D A VREF+ VREF- A A RA3 RA2 3/2 1101 D D D D VREF+ VREF- A A RA3 RA2 2/2 1110 D D D D D D D A VDD VSS 1/0 1111 D D D D VREF+ VREF- D A RA3 RA2 1/2 A = Analog input D = Digital I/O Note 1: These channels are not available on PIC16F873/876 devices. 2: This column indicates the number of analog channels available as A/D inputs and the number of analog channels used as voltage reference inputs. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown The ADRESH:ADRESL registers contain the 10-bit To determine sample time, see Section11.1. After this result of the A/D conversion. When the A/D conversion acquisition time has elapsed, the A/D conversion can is complete, the result is loaded into this A/D result reg- be started. ister pair, the GO/DONE bit (ADCON0<2>) is cleared and the A/D interrupt flag bit ADIF is set. The block dia- gram of the A/D module is shown in Figure11-1. After the A/D module has been configured as desired, the selected channel must be acquired before the con- version is started. The analog input channels must have their corresponding TRIS bits selected as inputs. DS30292D-page 112  1998-2013 Microchip Technology Inc.

PIC16F87X These steps should be followed for doing an A/D 3. Wait the required acquisition time. Conversion: 4. Start conversion: 1. Configure the A/D module: • Set GO/DONE bit (ADCON0) • Configure analog pins/voltage reference and 5. Wait for A/D conversion to complete, by either: digital I/O (ADCON1) • Polling for the GO/DONE bit to be cleared • Select A/D input channel (ADCON0) (with interrupts enabled); OR • Select A/D conversion clock (ADCON0) • Waiting for the A/D interrupt • Turn on A/D module (ADCON0) 6. Read A/D result register pair 2. Configure A/D interrupt (if desired): (ADRESH:ADRESL), clear bit ADIF if required. • Clear ADIF bit 7. For the next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is • Set ADIE bit defined as TAD. A minimum wait of 2TAD is • Set PEIE bit required before the next acquisition starts. • Set GIE bit FIGURE 11-1: A/D BLOCK DIAGRAM CHS2:CHS0 111 RE2/AN7(1) 110 RE1/AN6(1) 101 RE0/AN5(1) 100 RA5/AN4 VAIN 011 (Input Voltage) RA3/AN3/VREF+ 010 A/D RA2/AN2/VREF- Converter 001 RA1/AN1 000 VDD RA0/AN0 VREF+ (Reference Voltage) PCFG3:PCFG0 VREF- (Reference Voltage) VSS PCFG3:PCFG0 Note 1: Not available on PIC16F873/876 devices.  1998-2013 Microchip Technology Inc. DS30292D-page 113

PIC16F87X 11.1 A/D Acquisition Requirements After the analog input channel is selected (changed), this acquisition must be done before the conversion For the A/D converter to meet its specified accuracy, can be started. the charge holding capacitor (CHOLD) must be allowed To calculate the minimum acquisition time, to fully charge to the input channel voltage level. The Equation11-1 may be used. This equation assumes analog input model is shown in Figure11-2. The source that 1/2 LSb error is used (1024 steps for the A/D). The impedance (RS) and the internal sampling switch (RSS) 1/2 LSb error is the maximum error allowed for the A/D impedance directly affect the time required to charge to meet its specified resolution. the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see To calculate the minimum acquisition time, TACQ, see Figure11-2. The maximum recommended imped- the PIC® MCU Mid-Range Reference Manual ance for analog sources is 10 k. As the impedance (DS33023). is decreased, the acquisition time may be decreased. EQUATION 11-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + [(Temperature -25°C)(0.05s/°C)] TC = CHOLD (RIC + RSS + RS) In(1/2047) = - 120pF (1k + 7k + 10k) In(0.0004885) = 16.47s TACQ = 2s + 16.47s + [(50°C -25C)(0.05s/C) = 19.72s Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leak- age specification. 4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again. During this time, the holding capacitor is not connected to the selected A/D input channel. FIGURE 11-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC  1k SS RSS CHOLD VA C5 PpIFN VT = 0.6V I± L5E0A0K AnGAE == 1D2A0C p cFapacitance VSS Legend CPIN = input capacitance 6V VT = threshold voltage 5V I LEAKAGE = leakage current at the pin due to VDD4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5 6 7 891011 Sampling Switch (k) DS30292D-page 114  1998-2013 Microchip Technology Inc.

PIC16F87X 11.2 Selecting the A/D Conversion For correct A/D conversions, the A/D conversion clock Clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. The A/D conversion time per bit is defined as TAD. The Table11-1 shows the resultant TAD times derived from A/D conversion requires a minimum 12TAD per 10-bit the device operating frequencies and the A/D clock conversion. The source of the A/D conversion clock is source selected. software selected. The four possible options for TAD are: • 2TOSC • 8TOSC • 32TOSC • Internal A/D module RC oscillator (2-6 s) TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C)) AD Clock Source (TAD) Maximum Device Frequency Operation ADCS1:ADCS0 Max. 2TOSC 00 1.25 MHz 8TOSC 01 5 MHz 32TOSC 10 20 MHz RC(1, 2, 3) 11 (Note 1) Note 1: The RC source has a typical TAD time of 4 s, but can vary between 2-6 s. 2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recom- mended for SLEEP operation. 3: For extended voltage devices (LC), please refer to the Electrical Characteristics (Sections 15.1 and 15.2). 11.3 Configuring Analog Port Pins The ADCON1 and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, any pin configured as an analog input channel will read as cleared (a low level). Pins config- ured as digital inputs will convert an ana- log input. Analog levels on a digitally configured input will not affect the conver- sion accuracy. 2: Analog levels on any pin that is defined as a digital input (including the AN7:AN0 pins), may cause the input buffer to con- sume current that is out of the device specifications.  1998-2013 Microchip Technology Inc. DS30292D-page 115

PIC16F87X 11.4 A/D Conversions acquisition is started. After this 2TAD wait, acquisition on the selected channel is automatically started. The Clearing the GO/DONE bit during a conversion will GO/DONE bit can then be set to start the conversion. abort the current conversion. The A/D result register In Figure11-3, after the GO bit is set, the first time seg- pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL ment has a minimum of TCY and a maximum of TAD. registers will continue to contain the value of the last Note: The GO/DONE bit should NOT be set in completed conversion (or the last value written to the the same instruction that turns on the A/D. ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2TAD wait is required before the next FIGURE 11-3: A/D CONVERSION TAD CYCLES TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit ADRES is loaded GO bit is cleared ADIF bit is set Holding capacitor is connected to analog input 11.4.1 A/D RESULT REGISTERS Format Select bit (ADFM) controls this justification. Figure11-4 shows the operation of the A/D result justi- The ADRESH:ADRESL register pair is the location fication. The extra bits are loaded with ’0’s’. When an where the 10-bit A/D result is loaded at the completion A/D result will not overwrite these locations (A/D dis- of the A/D conversion. This register pair is 16-bits wide. able), these registers may be used as two general The A/D module gives the flexibility to left or right justify purpose 8-bit registers. the 10-bit result in the 16-bit result register. The A/D FIGURE 11-4: A/D RESULT JUSTIFICATION 10-bit Result ADFM = 1 ADFM = 0 7 2 1 0 7 0 7 0 7 6 5 0 0000 00 0000 00 ADRESH ADRESL ADRESH ADRESL 10-bit Result 10-bit Result Right Justified Left Justified DS30292D-page 116  1998-2013 Microchip Technology Inc.

PIC16F87X 11.5 A/D Operation During SLEEP Turning off the A/D places the A/D module in its lowest current consumption state. The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC Note: For the A/D module to operate in SLEEP, (ADCS1:ADCS0 = 11). When the RC clock source is the A/D clock source must be set to RC selected, the A/D module waits one instruction cycle (ADCS1:ADCS0 = 11). To allow the con- before starting the conversion. This allows the SLEEP version to occur during SLEEP, ensure the instruction to be executed, which eliminates all digital SLEEP instruction immediately follows the switching noise from the conversion. When the conver- instruction that sets the GO/DONE bit. sion is completed, the GO/DONE bit will be cleared and 11.6 Effects of a RESET the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from A device RESET forces all registers to their RESET SLEEP. If the A/D interrupt is not enabled, the A/D state. This forces the A/D module to be turned off, and module will then be turned off, although the ADON bit any conversion is aborted. All A/D input pins are con- will remain set. figured as analog inputs. When the A/D clock source is another clock option (not The value that is in the ADRESH:ADRESL registers is RC), a SLEEP instruction will cause the present conver- not modified for a Power-on Reset. The sion to be aborted and the A/D module to be turned off, ADRESH:ADRESL registers will contain unknown data though the ADON bit will remain set. after a Power-on Reset. TABLE 11-2: REGISTERS/BITS ASSOCIATED WITH A/D Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, MCLR, BOR WDT 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 89h(1) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 09h(1) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: These registers/bits are not available on the 28-pin devices.  1998-2013 Microchip Technology Inc. DS30292D-page 117

PIC16F87X NOTES: DS30292D-page 118  1998-2013 Microchip Technology Inc.

PIC16F87X 12.0 SPECIAL FEATURES OF THE SLEEP mode is designed to offer a very low current CPU Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer All PIC16F87X devices have a host of features Wake-up, or through an interrupt. intended to maximize system reliability, minimize cost Several oscillator options are also made available to through elimination of external components, provide allow the part to fit the application. The RC oscillator power saving operating modes and offer code protec- option saves system cost while the LP crystal option tion. These are: saves power. A set of configuration bits is used to • Oscillator Selection select various options. • RESET Additional information on special features is available - Power-on Reset (POR) in the PIC® MCU Mid-Range Reference Manual, - Power-up Timer (PWRT) (DS33023). - Oscillator Start-up Timer (OST) 12.1 Configuration Bits - Brown-out Reset (BOR) • Interrupts The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various • Watchdog Timer (WDT) device configurations. The erased, or unprogrammed • SLEEP value of the configuration word is 3FFFh. These bits • Code Protection are mapped in program memory location 2007h. • ID Locations It is important to note that address 2007h is beyond the • In-Circuit Serial Programming user program memory space, which can be accessed • Low Voltage In-Circuit Serial Programming only during programming. • In-Circuit Debugger PIC16F87X devices have a Watchdog Timer, which can be shut-off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nomi- nal) on power-up only. It is designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry.  1998-2013 Microchip Technology Inc. DS30292D-page 119

PIC16F87X REGISTER 12-1: CONFIGURATION WORD (ADDRESS 2007h)(1) CP1 CP0 DEBUG — WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 bit13 bit0 bit 13-12, CP1:CP0: FLASH Program Memory Code Protection bits(2) bit 5-4 11 = Code protection off 10 = 1F00h to 1FFFh code protected (PIC16F877, 876) 10 = 0F00h to 0FFFh code protected (PIC16F874, 873) 01 = 1000h to 1FFFh code protected (PIC16F877, 876) 01 = 0800h to 0FFFh code protected (PIC16F874, 873) 00 = 0000h to 1FFFh code protected (PIC16F877, 876) 00 = 0000h to 0FFFh code protected (PIC16F874, 873) bit 11 DEBUG: In-Circuit Debugger Mode 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger. bit 10 Unimplemented: Read as ‘1’ bit 9 WRT: FLASH Program Memory Write Enable 1 = Unprotected program memory may be written to by EECON control 0 = Unprotected program memory may not be written to by EECON control bit 8 CPD: Data EE Memory Code Protection 1 = Code protection off 0 = Data EEPROM memory code protected bit 7 LVP: Low Voltage In-Circuit Serial Programming Enable bit 1 = RB3/PGM pin has PGM function, low voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming bit 6 BODEN: Brown-out Reset Enable bit(3) 1 = BOR enabled 0 = BOR disabled bit 3 PWRTE: Power-up Timer Enable bit(3) 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 3: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled. DS30292D-page 120  1998-2013 Microchip Technology Inc.

PIC16F87X 12.2 Oscillator Configurations FIGURE 12-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR 12.2.1 OSCILLATOR TYPES LP OSC CONFIGURATION) The PIC16F87X can be operated in four different oscil- lator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: Clock from OSC1 • LP Low Power Crystal Ext. System PIC16F87X • XT Crystal/Resonator Open OSC2 • HS High Speed Crystal/Resonator • RC Resistor/Capacitor 12.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS In XT, LP or HS modes, a crystal or ceramic resonator TABLE 12-1: CERAMIC RESONATORS is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure12-1). The Ranges Tested: PIC16F87X oscillator design requires the use of a par- Mode Freq. OSC1 OSC2 allel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- XT 455 kHz 68 - 100 pF 68 - 100 pF tions. When in XT, LP or HS modes, the device can 2.0 MHz 15 - 68 pF 15 - 68 pF have an external clock source to drive the OSC1/ 4.0 MHz 15 - 68 pF 15 - 68 pF CLKIN pin (Figure12-2). HS 8.0 MHz 10 - 68 pF 10 - 68 pF 16.0 MHz 10 - 22 pF 10 - 22 pF FIGURE 12-1: CRYSTAL/CERAMIC These values are for design guidance only. RESONATOR OPERATION See notes following Table12-2. (HS, XT OR LP OSC CONFIGURATION) Resonators Used: 455 kHz Panasonic EFO-A455K04B  0.3% C1(1) OSC1 2.0 MHz Murata Erie CSA2.00MG  0.5% To 4.0 MHz Murata Erie CSA4.00MG  0.5% Internal XTAL RF(3) Logic 8.0 MHz Murata Erie CSA8.00MT  0.5% OSC2 16.0 MHz Murata Erie CSA16.00MX  0.5% SLEEP R (2) All resonators used did not have built-in capacitors. s C2(1) PIC16F87X Note1: See Table12-1 and Table12-2 for recom- mended values of C1 and C2. 2: A series resistor (R ) may be required for AT s strip cut crystals. 3: RF varies with the crystal chosen.  1998-2013 Microchip Technology Inc. DS30292D-page 121

PIC16F87X TABLE 12-2: CAPACITOR SELECTION FOR 12.2.3 RC OSCILLATOR CRYSTAL OSCILLATOR For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator Crystal Cap. Range Cap. Range Osc Type frequency is a function of the supply voltage, the resis- Freq. C1 C2 tor (REXT) and capacitor (CEXT) values, and the operat- LP 32 kHz 33 pF 33 pF ing temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal pro- 200 kHz 15 pF 15 pF cess parameter variation. Furthermore, the difference XT 200 kHz 47-68 pF 47-68 pF in lead frame capacitance between package types will 1 MHz 15 pF 15 pF also affect the oscillation frequency, especially for low 4 MHz 15 pF 15 pF CEXT values. The user also needs to take into account variation due to tolerance of external R and C compo- HS 4 MHz 15 pF 15 pF nents used. Figure12-3 shows how the R/C combina- 8 MHz 15-33 pF 15-33 pF tion is connected to the PIC16F87X. 20 MHz 15-33 pF 15-33 pF These values are for design guidance only. FIGURE 12-3: RC OSCILLATOR MODE See notes following this table. VDD Crystals Used 32 kHz Epson C-001R32.768K-A ± 20 PPM REXT Internal 200 kHz STD XTL 200.000KHz ± 20 PPM OSC1 Clock 1 MHz ECS ECS-10-13-1 ± 50 PPM CEXT PIC16F87X 4 MHz ECS ECS-40-20-1 ± 50 PPM VSS 8 MHz EPSON CA-301 8.000M-C ± 30 PPM OSC2/CLKOUT 20 MHz EPSON CA-301 20.000M- ± 30 PPM FOSC/4 C Recommended values: 3 k  REXT  100 k CEXT > 20pF Note 1: Higher capacitance increases the stability of oscillator, but also increases the start- up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appro- priate values of external components. 3: R may be required in HS mode, as well s as XT mode, to avoid overdriving crystals with low drive level specification. 4: When migrating from other PIC® MCU devices, oscillator performance should be verified. DS30292D-page 122  1998-2013 Microchip Technology Inc.

PIC16F87X 12.3 RESET SLEEP, and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the The PIC16F87X differentiates between various kinds of resumption of normal operation. The TO and PD bits RESET: are set or cleared differently in different RESET situa- • Power-on Reset (POR) tions as indicated in Table12-4. These bits are used in • MCLR Reset during normal operation software to determine the nature of the RESET. See Table12-6 for a full description of RESET states of all • MCLR Reset during SLEEP registers. • WDT Reset (during normal operation) A simplified block diagram of the On-Chip Reset Circuit • WDT Wake-up (during SLEEP) is shown in Figure12-4. • Brown-out Reset (BOR) These devices have a MCLR noise filter in the MCLR Some registers are not affected in any RESET condi- Reset path. The filter will detect and ignore small tion. Their status is unknown on POR and unchanged pulses. in any other RESET. Most other registers are reset to a “RESET state” on Power-on Reset (POR), on the It should be noted that a WDT Reset does not drive MCLR and WDT Reset, on MCLR Reset during MCLR pin low. FIGURE 12-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR SLEEP WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out Reset BODEN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1 (1) PWRT On-chip RC OSC 10-bit Ripple Counter Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.  1998-2013 Microchip Technology Inc. DS30292D-page 123

PIC16F87X 12.4 Power-On Reset (POR) 12.7 Brown-out Reset (BOR) A Power-on Reset pulse is generated on-chip when The configuration bit, BODEN, can enable or disable VDD rise is detected (in the range of 1.2V - 1.7V). To the Brown-out Reset circuit. If VDD falls below VBOR take advantage of the POR, tie the MCLR pin directly (parameter D005, about 4V) for longer than TBOR (or through a resistor) to VDD. This will eliminate (parameter #35, about 100S), the brown-out situation external RC components usually needed to create a will reset the device. If VDD falls below VBOR for less Power-on Reset. A maximum rise time for VDD is spec- than TBOR, a RESET may not occur. ified. See Electrical Specifications for details. Once the brown-out occurs, the device will remain in When the device starts normal operation (exits the Brown-out Reset until VDD rises above VBOR. The RESET condition), device operating parameters (volt- Power-up Timer then keeps the device in RESET for age, frequency, temperature,...) must be met to ensure TPWRT (parameter #33, about 72mS). If VDD should fall operation. If these conditions are not met, the device below VBOR during TPWRT, the Brown-out Reset pro- must be held in RESET until the operating conditions cess will restart when VDD rises above VBOR with the are met. Brown-out Reset may be used to meet the Power-up Timer Reset. The Power-up Timer is always start-up conditions. For additional information, refer to enabled when the Brown-out Reset circuit is enabled, Application Note, AN007, “Power-up Trouble Shoot- regardless of the state of the PWRT configuration bit. ing”, (DS00007). 12.8 Time-out Sequence 12.5 Power-up Timer (PWRT) On power-up, the time-out sequence is as follows: The The Power-up Timer provides a fixed 72 ms nominal PWRT delay starts (if enabled) when a POR Reset time-out on power-up only from the POR. The Power- occurs. Then OST starts counting 1024 oscillator up Timer operates on an internal RC oscillator. The cycles when PWRT ends (LP, XT, HS). When the OST chip is kept in RESET as long as the PWRT is active. ends, the device comes out of RESET. The PWRT’s time delay allows VDD to rise to an accept- If MCLR is kept low long enough, the time-outs will able level. A configuration bit is provided to enable/dis- expire. Bringing MCLR high will begin execution imme- able the PWRT. diately. This is useful for testing purposes or to synchro- The power-up time delay will vary from chip to chip due nize more than one PIC16F87X device operating in to VDD, temperature and process variation. See DC parallel. parameters for details (TPWRT, parameter #33). Table12-5 shows the RESET conditions for the STA- TUS, PCON and PC registers, while Table12-6 shows 12.6 Oscillator Start-up Timer (OST) the RESET conditions for all the registers. The Oscillator Start-up Timer (OST) provides a delay of 12.9 Power Control/Status Register 1024 oscillator cycles (from OSC1 input) after the PWRT delay is over (if PWRT is enabled). This helps to (PCON) ensure that the crystal oscillator or resonator has The Power Control/Status Register, PCON, has up to started and stabilized. two bits depending upon the device. The OST time-out is invoked only for XT, LP and HS Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is modes and only on Power-on Reset or Wake-up from unknown on a Power-on Reset. It must then be set by SLEEP. the user and checked on subsequent RESETS to see if bit BOR cleared, indicating a BOR occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable and is, therefore, not valid at any time. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Wake-up from Oscillator Configuration Brown-out SLEEP PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC RC 72 ms — 72 ms — DS30292D-page 124  1998-2013 Microchip Technology Inc.

PIC16F87X TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP Legend: x = don’t care, u = unchanged TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --u0 Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).  1998-2013 Microchip Technology Inc. DS30292D-page 125

PIC16F87X TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, MCLR Resets, Wake-up via WDT or Register Devices Brown-out Reset WDT Reset Interrupt W 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu INDF 873 874 876 877 N/A N/A N/A TMR0 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu PCL 873 874 876 877 0000h 0000h PC + 1(2) STATUS 873 874 876 877 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu PORTA 873 874 876 877 --0x 0000 --0u 0000 --uu uuuu PORTB 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu PORTD 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu PORTE 873 874 876 877 ---- -xxx ---- -uuu ---- -uuu PCLATH 873 874 876 877 ---0 0000 ---0 0000 ---u uuuu INTCON 873 874 876 877 0000 000x 0000 000u uuuu uuuu(1) PIR1 873 874 876 877 r000 0000 r000 0000 ruuu uuuu(1) 873 874 876 877 0000 0000 0000 0000 uuuu uuuu(1) PIR2 873 874 876 877 -r-0 0--0 -r-0 0--0 -r-u u--u(1) TMR1L 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 873 874 876 877 --00 0000 --uu uuuu --uu uuuu TMR2 873 874 876 877 0000 0000 0000 0000 uuuu uuuu T2CON 873 874 876 877 -000 0000 -000 0000 -uuu uuuu SSPBUF 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 873 874 876 877 0000 0000 0000 0000 uuuu uuuu CCPR1L 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 873 874 876 877 --00 0000 --00 0000 --uu uuuu RCSTA 873 874 876 877 0000 000x 0000 000x uuuu uuuu TXREG 873 874 876 877 0000 0000 0000 0000 uuuu uuuu RCREG 873 874 876 877 0000 0000 0000 0000 uuuu uuuu CCPR2L 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 873 874 876 877 0000 0000 0000 0000 uuuu uuuu ADRESH 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 873 874 876 877 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 873 874 876 877 1111 1111 1111 1111 uuuu uuuu TRISA 873 874 876 877 --11 1111 --11 1111 --uu uuuu TRISB 873 874 876 877 1111 1111 1111 1111 uuuu uuuu TRISC 873 874 876 877 1111 1111 1111 1111 uuuu uuuu TRISD 873 874 876 877 1111 1111 1111 1111 uuuu uuuu TRISE 873 874 876 877 0000 -111 0000 -111 uuuu -uuu PIE1 873 874 876 877 r000 0000 r000 0000 ruuu uuuu 873 874 876 877 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table12-5 for RESET value for specific condition. DS30292D-page 126  1998-2013 Microchip Technology Inc.

PIC16F87X TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, MCLR Resets, Wake-up via WDT or Register Devices Brown-out Reset WDT Reset Interrupt PIE2 873 874 876 877 -r-0 0--0 -r-0 0--0 -r-u u--u PCON 873 874 876 877 ---- --qq ---- --uu ---- --uu PR2 873 874 876 877 1111 1111 1111 1111 1111 1111 SSPADD 873 874 876 877 0000 0000 0000 0000 uuuu uuuu SSPSTAT 873 874 876 877 --00 0000 --00 0000 --uu uuuu TXSTA 873 874 876 877 0000 -010 0000 -010 uuuu -uuu SPBRG 873 874 876 877 0000 0000 0000 0000 uuuu uuuu ADRESL 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 873 874 876 877 0--- 0000 0--- 0000 u--- uuuu EEDATA 873 874 876 877 0--- 0000 0--- 0000 u--- uuuu EEADR 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu EEDATH 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu EEADRH 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu EECON1 873 874 876 877 x--- x000 u--- u000 u--- uuuu EECON2 873 874 876 877 ---- ---- ---- ---- ---- ---- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table12-5 for RESET value for specific condition. FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  1998-2013 Microchip Technology Inc. DS30292D-page 127

PIC16F87X FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 12-8: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30292D-page 128  1998-2013 Microchip Technology Inc.

PIC16F87X 12.10 Interrupts The RB0/INT pin interrupt, the RB port change inter- rupt, and the TMR0 overflow interrupt flags are con- The PIC16F87X family has up to 14 sources of inter- tained in the INTCON register. rupt. The interrupt control register (INTCON) records The peripheral interrupt flags are contained in the spe- individual interrupt requests in flag bits. It also has indi- cial function registers, PIR1 and PIR2. The correspond- vidual and global interrupt enable bits. ing interrupt enable bits are contained in special Note: Individual interrupt flag bits are set, regard- function registers, PIE1 and PIE2, and the peripheral less of the status of their corresponding interrupt enable bit is contained in special function reg- mask bit, or the GIE bit. ister INTCON. A global interrupt enable bit, GIE (INTCON<7>) When an interrupt is responded to, the GIE bit is enables (if set) all unmasked interrupts, or disables (if cleared to disable any further interrupt, the return cleared) all interrupts. When bit GIE is enabled, and an address is pushed onto the stack and the PC is loaded interrupt’s flag bit and mask bit are set, the interrupt will with 0004h. Once in the Interrupt Service Routine, the vector immediately. Individual interrupts can be dis- source(s) of the interrupt can be determined by polling abled through their corresponding enable bits in vari- the interrupt flag bits. The interrupt flag bit(s) must be ous registers. Individual interrupt bits are set, cleared in software before re-enabling interrupts to regardless of the status of the GIE bit. The GIE bit is avoid recursive interrupts. cleared on RESET. For external interrupt events, such as the INT pin or The “return from interrupt” instruction, RETFIE, exits PORTB change interrupt, the interrupt latency will be the interrupt routine, as well as sets the GIE bit, which three or four instruction cycles. The exact latency re-enables interrupts. depends when the interrupt event occurs. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or GIE bit. FIGURE 12-9: INTERRUPT LOGIC EEIF EEIE PSPIF PSPIE ADIF T0IF Wake-up (If in SLEEP mode) ADIE T0IE RCIF INTF RCIE INTE Interrupt to CPU TXIF RBIF TXIE RBIE SSPIF SSPIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE BCLIF BCLIE The following table shows which devices have which interrupts. Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF EEIF BCLIF CCP2IF PIC16F876/873 Yes Yes Yes — Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PIC16F877/874 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes  1998-2013 Microchip Technology Inc. DS30292D-page 129

PIC16F87X 12.10.1 INT INTERRUPT 12.11 Context Saving During Interrupts External interrupt on the RB0/INT pin is edge triggered, During an interrupt, only the return PC value is saved either rising, if bit INTEDG (OPTION_REG<6>) is set, on the stack. Typically, users may wish to save key reg- or falling, if the INTEDG bit is clear. When a valid edge isters during an interrupt, (i.e., W register and STATUS appears on the RB0/INT pin, flag bit INTF register). This will have to be implemented in software. (INTCON<1>) is set. This interrupt can be disabled by For the PIC16F873/874 devices, the register W_TEMP clearing enable bit INTE (INTCON<4>). Flag bit INTF must be defined in both banks 0 and 1 and must be must be cleared in software in the Interrupt Service defined at the same offset from the bank base address Routine before re-enabling this interrupt. The INT inter- (i.e., If W_TEMP is defined at 0x20 in bank 0, it must rupt can wake-up the processor from SLEEP, if bit INTE also be defined at 0xA0 in bank 1). The registers, was set prior to going into SLEEP. The status of global PCLATH_TEMP and STATUS_TEMP, are only defined interrupt enable bit, GIE, decides whether or not the in bank 0. processor branches to the interrupt vector following wake-up. See Section12.13 for details on SLEEP Since the upper 16 bytes of each bank are common in mode. the PIC16F876/877 devices, temporary holding regis- ters W_TEMP, STATUS_TEMP, and PCLATH_TEMP 12.10.2 TMR0 INTERRUPT should be placed in here. These 16 locations don’t require banking and therefore, make it easier for con- An overflow (FFh  00h) in the TMR0 register will set text save and restore. The same code shown in flag bit T0IF (INTCON<2>). The interrupt can be Example12-1 can be used. enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>) (Section5.0). 12.10.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>) (Section3.2). EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ;Save PCLATH into W CLRF PCLATH ;Page zero, regardless of current page : :(ISR) ;(Insert user code here) : MOVF PCLATH_TEMP, W ;Restore PCLATH MOVWF PCLATH ;Move W into PCLATH SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W DS30292D-page 130  1998-2013 Microchip Technology Inc.

PIC16F87X 12.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Elec- trical Specifications section under parameter #31. Val- The Watchdog Timer is a free running on-chip RC oscil- ues for the WDT prescaler (actually a postscaler, but lator which does not require any external components. shared with the Timer0 prescaler) may be assigned This RC oscillator is separate from the RC oscillator of using the OPTION_REG register. the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/ Note 1: The CLRWDT and SLEEP instructions CLKOUT pins of the device has been stopped, for clear the WDT and the postscaler, if example, by execution of a SLEEP instruction. assigned to the WDT, and prevent it from timing out and generating a device During normal operation, a WDT time-out generates a RESET condition. device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to 2: When a CLRWDT instruction is executed wake-up and continue with normal operation (Watch- and the prescaler is assigned to the WDT, dog Timer Wake-up). The TO bit in the STATUS regis- the prescaler count will be cleared, but ter will be cleared upon a Watchdog Timer time-out. the prescaler assignment is not changed. The WDT can be permanently disabled by clearing configuration bit WDTE (Section12.1). FIGURE 12-10: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure5-1) 0 M Postscaler 1 WDT Timer U X 8 8 - to - 1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure5-1) 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register. TABLE 12-7: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register12-1 for operation of these bits.  1998-2013 Microchip Technology Inc. DS30292D-page 131

PIC16F87X 12.13 Power-down Mode (SLEEP) When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to Power-down mode is entered by executing a SLEEP wake-up through an interrupt event, the corresponding instruction. interrupt enable bit must be set (enabled). Wake-up is If enabled, the Watchdog Timer will be cleared but regardless of the state of the GIE bit. If the GIE bit is keeps running, the PD bit (STATUS<3>) is cleared, the clear (disabled), the device continues execution at the TO (STATUS<4>) bit is set, and the oscillator driver is instruction after the SLEEP instruction. If the GIE bit is turned off. The I/O ports maintain the status they had set (enabled), the device executes the instruction after before the SLEEP instruction was executed (driving the SLEEP instruction and then branches to the inter- high, low, or hi-impedance). rupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the For lowest current consumption in this mode, place all user should have a NOP after the SLEEP instruction. I/O pins at either VDD or VSS, ensure no external cir- cuitry is drawing current from the I/O pin, power-down 12.13.2 WAKE-UP USING INTERRUPTS the A/D and disable external clocks. Pull all I/O pins that are hi-impedance inputs, high or low externally, to When global interrupts are disabled (GIE cleared) and avoid switching currents caused by floating inputs. The any interrupt source has both its interrupt enable bit T0CKI input should also be at VDD or VSS for lowest and interrupt flag bit set, one of the following will occur: current consumption. The contribution from on-chip • If the interrupt occurs before the execution of a pull-ups on PORTB should also be considered. SLEEP instruction, the SLEEP instruction will com- The MCLR pin must be at a logic high level (VIHMC). plete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not 12.13.1 WAKE-UP FROM SLEEP be set and PD bits will not be cleared. The device can wake-up from SLEEP through one of • If the interrupt occurs during or after the execu- the following events: tion of a SLEEP instruction, the device will imme- diately wake-up from SLEEP. The SLEEP 1. External RESET input on MCLR pin. instruction will be completely executed before the 2. Watchdog Timer Wake-up (if WDT was wake-up. Therefore, the WDT and WDT enabled). postscaler will be cleared, the TO bit will be set 3. Interrupt from INT pin, RB port change or and the PD bit will be cleared. peripheral interrupt. Even if the flag bits were checked before executing a External MCLR Reset will cause a device RESET. All SLEEP instruction, it may be possible for flag bits to other events are considered a continuation of program become set before the SLEEP instruction completes. To execution and cause a “wake-up”. The TO and PD bits determine whether a SLEEP instruction executed, test in the STATUS register can be used to determine the the PD bit. If the PD bit is set, the SLEEP instruction cause of device RESET. The PD bit, which is set on was executed as a NOP. power-up, is cleared when SLEEP is invoked. The TO To ensure that the WDT is cleared, a CLRWDT instruc- bit is cleared if a WDT time-out occurred and caused tion should be executed before a SLEEP instruction. wake-up. The following peripheral interrupts can wake the device from SLEEP: 1. PSP read or write (PIC16F874/877 only). 2. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 3. CCP Capture mode interrupt. 4. Special event trigger (Timer1 in Asynchronous mode using an external clock). 5. SSP (START/STOP) bit detect interrupt. 6. SSP transmit or receive in Slave mode (SPI/I2C). 7. USART RX or TX (Synchronous Slave mode). 8. A/D conversion (when A/D clock source is RC). 9. EEPROM write operation completion Other peripherals cannot generate interrupts since dur- ing SLEEP, no on-chip clocks are present. DS30292D-page 132  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 12-11: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF Flag (INTCON<1>) Interrupt Latency(2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h Instruction Fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) Instruction Executed Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. 3: GIE = '1' assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 12.14 In-Circuit Debugger 12.15 Program Verification/Code Protection When the DEBUG bit in the configuration word is pro- grammed to a '0', the In-Circuit Debugger functionality If the code protection bit(s) have not been pro- is enabled. This function allows simple debugging func- grammed, the on-chip program memory can be read tions when used with MPLAB® ICD. When the micro- out for verification purposes. controller has this feature enabled, some of the resources are not available for general use. Table12-8 12.16 ID Locations shows which features are consumed by the back- ground debugger. Four memory locations (2000h - 2003h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are TABLE 12-8: DEBUGGER RESOURCES not accessible during normal execution, but are read- I/O pins RB6, RB7 able and writable during program/verify. It is recom- mended that only the 4 Least Significant bits of the ID Stack 1 level location are used. Program Memory Address 0000h must be NOP Last 100h words Data Memory 0x070 (0x0F0, 0x170, 0x1F0) 0x1EB - 0x1EF To use the In-Circuit Debugger function of the micro- controller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip, or one of the third party development tool companies.  1998-2013 Microchip Technology Inc. DS30292D-page 133

PIC16F87X 12.17 In-Circuit Serial Programming Note 1: The High Voltage Programming mode is PIC16F87X microcontrollers can be serially pro- always available, regardless of the state grammed while in the end application circuit. This is of the LVP bit, by applying VIHH to the simply done with two lines for clock and data and three MCLR pin. other lines for power, ground, and the programming voltage. This allows customers to manufacture boards 2: While in Low Voltage ICSP mode, the with unprogrammed devices, and then program the RB3 pin can no longer be used as a gen- microcontroller just before shipping the product. This eral purpose I/O pin. also allows the most recent firmware, or a custom firm- 3: When using low voltage ICSP program- ware to be programmed. ming (LVP) and the pull-ups on PORTB When using ICSP, the part must be supplied at 4.5V to are enabled, bit 3 in the TRISB register 5.5V, if a bulk erase will be executed. This includes must be cleared to disable the pull-up on reprogramming of the code protect, both from an on- RB3 and ensure the proper operation of state to off-state. For all other cases of ICSP, the part the device. may be programmed at the normal operating voltages. 4: RB3 should not be allowed to float if LVP This means calibration values, unique user IDs, or user is enabled. An external pull-down device code can be reprogrammed or added. should be used to default the device to For complete details of serial programming, please normal operating mode. If RB3 floats refer to the EEPROM Memory Programming Specifica- high, the PIC16F87X device will enter tion for the PIC16F87X (DS39025). Programming mode. 5: LVP mode is enabled by default on all 12.18 Low Voltage ICSP Programming devices shipped from Microchip. It can be disabled by clearing the LVP bit in the The LVP bit of the configuration word enables low volt- CONFIG register. age ICSP programming. This mode allows the micro- controller to be programmed via ICSP using a VDD 6: Disabling LVP will provide maximum com- source in the operating voltage range. This only means patibility to other PIC16CXXX devices. that VPP does not have to be brought to VIHH, but can If Low Voltage Programming mode is not used, the LVP instead be left at the normal operating voltage. In this bit can be programmed to a '0' and RB3/PGM becomes mode, the RB3/PGM pin is dedicated to the program- a digital I/O pin. However, the LVP bit may only be pro- ming function and ceases to be a general purpose I/O grammed when programming is entered with VIHH on pin. During programming, VDD is applied to the MCLR MCLR. The LVP bit can only be charged when using pin. To enter Programming mode, VDD must be applied high voltage on MCLR. to the RB3/PGM, provided the LVP bit is set. The LVP bit defaults to on (‘1’) from the factory. It should be noted, that once the LVP bit is programmed to 0, only the High Voltage Programming mode is avail- able and only High Voltage Programming mode can be used to program the device. When using low voltage ICSP, the part must be supplied at 4.5V to 5.5V, if a bulk erase will be executed. This includes reprogramming of the code protect bits from an on-state to off-state. For all other cases of low voltage ICSP, the part may be programmed at the normal oper- ating voltage. This means calibration values, unique user IDs, or user code can be reprogrammed or added. DS30292D-page 134  1998-2013 Microchip Technology Inc.

PIC16F87X 13.0 INSTRUCTION SET SUMMARY All instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- Each PIC16F87X instruction is a 14-bit word, divided gram counter is changed as a result of an instruction. into an OPCODE which specifies the instruction type In this case, the execution takes two instruction cycles and one or more operands which further specify the with the second cycle executed as a NOP. One instruc- operation of the instruction. The PIC16F87X instruction tion cycle consists of four oscillator periods. Thus, for set summary in Table13-2 lists byte-oriented, bit-ori- an oscillator frequency of 4 MHz, the normal instruction ented, and literal and control operations. Table13-1 execution time is 1 s. If a conditional test is true, or the shows the opcode field descriptions. program counter is changed as a result of an instruc- For byte-oriented instructions, 'f' represents a file reg- tion, the instruction execution time is 2 s. ister designator and 'd' represents a destination desig- Table13-2 lists the instructions recognized by the nator. The file register designator specifies which file MPASMTM assembler. register is to be used by the instruction. Figure13-1 shows the general formats that the instruc- The destination designator specifies where the result of tions can have. the operation is to be placed. If 'd' is zero, the result is Note: To maintain upward compatibility with placed in the W register. If 'd' is one, the result is placed future PIC16F87X products, do not use the in the file register specified in the instruction. OPTION and TRIS instructions. For bit-oriented instructions, 'b' represents a bit field All examples use the following format to represent a designator which selects the number of the bit affected hexadecimal number: by the operation, while 'f' represents the address of the file in which the bit is located. 0xhh For literal and control operations, 'k' represents an where h signifies a hexadecimal digit. eight or eleven bit constant or literal value. FIGURE 13-1: GENERAL FORMAT FOR TABLE 13-1: OPCODE FIELD INSTRUCTIONS DESCRIPTIONS Byte-oriented file register operations 13 8 7 6 0 Field Description OPCODE d f (FILE #) f Register file address (0x00 to 0x7F) d = 0 for destination W W Working register (accumulator) d = 1 for destination f f = 7-bit file register address b Bit address within an 8-bit file register k Literal field, constant data or label Bit-oriented file register operations x Don't care location (= 0 or 1). 13 10 9 7 6 0 The assembler will generate code with x = 0. OPCODE b (BIT #) f (FILE #) It is the recommended form of use for compatibility with all Microchip software tools. b = 3-bit bit address f = 7-bit file register address d Destination select; d = 0: store result in W, d = 1: store result in file register f. Literal and control operations Default is d = 1. PC Program Counter General TO Time-out bit 13 8 7 0 PD Power-down bit OPCODE k (literal) k = 8-bit immediate value The instruction set is highly orthogonal and is grouped into three basic categories: CALL and GOTO instructions only • Byte-oriented operations 13 11 10 0 • Bit-oriented operations OPCODE k (literal) • Literal and control operations k = 11-bit immediate value A description of each instruction is available in the PIC® MCU Mid-Range Reference Manual, (DS33023).  1998-2013 Microchip Technology Inc. DS30292D-page 135

PIC16F87X TABLE 13-2: PIC16F87X INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Note: Additional information on the mid-range instruction set is available in the PIC® MCU Mid-Range Family Ref- erence Manual (DS33023). DS30292D-page 136  1998-2013 Microchip Technology Inc.

PIC16F87X 13.1 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [label] ADDLW k Syntax: [label] BCF f,b Operands: 0  k  255 Operands: 0  f  127 0  b  7 Operation: (W) + k  (W) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: The contents of the W register are added to the eight bit literal 'k' Description: Bit 'b' in register 'f' is cleared. and the result is placed in the W register. ADDWF Add W and f BSF Bit Set f Syntax: [label] ADDWF f,d Syntax: [label] BSF f,b Operands: 0  f  127 Operands: 0  f  127 d  0  b  7 Operation: (W) + (f)  (destination) Operation: 1  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit 'b' in register 'f' is set. with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. ANDLW AND Literal with W BTFSS Bit Test f, Skip if Set Syntax: [label] ANDLW k Syntax: [label] BTFSS f,b Operands: 0  k  255 Operands: 0  f  127 0  b < 7 Operation: (W) .AND. (k)  (W) Operation: skip if (f<b>) = 1 Status Affected: Z Status Affected: None Description: The contents of W register are AND’ed with the eight bit literal Description: If bit 'b' in register 'f' is '0', the next 'k'. The result is placed in the W instruction is executed. register. If bit 'b' is '1', then the next instruc- tion is discarded and a NOP is executed instead, making this a 2TCY instruction. ANDWF AND W with f BTFSC Bit Test, Skip if Clear Syntax: [label] ANDWF f,d Syntax: [label] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 d  0  b  7 Operation: (W) .AND. (f)  (destination) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: AND the W register with register Description: If bit 'b' in register 'f' is '1', the next 'f'. If 'd' is 0, the result is stored in instruction is executed. the W register. If 'd' is 1, the result If bit 'b', in register 'f', is '0', the is stored back in register 'f'. next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction.  1998-2013 Microchip Technology Inc. DS30292D-page 137

PIC16F87X CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<4:3>)  PC<12:11> 1  TO 1  PD Status Affected: None Status Affected: TO, PD Description: Call Subroutine. First, return address (PC+1) is pushed onto Description: CLRWDT instruction resets the the stack. The eleven-bit immedi- Watchdog Timer. It also resets ate address is loaded into PC bits the prescaler of the WDT. Status <10:0>. The upper bits of the PC bits TO and PD are set. are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f COMF Complement f Syntax: [label] CLRF f Syntax: [ label ] COMF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register 'f' are Description: The contents of register 'f' are cleared and the Z bit is set. complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. CLRW Clear W DECF Decrement f Syntax: [ label ] CLRW Syntax: [label] DECF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: 00h  (W) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: W register is cleared. Zero bit (Z) Description: Decrement register 'f'. If 'd' is 0, is set. the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. DS30292D-page 138  1998-2013 Microchip Technology Inc.

PIC16F87X DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register 'f' are Description: The contents of register 'f' are decremented. If 'd' is 0, the result incremented. If 'd' is 0, the result is is placed in the W register. If 'd' is placed in the W register. If 'd' is 1, 1, the result is placed back in the result is placed back in register 'f'. register 'f'. If the result is 1, the next instruc- If the result is 1, the next instruc- tion is executed. If the result is 0, tion is executed. If the result is 0, then a NOP is executed instead a NOP is executed instead, making making it a 2TCY instruction. it a 2TCY instruction. GOTO Unconditional Branch IORLW Inclusive OR Literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<4:3>  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the eight bit literal 'k'. The eleven-bit immediate value is The result is placed in the W loaded into PC bits <10:0>. The register. upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two- cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register 'f' are Description: Inclusive OR the W register with incremented. If 'd' is 0, the result register 'f'. If 'd' is 0 the result is is placed in the W register. If 'd' is placed in the W register. If 'd' is 1 1, the result is placed back in the result is placed back in register 'f'. register 'f'.  1998-2013 Microchip Technology Inc. DS30292D-page 139

PIC16F87X MOVF Move f NOP No Operation Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP Operands: 0  f  127 Operands: None d  [0,1] Operation: No operation Operation: (f)  (destination) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected. MOVLW Move Literal to W RETFIE Return from Interrupt Syntax: [ label ] MOVLW k Syntax: [ label ] RETFIE Operands: 0  k  255 Operands: None Operation: k  (W) Operation: TOS  PC, 1  GIE Status Affected: None Status Affected: None Description: The eight bit literal 'k' is loaded into W register. The don’t cares will assemble as 0’s. MOVWF Move W to f RETLW Return with Literal in W Syntax: [ label ] MOVWF f Syntax: [ label ] RETLW k Operands: 0  f  127 Operands: 0  k  255 Operation: (W)  (f) Operation: k  (W); TOS  PC Status Affected: None Status Affected: None Description: Move data from W register to register 'f'. Description: The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. DS30292D-page 140  1998-2013 Microchip Technology Inc.

PIC16F87X RLF Rotate Left f through Carry SLEEP Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP Operands: 0  f  127 Operands: None d  [0,1] Operation: 00h  WDT, Operation: See description below 0  WDT prescaler, 1  TO, Status Affected: C 0  PD Description: The contents of register 'f' are rotated Status Affected: TO, PD one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in Description: The power-down status bit, PD is the W register. If 'd' is 1, the result is cleared. Time-out status bit, TO stored back in register 'f'. is set. Watchdog Timer and its prescaler are cleared. C Register f The processor is put into SLEEP mode with the oscillator stopped. RETURN Return from Subroutine SUBLW Subtract W from Literal Syntax: [ label ] RETURN Syntax: [ label ] SUBLW k Operands: None Operands: 0 k 255 Operation: TOS  PC Operation: k - (W) W) Status Affected: None Status Affected: C, DC, Z Description: Return from subroutine. The stack Description: The W register is subtracted (2’s is POPed and the top of the stack complement method) from the (TOS) is loaded into the program eight-bit literal 'k'. The result is counter. This is a two-cycle placed in the W register. instruction. RRF Rotate Right f through Carry SUBWF Subtract W from f Syntax: [ label ] RRF f,d Syntax: [ label ] SUBWF f,d Operands: 0  f  127 Operands: 0 f 127 d  [0,1] d  [0,1] Operation: See description below Operation: (f) - (W) destination) Status Affected: C Status C, DC, Z Affected: Description: The contents of register 'f' are rotated one bit to the right through Description: Subtract (2’s complement method) the Carry Flag. If 'd' is 0, the result W register from register 'f'. If 'd' is 0, is placed in the W register. If 'd' is the result is stored in the W 1, the result is placed back in register. If 'd' is 1, the result is register 'f'. stored back in register 'f'. C Register f  1998-2013 Microchip Technology Inc. DS30292D-page 141

PIC16F87X SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [label] XORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f<3:0>)  (destination<7:4>), Operation: (W) .XOR. (f) destination) (f<7:4>)  (destination<3:0>) Status Affected: Z Status Affected: None Description: Exclusive OR the contents of the Description: The upper and lower nibbles of W register with register 'f'. If 'd' is register 'f' are exchanged. If 'd' is 0, the result is stored in the W 0, the result is placed in the W register. If 'd' is 1, the result is register. If 'd' is 1, the result is stored back in register 'f'. placed in register 'f'. XORLW Exclusive OR Literal with W Syntax: [label] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit lit- eral 'k'. The result is placed in the W register. DS30292D-page 142  1998-2013 Microchip Technology Inc.

PIC16F87X 14.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to: The PIC® microcontrollers are supported with a full • Edit your source files (either assembly or ‘C’) range of hardware and software development tools: • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (auto- • Integrated Development Environment matically updates all project information) - MPLAB® IDE Software • Debug using: • Assemblers/Compilers/Linkers - source files - MPASMTM Assembler - absolute listing file - MPLAB C17 and MPLAB C18 C Compilers - machine code - MPLINKTM Object Linker/ The ability to use MPLAB IDE with multiple debugging MPLIBTM Object Librarian tools allows users to easily switch from the cost- • Simulators effective simulator to a full-featured emulator with - MPLAB SIM Software Simulator minimal retraining. • Emulators 14.2 MPASM Assembler - MPLAB ICE 2000 In-Circuit Emulator - ICEPIC™ In-Circuit Emulator The MPASM assembler is a full-featured universal • In-Circuit Debugger macro assembler for all PIC® MCUs. - MPLAB ICD for PIC16F87X The MPASM assembler has a command line interface • Device Programmers and a Windows shell. It can be used as a stand-alone - PRO MATE® II Universal Device Programmer application on a Windows 3.x or greater system, or it - PICSTART® Plus Entry-Level Development can be used through MPLAB IDE. The MPASM assem- bler generates relocatable object files for the MPLINK Programmer object linker, Intel® standard HEX files, MAP files to • Low Cost Demonstration Boards detail memory usage and symbol reference, an abso- - PICDEMTM 1 Demonstration Board lute LST file that contains source lines and generated - PICDEM 2 Demonstration Board machine code, and a COD file for debugging. - PICDEM 3 Demonstration Board The MPASM assembler features include: - PICDEM 17 Demonstration Board • Integration into MPLAB IDE projects. - KEELOQ® Demonstration Board • User-defined macros to streamline assembly code. 14.1 MPLAB Integrated Development • Conditional assembly for multi-purpose source Environment Software files. The MPLAB IDE software brings an ease of software • Directives that allow complete control over the development previously unseen in the 8-bit microcon- assembly process. troller market. The MPLAB IDE is a Windows®-based application that contains: 14.3 MPLAB C17 and MPLAB C18 C Compilers • An interface to debugging tools - simulator The MPLAB C17 and MPLAB C18 Code Development - programmer (sold separately) Systems are complete ANSI ‘C’ compilers for - emulator (sold separately) Microchip’s PIC17CXXX and PIC18CXXX family of - in-circuit debugger (sold separately) microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not • A full-featured editor found with other compilers. • A project manager For easier source level debugging, the compilers pro- • Customizable toolbar and key mapping vide symbol information that is compatible with the • A status bar MPLAB IDE memory display. • On-line help  1998-2013 Microchip Technology Inc. DS30292D-page 143

PIC16F87X 14.4 MPLINK Object Linker/ 14.6 MPLAB ICE High Performance MPLIB Object Librarian Universal In-Circuit Emulator with MPLAB IDE The MPLINK object linker combines relocatable objects created by the MPASM assembler and the The MPLAB ICE universal in-circuit emulator is intended MPLAB C17 and MPLAB C18 C compilers. It can also to provide the product development engineer with a link relocatable objects from pre-compiled libraries, complete microcontroller design tool set for PIC MCU using directives from a linker script. microcontrollers (MCUs). Software control of the The MPLIB object librarian is a librarian for pre- MPLAB ICE in-circuit emulator is provided by the compiled code to be used with the MPLINK object MPLAB Integrated Development Environment (IDE), linker. When a routine from a library is called from which allows editing, building, downloading and source another source file, only the modules that contain that debugging from a single environment. routine will be linked in with the application. This allows The MPLAB ICE 2000 is a full-featured emulator sys- large libraries to be used efficiently in many different tem with enhanced trace, trigger and data monitoring applications. The MPLIB object librarian manages the features. Interchangeable processor modules allow the creation and modification of library files. system to be easily reconfigured for emulation of differ- The MPLINK object linker features include: ent processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to • Integration with MPASM assembler and MPLAB support new PIC microcontrollers. C17 and MPLAB C18 C compilers. The MPLAB ICE in-circuit emulator system has been • Allows all memory areas to be defined as sections designed as a real-time emulation system, with to provide link-time flexibility. advanced features that are generally found on more The MPLIB object librarian features include: expensive development tools. The PC platform and • Easier linking because single libraries can be Microsoft® Windows environment were chosen to best included instead of many smaller files. make these features available to you, the end user. • Helps keep code maintainable by grouping 14.7 ICEPIC In-Circuit Emulator related modules together. • Allows libraries to be created and modules to be The ICEPIC low cost, in-circuit emulator is a solution added, listed, replaced, deleted or extracted. for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit One- 14.5 MPLAB SIM Software Simulator Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X The MPLAB SIM software simulator allows code devel- or PIC16CXXX products through the use of inter- opment in a PC-hosted environment by simulating the changeable personality modules, or daughter boards. PIC MCU series microcontrollers on an instruction The emulator is capable of emulating without target level. On any given instruction, the data areas can be application circuitry being present. examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debug- ging using the MPLAB C17 and the MPLAB C18 C com- pilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. DS30292D-page 144  1998-2013 Microchip Technology Inc.

PIC16F87X 14.8 MPLAB ICD In-Circuit Debugger 14.11 PICDEM 1 Low Cost PIC MCU Demonstration Board Microchip's In-Circuit Debugger, MPLAB ICD, is a pow- erful, low cost, run-time development tool. This tool is The PICDEM 1 demonstration board is a simple board based on the FLASH PIC16F87X and can be used to which demonstrates the capabilities of several of develop for this and other PIC microcontrollers from the Microchip’s microcontrollers. The microcontrollers sup- PIC16CXXX family. The MPLAB ICD utilizes the in-cir- ported are: PIC16C5X (PIC16C54 to PIC16C58A), cuit debugging capability built into the PIC16F87X. This PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, feature, along with Microchip's In-Circuit Serial PIC17C42, PIC17C43 and PIC17C44. All necessary ProgrammingTM protocol, offers cost-effective in-circuit hardware and software is included to run basic demo FLASH debugging from the graphical user interface of programs. The user can program the sample microcon- the MPLAB Integrated Development Environment. This trollers provided with the PICDEM 1 demonstration enables a designer to develop and debug source code board on a PROMATE II device programmer, or a by watching variables, single-stepping and setting PICSTART Plus development programmer, and easily break points. Running at full speed enables testing test firmware. The user can also connect the hardware in real-time. PICDEM1 demonstration board to the MPLAB ICE in- circuit emulator and download the firmware to the emu- 14.9 PRO MATE II Universal Device lator for testing. A prototype area is available for the Programmer user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features The PRO MATE II universal device programmer is a include an RS-232 interface, a potentiometer for simu- full-featured programmer, capable of operating in lated analog input, push button switches and eight stand-alone mode, as well as PC-hosted mode. The LEDs connected to PORTB. PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has program- 14.12 PICDEM 2 Low Cost PIC16CXX mable VDD and VPP supplies, which allow it to verify Demonstration Board programmed memory at VDD min and VDD max for max- imum reliability. It has an LCD display for instructions The PICDEM 2 demonstration board is a simple dem- and error messages, keys to enter commands and a onstration board that supports the PIC16C62, modular detachable socket assembly to support various PIC16C64, PIC16C65, PIC16C73 and PIC16C74 package types. In stand-alone mode, the PRO MATE II microcontrollers. All the necessary hardware and soft- device programmer can read, verify, or program PIC ware is included to run the basic demonstration pro- devices. It can also set code protection in this mode. grams. The user can program the sample microcontrollers provided with the PICDEM2 demon- 14.10 PICSTART Plus Entry Level stration board on a PRO MATE II device programmer, Development Programmer or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emula- The PICSTART Plus development programmer is an tor may also be used with the PICDEM 2 demonstration easy-to-use, low cost, prototype programmer. It con- board to test firmware. A prototype area has been pro- nects to the PC via a COM (RS-232) port. MPLAB vided to the user for adding additional hardware and Integrated Development Environment software makes connecting it to the microcontroller socket(s). Some of using the programmer simple and efficient. the features include a RS-232 interface, push button The PICSTART Plus development programmer sup- switches, a potentiometer for simulated analog input, a ports all PIC devices with up to 40 pins. Larger pin serial EEPROM to demonstrate usage of the I2CTM bus count devices, such as the PIC16C92X and and separate headers for connection to an LCD PIC17C76X, may be supported with an adapter socket. module and a keypad. The PICSTART Plus development programmer is CE compliant.  1998-2013 Microchip Technology Inc. DS30292D-page 145

PIC16F87X 14.13 PICDEM 3 Low Cost PIC16CXXX 14.14 PICDEM 17 Demonstration Board Demonstration Board The PICDEM 17 demonstration board is an evaluation The PICDEM 3 demonstration board is a simple dem- board that demonstrates the capabilities of several onstration board that supports the PIC16C923 and Microchip microcontrollers, including PIC17C752, PIC16C924 in the PLCC package. It will also support PIC17C756A, PIC17C762 and PIC17C766. All neces- future 44-pin PLCC microcontrollers with an LCD Mod- sary hardware is included to run basic demo programs, ule. All the necessary hardware and software is which are supplied on a 3.5-inch disk. A programmed included to run the basic demonstration programs. The sample is included and the user may erase it and user can program the sample microcontrollers pro- program it with the other sample programs using the vided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or the PICSTART PRO MATE II device programmer, or a PICSTART Plus Plus development programmer, and easily debug and development programmer with an adapter socket, and test the sample code. In addition, the PICDEM17 dem- easily test firmware. The MPLAB ICE in-circuit emula- onstration board supports downloading of programs to tor may also be used with the PICDEM 3 demonstration and executing out of external FLASH memory on board. board to test firmware. A prototype area has been pro- The PICDEM 17 demonstration board is also usable vided to the user for adding hardware and connecting it with the MPLAB ICE in-circuit emulator, or the to the microcontroller socket(s). Some of the features PICMASTER emulator and all of the sample programs include a RS-232 interface, push button switches, a can be run and modified using either emulator. Addition- potentiometer for simulated analog input, a thermistor ally, a generous prototype area is available for user and separate headers for connection to an external hardware. LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 14.15 KEELOQ Evaluation and commons and 12 segments, that is capable of display- Programming Tools ing time, temperature and day of the week. The KEELOQ evaluation and programming tools support PICDEM 3 demonstration board provides an additional Microchip’s HCS Secure Data Products. The HCS eval- RS-232 interface and Windows software for showing uation kit includes a LCD display to show changing the demultiplexed LCD signals on a PC. A simple serial codes, a decoder to decode transmissions and a pro- interface allows the user to construct a hardware gramming interface to program test transmitters. demultiplexer for the LCD signals. DS30292D-page 146  1998-2013 Microchip Technology Inc.

PIC16F87X TABLE 14-1: DEVELOPMENT TOOLS FROM MICROCHIP 0152PCM  7. 7 6, XXXFRCM     4, 7 7 3, 7 XXXSCH     72, 5, 6 XXC39 4, //XXXXCC4522   3, 6 6 2, 6 C 2XXC81CIP        6 1 C PI h XX7C71CIP        wit 1) 0 0 4 X4C71CIP        16 V D er ( XX9C61CIP        gg u b e D XX8F61CIP       cuit Cir n- D I X8C61CIP        C ® I B A L XX7C61CIP       MP e h e t s X7C61CIP     *   † † o u w t o h X26F61CIP   ** ** ** on n o ati m XXXC61CIP        or nf or i X6C61CIP     *   † om f c p. hi c X5C61CIP        cro mi ww.e. X0X0X0C4211CCIPIP ®MPLAB IntegratedDevelopment Environment ®MPLAB C17 C Compiler ®MPLAB C18 C Compiler TMMPASM Assembler/ TMMPLINKObject Linker ®MPLAB ICE In-Circuit Emulator TMICEPIC In-Circuit Emulator ®MPLAB ICD In-Circuit Debugger ®PICSTART Plus Entry LevelDevelopment Programmer ®PRO MATE II Universal Device Programmer TMPICDEM 1 Demonstration Board TMPICDEM 2 Demonstration Board TMPICDEM 3 Demonstration Board TMPICDEM 14A Demonstration Board TMPICDEM 17 Demonstration Board ® KLEvaluation KitEEOQ ®KL Transponder KitEEOQ TMmicroID Programmer’s Kit TM125 kHz microID Developer’s Kit TM125 kHz Anticollision microID Developer’s Kit 13.56 MHz Anticollision TMmicroID Developer’s Kit MCP2510 CAN Developer’s Kit Contact the Microchip Technology Inc. web site at wContact Microchip Technology Inc. for availability datDevelopment tool is available on select devices. slooT erawtfoS srotalumE reggubeD sremmargorP stiK lavE dna sdraoB omeD ***†  1998-2013 Microchip Technology Inc. DS30292D-page 147

PIC16F87X NOTES: DS30292D-page 148  1998-2013 Microchip Technology Inc.

PIC16F87X 15.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias.................................................................................................................-55 to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4).......................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ........................................................................................................... -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2)................................................................................................0 to +14V Voltage on RA4 with respect to Vss.................................................................................................................0 to +8.5V Total power dissipation (Note 1)..............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)20mA Output clamp current, IOK (VO < 0 or VO > VDD)20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk byPORTA, PORTB, and PORTE (combined) (Note 3)...................................................200mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200mA Maximum current sunk by PORTC and PORTD (combined) (Note 3).................................................................200mA Maximum current sourced by PORTC and PORTD (combined) (Note 3)............................................................200mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD - VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to VSS. 3: PORTD and PORTE are not implemented on PIC16F873/876 devices. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  1998-2013 Microchip Technology Inc. DS30292D-page 149

PIC16F87X FIGURE 15-1: PIC16F87X-20 VOLTAGE-FREQUENCY GRAPH (COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ONLY) 6.0 V 5.5 V 5.0 V 4.5 V e g a 4.0 V t l o 3.5 V V 3.0 V 2.5 V 2.0 V 16 MHz 20 MHz Frequency FIGURE 15-2: PIC16LF87X-04 VOLTAGE-FREQUENCY GRAPH (COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ONLY) 6.0 V 5.5 V 5.0 V 4.5 V e g 4.0 V a t l o 3.5 V V 3.0 V 2.5 V 2.0 V 4 MHz 10 MHz Frequency FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application. Note 2: FMAX has a maximum frequency of 10MHz. DS30292D-page 150  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 15-3: PIC16F87X-04 VOLTAGE-FREQUENCY GRAPH (ALL TEMPERATURE RANGES) 6.0 V 5.5 V 5.0 V PIC16F87X-04 4.5 V e g a 4.0 V t l o 3.5 V V 3.0 V 2.5 V 2.0 V 4 MHz Frequency FIGURE 15-4: PIC16F87X-10 VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE RANGE ONLY) 6.0 V 5.5 V 5.0 V PIC16F87X-10 4.5 V e g a 4.0 V t l o 3.5 V V 3.0 V 2.5 V 2.0 V 10 MHz Frequency  1998-2013 Microchip Technology Inc. DS30292D-page 151

PIC16F87X 15.1 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) PIC16LF873/874/876/877-04 Operating temperature -40°C  TA  +85°C for industrial (Commercial, Industrial) 0°C  TA  +70°C for commercial PIC16F873/874/876/877-04 Standard Operating Conditions (unless otherwise stated) PIC16F873/874/876/877-20 Operating temperature -40°C  TA  +85°C for industrial (Commercial, Industrial) 0°C  TA  +70°C for commercial Param Symbol Characteristic/ Min Typ† Max Units Conditions No. Device VDD Supply Voltage D001 16LF87X 2.0 — 5.5 V LP, XT, RC osc configuration (DC to 4 MHz) D001 16F87X 4.0 — 5.5 V LP, XT, RC osc configuration D001A 4.5 5.5 V HS osc configuration VBOR 5.5 V BOR enabled, FMAX = 14 MHz(7) D002 VDR RAM Data Retention — 1.5 — V Voltage(1) D003 VPOR VDD Start Voltage to — VSS — V See section on Power-on Reset for ensure internal Power-on details Reset signal D004 SVDD VDD Rise Rate to ensure 0.05 — — V/ms See section on Power-on Reset for internal Power-on Reset details signal D005 VBOR Brown-out Reset 3.7 4.0 4.35 V BODEN bit in configuration word Voltage enabled Legend: Rows with standard voltage device data only are shaded for improved readability. † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. DS30292D-page 152  1998-2013 Microchip Technology Inc.

PIC16F87X 15.1 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF873/874/876/877-04 Operating temperature -40°C  TA  +85°C for industrial (Commercial, Industrial) 0°C  TA  +70°C for commercial PIC16F873/874/876/877-04 Standard Operating Conditions (unless otherwise stated) PIC16F873/874/876/877-20 Operating temperature -40°C  TA  +85°C for industrial (Commercial, Industrial) 0°C  TA  +70°C for commercial Param Symbol Characteristic/ Min Typ† Max Units Conditions No. Device IDD Supply Current(2,5) D010 16LF87X — 0.6 2.0 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V D010 16F87X — 1.6 4 mA RC osc configurations FOSC = 4 MHz, VDD = 5.5V D010A 16LF87X — 20 35 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D013 16F87X — 7 15 mA HS osc configuration, FOSC = 20MHz, VDD = 5.5V D015 IBOR Brown-out — 85 200 A BOR enabled, VDD = 5.0V Reset Current(6) Legend: Rows with standard voltage device data only are shaded for improved readability. † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.  1998-2013 Microchip Technology Inc. DS30292D-page 153

PIC16F87X 15.1 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF873/874/876/877-04 Operating temperature -40°C  TA  +85°C for industrial (Commercial, Industrial) 0°C  TA  +70°C for commercial PIC16F873/874/876/877-04 Standard Operating Conditions (unless otherwise stated) PIC16F873/874/876/877-20 Operating temperature -40°C  TA  +85°C for industrial (Commercial, Industrial) 0°C  TA  +70°C for commercial Param Symbol Characteristic/ Min Typ† Max Units Conditions No. Device IPD Power-down Current(3,5) D020 16LF87X — 7.5 30 A VDD = 3.0V, WDT enabled, -40C to +85C D020 16F87X — 10.5 42 A VDD = 4.0V, WDT enabled, -40C to +85C D021 16LF87X — 0.9 5 A VDD = 3.0V, WDT enabled, 0C to +70C D021 16F87X — 1.5 16 A VDD = 4.0V, WDT enabled, -40C to +85C D021A 16LF87X 0.9 5 A VDD = 3.0V, WDT enabled, -40C to +85C D021A 16F87X 1.5 19 A VDD = 4.0V, WDT enabled, -40C to +85C D023 IBOR Brown-out — 85 200 A BOR enabled, VDD = 5.0V Reset Current(6) Legend: Rows with standard voltage device data only are shaded for improved readability. † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. DS30292D-page 154  1998-2013 Microchip Technology Inc.

PIC16F87X 15.2 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC specification (Section15.1) Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O ports D030 with TTL buffer Vss — 0.15VDD V For entire VDD range D030A Vss — 0.8V V 4.5V  VDD 5.5V D031 with Schmitt Trigger buffer Vss — 0.2VDD V D032 MCLR, OSC1 (in RC mode) VSS — 0.2VDD V D033 OSC1 (in XT, HS and LP) VSS — 0.3VDD V (Note 1) Ports RC3 and RC4 — D034 with Schmitt Trigger buffer Vss — 0.3VDD V For entire VDD range D034A with SMBus -0.5 — 0.6 V for VDD = 4.5 to 5.5V VIH Input High Voltage I/O ports — D040 with TTL buffer 2.0 — VDD V 4.5V  VDD 5.5V D040A 0.25VDD — VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD — VDD V For entire VDD range D042 MCLR 0.8VDD — VDD V D042A OSC1 (XT, HS and LP) 0.7VDD — VDD V (Note 1) D043 OSC1 (in RC mode) 0.9VDD — VDD V Ports RC3 and RC4 D044 with Schmitt Trigger buffer 0.7VDD — VDD V For entire VDD range D044A with SMBus 1.4 — 5.5 V for VDD = 4.5 to 5.5V D070 IPURB PORTB Weak Pull-up Current 50 250 400 A VDD = 5V, VPIN = VSS, -40°C TO +85°C IIL Input Leakage Current(2, 3) D060 I/O ports — — 1 A Vss VPIN VDD, Pin at hi-impedance D061 MCLR, RA4/T0CKI — — 5 A Vss VPIN VDD D063 OSC1 — — 5 A Vss VPIN VDD, XT, HS and LP osc configuration * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F87X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  1998-2013 Microchip Technology Inc. DS30292D-page 155

PIC16F87X 15.2 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC specification (Section15.1) Param Sym Characteristic Min Typ† Max Units Conditions No. VOL Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKOUT (RC osc config) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C VOH Output High Voltage D090 I/O ports(3) VDD - 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 — — V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C D150* VOD Open-Drain High Voltage — — 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 (RC mode) — — 50 pF D102 CB SCL, SDA (I2C mode) — — 400 pF Data EEPROM Memory D120 ED Endurance 100K — — E/W 25C at 5V D121 VDRW VDD for read/write VMIN — 5.5 V Using EECON to read/write VMIN = min. operating voltage D122 TDEW Erase/write cycle time — 4 8 ms Program FLASH Memory D130 EP Endurance 1000 — — E/W 25C at 5V D131 VPR VDD for read VMIN — 5.5 V VMIN = min operating voltage D132A VDD for erase/write VMIN — 5.5 V Using EECON to read/write, VMIN = min. operating voltage D133 TPEW Erase/Write cycle time — 4 8 ms * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F87X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30292D-page 156  1998-2013 Microchip Technology Inc.

PIC16F87X 15.3 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) PIC16F873/874/876/877-04 Standard Operating Conditions (unless otherwise stated) PIC16F873/874/876/877-20 Operating temperature -40°C  TA  +125°C (Extended) Param Symbol Characteristic/ Min Typ† Max Units Conditions No. Device VDD Supply Voltage D001 4.0 — 5.5 V LP, XT, RC osc configuration D001A 4.5 5.5 V HS osc configuration D001A VBOR 5.5 V BOR enabled, FMAX = 10 MHz(7) D002 VDR RAM Data Retention — 1.5 — V Voltage(1) D003 VPOR VDD Start Voltage to — VSS — V See section on Power-on Reset for ensure internal Power-on details Reset signal D004 SVDD VDD Rise Rate to ensure 0.05 — — V/ms See section on Power-on Reset for internal Power-on Reset details signal D005 VBOR Brown-out Reset 3.7 4.0 4.35 V BODEN bit in configuration word Voltage enabled † Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.  1998-2013 Microchip Technology Inc. DS30292D-page 157

PIC16F87X 15.3 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) (Continued) PIC16F873/874/876/877-04 Standard Operating Conditions (unless otherwise stated) PIC16F873/874/876/877-20 Operating temperature -40°C  TA  +125°C (Extended) Param Symbol Characteristic/ Min Typ† Max Units Conditions No. Device IDD Supply Current(2,5) D010 — 1.6 4 mA RC osc configurations FOSC = 4 MHz, VDD = 5.5V D013 — 7 15 mA HS osc configuration, FOSC = 10MHz, VDD = 5.5V D015 IBOR Brown-out — 85 200 A BOR enabled, VDD = 5.0V Reset Current(6) IPD Power-down Current(3,5) D020A 10.5 60 A VDD = 4.0V, WDT enabled D021B 1.5 30 A VDD = 4.0V, WDT disabled D023 IBOR Brown-out — 85 200 A BOR enabled, VDD = 5.0V Reset Current(6) † Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. DS30292D-page 158  1998-2013 Microchip Technology Inc.

PIC16F87X 15.4 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C DC CHARACTERISTICS Operating voltage VDD range as described in DC specification (Section15.1) Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O ports D030 with TTL buffer Vss — 0.15VDD V For entire VDD range D030A Vss — 0.8V V 4.5V  VDD 5.5V D031 with Schmitt Trigger buffer Vss — 0.2VDD V D032 MCLR, OSC1 (in RC mode) VSS — 0.2VDD V D033 OSC1 (in XT, HS and LP) VSS — 0.3VDD V (Note 1) Ports RC3 and RC4 D034 with Schmitt Trigger buffer Vss — 0.3VDD V For entire VDD range D034A with SMBus -0.5 — 0.6 V for VDD = 4.5 to 5.5V VIH Input High Voltage I/O ports — D040 with TTL buffer 2.0 — VDD V 4.5V  VDD 5.5V D040A 0.25VDD — VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD — VDD V For entire VDD range D042 MCLR 0.8VDD — VDD V D042A OSC1 (XT, HS and LP) 0.7VDD — VDD V (Note 1) D043 OSC1 (in RC mode) 0.9VDD — VDD V Ports RC3 and RC4 D044 with Schmitt Trigger buffer 0.7VDD — VDD V For entire VDD range D044A with SMBus 1.4 — 5.5 V for VDD = 4.5 to 5.5V D070A IPURB PORTB Weak Pull-up Current 50 250 400 A VDD = 5V, VPIN = VSS, IIL Input Leakage Current(2, 3) D060 I/O ports - - 1 A Vss VPIN VDD, Pin at hi-impedance D061 MCLR, RA4/T0CKI - - 5 A Vss VPIN VDD D063 OSC1 - - 5 A Vss VPIN VDD, XT, HS and LP osc configuration * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F87X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  1998-2013 Microchip Technology Inc. DS30292D-page 159

PIC16F87X 15.4 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C DC CHARACTERISTICS Operating voltage VDD range as described in DC specification (Section15.1) Param Sym Characteristic Min Typ† Max Units Conditions No. VOL Output Low Voltage D080A I/O ports — — 0.6 V IOL = 7.0 mA, VDD = 4.5V D083A OSC2/CLKOUT (RC osc config) — — 0.6 V IOL = 1.2 mA, VDD = 4.5V VOH Output High Voltage D090A I/O ports(3) VDD - 0.7 — — V IOH = -2.5 mA, VDD = 4.5V D092A OSC2/CLKOUT (RC osc config) VDD - 0.7 — — V IOH = -1.0 mA, VDD = 4.5V D150* VOD Open Drain High Voltage — — 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 (RC mode) — — 50 pF D102 CB SCL, SDA (I2C mode) — — 400 pF Data EEPROM Memory D120 ED Endurance 100K — — E/W 25C at 5V D121 VDRW VDD for read/write VMIN — 5.5 V Using EECON to read/write VMIN = min. operating voltage D122 TDEW Erase/write cycle time — 4 8 ms Program FLASH Memory D130 EP Endurance 1000 — — E/W 25C at 5V D131 VPR VDD for read VMIN — 5.5 V VMIN = min operating voltage D132A VDD for erase/write VMIN — 5.5 V Using EECON to read/write, VMIN = min. operating voltage D133 TPEW Erase/Write cycle time — 4 8 ms * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F87X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30292D-page 160  1998-2013 Microchip Technology Inc.

PIC16F87X 15.5 Timing Parameter Symbology The timing parameter symbols have been created fol- lowing one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 15-5: LOAD CONDITIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464 CL = 50pF for all pins except OSC2, but including PORTD and PORTE outputs as ports, 15pF for OSC2 output Note: PORTD and PORTE are not implemented on PIC16F873/876 devices.  1998-2013 Microchip Technology Inc. DS30292D-page 161

PIC16F87X FIGURE 15-6: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. FOSC External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 10 MHz HS osc mode (-10) 4 — 20 MHz HS osc mode (-20) 5 — 200 kHz LP osc mode 1 TOSC External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — — ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode 2 TCY Instruction Cycle Time 200 TCY DC ns TCY = 4/FOSC (Note 1) 3 TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — s LP oscillator 15 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. DS30292D-page 162  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 15-7: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 18 12 14 19 16 I/O Pin (Input) 17 15 I/O Pin Old Value New Value (Output) 20, 21 Note: Refer to Figure15-5 for load conditions. TABLE 15-2: CLKOUT AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns (Note 1) 11* TosH2ck OSC1 to CLKOUT — 75 200 ns (Note 1) H 12* TckR CLKOUT rise time — 35 100 ns (Note 1) 13* TckF CLKOUT fall time — 35 100 ns (Note 1) 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns (Note 1) 15* TioV2ckH Port in valid before CLKOUT  TOSC + 200 — — ns (Note 1) 16* TckH2ioI Port in hold after CLKOUT  0 — — ns (Note 1) 17* TosH2ioV OSC1 (Q1 cycle) to — 100 255 ns Port out valid 18* TosH2ioI OSC1 (Q2 cycle) to Standard (F) 100 — — ns Port input invalid (I/O in Extended (LF) 200 — — ns hold time) 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time Standard (F) — 10 40 ns Extended (LF) — — 145 ns 21* TioF Port output fall time Standard (F) — 10 40 ns Extended (LF) — — 145 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.  1998-2013 Microchip Technology Inc. DS30292D-page 163

PIC16F87X FIGURE 15-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure15-5 for load conditions. FIGURE 15-9: BROWN-OUT RESET TIMING VDD VBOR 35 TABLE 15-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Symbol Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +85°C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +85°C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C 34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 s or Watchdog Timer Reset 35 TBOR Brown-out Reset pulse width 100 — — s VDD  VBOR (D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30292D-page 164  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 15-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure15-5 for load conditions. TABLE 15-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4,..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, Standard(F) 15 — — ns parameter 47 Prescaler = 2,4,8 Extended(LF) 25 — — ns Asynchronous Standard(F) 30 — — ns Extended(LF) 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, Standard(F) 15 — — ns parameter 47 Prescaler = 2,4,8 Extended(LF) 25 — — ns Asynchronous Standard(F) 30 — — ns Extended(LF) 50 — — ns 47* Tt1P T1CKI input Synchronous Standard(F) Greater of: — — ns N = prescale value period 30 OR TCY + 40 (1, 2, 4, 8) N Extended(LF) Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous Standard(F) 60 — — ns Extended(LF) 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2TOSC — 7TOSC — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1998-2013 Microchip Technology Inc. DS30292D-page 165

PIC16F87X FIGURE 15-11: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure15-5 for load conditions. TABLE 15-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input low time Standard(F) 10 — — ns With Prescaler Extended(LF) 20 — — ns 51* TccH CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input high time Standard(F) 10 — — ns With Prescaler Extended(LF) 20 — — ns 52* TccP CCP1 and CCP2 input period 3TCY + 40 — — ns N = prescale N value (1, 4 or 16) 53* TccR CCP1 and CCP2 output rise time Standard(F) — 10 25 ns Extended(LF) — 25 50 ns 54* TccF CCP1 and CCP2 output fall time Standard(F) — 10 25 ns Extended(LF) — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30292D-page 166  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 15-12: PARALLEL SLAVE PORT TIMING (PIC16F874/877 ONLY) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure15-5 for load conditions. TABLE 15-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874/877 ONLY) Parameter Symbol Characteristic Min Typ† Max Units Conditions No. 62 TdtV2wrH Data in valid before WR or CS (setup time) 20 — — ns 25 — — ns Extended Range Only 63* TwrH2dtI WR or CS to data–in invalid (hold time) Standard(F) 20 — — ns Extended(LF) 35 — — ns 64 TrdL2dtV RD and CS to data–out valid — — 80 ns — — 90 ns Extended Range Only 65 TrdH2dtI RD or CS to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1998-2013 Microchip Technology Inc. DS30292D-page 167

PIC16F87X FIGURE 15-13: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure15-5 for load conditions. FIGURE 15-14: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Note: Refer to Figure15-5 for load conditions. DS30292D-page 168  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 15-15: SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 77 SSDDII MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure15-5 for load conditions. FIGURE 15-16: SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 77 SSDDII MSb IN BIT6 - - - -1 LSb IN 74 Note: Refer to Figure15-5 for load conditions.  1998-2013 Microchip Technology Inc. DS30292D-page 169

PIC16F87X TABLE 15-7: SPI MODE REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 70* TssL2scH, SS to SCK or SCK input Tcy — — ns TssL2scL 71* TscH SCK input high time (Slave mode) TCY + 20 — — ns 72* TscL SCK input low time (Slave mode) TCY + 20 — — ns 73* TdiV2scH, Setup time of SDI data input to SCK edge 100 — — ns TdiV2scL 74* TscH2diL, Hold time of SDI data input to SCK edge 100 — — ns TscL2diL 75* TdoR SDO data output rise time Standard(F) — 10 25 ns Extended(LF) — 25 50 ns 76* TdoF SDO data output fall time — 10 25 ns 77* TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78* TscR SCK output rise time (Master mode) Standard(F) — 10 25 ns Extended(LF) — 25 50 ns 79* TscF SCK output fall time (Master mode) — 10 25 ns 80* TscH2doV, SDO data output valid after SCK Standard(F) — — 50 ns TscL2doV edge Extended(LF) — — 145 81* TdoV2scH, SDO data output setup to SCK edge Tcy — — ns TdoV2scL 82* TssL2doV SDO data output valid after SS edge — — 50 ns 83* TscH2ssH, SS after SCK edge 1.5TCY + 40 — — ns TscL2ssH * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 15-17: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure15-5 for load conditions. DS30292D-page 170  1998-2013 Microchip Technology Inc.

PIC16F87X TABLE 15-8: I2C BUS START/STOP BITS REQUIREMENTS Parameter Symbol Characteristic Min Typ Max Units Conditions No. 90 Tsu:sta START condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — START condition 91 Thd:sta START condition 100 kHz mode 4000 — — ns After this period, the first clock Hold time 400 kHz mode 600 — — pulse is generated 92 Tsu:sto STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 Thd:sto STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — FIGURE 15-18: I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure15-5 for load conditions.  1998-2013 Microchip Technology Inc. DS30292D-page 171

PIC16F87X TABLE 15-9: I2C BUS DATA REQUIREMENTS Param Sym Characteristic Min Max Units Conditions No. 100 Thigh Clock high time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP Module 0.5TCY — 101 Tlow Clock low time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP Module 0.5TCY — 102 Tr SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 103 Tf SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 90 Tsu:sta START condition 100 kHz mode 4.7 — s Only relevant for Repeated setup time 400 kHz mode 0.6 — s START condition 91 Thd:sta START condition hold 100 kHz mode 4.0 — s After this period, the first clock time 400 kHz mode 0.6 — s pulse is generated 106 Thd:dat Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 Tsu:dat Data input setup time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 Tsu:sto STOP condition setup 100 kHz mode 4.7 — s time 400 kHz mode 0.6 — s 109 Taa Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns 110 Tbuf Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start Cb Bus capacitive loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement that Tsu:dat250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+ Tsu:dat=1000+250=1250ns (according to the standard mode I2C bus specification) before the SCL line is released. DS30292D-page 172  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 15-19: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK 121 Pin 121 RC7/RX/DT Pin 120 122 Note: Refer to Figure15-5 for load conditions. TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & Standard(F) SLAVE) — — 80 ns Clock high to data out valid Extended(LF) — — 100 ns 121 Tckrf Clock out rise time and fall time Standard(F) — — 45 ns (Master mode) Extended(LF) — — 50 ns 122 Tdtrf Data out rise time and fall time Standard(F) — — 45 ns Extended(LF) — — 50 ns † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 15-20: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure15-5 for load conditions. TABLE 15-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 125 TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK  (DT setup 15 — — ns time) 126 TckL2dtl Data hold after CK  (DT hold time) 15 — — ns † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.  1998-2013 Microchip Technology Inc. DS30292D-page 173

PIC16F87X TABLE 15-12: PIC16F87X-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16F87X-10 (EXTENDED) PIC16F87X-20 (COMMERCIAL, INDUSTRIAL) PIC16LF87X-04 (COMMERCIAL, INDUSTRIAL) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 10-bits bit VREF = VDD = 5.12V, VSS  VAIN  VREF A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A06 EOFF Offset error — — < ± 2 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A07 EGN Gain error — — < ± 1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A10 — Monotonicity(3) — guaranteed — — VSS  VAIN  VREF A20 VREF Reference voltage (VREF+ - VREF-) 2.0 — VDD + 0.3 V Absolute minimum electrical spec. To ensure 10-bit accuracy. A21 VREF+ Reference voltage High AVDD - 2.5V AVDD + 0.3V V A22 VREF- Reference voltage low AVSS - 0.3V VREF+ - 2.0V V A25 VAIN Analog input voltage VSS - 0.3V — VREF + 0.3V V A30 ZAIN Recommended impedance of — — 10.0 k analog voltage source A40 IAD A/D conversion Standard — 220 — A Average current consumption current (VDD) Extended — 90 — A when A/D is on (Note 1) A50 IREF VREF input current (Note 2) 10 — 1000 A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section11.1. — — 10 A During A/D Conversion cycle * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. DS30292D-page 174  1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 15-21: A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 132 A/D DATA 9 8 7   2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-13: A/D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D clock period Standard(F) 1.6 — — s TOSC based, VREF  3.0V Extended(LF) 3.0 — — s TOSC based, VREF  2.0V Standard(F) 2.0 4.0 6.0 s A/D RC mode Extended(LF) 3.0 6.0 9.0 s A/D RC mode 131 TCNV Conversion time (not including S/H time) — 12 TAD (Note 1) 132 TACQ Acquisition time (Note 2) 40 — s 10* — — s The minimum time is the amplifier settling time. This may be used if the "new" input volt- age has not changed by more than 1 LSb (i.e., 20.0mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section11.1 for minimum conditions.  1998-2013 Microchip Technology Inc. DS30292D-page 175

PIC16F87X NOTES: DS30292D-page 176  1998-2013 Microchip Technology Inc.

PIC16F87X 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented is outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at 25C. 'max' or 'min' represents (mean+3) or (mean-3) respectively, where  is standard deviation, over the whole temperature range. FIGURE 16-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) 7 Typical: statistical mean @ 25°C 6 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 5 5.5V 4 mA) 5.0V (DD 4.5V I 3 4.0V 2 3.5V 3.0V 1 2.5V 2.0V 0 4 6 8 10 12 14 16 18 20 FOSC (MHz) FIGURE 16-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) 8 Typical: statistical mean @ 25°C 7 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 6 5.5V 5 5.0V A) (mDD 4 4.5V I 4.0V 3 3.5V 2 3.0V 1 2.5V 2.0V 0 4 6 8 10 12 14 16 18 20 FOSC (MHz)  1998-2013 Microchip Technology Inc. DS30292D-page 177

PIC16F87X FIGURE 16-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.6 Typical: statistical mean @ 25°C 1.4 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 5.5V 1.2 5.0V 1.0 4.5V A) (mD 0.8 4.0V D I 3.5V 0.6 3.0V 0.4 2.5V 2.0V 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 16-4: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 2.0 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 5.5V 1.4 5.0V 1.2 A) 4.5V m 1.0 (DD 4.0V I 0.8 3.5V 0.6 3.0V 2.5V 0.4 2.0V 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) DS30292D-page 178 © 1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 16-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 90 Typical: statistical mean @ 25°C 80 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 5.5V 70 5.0V 60 4.5V 50 A) 4.0V u (D D I 40 3.5V 3.0V 30 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 16-6: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 120 110 Typical: statistical mean @ 25°C 5.5V Maximum: mean + 3s (-40°C to 125°C) 100 Minimum: mean – 3s (-40°C to 125°C) 5.0V 90 80 4.5V 70 A) 4.0V (uD 60 D I 3.5V 50 3.0V 40 2.5V 30 2.0V 20 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz)  1998-2013 Microchip Technology Inc. DS30292D-page 179

PIC16F87X FIGURE 16-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20pF, 25C) 4.0 3.3k 3.5 3.0 5.1k 2.5 z) H M q ( 2.0 e Fr 10k 1.5 1.0 0.5 100k 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100pF, 25C) 2.0 1.8 1.6 3.3k 1.4 1.2 z) MH 5.1k q ( 1.0 e Fr 0.8 0.6 10k 0.4 0.2 100k 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30292D-page 180 © 1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 16-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300pF, 25C) 1.0 0.9 0.8 3.3k 0.7 0.6 Hz) 5.1k M q ( 0.5 e Fr 0.4 0.3 10k 0.2 0.1 100k 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-10: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 100.00 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Max (125C) 10.00 Max (85C) A)  (D 1.00 P I 0.10 Typ (25C) 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  1998-2013 Microchip Technology Inc. DS30292D-page 181

PIC16F87X FIGURE 16-11: IBOR vs. VDD OVER TEMPERATURE 1.2 Note: Device current in RESET 1.0 depends on oscillator mode, Typical: statistical mean @ 25°C frequency and circuit. Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 0.8 A) Max Reset m (R 0.6 O B I Indeterminate Typ Reset (25C) State 0.4 Device in Sleep Device in Reset 0.2 Max Sleep Typ Sleep (25C) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-12: TYPICAL AND MAXIMUMITMR1 vs. VDD OVER TEMPERATURE (-10C TO 70C, TIMER1 WITH OSCILLATOR, XTAL=32 kHZ, C1 AND C2=50pF) 90 Typical: statistical mean @ 25°C 80 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 70 60 A) 50 u 1 ( R M T 40 I Max 30 Typ (25C) 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30292D-page 182 © 1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 16-13: TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE 14 Typical: statistical mean @ 25°C 12 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10 Max (85C) 8 A) u Typ (25C) (T D W I 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO 125C) 60 Typical: statistical mean @ 25°C 50 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 40 s) m d ( Max (125C) o eri 30 P T D W 20 Typ (25C) 10 Min (-40C) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  1998-2013 Microchip Technology Inc. DS30292D-page 183

PIC16F87X FIGURE 16-15: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40C TO 125C) 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) 40 Minimum: mean – 3s (-40°C to 125°C) 125C 35 85C s) 30 m d ( o Peri 25 25C T D W 20 -40C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=5V, -40C TO 125C) 5.0 Max (-40C) 4.5 Typ (25C) 4.0 V) (H 3.5 O V Min (125C) 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 2.0 0 5 10 15 20 25 IOH (-mA) DS30292D-page 184 © 1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 16-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=3V, -40C TO 125C) 3.0 Max (-40C) Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Typ (25C) 2.0 V) (H 1.5 O V Min (125C) 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 16-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=5V, -40C TO 125C) 2.0 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 1.4 1.2 V) (L 1.0 VO Max (125C) 0.8 0.6 Typ (25C) 0.4 Min (-40C) 0.2 0.0 0 5 10 15 20 25 IOL (-mA)  1998-2013 Microchip Technology Inc. DS30292D-page 185

PIC16F87X FIGURE 16-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=3V, -40C TO 125C) 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 2.0 V) (L 1.5 O V Max (125C) 1.0 Typ (25C) 0.5 Min (-40C) 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 16-20: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40C TO 125C) 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Max (-40C) 1.4 1.2 Min (125C) 1.0 V) (N VI 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30292D-page 186 © 1998-2013 Microchip Technology Inc.

PIC16F87X FIGURE 16-21: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO 125C) 4.5 Typical: statistical mean @ 25°C 4.0 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 3.5 Max High (125C) 3.0 Min High (-40C) 2.5 V) (N VI 2.0 Max Low (125C) 1.5 Min Low (-40C) 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-22: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO 125C) 3.5 Typical: statistical mean @ 25°C 3.0 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Max High (125C) 2.5 Min High (-40C) Max Low (125C) 2.0 V) Min Low (25C) (N VI 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  1998-2013 Microchip Technology Inc. DS30292D-page 187

PIC16F87X NOTES: DS30292D-page 188 © 1998-2013 Microchip Technology Inc.

PIC16F87X 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example XXXXXXXXXXXXXXXXX PIC16F876-20/SP XXXXXXXXXXXXXXXXX YYWWNNN 0117HAT 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC16F876-04/SO XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 0110SAA Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  1998-2013 Microchip Technology Inc. DS30292D-page 189

PIC16F87X Package Marking Information (Cont’d) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX PIC16F877-04/P XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 0112SAA 44-Lead TQFP Example XXXXXXXXXX PIC16F877 XXXXXXXXXX -04/PT XXXXXXXXXX YYWWNNN 0111HAT 44-Lead MQFP Example XXXXXXXXXX PIC16F877 XXXXXXXXXX -20/PQ XXXXXXXXXX YYWWNNN 0104SAT 44-Lead PLCC Example XXXXXXXXXX PIC16F877 XXXXXXXXXX -20/L XXXXXXXXXX YYWWNNN 0103SAT DS30292D-page 190  1998-2013 Microchip Technology Inc.

PIC16F87X 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1  E A2 A L c  A1 B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 8.26 Molded Package Width E1 .275 .285 .295 6.99 7.24 7.49 Overall Length D 1.345 1.365 1.385 34.16 34.67 35.18 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .040 .053 .065 1.02 1.33 1.65 Lower Lead Width B .016 .019 .022 0.41 0.48 0.56 Overall Row Spacing § eB .320 .350 .430 8.13 8.89 10.92 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070  1998-2013 Microchip Technology Inc. DS30292D-page 191

PIC16F87X 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1 h  45 c A A2   L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .288 .295 .299 7.32 7.49 7.59 Overall Length D .695 .704 .712 17.65 17.87 18.08 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle Top  0 4 8 0 4 8 Lead Thickness c .009 .011 .013 0.23 0.28 0.33 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top  0 12 15 0 12 15 Mold Draft Angle Bottom  0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 DS30292D-page 192  1998-2013 Microchip Technology Inc.

PIC16F87X 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2  n 1 E A A2 L c B1  A1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 40 40 Pitch p .100 2.54 Top to Seating Plane A .160 .175 .190 4.06 4.45 4.83 Molded Package Thickness A2 .140 .150 .160 3.56 3.81 4.06 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .595 .600 .625 15.11 15.24 15.88 Molded Package Width E1 .530 .545 .560 13.46 13.84 14.22 Overall Length D 2.045 2.058 2.065 51.94 52.26 52.45 Tip to Seating Plane L .120 .130 .135 3.05 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .030 .050 .070 0.76 1.27 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .620 .650 .680 15.75 16.51 17.27 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016  1998-2013 Microchip Technology Inc. DS30292D-page 193

PIC16F87X 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45  A c   A1 A2 L (F) Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .031 0.80 Pins per Side n1 11 11 Overall Height A .039 .043 .047 1.00 1.10 1.20 Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Foot Length L .018 .024 .030 0.45 0.60 0.75 Footprint (Reference) (F) .039 1.00 Foot Angle  0 3.5 7 0 3.5 7 Overall Width E .463 .472 .482 11.75 12.00 12.25 Overall Length D .463 .472 .482 11.75 12.00 12.25 Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10 Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .012 .015 .017 0.30 0.38 0.44 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076 DS30292D-page 194  1998-2013 Microchip Technology Inc.

PIC16F87X 44-Lead Plastic Metric Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form (MQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45  A1 c A  L  (F) A2 Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .031 0.80 Pins per Side n1 11 11 Overall Height A .079 .086 .093 2.00 2.18 2.35 Molded Package Thickness A2 .077 .080 .083 1.95 2.03 2.10 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Foot Length L .029 .035 .041 0.73 0.88 1.03 Footprint (Reference) (F) .063 1.60 Foot Angle  0 3.5 7 0 3.5 7 Overall Width E .510 .520 .530 12.95 13.20 13.45 Overall Length D .510 .520 .530 12.95 13.20 13.45 Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10 Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10 Lead Thickness c .005 .007 .009 0.13 0.18 0.23 Lead Width B .012 .015 .018 0.30 0.38 0.45 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-022 Drawing No. C04-071  1998-2013 Microchip Technology Inc. DS30292D-page 195

PIC16F87X 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 1 2 CH2 x 45 CH1 x 45 A3  A2 A 35 B1 c B A1  p E2 D2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .050 1.27 Pins per Side n1 11 11 Overall Height A .165 .173 .180 4.19 4.39 4.57 Molded Package Thickness A2 .145 .153 .160 3.68 3.87 4.06 Standoff § A1 .020 .028 .035 0.51 0.71 0.89 Side 1 Chamfer Height A3 .024 .029 .034 0.61 0.74 0.86 Corner Chamfer 1 CH1 .040 .045 .050 1.02 1.14 1.27 Corner Chamfer (others) CH2 .000 .005 .010 0.00 0.13 0.25 Overall Width E .685 .690 .695 17.40 17.53 17.65 Overall Length D .685 .690 .695 17.40 17.53 17.65 Molded Package Width E1 .650 .653 .656 16.51 16.59 16.66 Molded Package Length D1 .650 .653 .656 16.51 16.59 16.66 Footprint Width E2 .590 .620 .630 14.99 15.75 16.00 Footprint Length D2 .590 .620 .630 14.99 15.75 16.00 Lead Thickness c .008 .011 .013 0.20 0.27 0.33 Upper Lead Width B1 .026 .029 .032 0.66 0.74 0.81 Lower Lead Width B .013 .020 .021 0.33 0.51 0.53 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-048 DS30292D-page 196  1998-2013 Microchip Technology Inc.

PIC16F87X APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Version Date Revision Description The differences between the devices in this data sheet A 1998 This is a new data sheet. are listed in TableB-1. However, these devices are similar to the PIC16C7X devices found in the PIC16C7X Data Sheet TABLE B-1: DEVICE DIFFERENCES (DS30390). Data Memory Map for PIC16F873/874, Difference PIC16F876/873 PIC16F877/874 moved ADFM bit from ADCON1<5> to ADCON1<7>. A/D 5 channels, 8 channels, 10-bits 10-bits B 1999 FLASH EEPROM access information. Parallel no yes C 2000 DC characteristics updated. Slave Port DC performance graphs added. Packages 28-pin PDIP, 40-pin PDIP, 28-pin windowed 44-pin TQFP, D 2013 Added a note to each package CERDIP, 28-pin 44-pin MQFP, drawing. SOIC 44-pin PLCC  1998-2013 Microchip Technology Inc. DS30292D-page 197

PIC16F87X APPENDIX C: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in TableC-1. TABLE C-1: CONVERSION CONSIDERATIONS Characteristic PIC16C7X PIC16F87X Pins 28/40 28/40 Timers 3 3 Interrupts 11 or 12 13 or 14 Communication PSP, USART, PSP, USART, SSP (SPI, I2C SSP (SPI, I2C Slave) Master/Slave) Frequency 20 MHz 20 MHz Voltage 2.5V - 5.5V 2.0V - 5.5V A/D 8-bit 10-bit CCP 2 2 Program 4K, 8K 4K, 8K Memory EPROM FLASH RAM 192, 368 192, 368 bytes bytes EEPROM data None 128, 256 bytes Other  In-Circuit Debugger, Low Voltage Programming DS30292D-page 198  1998-2013 Microchip Technology Inc.

PIC16F87X INDEX A PIC16F874/PIC16F877 ...............................................6 PORTA A/D ...................................................................................111 RA3:RA0 and RA5 Pins .....................................29 Acquisition Requirements ........................................114 RA4/T0CKI Pin ..................................................29 ADCON0 Register ....................................................111 PORTB ADCON1 Register ....................................................112 RB3:RB0 Port Pins ............................................31 ADIF bit ....................................................................112 RB7:RB4 Port Pins ............................................31 Analog Input Model Block Diagram ..........................114 PORTC Analog Port Pins .......................................7, 8, 9, 36, 38 Peripheral Output Override (RC 0:2, 5:7) ..........33 Associated Registers and Bits .................................117 Peripheral Output Override (RC 3:4) .................33 Block Diagram ..........................................................113 PORTD ......................................................................35 Calculating Acquisition Time ....................................114 PORTD and PORTE (Parallel Slave Port) .................38 Configuring Analog Port Pins ...................................115 PORTE ......................................................................36 Configuring the Interrupt ..........................................113 PWM Mode ................................................................61 Configuring the Module ............................................113 RESET Circuit ..........................................................123 Conversion Clock .....................................................115 SSP (I2C Mode) .........................................................73 Conversions .............................................................116 SSP (SPI Mode) ........................................................69 Delays ......................................................................114 Timer0/WDT Prescaler ..............................................47 Effects of a RESET ..................................................117 Timer1 .......................................................................52 GO/DONE bit ...........................................................112 Timer2 .......................................................................55 Internal Sampling Switch (Rss) Impedence .............114 USART Asynchronous Receive ...............................101 Operation During SLEEP .........................................117 USART Asynchronous Receive (9-bit Mode) ..........103 Result Registers .......................................................116 USART Transmit ........................................................99 Sampling Requirements ...........................................114 Watchdog Timer ......................................................131 Source Impedence ...................................................114 BOR. See Brown-out Reset Time Delays .............................................................114 BRG ...................................................................................79 Absolute Maximum Ratings .............................................149 BRGH bit ............................................................................97 ACK ....................................................................................74 Brown-out Reset (BOR) ............................119, 123, 125, 126 Acknowledge Data bit ........................................................68 BOR Status (BOR Bit) ...............................................25 Acknowledge Pulse ............................................................74 Buffer Full bit, BF ...............................................................74 Acknowledge Sequence Enable bit ....................................68 Bus Arbitration ...................................................................89 Acknowledge Status bit ......................................................68 Bus Collision Section .........................................................89 ADRES Register ........................................................15, 111 Bus Collision During a Repeated START Condition ..........92 Analog Port Pins. See A/D Bus Collision During a START Condition ..........................90 Analog-to-Digital Converter. See A/D Bus Collision During a STOP Condition ............................93 Application Notes Bus Collision Interrupt Flag bit, BCLIF ...............................24 AN552 (Implementing Wake-up on Key Strokes Using PIC16CXXX) ....................................31 C AN556 (Implementing a Table Read) ........................26 Capture/Compare/PWM (CCP) .........................................57 AN578 (Use of the SSP Module in the I2C Associated Registers Multi-Master Environment) .........................73 Capture, Compare and Timer1 ..........................62 Architecture PWM and Timer2 ...............................................63 PIC16F873/PIC16F876 Block Diagram .......................5 Capture Mode ............................................................59 PIC16F874/PIC16F877 Block Diagram .......................6 Block Diagram ...................................................59 Assembler CCP1CON Register ...........................................58 MPASM Assembler ..................................................143 CCP1IF ..............................................................59 B Prescaler ...........................................................59 CCP Timer Resources ...............................................57 Banking, Data Memory .................................................12, 18 CCP1 Baud Rate Generator .........................................................79 RC2/CCP1 Pin ..................................................7, 9 BCLIF .................................................................................24 CCP2 BF ............................................................................74, 82, 84 RC1/T1OSI/CCP2 Pin ......................................7, 9 Block Diagrams Compare A/D ...........................................................................113 Special Trigger Output of CCP1 ........................60 A/D Converter ..........................................................113 Special Trigger Output of CCP2 ........................60 Analog Input Model ..................................................114 Compare Mode ..........................................................60 Baud Rate Generator .................................................79 Block Diagram ...................................................60 Capture Mode ............................................................59 Software Interrupt Mode ....................................60 Compare Mode ..........................................................60 I2C Master Mode ........................................................78 Special Event Trigger ........................................60 I2C Module .................................................................73 Interaction of Two CCP Modules (table) ....................57 I2C Slave Mode ..........................................................73 Interrupt Logic ..........................................................129 PIC16F873/PIC16F876 ................................................5  1998-2013 Microchip Technology Inc. DS30292D-page 199

PIC16F87X PWM Mode ................................................................61 E Block Diagram ....................................................61 Electrical Characteristics ..................................................149 Duty Cycle ..........................................................61 Errata ...................................................................................4 Example Frequencies/Resolutions (Table) ........62 External Clock Input (RA4/T0CKI). See Timer0 PWM Period .......................................................61 External Interrupt Input (RB0/INT). See Interrupt Sources Special Event Trigger and A/D Conversions ..............60 CCP. See Capture/Compare/PWM F CCP1CON ..........................................................................17 Firmware Instructions .......................................................135 CCP2CON ..........................................................................17 FLASH Program Memory ...................................................41 CCPR1H Register ..................................................15, 17, 57 Associated Registers .................................................46 CCPR1L Register .........................................................17, 57 Code Protection .........................................................45 CCPR2H Register ........................................................15, 17 Configuration Bits and Read/Write State ...................46 CCPR2L Register .........................................................15, 17 Reading .....................................................................44 CCPxM0 bit ........................................................................58 Special Function Registers ........................................41 CCPxM1 bit ........................................................................58 Spurious Write Protection ..........................................45 CCPxM2 bit ........................................................................58 Write Protection .........................................................46 CCPxM3 bit ........................................................................58 Write Verify ................................................................45 CCPxX bit ...........................................................................58 Writing to ....................................................................44 CCPxY bit ...........................................................................58 FSR Register ....................................................15, 16, 17, 27 CKE ....................................................................................66 CKP ....................................................................................67 G Clock Polarity Select bit, CKP ............................................67 General Call Address Sequence ........................................76 Code Examples General Call Address Support ...........................................76 Call of a Subroutine in Page 1 from Page 0 ...............26 General Call Enable bit ......................................................68 EEPROM Data Read .................................................43 I EEPROM Data Write ..................................................43 FLASH Program Read ...............................................44 I/O Ports .............................................................................29 FLASH Program Write ...............................................45 I2C ......................................................................................73 Indirect Addressing ....................................................27 I2C Bus Initializing PORTA ......................................................29 Connection Considerations ........................................94 Saving STATUS, W and PCLATH Registers ...........130 Sample Device Configuration ....................................94 Code Protected Operation I2C Master Mode Reception ...............................................84 Data EEPROM and FLASH Program Memory ...........45 I2C Master Mode Repeated START Condition ..................81 Code Protection .......................................................119, 133 I2C Mode Selection ............................................................73 Computed GOTO ...............................................................26 I2C Module Configuration Bits .............................................................119 Acknowledge Sequence Timing ................................86 Configuration Word ..........................................................120 Addressing .................................................................74 Conversion Considerations ..............................................198 Associated Registers .................................................77 Baud Rate Generator .................................................79 D Block Diagram ...........................................................78 D/A .....................................................................................66 BRG Block Diagram ...................................................79 Data EEPROM ...................................................................41 BRG Reset due to SDA Collision ...............................91 Associated Registers .................................................46 BRG Timing ...............................................................80 Code Protection .........................................................45 Bus Arbitration ...........................................................89 Reading ......................................................................43 Bus Collision ..............................................................89 Special Functions Registers .......................................41 Acknowledge .....................................................89 Spurious Write Protection ..........................................45 Repeated START Condition ..............................92 Write Verify .................................................................45 Repeated START Condition Timing Writing to ....................................................................43 (Case1) ..............................................92 Data Memory ......................................................................12 Repeated START Condition Timing Bank Select (RP1:RP0 Bits) .................................12, 18 (Case2) ..............................................92 General Purpose Registers ........................................12 START Condition ...............................................90 Register File Map .................................................13, 14 START Condition Timing ..............................90, 91 Special Function Registers ........................................15 STOP Condition .................................................93 Data/Address bit, D/A .........................................................66 STOP Condition Timing (Case1) .......................93 DC and AC Characteristics Graphs and Tables ...............177 STOP Condition Timing (Case2) .......................93 DC Characteristics Transmit Timing .................................................89 Commercial and Industrial ...............................152–156 Bus Collision Timing ..................................................89 Extended ..........................................................157–160 Clock Arbitration ........................................................88 Development Support ......................................................143 Clock Arbitration Timing (Master Transmit) ...............88 Device Differences ...........................................................197 Conditions to not give ACK Pulse ..............................74 Device Overview ..................................................................5 General Call Address Support ...................................76 Direct Addressing ...............................................................27 Master Mode ..............................................................78 Master Mode 7-bit Reception Timing .........................85 Master Mode Block Diagram .....................................78 DS30292D-page 200  1998-2013 Microchip Technology Inc.

PIC16F87X Master Mode Operation .............................................79 INT Interrupt (RB0/INT). See Interrupt Sources Master Mode START Condition .................................80 INTCON .............................................................................17 Master Mode Transmission ........................................82 INTCON Register ...............................................................20 Master Mode Transmit Sequence ..............................79 GIE Bit .......................................................................20 Multi-Master Communication .....................................89 INTE Bit .....................................................................20 Multi-master Mode .....................................................78 INTF Bit .....................................................................20 Operation ...................................................................73 PEIE Bit .....................................................................20 Repeat START Condition Timing ...............................81 RBIE Bit .....................................................................20 Slave Mode ................................................................74 RBIF Bit ................................................................20, 31 Block Diagram ....................................................73 T0IE Bit ......................................................................20 Slave Reception .........................................................74 T0IF Bit ......................................................................20 Slave Transmission ....................................................75 Inter-Integrated Circuit (I2C) ..............................................65 SSPBUF .....................................................................73 Internal Sampling Switch (Rss) Impedence .....................114 STOP Condition Receive or Transmit Timing ............87 Interrupt Sources ......................................................119, 129 STOP Condition Timing .............................................87 Block Diagram .........................................................129 Waveforms for 7-bit Reception ..................................75 Interrupt-on-Change (RB7:RB4 ) ...............................31 Waveforms for 7-bit Transmission .............................76 RB0/INT Pin, External .......................................7, 8, 130 I2C Module Address Register, SSPADD ............................73 TMR0 Overflow ........................................................130 I2C Slave Mode ..................................................................74 USART Receive/Transmit Complete .........................95 ICEPIC In-Circuit Emulator ..............................................144 Interrupts ID Locations .............................................................119, 133 Bus Collision Interrupt ................................................24 In-Circuit Serial Programming (ICSP) ......................119, 134 Synchronous Serial Port Interrupt ..............................22 INDF ...................................................................................17 Interrupts, Context Saving During ....................................130 INDF Register .........................................................15, 16, 27 Interrupts, Enable Bits Indirect Addressing ............................................................27 Global Interrupt Enable (GIE Bit) ........................20, 129 FSR Register .............................................................12 Interrupt-on-Change (RB7:RB4) Enable Instruction Format ............................................................135 (RBIE Bit) .................................................130 Instruction Set ..................................................................135 Interrupt-on-Change (RB7:RB4) Enable ADDLW ....................................................................137 (RBIE Bit) ...................................................20 ADDWF ....................................................................137 Peripheral Interrupt Enable (PEIE Bit) .......................20 ANDLW ....................................................................137 RB0/INT Enable (INTE Bit) ........................................20 ANDWF ....................................................................137 TMR0 Overflow Enable (T0IE Bit) .............................20 BCF ..........................................................................137 Interrupts, Flag Bits BSF ..........................................................................137 Interrupt-on-Change (RB7:RB4) Flag BTFSC .....................................................................137 (RBIF Bit) .................................................130 BTFSS .....................................................................137 Interrupt-on-Change (RB7:RB4) Flag CALL ........................................................................138 (RBIF Bit) ..............................................20, 31 CLRF ........................................................................138 RB0/INT Flag (INTF Bit) ............................................20 CLRW ......................................................................138 TMR0 Overflow Flag (T0IF Bit) ...........................20, 130 CLRWDT ..................................................................138 K COMF ......................................................................138 DECF .......................................................................138 KEELOQ Evaluation and Programming Tools ...................146 DECFSZ ...................................................................139 L GOTO ......................................................................139 INCF .........................................................................139 Loading of PC ....................................................................26 INCFSZ ....................................................................139 M IORLW .....................................................................139 IORWF .....................................................................139 Master Clear (MCLR) ........................................................7, 8 MOVF .......................................................................140 MCLR Reset, Normal Operation ...............123, 125, 126 MOVLW ...................................................................140 MCLR Reset, SLEEP ................................123, 125, 126 MOVWF ...................................................................140 Memory Organization NOP .........................................................................140 Data Memory .............................................................12 RETFIE ....................................................................140 Program Memory .......................................................11 RETLW ....................................................................140 MPLAB C17 and MPLAB C18 C Compilers ....................143 RETURN ..................................................................141 MPLAB ICD In-Circuit Debugger .....................................145 RLF ..........................................................................141 MPLAB ICE High Performance Universal In-Circuit RRF ..........................................................................141 Emulator with MPLAB IDE ...............................................144 SLEEP .....................................................................141 MPLAB Integrated Development Environment Software .143 SUBLW ....................................................................141 MPLINK Object Linker/MPLIB Object Librarian ...............144 SUBWF ....................................................................141 Multi-Master Communication .............................................89 SWAPF ....................................................................142 Multi-Master Mode .............................................................78 XORLW ....................................................................142 XORWF ....................................................................142 Summary Table ........................................................136  1998-2013 Microchip Technology Inc. DS30292D-page 201

PIC16F87X O PORTA .......................................................................7, 8, 17 Analog Port Pins .......................................................7, 8 On-Line Support ...............................................................207 Associated Registers .................................................30 OPCODE Field Descriptions ............................................135 Block Diagram OPTION_REG Register ...............................................19, 48 RA3:RA0 and RA5 Pins .....................................29 INTEDG Bit ................................................................19 RA4/T0CKI Pin ..................................................29 PS2:PS0 Bits ..............................................................19 Initialization ................................................................29 PSA Bit .......................................................................19 PORTA Register ...................................................15, 29 T0CS Bit .....................................................................19 RA3 T0SE Bit .....................................................................19 RA0 and RA5 Port Pins .....................................29 OSC1/CLKIN Pin ..............................................................7, 8 RA4/T0CKI Pin .........................................................7, 8 OSC2/CLKOUT Pin ..........................................................7, 8 RA5/SS/AN4 Pin .......................................................7, 8 Oscillator Configuration ....................................................119 TRISA Register ..........................................................29 HS ....................................................................121, 124 PORTB .......................................................................7, 8, 17 LP .....................................................................121, 124 Associated Registers .................................................32 RC ............................................................121, 122, 124 Block Diagram XT .....................................................................121, 124 RB3:RB0 Port Pins ............................................31 Oscillator, WDT ................................................................131 RB7:RB4 Port Pins ............................................31 Oscillators PORTB Register ...................................................15, 31 Capacitor Selection ..................................................122 RB0/INT Edge Select (INTEDG Bit) ..........................19 Crystal and Ceramic Resonators .............................121 RB0/INT Pin, External .......................................7, 8, 130 RC ............................................................................122 RB7:RB4 Interrupt on Change .................................130 P RB7:RB4 Interrupt on Change Enable P (STOP bit) .......................................................................66 (RBIE Bit) .................................................130 Package Marking Information ..........................................189 RB7:RB4 Interrupt on Change Flag Packaging Information .....................................................189 (RBIF Bit) .................................................130 Paging, Program Memory ............................................11, 26 RB7:RB4 Interrupt-on-Change Enable Parallel Slave Port (PSP) .........................................9, 35, 38 (RBIE Bit) ...................................................20 Associated Registers .................................................39 RB7:RB4 Interrupt-on-Change Flag Block Diagram ............................................................38 (RBIF Bit) ..............................................20, 31 RE0/RD/AN5 Pin ..............................................9, 36, 38 TRISB Register .....................................................17, 31 RE1/WR/AN6 Pin .............................................9, 36, 38 PORTC .......................................................................7, 9, 17 RE2/CS/AN7 Pin ..............................................9, 36, 38 Associated Registers .................................................34 Read Waveforms .......................................................39 Block Diagrams Select (PSPMODE Bit) ..............................35, 36, 37, 38 Peripheral Output Override Write Waveforms ........................................................39 (RC 0:2, 5:7) ......................................33 PCL Register ..........................................................15, 16, 26 Peripheral Output Override PCLATH Register ..............................................15, 16, 17, 26 (RC 3:4) .............................................33 PCON Register ..........................................................25, 124 PORTC Register ...................................................15, 33 BOR Bit ......................................................................25 RC0/T1OSO/T1CKI Pin ............................................7, 9 POR Bit ......................................................................25 RC1/T1OSI/CCP2 Pin ..............................................7, 9 PIC16F876 Pinout Description .............................................7 RC2/CCP1 Pin ..........................................................7, 9 PIC16F87X Product Identification System .......................209 RC3/SCK/SCL Pin ....................................................7, 9 PICDEM 1 Low Cost PIC MCU RC4/SDI/SDA Pin .....................................................7, 9 Demonstration Board ...................................................145 RC5/SDO Pin ............................................................7, 9 PICDEM 17 Demonstration Board ...................................146 RC6/TX/CK Pin ...................................................7, 9, 96 PICDEM 2 Low Cost PIC16CXX RC7/RX/DT Pin .............................................7, 9, 96, 97 Demonstration Board ...................................................145 TRISC Register .....................................................33, 95 PICDEM 3 Low Cost PIC16CXXX PORTD .....................................................................9, 17, 38 Demonstration Board ...................................................146 Associated Registers .................................................35 PICSTART Plus Entry Level Block Diagram ...........................................................35 Development Programmer ...........................................145 Parallel Slave Port (PSP) Function ............................35 PIE1 Register .....................................................................21 PORTD Register ...................................................15, 35 PIE2 Register .....................................................................23 TRISD Register ..........................................................35 Pinout Descriptions PIC16F873/PIC16F876 ................................................7 PIC16F874/PIC16F877 ................................................8 PIR1 Register .....................................................................22 PIR2 Register .....................................................................24 POP ....................................................................................26 POR. See Power-on Reset DS30292D-page 202  1998-2013 Microchip Technology Inc.

PIC16F87X PORTE ...........................................................................9, 17 Registers Analog Port Pins ...............................................9, 36, 38 ADCON0 (A/D Control 0) .........................................111 Associated Registers .................................................36 ADCON1 (A/D Control 1) .........................................112 Block Diagram ............................................................36 CCP1CON (CCP Control 1) .......................................58 Input Buffer Full Status (IBF Bit) ................................37 EECON2 ....................................................................41 Input Buffer Overflow (IBOV Bit) ................................37 FSR ...........................................................................27 Output Buffer Full Status (OBF Bit) ............................37 INTCON .....................................................................20 PORTE Register ..................................................15, 36 OPTION_REG ......................................................19, 48 PSP Mode Select (PSPMODE Bit) ...........35, 36, 37, 38 PCON (Power Control) ..............................................25 RE0/RD/AN5 Pin ...............................................9, 36, 38 PIE1 (Peripheral Interrupt Enable 1) ..........................21 RE1/WR/AN6 Pin ..............................................9, 36, 38 PIE2 (Peripheral Interrupt Enable 2) ..........................23 RE2/CS/AN7 Pin ...............................................9, 36, 38 PIR1 (Peripheral Interrupt Request 1) .......................22 TRISE Register ..........................................................36 PIR2 (Peripheral Interrupt Request 2) .......................24 Postscaler, WDT RCSTA (Receive Status and Control) .......................96 Assignment (PSA Bit) ................................................19 Special Function, Summary .......................................15 Rate Select (PS2:PS0 Bits) .......................................19 SSPCON2 (Sync Serial Port Control 2) .....................68 Power-down Mode. See SLEEP STATUS ....................................................................18 Power-on Reset (POR) .....................119, 123, 124, 125, 126 T1CON (Timer1 Control) ...........................................51 Oscillator Start-up Timer (OST) .......................119, 124 T2CON (Timer 2 Control) POR Status (POR Bit) ................................................25 Timer2 Power Control (PCON) Register ..............................124 T2CON Register ........................................55 Power-down (PD Bit) .........................................18, 123 TRISE ........................................................................37 Power-up Timer (PWRT) .................................119, 124 TXSTA (Transmit Status and Control) .......................95 Time-out (TO Bit) ...............................................18, 123 Repeated START Condition Enable bit .............................68 Time-out Sequence on Power-up ....................127, 128 RESET ......................................................................119, 123 PR2 Register ................................................................16, 55 Block Diagram .........................................................123 Prescaler, Timer0 MCLR Reset. See MCLR Assignment (PSA Bit) ................................................19 RESET Rate Select (PS2:PS0 Bits) .......................................19 Brown-out Reset (BOR). See Brown-out Reset (BOR) PRO MATE II Universal Device Programmer ..................145 Power-on Reset (POR). See Power-on Reset (POR) Program Counter RESET Conditions for PCON Register ....................125 RESET Conditions ...................................................125 RESET Conditions for Program Counter .................125 Program Memory ...............................................................11 RESET Conditions for STATUS Register ................125 Interrupt Vector ..........................................................11 WDT Reset. See Watchdog Timer (WDT) Paging ..................................................................11, 26 Revision History ...............................................................197 Program Memory Map ...............................................11 S RESET Vector ............................................................11 Program Verification .........................................................133 S (START bit) ....................................................................66 Programming Pin (VPP) ....................................................7, 8 Sales and Support ...........................................................209 Programming, Device Instructions ...................................135 SCI. See USART PSP. See Parallel Slave Port. ............................................38 SCK ...................................................................................69 Pulse Width Modulation.SeeCapture/Compare/PWM, SCL ....................................................................................74 PWM Mode. SDA ...................................................................................74 PUSH .................................................................................26 SDI .....................................................................................69 SDO ...................................................................................69 R Serial Clock, SCK ..............................................................69 R/W ....................................................................................66 Serial Clock, SCL ...............................................................74 R/W bit ...............................................................................74 Serial Communication Interface. See USART R/W bit ...............................................................................74 Serial Data Address, SDA .................................................74 RAM. See Data Memory Serial Data In, SDI .............................................................69 RCREG ..............................................................................17 Serial Data Out, SDO ........................................................69 RCSTA Register ...........................................................17, 96 Slave Select, SS ................................................................69 ADDEN Bit .................................................................96 SLEEP ..............................................................119, 123, 132 CREN Bit ....................................................................96 SMP ...................................................................................66 FERR Bit ....................................................................96 Software Simulator (MPLAB SIM) ...................................144 OERR Bit ...................................................................96 SPBRG Register ................................................................16 RX9 Bit .......................................................................96 Special Features of the CPU ...........................................119 RX9D Bit ....................................................................96 Special Function Registers ................................................15 SPEN Bit ..............................................................95, 96 Special Function Registers (SFRs) ....................................15 SREN Bit ....................................................................96 Data EEPROM and FLASH Program Memory ..........41 Read/Write bit, R/W ...........................................................66 Speed, Operating .................................................................1 Reader Response ............................................................208 Receive Enable bit .............................................................68 Receive Overflow Indicator bit, SSPOV .............................67 Register File .......................................................................12 Register File Map .........................................................13, 14  1998-2013 Microchip Technology Inc. DS30292D-page 203

PIC16F87X SPI Synchronous Serial Port ....................................................65 Master Mode ..............................................................70 Synchronous Serial Port Enable bit, SSPEN .....................67 Master Mode Timing ..................................................70 Synchronous Serial Port Interrupt ......................................22 Serial Clock ................................................................69 Synchronous Serial Port Mode Select bits, Serial Data In .............................................................69 SSPM3:SSPM0 .............................................................67 Serial Data Out ...........................................................69 T Serial Peripheral Interface (SPI) ................................65 Slave Mode Timing ....................................................71 T1CKPS0 bit ......................................................................51 Slave Mode Timing Diagram ......................................71 T1CKPS1 bit ......................................................................51 Slave Select ...............................................................69 T1CON ...............................................................................17 SPI Clock ...................................................................70 T1CON Register ................................................................17 SPI Mode ...................................................................69 T1OSCEN bit .....................................................................51 SPI Clock Edge Select, CKE ..............................................66 T1SYNC bit ........................................................................51 SPI Data Input Sample Phase Select, SMP .......................66 T2CKPS0 bit ......................................................................55 SPI Mode T2CKPS1 bit ......................................................................55 Associated Registers .................................................72 T2CON Register ...........................................................17, 55 SPI Module TAD ...................................................................................115 Slave Mode ................................................................71 Time-out Sequence .........................................................124 SS ......................................................................................69 Timer0 ................................................................................47 SSP ....................................................................................65 Associated Registers .................................................49 Block Diagram (SPI Mode) .........................................69 Clock Source Edge Select (T0SE Bit) .......................19 RA5/SS/AN4 Pin ......................................................7, 8 Clock Source Select (T0CS Bit) .................................19 RC3/SCK/SCL Pin ...................................................7, 9 External Clock ............................................................48 RC4/SDI/SDA Pin ....................................................7, 9 Interrupt .....................................................................47 RC5/SDO Pin ...........................................................7, 9 Overflow Enable (T0IE Bit) ........................................20 SPI Mode ...................................................................69 Overflow Flag (T0IF Bit) ......................................20, 130 SSPADD ..............................................................73, 74 Overflow Interrupt ....................................................130 SSPBUF ...............................................................70, 73 Prescaler ....................................................................48 SSPCON2 ..................................................................68 RA4/T0CKI Pin, External Clock ................................7, 8 SSPSR .................................................................70, 74 T0CKI .........................................................................48 SSPSTAT ...................................................................73 WDT Prescaler Block Diagram ..................................47 SSP I2C Timer1 ................................................................................51 SSP I2C Operation .....................................................73 Associated Registers .................................................54 SSP Module Asynchronous Counter Mode ....................................53 SPI Master Mode .......................................................70 Reading and Writing to ......................................53 SPI Slave Mode .........................................................71 Block Diagram ...........................................................52 SSPCON1 Register ....................................................73 Counter Operation .....................................................52 SSP Overflow Detect bit, SSPOV ......................................74 Operation in Timer Mode ...........................................52 SSPADD Register ..............................................................16 Oscillator ....................................................................53 SSPBUF .................................................................17, 73, 74 Capacitor Selection ............................................53 SSPBUF Register ..............................................................15 Prescaler ....................................................................54 SSPCON Register ..............................................................15 RC0/T1OSO/T1CKI Pin ............................................7, 9 SSPCON1 ..........................................................................73 RC1/T1OSI/CCP2 Pin ..............................................7, 9 SSPCON2 Register ............................................................68 Resetting of Timer1 Registers ...................................54 SSPEN ...............................................................................67 Resetting Timer1 using a CCP Trigger Output ..........53 SSPIF ...........................................................................22, 74 Synchronized Counter Mode .....................................52 SSPM3:SSPM0 ..................................................................67 T1CON .......................................................................51 SSPOV ...................................................................67, 74, 84 T1CON Register ........................................................51 SSPSTAT ...........................................................................73 TMR1H ......................................................................53 SSPSTAT Register ............................................................16 TMR1L .......................................................................53 Stack ..................................................................................26 Timer2 ................................................................................55 Overflows ...................................................................26 Associated Registers .................................................56 Underflow ...................................................................26 Block Diagram ...........................................................55 START bit (S) .....................................................................66 Output ........................................................................56 START Condition Enable bit ..............................................68 Postscaler ..................................................................55 STATUS Register ...............................................................18 Prescaler ....................................................................55 C Bit ...........................................................................18 T2CON .......................................................................55 DC Bit .........................................................................18 Timing Diagrams IRP Bit ........................................................................18 A/D Conversion ........................................................175 PD Bit .................................................................18, 123 Acknowledge Sequence Timing ................................86 RP1:RP0 Bits .............................................................18 Baud Rate Generator with Clock Arbitration ..............80 TO Bit .................................................................18, 123 BRG Reset Due to SDA Collision ..............................91 Z Bit ............................................................................18 Brown-out Reset ......................................................164 STOP bit (P) .......................................................................66 Bus Collision STOP Condition Enable bit ................................................68 START Condition Timing ...................................90 DS30292D-page 204  1998-2013 Microchip Technology Inc.

PIC16F87X Bus Collision During a Repeated TXSTA Register .................................................................95 START Condition (Case 1) ........................92 BRGH Bit ...................................................................95 Bus Collision During a Repeated CSRC Bit ...................................................................95 START Condition (Case2) .........................92 SYNC Bit ...................................................................95 Bus Collision During a START TRMT Bit ....................................................................95 Condition (SCL = 0) ...................................91 TX9 Bit .......................................................................95 Bus Collision During a STOP Condition .....................93 TX9D Bit ....................................................................95 Bus Collision for Transmit and Acknowledge .............89 TXEN Bit ....................................................................95 Capture/Compare/PWM ...........................................166 U CLKOUT and I/O ......................................................163 I2C Bus Data ............................................................171 UA ......................................................................................66 I2C Bus START/STOP bits ......................................170 Universal Synchronous Asynchronous Receiver I2C Master Mode First START Bit Timing ..................80 Transmitter. See USART I2C Master Mode Reception Timing ...........................85 Update Address, UA ..........................................................66 I2C Master Mode Transmission Timing ......................83 USART ...............................................................................95 Master Mode Transmit Clock Arbitration ....................88 Address Detect Enable (ADDEN Bit) .........................96 Power-up Timer .......................................................164 Asynchronous Mode ..................................................99 Repeat START Condition ..........................................81 Asynchronous Receive ............................................101 RESET .....................................................................164 Associated Registers .......................................102 SPI Master Mode .......................................................70 Block Diagram .................................................101 SPI Slave Mode (CKE = 1) ........................................71 Asynchronous Receive (9-bit Mode) ........................103 SPI Slave Mode Timing (CKE = 0) .............................71 Associated Registers .......................................104 Start-up Timer ..........................................................164 Block Diagram .................................................103 STOP Condition Receive or Transmit ........................87 Timing Diagram ...............................................104 Time-out Sequence on Power-up ....................127, 128 Asynchronous Receive with Address Detect. Timer0 ......................................................................165 SeeAsynchronous Receive (9-bit Mode). Timer1 ......................................................................165 Asynchronous Reception .........................................102 USART Asynchronous Master Transmission ...........100 Asynchronous Transmitter .........................................99 USART Asynchronous Reception ............................102 Baud Rate Generator (BRG) .....................................97 USART Synchronous Receive .................................173 Baud Rate Formula ...........................................97 USART Synchronous Reception ..............................108 Baud Rates, Asynchronous Mode (BRGH=0) ...98 USART Synchronous Transmission ................106, 173 High Baud Rate Select (BRGH Bit) ...................95 USART, Asynchronous Reception ...........................104 Sampling ............................................................97 Wake-up from SLEEP via Interrupt ..........................133 Clock Source Select (CSRC Bit) ................................95 Watchdog Timer .......................................................164 Continuous Receive Enable (CREN Bit) ....................96 TMR0 .................................................................................17 Framing Error (FERR Bit) ..........................................96 TMR0 Register ...................................................................15 Mode Select (SYNC Bit) ............................................95 TMR1CS bit ........................................................................51 Overrun Error (OERR Bit) ..........................................96 TMR1H ...............................................................................17 RC6/TX/CK Pin .........................................................7, 9 TMR1H Register ................................................................15 RC7/RX/DT Pin .........................................................7, 9 TMR1L ...............................................................................17 RCSTA Register ........................................................96 TMR1L Register .................................................................15 Receive Data, 9th bit (RX9D Bit) ...............................96 TMR1ON bit .......................................................................51 Receive Enable, 9-bit (RX9 Bit) .................................96 TMR2 .................................................................................17 Serial Port Enable (SPEN Bit) ..............................95, 96 TMR2 Register ...................................................................15 Single Receive Enable (SREN Bit) ............................96 TMR2ON bit .......................................................................55 Synchronous Master Mode ......................................105 TOUTPS0 bit ......................................................................55 Synchronous Master Reception ...............................107 TOUTPS1 bit ......................................................................55 Associated Registers .......................................107 TOUTPS2 bit ......................................................................55 Synchronous Master Transmission .........................105 TOUTPS3 bit ......................................................................55 Associated Registers .......................................106 TRISA Register ..................................................................16 Synchronous Slave Mode ........................................108 TRISB Register ..................................................................16 Synchronous Slave Reception .................................109 TRISC Register ..................................................................16 Associated Registers .......................................109 TRISD Register ..................................................................16 Synchronous Slave Transmit ...................................108 TRISE Register .......................................................16, 36, 37 Associated Registers .......................................108 IBF Bit ........................................................................37 Transmit Block Diagram ............................................99 IBOV Bit .....................................................................37 Transmit Data, 9th Bit (TX9D) ...................................95 OBF Bit ......................................................................37 Transmit Enable (TXEN Bit) ......................................95 PSPMODE Bit ...........................................35, 36, 37, 38 Transmit Enable, Nine-bit (TX9 Bit) ...........................95 TXREG ...............................................................................17 Transmit Shift Register Status (TRMT Bit) ................95 TXSTA Register .........................................................95  1998-2013 Microchip Technology Inc. DS30292D-page 205

PIC16F87X W Wake-up from SLEEP ..............................................119, 132 Interrupts ..........................................................125, 126 MCLR Reset .............................................................126 Timing Diagram ........................................................133 WDT Reset ...............................................................126 Watchdog Timer (WDT) ...........................................119, 131 Block Diagram ..........................................................131 Enable (WDTE Bit) ...................................................131 Postscaler. See Postscaler, WDT Programming Considerations ...................................131 RC Oscillator ............................................................131 Time-out Period ........................................................131 WDT Reset, Normal Operation ................123, 125, 126 WDT Reset, SLEEP .................................123, 125, 126 Waveform for General Call Address Sequence .................76 WCOL ...................................................67, 80, 82, 84, 86, 87 WCOL Status Flag .............................................................80 Write Collision Detect bit, WCOL .......................................67 Write Verify Data EEPROM and FLASH Program Memory ...........45 WWW, On-Line Support .......................................................4 DS30292D-page 206  1998-2013 Microchip Technology Inc.

PIC16F87X ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events  1998-2013 Microchip Technology Inc. DS30292D-page 207

PIC16F87X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16F87X Literature Number: DS30292D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30292D-page 208  1998-2013 Microchip Technology Inc.

PIC16F87X PIC16F87X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F877 - 20/P 301 = Commercial temp., Range PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. b) PIC16LF876 - 04I/SO = Industrial temp., SOIC Device PPIICC1166FLF878X7X(1()1, ),P PICIC1166FL8F78X7TX(2T);( 2V )D; DV DraDn rgaen g4e.0 2V. 0toV 5to.5 5V.5V c) PppaaICcckk1aa6ggFee8,,7 12700 M0- 1HkH0zEz, ,/n PEo rx=mt eaEnlxd VteeDdnD dV leiDmdD i ttlseim.mitps.., PDIP Frequency Range 04 = 4 MHz 10 = 10 MHz 20 = 20 MHz Temperature Range blank = 0C to +70C (Commercial) I = -40C to +85C (Industrial) E = -40C to +125C (Extended) Note 1: F = CMOS FLASH Package PQ = MQFP (Metric PQFP) LF = Low Power CMOS FLASH PT = TQFP (Thin Quad Flatpack) 2: T = in tape and reel - SOIC, PLCC, SO = SOIC MQFP, TQFP packages only. SP = Skinny plastic DIP P = PDIP L = PLCC * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  1998-2013 Microchip Technology Inc. DS30292D-page 209

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PIC16F87X NOTES:  1998-2013 Microchip Technology Inc. DS30292D-page 211

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PIC16F87X DS30292D-page 216  1998-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1998-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769294 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  1998-2013 Microchip Technology Inc. DS30292D-page 217

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