PIC16F870/871 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers Devices Included in this Data Sheet: Pin Diagram • PIC16F870 • PIC16F871 PDIP Microcontroller Core Features: MCLR/VPP/THV 1 40 RB7/PGD RA0/AN0 2 39 RB6/PGC RA1/AN1 3 38 RB5 • High performance RISC CPU RA2/AN2/VREF- 4 37 RB4 • Only 35 single word instructions to learn RA3/AN3/VREF+ 5 36 RB3/PGM • All single cycle instructions except for program RA4/T0CKI 6 35 RB2 RA5/AN4 7 34 RB1 branches which are two-cycle RE0/RD/AN5 8 33 RB0/INT 1 • Operating speed: DC - 20 MHz clock input RE1/WR/AN6 9 7 32 VDD 8 DC - 200 ns instruction cycle RE2/CS/AN7 10 F 31 VSS 6 VDD 11 1 30 RD7/PSP7 • 2K x 14 words of FLASH Program Memory C VSS 12 PI 29 RD6/PSP6 128 x 8 bytes of Data Memory (RAM) OSC1/CLKI 13 28 RD5/PSP5 64 x 8 bytes of EEPROM Data Memory OSC2/CLKO 14 27 RD4/PSP4 RC0/T1OSO/T1CKI 15 26 RC7/RX/DT • Pinout compatible to the PIC16CXXX 28 and RC1/T1OSI 16 25 RC6/TX/CK 40-pin devices RC2/CCP1 17 24 RC5 • Interrupt capability (up to 11 sources) RC3 18 23 RC4 RD0/PSP0 19 22 RD3/PSP3 • Eight level deep hardware stack RD1/PSP1 20 21 RD2/PSP2 • Direct, Indirect and Relative Addressing modes • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Peripheral Features: • Watchdog Timer (WDT) with its own on-chip RC • Timer0: 8-bit timer/counter with 8-bit prescaler oscillator for reliable operation • Timer1: 16-bit timer/counter with prescaler, • Programmable code protection can be incremented during SLEEP via external • Power saving SLEEP mode crystal/clock • Selectable oscillator options • Timer2: 8-bit timer/counter with 8-bit period • Low power, high speed CMOS FLASH/EEPROM register, prescaler and postscaler technology • One Capture, Compare, PWM module • Fully static design - Capture is 16-bit, max. resolution is 12.5 ns • In-Circuit Serial Programming(ICSP)via - Compare is 16-bit, max. resolution is 200 ns two pins - PWM max. resolution is 10-bit • Single 5V In-Circuit Serial Programming capability • 10-bit multi-channel Analog-to-Digital converter • In-Circuit Debugging via two pins • Universal Synchronous Asynchronous Receiver • Processor read/write access to program memory Transmitter (USART/SCI) with 9-bit address • Wide operating voltage range: 2.0V to 5.5V detection • High Sink/Source Current: 25 mA • Parallel Slave Port (PSP) 8-bits wide, with • Commercial and Industrial temperature ranges external RD, WR and CS controls (40/44-pin only) • Low power consumption: • Brown-out detection circuitry for Brown-out Reset (BOR) - < 1.6 mA typical @ 5V, 4 MHz - 20 A typical @ 3V, 32 kHz - < 1 A typical standby current  2000-2013 Microchip Technology Inc. DS30569C-page 1

PIC16F870/871 Pin Diagrams DIP, SOIC, SSOP MCLR/VPP/THV 1 28 RB7/PGD RA0/AN0 2 27 RB6/PGC RA1/AN1 3 26 RB5 RA2/AN2/VREF- 4 25 RB4 RA3/AN3/VREF+ 5 24 RB3/PGM RA4/T0CKI 6 0 23 RB2 RA5/AN4 7 87 22 RB1 F VSS 8 6 21 RB0/INT 1 OSC1/CLKI 9 C 20 VDD OSC2/CLKO 10 PI 19 VSS RC0/T1OSO/T1CKI 11 18 RC7/RX/DT RC1/T1OSI 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5 RC3 14 15 RC4 +EF-EF HV RR T PLCC N3/VN2/VN1N0V/PP GDGC AAAAR/ PP A3/A2/A1/A0/CLCB7/B6/B5B4C RRRRMNRRRRN 65432143210 RA4/T0CKI 7 4444439 RB3/PGM RA5/AN4 8 38 RB2 RE0/RD/AN5 9 37 RB1 RE1/WR/AN6 10 36 RB0/INT RE2/CS/AN7 11 35 VDD VDD 12 PIC16F871 34 VSS VSS 13 33 RD7/PSP7 OSC1/CLKI 14 32 RD6/PSP6 OSC2/CLKO 15 31 RD5/PSP5 RC0/T1OSO/T1CK1 16 30 RD4/PSP4 NC 17 29 RC7/RX/DT 89012345678 11222222222 TQFP RC6/TX/CKRC5RC4RD3/PSP3RD2/PSP2RD1/PSP1RD0/PSP0RC3RC2/CCP1RC1/T1OSINC RC1/T1OSIRC2/CCP1RC3RD0/PSP0RD1/PSP1RD2/PSP2RD3/PSP3RC4RC5RC6/TX/CKNC 43210987654 44444333333 RC7/RX/DT 1 33 NC RD4/PSP4 2 32 RC0/T1OSO/T1CKI RD5/PSP5 3 31 OSC2/CLKO RD6/PSP6 4 30 OSC1/CLKI RD7/PSP7 5 29 VSS VSS 6 PIC16F871 28 VDD VDD 7 27 RE2/CS/AN7 RB0/INT 8 26 RE1/WR/AN6 RB1 9 25 RE0/RD/AN5 RB2 10 24 RA5/AN4 RB3/PGM 11 23 RA4/T0CKI 23456789012 11111111222 NCNCRB4RB5RB6/PGCRB7/PGDR/V/THVPPRA0/AN0RA1/AN1AN2/V-REFAN3/V+REF CL A2/A3/ M RR DS30569C-page 2  2000-2013 Microchip Technology Inc.

PIC16F870/871 Key Features PICmicroTM Mid-Range MCU Family Reference Manual PIC16F870 PIC16F871 (DS33023) Operating Frequency DC - 20 MHz DC - 20 MHz RESETS (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) FLASH Program Memory (14-bit words) 2K 2K Data Memory (bytes) 128 128 EEPROM Data Memory 64 64 Interrupts 10 11 I/O Ports Ports A,B,C Ports A,B,C,D,E Timers 3 3 Capture/Compare/PWM modules 1 1 Serial Communications USART USART Parallel Communications — PSP 10-bit Analog-to-Digital Module 5 input channels 8 input channels Instruction Set 35 Instructions 35 Instructions  2000-2013 Microchip Technology Inc. DS30569C-page 3

PIC16F870/871 Table of Contents 1.0 Device Overview..........................................................................................................................................................................5 2.0 Memory Organization.................................................................................................................................................................11 3.0 Data EEPROM and Flash Program Memory..............................................................................................................................27 4.0 I/O Ports.....................................................................................................................................................................................33 5.0 Timer0 Module...........................................................................................................................................................................45 6.0 Timer1 Module...........................................................................................................................................................................49 7.0 Timer2 Module...........................................................................................................................................................................53 8.0 Capture/Compare/PWM Modules..............................................................................................................................................55 9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)................................................................61 10.0 Analog-to-Digital (A/D) Converter Module..................................................................................................................................79 11.0 Special Features of the CPU......................................................................................................................................................87 12.0 Instruction Set Summary..........................................................................................................................................................103 13.0 Development Support...............................................................................................................................................................111 14.0 Electrical Characteristics..........................................................................................................................................................117 15.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................137 16.0 Packaging Information..............................................................................................................................................................149 Appendix A: Revision History.............................................................................................................................................................157 Appendix B: Device Differences.........................................................................................................................................................157 Appendix C: Conversion Considerations...........................................................................................................................................158 Appendix D: Migration from Mid-Range to Enhanced Devices..........................................................................................................158 Appendix E: Migration from High-End to Enhanced Devices.............................................................................................................159 Index..................................................................................................................................................................................................161 On-Line Support.................................................................................................................................................................................167 Systems Information and Upgrade Hot Line......................................................................................................................................167 Reader Response..............................................................................................................................................................................168 PIC16F870/871 Product Identification System..................................................................................................................................169 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS30569C-page 4  2000-2013 Microchip Technology Inc.

PIC16F870/871 1.0 DEVICE OVERVIEW There are two devices (PIC16F870 and PIC16F871) covered by this data sheet. The PIC16F870 device This document contains device specific information. comes in a 28-pin package and the PIC16F871 device Additional information may be found in the PICmicroTM comes in a 40-pin package. The 28-pin device does not Mid-Range MCU Family Reference Manual have a Parallel Slave Port implemented. (DS33023), which may be obtained from your local The following two figures are device block diagrams Microchip Sales Representative or downloaded from sorted by pin number: 28-pin for Figure1-1 and 40-pin the Microchip web site. The Reference Manual should for Figure1-2. The 28-pin and 40-pin pinouts are listed be considered a complementary document to this data in Table1-1 and Table1-2, respectively. sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. FIGURE 1-1: PIC16F870 BLOCK DIAGRAM Device Program FLASH Data Memory Data EEPROM PIC16F870 2K 128 Bytes 64 Bytes 13 Data Bus 8 PORTA Program Counter FLASH RA0/AN0 Program RA1/AN1 Memory RAM RA2/AN2/VREF- 8 Level Stack File RA3/AN3/VREF+ (13-bit) Registers RA4/T0CKI RA5/AN4 Program 14 Bus RAM Addr (1) 9 PORTB RB0/INT Instruction reg Addr MUX RB1 RB2 Direct Addr 7 Indirect RB3/PGM 8 Addr RB4 FSR reg RB5 RB6/PGC STATUS reg RB7/PGD 8 PORTC RC0/T1OSO/T1CKI RC1/T1OSI Power-up 3 MUX RRCC23/CCP1 Timer RC4 Instruction Oscillator RC5 Decode & Start-up Timer ALU RC6/TX/CK Control Power-on RC7/RX/DT Reset 8 Timing Watchdog Generation Timer W reg OSC1/CLKI Brown-out OSC2/CLKO Reset In-Circuit Debugger Low-Voltage Programming MCLR VDD, VSS Timer0 Timer1 Timer2 10-bit A/D Data EEPROM CCP1 USART Note 1: Higher order bits are from the STATUS register.  2000-2013 Microchip Technology Inc. DS30569C-page 5

PIC16F870/871 FIGURE 1-2: PIC16F871 BLOCK DIAGRAM Device Program FLASH Data Memory Data EEPROM PIC16F871 2K 128 Bytes 64 Bytes 13 Data Bus 8 PORTA Program Counter FLASH RA0/AN0 Program RA1/AN1 Memory RAM RA2/AN2/VREF- 8 Level Stack File RA3/AN3/VREF+ (13-bit) Registers RA4/T0CKI RA5/AN4 Program 14 Bus RAM Addr (1) 9 PORTB RB0/INT Addr MUX RB1 Instruction reg RB2 Direct Addr 7 Indirect RB3/PGM 8 Addr RB4 FSR reg RB5 RB6/PGC STATUS reg RB7/PGD 8 PORTC RC0/T1OSO/T1CKI RC1/T1OSI Power-up 3 MUX RRCC23/CCP1 Timer RC4 Instruction Oscillator RC5 Decode & Start-up Timer ALU RC6/TX/CK Control Power-on RC7/RX/DT Reset 8 PORTD Timing Watchdog Generation Timer W reg OSC1/CLKI Brown-out OSC2/CLKO Reset RD7/PSP7:RD0/PSP0 In-Circuit Debugger Low-Voltage Programming PORTE RE0/RD/AN5 RE1/WR/AN6 MCLR VDD, VSS RE2/CS/AN7 Timer0 Timer1 Timer2 10-bit A/D Data EEPROM CCP1 Parallel Slave Port USART Note 1: Higher order bits are from the STATUS register. DS30569C-page 6  2000-2013 Microchip Technology Inc.

PIC16F870/871 TABLE 1-1: PIC16F870 PINOUT DESCRIPTION DIP SOIC I/O/P Buffer Pin Name Description Pin# Pin# Type Type OSC1/CLKI 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input. OSC2/CLKO 10 10 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, the OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP/THV 1 1 I/P ST Master Clear (Reset) input or programming voltage input or High Voltage Test mode control. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0/AN0 2 2 I/O TTL RA0 can also be analog input 0. RA1/AN1 3 3 I/O TTL RA1 can also be analog input 1. RA2/AN2/VREF- 4 4 I/O TTL RA2 can also be analog input 2 or negative analog reference voltage. RA3/AN3/VREF+ 5 5 I/O TTL RA3 can also be analog input 3 or positive analog reference voltage. RA4/T0CKI 6 6 I/O ST/OD RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5/AN4 7 7 I/O TTL RA5 can also be analog input 4. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 22 22 I/O TTL RB2 23 23 I/O TTL RB3/PGM 24 24 I/O TTL/ST(1) RB3 can also be the low voltage programming input. RB4 25 25 I/O TTL Interrupt-on-change pin. RB5 26 26 I/O TTL Interrupt-on-change pin. RB6/PGC 27 27 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming clock. RB7/PGD 28 28 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI 12 12 I/O ST RC1 can also be the Timer1 oscillator input. RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3 14 14 I/O ST RC4 15 15 I/O ST RC5 16 16 I/O ST RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins. VDD 20 20 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power OD = Open Drain — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.  2000-2013 Microchip Technology Inc. DS30569C-page 7

PIC16F870/871 TABLE 1-2: PIC16F871 PINOUT DESCRIPTION DIP PLCC QFP I/O/P Buffer Pin Name Description Pin# Pin# Pin# Type Type OSC1/CLKI 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input. OSC2/CLKO 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP/THV 1 2 18 I/P ST Master Clear (Reset) input or programming voltage input or High Voltage Test mode control. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input 0. RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input 1. RA2/AN2/VREF- 4 5 21 I/O TTL RA2 can also be analog input 2 or negative analog reference voltage. RA3/AN3/VREF+ 5 6 22 I/O TTL RA3 can also be analog input 3 or positive analog reference voltage. RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/counter. Output is open drain type. RA5/AN4 7 8 24 I/O TTL RA5 can also be analog input 4. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 34 37 9 I/O TTL RB2 35 38 10 I/O TTL RB3/PGM 36 39 11 I/O TTL/ST(1) RB3 can also be the low voltage programming input. RB4 37 41 14 I/O TTL Interrupt-on-change pin. RB5 38 42 15 I/O TTL Interrupt-on-change pin. RB6/PGC 39 43 16 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming clock. RB7/PGD 40 44 17 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input. RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3 18 20 37 I/O ST RC4 23 25 42 I/O ST RC5 24 26 43 I/O ST RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. DS30569C-page 8  2000-2013 Microchip Technology Inc.

PIC16F870/871 TABLE 1-2: PIC16F871 PINOUT DESCRIPTION (CONTINUED) DIP PLCC QFP I/O/P Buffer Pin Name Description Pin# Pin# Pin# Type Type PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus. RD0/PSP0 19 21 38 I/O ST/TTL(3) RD1/PSP1 20 22 39 I/O ST/TTL(3) RD2/PSP2 21 23 40 I/O ST/TTL(3) RD3/PSP3 22 24 41 I/O ST/TTL(3) RD4/PSP4 27 30 2 I/O ST/TTL(3) RD5/PSP5 28 31 3 I/O ST/TTL(3) RD6/PSP6 29 32 4 I/O ST/TTL(3) RD7/PSP7 30 33 5 I/O ST/TTL(3) PORTE is a bi-directional I/O port. RE0/RD/AN5 8 9 25 I/O ST/TTL(3) RE0 can also be read control for the parallel slave port, or analog input 5. RE1/WR/AN6 9 10 26 I/O ST/TTL(3) RE1 can also be write control for the parallel slave port, or analog input 6. RE2/CS/AN7 10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave port, or analog input 7. VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins. VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins. NC — 1,17,28, 12,13, — These pins are not internally connected. These pins should be 40 33,34 left unconnected. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.  2000-2013 Microchip Technology Inc. DS30569C-page 9

PIC16F870/871 NOTES: DS30569C-page 10  2000-2013 Microchip Technology Inc.

PIC16F870/871 2.0 MEMORY ORGANIZATION 2.2 Data Memory Organization The PIC16F870/871 devices have three memory The data memory is partitioned into multiple banks blocks. The Program Memory and Data Memory have which contain the General Purpose Registers and the separate buses, so that concurrent access can occur, Special Function Registers. Bits RP1 (STATUS<6>) and is detailed in this section. The EEPROM data and RP0 (STATUS<5>) are the bank select bits. memory block is detailed in Section3.0. RP<1:0> Bank Additional information on device memory may be found 00 0 in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023). 01 1 10 2 2.1 Program Memory Organization 11 3 The PIC16F870/871 devices have a 13-bit program Each bank extends up to 7Fh (128 bytes). The lower counter capable of addressing an 8K x 14 program locations of each bank are reserved for the Special memory space. The PIC16F870/871 devices have Function Registers. Above the Special Function Regis- 2Kx 14 words of FLASH program memory. Accessing ters are General Purpose Registers, implemented as a location above the physically implemented address static RAM. All implemented banks contain Special will cause a wraparound. Function Registers. Some “high use” Special Function The RESET vector is at 0000h and the interrupt vector Registers from one bank may be mirrored in another is at 0004h. bank for code reduction and quicker access. Note: EEPROM Data Memory description can FIGURE 2-1: PIC16F870/871 PROGRAM be found in Section3.0 of this Data Sheet. MEMORY MAP AND STACK 2.2.1 GENERAL PURPOSE REGISTER FILE PC<12:0> The register file can be accessed either directly, or CALL, RETURN 13 indirectly through the File Select Register FSR. RETFIE, RETLW Stack Level 1 Stack Level 2 Stack Level 8 RESET Vector 0000h Interrupt Vector 0004h On-Chip 0005h Program Page 0 Memory 07FFh 0800h 1FFFh  2000-2013 Microchip Technology Inc. DS30569C-page 11

PIC16F870/871 FIGURE 2-2: PIC16F870/871 REGISTER FILE MAP File File File File Address Address Address Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h 107h 187h PORTD(2) 08h TRISD(2) 88h 108h 188h PORTE(2) 09h TRISE(2) 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDATA 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved(1) 18Eh TMR1H 0Fh 8Fh EEADRH 10Fh Reserved(1) 18Fh T1CON 10h 90h 110h 190h TMR2 11h 91h T2CON 12h PR2 92h 13h 93h 14h 94h CCPR1L 15h 95h CCPR1H 16h 96h CCP1CON 17h 97h RCSTA 18h TXSTA 98h TXREG 19h SPBRG 99h RCREG 1Ah 9Ah 1Bh 9Bh 1Ch 9Ch 1Dh 9Dh ADRESH 1Eh ADRESL 9Eh ADCON0 1Fh ADCON1 9Fh 120h 1A0h 20h General A0h Purpose accesses accesses Register 20h-7Fh A0h - BFh General Purpose 32 Bytes BFh 1BFh Register C0h 1C0h 96 Bytes 16Fh 1EFh EFh accesses F0h accesses 170h accesses 1F0h 70h-7Fh 70h-7Fh 70h-7Fh 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are reserved; maintain these registers clear. 2: These registers are not implemented on the PIC16F870. DS30569C-page 12  2000-2013 Microchip Technology Inc.

PIC16F870/871 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers The Special Function Registers are registers used by associated with the core functions are described in the CPU and peripheral modules for controlling the detail in this section. Those related to the operation of desired operation of the device. These registers are the peripheral features are described in detail in the implemented as static RAM. A list of these registers is peripheral feature section. given in Table2-1. TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS(2) Bank 0 00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 09h(5) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(3) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 0Dh PIR2 — — — EEIF — — — — ---0 ---- ---0 ---- 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h — Unimplemented — — 14h — Unimplemented — — 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.  2000-2013 Microchip Technology Inc. DS30569C-page 13

PIC16F870/871 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS(2) Bank 1 80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h(5) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE(3) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 8Dh PIE2 — — — EEIE — — — — ---0 ---- ---0 ---- 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h — Unimplemented — — 94h — Unimplemented — — 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 0--- 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’. DS30569C-page 14  2000-2013 Microchip Technology Inc.

PIC16F870/871 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS(2) Bank 2 100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 102h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 103h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 104h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 105h — Unimplemented — — 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 10Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Ch EEDATA EEPROM Data Register xxxx xxxx uuuu uuuu 10Dh EEADR EEPROM Address Register xxxx xxxx uuuu uuuu 10Eh EEDATH — — EEPROM Data Register High Byte xxxx xxxx uuuu uuuu 10Fh EEADRH — — — EEPROM Address Register High Byte xxxx xxxx uuuu uuuu Bank 3 180h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 182h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 183h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 184h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 18Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 x--- u000 18Dh EECON2 EEPROM Control Register2 (not a physical register) ---- ---- ---- ---- 18Eh — Reserved maintain clear 0000 0000 0000 0000 18Fh — Reserved maintain clear 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.  2000-2013 Microchip Technology Inc. DS30569C-page 15

PIC16F870/871 2.2.2.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register contains the arithmetic status of as 000u u1uu (where u = unchanged). the ALU, the RESET status and the bank select bits for data memory. It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the The STATUS register can be the destination for any STATUS register, because these instructions do not instruction, as with any other register. If the STATUS affect the Z, C or DC bits from the STATUS register. For register is the destination for an instruction that affects other instructions not affecting any status bits, see the the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”. disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not Note1: The C and DC bits operate as a borrow writable, therefore, the result of an instruction with the and digit borrow bit, respectively, in sub- STATUS register as destination may be different than traction. See the SUBLW and SUBWF intended. instructions for examples. REGISTER 2-1: STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 bit 7-6 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 11 = Bank 1 (80h - FFh) 10 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30569C-page 16  2000-2013 Microchip Technology Inc.

PIC16F870/871 2.2.2.2 OPTION_REG Register The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assign- able register known also as the prescaler), the External INT interrupt, TMR0 and the weak pull-ups on PORTB. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. REGISTER 2-2: OPTION_REG REGISTER (ADDRESS: 81h,181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2000-2013 Microchip Technology Inc. DS30569C-page 17

PIC16F870/871 2.2.2.3 INTCON Register Note: Interrupt flag bits get set when an interrupt The INTCON register is a readable and writable regis- condition occurs, regardless of the state of ter, which contains various enable and flag bits for the its corresponding enable bit or the global TMR0 register overflow, RB Port change and External enable bit, GIE (INTCON<7>). User soft- RB0/INT pin interrupts. ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit 7 bit 0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30569C-page 18  2000-2013 Microchip Technology Inc.

PIC16F870/871 2.2.2.4 PIE1 Register The PIE1 register contains the individual enable bits for the peripheral interrupts. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. REGISTER 2-4: PIE1 REGISTER (ADDRESS: 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE  CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 Unimplemented: Read as ‘0’ bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note1: PSPIE is reserved on the PIC16F870; always maintain this bit clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2000-2013 Microchip Technology Inc. DS30569C-page 19

PIC16F870/871 2.2.2.5 PIR1 Register The PIR1 register contains the individual flag bits for the peripheral interrupts. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1 REGISTER (ADDRESS: 0Ch) R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF  CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full bit 3 Unimplemented: Read as ‘0’ bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: PSPIF is reserved on the PIC16F870; always maintain this bit clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30569C-page 20  2000-2013 Microchip Technology Inc.

PIC16F870/871 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bit for the EEPROM write operation interrupt. REGISTER 2-6: PIE2 REGISTER (ADDRESS: 8Dh) U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 — — — EEIE — — — — bit 7 bit 0 bit 7-5 Unimplemented: Read as '0' bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit 1 = Enable EE write interrupt 0 = Disable EE write interrupt bit 3-0 Unimplemented: Read as '0' Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2000-2013 Microchip Technology Inc. DS30569C-page 21

PIC16F870/871 2.2.2.7 PIR2 Register The PIR2 register contains the flag bit for the EEPROM write operation interrupt. . Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. REGISTER 2-7: PIR2 REGISTER (ADDRESS: 0Dh) U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 — — — EEIF — — — — bit 7 bit 0 bit 7-5 Unimplemented: Read as '0' bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3-0 Unimplemented: Read as '0' Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30569C-page 22  2000-2013 Microchip Technology Inc.

PIC16F870/871 2.2.2.8 PCON Register The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. Note: BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don’t care and is not predictable if the brown-out circuit is dis- abled (by clearing the BOREN bit in the configuration word). REGISTER 2-8: PCON REGISTER (ADDRESS: 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1 — — — — — — POR BOR bit 7 bit 0 bit 7-2 Unimplemented: Read as '0' bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2000-2013 Microchip Technology Inc. DS30569C-page 23

PIC16F870/871 2.3 PCL and PCLATH The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth The Program Counter (PC) is 13-bits wide. The low push overwrites the value that was stored from the first byte comes from the PCL register, which is a readable push. The tenth push overwrites the second push (and and writable register. The upper bits (PC<12:8>) are so on). not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the Note1: There are no status bits to indicate stack PC will be cleared. Figure2-3 shows the two situations overflow or stack underflow conditions. for the loading of the PC. The upper example in the fig- 2: There are no instructions/mnemonics ure shows how the PC is loaded on a write to PCL called PUSH or POP. These are actions (PCLATH<4:0>  PCH). The lower example in the fig- that occur from the execution of the CALL, ure shows how the PC is loaded during a CALL or GOTO RETURN, RETLW and RETFIE instruc- instruction (PCLATH<4:3>  PCH). tions, or the vectoring to an interrupt address. FIGURE 2-3: LOADING OF PC IN DIFFERENT SITUATIONS 2.4 Program Memory Paging The PIC16FXXX architecture is capable of addressing PCH PCL a continuous 8K word block of program memory. The 12 8 7 0 Instruction with CALL and GOTO instructions provide 11 bits of the PC PCL as address, which allows branches within any 2K program Destination PCLATH<4:0> 8 memory page. Therefore, the 8K words of program 5 ALU memory are broken into four pages. Since the PIC16F872 has only 2K words of program memory or PCLATH one page, additional code is not required to ensure that the correct page is selected before a CALL or GOTO PCH PCL instruction is executed. The PCLATH<4:3> bits should 12 11 10 8 7 0 always be maintained as zeros. If a return from a CALL PC GOTO,CALL instruction (or interrupt) is executed, the entire 13-bit PCLATH<4:3> 11 PC is popped off the stack. Manipulation of the 2 Opcode <10:0> PCLATH is not required for the return instructions. PCLATH 2.5 Indirect Addressing, INDF and FSR Registers 2.3.1 COMPUTED GOTO The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a Indirect addressing is possible by using the INDF reg- table read using a computed GOTO method, care ister. Any instruction using the INDF register actually should be exercised if the table location crosses a PCL accesses the register pointed to by the File Select reg- memory boundary (each 256-byte block). Refer to the ister, FSR. Reading the INDF register itself indirectly application note, “Implementing a Table Read" (FSR = 0) will read 00h. Writing to the INDF register (AN556). indirectly results in a no operation (although status bits may be affected). An effective 9-bit address is obtained 2.3.2 STACK by concatenating the 8-bit FSR register and the IRP bit The PIC16FXXX family has an 8-level deep x 13-bit (STATUS<7>), as shown in Figure2-4. wide hardware stack. The stack space is not part of A simple program to clear RAM locations 20h-2Fh either program or data space and the stack pointer is using indirect addressing is shown in Example2-1. not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an inter- EXAMPLE 2-1: INDIRECT ADDRESSING rupt causes a branch. The stack is POPed in the event movlw 0x20 ;initialize pointer of a RETURN, RETLW or a RETFIE instruction movwf FSR ;to RAM execution. PCLATH is not affected by a PUSH or POP NEXT clrf INDF ;clear INDF register operation. incf FSR,F ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next CONTINUE : ;yes continue DS30569C-page 24  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 2-4: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1:RP0 6 from opcode 0 IRP 7 FSR Register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 80h 100h 180h Data Memory(1) 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register file map detail see Figure2-2.  2000-2013 Microchip Technology Inc. DS30569C-page 25

PIC16F870/871 NOTES: DS30569C-page 26  2000-2013 Microchip Technology Inc.

PIC16F870/871 3.0 DATA EEPROM AND FLASH The value written to program memory does not need to PROGRAM MEMORY be a valid instruction. Therefore, up to 14-bit numbers can be stored in memory for use as calibration param- The Data EEPROM and FLASH Program Memory are eters, serial numbers, packed 7-bit ASCII, etc. Execut- readable and writable during normal operation over the ing a program memory location containing data that entire VDD range. A bulk erase operation may not be forms an invalid instruction results in a NOP. issued from user code (which includes removing code protection). The data memory is not directly mapped in 3.1 EEADR the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). The address registers can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of There are six SFRs used to read and write the program 8Kwords of program FLASH. However, the and data EEPROM memory. These registers are: PIC16F870/871 have 64 bytes of data EEPROM and • EECON1 2K words of program FLASH. • EECON2 When selecting a program address value, the MSByte • EEDATA of the address is written to the EEADRH register and • EEDATH the LSByte is written to the EEADR register. When selecting a data address value, only the LSByte of the • EEADR address is written to the EEADR register. • EEADRH On the PIC16F870/871 devices, the upper two bits of The EEPROM data memory allows byte read and write. the EEADR must always be cleared to prevent inadver- When interfacing to the data memory block, EEDATA tent access to the wrong location in data EEPROM. holds the 8-bit data for read/write and EEADR holds the This also applies to the program memory. The upper address of the EEPROM location being accessed. The five MSbits of EEADRH must always be clear during registers EEDATH and EEADRH are not used for data program FLASH access. EEPROM access. The PIC16F870/871 devices have 64 bytes of data EEPROM with an address range from 3.2 EECON1 and EECON2 Registers 0h to 3Fh. The EEPROM data memory is rated for high erase/ The EECON1 register is the control register for config- write cycles. The write time is controlled by an on-chip uring and initiating the access. The EECON2 register is timer. The write time will vary with voltage and temper- not a physically implemented register, but is used ature, as well as from chip-to-chip. Please refer to the exclusively in the memory write sequence to prevent specifications for exact limits. inadvertent writes. The program memory allows word reads and writes. There are many bits used to control the read and write Program memory access allows for checksum calcula- operations to EEPROM data and FLASH program tion and calibration table storage. A byte or word write memory. The EEPGD bit determines if the access will automatically erases the location and writes the new be a program or data memory access. When clear, any data (erase before write). Writing to program memory subsequent operations will work on the EEPROM data will cease operation until the write is complete. The pro- memory. When set, all subsequent operations will gram memory cannot be accessed during the write, operate in the program memory. therefore code cannot execute. During the write opera- Read operations only use one additional bit, RD, which tion, the oscillator continues to clock the peripherals, initiates the read operation from the desired memory and therefore, they continue to operate. Interrupt location. Once this bit is set, the value of the desired events will be detected and essentially “queued” until memory location will be available in the data registers. the write is completed. When the write completes, the This bit cannot be cleared by firmware. It is automati- next instruction in the pipeline is executed and the cally cleared at the end of the read operation. For branch to the interrupt vector address will occur. EEPROM data memory reads, the data will be avail- When interfacing to the program memory block, the able in the EEDATA register in the very next instruction EEDATH:EEDATA registers form a two-byte word, cycle after the RD bit is set. For program memory which holds the 14-bit data for read/write. The reads, the data will be loaded into the EEADRH:EEADR registers form a two-byte word, EEDATH:EEDATA registers, following the second which holds the 13-bit address of the FLASH location instruction after the RD bit is set. being accessed. The PIC16F870/871 devices have 2Kwords of program FLASH with an address range from 0h to 7FFh. The unused upper bits in both the EEDATH and EEDATA registers all read as ‘0’s.  2000-2013 Microchip Technology Inc. DS30569C-page 27

PIC16F870/871 Write operations have two control bits, WR and WREN, cute instructions. The desired memory location pointed and two status bits, WRERR and EEIF. The WREN bit to by EEADRH:EEADR will be erased. Then, the data is used to enable or disable the write operation. When value in EEDATH:EEDATA will be programmed. When WREN is clear, the write operation will be disabled. complete, the EEIF flag bit will be set and the Therefore, the WREN bit must be set before executing microcontroller will continue to execute code. a write operation. The WR bit is used to initiate the write The WRERR bit is used to indicate when the operation. It also is automatically cleared at the end of PIC16F870/871 devices have been reset during a write the write operation. The interrupt flag EEIF is used to operation. WRERR should be cleared after Power-on determine when the memory write completes. This flag Reset. Thereafter, it should be checked on any other must be cleared in software before setting the WR bit. RESET. The WRERR bit is set when a write operation For EEPROM data memory, once the WREN bit and is interrupted by a MCLR Reset, or a WDT Time-out the WR bit have been set, the desired memory address Reset, during normal operation. In these situations, fol- in EEADR will be erased, followed by a write of the data lowing a RESET, the user should check the WRERR bit in EEDATA. This operation takes place in parallel with and rewrite the memory location, if set. The contents of the microcontroller continuing to execute normally. the data registers, address registers and EEPGD bit When the write is complete, the EEIF flag bit will be set. are not affected by either MCLR Reset, or WDT For program memory, once the WREN bit and the WR Time-out Reset, during normal operation. bit have been set, the microcontroller will cease to exe- REGISTER 3-1: EECON1 REGISTER (ADDRESS: 18Ch) R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — — WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory (This bit cannot be changed while a read or write operation is in progress.) bit 6-4 Unimplemented: Read as '0' bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset or any WDT Reset during normal operation) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read. (RD is cleared in hardware. The RD bit can only be set (not cleared) in software.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30569C-page 28  2000-2013 Microchip Technology Inc.

PIC16F870/871 3.3 Reading the EEPROM Data The steps to write to EEPROM data memory are: Memory 1. If step 10 is not implemented, check the WR bit to see if a write is in progress. Reading EEPROM data memory only requires that the 2. Write the address to EEADR. Make sure that the desired address to access be written to the EEADR address is not larger than the memory size of register and clear the EEPGD bit. After the RD bit is set, the PIC16F870/871 devices. data will be available in the EEDATA register on the very next instruction cycle. EEDATA will hold this value 3. Write the 8-bit data value to be programmed in until another read operation is initiated or until it is the EEDATA register. written by firmware. 4. Clear the EEPGD bit to point to EEPROM data memory. The steps to reading the EEPROM data memory are: 5. Set the WREN bit to enable program operations. 1. Write the address to EEDATA. Make sure that 6. Disable interrupts (if enabled). the address is not larger than the memory size of the PIC16F870/871 devices. 7. Execute the special five instruction sequence: 2. Clear the EEPGD bit to point to EEPROM data • Write 55h to EECON2 in two steps (first to W, memory. then to EECON2) 3. Set the RD bit to start the read operation. • Write AAh to EECON2 in two steps (first to W, then to EECON2) 4. Read the data from the EEDATA register. • Set the WR bit EXAMPLE 3-1: EEPROM DATA READ 8. Enable interrupts (if using interrupts). BSF STATUS, RP1 ; 9. Clear the WREN bit to disable program BCF STATUS, RP0 ;Bank 2 operations. MOVF ADDR, W ;Write address 10. At the completion of the write cycle, the WR bit MOVWF EEADR ;to read from is cleared and the EEIF interrupt flag bit is set. BSF STATUS, RP0 ;Bank 3 (EEIF must be cleared by firmware.) If step 1 is BCF EECON1, EEPGD ;Point to Data memory not implemented, then firmware should check BSF EECON1, RD ;Start read operation for EEIF to be set, or WR to clear, to indicate the BCF STATUS, RP0 ;Bank 2 end of the program cycle. MOVF EEDATA, W ;W = EEDATA EXAMPLE 3-2: EEPROM DATA WRITE 3.4 Writing to the EEPROM Data BSF STATUS, RP1 ; Memory BSF STATUS, RP0 ;Bank 3 BTFSCEECON1, WR ;Wait for There are many steps in writing to the EEPROM data GOTO $-1 ;write to finish memory. Both address and data values must be written BCF STATUS, RP0 ;Bank 2 to the SFRs. The EEPGD bit must be cleared, and the MOVF ADDR, W ;Address to WREN bit must be set, to enable writes. The WREN bit MOVWFEEADR ;write to MOVF VALUE, W ;Data to should be kept clear at all times, except when writing to MOVWFEEDATA ;write the EEPROM data. The WR bit can only be set if the BSF STATUS, RP0 ;Bank 3 WREN bit was set in a previous operation (i.e., they BCF EECON1, EEPGD;Point to Data memory both cannot be set in the same operation). The WREN BSF EECON1, WREN ;Enable writes bit should then be cleared by firmware after the write. ;Only disable interrupts Clearing the WREN bit before the write actually BCF INTCON, GIE ;if already enabled, completes will not terminate the write in progress. ;otherwise discard MOVLW0x55 ;Write 55h to Writes to EEPROM data memory must also be pref- MOVWFEECON2 ;EECON2 aced with a special sequence of instructions that pre- MOVLW0xAA ;Write AAh to vent inadvertent write operations. This is a sequence of MOVWFEECON2 ;EECON2 five instructions that must be executed without interrup- BSF EECON1, WR ;Start write operation tions. The firmware should verify that a write is not in ;Only enable interrupts progress before starting another cycle. BSF INTCON, GIE ;if using interrupts, ;otherwise discard BCF EECON1, WREN ;Disable writes  2000-2013 Microchip Technology Inc. DS30569C-page 29

PIC16F870/871 3.5 Reading the FLASH Program 3.6 Writing to the FLASH Program Memory Memory Reading FLASH program memory is much like that of Writing to FLASH program memory is unique, in that EEPROM data memory, only two NOP instructions must the microcontroller does not execute instructions while be inserted after the RD bit is set. These two instruction programming is taking place. The oscillator continues cycles that the NOP instructions execute, will be used by to run and all peripherals continue to operate and the microcontroller to read the data out of program queue interrupts, if enabled. Once the write operation memory and insert the value into the EEDATH:EEDATA completes (specification D133), the processor begins registers. Data will be available following the second executing code from where it left off. The other impor- NOP instruction. EEDATH and EEDATA will hold their tant difference when writing to FLASH program mem- value until another read operation is initiated, or until ory is that the WRT configuration bit, when clear, they are written by firmware. prevents any writes to program memory (see Table3-1). The steps to reading the FLASH program memory are: Just like EEPROM data memory, there are many steps in writing to the FLASH program memory. Both address 1. Write the address to EEADRH:EEADR. Make and data values must be written to the SFRs. The sure that the address is not larger than the EEPGD bit must be set, and the WREN bit must be set memory size of the PIC16F870/871 devices. to enable writes. The WREN bit should be kept clear at 2. Set the EEPGD bit to point to FLASH program all times, except when writing to the FLASH program memory. memory. The WR bit can only be set if the WREN bit 3. Set the RD bit to start the read operation. was set in a previous operation (i.e., they both cannot 4. Execute two NOP instructions to allow the be set in the same operation). The WREN bit should microcontroller to read out of program memory. then be cleared by firmware after the write. Clearing the 5. Read the data from the EEDATH:EEDATA WREN bit before the write actually completes will not registers. terminate the write in progress. Writes to program memory must also be prefaced with EXAMPLE 3-3: FLASH PROGRAM READ a special sequence of instructions that prevent inad- BSF STATUS, RP1 ; vertent write operations. This is a sequence of five BCF STATUS, RP0 ;Bank 2 instructions that must be executed without interruption MOVF ADDRL, W ;Write the for each byte written. These instructions must then be MOVWF EEADR ;address bytes followed by two NOP instructions to allow the microcon- MOVF ADDRH,W ;for the desired troller to setup for the write operation. Once the write is MOVWF EEADRH ;address to read complete, the execution of instructions starts with the BSF STATUS, RP0 ;Bank 3 instruction after the second NOP. BSF EECON1, EEPGD ;Point to Program memory BSF EECON1, RD ;Start read operation The steps to write to program memory are: NOP ;Required two NOPs 1. Write the address to EEADRH:EEADR. Make NOP ; sure that the address is not larger than the BCF STATUS, RP0 ;Bank 2 memory size of the PIC16F870/871 devices. MOVF EEDATA, W ;DATAL = EEDATA MOVWF DATAL ; 2. Write the 14-bit data value to be programmed in MOVF EEDATH,W ;DATAH = EEDATH the EEDATH:EEDATA registers. MOVWF DATAH ; 3. Set the EEPGD bit to point to FLASH program memory. 4. Set the WREN bit to enable program operations. 5. Disable interrupts (if enabled). 6. Execute the special five instruction sequence: • Write 55h to EECON2 in two steps (first to W, then to EECON2) • Write AAh to EECON2 in two steps (first to W, then to EECON2) • Set the WR bit 7. Execute two NOP instructions to allow the microcontroller to setup for write operation. 8. Enable interrupts (if using interrupts). 9. Clear the WREN bit to disable program operations. DS30569C-page 30  2000-2013 Microchip Technology Inc.

PIC16F870/871 At the completion of the write cycle, the WR bit is 3.8 Protection Against Spurious cleared and the EEIF interrupt flag bit is set. (EEIF Writes must be cleared by firmware.) Since the microcontroller does not execute instructions during the write cycle, the There are conditions when the device may not want to firmware does not necessarily have to check either write to the EEPROM data memory or FLASH program EEIF, or WR, to determine if the write had finished. memory. To protect against these spurious write condi- tions, various mechanisms have been built into the EXAMPLE 3-4: FLASH PROGRAM WRITE PIC16F870/871 devices. On power-up, the WREN bit is cleared and the Power-up Timer (if enabled) BSF STATUS, RP1 ; prevents writes. BCF STATUS, RP0 ;Bank 2 MOVF ADDRL, W ;Write address The write initiate sequence and the WREN bit together, MOVWF EEADR ;of desired help prevent any accidental writes during brown-out, MOVF ADDRH, W ;program memory power glitches, or firmware malfunction. MOVWF EEADRH ;location MOVF VALUEL, W ;Write value to 3.9 Operation While Code Protected MOVWF EEDATA ;program at MOVF VALUEH, W ;desired memory The PIC16F870/871 devices have two code protect MOVWF EEDATH ;location mechanisms, one bit for EEPROM data memory and BSF STATUS, RP0 ;Bank 3 two bits for FLASH program memory. Data can be read BSF EECON1, EEPGD ;Point to Program memory BSF EECON1, WREN ;Enable writes and written to the EEPROM data memory, regardless ;Only disable interrupts of the state of the code protection bit, CPD. When code BCF INTCON, GIE ;if already enabled, protection is enabled and CPD cleared, external ;otherwise discard access via ICSP is disabled, regardless of the state of MOVLW 0x55 ;Write 55h to the program memory code protect bits. This prevents MOVWF EECON2 ;EECON2 the contents of EEPROM data memory from being read MOVLW 0xAA ;Write AAh to out of the device. MOVWF EECON2 ;EECON2 BSF EECON1, WR ;Start write operation The state of the program memory code protect bits, NOP ;Two NOPs to allow micro CP0 and CP1, do not affect the execution of instruc- NOP ;to setup for write tions out of program memory. The PIC16F870/871 ;Only enable interrupts devices can always read the values in program mem- BSF INTCON, GIE ;if using interrupts, ory, regardless of the state of the code protect bits. ;otherwise discard However, the state of the code protect bits and the BCF EECON1, WREN ;Disable writes WRT bit will have different effects on writing to program memory. Table 4-1 shows the effect of the code protect bits and the WRT bit on program memory. 3.7 Write Verify Once code protection has been enabled for either The PIC16F870/871 devices do not automatically ver- EEPROM data memory or FLASH program memory, ify the value written during a write operation. Depend- only a full erase of the entire device will disable code ing on the application, good programming practice may protection. dictate that the value written to memory be verified against the original value. This should be used in appli- cations where excessive writes can stress bits near the specified endurance limits.  2000-2013 Microchip Technology Inc. DS30569C-page 31

PIC16F870/871 3.10 FLASH Program Memory Write Protection The configuration word contains a bit that write protects the FLASH program memory, called WRT. This bit can only be accessed when programming the PIC16F870/871 devices via ICSP. Once write protec- tion is enabled, only an erase of the entire device will disable it. When enabled, write protection prevents any writes to FLASH program memory. Write protection does not affect program memory reads. TABLE 3-1: READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY Configuration Bits Internal Internal Memory Location ICSP Read ICSP Write Read Write CP1 CP0 WRT 0 0 x All program memory Yes No No No 0 1 0 Unprotected areas Yes No Yes No 0 1 0 Protected areas Yes No No No 0 1 1 Unprotected areas Yes Yes Yes No 0 1 1 Protected areas Yes No No No 1 0 0 Unprotected areas Yes No Yes No 1 0 0 Protected areas Yes No No No 1 0 1 Unprotected areas Yes Yes Yes No 1 0 1 Protected areas Yes No No No 1 1 0 All program memory Yes No Yes Yes 1 1 1 All program memory Yes Yes Yes Yes TABLE 3-2: REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 10Dh EEADR EEPROM Address Register, Low Byte xxxx xxxx uuuu uuuu 10Fh EEADRH — — — EEPROM Address, High Byte xxxx xxxx uuuu uuuu 10Ch EEDATA EEPROM Data Register, Low Byte xxxx xxxx uuuu uuuu 10Eh EEDATH — — EEPROM Data Register, High Byte xxxx xxxx uuuu uuuu 18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 x--- u000 18Dh EECON2 EEPROM Control Register2 (not a physical register) — — Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'. Shaded cells are not used during FLASH/EEPROM access. Note 1: These bits are reserved; always maintain these bits clear. DS30569C-page 32  2000-2013 Microchip Technology Inc.

PIC16F870/871 4.0 I/O PORTS FIGURE 4-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the Data device. In general, when a peripheral is enabled, that Bus D Q pin may not be used as a general purpose I/O pin. VDD WR Additional information on I/O ports may be found in the Port PIC® Mid-Range MCU Family Reference Manual CK Q P (DS33023). Data Latch 4.1 PORTA and the TRISA Register D Q N I/O pin(1) PORTA is a 6-bit wide bi-directional port. The corre- WR sponding data direction register is TRISA. Setting a TRIS CK Q VSS TRISA bit (= 1) will make the corresponding PORTA pin Analog TRIS Latch Input an input (i.e., put the corresponding output driver in a Mode Hi-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). RD TRIS TTL Input Reading the PORTA register reads the status of the pins, Buffer whereas writing to it will write to the port latch. All write Q D operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. EN Pin RA4 is multiplexed with the Timer0 module clock RD PORT input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. To A/D Converter All other PORTA pins have TTL input levels and full CMOS output drivers. Note1: I/O pins have protection diodes to VDD and VSS. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the FIGURE 4-2: BLOCK DIAGRAM OF ADCON1 register (A/D Control Register 1). RA4/T0CKI PIN Note: On a Power-on Reset, these pins are Data configured as analog inputs and read as Bus D Q '0'. WR PORT The TRISA register controls the direction of the RA CK Q I/O pin(1) N pins, even when they are being used as analog inputs. Data Latch The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. D Q VSS WR TRIS CK Q Schmitt EXAMPLE 4-1: INITIALIZING PORTA Trigger BCF STATUS, RP0 ; TRIS Latch Input Buffer BCF STATUS, RP1 ;Bank0 CLRF PORTA ;Initialize PORTA by ;clearing output RD TRIS ;data latches BSF STATUS, RP0 ;Select Bank 1 Q D MOVLW 0x06 ;Configure all pins MOVWF ADCON1 ;as digital inputs MOVLW 0xCF ;Value used to ENEN ;initialize data RD PORT ;direction MOVWF TRISA ;Set RA<3:0> as TMR0 Clock Input ;inputs ;RA<5:4> as outputs ;TRISA<7:6> are Note1: I/O pin has protection diodes to VSS only. ;always read as '0'.  2000-2013 Microchip Technology Inc. DS30569C-page 33

PIC16F870/871 TABLE 4-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2 bit2 TTL Input/output or analog input. RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF. RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/AN4 bit5 TTL Input/output or analog input. Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. DS30569C-page 34  2000-2013 Microchip Technology Inc.

PIC16F870/871 4.2 PORTB and the TRISB Register This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the PORTB is an 8-bit wide, bi-directional port. The corre- interrupt in the following manner: sponding data direction register is TRISB. Setting a a) Any read or write of PORTB. This will end the TRISB bit (= 1) will make the corresponding PORTB mismatch condition. pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will b) Clear flag bit RBIF. make the corresponding PORTB pin an output (i.e., put A mismatch condition will continue to set flag bit RBIF. the contents of the output latch on the selected pin). Reading PORTB will end the mismatch condition and Three pins of PORTB are multiplexed with the Low allow flag bit RBIF to be cleared. Voltage Programming function: RB3/PGM, RB6/PGC The interrupt-on-change feature is recommended for and RB7/PGD. The alternate functions of these pins wake-up on key depression operation and operations are described in the Special Features Section. where PORTB is only used for the interrupt-on-change Each of the PORTB pins has a weak internal pull-up. A feature. Polling of PORTB is not recommended while single control bit can turn on all the pull-ups. This is per- using the interrupt-on-change feature. formed by clearing bit RBPU (OPTION_REG<7>). The This interrupt on mismatch feature, together with soft- weak pull-up is automatically turned off when the port ware configurable pull-ups on these four pins, allow pin is configured as an output. The pull-ups are easy interface to a keypad and make it possible for disabled on a Power-on Reset. wake-up on key-depression. Refer to the Embedded Control Handbook, “Implementing Wake-up on Key FIGURE 4-3: BLOCK DIAGRAM OF Stroke” (AN552). RB3:RB0 PINS RB0/INT is an external interrupt input pin and is VDD configured using the INTEDG bit (OPTION_REG<6>). RBPU(2) Weak RB0/INT is discussed in detail in Section11.10.1. PPull-up Data Latch Data Bus FIGURE 4-4: BLOCK DIAGRAM OF D Q RB7:RB4 PINS WR Port I/O pin(1) CK VDD TRIS Latch RBPU(2) Weak D Q P Pull-up TTL Data Latch WR TRIS CK IBnupfufetr Data Bus D Q I/O pin(1) WR Port CK TRIS Latch RD TRIS D Q Q D WR TRIS TTL CK Input RD Port EN Buffer ST Buffer RB0/INT RB3/PGM RD TRIS Latch Schmitt Trigger RD Port Q D Buffer Note1: I/O pins have diode protection to VDD and VSS. RD Port EN Q1 2: To enable weak pull-ups, set the appropriate TRIS Set RBIF bit(s) and clear the RBPU bit (OPTION_REG<7>). From other Q D Four of PORTB’s pins, RB7:RB4, have an interrupt-on- RB7:RB4 pins RD Port change feature. Only pins configured as inputs can EN Q3 cause this interrupt to occur (i.e., any RB7:RB4 pin RB7:RB6 in Serial Programming Mode configured as an output is excluded from the interrupt- on-change comparison). The input pins (of RB7:RB4) Note1: I/O pins have diode protection to VDD and VSS. are compared with the old value latched on the last 2: To enable weak pull-ups, set the appropriate TRIS read of PORTB. The “mismatch” outputs of RB7:RB4 bit(s) and clear the RBPU bit (OPTION_REG<7>). are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).  2000-2013 Microchip Technology Inc. DS30569C-page 35

PIC16F870/871 TABLE 4-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3/PGM bit3 TTL/ST(1) Input/output pin or programming pin in LVP mode. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB6/PGC bit6 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming clock. RB7/PGD bit7 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30569C-page 36  2000-2013 Microchip Technology Inc.

PIC16F870/871 4.3 PORTC and the TRISC Register FIGURE 4-5: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT PORTC is an 8-bit wide, bi-directional port. The corre- OVERRIDE) sponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC Port/Peripheral Select(2) pin an input (i.e., put the corresponding output driver in Peripheral Data Out a Hi-Impedance mode). Clearing a TRISC bit (= 0) will 0 VDD Data Bus make the corresponding PORTC pin an output (i.e., put WR D Q 1 P the contents of the output latch on the selected pin). PORT CK Q PORTC is multiplexed with several peripheral functions Data Latch (Table4-5). PORTC pins have Schmitt Trigger input D Q I/O buffers. WR pin(1) TRIS When enabling peripheral functions, care should be CK Q N taken in defining TRIS bits for each PORTC pin. Some TRIS Latch peripherals override the TRIS bit to make a pin an out- Vss put, while other peripherals override the TRIS bit to Schmitt make a pin an input. Since the TRIS bit override is in RD TRIS Trigger effect while the peripheral is enabled, read-modify- Peripheral write instructions (BSF, BCF, XORWF) with TRISC as OE(3) Q D the destination should be avoided. The user should EN refer to the corresponding peripheral section for the RD PORT correct TRIS bit settings. Peripheral Input Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral Select signal selects between port data and peripheral output. 3: Peripheral OE (Output Enable) is only activated if Peripheral Select is active. TABLE 4-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input. RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. RC3 bit3 ST Input/output port pin. RC4 bit4 ST Input/output port pin. RC5 bit5 ST Input/output port pin. RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive or Synchronous Data. Legend: ST = Schmitt Trigger input TABLE 4-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged  2000-2013 Microchip Technology Inc. DS30569C-page 37

PIC16F870/871 4.4 PORTD and TRISD Registers FIGURE 4-6: PORTD BLOCK DIAGRAM (IN I/O PORT MODE) This section is not applicable to the PIC16F870. PORTD is an 8-bit port with Schmitt Trigger input buff- Data Bus ers. Each pin is individually configurable as an input or D Q output. WPoRrt I/O pin(1) CK PORTD can be configured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit Data Latch PSPMODE (TRISE<4>). In this mode, the input buffers D Q are TTL. WR TRIS CK Schmitt Trigger TRIS Latch Input Buffer RD TRIS Q D ENEN RD Port Note 1: I/O pins have protection diodes to VDD and VSS. TABLE 4-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0. RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1. RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2. RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3. RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4. RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5. RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6. RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. TABLE 4-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD. DS30569C-page 38  2000-2013 Microchip Technology Inc.

PIC16F870/871 4.5 PORTE and TRISE Register FIGURE 4-7: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) This section is not applicable to the PIC16F870. Data PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 Bus D Q and RE2/CS/AN7, which are individually configurable WR as inputs or outputs. These pins have Schmitt Trigger PORT I/O pin(1) CK input buffers. Data Latch I/O PORTE becomes control inputs for the micropro- cessor port when bit PSPMODE (TRISE<4>) is set. In D Q this mode, the user must make sure that the WR TRISE<2:0> bits are set (pins are configured as digital TRIS CK Schmitt Trigger inputs). Ensure ADCON1 is configured for digital I/O. In TRIS Latch input this mode, the input buffers are TTL. buffer Register4-1 shows the TRISE register, which also controls the parallel slave port operation. RD TRIS PORTE pins are multiplexed with analog inputs. When selected as an analog input, these pins will read as '0's. Q D TRISE controls the direction of the RE pins, even when EN they are being used as analog inputs. The user must RD PORT make sure to keep the pins configured as inputs when using them as analog inputs. Note 1: I/O pins have protection diodes to VDD and VSS. Note: On a Power-on Reset, these pins are configured as analog inputs.  2000-2013 Microchip Technology Inc. DS30569C-page 39

PIC16F870/871 REGISTER 4-1: TRISE REGISTER (ADDRESS: 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — Bit2 Bit1 Bit0 bit 7 bit 0 bit 7 Parallel Slave Port Status/Control Bits IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3 Unimplemented: Read as '0' PORTE Data Direction Bits bit 2 Bit2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output bit 1 Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0 Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30569C-page 40  2000-2013 Microchip Technology Inc.

PIC16F870/871 TABLE 4-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/RD/AN5 bit0 ST/TTL(1) Input/output port pin or read control input in Parallel Slave Port mode or analog input: RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected.) RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in Parallel Slave Port mode or analog input: WR 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected). RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in Parallel Slave Port mode or analog input: CS 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. TABLE 4-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on Value on: Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.  2000-2013 Microchip Technology Inc. DS30569C-page 41

PIC16F870/871 4.6 Parallel Slave Port FIGURE 4-8: PORTD AND PORTE BLOCK DIAGRAM The Parallel Slave Port is not implemented on the (PARALLEL SLAVE PORT) PIC16F870. PORTD operates as an 8-bit wide Parallel Slave Port or microprocessor port when control bit PSPMODE Data Bus D Q (TRISE<4>) is set. In Slave mode, it is asynchronously WR readable and writable by the external world through RD RDx Port control input pin RE0/RD and WR control input pin CK pin RE1/WR. TTL It can directly interface to an 8-bit microprocessor data Q D bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE RD ENEN enables port pin RE0/RD to be the RD input, RE1/WR Port to be the WR input and RE2/CS to be the CS (chip One bit of PORTD select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) Set Interrupt Flag must be configured as inputs (set). The A/D port config- PSPIF (PIR1<7>) uration bits PCFG3:PCFG0 (ADCON1<3:0>) must be set to configure pins RE2:RE0 as digital I/O. There are actually two 8-bit latches. One for data out- put and one for data input. The user writes 8-bit data to Read TTL RD the PORTD data latch and reads data from the port pin latch (note that they have the same address). In this Chip Select TTL CS mode, the TRISD register is ignored, since the microprocessor is controlling the direction of data flow. Write TTL WR A write to the PSP occurs when both the CS and WR lines are first detected low. When either the CS or WR Note: I/O pin has protection diodes to VDD and VSS. lines become high (level triggered), the Input Buffer Full (IBF) status flag bit (TRISE<7>) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is complete (Figure4-9). The interrupt flag bit, PSPIF (PIR1<7>), is also set on the same Q4 clock cycle. IBF can only be cleared by reading the PORTD input latch. The Input Buffer Overflow (IBOV) status flag bit (TRISE<5>) is set if a second write to the PSP is attempted when the previous byte has not been read out of the buffer. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full (OBF) status flag bit (TRISE<6>) is cleared immedi- ately (Figure4-10), indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the inter- rupt flag bit PSPIF is set on the Q4 clock cycle, follow- ing the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware. When not in PSP mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previously set, it must be cleared in firmware. An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>). DS30569C-page 42  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 4-9: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 4-10: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 4-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 08h PORTD Port Data Latch when written: Port pins when read xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 0Ch PIR1 PSPIF ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.  2000-2013 Microchip Technology Inc. DS30569C-page 43

PIC16F870/871 NOTES: DS30569C-page 44  2000-2013 Microchip Technology Inc.

PIC16F870/871 5.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will The Timer0 module timer/counter has the following increment either on every rising, or falling edge of pin features: RA4/T0CKI. The incrementing edge is determined by • 8-bit timer/counter the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the ris- • Readable and writable ing edge. Restrictions on the external clock input are • 8-bit software programmable prescaler discussed in detail in Section5.2. • Internal or external clock select The prescaler is mutually exclusively shared between • Interrupt on overflow from FFh to 00h the Timer0 module and the Watchdog Timer. The pres- • Edge select for external clock caler is not readable or writable. Section5.3 details the Figure5-1 is a block diagram of the Timer0 module and operation of the prescaler. the prescaler shared with the WDT. 5.1 Timer0 Interrupt Additional information on the Timer0 module is avail- able in the PIC® Mid-Range MCU Family Reference The TMR0 interrupt is generated when the TMR0 reg- Manual (DS33023). ister overflows from FFh to 00h. This overflow sets bit Timer mode is selected by clearing bit T0CS T0IF (INTCON<2>). The interrupt can be masked by (OPTION_REG<5>). In Timer mode, the Timer0 mod- clearing bit T0IE (INTCON<5>). Bit T0IF must be ule will increment every instruction cycle (without pres- cleared in software by the Timer0 module Interrupt Ser- caler). If the TMR0 register is written, the increment is vice Routine before re-enabling this interrupt. The inhibited for the following two instruction cycles. The TMR0 interrupt cannot awaken the processor from user can work around this by writing an adjusted value SLEEP, since the timer is shut-off during SLEEP. to the TMR0 register. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKO (= FOSC/4) Data Bus 8 M 0 1 RA4/T0CKI U M SYNC pin 1 X 0 U 2 TMR0 Reg X Cycles T0SE T0CS PSA Set Flag Bit T0IF on Overflow PRESCALER 0 8-bit Prescaler M U Watchdog 1 X 8 Timer 8 - to - 1MUX PS2:PS0 PSA 0 1 WDT Enable bit M U X PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).  2000-2013 Microchip Technology Inc. DS30569C-page 45

PIC16F870/871 5.2 Using Timer0 with an External 5.3 Prescaler Clock There is only one prescaler available, which is mutually When no prescaler is used, the external clock input is exclusively shared between the Timer0 module and the the same as the prescaler output. The synchronization Watchdog Timer. A prescaler assignment for the of T0CKI with the internal phase clocks is accom- Timer0 module means that there is no prescaler for the plished by sampling the prescaler output on the Q2 and Watchdog Timer, and vice-versa. This prescaler is not Q4 cycles of the internal phase clocks. Therefore, it is readable or writable (see Figure5-1). necessary for T0CKI to be high for at least 2 TOSC (and The PSA and PS2:PS0 bits (OPTION_REG<3:0>) a small RC delay of 20 ns) and low for at least 2 TOSC determine the prescaler assignment and prescale ratio. (and a small RC delay of 20 ns). Refer to the electrical When assigned to the Timer0 module, all instructions specification of the desired device. writing to the TMR0 register (e.g., CLRF1, MOVWF1, BSF1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. Note: Writing to TMR0 when the prescaler is assigned to Timer0, will clear the prescaler count, but will not change the prescaler assignment. REGISTER 5-1: OPTION_REG REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU bit 6 INTEDG bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: To avoid an unintended device RESET, the instruction sequence shown in the PIC® Mid-Range MCU Fam- ily Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. DS30569C-page 46  2000-2013 Microchip Technology Inc.

PIC16F870/871 TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 01h,101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.  2000-2013 Microchip Technology Inc. DS30569C-page 47

PIC16F870/871 NOTES: DS30569C-page 48  2000-2013 Microchip Technology Inc.

PIC16F870/871 6.0 TIMER1 MODULE In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising The Timer1 module is a 16-bit timer/counter consisting edge of the external clock input. of two 8-bit registers (TMR1H and TMR1L), which are Timer1 can be enabled/disabled by setting/clearing readable and writable. The TMR1 register pair control bit, TMR1ON (T1CON<0>). (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, Timer1 also has an internal “RESET input”. This is generated on overflow, which is latched in interrupt RESET can be generated by either of the two CCP flag bit, TMR1IF (PIR1<0>). This interrupt can be modules (Section8.0). Register6-1 shows the Timer1 enabled/disabled by setting/clearing TMR1 interrupt control register. enable bit, TMR1IE (PIE1<0>). When the Timer1 oscillator is enabled (T1OSCEN is Timer1 can operate in one of two modes: set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is • As a timer ignored, and these pins read as ‘0’. • As a counter Additional information on timer modules is available in The Operating mode is determined by the clock select the PIC® Mid-Range MCU Family Reference Manual bit, TMR1CS (T1CON<1>). (DS33023). REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2000-2013 Microchip Technology Inc. DS30569C-page 49

PIC16F870/871 6.1 Timer1 Operation in Timer Mode 6.2 Timer1 Counter Operation Timer mode is selected by clearing the TMR1CS Timer1 may operate in either a Synchronous, or an (T1CON<1>) bit. In this mode, the input clock to the Asynchronous mode, depending on the setting of the timer is FOSC/4. The synchronize control bit, T1SYNC TMR1CS bit. (T1CON<2>), has no effect, since the internal clock is When Timer1 is being incremented via an external always in sync. source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment. FIGURE 6-1: TIMER1 INCREMENTING EDGE T1CKI (Default High) T1CKI (Default Low) Note: Arrows indicate counter increments. 6.3 Timer1 Operation in Synchronized If T1SYNC is cleared, then the external clock input is Counter Mode synchronized with internal phase clocks. The synchro- nization is done after the prescaler stage. The Counter mode is selected by setting bit TMR1CS. In prescaler stage is an asynchronous ripple counter. this mode, the timer increments on every rising edge of In this configuration, during SLEEP mode, Timer1 will clock input on pin RC1/T1OSI, when bit T1OSCEN is not increment even if the external clock is present, set, or on pin RC0/T1OSO/T1CKI, when bit T1OSCEN since the synchronization circuit is shut-off. The is cleared. prescaler, however, will continue to increment. FIGURE 6-2: TIMER1 BLOCK DIAGRAM Set Flag bit TMR1IF on Overflow Synchronized TMR1 0 Clock Input TMR1H TMR1L 1 TMR1ON On/Off T1SYNC T1OSC RC0/T1OSO/T1CKI 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 RC1/T1OSI Oscillator(1) Clock 2 Q Clock T1CKPS1:T1CKPS0 TMR1CS Note1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. DS30569C-page 50  2000-2013 Microchip Technology Inc.

PIC16F870/871 6.4 Timer1 Operation in TABLE 6-1: CAPACITOR SELECTION FOR Asynchronous Counter Mode THE TIMER1 OSCILLATOR If control bit T1SYNC (T1CON<2>) is set, the external Osc Type Freq. C1 C2 clock input is not synchronized. The timer continues to LP 32 kHz 33 pF 33 pF increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can 100 kHz 15 pF 15 pF generate an interrupt-on-overflow, which will wake-up 200 kHz 15 pF 15 pF the processor. However, special precautions in These values are for design guidance only. software are needed to read/write the timer (Section6.4.1). Crystals Tested: In Asynchronous Counter mode, Timer1 cannot be 32.768 kHz Epson C-001R32.768K-A ± 20 PPM used as a time base for capture or compare operations. 100 kHz Epson C-2 100.00 KC-P ± 20 PPM 6.4.1 READING AND WRITING TIMER1 IN 200 kHz STD XTL 200.000 kHz ± 20 PPM ASYNCHRONOUS COUNTER Note 1: Higher capacitance increases the stability MODE of oscillator, but also increases the start-up time. Reading TMR1H or TMR1L while the timer is running 2: Since each resonator/crystal has its own from an external asynchronous clock, will ensure a characteristics, the user should consult the valid read (taken care of in hardware). However, the resonator/crystal manufacturer for user should keep in mind that reading the 16-bit timer appropriate values of external components. in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. 6.6 Resetting Timer1 Using a CCP For writes, it is recommended that the user simply stop Trigger Output the timer and write the desired values. A write conten- tion may occur by writing to the timer registers, while If the CCP1 module is configured in Compare mode to the register is incrementing. This may produce an generate a “special event trigger” (CCP1M3:CCP1M0 unpredictable value in the timer register. = 1011), this signal will reset Timer1. Reading the 16-bit value requires some care. Note: The special event triggers from the CCP1 Examples 12-2 and 12-3 in the PIC® Mid-Range MCU module will not set interrupt flag bit Family Reference Manual (DS33023) show how to TMR1IF (PIR1<0>). read and write Timer1 when it is running in Asynchronous mode. Timer1 must be configured for either Timer or Synchro- nized Counter mode to take advantage of this feature. 6.5 Timer1 Oscillator If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. A crystal oscillator circuit is built-in between pins T1OSI In the event that a write to Timer1 coincides with a (input) and T1OSO (amplifier output). It is enabled by special event trigger from CCP1, the write will take setting control bit, T1OSCEN (T1CON<3>). The oscil- precedence. lator is a low power oscillator, rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended In this mode of operation, the CCPRH:CCPRL register for use with a 32 kHz crystal. Table6-1 shows the pair effectively becomes the period register for Timer1. capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.  2000-2013 Microchip Technology Inc. DS30569C-page 51

PIC16F870/871 6.7 Resetting of Timer1 Register Pair 6.8 Timer1 Prescaler (TMR1H, TMR1L) The prescaler counter is cleared on writes to the TMR1H and TMR1L registers are not reset to 00h on a TMR1H or TMR1L registers. POR, or any other RESET, except by the CCP1 special event trigger. T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected. TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. DS30569C-page 52  2000-2013 Microchip Technology Inc.

PIC16F870/871 7.0 TIMER2 MODULE Register7-1 shows the Timer2 control register. Additional information on timer modules is available in Timer2 is an 8-bit timer with a prescaler and a the PIC® Mid-Range MCU Family Reference Manual postscaler. It can be used as the PWM time base for the (DS33023). PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device FIGURE 7-1: TIMER2 BLOCK DIAGRAM RESET. The input clock (FOSC/4) has a prescale option of 1:1, Sets Flag TMR2 1:4, or 1:16, selected by control bits bit TMR2IF Output(1) T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. RESET TMR2 Reg Prescaler FOSC/4 1:1, 1:4, 1:16 Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is Postscaler Comparator 2 a readable and writable register. The PR2 register is 1:1 to 1:16 EQ T2CKPS1: initialized to FFh upon RESET. 4 PR2 Reg T2CKPS0 The match output of TMR2 goes through a 4-bit T2OUTPS3: postscaler (which gives a 1:1 to 1:16 scaling inclusive) T2OUTPS0 to generate a TMR2 interrupt (latched in flag bit Note1: TMR2 register output can be software selected by the TMR2IF (PIR1<1>)). SSP module as a baud clock. Timer2 can be shut-off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2000-2013 Microchip Technology Inc. DS30569C-page 53

PIC16F870/871 7.1 Timer2 Prescaler and Postscaler 7.2 Output of TMR2 The prescaler and postscaler counters are cleared The output of TMR2 (before the postscaler) is fed to the when any of the following occurs: SSP module, which optionally uses it to generate shift clock. • a write to the TMR2 register • a write to the T2CON register • any device RESET (POR, MCLR Reset, WDT Reset, or BOR) TMR2 is not cleared when T2CON is written. TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. DS30569C-page 54  2000-2013 Microchip Technology Inc.

PIC16F870/871 8.0 CAPTURE/COMPARE/PWM Additional information on CCP modules is available in MODULES the PIC® Mid-Range MCU Family Reference Manual (DS33023) and in application note AN594, “Using the Each Capture/Compare/PWM (CCP) module contains CCP Modules” (DS00594). a 16-bit register which can operate as a: TABLE 8-1: CCP MODE - TIMER • 16-bit Capture register RESOURCES REQUIRED • 16-bit Compare register • PWM Master/Slave Duty Cycle register CCP Mode Timer Resource Table8-1 shows the resources and interactions of the Capture Timer1 CCP module. In the following sections, the operation of Compare Timer1 a CCP module is described. PWM Timer2 8.1 CCP1 Module Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled). REGISTER 8-1: CCP1CON REGISTER REGISTER (ADDRESS: 17h/1Dh) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 CCP1X:CCP1Y: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M3:CCP1M0: CCP1 Mode Select bits 0000 =Capture/Compare/PWM disabled (resets CCP1 module) 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, set output on match (CCP1IF bit is set) 1001 =Compare mode, clear output on match (CCP1IF bit is set) 1010 =Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 =Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected); CCP1resets TMR1, and starts an A/D conversion (if A/D module is enabled) 11xx =PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2000-2013 Microchip Technology Inc. DS30569C-page 55

PIC16F870/871 8.2 Capture Mode 8.2.2 TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode, or Synchro- 16-bit value of the TMR1 register when an event occurs nized Counter mode, for the CCP module to use the on pin RC2/CCP1. An event is defined as one of the capture feature. In Asynchronous Counter mode, the following: capture operation may not work. • Every falling edge 8.2.3 SOFTWARE INTERRUPT • Every rising edge When the Capture mode is changed, a false capture • Every 4th rising edge interrupt may be generated. The user should keep bit • Every 16th rising edge CCP1IE (PIE1<2>) clear to avoid false interrupts and The type of event is configured by control bits should clear the flag bit, CCP1IF, following any such change in Operating mode. CCP1M3:CCP1M0 (CCP1CON<3:0>). When a cap- ture is made, the interrupt request flag bit CCP1IF 8.2.4 CCP PRESCALER (PIR1<2>) is set. The interrupt flag must be cleared in software. If another capture occurs before the value in There are four prescaler settings, specified by bits register CCPR1 is read, the old captured value is CCP1M3:CCP1M0. Whenever the CCP module is overwritten by the new value. turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any RESET will clear 8.2.1 CCP PIN CONFIGURATION the prescaler counter. In Capture mode, the RC2/CCP1 pin should be Switching from one capture prescaler to another may configured as an input by setting the TRISC<2> bit. generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from Note: If the RC2/CCP1 pin is configured as an a non-zero prescaler. Example8-1 shows the recom- output, a write to the port can cause a mended method for switching between capture pres- capture condition. calers. This example also clears the prescaler counter and will not generate the “false” interrupt. FIGURE 8-1: CAPTURE MODE OPERATION BLOCK EXAMPLE 8-1: CHANGING BETWEEN DIAGRAM CAPTURE PRESCALERS RC2/CCP1 Set Flag bit CCP1IF CLRF CCP1CON ; Turn CCP module off pin (PIR1<2>) Prescaler MOVLW NEW_CAPT_PS ; Load the W reg with  1, 4, 16 ; the new prescaler CCPR1H CCPR1L ; move value and CCP ON MOVWF CCP1CON ; Load CCP1CON with this and Capture ; value Edge Detect Enable TMR1H TMR1L CCP1CON<3:0> Qs DS30569C-page 56  2000-2013 Microchip Technology Inc.

PIC16F870/871 8.3 Compare Mode 8.3.2 TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is Timer1 must be running in Timer mode, or Synchro- constantly compared against the TMR1 register pair nized Counter mode, if the CCP module is using the value. When a match occurs, the RC2/CCP1 pin is: compare feature. In Asynchronous Counter mode, the compare operation may not work. • Driven high • Driven low 8.3.3 SOFTWARE INTERRUPT MODE • Remains unchanged When Generate Software Interrupt mode is chosen, the The action on the pin is based on the value of control CCP1 pin is not affected. The CCPIF bit is set, causing bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the a CCP interrupt (if enabled). same time, interrupt flag bit CCP1IF is set. 8.3.4 SPECIAL EVENT TRIGGER FIGURE 8-2: COMPARE MODE In this mode, an internal hardware trigger is generated, OPERATION BLOCK which may be used to initiate an action. DIAGRAM The special event trigger output of CCP1 resets the TMR1 register pair, and starts an A/D conversion (if A/D Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), module is enabled). This allows the CCPR1 register to and set bit GO/DONE (ADCON0<2>). effectively be a 16-bit programmable period register for Timer1. Special Event Trigger Note: The special event trigger from the CCP1 Set Flag bit CCP1IF module will not set interrupt flag bit (PIR1<2>) RC2/CCP1 CCPR1H CCPR1L TMR1IF (PIR1<0>). pin Q S Output R Logic Match Comparator TRISC<2> TMR1H TMR1L Output Enable CCP1CON<3:0> Mode Select 8.3.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch.  2000-2013 Microchip Technology Inc. DS30569C-page 57

PIC16F870/871 8.4 PWM Mode (PWM) 8.4.1 PWM PERIOD In Pulse Width Modulation mode, the CCP1 pin pro- The PWM period is specified by writing to the PR2 duces up to a 10-bit resolution PWM output. Since the register. The PWM period can be calculated using the CCP1 pin is multiplexed with the PORTC data latch, the following formula: TRISC<2> bit must be cleared to make the CCP1 pin PWM period =[(PR2) + 1] • 4 (cid:129) TOSC (cid:129) an output. (TMR2 prescale value) Note: Clearing the CCP1CON register will force PWM frequency is defined as 1 / [PWM period]. the CCP1 PWM output latch to the default When TMR2 is equal to PR2, the following three events low level. This is not the PORTC I/O data occur on the next increment cycle: latch. • TMR2 is cleared Figure8-3 shows a simplified block diagram of the • The CCP1 pin is set (exception: if PWM duty CCP module in PWM mode. cycle=0%, the CCP1 pin will not be set) For a step-by-step procedure on how to set up the CCP • The PWM duty cycle is latched from CCPR1L into module for PWM operation, see Section8.4.3. CCPR1H FIGURE 8-3: SIMPLIFIED PWM BLOCK Note: The Timer2 postscaler (see Section7.1) is DIAGRAM not used in the determination of the PWM frequency. The postscaler could be used CCP1CON<5:4> Duty Cycle Registers to have a servo update rate at a different CCPR1L frequency than the PWM output. 8.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1H (Slave) CCPR1L register and to the CCP1CON<5:4> bits. Up RC2/CCP1 to 10-bit resolution is available. The CCPR1L contains Comparator R Q the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is TMR2 (Note 1) used to calculate the PWM duty cycle in time: S PWM duty cycle =(CCPR1L:CCP1CON<5:4>) (cid:129) Comparator TRISC<2> TOSC (cid:129) (TMR2 prescale value) Clear Timer, CCP1 pin and CCPR1L and CCP1CON<5:4> can be written to at any latch D.C. PR2 time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 Note1: The 8-bit timer is concatenated with 2-bit internal Q occurs (i.e., the period is complete). In PWM mode, clock, or 2 bits of the prescaler, to create 10-bit time CCPR1H is a read-only register. base. The CCPR1H register and a 2-bit internal latch are A PWM output (Figure8-4) has a time base (period) used to double buffer the PWM duty cycle. This double and a time that the output stays high (duty cycle). The buffering is essential for glitch-free PWM operation. frequency of the PWM is the inverse of the period When the CCPR1H and 2-bit latch match TMR2, con- (1/period). catenated with an internal 2-bit Q clock, or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. FIGURE 8-4: PWM OUTPUT The maximum PWM resolution (bits) for a given PWM Period frequency is given by the formula: (FOSC ) log Resolution = FPWM bits log(2) Duty Cycle TMR2 = PR2 Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be TMR2 = Duty Cycle cleared. TMR2 = PR2 DS30569C-page 58  2000-2013 Microchip Technology Inc.

PIC16F870/871 8.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 register. 2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. 4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. 5. Configure the CCP1 module for PWM operation. TABLE 8-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFFh 0xFFh 0xFFh 0x3Fh 0x1Fh 0x17h Maximum Resolution (bits) 10 10 10 8 7 6.5 TABLE 8-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: The PSP is not implemented on the PIC16F870; always maintain these bits clear.  2000-2013 Microchip Technology Inc. DS30569C-page 59

PIC16F870/871 TABLE 8-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000 92h PR2 Timer2 Module’s Period Register 1111 1111 1111 1111 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. DS30569C-page 60  2000-2013 Microchip Technology Inc.

PIC16F870/871 9.0 ADDRESSABLE UNIVERSAL The USART can be configured in the following modes: SYNCHRONOUS • Asynchronous (full-duplex) ASYNCHRONOUS RECEIVER • Synchronous - Master (half-duplex) TRANSMITTER (USART) • Synchronous - Slave (half-duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to The Universal Synchronous Asynchronous Receiver be set in order to configure pins RC6/TX/CK and Transmitter (USART) module is one of the two serial RC7/RX/DT as the Universal Synchronous I/O modules. (USART is also known as a Serial Com- Asynchronous Receiver Transmitter. munications Interface or SCI.) The USART can be con- figured as a full duplex asynchronous system that can The USART module also has a multi-processor communicate with peripheral devices, such as CRT ter- communication capability using 9-bit address minals and personal computers, or it can be configured detection. as a half-duplex synchronous system that can commu- nicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. REGISTER 9-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as '0' bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data, can be parity bit Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2000-2013 Microchip Technology Inc. DS30569C-page 61

PIC16F870/871 REGISTER 9-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode - master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - slave: Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30569C-page 62  2000-2013 Microchip Technology Inc.

PIC16F870/871 9.1 USART Baud Rate Generator It may be advantageous to use the high baud rate (BRG) (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the The BRG supports both the Asynchronous and Syn- baud rate error in some cases. chronous modes of the USART. It is a dedicated 8-bit Writing a new value to the SPBRG register causes the baud rate generator. The SPBRG register controls the BRG timer to be reset (or cleared). This ensures the period of a free running 8-bit timer. In Asynchronous BRG does not wait for a timer overflow before mode, bit BRGH (TXSTA<2>) also controls the baud outputting the new baud rate. rate. In Synchronous mode, bit BRGH is ignored. Table9-1 shows the formula for computation of the 9.1.1 SAMPLING baud rate for different USART modes which only apply in Master mode (internal clock). The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a Given the desired baud rate and FOSC, the nearest low level is present at the RX pin. integer value for the SPBRG register can be calculated using the formula in Table9-1. From this, the error in baud rate can be determined. TABLE 9-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate = FOSC/(16(X+1)) 1 (Synchronous) Baud Rate = FOSC/(4(X+1)) N/A Legend: X = value in SPBRG (0 to 255) TABLE 9-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.  2000-2013 Microchip Technology Inc. DS30569C-page 63

PIC16F870/871 TABLE 9-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz BAUD RATE SPBRG SPBRG SPBRG % % % (K) value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) 0.3 - - - - - - - - - 1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129 2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64 9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15 19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7 28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4 33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4 57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2 HIGH 1.221 - 255 0.977 - 255 0.610 - 255 LOW 312.500 - 0 250.000 - 0 156.250 - 0 FOSC = 4 MHz FOSC = 3.6864 MHz BAUD RATE SPBRG SPBRG % % (K) value value ERROR ERROR KBAUD (decimal) KBAUD (decimal) 0.3 0.300 0 207 0.3 0 191 1.2 1.202 0.17 51 1.2 0 47 2.4 2.404 0.17 25 2.4 0 23 9.6 8.929 6.99 6 9.6 0 5 19.2 20.833 8.51 2 19.2 0 2 28.8 31.250 8.51 1 28.8 0 1 33.6 - - - - - - 57.6 62.500 8.51 0 57.6 0 0 HIGH 0.244 - 255 0.225 - 255 LOW 62.500 - 0 57.6 - 0 DS30569C-page 64  2000-2013 Microchip Technology Inc.

PIC16F870/871 TABLE 9-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz BAUD RATE SPBRG SPBRG SPBRG % % % (K) value value value KBAUD ERROR KBAUD ERROR KBAUD ERROR (decimal) (decimal) (decimal) 0.3 - - - - - - - - - 1.2 - - - - - - - - - 2.4 - - - - - - 2.441 1.71 255 9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64 19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31 28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21 33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18 57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10 HIGH 4.883 - 255 3.906 - 255 2.441 - 255 LOW 1250.000 - 0 1000.000 0 625.000 - 0 FOSC = 4 MHz FOSC = 3.6864 MHz BAUD RATE SPBRG SPBRG % % (K) value value ERROR ERROR KBAUD (decimal) KBAUD (decimal) 0.3 - - - - - - 1.2 1.202 0.17 207 1.2 0 191 2.4 2.404 0.17 103 2.4 0 95 9.6 9.615 0.16 25 9.6 0 23 19.2 19.231 0.16 12 19.2 0 11 28.8 27.798 3.55 8 28.8 0 7 33.6 35.714 6.29 6 32.9 2.04 6 57.6 62.500 8.51 3 57.6 0 3 HIGH 0.977 - 255 0.9 - 255 LOW 250.000 - 0 230.4 - 0  2000-2013 Microchip Technology Inc. DS30569C-page 65

PIC16F870/871 9.2 USART Asynchronous Mode enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the In this mode, the USART uses standard non-return-to- state of enable bit TXIE and cannot be cleared in soft- zero (NRZ) format (one START bit, eight or nine data ware. It will reset only when new data is loaded into the bits, and one STOP bit). The most common data format TXREG register. While flag bit TXIF indicates the status is 8-bits. An on-chip, dedicated, 8-bit baud rate gener- of the TXREG register, another bit, TRMT (TXSTA<1>), ator can be used to derive standard baud rate frequen- shows the status of the TSR register. Status bit TRMT cies from the oscillator. The USART transmits and is a read only bit, which is set when the TSR register is receives the LSb first. The transmitter and receiver are empty. No interrupt logic is tied to this bit, so the user functionally independent, but use the same data format has to poll this bit in order to determine if the TSR and baud rate. The baud rate generator produces a register is empty. clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by Note1: The TSR register is not mapped in data the hardware, but can be implemented in software (and memory, so it is not available to the user. stored as the ninth data bit). Asynchronous mode is 2: Flag bit TXIF is set when enable bit TXEN stopped during SLEEP. is set. TXIF is cleared by loading TXREG. Asynchronous mode is selected by clearing bit SYNC Transmission is enabled by setting enable bit TXEN (TXSTA<4>). (TXSTA<5>). The actual transmission will not occur The USART Asynchronous module consists of the until the TXREG register has been loaded with data following important elements: and the baud rate generator (BRG) has produced a shift clock (Figure9-2). The transmission can also be • Baud Rate Generator started by first loading the TXREG register and then • Sampling Circuit setting enable bit TXEN. Normally, when transmission • Asynchronous Transmitter is first started, the TSR register is empty. At that point, • Asynchronous Receiver transfer to the TXREG register will result in an immedi- ate transfer to TSR, resulting in an empty TXREG. A 9.2.1 USART ASYNCHRONOUS back-to-back transfer is thus possible (Figure9-3). TRANSMITTER Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the The USART transmitter block diagram is shown in transmitter. As a result, the RC6/TX/CK pin will revert Figure9-1. The heart of the transmitter is the Transmit to hi-impedance. (Serial) Shift register (TSR). The Shift register obtains its data from the read/write transmit buffer, TXREG. The In order to select 9-bit transmission, transmit bit TX9 TXREG register is loaded with data in software. The (TXSTA<6>) should be set and the ninth bit should be TSR register is not loaded until the STOP bit has been written to TX9D (TXSTA<0>). The ninth bit must be transmitted from the previous load. As soon as the written before writing the 8-bit data to the TXREG reg- STOP bit is transmitted, the TSR is loaded with new ister. This is because a data write to the TXREG regis- data from the TXREG register (if available). Once the ter can result in an immediate transfer of the data to the TXREG register transfers the data to the TSR register TSR register (if the TSR is empty). In such a case, an (occurs in one TCY), the TXREG register is empty and incorrect ninth data bit may be loaded in the TSR flag bit TXIF (PIR1<4>) is set. This interrupt can be register. FIGURE 9-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8)  0 Pin Buffer and Control TSR Register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D DS30569C-page 66  2000-2013 Microchip Technology Inc.

PIC16F870/871 When setting up an Asynchronous Transmission, 5. Enable the transmission by setting bit TXEN, follow these steps: which will also set bit TXIF. 1. Initialize the SPBRG register for the appropriate 6. If 9-bit transmission is selected, the ninth bit baud rate. If a high speed baud rate is desired, should be loaded in bit TX9D. set bit BRGH (Section9.1). 7. Load data to the TXREG register (starts 2. Enable the asynchronous serial port by clearing transmission). bit SYNC and setting bit SPEN. 8. If using interrupts, ensure that GIE and PEIE 3. If interrupts are desired, then set enable bit (bits 7 and 6) of the INTCON register are set. TXIE. 4. If 9-bit transmission is desired, then set transmit bit TX9. FIGURE 9-2: ASYNCHRONOUS MASTER TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK (pin) START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit Word 1 (Transmit Shift Transmit Shift Reg Reg. Empty Flag) FIGURE 9-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) RC6/TX/CK (pin) START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit START Bit Bit 0 TXIF bit Word 1 Word 2 (Interrupt Reg. Flag) T(RTReragMn. TsE mmbiitpt tSyh Fifltag) TWraonrds m1it Shift Reg. WTraonrds m2it Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 9-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.  2000-2013 Microchip Technology Inc. DS30569C-page 67

PIC16F870/871 9.2.2 USART ASYNCHRONOUS is possible for two bytes of data to be received and RECEIVER transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of The receiver block diagram is shown in Figure9-4. The the STOP bit of the third byte, if the RCREG register is data is received on the RC7/RX/DT pin and drives the still full, the overrun error bit OERR (RCSTA<1>) will be data recovery block. The data recovery block is actually set. The word in the RSR will be lost. The RCREG reg- a high speed shifter, operating at x16 times the baud ister can be read twice to retrieve the two bytes in the rate; whereas, the main receive serial shifter operates FIFO. Overrun bit OERR has to be cleared in software. at the bit rate or at FOSC. This is done by resetting the receive logic (CREN is Once Asynchronous mode is selected, reception is cleared and then set). If bit OERR is set, transfers from enabled by setting bit CREN (RCSTA<4>). the RSR register to the RCREG register are inhibited, The heart of the receiver is the Receive (Serial) Shift and no further data will be received. It is therefore, register (RSR). After sampling the STOP bit, the essential to clear error bit OERR if it is set. Framing received data in the RSR is transferred to the RCREG error bit FERR (RCSTA<2>) is set if a STOP bit is register (if it is empty). If the transfer is complete, flag detected as clear. Bit FERR and the 9th receive bit are bit RCIF (PIR1<5>) is set. The actual interrupt can be buffered the same way as the receive data. Reading enabled/disabled by setting/clearing enable bit RCIE the RCREG will load bits RX9D and FERR with new (PIE1<5>). Flag bit RCIF is a read only bit, which is values, therefore, it is essential for the user to read the cleared by the hardware. It is cleared when the RCREG RCSTA register before reading the RCREG register in order not to lose the old FERR and RX9D information. register has been read and is empty. The RCREG is a double-buffered register (i.e., it is a two-deep FIFO). It FIGURE 9-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN FOSC SPBRG 64 MSb RSR Register LSb or Baud Rate Generator 16 STOP (8) 7  1 0 START RC7/RX/DT Pin Buffer Data and Control Recovery RX9 SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF Data Bus RCIE FIGURE 9-5: ASYNCHRONOUS RECEPTION RX (pin) START START START bit bit0 bit1 bit7/8 STOP bit bit0 bit7/8 STOP bit bit7/8 STOP bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS30569C-page 68  2000-2013 Microchip Technology Inc.

PIC16F870/871 When setting up an Asynchronous Reception, follow 6. Flag bit RCIF will be set when reception is com- these steps: plete and an interrupt will be generated if enable bit RCIE is set. 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, 7. Read the RCSTA register to get the ninth bit (if set bit BRGH (Section9.1). enabled) and determine if any error occurred during reception. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 8. Read the 8-bit received data by reading the RCREG register. 3. If interrupts are desired, then set enable bit RCIE. 9. If any error occurred, clear the error by clearing enable bit CREN. 4. If 9-bit reception is desired, then set bit RX9. 10. If using interrupts, ensure that GIE and PEIE 5. Enable the reception by setting bit CREN. (bits 7 and 6) of the INTCON register are set. TABLE 9-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.  2000-2013 Microchip Technology Inc. DS30569C-page 69

PIC16F870/871 9.2.3 SETTING UP 9-BIT MODE WITH • Flag bit RCIF will be set when reception is com- ADDRESS DETECT plete, and an interrupt will be generated if enable bit RCIE was set. When setting up an Asynchronous Reception with • Read the RCSTA register to get the ninth bit and Address Detect enabled: determine if any error occurred during reception. • Initialize the SPBRG register for the appropriate • Read the 8-bit received data by reading the baud rate. If a high speed baud rate is desired, set RCREG register, to determine if the device is bit BRGH. being addressed. • Enable the asynchronous serial port by clearing • If any error occurred, clear the error by clearing bit SYNC and setting bit SPEN. enable bit CREN. • If interrupts are desired, then set enable bit RCIE. • If the device has been addressed, clear the • Set bit RX9 to enable 9-bit reception. ADDEN bit to allow data bytes and address bytes • Set ADDEN to enable address detect. to be read into the receive buffer, and interrupt the • Enable the reception by setting enable bit CREN. CPU. FIGURE 9-6: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN FOSC SPBRG  64 MSb RSR Register LSb or Baud Rate Generator  16 STOP (8) 7  1 0 START RC7/RX/DT Pin Buffer Data and Control Recovery RX9 8 SPEN RX9 Enable ADDEN Load of Receive RX9 Buffer ADDEN RSR<8> 8 RX9D RCREG Register FIFO 8 Interrupt RCIF Data Bus RCIE DS30569C-page 70  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 9-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT RC7/RX/DT (pin) START START bit bit0 bit1 bit8 STOP bit bit0 bit8 STOP bit bit Load RSR Bit8 = 0, Data Byte Bit8 = 1, Address Byte Word 1 RCREG Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN = 1. FIGURE 9-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST RC7/RX/DT (pin) START START bit bit0 bit1 bit8 STOP bit bit0 bit8 STOP bit bit Load RSR Bit8 = 1, Address Byte Bit8 = 0, Data Byte Word 1 RCREG Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN was not updated and still = 0. TABLE 9-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.  2000-2013 Microchip Technology Inc. DS30569C-page 71

PIC16F870/871 9.3 USART Synchronous Clearing enable bit TXEN during a transmission will Master Mode cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to hi- In Synchronous Master mode, the data is transmitted in impedance. If either bit CREN or bit SREN is set during a half-duplex manner (i.e., transmission and reception a transmission, the transmission is aborted and the DT do not occur at the same time). When transmitting data, pin reverts to a hi-impedance state (for a reception). the reception is inhibited and vice versa. Synchronous The CK pin will remain an output if bit CSRC is set mode is entered by setting bit SYNC (TXSTA<4>). In (internal clock). The transmitter logic, however, is not addition, enable bit SPEN (RCSTA<7>) is set in order reset, although it is disconnected from the pins. In order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to reset the transmitter, the user has to clear bit TXEN. to CK (clock) and DT (data) lines, respectively. The If bit SREN is set (to interrupt an on-going transmission Master mode indicates that the processor transmits the and receive a single word), then after the single word is master clock on the CK line. The Master mode is received, bit SREN will be cleared and the serial port entered by setting bit CSRC (TXSTA<7>). will revert back to transmitting, since bit TXEN is still set. The DT line will immediately switch from Hi- 9.3.1 USART SYNCHRONOUS MASTER Impedance Receive mode to transmit and start driving. TRANSMISSION To avoid this, bit TXEN should be cleared. The USART transmitter block diagram is shown in In order to select 9-bit transmission, the TX9 Figure9-6. The heart of the transmitter is the Transmit (TXSTA<6>) bit should be set and the ninth bit should (Serial) Shift register (TSR). The Shift register obtains be written to bit TX9D (TXSTA<0>). The ninth bit must its data from the Read/Write Transmit Buffer register be written before writing the 8-bit data to the TXREG TXREG. The TXREG register is loaded with data in register. This is because a data write to the TXREG can software. The TSR register is not loaded until the last result in an immediate transfer of the data to the TSR bit has been transmitted from the previous load. As register (if the TSR is empty). If the TSR was empty and soon as the last bit is transmitted, the TSR is loaded the TXREG was written before writing the “new” TX9D, with new data from the TXREG (if available). Once the the “present” value of bit TX9D is loaded. TXREG register transfers the data to the TSR register Steps to follow when setting up a Synchronous Master (occurs in one TCYCLE), the TXREG is empty and inter- Transmission: rupt bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE 1. Initialize the SPBRG register for the appropriate (PIE1<4>). Flag bit TXIF will be set, regardless of the baud rate (Section9.1). state of enable bit TXIE and cannot be cleared in soft- 2. Enable the synchronous master serial port by ware. It will reset only when new data is loaded into the setting bits SYNC, SPEN and CSRC. TXREG register. While flag bit TXIF indicates the status 3. If interrupts are desired, set enable bit TXIE. of the TXREG register, another bit TRMT (TXSTA<1>) 4. If 9-bit transmission is desired, set bit TX9. shows the status of the TSR register. TRMT is a read 5. Enable the transmission by setting bit TXEN. only bit which is set when the TSR is empty. No inter- rupt logic is tied to this bit, so the user has to poll this 6. If 9-bit transmission is selected, the ninth bit bit in order to determine if the TSR register is empty. should be loaded in bit TX9D. The TSR is not mapped in data memory, so it is not 7. Start transmission by loading data to the TXREG available to the user. register. Transmission is enabled by setting enable bit TXEN 8. If using interrupts, ensure that GIE and PEIE (TXSTA<5>). The actual transmission will not occur (bits 7 and 6) of the INTCON register are set. until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is sta- ble around the falling edge of the synchronous clock (Figure9-9). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure9-10). This is advantageous when slow baud rates are selected, since the BRG is kept in RESET when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally, when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible. DS30569C-page 72  2000-2013 Microchip Technology Inc.

PIC16F870/871 TABLE 9-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. FIGURE 9-9: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX/CK pin Write to TXREG reg Write Word1 Write Word2 TXIF bit (Interrupt Flag) TRMT bit '1' '1' TXEN bit Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words. FIGURE 9-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit0 bit1 bit2 bit6 bit7 RC6/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit  2000-2013 Microchip Technology Inc. DS30569C-page 73

PIC16F870/871 9.3.2 USART SYNCHRONOUS MASTER When setting up a Synchronous Master Reception: RECEPTION 1. Initialize the SPBRG register for the appropriate Once Synchronous mode is selected, reception is baud rate (Section9.1). enabled by setting either enable bit SREN 2. Enable the synchronous master serial port by (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is setting bits SYNC, SPEN and CSRC. sampled on the RC7/RX/DT pin on the falling edge of 3. Ensure bits CREN and SREN are clear. the clock. If enable bit SREN is set, then only a single 4. If interrupts are desired, then set enable bit word is received. If enable bit CREN is set, the recep- RCIE. tion is continuous until CREN is cleared. If both bits are 5. If 9-bit reception is desired, then set bit RX9. set, CREN takes precedence. After clocking the last bit, the received data in the Receive Shift register (RSR) is 6. If a single reception is required, set bit SREN. transferred to the RCREG register (if it is empty). When For continuous reception, set bit CREN. the transfer is complete, interrupt flag bit RCIF 7. Interrupt flag bit RCIF will be set when reception (PIR1<5>) is set. The actual interrupt can be enabled/ is complete and an interrupt will be generated if disabled by setting/clearing enable bit RCIE enable bit RCIE was set. (PIE1<5>). Flag bit RCIF is a read only bit, which is 8. Read the RCSTA register to get the ninth bit (if reset by the hardware. In this case, it is reset when the enabled) and determine if any error occurred RCREG register has been read and is empty. The during reception. RCREG is a double-buffered register (i.e., it is a two- 9. Read the 8-bit received data by reading the deep FIFO). It is possible for two bytes of data to be RCREG register. received and transferred to the RCREG FIFO and a 10. If any error occurred, clear the error by clearing third byte to begin shifting into the RSR register. On the bit CREN. clocking of the last bit of the third byte, if the RCREG 11. If using interrupts, ensure that GIE and PEIE register is still full, then overrun error bit OERR (bits 7 and 6) of the INTCON register are set. (RCSTA<1>) is set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, so it is essential to clear bit OERR if it is set. The ninth receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG, in order not to lose the old RX9D information. DS30569C-page 74  2000-2013 Microchip Technology Inc.

PIC16F870/871 TABLE 9-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. FIGURE 9-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.  2000-2013 Microchip Technology Inc. DS30569C-page 75

PIC16F870/871 9.4 USART Synchronous Slave Mode When setting up a Synchronous Slave Transmission, follow these steps: Synchronous Slave mode differs from the Master mode 1. Enable the synchronous slave serial port by set- in the fact that the shift clock is supplied externally at ting bits SYNC and SPEN and clearing bit the RC6/TX/CK pin (instead of being supplied internally CSRC. in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is 2. Clear bits CREN and SREN. entered by clearing bit CSRC (TXSTA<7>). 3. If interrupts are desired, then set enable bit TXIE. 9.4.1 USART SYNCHRONOUS SLAVE 4. If 9-bit transmission is desired, then set bit TX9. TRANSMIT 5. Enable the transmission by setting enable bit The operation of the Synchronous Master and Slave TXEN. modes is identical, except in the case of the SLEEP mode. 6. If 9-bit transmission is selected, the ninth bit If two words are written to the TXREG and then the should be loaded in bit TX9D. SLEEP instruction is executed, the following will occur: 7. Start transmission by loading data to the TXREG register. a) The first word will immediately transfer to the TSR register and transmit. 8. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. b) The second word will remain in TXREG register. c) Flag bit TXIF will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. e) If enable bit TXIE is set, the interrupt will wake the chip from SLEEP and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). TABLE 9-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear. DS30569C-page 76  2000-2013 Microchip Technology Inc.

PIC16F870/871 9.4.2 USART SYNCHRONOUS SLAVE When setting up a Synchronous Slave Reception, RECEPTION follow these steps: The operation of the Synchronous Master and Slave 1. Enable the synchronous master serial port by modes is identical, except in the case of the SLEEP setting bits SYNC and SPEN and clearing bit mode. Bit SREN is a “don't care” in Slave mode. CSRC. 2. If interrupts are desired, set enable bit RCIE. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during 3. If 9-bit reception is desired, set bit RX9. SLEEP. On completely receiving the word, the RSR 4. To enable reception, set enable bit CREN. register will transfer the data to the RCREG register 5. Flag bit RCIF will be set when reception is com- and if enable bit RCIE bit is set, the interrupt generated plete and an interrupt will be generated, if will wake the chip from SLEEP. If the global interrupt is enable bit RCIE was set. enabled, the program will branch to the interrupt vector 6. Read the RCSTA register to get the ninth bit (if (0004h). enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register. 8. If any error occurred, clear the error by clearing bit CREN. 9. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. TABLE 9-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870, always maintain these bits clear.  2000-2013 Microchip Technology Inc. DS30569C-page 77

PIC16F870/871 NOTES: DS30569C-page 78  2000-2013 Microchip Technology Inc.

PIC16F870/871 10.0 ANALOG-TO-DIGITAL (A/D) The A/D module has four registers. These registers CONVERTER MODULE are: • A/D Result High Register (ADRESH) The Analog-to-Digital (A/D) Converter module has five • A/D Result Low Register (ADRESL) inputs for the 28-pin devices and eight for the other • A/D Control Register0 (ADCON0) devices. • A/D Control Register1 (ADCON1) The analog input charges a sample and hold capacitor. The output of the sample and hold capacitor is the input The ADCON0 register, shown in Register10-1, con- into the converter. The converter then generates a dig- trols the operation of the A/D module. The ADCON1 ital result of this analog level via successive approxima- register, shown in Register10-2, configures the func- tion. The A/D conversion of the analog input signal tions of the port pins. The port pins can be configured results in a corresponding 10-bit digital number. The as analog inputs (RA3 can also be the voltage A/D module has high and low voltage reference input reference), or as digital I/O. that is software selectable to some combination of VDD, Additional information on using the A/D module can be VSS, RA2, or RA3. found in the PIC® Mid-Range MCU Family Reference The A/D converter has a unique feature of being able Manual (DS33023). to operate while the device is in SLEEP mode. To oper- ate in SLEEP, the A/D clock must be derived from the A/D’s internal RC oscillator. REGISTER 10-1: ADCON0 REGISTER (ADDRESS: 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal A/D module RC oscillator) bit 5-3 CHS2:CHS0: Analog Channel Select bits 000 = Channel 0, (RA0/AN0) 010 = Channel 2, (RA2/AN2) 011 = Channel 3, (RA3/AN3) 100 = Channel 4, (RA5/AN4) 101 = Channel 5, (RE0/AN5)(1) 110 = Channel 6, (RE1/AN6)(1) 111 = Channel 7, (RE2/AN7)(1) bit 2 GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete) bit 1 Unimplemented: Read as '0' bit 0 ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Note1: These channels are not available on the PIC16F870 device. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2000-2013 Microchip Technology Inc. DS30569C-page 79

PIC16F870/871 REGISTER 10-2: ADCON1 REGISTER (ADDRESS: 9Fh) U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’. bit 6-4 Unimplemented: Read as '0' bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits: PCFG3: AN7(1) AN6(1) AN5(1) AN4 AN3 AN2 AN1 AN0 CHAN/ PCFG0 RE2 RE1 RE0 RA5 RA3 RA2 RA1 RA0 VREF+ VREF- Refs(2) 0000 A A A A A A A A VDD VSS 8/0 0001 A A A A VREF+ A A A RA3 VSS 7/1 0010 D D D A A A A A VDD VSS 5/0 0011 D D D A VREF+ A A A RA3 VSS 4/1 0100 D D D D A D A A VDD VSS 3/0 0101 D D D D VREF+ D A A RA3 VSS 2/1 011x D D D D D D D D VDD VSS 0/0 1000 A A A A VREF+ VREF- A A RA3 RA2 6/2 1001 D D A A A A A A VDD VSS 6/0 1010 D D A A VREF+ A A A RA3 VSS 5/1 1011 D D A A VREF+ VREF- A A RA3 RA2 4/2 1100 D D D A VREF+ VREF- A A RA3 RA2 3/2 1101 D D D D VREF+ VREF- A A RA3 RA2 2/2 1110 D D D D D D D A VDD VSS 1/0 1111 D D D D VREF+ VREF- D A RA3 RA2 1/2 A = Analog input D = Digital I/O Note1: These channels are not available on the PIC16F870 device. 2: This column indicates the number of analog channels available as A/D inputs and the number of analog channels used as voltage reference inputs. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown The ADRESH:ADRESL registers contain the 10-bit To determine sample time, see Section10.1. After this result of the A/D conversion. When the A/D conversion acquisition time has elapsed, the A/D conversion can is complete, the result is loaded into this A/D result reg- be started. ister pair, the GO/DONE bit (ADCON0<2>) is cleared and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure10-1. After the A/D module has been configured as desired, the selected channel must be acquired before the con- version is started. The analog input channels must have their corresponding TRIS bits selected as inputs. DS30569C-page 80  2000-2013 Microchip Technology Inc.

PIC16F870/871 These steps should be followed for doing an A/D 3. Wait the required acquisition time. Conversion: 4. Start conversion: 1. Configure the A/D module: • Set GO/DONE bit (ADCON0) • Configure analog pins/voltage reference and 5. Wait for A/D conversion to complete, by either: digital I/O (ADCON1) • Polling for the GO/DONE bit to be cleared • Select A/D input channel (ADCON0) (with interrupts enabled); OR • Select A/D conversion clock (ADCON0) • Waiting for the A/D interrupt • Turn on A/D module (ADCON0) 6. Read A/D Result register pair 2. Configure A/D interrupt (if desired): (ADRESH:ADRESL), clear bit ADIF if required. • Clear ADIF bit 7. For the next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is • Set ADIE bit defined as TAD. A minimum wait of 2 TAD is • Set PEIE bit required before the next acquisition starts. • Set GIE bit FIGURE 10-1: A/D BLOCK DIAGRAM CHS2:CHS0 111 RE2/AN7(1) 110 RE1/AN6(1) 101 RE0/AN5(1) 100 RA5/AN4 VAIN 011 (Input Voltage) RA3/AN3/VREF+ 010 A/D RA2/AN2/VREF- Converter 001 RA1/AN1 000 VDD RA0/AN0 VREF+ (Reference Voltage) PCFG3:PCFG0 VREF- (Reference Voltage) VSS PCFG3:PCFG0 Note 1: Not available on the PIC16F870 device.  2000-2013 Microchip Technology Inc. DS30569C-page 81

PIC16F870/871 10.1 A/D Acquisition Requirements be decreased. After the analog input channel is selected (changed), this acquisition must be done For the A/D converter to meet its specified accuracy, before the conversion can be started. the charge holding capacitor (CHOLD) must be allowed To calculate the minimum acquisition time, to fully charge to the input channel voltage level. The Equation10-1 may be used. This equation assumes analog input model is shown in Figure10-2. The that 1/2 LSb error is used (1024 steps for the A/D). The source impedance (RS) and the internal sampling 1/2 LSb error is the maximum error allowed for the A/D switch (RSS) impedance directly affect the time to meet its specified resolution. required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage To calculate the minimum acquisition time, TACQ, see (VDD), see Figure10-2. The maximum recom- the PIC® Mid-Range MCU Family Reference Manual mended impedance for analog sources is 10 k. As (DS33023). the impedance is decreased, the acquisition time may EQUATION 10-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2 s + TC + [(Temperature – 25°C)(0.05 s/°C)] TC = CHOLD (RIC + RSS + RS) In(1/2047) = - 120 pF (1 k + 7 k + 10 k) In(0.0004885) = 16.47 s TACQ = 2 s + 16.47 s + [(50°C – 25C)(0.05 s/C) = 19.72 s Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again. During this time, the holding capacitor is not connected to the selected A/D input channel. FIGURE 10-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC  1k SS RSS CHOLD VA C5 PpIFN VT = 0.6V I± L5E0A0K AnGAE == 1D2A0C p cFapacitance VSS Legend CPIN = input capacitance 6V VT = threshold voltage 5V I LEAKAGE = leakage current at the pin due to VDD4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5 6 7 891011 Sampling Switch (k) DS30569C-page 82  2000-2013 Microchip Technology Inc.

PIC16F870/871 10.2 Selecting the A/D Conversion For correct A/D conversions, the A/D conversion clock Clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. The A/D conversion time per bit is defined as TAD. The Table10-1 shows the resultant TAD times derived from A/D conversion requires a minimum 12 TAD per 10-bit the device operating frequencies and the A/D clock conversion. The source of the A/D conversion clock is source selected. software selected. The four possible options for TAD are: • 2 TOSC • 8 TOSC • 32 TOSC • Internal A/D module RC oscillator (2-6 s) TABLE 10-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C)) AD Clock Source (TAD) Maximum Device Frequency Operation ADCS1:ADCS0 Max. 2 TOSC 00 1.25 MHz 8 TOSC 01 5 MHz 32 TOSC 10 20 MHz RC(1, 2, 3) 11 (Note 1) Note 1: The RC source has a typical TAD time of 4 s, but can vary between 2-6 s. 2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for SLEEP operation. 3: For extended voltage devices (LC), please refer to the Electrical Characteristics (Section14.1 and 14.2). 10.3 Configuring Analog Port Pins Note1: When reading the port register, any pin configured as an analog input channel will The ADCON1 and TRIS registers control the operation read as cleared (a low level). Pins config- of the A/D port pins. The port pins that are desired as ured as digital inputs will convert an ana- analog inputs must have their corresponding TRIS bits log input. Analog levels on a digitally set (input). If the TRIS bit is cleared (output), the digital configured input will not affect the output level (VOH or VOL) will be converted. conversion accuracy. The A/D operation is independent of the state of the 2: Analog levels on any pin that is defined as CHS2:CHS0 bits and the TRIS bits. a digital input (including the AN7:AN0 pins), may cause the input buffer to con- sume current that is out of the device specifications.  2000-2013 Microchip Technology Inc. DS30569C-page 83

PIC16F870/871 10.4 A/D Conversions acquisition is started. After this 2 TAD wait, acquisition on the selected channel is automatically started. The Clearing the GO/DONE bit during a conversion will GO/DONE bit can then be set to start the conversion. abort the current conversion. The A/D result register In Figure10-3, after the GO bit is set, the first time pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL segment has a minimum of TCY and a maximum of TAD. registers will continue to contain the value of the last Note: The GO/DONE bit should NOT be set in completed conversion (or the last value written to the the same instruction that turns on the A/D. ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2 TAD wait is required before the next FIGURE 10-3: A/D CONVERSION TAD CYCLES TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit ADRES is loaded GO bit is cleared ADIF bit is set Holding capacitor is connected to analog input 10.4.1 A/D RESULT REGISTERS mat Select bit (ADFM) controls this justification. Figure10-4 shows the operation of the A/D result justifi- The ADRESH:ADRESL register pair is the location cation. The extra bits are loaded with ‘0’. When an A/D where the 10-bit A/D result is loaded at the completion of result will not overwrite these locations (A/D disable), the A/D conversion. This register pair is 16-bits wide. these registers may be used as two general purpose The A/D module gives the flexibility to left or right justify 8-bit registers. the 10-bit result in the 16-bit result register. The A/D For- FIGURE 10-4: A/D RESULT JUSTIFICATION 10-bit Result ADFM = 1 ADFM = 0 7 2 1 0 7 0 7 0 7 6 5 0 0000 00 0000 00 ADRESH ADRESL ADRESH ADRESL 10-bit Result 10-bit Result Right Justified Left Justified DS30569C-page 84  2000-2013 Microchip Technology Inc.

PIC16F870/871 10.5 A/D Operation During SLEEP Turning off the A/D places the A/D module in its lowest current consumption state. The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC Note: For the A/D module to operate in SLEEP, (ADCS1:ADCS0 = 11). When the RC clock source is the A/D clock source must be set to RC selected, the A/D module waits one instruction cycle (ADCS1:ADCS0 = 11). To allow the con- before starting the conversion. This allows the SLEEP version to occur during SLEEP, ensure the instruction to be executed, which eliminates all digital SLEEP instruction immediately follows the switching noise from the conversion. When the conver- instruction that sets the GO/DONE bit. sion is completed, the GO/DONE bit will be cleared and the result loaded into the ADRES register. If the A/D 10.6 Effects of a RESET interrupt is enabled, the device will wake-up from A device RESET forces all registers to their RESET SLEEP. If the A/D interrupt is not enabled, the A/D mod- state. This forces the A/D module to be turned off, and ule will then be turned off, although the ADON bit will any conversion is aborted. All A/D input pins are remain set. configured as analog inputs. When the A/D clock source is another clock option (not The value that is in the ADRESH:ADRESL registers is RC), a SLEEP instruction will cause the present conver- not modified for a Power-on Reset. The sion to be aborted and the A/D module to be turned off, ADRESH:ADRESL registers will contain unknown data though the ADON bit will remain set. after a Power-on Reset. TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH A/D Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCLR, POR, BOR WDT 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 89h(1) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 09h(1) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: These registers/bits are not available on the 28-pin devices.  2000-2013 Microchip Technology Inc. DS30569C-page 85

PIC16F870/871 NOTES: DS30569C-page 86  2000-2013 Microchip Technology Inc.

PIC16F870/871 11.0 SPECIAL FEATURES OF THE SLEEP mode is designed to offer a very low current CPU Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer The PIC16F870/871 devices have a host of features Wake-up, or through an interrupt. intended to maximize system reliability, minimize cost Several oscillator options are also made available to through elimination of external components, provide allow the part to fit the application. The RC oscillator Power Saving Operating modes and offer code option saves system cost while the LP crystal option protection. These are: saves power. A set of configuration bits is used to • Oscillator Selection select various options. • RESET Additional information on special features is available - Power-on Reset (POR) in the PIC® Mid-Range MCU Family Reference Manual - Power-up Timer (PWRT) (DS33023). - Oscillator Start-up Timer (OST) 11.1 Configuration Bits - Brown-out Reset (BOR) • Interrupts The configuration bits can be programmed (read as '0'), • Watchdog Timer (WDT) or left unprogrammed (read as '1'), to select various device configurations. The erased, or unprogrammed • SLEEP value of the configuration word is 3FFFh. These bits • Code Protection are mapped in program memory location 2007h. • ID Locations It is important to note that address 2007h is beyond the • In-Circuit Serial Programming user program memory space, which can be accessed • Low Voltage In-Circuit Serial Programming only during programming. • In-Circuit Debugger PIC16F870/871 devices have a Watchdog Timer, which can be shut-off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nomi- nal) on power-up only. It is designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry.  2000-2013 Microchip Technology Inc. DS30569C-page 87

PIC16F870/871 REGISTER 11-1: CONFIGURATION WORD (ADDRESS 2007h)(1) CP1 CP0 DEBUG — WRT CPD LVP BOREN CP1 CP0 PWRTEN WDTEN FOSC1 FOSC0 bit 13 bit 0 bit 13-12, CP1:CP0: FLASH Program Memory Code Protection bits(2) bit 5-4 11 = Code protection off 10 = Not supported 01 = Not supported 00 = Code protection on bit 11 DEBUG: In-Circuit Debugger Mode 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger bit 10 Unimplemented: Read as ‘1’ bit 9 WRT: FLASH Program Memory Write Enable 1 = Unprotected program memory may be written to by EECON control 0 = Unprotected program memory may not be written to by EECON control bit 8 CPD: Data EE Memory Code Protection 1 = Code protection off 0 = Data EEPROM memory code protected bit 7 LVP: Low Voltage In-Circuit Serial Programming Enable bit 1 = RB3/PGM pin has PGM function, low voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming bit 6 BOREN: Brown-out Reset Enable bit(3) 1 = BOR enabled 0 = BOR disabled bit 3 PWRTEN: Power-up Timer Enable bit(3) 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note1: The erased (unprogrammed) value of the configuration word is 3FFFh. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 3: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTEN. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled. DS30569C-page 88  2000-2013 Microchip Technology Inc.

PIC16F870/871 11.2 Oscillator Configurations FIGURE 11-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP 11.2.1 OSCILLATOR TYPES OSC CONFIGURATION) The PIC16F870/871 can be operated in four different Oscillator modes. The user can program two configura- tion bits (FOSC1 and FOSC0) to select one of these Clock from OSC1 four modes: Ext. System PIC16F870/871 • LP Low Power Crystal Open OSC2 • XT Crystal/Resonator • HS High Speed Crystal/Resonator • RC Resistor/Capacitor 11.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS TABLE 11-1: CERAMIC RESONATORS In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKI and OSC2/CLKO pins Ranges Tested: to establish oscillation (Figure11-1). The PIC16F870/ Mode Freq. OSC1 OSC2 871 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency XT 455 kHz 68 - 100 pF 68 - 100 pF out of the crystal manufacturers specifications. When in 2.0 MHz 15 - 68 pF 15 - 68 pF XT, LP or HS modes, the device can have an external 4.0 MHz 15 - 68 pF 15 - 68 pF clock source to drive the OSC1/CLKI pin (Figure11-2). HS 8.0 MHz 10 - 68 pF 10 - 68 pF 16.0 MHz 10 - 22 pF 10 - 22 pF FIGURE 11-1: CRYSTAL/CERAMIC These values are for design guidance only. RESONATOR OPERATION See notes following Table11-2. (HS, XT OR LP Resonators Used: OSC CONFIGURATION) 455 kHz Panasonic EFO-A455K04B  0.3% C1(1) OSC1 2.0 MHz Murata Erie CSA2.00MG  0.5% To 4.0 MHz Murata Erie CSA4.00MG  0.5% Internal XTAL RF(3) Logic 8.0 MHz Murata Erie CSA8.00MT  0.5% OSC2 16.0 MHz Murata Erie CSA16.00MX  0.5% SLEEP R (2) All resonators used did not have built-in capacitors. s C2(1) PIC16F870/871 Note 1: See Table11-1 and Table11-2 for recommended values of C1 and C2. 2: A series resistor (R ) may be required for s AT strip cut crystals. 3: RF varies with the crystal chosen.  2000-2013 Microchip Technology Inc. DS30569C-page 89

PIC16F870/871 TABLE 11-2: CAPACITOR SELECTION FOR 11.2.3 RC OSCILLATOR CRYSTAL OSCILLATOR For timing insensitive applications, the “RC” device Crystal Cap. Range Cap. Range option offers additional cost savings. The RC oscillator Osc Type Freq. C1 C2 frequency is a function of the supply voltage, the resis- tor (REXT) and capacitor (CEXT) values, and the operat- LP 32 kHz 33 pF 33 pF ing temperature. In addition to this, the oscillator 200 kHz 15 pF 15 pF frequency will vary from unit to unit due to normal pro- cess parameter variation. Furthermore, the difference XT 200 kHz 47-68 pF 47-68 pF in lead frame capacitance between package types will 1 MHz 15 pF 15 pF also affect the oscillation frequency, especially for low 4 MHz 15 pF 15 pF CEXT values. The user also needs to take into account HS 4 MHz 15 pF 15 pF variation due to tolerance of external R and C components used. Figure11-3 shows how the R/C 8 MHz 15-33 pF 15-33 pF combination is connected to the PIC16F870/871. 20 MHz 15-33 pF 15-33 pF These values are for design guidance only. FIGURE 11-3: RC OSCILLATOR MODE See notes following this table. Crystals Used VDD 32 kHz Epson C-001R32.768K-A ± 20 PPM REXT 200 kHz STD XTL 200.000KHz ± 20 PPM OSC1 Internal Clock 1 MHz ECS ECS-10-13-1 ± 50 PPM 4 MHz ECS ECS-40-20-1 ± 50 PPM CEXT PIC16F870/871 8 MHz EPSON CA-301 8.000M-C ± 30 PPM VSS OSC2/CLKO 20 MHz EPSON CA-301 20.000M-C ± 30 PPM FOSC/4 Recommended values: 3 k  REXT  100 k Note1: Higher capacitance increases the stability CEXT > 20pF of oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: R may be required in HS mode, as well s as XT mode, to avoid overdriving crystals with low drive level specification. 4: When migrating from other PIC® devices, oscillator performance should be verified. DS30569C-page 90  2000-2013 Microchip Technology Inc.

PIC16F870/871 11.3 RESET SLEEP, and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the The PIC16F870/871 differentiates between various resumption of normal operation. The TO and PD bits kinds of RESET: are set or cleared differently in different RESET situa- • Power-on Reset (POR) tions, as indicated in Table11-4. These bits are used in • MCLR Reset during normal operation software to determine the nature of the RESET. See Table11-6 for a full description of RESET states of all • MCLR Reset during SLEEP registers. • WDT Reset (during normal operation) A simplified block diagram of the On-Chip Reset Circuit • WDT Wake-up (during SLEEP) is shown in Figure11-4. • Brown-out Reset (BOR) These devices have a MCLR noise filter in the MCLR Some registers are not affected in any RESET condi- Reset path. The filter will detect and ignore small tion. Their status is unknown on POR and unchanged pulses. in any other RESET. Most other registers are reset to a “RESET state” on Power-on Reset (POR), on the It should be noted that a WDT Reset does not drive MCLR and WDT Reset, on MCLR Reset during MCLR pin low. FIGURE 11-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External RESET MCLR SLEEP WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out Reset BOREN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1 (1) PWRT On-chip RC OSC 10-bit Ripple Counter Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.  2000-2013 Microchip Technology Inc. DS30569C-page 91

PIC16F870/871 11.4 Power-on Reset (POR) 11.7 Brown-out Reset (BOR) A Power-on Reset pulse is generated on-chip when The configuration bit, BOREN, can enable or disable VDD rise is detected (in the range of 1.2V - 1.7V). To the Brown-out Reset circuit. If VDD falls below VBOR take advantage of the POR, tie the MCLR pin directly (parameter D005, about 4V) for longer than TBOR (or through a resistor) to VDD. This will eliminate (parameter #35, about 100 S), the brown-out situation external RC components usually needed to create a will reset the device. If VDD falls below VBOR for less Power-on Reset. A maximum rise time for VDD is than TBOR, a RESET may not occur. specified. See Electrical Specifications for details. Once the brown-out occurs, the device will remain in When the device starts normal operation (exits the Brown-out Reset until VDD rises above VBOR. The RESET condition), device operating parameters (volt- Power-up Timer then keeps the device in RESET for age, frequency, temperature,...) must be met to ensure TPWRT (parameter #33, about 72 ms). If VDD should fall operation. If these conditions are not met, the device below VBOR during TPWRT, the Brown-out Reset pro- must be held in RESET until the operating conditions cess will restart when VDD rises above VBOR with the are met. Brown-out Reset may be used to meet the Power-up Timer Reset. The Power-up Timer is always start-up conditions. For additional information, refer to enabled when the Brown-out Reset circuit is enabled, Application Note, AN007, “Power-up Trouble Shooting” regardless of the state of the PWRT configuration bit. (DS00007). 11.8 Time-out Sequence 11.5 Power-up Timer (PWRT) On power-up, the time-out sequence is as follows: The The Power-up Timer provides a fixed 72 ms nominal PWRT delay starts (if enabled) when a POR Reset time-out on power-up only from the POR. The Power- occurs. Then OST starts counting 1024 oscillator up Timer operates on an internal RC oscillator. The cycles when PWRT ends (LP, XT, HS). When the OST chip is kept in RESET as long as the PWRT is active. ends, the device comes out of RESET. The PWRT’s time delay allows VDD to rise to an If MCLR is kept low long enough, the time-outs will acceptable level. A configuration bit is provided to expire. Bringing MCLR high will begin execution imme- enable/disable the PWRT. diately. This is useful for testing purposes or to synchro- The power-up time delay will vary from chip to chip due nize more than one PIC16F870/871 device operating in to VDD, temperature and process variation. See DC parallel. parameters for details (TPWRT, parameter #33). Table11-5 shows the RESET conditions for the STATUS, PCON and PC registers, while Table11-6 11.6 Oscillator Start-up Timer (OST) shows the RESET conditions for all the registers. The Oscillator Start-up Timer (OST) provides a delay of 11.9 Power Control/Status Register 1024 oscillator cycles (from OSC1 input) after the PWRT delay is over (if PWRT is enabled). This helps to (PCON) ensure that the crystal oscillator or resonator has The Power Control/Status Register, PCON, has up to started and stabilized. two bits depending upon the device. The OST time-out is invoked only for XT, LP and HS Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is modes and only on Power-on Reset or Wake-up from unknown on a Power-on Reset. It must then be set by SLEEP. the user and checked on subsequent RESETS to see if bit BOR cleared, indicating a BOR occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable and is, therefore, not valid at any time. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. TABLE 11-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Oscillator Brown-out Wake-up from SLEEP Configuration PWRTEN = 0 PWRTEN = 1 XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC RC 72 ms — 72 ms — DS30569C-page 92  2000-2013 Microchip Technology Inc.

PIC16F870/871 TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP Legend: x = don’t care, u = unchanged TABLE 11-5: RESET CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --u0 Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, MCLR Resets Wake-up via WDT or Register Devices Brown-out Reset WDT Reset Interrupt W PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu INDF PIC16F870 PIC16F871 N/A N/A N/A TMR0 PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu PCL PIC16F870 PIC16F871 0000h 0000h PC + 1(2) STATUS PIC16F870 PIC16F871 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu PORTA PIC16F870 PIC16F871 --0x 0000 --0u 0000 --uu uuuu PORTB PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu PORTD PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu PORTE PIC16F870 PIC16F871 ---- -xxx ---- -uuu ---- -uuu PCLATH PIC16F870 PIC16F871 ---0 0000 ---0 0000 ---u uuuu INTCON PIC16F870 PIC16F871 0000 000x 0000 000u uuuu uuuu(1) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table11-5 for RESET value for specific condition.  2000-2013 Microchip Technology Inc. DS30569C-page 93

PIC16F870/871 TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, MCLR Resets Wake-up via WDT or Register Devices Brown-out Reset WDT Reset Interrupt PIR1 PIC16F870 PIC16F871 r000 -000 r000 -000 ruuu -uuu(1) PIC16F870 PIC16F871 0000 -000 0000 -000 uuuu -uuu(1) PIR2 PIC16F870 PIC16F871 ---0 ---- ---0 ---- ---u ----(1) TMR1L PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu TMR1H PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC16F870 PIC16F871 --00 0000 --uu uuuu --uu uuuu TMR2 PIC16F870 PIC16F871 0000 0000 0000 0000 uuuu uuuu T2CON PIC16F870 PIC16F871 -000 0000 -000 0000 -uuu uuuu CCPR1L PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC16F870 PIC16F871 --00 0000 --00 0000 --uu uuuu RCSTA PIC16F870 PIC16F871 0000 000x 0000 000x uuuu uuuu TXREG PIC16F870 PIC16F871 0000 0000 0000 0000 uuuu uuuu RCREG PIC16F870 PIC16F871 0000 0000 0000 0000 uuuu uuuu ADRESH PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC16F870 PIC16F871 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG PIC16F870 PIC16F871 1111 1111 1111 1111 uuuu uuuu TRISA PIC16F870 PIC16F871 --11 1111 --11 1111 --uu uuuu TRISB PIC16F870 PIC16F871 1111 1111 1111 1111 uuuu uuuu TRISC PIC16F870 PIC16F871 1111 1111 1111 1111 uuuu uuuu TRISD PIC16F870 PIC16F871 1111 1111 1111 1111 uuuu uuuu TRISE PIC16F870 PIC16F871 0000 -111 0000 -111 uuuu -uuu PIE1 PIC16F870 PIC16F871 r000 -000 r000 -000 ruuu -uuu PIC16F870 PIC16F871 0000 0000 0000 0000 uuuu uuuu PIE2 PIC16F870 PIC16F871 ---0 ---- ---0 ---- ---u ---- PCON PIC16F870 PIC16F871 ---- --qq ---- --uu ---- --uu PR2 PIC16F870 PIC16F871 1111 1111 1111 1111 1111 1111 TXSTA PIC16F870 PIC16F871 0000 -010 0000 -010 uuuu -uuu SPBRG PIC16F870 PIC16F871 0000 0000 0000 0000 uuuu uuuu ADRESL PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 PIC16F870 PIC16F871 0--- 0000 0--- 0000 u--- uuuu EEDATA PIC16F870 PIC16F871 0--- 0000 0--- 0000 u--- uuuu EEADR PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu EEDATH PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu EEADRH PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu EECON1 PIC16F870 PIC16F871 x--- x000 u--- u000 u--- uuuu EECON2 PIC16F870 PIC16F871 ---- ---- ---- ---- ---- ---- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table11-5 for RESET value for specific condition. DS30569C-page 94  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  2000-2013 Microchip Technology Inc. DS30569C-page 95

PIC16F870/871 FIGURE 11-8: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 11.10 Interrupts The peripheral interrupt flags are contained in the spe- cial function registers, PIR1 and PIR2. The correspond- The PIC16F870/871 family has up to 14 sources of ing interrupt enable bits are contained in special interrupt. The Interrupt Control register (INTCON) function registers, PIE1 and PIE2, and the peripheral records individual interrupt requests in flag bits. It also interrupt enable bit is contained in special function has individual and global interrupt enable bits. register, INTCON. Note: Individual interrupt flag bits are set, When an interrupt is responded to, the GIE bit is regardless of the status of their cleared to disable any further interrupt, the return corresponding mask bit, or the GIE bit. address is pushed onto the stack and the PC is loaded A global interrupt enable bit, GIE (INTCON<7>), with 0004h. Once in the Interrupt Service Routine, the enables (if set) all unmasked interrupts, or disables (if source(s) of the interrupt can be determined by polling cleared) all interrupts. When bit GIE is enabled, and an the interrupt flag bits. The interrupt flag bit(s) must be interrupt’s flag bit and mask bit are set, the interrupt will cleared in software before re-enabling interrupts to vector immediately. Individual interrupts can be dis- avoid recursive interrupts. abled through their corresponding enable bits in vari- For external interrupt events, such as the INT pin or ous registers. Individual interrupt bits are set, PORTB change interrupt, the interrupt latency will be regardless of the status of the GIE bit. The GIE bit is three or four instruction cycles. The exact latency cleared on RESET. depends when the interrupt event occurs. The latency The “return from interrupt” instruction, RETFIE, exits is the same for one or two-cycle instructions. Individual the interrupt routine as well as sets the GIE bit, which interrupt flag bits are set, regardless of the status of re-enables interrupts. their corresponding mask bit, PEIE bit, or GIE bit. The RB0/INT pin interrupt, the RB port change interrupt, and the TMR0 overflow interrupt flags are contained in the INTCON register. DS30569C-page 96  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 11-9: INTERRUPT LOGIC EEIF EEIE PSPIF PSPIE ADIF T0IF Wake-up (If in SLEEP mode) ADIE T0IE RCIF INTF RCIE INTE Interrupt to CPU TXIF RBIF TXIE RBIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE The following table shows which devices have which interrupts. Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF EEIF PIC18F870 Yes Yes Yes — Yes Yes Yes Yes Yes Yes Yes PIC18F871 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 11.10.1 INT INTERRUPT 11.10.2 TMR0 INTERRUPT External interrupt on the RB0/INT pin is edge triggered, An overflow (FFh  00h) in the TMR0 register will set either rising, if bit INTEDG (OPTION_REG<6>) is set, flag bit T0IF (INTCON<2>). The interrupt can be or falling, if the INTEDG bit is clear. When a valid edge enabled/disabled by setting/clearing enable bit T0IE appears on the RB0/INT pin, flag bit INTF (INTCON<5>) (Section5.0). (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF 11.10.3 PORTB INTCON CHANGE must be cleared in software in the Interrupt Service An input change on PORTB<7:4> sets flag bit RBIF Routine before re-enabling this interrupt. The INT inter- (INTCON<0>). The interrupt can be enabled/disabled rupt can wake-up the processor from SLEEP, if bit INTE by setting/clearing enable bit RBIE (INTCON<4>) was set prior to going into SLEEP. The status of global (Section4.2). interrupt enable bit, GIE, decides whether or not the processor branches to the interrupt vector following wake-up. See Section11.13 for details on SLEEP mode.  2000-2013 Microchip Technology Inc. DS30569C-page 97

PIC16F870/871 11.11 Context Saving During Interrupts Since the upper 16 bytes of each bank are common in the PIC16F870/871 devices, temporary holding regis- During an interrupt, only the return PC value is saved ters W_TEMP, STATUS_TEMP, and PCLATH_TEMP on the stack. Typically, users may wish to save key reg- should be placed in here. These 16 locations don’t isters during an interrupt, (i.e., W register and STATUS require banking and therefore, make it easier for con- register). This will have to be implemented in software. text save and restore. The same code shown in For the PIC16F870/871 devices, the register W_TEMP Example11-1 can be used. must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., If W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). The registers, PCLATH_TEMP and STATUS_TEMP, are only defined in bank 0. EXAMPLE 11-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ;Save PCLATH into W CLRF PCLATH ;Page zero, regardless of current page : :(ISR) ;(Insert user code here) : MOVF PCLATH_TEMP, W ;Restore PCLATH MOVWF PCLATH ;Move W into PCLATH SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W DS30569C-page 98  2000-2013 Microchip Technology Inc.

PIC16F870/871 11.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Elec- trical Specifications section under parameter #31. Val- The Watchdog Timer is a free running on-chip RC oscil- ues for the WDT prescaler (actually a postscaler, but lator which does not require any external components. shared with the Timer0 prescaler) may be assigned This RC oscillator is separate from the RC oscillator of using the OPTION_REG register. the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/CLKO Note1: The CLRWDT and SLEEP instructions pins of the device has been stopped, for example, by clear the WDT and the postscaler, if execution of a SLEEP instruction. assigned to the WDT, and prevent it from timing out and generating a device During normal operation, a WDT time-out generates a RESET condition. device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to 2: When a CLRWDT instruction is executed wake-up and continue with normal operation and the prescaler is assigned to the WDT, (Watchdog Timer Wake-up). The TO bit in the STATUS the prescaler count will be cleared, but register will be cleared upon a Watchdog Timer the prescaler assignment is not changed. time-out. The WDT can be permanently disabled by clearing configuration bit WDTEN (Section11.1). FIGURE 11-10: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure5-1) 0 M Postscaler 1 WDT Timer U X 8 8 - to - 1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure5-1) 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register. TABLE 11-7: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits (1) BOREN(1) CP1 CP0 PWRTEN(1) WDTEN FOSC1 FOSC0 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register11-1 for operation of these bits.  2000-2013 Microchip Technology Inc. DS30569C-page 99

PIC16F870/871 11.13 Power-down Mode (SLEEP) When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to Power-down mode is entered by executing a SLEEP wake-up through an interrupt event, the corresponding instruction. interrupt enable bit must be set (enabled). Wake-up is If enabled, the Watchdog Timer will be cleared but regardless of the state of the GIE bit. If the GIE bit is keeps running, the PD bit (STATUS<3>) is cleared, the clear (disabled), the device continues execution at the TO (STATUS<4>) bit is set, and the oscillator driver is instruction after the SLEEP instruction. If the GIE bit is turned off. The I/O ports maintain the status they had set (enabled), the device executes the instruction after before the SLEEP instruction was executed (driving the SLEEP instruction and then branches to the inter- high, low, or hi-impedance). rupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the For lowest current consumption in this mode, place all user should have a NOP after the SLEEP instruction. I/O pins at either VDD or VSS, ensure no external cir- cuitry is drawing current from the I/O pin, power-down 11.13.2 WAKE-UP USING INTERRUPTS the A/D and disable external clocks. Pull all I/O pins that are hi-impedance inputs, high or low externally, to When global interrupts are disabled (GIE cleared) and avoid switching currents caused by floating inputs. The any interrupt source has both its interrupt enable bit T0CKI input should also be at VDD or VSS for lowest and interrupt flag bit set, one of the following will occur: current consumption. The contribution from on-chip • If the interrupt occurs before the execution of a pull-ups on PORTB should also be considered. SLEEP instruction, the SLEEP instruction will com- The MCLR pin must be at a logic high level (VIHMC). plete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not 11.13.1 WAKE-UP FROM SLEEP be set and PD bits will not be cleared. • If the interrupt occurs during or after the The device can wake-up from SLEEP through one of the following events: execution of a SLEEP instruction, the device will immediately wake-up from SLEEP. The SLEEP 1. External RESET input on MCLR pin. instruction will be completely executed before the 2. Watchdog Timer Wake-up (if WDT was wake-up. Therefore, the WDT and WDT enabled). postscaler will be cleared, the TO bit will be set 3. Interrupt from INT pin, RB port change or and the PD bit will be cleared. peripheral interrupt. Even if the flag bits were checked before executing a External MCLR Reset will cause a device RESET. All SLEEP instruction, it may be possible for flag bits to other events are considered a continuation of program become set before the SLEEP instruction completes. To execution and cause a “wake-up”. The TO and PD bits determine whether a SLEEP instruction executed, test in the STATUS register can be used to determine the the PD bit. If the PD bit is set, the SLEEP instruction cause of device RESET. The PD bit, which is set on was executed as a NOP. power-up, is cleared when SLEEP is invoked. The TO To ensure that the WDT is cleared, a CLRWDT bit is cleared if a WDT time-out occurred and caused instruction should be executed before a SLEEP wake-up. instruction. The following peripheral interrupts can wake the device from SLEEP: 1. PSP read or write (PIC16F874/877 only). 2. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 3. CCP Capture mode interrupt. 4. Special event trigger (Timer1 in Asynchronous mode using an external clock). 5. SSP (START/STOP) bit detect interrupt. 6. SSP transmit or receive in Slave mode (SPI/I2C). 7. USART RX or TX (Synchronous Slave mode). 8. A/D conversion (when A/D clock source is RC). 9. EEPROM write operation completion Other peripherals cannot generate interrupts, since during SLEEP, no on-chip clocks are present. DS30569C-page 100  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 11-11: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 CLKO(4) TOST(2) INT pin INTF Flag (INTCON<1>) Interrupt Latency(2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h Instruction Fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) Instruction Executed Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Osc mode. 3: GIE = 1 assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. 4: CLKO is not available in these Osc modes, but shown here for timing reference. 11.14 In-Circuit Debugger 11.15 Program Verification/Code Protection When the DEBUG bit in the configuration word is pro- grammed to a '0', the In-Circuit Debugger functionality If the code protection bit(s) have not been pro- is enabled. This function allows simple debugging func- grammed, the on-chip program memory can be read tions when used with MPLAB® ICD. When the micro- out for verification purposes. controller has this feature enabled, some of the resources are not available for general use. Table11-8 11.16 ID Locations shows which features are consumed by the background debugger. Four memory locations (2000h - 2003h) are designated as ID locations, where the user can store checksum or TABLE 11-8: DEBUGGER RESOURCES other code identification numbers. These locations are not accessible during normal execution, but are read- I/O pins RB6, RB7 able and writable during program/verify. It is recom- Stack 1 level mended that only the 4 Least Significant bits of the ID Program Memory Address 0000h must be NOP location are used. Last 100h words Data Memory 0x070 (0x0F0, 0x170, 0x1F0) 0x1EB - 0x1EF To use the In-Circuit Debugger function of the micro- controller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip, or one of the third party development tool companies.  2000-2013 Microchip Technology Inc. DS30569C-page 101

PIC16F870/871 11.17 In-Circuit Serial Programming Note1: The High Voltage Programming mode is PIC16F870/871 microcontrollers can be serially pro- always available, regardless of the state grammed while in the end application circuit. This is of the LVP bit, by applying VIHH to the simply done with two lines for clock and data and three MCLR pin. other lines for power, ground, and the programming voltage. This allows customers to manufacture boards 2: While in Low Voltage ICSP mode, the with unprogrammed devices, and then program the RB3 pin can no longer be used as a microcontroller just before shipping the product. This general purpose I/O pin. also allows the most recent firmware, or a custom 3: When using low voltage ICSP program- firmware to be programmed. ming (LVP) and the pull-ups on PORTB When using ICSP, the part must be supplied at 4.5V to are enabled, bit 3 in the TRISB register 5.5V, if a bulk erase will be executed. This includes must be cleared to disable the pull-up on reprogramming of the code protect, both from an on- RB3 and ensure the proper operation of state to off-state. For all other cases of ICSP, the part the device. may be programmed at the normal operating voltages. 4: RB3 should not be allowed to float if LVP This means calibration values, unique user IDs, or user is enabled. An external pull-down device code can be reprogrammed or added. should be used to default the device to For complete details of serial programming, please normal Operating mode. If RB3 floats refer to the EEPROM Memory Programming high, the PIC16F870/871 devices will Specification for the PIC16F87X (DS39025). enter Programming mode. 5: LVP mode is enabled by default on all 11.18 Low Voltage ICSP Programming devices shipped from Microchip. It can be disabled by clearing the LVP bit in the The LVP bit of the configuration word enables low volt- CONFIG register. age ICSP programming. This mode allows the micro- controller to be programmed via ICSP, using a VDD 6: Disabling LVP will provide maximum source in the operating voltage range. This only means compatibility to other PIC16CXXX that VPP does not have to be brought to VIHH, but can devices. instead be left at the normal operating voltage. In this If Low Voltage Programming mode is not used, the LVP mode, the RB3/PGM pin is dedicated to the program- bit can be programmed to a '0' and RB3/PGM becomes ming function and ceases to be a general purpose I/O a digital I/O pin. However, the LVP bit may only be pro- pin. During programming, VDD is applied to the MCLR grammed when programming is entered with VIHH on pin. To enter Programming mode, VDD must be applied MCLR. The LVP bit can only be charged when using to the RB3/PGM pin, provided the LVP bit is set. The high voltage on MCLR. LVP bit defaults to on (‘1’) from the factory. It should be noted, that once the LVP bit is programmed to 0, only the High Voltage Programming mode is avail- able and only High Voltage Programming mode can be used to program the device. When using low voltage ICSP, the part must be supplied at 4.5V to 5.5V, if a bulk erase will be executed. This includes reprogramming of the code protect bits from an on-state to off-state. For all other cases of low voltage ICSP, the part may be programmed at the normal oper- ating voltage. This means calibration values, unique user IDs, or user code can be reprogrammed or added. DS30569C-page 102  2000-2013 Microchip Technology Inc.

PIC16F870/871 12.0 INSTRUCTION SET SUMMARY All instructions are executed within one single instruc- tion cycle, unless a conditional test is true, or the pro- Each PIC16F870/871 instruction is a 14-bit word, gram counter is changed as a result of an instruction. divided into an OPCODE, which specifies the instruc- In this case, the execution takes two instruction cycles, tion type, and one or more operands, which further with the second cycle executed as a NOP. One instruc- specify the operation of the instruction. The tion cycle consists of four oscillator periods. Thus, for PIC16F870/871 instruction set summary in Table12-2 an oscillator frequency of 4 MHz, the normal instruction lists byte-oriented, bit-oriented, and literal and con- execution time is 1 s. If a conditional test is true, or the trol operations. Table12-1 shows the opcode field program counter is changed as a result of an descriptions. instruction, the instruction execution time is 2 s. For byte-oriented instructions, 'f' represents a file reg- Table12-2 lists the instructions recognized by the ister designator and 'd' represents a destination desig- MPASMTM assembler. nator. The file register designator specifies which file Figure12-1 shows the general formats that the register is to be used by the instruction. instructions can have. The destination designator specifies where the result of Note: To maintain upward compatibility with the operation is to be placed. If 'd' is zero, the result is future PIC16F870/871 products, do not placed in the W register. If 'd' is one, the result is placed use the OPTION and TRIS instructions. in the file register specified in the instruction. All examples use the following format to represent a For bit-oriented instructions, 'b' represents a bit field hexadecimal number: designator which selects the number of the bit affected by the operation, while 'f' represents the address of the 0xhh file in which the bit is located. where h signifies a hexadecimal digit. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. FIGURE 12-1: GENERAL FORMAT FOR INSTRUCTIONS TABLE 12-1: OPCODE FIELD Byte-oriented file register operations DESCRIPTIONS 13 8 7 6 0 Field Description OPCODE d f (FILE #) f Register file address (0x00 to 0x7F) d = 0 for destination W d = 1 for destination f W Working register (accumulator) f = 7-bit file register address b Bit address within an 8-bit file register k Literal field, constant data or label Bit-oriented file register operations 13 10 9 7 6 0 x Don't care location (= 0 or 1). OPCODE b (BIT #) f (FILE #) The assembler will generate code with x = 0. It is the recommended form of use for b = 3-bit bit address compatibility with all Microchip software tools. f = 7-bit file register address d Destination select; d = 0: store result in W, d = 1: store result in file register f. Literal and control operations Default is d = 1. General PC Program Counter 13 8 7 0 TO Time-out bit OPCODE k (literal) PD Power-down bit k = 8-bit immediate value The instruction set is highly orthogonal and is grouped into three basic categories: CALL and GOTO instructions only • Byte-oriented operations 13 11 10 0 • Bit-oriented operations OPCODE k (literal) • Literal and control operations k = 11-bit immediate value A description of each instruction is available in the PIC® Mid-Range MCU Family Reference Manual (DS33023).  2000-2013 Microchip Technology Inc. DS30569C-page 103

PIC16F870/871 TABLE 12-2: PIC16F870/871 INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into Standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Note: Additional information on the mid-range instruction set is available in the PIC® Mid-Range MCU Family Ref- erence Manual (DS33023). DS30569C-page 104  2000-2013 Microchip Technology Inc.

PIC16F870/871 12.1 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b Operands: 0  k  255 Operands: 0  f  127 0  b  7 Operation: (W) + k  (W) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: The contents of the W register are added to the eight-bit literal 'k' Description: Bit 'b' in register 'f' is cleared. and the result is placed in the W register. ADDWF Add W and f BSF Bit Set f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b Operands: 0  f  127 Operands: 0  f  127 d  0  b  7 Operation: (W) + (f)  (destination) Operation: 1  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit 'b' in register 'f' is set. with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. ANDLW AND Literal with W BTFSS Bit Test f, Skip if Set Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSS f,b Operands: 0  k  255 Operands: 0  f  127 0  b < 7 Operation: (W) .AND. (k)  (W) Operation: skip if (f<b>) = 1 Status Affected: Z Status Affected: None Description: The contents of W register are AND’ed with the eight-bit literal Description: If bit 'b' in register 'f' is '0', the next 'k'. The result is placed in the W instruction is executed. register. If bit 'b' is '1', then the next instruc- tion is discarded and a NOP is executed instead, making this a 2TCY instruction. ANDWF AND W with f BTFSC Bit Test, Skip if Clear Syntax: [ label ] ANDWF f,d Syntax: [ label ] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 d  0  b  7 Operation: (W) .AND. (f)  (destination) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: AND the W register with register Description: If bit 'b' in register 'f' is '1', the next 'f'. If 'd' is 0, the result is stored in instruction is executed. the W register. If 'd' is 1, the result If bit 'b', in register 'f', is '0', the is stored back in register 'f'. next instruction is discarded, and a NOP is executed instead, making this a 2 TCY instruction.  2000-2013 Microchip Technology Inc. DS30569C-page 105

PIC16F870/871 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<4:3>)  PC<12:11> 1  TO 1  PD Status Affected: None Status Affected: TO, PD Description: Call Subroutine. First, return address (PC+1) is pushed onto Description: CLRWDT instruction resets the the stack. The eleven-bit Watchdog Timer. It also resets immediate address is loaded into the prescaler of the WDT. Status PC bits <10:0>. The upper bits of bits TO and PD are set. the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f COMF Complement f Syntax: [ label ] CLRF f Syntax: [ label ] COMF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register 'f' are Description: The contents of register 'f' are cleared and the Z bit is set. complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. CLRW Clear W DECF Decrement f Syntax: [ label ] CLRW Syntax: [ label ] DECF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: 00h  (W) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: W register is cleared. Zero bit (Z) Description: Decrement register 'f'. If 'd' is 0, is set. the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. DS30569C-page 106  2000-2013 Microchip Technology Inc.

PIC16F870/871 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register 'f' are Description: The contents of register 'f' are decremented. If 'd' is 0, the result incremented. If 'd' is 0, the result is is placed in the W register. If 'd' is placed in the W register. If 'd' is 1, 1, the result is placed back in the result is placed back in register 'f'. register 'f'. If the result is 1, the next instruc- If the result is 1, the next instruc- tion is executed. If the result is 0, tion is executed. If the result is 0, then a NOP is executed instead a NOP is executed instead, making making it a 2 TCY instruction. it a 2 TCY instruction. GOTO Unconditional Branch IORLW Inclusive OR Literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<4:3>  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the eight bit literal 'k'. The eleven-bit immediate value is The result is placed in the W loaded into PC bits <10:0>. The register. upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register 'f' are Description: Inclusive OR the W register with incremented. If 'd' is 0, the result register 'f'. If 'd' is 0 the result is is placed in the W register. If 'd' is placed in the W register. If 'd' is 1 1, the result is placed back in the result is placed back in register 'f'. register 'f'.  2000-2013 Microchip Technology Inc. DS30569C-page 107

PIC16F870/871 MOVF Move f NOP No Operation Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP Operands: 0  f  127 Operands: None d  [0,1] Operation: No operation Operation: (f)  (destination) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected. MOVLW Move Literal to W RETFIE Return from Interrupt Syntax: [ label ] MOVLW k Syntax: [ label ] RETFIE Operands: 0  k  255 Operands: None Operation: k  (W) Operation: TOS  PC, 1  GIE Status Affected: None Status Affected: None Description: The eight-bit literal 'k' is loaded into W register. The don’t cares will assemble as 0’s. MOVWF Move W to f RETLW Return with Literal in W Syntax: [ label ] MOVWF f Syntax: [ label ] RETLW k Operands: 0  f  127 Operands: 0  k  255 Operation: (W)  (f) Operation: k  (W); TOS  PC Status Affected: None Status Affected: None Description: Move data from W register to register 'f'. Description: The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. DS30569C-page 108  2000-2013 Microchip Technology Inc.

PIC16F870/871 RLF Rotate Left f through Carry SLEEP Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP Operands: 0  f  127 Operands: None d  [0,1] Operation: 00h  WDT, Operation: See description below 0  WDT prescaler, 1  TO, Status Affected: C 0  PD Description: The contents of register 'f' are rotated Status Affected: TO, PD one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in Description: The power-down status bit, PD is the W register. If 'd' is 1, the result is cleared. Time-out status bit, TO stored back in register 'f'. is set. Watchdog Timer and its prescaler are cleared. C Register f The processor is put into SLEEP mode with the oscillator stopped. RETURN Return from Subroutine SUBLW Subtract W from Literal Syntax: [ label ] RETURN Syntax: [ label ] SUBLW k Operands: None Operands: 0 k 255 Operation: TOS  PC Operation: k - (W) W) Status Affected: None Status Affected: C, DC, Z Description: Return from subroutine. The stack Description: The W register is subtracted (2’s is POPed and the top of the stack complement method) from the (TOS) is loaded into the program eight-bit literal 'k'. The result is counter. This is a two-cycle placed in the W register. instruction. RRF Rotate Right f through Carry SUBWF Subtract W from f Syntax: [ label ] RRF f,d Syntax: [ label ] SUBWF f,d Operands: 0  f  127 Operands: 0 f 127 d  [0,1] d  [0,1] Operation: See description below Operation: (f) - (W) destination) Status Affected: C Status C, DC, Z Affected: Description: The contents of register 'f' are rotated one bit to the right through Description: Subtract (2’s complement method) the Carry Flag. If 'd' is 0, the result W register from register 'f'. If 'd' is 0, is placed in the W register. If 'd' is the result is stored in the W 1, the result is placed back in register. If 'd' is 1, the result is register 'f'. stored back in register 'f'. C Register f  2000-2013 Microchip Technology Inc. DS30569C-page 109

PIC16F870/871 SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f<3:0>)  (destination<7:4>), Operation: (W) .XOR. (f) destination) (f<7:4>)  (destination<3:0>) Status Affected: Z Status Affected: None Description: Exclusive OR the contents of the Description: The upper and lower nibbles of W register with register 'f'. If 'd' is register 'f' are exchanged. If 'd' is 0, the result is stored in the W 0, the result is placed in the W register. If 'd' is 1, the result is register. If 'd' is 1, the result is stored back in register 'f'. placed in register 'f'. XORLW Exclusive OR Literal with W Syntax: [ label ] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal 'k'. The result is placed in the W register. DS30569C-page 110  2000-2013 Microchip Technology Inc.

PIC16F870/871 13.0 DEVELOPMENT SUPPORT 13.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- • Integrated Development Environment controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software based application that contains: • Assemblers/Compilers/Linkers • An interface to debugging tools - MPASMTM Assembler - simulator - MPLAB C17 and MPLAB C18 C Compilers - programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - emulator (sold separately) - MPLAB C30 C Compiler - in-circuit debugger (sold separately) - MPLAB ASM30 Assembler/Linker/Library • A full-featured editor with color coded context • Simulators • A multiple project manager - MPLAB SIM Software Simulator • Customizable data windows with direct edit of contents - MPLAB dsPIC30 Software Simulator • High level source code debugging • Emulators • Mouse over variable inspection - MPLAB ICE 2000 In-Circuit Emulator • Extensive on-line help - MPLAB ICE 4000 In-Circuit Emulator • In-Circuit Debugger The MPLAB IDE allows you to: - MPLAB ICD 2 • Edit your source files (either assembly or C) • Device Programmers • One touch assemble (or compile) and download - PRO MATE® II Universal Device Programmer to PIC MCU emulator and simulator tools (automatically updates all project information) - PICSTART® Plus Development Programmer • Debug using: • Low Cost Demonstration Boards - source files (assembly or C) - PICDEMTM 1 Demonstration Board - absolute listing file (mixed assembly and C) - PICDEM.netTM Demonstration Board - machine code - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective - PICDEM 4 Demonstration Board simulators, through low cost in-circuit debuggers, to - PICDEM 17 Demonstration Board full-featured emulators. This eliminates the learning - PICDEM 18R Demonstration Board curve when upgrading to tools with increasing flexibility - PICDEM LIN Demonstration Board and power. - PICDEM USB Demonstration Board 13.2 MPASM Assembler • Evaluation Kits - KEELOQ® The MPASM assembler is a full-featured, universal - PICDEM MSC macro assembler for all PIC MCUs. - microID® The MPASM assembler generates relocatable object - CAN files for the MPLINK object linker, Intel® standard HEX - PowerSmart® files, MAP files to detail memory usage and symbol ref- - Analog erence, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM assembler features include: • Integration into MPLAB IDE projects • User defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process  2000-2013 Microchip Technology Inc. DS30569C-page 111

PIC16F870/871 13.3 MPLAB C17 and MPLAB C18 13.6 MPLAB ASM30 Assembler, Linker, C Compilers and Librarian The MPLAB C17 and MPLAB C18 Code Development MPLAB ASM30 assembler produces relocatable Systems are complete ANSI C compilers for machine code from symbolic assembly language for Microchip’s PIC17CXXX and PIC18CXXX family of dsPIC30F devices. MPLAB C30 compiler uses the microcontrollers. These compilers provide powerful assembler to produce it’s object file. The assembler integration capabilities, superior code optimization and generates relocatable object files that can then be ease of use not found with other compilers. archived or linked with other relocatable object files and archives to create an executable file. Notable features For easy source level debugging, the compilers provide of the assembler include: symbol information that is optimized to the MPLAB IDE debugger. • Support for the entire dsPIC30F instruction set • Support for fixed-point and floating-point data 13.4 MPLINK Object Linker/ • Command line interface MPLIB Object Librarian • Rich directive set The MPLINK object linker combines relocatable • Flexible macro language objects created by the MPASM assembler and the • MPLAB IDE compatibility MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from pre-compiled libraries, using 13.7 MPLAB SIM Software Simulator directives from a linker script. The MPLAB SIM software simulator allows code devel- The MPLIB object librarian manages the creation and opment in a PC hosted environment by simulating the modification of library files of pre-compiled code. When PIC series microcontrollers on an instruction level. On a routine from a library is called from a source file, only any given instruction, the data areas can be examined the modules that contain that routine will be linked in or modified and stimuli can be applied from a file, or with the application. This allows large libraries to be user defined key press, to any pin. The execution can used efficiently in many different applications. be performed in Single-Step, Execute Until Break, or The object linker/library features include: Trace mode. • Efficient linking of single libraries instead of many The MPLAB SIM simulator fully supports symbolic smaller files debugging using the MPLAB C17 and MPLAB C18 • Enhanced code maintainability by grouping CCompilers, as well as the MPASM assembler. The related modules together software simulator offers the flexibility to develop and debug code outside of the laboratory environment, • Flexible creation of libraries with easy module making it an excellent, economical software listing, replacement, deletion and extraction development tool. 13.5 MPLAB C30 C Compiler 13.8 MPLAB SIM30 Software Simulator The MPLAB C30 C compiler is a full-featured, ANSI The MPLAB SIM30 software simulator allows code compliant, optimizing compiler that translates standard development in a PC hosted environment by simulating ANSI C programs into dsPIC30F assembly language the dsPIC30F series microcontrollers on an instruction source. The compiler also supports many command- level. On any given instruction, the data areas can be line options and language extensions to take full examined or modified and stimuli can be applied from advantage of the dsPIC30F device hardware capabili- a file, or user defined key press, to any of the pins. ties, and afford fine control of the compiler code generator. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB C30 is distributed with a complete ANSI C MPLAB ASM30 assembler. The simulator runs in either standard library. All library functions have been vali- a Command Line mode for automated tasks, or from dated and conform to the ANSI C library standard. The MPLAB IDE. This high speed simulator is designed to library includes functions for string manipulation, debug, analyze and optimize time intensive DSP dynamic memory allocation, data conversion, time- routines. keeping, and math functions (trigonometric, exponen- tial and hyperbolic). The compiler provides symbolic information for high level source debugging with the MPLAB IDE. DS30569C-page 112  2000-2013 Microchip Technology Inc.

PIC16F870/871 13.9 MPLAB ICE 2000 13.11 MPLAB ICD 2 In-Circuit Debugger High Performance Universal Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low cost, run-time development tool, connecting to the host PC via an RS-232 or high speed The MPLAB ICE 2000 universal in-circuit emulator is USB interface. This tool is based on the FLASH PIC intended to provide the product development engineer MCUs and can be used to develop for these and other with a complete microcontroller design tool set for PIC PIC microcontrollers. The MPLAB ICD2 utilizes the in- microcontrollers. Software control of the MPLAB ICE circuit debugging capability built into the FLASH 2000 in-circuit emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers cost editing, building, downloading and source debugging effective in-circuit FLASH debugging from the graphical from a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator sys- Environment. This enables a designer to develop and tem with enhanced trace, trigger and data monitoring debug source code by setting breakpoints, single- features. Interchangeable processor modules allow the stepping and watching variables, CPU status and system to be easily reconfigured for emulation of differ- peripheral registers. Running at full speed enables test- ent processors. The universal architecture of the ing hardware and applications in real-time. MPLAB MPLAB ICE in-circuit emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with 13.12 PRO MATE II Universal Device advanced features that are typically found on more Programmer expensive development tools. The PC platform and Microsoft® Windows 32-bit operating system were The PRO MATE II is a universal, CE compliant device chosen to best make these features available in a programmer with programmable voltage verification at simple, unified application. VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages 13.10 MPLAB ICE 4000 and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the High Performance Universal PROMATE II device programmer can read, verify, and In-Circuit Emulator program PIC devices without a PC connection. It can The MPLAB ICE 4000 universal in-circuit emulator is also set code protection in this mode. intended to provide the product development engineer with a complete microcontroller design tool set for high- 13.13 PICSTART Plus Development end PIC microcontrollers. Software control of the Programmer MPLAB ICE in-circuit emulator is provided by the The PICSTART Plus development programmer is an MPLAB Integrated Development Environment, which easy-to-use, low cost, prototype programmer. It con- allows editing, building, downloading and source nects to the PC via a COM (RS-232) port. MPLAB debugging from a single environment. Integrated Development Environment software makes The MPLAB ICD 4000 is a premium emulator system, using the programmer simple and efficient. The providing the features of MPLAB ICE 2000, but with PICSTART Plus development programmer supports increased emulation memory and high speed perfor- most PIC devices up to 40 pins. Larger pin count mance for dsPIC30F and PIC18XXXX devices. Its devices, such as the PIC16C92X and PIC17C76X, advanced emulator features include complex triggering may be supported with an adapter socket. The and timing, up to 2 Mb of emulation memory, and the PICSTART Plus development programmer is CE ability to view variables in real-time. compliant. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application.  2000-2013 Microchip Technology Inc. DS30569C-page 113

PIC16F870/871 13.14 PICDEM 1 PIC MCU 13.17 PICDEM 3 PIC16C92X Demonstration Board Demonstration Board The PICDEM 1 demonstration board demonstrates the The PICDEM 3 demonstration board supports the capabilities of the PIC16C5X (PIC16C54 to PIC16C923 and PIC16C924 in the PLCC package. All PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, the necessary hardware and software is included to run PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All the demonstration programs. necessary hardware and software is included to run basic demo programs. The sample microcontrollers 13.18 PICDEM 4 8/14/18-Pin provided with the PICDEM 1 demonstration board can Demonstration Board be programmed with a PRO MATE II device program- mer, or a PICSTART Plus development programmer. The PICDEM 4 can be used to demonstrate the capa- The PICDEM 1 demonstration board can be connected bilities of the 8-, 14-, and 18-pin PIC16XXXX and to the MPLAB ICE in-circuit emulator for testing. A pro- PIC18XXXX MCUs, including the PIC16F818/819, totype area extends the circuitry for additional applica- PIC16F87/88, PIC16F62XA and the PIC18F1320 fam- tion components. Features include an RS-232 ily of microcontrollers. PICDEM 4 is intended to show- interface, a potentiometer for simulated analog input, case the many features of these low pin count parts, push button switches and eight LEDs. including LIN and Motor Control using ECCP. Special provisions are made for low power operation with the 13.15 PICDEM.net Internet/Ethernet supercapacitor circuit, and jumpers allow on-board Demonstration Board hardware to be disabled to eliminate current draw in this mode. Included on the demo board are provisions The PICDEM.net demonstration board is an Internet/ for Crystal, RC or Canned Oscillator modes, a five volt Ethernet demonstration board using the PIC18F452 regulator for use with a nine volt wall adapter or battery, microcontroller and TCP/IP firmware. The board DB-9 RS-232 interface, ICD connector for program- supports any 40-pin DIP device that conforms to the ming via ICSP and development with MPLAB ICD 2, standard pinout used by the PIC16F877 or 2x16 liquid crystal display, PCB footprints for H-Bridge PIC18C452. This kit features a user friendly TCP/IP motor driver, LIN transceiver and EEPROM. Also stack, web server with HTML, a 24L256 Serial included are: header for expansion, eight LEDs, four EEPROM for Xmodem download to web pages into potentiometers, three push buttons and a prototyping Serial EEPROM, ICSP/MPLAB ICD 2 interface con- area. Included with the kit is a PIC16F627A and a nector, an Ethernet interface, RS-232 interface, and a PIC18F1320. Tutorial firmware is included along with 16 x 2 LCD display. Also included is the book and the User’s Guide. CD-ROM “TCP/IP Lean, Web Servers for Embedded Systems,” by Jeremy Bentham 13.19 PICDEM 17 Demonstration Board 13.16 PICDEM 2 Plus The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Demonstration Board Microchip microcontrollers, including PIC17C752, The PICDEM 2 Plus demonstration board supports PIC17C756A, PIC17C762 and PIC17C766. A pro- many 18-, 28-, and 40-pin microcontrollers, including grammed sample is included. The PRO MATE II device PIC16F87X and PIC18FXX2 devices. All the neces- programmer, or the PICSTART Plus development pro- sary hardware and software is included to run the dem- grammer, can be used to reprogram the device for user onstration programs. The sample microcontrollers tailored application development. The PICDEM 17 provided with the PICDEM 2 demonstration board can demonstration board supports program download and be programmed with a PRO MATE II device program- execution from external on-board FLASH memory. A mer, PICSTART Plus development programmer, or generous prototype area is available for user hardware MPLAB ICD 2 with a Universal Programmer Adapter. expansion. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2x16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs, and sample PIC18F452 and PIC16F877 FLASH microcontrollers. DS30569C-page 114  2000-2013 Microchip Technology Inc.

PIC16F870/871 13.20 PICDEM 18R PIC18C601/801 13.23 PICDEM USB PIC16C7X5 Demonstration Board Demonstration Board The PICDEM 18R demonstration board serves to assist The PICDEM USB Demonstration Board shows off the development of the PIC18C601/801 family of Microchip capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. It provides hardware implementation microcontrollers. This board provides the basis for of both 8-bit Multiplexed/De-multiplexed and 16-bit future USB products. Memory modes. The board includes 2 Mb external FLASH memory and 128 Kb SRAM memory, as well as 13.24 Evaluation and serial EEPROM, allowing access to the wide range of Programming Tools memory types supported by the PIC18C601/801. In addition to the PICDEM series of circuits, Microchip 13.21 PICDEM LIN PIC16C43X has a line of evaluation kits and demonstration software Demonstration Board for these products. • KEELOQ evaluation and programming tools for The powerful LIN hardware and software kit includes a Microchip’s HCS Secure Data Products series of boards and three PIC microcontrollers. The • CAN developers kit for automotive network small footprint PIC16C432 and PIC16C433 are used applications as slaves in the LIN communication and feature on- board LIN transceivers. A PIC16F874 FLASH micro- • Analog design boards and filter design software controller serves as the master. All three microcon- • PowerSmart battery charging evaluation/ trollers are programmed with firmware to provide LIN calibration kits bus communication. • IrDA® development kit • microID development and rfLabTM development 13.22 PICkitTM 1 FLASH Starter Kit software • SEEVAL® designer kit for memory evaluation and A complete "development system in a box", the PICkit endurance calculations FLASH Starter Kit includes a convenient multi-section board for programming, evaluation, and development • PICDEM MSC demo boards for Switching mode of 8/14-pin FLASH PIC® microcontrollers. Powered via power supply, high power IR driver, delta sigma USB, the board operates under a simple Windows GUI. ADC, and flow rate sensor The PICkit 1 Starter Kit includes the user's guide (on Check the Microchip web page and the latest Product CD ROM), PICkit 1 tutorial software and code for vari- Line Card for the complete list of demonstration and ous applications. Also included are MPLAB® IDE (Inte- evaluation kits. grated Development Environment) software, software and hardware "Tips 'n Tricks for 8-pin FLASH PIC® Microcontrollers" Handbook and a USB Interface Cable. Supports all current 8/14-pin FLASH PIC microcontrollers, as well as many future planned devices.  2000-2013 Microchip Technology Inc. DS30569C-page 115

PIC16F870/871 NOTES: DS30569C-page 116  2000-2013 Microchip Technology Inc.

PIC16F870/871 14.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias.................................................................................................................-55 to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4).........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2)............................................................................................0 to +13.25V Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (combined) (Note 3)...................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3).................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3)............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD - VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to VSS. 3: PORTD and PORTE are not implemented on the 28-pin devices. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2000-2013 Microchip Technology Inc. DS30569C-page 117

PIC16F870/871 FIGURE 14-1: PIC16FXXX VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V e g a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 20 MHz Frequency FIGURE 14-2: PIC16LFXXX VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V e g 4.0V a t l o 3.5V V 3.0V E q u atio n 2 2.5V 2.0V E q u atio n 1 4 MHz 10 MHz 20 MHz Frequency Equation 1: FMAX = (6.0 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz; VDDAPPMIN = 2.0V - 3.0V Equation 2: FMAX = (10.0 MHz/V) (VDDAPPMIN – 3.0V) + 10 MHz; VDDAPPMIN = 3.0V - 4.0V Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application. Note 2: FMAX has a maximum frequency of 10 MHz. DS30569C-page 118  2000-2013 Microchip Technology Inc.

PIC16F870/871 14.1 DC Characteristics: PIC16F870/871 (Industrial, Extended) PIC16LF870/871 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) PIC16LF870/871 Operating temperature-40°C  TA  +85°C for Industrial (Commercial, Industrial) 0°C  TA  +70°C for Commercial Standard Operating Conditions (unless otherwise stated) PIC16F870/871 Operating temperature-40°C  TA  +85°C for Industrial (Industrial, Extended) -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ† Max Units Conditions No. VDD Supply Voltage D001 PIC16LF870/871 2.0 — 5.5 V All configurations. See Figure14-2 for details. D001 PIC16F870/871 4.0 — 5.5 V All configurations. D001A VBOR* — 5.5 V BOR enabled, FMAX = 14 MHz (Note 7), -40°C to +85°C VBOR — 5.5 V BOR enabled, FMAX = 10 MHz (Note 7), -40°C to +125°C D002* VDR RAM Data Retention — 1.5 — V Voltage(1) D003 VPOR VDD Start Voltage to — Vss — V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* SVDD VDD Rise Rate to ensure 0.05 — — V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 VBOR Brown-out Reset 3.7 4.0 4.35 V BOREN bit in configuration word enabled Voltage * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.  2000-2013 Microchip Technology Inc. DS30569C-page 119

PIC16F870/871 14.1 DC Characteristics: PIC16F870/871 (Industrial, Extended) PIC16LF870/871 (Commercial, Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF870/871 Operating temperature-40°C  TA  +85°C for Industrial (Commercial, Industrial) 0°C  TA  +70°C for Commercial Standard Operating Conditions (unless otherwise stated) PIC16F870/871 Operating temperature-40°C  TA  +85°C for Industrial (Industrial, Extended) -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ† Max Units Conditions No. IDD Supply Current(2,5) D010 PIC16LF870/871 — 0.6 2.0 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A — 20 35 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D010 PIC16F870/871 — 1.6 4 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 — 7 15 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V, -40C to +85C — 7 15 mA HS osc configuration FOSC = 10 MHz, VDD = 5.5V, -40C to +125C D015* IBOR Brown-out Reset — 85 200 A BOR enabled, VDD = 5.0V Current(6) IPD Power-down Current(3,5) D020 PIC16LF870/871 — 7.5 30 A VDD = 3.0V, WDT enabled, -40C to +85C D021 — 0.8 4.5 A VDD = 3.0V, WDT disabled, 0C to +70C D021A — 0.9 5 A VDD = 3.0V, WDT disabled, -40C to +85C D020 PIC16F870/871 — 10.5 42 A VDD = 4.0V, WDT enabled, -40C to +85C D20A — 10.5 60 A VDD = 4.0V, WDT enabled, -40C to +125C D021 — 1.5 16 A VDD = 4.0V, WDT disabled, -0C to +70C D021A — 1.5 19 A VDD = 4.0V, WDT disabled, -40C to +85C D21B — 1.5 30 A VDD = 4.0V, WDT disabled, -40C to +125C D023* IBOR Brown-out Reset — 85 200 A BOR enabled, VDD = 5.0V Current(6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. DS30569C-page 120  2000-2013 Microchip Technology Inc.

PIC16F870/871 14.2 DC Characteristics: PIC16F870/871 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section14.1 and Section14.2. Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS — 0.15 VDD V For entire VDD range D030A VSS — 0.8V V 4.5V  VDD 5.5V D031 with Schmitt Trigger buffer VSS — 0.2 VDD V D032 MCLR, OSC1 (in RC mode) VSS — 0.2 VDD V D033 OSC1 (in XT, HS and LP) VSS — 0.3 VDD V (Note 1) Ports RC3 and RC4: D034 with Schmitt Trigger buffer VSS — 0.3 VDD V For entire VDD range D034A with SMBus -0.5 — 0.6 V For VDD = 4.5 to 5.5V VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V 4.5V  VDD 5.5V D040A 0.25 VDD + — VDD V For entire VDD range 0.8V D041 with Schmitt Trigger buffer 0.8 VDD — VDD V For entire VDD range D042 MCLR 0.8 VDD — VDD V D042A OSC1 (XT, HS and LP) 0.7 VDD — VDD V (Note 1) D043 OSC1 (in RC mode) 0.9 VDD — VDD V Ports RC3 and RC4: D044 with Schmitt Trigger buffer 0.7 VDD — VDD V For entire VDD range D044A with SMBus 1.4 — 5.5 V for VDD = 4.5 to 5.5V D070 IPURB PORTB Weak Pull-up 50 250 400 A VDD = 5V, VPIN = VSS Current IIL Input Leakage Current (Notes 2, 3) D060 I/O ports — — 1 A Vss VPIN VDD, Pin at hi-impedance D061 MCLR, RA4/T0CKI — — 5 A Vss VPIN VDD D063 OSC1 — — 5 A Vss VPIN VDD, XT, HS and LP osc configuration * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F870/871 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2000-2013 Microchip Technology Inc. DS30569C-page 121

PIC16F870/871 14.2 DC Characteristics: PIC16F870/871 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section14.1 and Section14.2. Param Sym Characteristic Min Typ† Max Units Conditions No. VOL Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKO (RC osc config) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C VOH Output High Voltage D090 I/O ports (Note 3) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D092 OSC2/CLKO (RC osc config) VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C D150* VOD Open Drain High Voltage — — 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 CIO All I/O pins and OSC2 — — 50 pF (in RC mode) D102 CB SCL, SDA in I2C mode — — 400 pF Data EEPROM Memory D120 ED Endurance 100K — — E/W 25C at 5V D121 VDRW VDD for read/write VMIN — 5.5 V Using EECON to read/write VMIN = min operating voltage D122 TDEW Erase/write cycle time — 4 8 ms Program FLASH Memory D130 EP Endurance 1000 — — E/W 25C at 5V D131 VPR VDD for read VMIN — 5.5 V VMIN = min operating voltage D132a VDD for erase/write VMIN — 5.5 V Using EECON to read/write, VMIN = min operating voltage D133 TPEW Erase/Write cycle time — 4 8 ms * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F870/871 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30569C-page 122  2000-2013 Microchip Technology Inc.

PIC16F870/871 14.3 DC Characteristics: PIC16F870/871 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C DC CHARACTERISTICS Operating voltage VDD range as described in DC specification (Section) Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS — 0.15 VDD V For entire VDD range D030A VSS — 0.8V V 4.5V  VDD 5.5V D031 with Schmitt Trigger buffer VSS — 0.2 VDD V D032 MCLR, OSC1 (in RC mode) VSS — 0.2 VDD V D033 OSC1 (in XT, HS and LP) VSS — 0.3 VDD V (Note 1) Ports RC3 and RC4: D034 with Schmitt Trigger buffer VSS — 0.3 VDD V For entire VDD range D034A with SMBus -0.5 — 0.6 V For VDD = 4.5 to 5.5V VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V 4.5V  VDD 5.5V D040A 0.25 VDD — VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8 VDD — VDD V For entire VDD range D042 MCLR 0.8 VDD — VDD V D042A OSC1 (XT, HS and LP) 0.7 VDD — VDD V (Note 1) D043 OSC1 (in RC mode) 0.9 VDD — VDD V Ports RC3 and RC4: D044 with Schmitt Trigger buffer 0.7 VDD — VDD V For entire VDD range D044A with SMBus 1.4 — 5.5 V For VDD = 4.5 to 5.5V D070A IPURB PORTB Weak Pull-up Current 50 250 400 A VDD = 5V, VPIN = VSS IIL Input Leakage Current(2,3) D060 I/O ports — — 1 A Vss VPIN VDD, Pin at hi-impedance D061 MCLR, RA4/T0CKI — — 5 A Vss VPIN VDD D063 OSC1 — — 5 A Vss VPIN VDD, XT, HS and LP osc configuration * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F87X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2000-2013 Microchip Technology Inc. DS30569C-page 123

PIC16F870/871 14.3 DC Characteristics: PIC16F870/871 (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C DC CHARACTERISTICS Operating voltage VDD range as described in DC specification (Section) Param Sym Characteristic Min Typ† Max Units Conditions No. VOL Output Low Voltage D080A I/O ports — — 0.6 V IOL = 7.0 mA, VDD = 4.5V D083A OSC2/CLKO (RC osc config) — — 0.6 V IOL = 1.2 mA, VDD = 4.5V VOH Output High Voltage D090A I/O ports(3) VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V D092A OSC2/CLKO (RC osc config) VDD – 0.7 — — V IOH = -1.0 mA, VDD = 4.5V D150* VOD Open Drain High Voltage — — 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 — — 50 pF (RC mode) D102 CB SCL, SDA (I2C mode) — — 400 pF Data EEPROM Memory D120 ED Endurance 100K — — E/W 25C at 5V D121 VDRW VDD for read/write VMIN — 5.5 V Using EECON to read/write, VMIN = min. operating voltage D122 TDEW Erase/write cycle time — 4 8 ms Program FLASH Memory D130 EP Endurance 1000 — — E/W 25C at 5V D131 VPR VDD for read VMIN — 5.5 V VMIN = min operating voltage D132A VDD for erase/write VMIN — 5.5 V Using EECON to read/write, VMIN = min. operating voltage D133 TPEW Erase/Write cycle time — 4 8 ms * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F87X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30569C-page 124  2000-2013 Microchip Technology Inc.

PIC16F870/871 14.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition  2000-2013 Microchip Technology Inc. DS30569C-page 125

PIC16F870/871 FIGURE 14-3: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464 CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports 15 pF for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16F870. FIGURE 14-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO DS30569C-page 126  2000-2013 Microchip Technology Inc.

PIC16F870/871 TABLE 14-1: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. FOSC External CLKI Frequency DC — 4 MHz XT and RC Osc mode (Note 1) DC — 4 MHz HS Osc mode (-04) DC — 20 MHz HS Osc mode (-20) DC — 200 kHz LP Osc mode Oscillator Frequency DC — 4 MHz RC Osc mode (Note 1) 0.1 — 4 MHz XT Osc mode 4 — 20 MHz HS Osc mode 5 — 200 kHz LP Osc mode 1 TOSC External CLKI Period 250 — — ns XT and RC Osc mode (Note 1) 250 — — ns HS Osc mode (-04) 50 — — ns HS Osc mode (-20) 5 — — s LP Osc mode Oscillator Period 250 — — ns RC Osc mode (Note 1) 250 — 10,000 ns XT Osc mode 250 — 250 ns HS Osc mode (-04) 50 — 250 ns HS Osc mode (-20) 5 — — s LP Osc mode 2 TCY Instruction Cycle Time 200 TCY DC ns TCY = 4/FOSC (Note 1) 3 TosL, External Clock in (OSC1) High 100 — — ns XT oscillator TosH or Low Time 2.5 — — s LP oscillator 15 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise — — 25 ns XT oscillator TosF or Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper- ation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  2000-2013 Microchip Technology Inc. DS30569C-page 127

PIC16F870/871 FIGURE 14-5: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 18 12 14 19 16 I/O Pin (Input) 17 15 I/O Pin Old Value New Value (Output) 20, 21 Note: Refer to Figure14-3 for load conditions. TABLE 14-2: CLKO AND I/O TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1 to CLKO — 75 200 ns (Note 1) 11* TosH2ckH OSC1 to CLKO — 75 200 ns (Note 1) 12* TckR CLKO rise time — 35 100 ns (Note 1) 13* TckF CLKO fall time — 35 100 ns (Note 1) 14* TckL2ioV CLKO to Port out valid — — 0.5 TCY + 20 ns (Note 1) 15* TioV2ckH Port in valid before CLKO TOSC + 200 — — ns (Note 1) 16* TckH2ioI Port in hold after CLKO 0 — — ns (Note 1) 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 100 255 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input Standard (F) 100 — — ns invalid (I/O in hold time) Extended (LF) 200 — — ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TIOR Port output rise time Standard (F) — 10 40 ns Extended (LF) — — 145 ns 21* TIOF Port output fall time Standard (F) — 10 40 ns Extended (LF) — — 145 ns 22††* TINP INT pin high or low time TCY — — ns 23††* TRBP RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode where CLKO output is 4 x TOSC. DS30569C-page 128  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Osc Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure14-3 for load conditions. FIGURE 14-7: BROWN-OUT RESET TIMING VDD VBOR 35 TABLE 14-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +85°C 31* TWDT Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +85°C (No Prescaler) 32 TOST Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33* TPWRT Power up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C 34 TIOZ I/O Hi-impedance from MCLR Low or — — 2.1 s Watchdog Timer Reset 35 TBOR Brown-out Reset pulse width 100 — — s VDD  VBOR (D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2000-2013 Microchip Technology Inc. DS30569C-page 129

PIC16F870/871 FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure14-3 for load conditions. TABLE 14-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns Must also meet parameter 42 With Prescaler 10 — — ns 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet Synchronous, Standard(F) 15 — — ns parameter 47 Prescaler = 2,4,8 Extended(LF) 25 — — ns Asynchronous Standard(F) 30 — — ns Extended(LF) 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet Synchronous, Standard(F) 15 — — ns parameter 47 Prescaler = 2,4,8 Extended(LF) 25 — — ns Asynchronous Standard(F) 30 — — ns Extended(LF) 50 — — ns 47* Tt1P T1CKI input period Synchronous Standard(F) Greater of: — — ns N = prescale value 30 or TCY + 40 (1, 2, 4, 8) N Extended(LF) Greater of: N = prescale value 50 or TCY + 40 (1, 2, 4, 8) N Asynchronous Standard(F) 60 — — ns Extended(LF) 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1 Delay from external clock edge to timer increment 2 TOSC — 7 TOSC — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30569C-page 130  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 14-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure14-3 for load conditions. TABLE 14-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Param Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL * CCP1 No Prescaler 0.5 TCY + 20 — — ns input low Standard(F) 10 — — ns With Prescaler time Extended(LF) 20 — — ns 51* TccH CCP1 input high time No Prescaler 0.5 TCY + 20 — — ns Standard(F) 10 — — ns With Prescaler Extended(LF) 20 — — ns 52* TccP CCP1 input period 3 TCY + 40 — — ns N = prescale value N (1,4 or 16) 53* TccR CCP1 output rise time Standard(F) — 10 25 ns Extended(LF) — 25 50 ns 54* TccF CCP1 output fall time Standard(F) — 10 25 ns Extended(LF) — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2000-2013 Microchip Technology Inc. DS30569C-page 131

PIC16F870/871 FIGURE 14-10: PARALLEL SLAVE PORT TIMING (PIC16F871 ONLY) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure14-3 for load conditions. TABLE 14-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F871 ONLY) Param Sym Characteristic Min Typ† Max Units Conditions No. 62 TdtV2wrH Data in valid before WR or CS (setup time) 20 — — ns 25 — — ns Extended range only 63* TwrH2dtI WR or CS to data–in invalid (hold time) Standard(F) 20 — — ns Extended(LF) 35 — — ns 64 TrdL2dtV RD and CS to data–out valid — — 80 ns — — 90 ns Extended range only 65 TrdH2dtI RD or CS to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30569C-page 132  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 14-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK 121 pin 121 RC7/RX/DT pin 120 122 Note: Refer to Figure14-3 for load conditions. TABLE 14-7: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) Standard(F) Clock high to data out valid — — 80 ns Extended(LF) — — 100 ns 121 Tckrf Clock out rise time and fall time Standard(F) — — 45 ns (Master mode) Extended(LF) — — 50 ns 122 Tdtrf Data out rise time and fall time Standard(F) — — 45 ns Extended(LF) — — 50 ns † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 14-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure14-3 for load conditions. TABLE 14-8: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 125 TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK  (DT setup time) 15 — — ns 126 TckL2dtl Data hold after CK  (DT hold time) 15 — — ns † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.  2000-2013 Microchip Technology Inc. DS30569C-page 133

PIC16F870/871 TABLE 14-9: PIC16F870/871 (INDUSTRIAL) PIC16LF870/871 (INDUSTRIAL) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 10-bits bit VREF = VDD = 5.12V, VSS  VAIN  VREF A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A07 EGN Gain error — — < ± 1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A10 — Monotonicity(3) — guaranteed — — VSS  VAIN  VREF A20 VREF Reference voltage (VREF+ – VREF-) 2.0V — VDD + 0.3 V A21 VREF+ Reference voltage High VDD – 2.5V VDD + 0.3V V Must meet spec. A20 A22 VREF- Reference voltage Low VSS – 0.3V VREF+ – 2.0V V Must meet spec. A20 A25 VAIN Analog input voltage VSS – 0.3 — VREF + 0.3 V A30 ZAIN Recommended impedance of — — 10.0 k analog voltage source A40 IAD A/D conversion Standard(F) — 220 — A Average current consumption current (VDD) Extended(LF) — 90 — A when A/D is on (Note 1). A50 IREF VREF input current (Note 2) 10 — 1000 A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section10.1. — — 10 A During A/D Conversion cycle * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. DS30569C-page 134  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 14-13: A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 132 A/D DATA 9 8 7   2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 14-10: A/D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D clock period Standard(F) 1.6 — — s TOSC based, VREF  3.0V Extended(LF) 3.0 — — s TOSC based, VREF  2.0V Standard(F) 2.0 4.0 6.0 s A/D RC Mode Extended(LF) 3.0 6.0 9.0 s A/D RC Mode 131 TCNV Conversion time (not including S/H time) — 12 TAD (Note 1) 132 TACQ Acquisition time (Note 2) 40 — s 10* — — s The minimum time is the ampli- fier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section10.1 for min conditions.  2000-2013 Microchip Technology Inc. DS30569C-page 135

PIC16F870/871 NOTES: DS30569C-page 136  2000-2013 Microchip Technology Inc.

PIC16F870/871 15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over the whole temperature range. FIGURE 15-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) 7 Typical: statistical mean @ 25°C 6 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 5 5.5V 4 A) 5.0V m (DD 4.5V I 3 4.0V 2 3.5V 3.0V 1 2.5V 2.0V 0 4 6 8 10 12 14 16 18 20 FOSC (MHz) FIGURE 15-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) 8 Typical: statistical mean @ 25°C 7 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 6 5.5V 5 5.0V A) (mDD 4 4.5V I 4.0V 3 3.5V 2 3.0V 1 2.5V 2.0V 0 4 6 8 10 12 14 16 18 20 FOSC (MHz)  2000-2013 Microchip Technology Inc. DS30569C-page 137

PIC16F870/871 FIGURE 15-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.6 Typical: statistical mean @ 25°C 1.4 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 5.5V 1.2 5.0V 1.0 4.5V A) (mD 0.8 4.0V D I 3.5V 0.6 3.0V 0.4 2.5V 2.0V 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 15-4: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 2.0 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 5.5V 1.4 5.0V 1.2 A) 4.5V m 1.0 (DD 4.0V I 0.8 3.5V 0.6 3.0V 2.5V 0.4 2.0V 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) DS30569C-page 138  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 15-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 90 Typical: statistical mean @ 25°C 80 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 5.5V 70 5.0V 60 4.5V 50 A) 4.0V u (D D I 40 3.5V 3.0V 30 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 15-6: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 120 110 Typical: statistical mean @ 25°C 5.5V Maximum: mean + 3 (-40°C to 125°C) 100 Minimum: mean – 3 (-40°C to 125°C) 5.0V 90 80 4.5V 70 A) 4.0V (uD 60 D I 3.5V 50 3.0V 40 2.5V 30 2.0V 20 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz)  2000-2013 Microchip Technology Inc. DS30569C-page 139

PIC16F870/871 FIGURE 15-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20pF, 25C) 4.0 3.3k 3.5 3.0 5.1k 2.5 z) H M q ( 2.0 e Fr 10k 1.5 1.0 0.5 100k 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100pF, 25C) 2.0 1.8 1.6 3.3 k 1.4 1.2 z) H 5.1 k M q ( 1.0 e Fr 0.8 0.6 10 k 0.4 0.2 100 k 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30569C-page 140  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 15-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300pF, 25C) 1.0 0.9 0.8 3.3 k 0.7 0.6 z) H M 5.1 k 0.5 q ( e Fr 0.4 0.3 10 k 0.2 0.1 100 k 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-10: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 100.00 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Max (125C) 10.00 Max (85C) A)  (D 1.00 P I 0.10 Typ (25C) 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2000-2013 Microchip Technology Inc. DS30569C-page 141

PIC16F870/871 FIGURE 15-11: IBOR vs. VDD OVER TEMPERATURE 1.2 Note: Device current in RESET 1.0 depends on Oscillator mode, Typical: statistical mean @ 25°C frequency and circuit. Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 0.8 A) m Max RESET ( 0.6 I Typ RESET (25°C) Indeterminate State 0.4 Device in SLEEP Device in RESET 0.2 Max SLEEP Typ SLEEP (25°C) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-12: TYPICAL AND MAXIMUMITMR1 vs. VDD OVER TEMPERATURE (-10C TO 70C, TIMER1 WITH OSCILLATOR, XTAL=32 kHZ, C1 AND C2=50pF) 90 Typical: statistical mean @ 25°C 80 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 70 60 A) 50 u 1 ( R M T 40 I Max 30 Typ (25C) 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30569C-page 142  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 15-13: TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE 14 Typical: statistical mean @ 25°C 12 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 10 Max (85C) 8 A) u Typ (25C) (T D W I 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO 125C) 60 Typical: statistical mean @ 25°C 50 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 40 s) m d ( Max (125C) o eri 30 P T D W 20 Typ (25C) 10 Min (-40C) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2000-2013 Microchip Technology Inc. DS30569C-page 143

PIC16F870/871 FIGURE 15-15: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40C TO 125C) 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) 40 Minimum: mean – 3 (-40°C to 125°C) 125C 35 85C s) 30 m d ( o Peri 25 25C T D W 20 -40C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO 125C) 5.0 Max (-40C) 4.5 Typ (25C) 4.0 V) (H 3.5 O V Min (125C) 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.0 0 5 10 15 20 25 IOH (-mA) DS30569C-page 144  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 15-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO 125C) 3.0 Max (-40C) Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Typ (25C) 2.0 V) (H 1.5 O V Min (125C) 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 15-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO 125C) 2.0 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.4 1.2 V) (L 1.0 VO Max (125C) 0.8 0.6 Typ (25C) 0.4 Min (-40C) 0.2 0.0 0 5 10 15 20 25 IOL (-mA)  2000-2013 Microchip Technology Inc. DS30569C-page 145

PIC16F870/871 FIGURE 15-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO 125C) 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.0 V) (L 1.5 O V Max (125C) 1.0 Typ (25C) 0.5 Min (-40C) 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 15-20: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40C TO 125C) 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Max (-40C) 1.4 1.2 Min (125C) 1.0 V) (N VI 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30569C-page 146  2000-2013 Microchip Technology Inc.

PIC16F870/871 FIGURE 15-21: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO 125C) 4.5 Typical: statistical mean @ 25°C 4.0 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 3.5 Max High (125C) 3.0 Min High (-40C) 2.5 V) (N VI 2.0 Max Low (125C) 1.5 Min Low (-40C) 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-22: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO 125C) 3.5 Typical: statistical mean @ 25°C 3.0 Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Max High (125C) 2.5 Min High (-40C) Max Low (125C) 2.0 V) Min Low (25C) (N VI 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2000-2013 Microchip Technology Inc. DS30569C-page 147

PIC16F870/871 NOTES: DS30569C-page 148  2000-2013 Microchip Technology Inc.

PIC16F870/871 16.0 PACKAGING INFORMATION 16.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example XXXXXXXXXXXXXXXXX PIC16F870-I/SP XXXXXXXXXXXXXXXXX YYWWNNN 0317017 28-Lead SOIC Example XXXXXXXXXXXXXXXXX PIC16F870-I/SO XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 0310017 28-Lead SSOP Example XXXXXXXXXXXX PIC16F870-I/SS XXXXXXXXXXXX YYWWNNN 0320017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2000-2013 Microchip Technology Inc. DS30569C-page 149

PIC16F870/871 Package Marking Information (Cont’d) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX PIC16F871-I/P XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 0312017 44-Lead TQFP Example XXXXXXXXXX PIC16F871 XXXXXXXXXX -I/PT XXXXXXXXXX YYWWNNN 0320017 44-Lead PLCC Example XXXXXXXXXX PIC16F871 XXXXXXXXXX -I/L XXXXXXXXXX YYWWNNN 0320017 DS30569C-page 150  2000-2013 Microchip Technology Inc.

PIC16F870/871 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1  E A2 A L c  A1 B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 8.26 Molded Package Width E1 .275 .285 .295 6.99 7.24 7.49 Overall Length D 1.345 1.365 1.385 34.16 34.67 35.18 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .040 .053 .065 1.02 1.33 1.65 Lower Lead Width B .016 .019 .022 0.41 0.48 0.56 Overall Row Spacing § eB .320 .350 .430 8.13 8.89 10.92 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070  2000-2013 Microchip Technology Inc. DS30569C-page 151

PIC16F870/871 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1 h  45 c A A2   L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .288 .295 .299 7.32 7.49 7.59 Overall Length D .695 .704 .712 17.65 17.87 18.08 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle Top  0 4 8 0 4 8 Lead Thickness c .009 .011 .013 0.23 0.28 0.33 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top  0 12 15 0 12 15 Mold Draft Angle Bottom  0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 DS30569C-page 152  2000-2013 Microchip Technology Inc.

PIC16F870/871 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1  A c A2  A1 L  Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .026 0.65 Overall Height A .068 .073 .078 1.73 1.85 1.98 Molded Package Thickness A2 .064 .068 .072 1.63 1.73 1.83 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Overall Width E .299 .309 .319 7.59 7.85 8.10 Molded Package Width E1 .201 .207 .212 5.11 5.25 5.38 Overall Length D .396 .402 .407 10.06 10.20 10.34 Foot Length L .022 .030 .037 0.56 0.75 0.94 Lead Thickness c .004 .007 .010 0.10 0.18 0.25 Foot Angle  0 4 8 0.00 101.60 203.20 Lead Width B .010 .013 .015 0.25 0.32 0.38 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073  2000-2013 Microchip Technology Inc. DS30569C-page 153

PIC16F870/871 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2  n 1 E A A2 L c B1  A1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 40 40 Pitch p .100 2.54 Top to Seating Plane A .160 .175 .190 4.06 4.45 4.83 Molded Package Thickness A2 .140 .150 .160 3.56 3.81 4.06 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .595 .600 .625 15.11 15.24 15.88 Molded Package Width E1 .530 .545 .560 13.46 13.84 14.22 Overall Length D 2.045 2.058 2.065 51.94 52.26 52.45 Tip to Seating Plane L .120 .130 .135 3.05 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .030 .050 .070 0.76 1.27 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .620 .650 .680 15.75 16.51 17.27 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016 DS30569C-page 154  2000-2013 Microchip Technology Inc.

PIC16F870/871 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45  A c   A1 A2 L (F) Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .031 0.80 Pins per Side n1 11 11 Overall Height A .039 .043 .047 1.00 1.10 1.20 Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Foot Length L .018 .024 .030 0.45 0.60 0.75 Footprint (Reference) (F) .039 1.00 Foot Angle  0 3.5 7 0 3.5 7 Overall Width E .463 .472 .482 11.75 12.00 12.25 Overall Length D .463 .472 .482 11.75 12.00 12.25 Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10 Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .012 .015 .017 0.30 0.38 0.44 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076  2000-2013 Microchip Technology Inc. DS30569C-page 155

PIC16F870/871 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 1 2 CH2 x 45 CH1 x 45 A3  A2 A 35 B1 c B A1  p E2 D2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .050 1.27 Pins per Side n1 11 11 Overall Height A .165 .173 .180 4.19 4.39 4.57 Molded Package Thickness A2 .145 .153 .160 3.68 3.87 4.06 Standoff § A1 .020 .028 .035 0.51 0.71 0.89 Side 1 Chamfer Height A3 .024 .029 .034 0.61 0.74 0.86 Corner Chamfer 1 CH1 .040 .045 .050 1.02 1.14 1.27 Corner Chamfer (others) CH2 .000 .005 .010 0.00 0.13 0.25 Overall Width E .685 .690 .695 17.40 17.53 17.65 Overall Length D .685 .690 .695 17.40 17.53 17.65 Molded Package Width E1 .650 .653 .656 16.51 16.59 16.66 Molded Package Length D1 .650 .653 .656 16.51 16.59 16.66 Footprint Width E2 .590 .620 .630 14.99 15.75 16.00 Footprint Length D2 .590 .620 .630 14.99 15.75 16.00 Lead Thickness c .008 .011 .013 0.20 0.27 0.33 Upper Lead Width B1 .026 .029 .032 0.66 0.74 0.81 Lower Lead Width B .013 .020 .021 0.33 0.51 0.53 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-048 DS30569C-page 156  2000-2013 Microchip Technology Inc.

PIC16F870/871 APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (December 1999) The differences between the devices listed in this data Original data sheet for the PIC16F870/871 family. sheet are shown in TableB-1. Revision B (April 2003) This revision includes the DC and AC Characteristics Graphs and Tables. The Electrical Specifications in Section14.0 have been updated and there have been minor corrections to the data sheet text. Revision C (January 2013) Added a note to each package outline drawing. TABLE B-1: DEVICE DIFFERENCES Feature PIC16F870 PIC16F871 On-chip Program Memory (Kbytes) 2K 2K Data Memory (bytes) 128 128 Boot Block (bytes) 2048 512 Timer1 Low Power Option Yes No I/O Ports Ports A, B, C Ports A, B, C, D, E A/D Channels 5 8 External Memory Interface No No Package Types 28-pin DIP, SOIC, SSOP 40-pin PDIP, 44-pin PLCC, TQFP  2000-2013 Microchip Technology Inc. DS30569C-page 157

PIC16F870/871 APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM CONSIDERATIONS MID-RANGE TO ENHANCED DEVICES This appendix discusses the considerations for con- verting from previous versions of a device to the ones A detailed discussion of the differences between the listed in this data sheet. Typically, these changes are mid-range MCU devices (i.e., PIC16CXXX) and the due to the differences in the process technology used. enhanced devices (i.e., PIC18FXXX) is provided in An example of this type of conversion is from a AN716, “Migrating Designs from PIC16C74A/74B to PIC17C756 to a PIC18F8720. PIC18C442.” The changes discussed, while device Not Applicable specific, are generally applicable to all mid-range to enhanced device migrations. This Application Note is available as Literature Number DS00716. DS30569C-page 158  2000-2013 Microchip Technology Inc.

PIC16F870/871 APPENDIX E: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and dif- ferences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXXX) is provided in AN726, “PIC17CXXX to PIC18CXXX Migration.” This Application Note is available as Literature Number DS00726.  2000-2013 Microchip Technology Inc. DS30569C-page 159

PIC16F870/871 NOTES: DS30569C-page 160  2000-2013 Microchip Technology Inc.

PIC16F870/871 INDEX A Timer1........................................................................50 Timer2........................................................................53 A/D......................................................................................79 USART Asynchronous Receive..................................68 Acquisition Requirements...........................................82 USART Asynchronous Receive (9-bit Mode).............70 ADCON0 Register.......................................................79 USART Transmit........................................................66 ADCON1 Register.......................................................79 Watchdog Timer.........................................................99 ADIF Bit.......................................................................80 BOR. See Brown-out Reset. ADRESH Register.......................................................79 BRGH Bit............................................................................63 ADRESL Register.......................................................79 Brown-out Reset (BOR)....................................87, 91, 92, 93 Analog Port Pins...................................................41, 42 BOR Status (BOR Bit)................................................23 Associated Registers and Bits....................................85 Calculating Acquisition Time.......................................82 C Configuring Analog Port Pins......................................83 C Compilers Configuring the Interrupt.............................................81 MPLAB C17..............................................................112 Configuring the Module...............................................81 MPLAB C18..............................................................112 Conversion Clock........................................................83 MPLAB C30..............................................................112 Conversions................................................................84 Capture/Compare/PWM (CCP)..........................................55 Delays.........................................................................82 Associated Registers Effects of a RESET.....................................................85 Capture, Compare and Timer1...........................59 GO/DONE Bit..............................................................80 PWM and Timer2................................................60 Internal Sampling Switch (Rss) Impedance................82 Capture Mode.............................................................56 Operation During SLEEP............................................85 CCP1IF...............................................................56 Result Registers..........................................................84 Prescaler............................................................56 Source Impedance......................................................82 CCP Timer Resources................................................55 Time Delays................................................................82 Compare Absolute Maximum Ratings..............................................117 Special Trigger Output of CCP1.........................57 ADCON0 Register...............................................................13 Compare Mode...........................................................57 ADCON1 Register...............................................................14 Software Interrupt Mode.....................................57 ADRESH Registers.............................................................13 Special Event Trigger.........................................57 ADRESL Register...............................................................14 PWM Mode.................................................................58 Analog-to-Digital Converter. See A/D. Duty Cycle..........................................................58 Application Notes Example Frequencies/Resolutions (table)..........59 AN552 (Implementing Wake-up on Key Stroke).........35 PWM Period.......................................................58 AN556 (Implementing a Table Read).........................24 Setup for PWM Operation..................................59 Assembler Special Event Trigger and A/D Conversions..............57 MPASM Assembler...................................................111 CCP. See Capture/Compare/PWM. Asynchronous Reception CCP1CON Register............................................................13 Associated Registers..................................................69 CCP1M0 Bit........................................................................55 Asynchronous Reception (9-bit Mode) CCP1M1 Bit........................................................................55 Associated Registers..................................................71 CCP1M2 Bit........................................................................55 B CCP1M3 Bit........................................................................55 CCP1X Bit..........................................................................55 Banking, Data Memory.......................................................11 CCP1Y Bit..........................................................................55 Baud Rate Generator (BRG) CCPR1H Register.........................................................13, 55 Associated Registers..................................................63 CCPR1L Register.........................................................13, 55 Block Diagrams Code Examples A/D..............................................................................81 Changing Between Capture Prescalers.....................56 Analog Input Model.....................................................82 EEPROM Data Read..................................................29 Capture Mode Operation............................................56 EEPROM Data Write..................................................29 Compare Mode Operation..........................................57 FLASH Program Read................................................30 Interrupt Logic.............................................................97 FLASH Program Write................................................31 On-Chip RESET Circuit..............................................91 Indirect Addressing.....................................................24 PIC16F870....................................................................5 Initializing PORTA......................................................33 PIC16F871....................................................................6 Saving STATUS, W and PCLATH Registers PORTC (Peripheral Output Override).........................37 in RAM................................................................98 PORTD (In I/O Port Mode)..........................................38 Code Protected Operation PORTD and PORTE (Parallel Slave Port)..................42 Data EEPROM and FLASH Program Memory...........31 PORTE (In I/O Port Mode)..........................................39 Code Protection..........................................................87, 101 PWM Mode.................................................................58 Computed GOTO................................................................24 RA3:RA0 and RA5 Pins..............................................33 Configuration Bits...............................................................87 RA4/T0CKI Pin............................................................33 Configuration Word.............................................................88 RB3:RB0 Pins.............................................................35 Conversion Considerations...............................................158 RB7:RB4 Pins.............................................................35 Timer0/WDT Prescaler...............................................45  2000-2013 Microchip Technology Inc. DS30569C-page 161

PIC16F870/871 D Indirect Addressing.............................................................25 FSR Register........................................................11, 24 Data EEPROM....................................................................27 INDF Register.............................................................24 Associated Registers..................................................32 Instruction Descriptions....................................................105 Code Protection..........................................................31 Instruction Format.............................................................103 Reading.......................................................................29 Instruction Set...................................................................103 Spurious Write Protection...........................................31 ADDLW.....................................................................105 Write Verify.................................................................31 ADDWF.....................................................................105 Writing to.....................................................................29 ANDLW.....................................................................105 Data Memory.......................................................................11 ANDWF.....................................................................105 Bank Select (RP1:RP0 Bits).......................................11 BCF..........................................................................105 General Purpose Registers.........................................11 BSF...........................................................................105 Register File Map........................................................12 BTFSC......................................................................105 Special Function Registers.........................................13 BTFSS......................................................................105 DC and AC Characteristics Graphs and Tables................137 CALL.........................................................................106 DC Characteristics CLRF........................................................................106 PIC16F870/871 (Extended)......................................123 CLRW.......................................................................106 PIC16F870/871 (Industrial).......................................121 CLRWDT..................................................................106 PIC16F870/871 (Industrial, Extended) and COMF.......................................................................106 PIC16LF870/871 (Commercial, Industrial)........119 DECF........................................................................106 Demonstration Boards DECFSZ...................................................................107 PICDEM 1.................................................................114 GOTO.......................................................................107 PICDEM 17...............................................................114 INCF.........................................................................107 PICDEM 18R PIC18C601/801..................................115 INCFSZ.....................................................................107 PICDEM 2 Plus.........................................................114 IORLW......................................................................107 PICDEM 3 PIC16C92X.............................................114 IORWF......................................................................107 PICDEM 4.................................................................114 MOVF.......................................................................108 PICDEM LIN PIC16C43X.........................................115 MOVLW....................................................................108 PICDEM USB PIC16C7X5........................................115 MOVWF....................................................................108 PICDEM.net Internet/Ethernet..................................114 NOP..........................................................................108 Development Support.......................................................111 RETFIE.....................................................................108 Device Differences............................................................157 RETLW.....................................................................108 Device Overview...................................................................5 RETURN...................................................................109 Direct Addressing................................................................25 RLF...........................................................................109 E RRF..........................................................................109 EEADR Register.................................................................15 SLEEP......................................................................109 EEADRH Register...............................................................15 SUBLW.....................................................................109 EECON1 Register.........................................................15, 27 SUBWF.....................................................................109 EECON2 Register.........................................................15, 27 SWAPF.....................................................................110 EEDATA Register...............................................................15 XORLW....................................................................110 EEDATH Register...............................................................15 XORWF....................................................................110 Electrical Characteristics...................................................117 Summary Table........................................................104 Errata....................................................................................4 INT Interrupt (RB0/INT). See Interrupt Sources. Evaluation and Programming Tools..................................115 INTCON..............................................................................15 INTCON Register..........................................................13, 15 F GIE Bit........................................................................18 Firmware Instructions........................................................103 INTE Bit......................................................................18 FLASH Program Memory....................................................27 INTF Bit......................................................................18 Associated Registers..................................................32 PEIE Bit......................................................................18 Code Protection..........................................................31 RBIE Bit......................................................................18 Configuration Bits and Read/Write State....................32 RBIF Bit................................................................18, 35 Reading.......................................................................30 T0IE Bit.......................................................................18 Spurious Write Protection...........................................31 Internal Sampling Switch (Rss) Impedance........................82 Write Protection..........................................................32 Interrupt Sources..........................................................87, 96 Write Verify.................................................................31 Interrupt-on-Change (RB7:RB4).................................35 Writing to.....................................................................30 RB0/INT Pin, External.................................................97 FSR Register...........................................................13, 14, 15 TMR0 Overflow...........................................................97 USART Receive/Transmit Complete..........................61 I Interrupts, Context Saving During.......................................98 I/O Ports..............................................................................33 ID Locations................................................................87, 101 In-Circuit Debugger.....................................................87, 101 In-Circuit Serial Programming (ICSP).........................87, 102 INDF Register.........................................................13, 14, 15 DS30569C-page 162  2000-2013 Microchip Technology Inc.

PIC16F870/871 Interrupts, Enable Bits P Global Interrupt Enable (GIE Bit)..........................18, 96 Packaging.........................................................................149 Interrupt-on-Change (RB7:RB4) Enable Marking Information..................................................149 (RBIE Bit)......................................................18, 97 Parallel Slave Port (PSP)..........................................9, 38, 42 Peripheral Interrupt Enable (PEIE Bit)........................18 Associated Registers..................................................43 RB0/INT Enable (INTE Bit).........................................18 RE0/RD/AN5 Pin..................................................41, 42 TMR0 Overflow Enable (T0IE Bit)...............................18 RE1/WR/AN6 Pin.................................................41, 42 Interrupts, Flag Bits RE2/CS/AN7 Pin..................................................41, 42 Interrupt-on-Change (RB7:RB4) Select (PSPMODE Bit).............................38, 39, 40, 42 Flag (RBIF Bit)........................................18, 35, 97 PCL Register....................................................13, 14, 15, 24 RB0/INT Flag (INTF Bit)..............................................18 PCLATH Register.............................................13, 14, 15, 24 TMR0 Overflow Flag (T0IF Bit)...................................97 PCON Register.......................................................14, 15, 92 L BOR Bit.......................................................................23 POR Bit.......................................................................23 Loading of PC.....................................................................24 PICkit 1 FLASH Starter Kit................................................115 Low Voltage In-Circuit Serial Programming................87, 102 PICSTART Plus Development Programmer.....................113 M PIE1 Register...............................................................14, 15 PIE2 Register...............................................................14, 15 Master Clear (MCLR) Pinout Descriptions MCLR Reset, Normal Operation...........................91, 93 PIC16F870...................................................................7 MCLR Reset, SLEEP............................................91, 93 PIC16F871...................................................................8 MCLR/VPP/THV Pin..........................................................7, 8 PIR1 Register.....................................................................13 Memory Organization PIR2 Register.....................................................................13 Data Memory..............................................................11 POP....................................................................................24 Program Memory........................................................11 POR. See Power-on Reset. Migration from High-End to Enhanced Devices................159 PORTA.............................................................................7, 8 Migration from Mid-Range to Enhanced Devices.............158 Associated Registers..................................................34 MPLAB ASM30 Assembler, Linker, Librarian...................112 PORTA Register.........................................................33 MPLAB ICD 2 In-Circuit Debugger...................................113 RA0/AN0 Pin............................................................7, 8 MPLAB ICE 2000 High Performance Universal RA1/AN1 Pin............................................................7, 8 In-Circuit Emulator....................................................113 MPLAB ICE 4000 High Performance Universal RA2/AN2/VREF- Pin......................................................7 In-Circuit Emulator....................................................113 RA2/AN2/VREF- Pin......................................................8 MPLAB Integrated Development RA3/AN3/VREF+ Pin.....................................................7 Environment Software...............................................111 RA3/AN3/VREF+ Pin.....................................................8 RA4/T0CKI Pin.........................................................7, 8 MPLINK Object Linker/MPLIB Object Librarian................112 RA5/AN4 Pin............................................................7, 8 O TRISA Register...........................................................33 OPCODE Field Descriptions.............................................103 PORTA Register.................................................................13 OPTION..............................................................................15 PORTB.............................................................................7, 8 OPTION Register................................................................15 PORTB Register.........................................................35 OPTION_REG Register................................................14, 17 Pull-up Enable (RBPU Bit)..........................................17 INTEDG Bit.................................................................17 RB0/INT Edge Select (INTEDG Bit)...........................17 PSA Bit........................................................................17 RB0/INT Pin..............................................................7, 8 RBPU Bit.....................................................................17 RB0/INT Pin, External................................................97 T0CS Bit......................................................................17 RB1 Pin....................................................................7, 8 T0SE Bit......................................................................17 RB2 Pin....................................................................7, 8 OSC1/CLKI Pin.................................................................7, 8 RB3/PGM Pin...........................................................7, 8 OSC2/CLKO Pin...............................................................7, 8 RB4 Pin....................................................................7, 8 Oscillator Configuration.......................................................87 RB5 Pin....................................................................7, 8 HS.........................................................................89, 92 RB6/PGC Pin............................................................7, 8 LP..........................................................................89, 92 RB7/PGD Pin............................................................7, 8 RC...................................................................89, 90, 92 RB7:RB4 Interrupt-on-Change...................................97 XT.........................................................................89, 92 RB7:RB4 Interrupt-on-Change Enable (RBIE Bit).........................................18, 97 Oscillator, WDT...................................................................99 Oscillators RB7:RB4 Interrupt-on-Change Capacitor Selection.....................................................90 Flag (RBIF Bit)........................................18, 35, 97 Crystal and Ceramic Resonators................................89 TRISB Register...........................................................35 RC...............................................................................90 PORTB Register...........................................................13, 15  2000-2013 Microchip Technology Inc. DS30569C-page 163

PIC16F870/871 PORTC..............................................................................7, 8 Pulse Width Modulation. Associated Registers..................................................37 See Capture/Compare/PWM, PWM Mode. PORTC Register.........................................................37 PUSH..................................................................................24 RC0/T1OSO/T1CKI Pin............................................7, 8 R RC1/T1OSI Pin.........................................................7, 8 RC2/CCP1 Pin..........................................................7, 8 RAM. See Data Memory. RC3 Pin.....................................................................7, 8 RCREG Register................................................................13 RC4 Pin.....................................................................7, 8 RCSTA Register.................................................................13 RC5 Pin.....................................................................7, 8 ADDEN Bit..................................................................62 RC6/TX/CK Pin...................................................7, 8, 62 CREN Bit....................................................................62 RC7/RX/DT Pin.............................................7, 8, 62, 63 FERR Bit.....................................................................62 TRISC Register.....................................................37, 61 OERR Bit....................................................................62 PORTC Register.................................................................13 RX9 Bit.......................................................................62 PORTD............................................................................9, 42 RX9D Bit.....................................................................62 Associated Registers..................................................38 SPEN Bit...............................................................61, 62 Parallel Slave Port (PSP) Function.............................38 SREN Bit....................................................................62 PORTD Register.........................................................38 Register File........................................................................11 RD0/PSP0 Pin..............................................................9 Register File Map................................................................12 RD1/PSP1 Pin..............................................................9 Registers RD2/PSP2 Pin..............................................................9 ADCON0 (A/D Control 0)............................................79 RD3/PSP3 Pin..............................................................9 ADCON1 (A/D Control 1)............................................80 RD4/PSP4 Pin..............................................................9 CCP1CON (CCP Control 1)........................................55 RD5/PSP5 Pin..............................................................9 EECON1 (EEPROM Control 1)..................................28 RD6/PSP6 Pin..............................................................9 INTCON......................................................................18 RD7/PSP7 Pin..............................................................9 OPTION_REG......................................................17, 46 TRISD Register...........................................................38 PCON (Power Control)...............................................23 PORTD Register.................................................................13 PIE1 (Peripheral Interrupt Enable 1)...........................19 PORTE..................................................................................9 PIE2 (Peripheral Interrupt Enable 2)...........................21 Analog Port Pins...................................................41, 42 PIR1 (Peripheral Interrupt Request Flag 1)................20 Associated Registers..................................................41 PIR2 (Peripheral Interrupt Request Flag 2)................22 Input Buffer Full Status (IBF Bit).................................40 RCSTA (Receive Status and Control)........................62 Input Buffer Overflow (IBOV Bit).................................40 STATUS.....................................................................16 Output Buffer Full Status (OBF Bit).............................40 T1CON (Timer1 Control)............................................49 PORTE Register.........................................................39 T2CON (Timer 2 Control)...........................................53 PSP Mode Select (PSPMODE Bit)...........38, 39, 40, 42 TRISE.........................................................................40 RE0/RD/AN5 Pin...............................................9, 41, 42 TXSTA (Transmit Status and Control)........................61 RE1/WR/AN6 Pin..............................................9, 41, 42 Reset............................................................................87, 91 RE2/CS/AN7 Pin...............................................9, 41, 42 MCLR Reset. See MCLR. TRISE Register...........................................................39 RESET Conditions for All Registers...........................93 PORTE Register.................................................................13 RESET Conditions for PCON Register.......................93 Postscaler, WDT RESET Conditions for Program Counter....................93 Assignment (PSA Bit).................................................17 RESET Conditions for STATUS Register...................93 Power-down Mode. See SLEEP. Reset Power-on Reset (POR).....................................87, 91, 92, 93 Brown-out Reset (BOR). See Brown-out Reset (BOR). Oscillator Start-up Timer (OST)............................87, 92 Power-on Reset (POR). See Power-on Reset (POR). POR Status (POR Bit).................................................23 WDT Reset. See Watchdog Timer (WDT). Power Control (PCON) Register.................................92 Revision History................................................................157 Power-down (PD Bit)..................................................91 S Power-up Timer (PWRT)......................................87, 92 Time-out (TO Bit)........................................................91 SCI. See USART PR2.....................................................................................15 Serial Communication Interface. See USART. PR2 Register.................................................................14, 53 SLEEP..................................................................87, 91, 100 Prescaler, Timer0 Software Simulator (MPLAB SIM)....................................112 Assignment (PSA Bit).................................................17 Software Simulator (MPLAB SIM30)................................112 PRO MATE II Universal Device Programmer...................113 SPBRG...............................................................................15 Product Identification System............................................169 SPBRG Register.................................................................14 Program Counter Special Features of the CPU..............................................87 RESET Conditions......................................................93 Special Function Registers.................................................13 Program Memory................................................................11 Special Function Register Summary..........................13 Interrupt Vector...........................................................11 Speed, Operating..................................................................1 Map and Stack............................................................11 SSPADD Register...............................................................15 Paging.........................................................................24 SSPSTAT Register.............................................................15 RESET Vector.............................................................11 Stack...................................................................................24 Program Verification..........................................................101 Overflows....................................................................24 Programming, Device Instructions....................................103 Underflow...................................................................24 DS30569C-page 164  2000-2013 Microchip Technology Inc.

PIC16F870/871 STATUS Register.........................................................13, 15 Asynchronous Reception with PD Bit..........................................................................91 Address Detect...................................................71 TO Bit..........................................................................91 Brown-out Reset.......................................................129 Synchronous Master Reception Capture/Compare/PWM (CCP1)..............................131 Associated Registers..................................................75 CLKO and I/O...........................................................128 Synchronous Master Transmission External Clock..........................................................126 Associated Registers..................................................73 Parallel Slave Port (PSP) Read..................................43 Synchronous Slave Reception Parallel Slave Port (PSP) Write..................................43 Associated Registers..................................................77 RESET, Watchdog Timer, Oscillator Synchronous Slave Transmission Start-up Timer and Power-up Timer.................129 Associated Registers..................................................76 Slow Rise Time (MCLR Tied to VDD).........................96 Time-out Sequence on Power-up T (MCLR Not Tied to VDD) T1CKPS0 Bit.......................................................................49 Case 1................................................................95 T1CKPS1 Bit.......................................................................49 Case 2................................................................95 T1CON Register.................................................................13 Time-out Sequence on Power-up T1OSCEN Bit......................................................................49 (MCLR Tied to VDD)...........................................95 T1SYNC Bit.........................................................................49 Timer0 and Timer1 External Clock...........................130 T2CKPS0 Bit.......................................................................53 USART Asynchronous Reception..............................68 T2CKPS1 Bit.......................................................................53 USART Synchronous Receive (Master/Slave).........133 T2CON Register.................................................................13 USART Synchronous Reception TAD......................................................................................83 (Master Mode, SREN)........................................75 Time-out Sequence.............................................................92 USART Synchronous Transmission...........................73 Timer0.................................................................................45 USART Synchronous Transmission Associated Registers..................................................47 (Master/Slave)..................................................133 Clock Source Edge Select (T0SE Bit).........................17 Wake-up from SLEEP via Interrupt..........................101 Clock Source Select (T0CS Bit)..................................17 Timing Parameter Symbology..........................................125 External Clock.............................................................46 TMR0 Register..............................................................13, 15 Interrupt.......................................................................45 TMR1CS Bit........................................................................49 Overflow Enable (T0IE Bit).........................................18 TMR1H Register.................................................................13 Overflow Flag (T0IF Bit)..............................................97 TMR1L Register..................................................................13 Overflow Interrupt.......................................................97 TMR1ON Bit.......................................................................49 Prescaler.....................................................................46 TMR2 Register....................................................................13 T0CKI..........................................................................46 TMR2ON Bit.......................................................................53 Timer1.................................................................................49 TOUTPS0 Bit......................................................................53 Associated Registers..................................................52 TOUTPS1 Bit......................................................................53 Asynchronous Counter Mode TOUTPS2 Bit......................................................................53 Reading and Writing to.......................................51 TOUTPS3 Bit......................................................................53 Counter Operation......................................................50 TRISA.................................................................................15 Incrementing Edge (figure).........................................50 TRISA Register...................................................................14 Operation in Asynchronous Counter Mode.................51 TRISB.................................................................................15 Operation in Synchronized Counter Mode..................50 TRISB Register.............................................................14, 15 Operation in Timer Mode............................................50 TRISC.................................................................................15 Oscillator.....................................................................51 TRISC Register...................................................................14 Capacitor Selection.............................................51 TRISD.................................................................................15 Prescaler.....................................................................52 TRISD Register...................................................................14 Resetting of Timer1 Register Pair TRISE.................................................................................15 (TMR1H, TMR1L)...............................................52 TRISE Register...................................................................14 Resetting Timer1 Using a CCP Trigger Output...........51 IBF Bit.........................................................................40 TMR1H........................................................................51 IBOV Bit......................................................................40 TMR1L........................................................................51 OBF Bit.......................................................................40 Timer2.................................................................................53 PSPMODE Bit..........................................38, 39, 40, 42 Associated Registers..................................................54 TXREG Register.................................................................13 Output.........................................................................54 TXSTA................................................................................15 Postscaler...................................................................53 TXSTA Register..................................................................14 Prescaler.....................................................................53 BRGH Bit....................................................................61 Prescaler and Postscaler............................................54 CSRC Bit....................................................................61 Timing Diagrams TRMT Bit....................................................................61 A/D Conversion.........................................................135 TX9 Bit........................................................................61 Asynchronous Master Transmission...........................67 TX9D Bit.....................................................................61 Asynchronous Master Transmission TXEN Bit.....................................................................61 (Back to Back)....................................................67 Asynchronous Reception with Address Byte First..............................................71  2000-2013 Microchip Technology Inc. DS30569C-page 165

PIC16F870/871 U W Universal Synchronous Asynchronous Receiver Transmitter. Wake-up from SLEEP.................................................87, 100 See USART Interrupts....................................................................93 USART................................................................................61 MCLR Reset...............................................................93 Address Detect Enable (ADDEN Bit)..........................62 Timing Diagram........................................................101 Asynchronous Mode...................................................66 WDT Reset.................................................................93 Asynchronous Receive...............................................68 Watchdog Timer Asynchronous Receive (9-bit Mode)...........................70 Register Summary......................................................99 Asynchronous Receive with Address Detect. Watchdog Timer (WDT)................................................87, 99 See Asynchronous Receive (9-bit Mode). Enable (WDTEN Bit)...................................................99 Asynchronous Reception............................................69 Postscaler. See Postscaler, WDT. Asynchronous Transmitter..........................................66 Programming Considerations.....................................99 Baud Rate Generator (BRG).......................................63 RC Oscillator...............................................................99 Baud Rate Formula.............................................63 Time-out Period..........................................................99 Baud Rates, Asynchronous Mode WDT Reset, Normal Operation.............................91, 93 (BRGH = 0).................................................64 WDT Reset, SLEEP..............................................91, 93 Baud Rates, Asynchronous Mode Write Verify (BRGH = 1).................................................65 Data EEPROM and FLASH Program Memory...........31 High Baud Rate Select (BRGH Bit).....................61 WWW, On-Line Support.......................................................4 Sampling.............................................................63 Clock Source Select (CSRC Bit).................................61 Continuous Receive Enable (CREN Bit).....................62 Framing Error (FERR Bit)...........................................62 Overrun Error (OERR Bit)...........................................62 Receive Data, 9th bit (RX9D Bit)................................62 Receive Enable, 9-bit (RX9 Bit)..................................62 Serial Port Enable (SPEN Bit)...............................61, 62 Single Receive Enable (SREN Bit).............................62 Synchronous Master Mode.........................................72 Synchronous Master Reception..................................74 Synchronous Master Transmission.............................72 Synchronous Slave Mode...........................................76 Synchronous Slave Reception....................................77 Synchronous Slave Transmit......................................76 Transmit Data, 9th Bit (TX9D).....................................61 Transmit Enable (TXEN Bit)........................................61 Transmit Enable, Nine-bit (TX9 Bit)............................61 Transmit Shift Register Status (TRMT Bit)..................61 DS30569C-page 166  2000-2013 Microchip Technology Inc.

PIC16F870/871 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or field application engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2000-2013 Microchip Technology Inc. DS30569C-page 167

PIC16F870/871 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16F870/871 Literature Number: DS30569C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS30569C-page 168  2000-2013 Microchip Technology Inc.

PIC16F870/871 PIC16F870/871 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F870-I/SP 301 = Industrial temp., PDIP Range package, 20 MHz, normal VDD limits, QTP pattern #301. b) PIC16F871-I/PT = Industrial temp., TQFP package, 20 MHz, Extended VDD limits. Device PIC16F870, PIC16F870T; VDD range 4.0V to 5.5V c) PIC16F871-I/P = Industrial temp., PDIP PIC16F871, PIC16F871T ; VDD range 4.0V to 5.5V package, 20 MHz, normal VDD limits. PIC16LF870X, PIC16LF870T; VDD range 2.0V to 5.5V PIC16LF871X, PIC16LF871T; VDD range 2.0V to 5.5V d) PIC16LF870-I/SS = Industrial temp., SSOP package, DC - 20 MHz, extended VDD limits. F = Normal VDD limits LP = Extended VDD limits T = In Tape and Reel - SOIC, SSOP, TQFP and PLCC packages only. Temperature Range blank(3) = 0°C to +70°C (Commercial) I = -40°C to +85°C (Industrial) Package PQ = MQFP (Metric PQFP) PT = TQFP (Thin Quad Flatpack) SO = SOIC SP = Skinny Plastic Dip SS = SSOP P = PDIP L = PLCC Pattern QTP, Code or Special Requirements (blank otherwise) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Worldwide Site (www.microchip.com)  2000-2013 Microchip Technology Inc. DS30569C-page 169

PIC16F870/871 NOTES:  2000-2013 Microchip Technology Inc. DS30569C-page 170

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2000-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769379 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2000-2013 Microchip Technology Inc. DS30569C-page 171

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://www.microchip.com/ support Fax: 852-2401-3431 India - Pune France - Paris Web Address: Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 www.microchip.com Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 Atlanta Fax: 61-2-9868-6755 Japan - Osaka Germany - Munich Duluth, GA China - Beijing Tel: 81-6-6152-7160 Tel: 49-89-627-144-0 Tel: 86-10-8569-7000 Fax: 49-89-627-144-44 Tel: 678-957-9614 Fax: 81-6-6152-9310 Fax: 678-957-1455 Fax: 86-10-8528-2104 Japan - Tokyo Italy - Milan China - Chengdu Tel: 39-0331-742611 Boston Tel: 81-3-6880- 3770 Tel: 86-28-8665-5511 Fax: 39-0331-466781 Westborough, MA Fax: 81-3-6880-3771 Tel: 774-760-0087 Fax: 86-28-8665-7889 Korea - Daegu Netherlands - Drunen Fax: 774-760-0088 China - Chongqing Tel: 82-53-744-4301 Tel: 31-416-690399 Chicago Tel: 86-23-8980-9588 Fax: 82-53-744-4302 Fax: 31-416-690340 Itasca, IL Fax: 86-23-8980-9500 Korea - Seoul Spain - Madrid Tel: 630-285-0071 China - Hangzhou Tel: 82-2-554-7200 Tel: 34-91-708-08-90 Fax: 630-285-0075 Tel: 86-571-2819-3187 Fax: 82-2-558-5932 or Fax: 34-91-708-08-91 Cleveland Fax: 86-571-2819-3189 82-2-558-5934 UK - Wokingham Independence, OH China - Hong Kong SAR Malaysia - Kuala Lumpur Tel: 44-118-921-5869 Tel: 216-447-0464 Tel: 852-2943-5100 Tel: 60-3-6201-9857 Fax: 44-118-921-5820 Fax: 216-447-0643 Fax: 852-2401-3431 Fax: 60-3-6201-9859 Dallas China - Nanjing Malaysia - Penang Addison, TX Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Tel: 972-818-7423 Fax: 86-25-8473-2470 Fax: 60-4-227-4068 Fax: 972-818-2924 China - Qingdao Philippines - Manila Detroit Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Farmington Hills, MI Fax: 86-532-8502-7205 Fax: 63-2-634-9069 Tel: 248-538-2250 Fax: 248-538-2260 China - Shanghai Singapore Tel: 86-21-5407-5533 Tel: 65-6334-8870 Indianapolis Fax: 86-21-5407-5066 Fax: 65-6334-8850 Noblesville, IN Tel: 317-773-8323 China - Shenyang Taiwan - Hsin Chu Fax: 317-773-5453 Tel: 86-24-2334-2829 Tel: 886-3-5778-366 Fax: 86-24-2334-2393 Fax: 886-3-5770-955 Los Angeles Mission Viejo, CA China - Shenzhen Taiwan - Kaohsiung Tel: 949-462-9523 Tel: 86-755-8864-2200 Tel: 886-7-213-7828 Fax: 949-462-9608 Fax: 86-755-8203-1760 Fax: 886-7-330-9305 Santa Clara China - Wuhan Taiwan - Taipei Santa Clara, CA Tel: 86-27-5980-5300 Tel: 886-2-2508-8600 Tel: 408-961-6444 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 Fax: 408-961-6445 China - Xian Thailand - Bangkok Toronto Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Mississauga, Ontario, Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Canada China - Xiamen Tel: 905-673-0699 Tel: 86-592-2388138 Fax: 905-673-6509 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 11/29/12 Fax: 86-756-3210049 DS30569C-page 172  2000-2013 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16F871-E/P PIC16F871-E/L PIC16F871-I/PT PIC16F870-E/SS PIC16F870-E/SP PIC16F870-E/SO PIC16F871T-E/PT PIC16F871T-I/L PIC16F870T-E/SS PIC16F870T-E/SO PIC16F871-I/P PIC16F871-I/L PIC16F871-E/PT PIC16LF871-I/PT PIC16LF871T-I/PT PIC16LF870T-I/SS PIC16F870-I/SO PIC16F870-I/SP PIC16F870-I/SS PIC16F871T-E/L PIC16LF870T-I/SO PIC16F871T-I/PT PIC16F870T-I/SO PIC16F870T-I/SS PIC16LF871T-I/L PIC16LF871-I/P PIC16LF871-I/L PIC16LF870-I/SS PIC16LF870-I/SP PIC16LF870-I/SO