PIC16(L)F722A/723A 28-Pin Flash Microcontrollers with XLP Technology Devices Included In This Data Sheet: Extreme Low-Power Management PIC16LF722A/723A with XLP: PIC16F722A/723A Devices: • Sleep Mode: 20nA • PIC16F722A • Watchdog Timer: 500nA • PIC16F723A • Timer1 Oscillator: 600 nA @ 32 kHz PIC16LF722A/723A Devices: Analog Features: • PIC16LF722A • A/D Converter: • PIC16LF723A - 8-bit resolution, 11 channels - Conversion available during Sleep High-Performance RISC CPU: - Selectable 1.024/2.048/4.096V voltage reference • Only 35 Instructions to Learn: • On-chip 3.2V Regulator (PIC16F722A/723A - All single-cycle instructions except branches devices only) • Operating Speed: - DC – 20MHz oscillator/clock input Peripheral Highlights: - DC – 200ns instruction cycle • Up to 4K x 14 Words of Flash Program Memory • 25 I/O Pins (1 Input-only Pin): • Up to 192 Bytes of Data Memory (RAM) - High-current source/sink for direct LED drive • Interrupt Capability - Interrupt-on-pin change • 8-Level Deep Hardware Stack - Individually programmable weak pull ups • Direct, Indirect and Relative Addressing modes • Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler • Processor Read Access to Program Memory • Enhanced Timer1: • Pinout Compatible to other 28-pin PIC16CXXX - Dedicated low-power 32 kHz oscillator and PIC16FXXX Microcontrollers - 16-bit timer/counter with prescaler - External Gate Input mode with toggle and Special Microcontroller Features: single shot modes - Interrupt-on-gate completion • Precision Internal Oscillator: • Timer2: 8-Bit Timer/Counter with 8-Bit Period - 16 MHz or 500 kHz operation Register, Prescaler and Postscaler - Factory-calibrated to ±1%, typical • Two Capture, Compare, PWM (CCP) modules: - Software tunable - 16-bit Capture, max. resolution 12.5ns - Software selectable ÷1, ÷2, ÷4 or ÷8 divider - 16-bit Compare, max. resolution 200ns • 1.8V-5.5V Operation – PIC16F722A/723A - 10-bit PWM, max. frequency 20kHz • 1.8V-3.6V Operation – PIC16LF722A/723A • Addressable Universal Synchronous • Power-on Reset (POR), Power-up Timer (PWRT) Asynchronous Receiver Transmitter (AUSART) and Oscillator Start-up Timer (OST) • Synchronous Serial Port (SSP): • Brown-out Reset (BOR): - Selectable between two trip points - SPI (Master/Slave) - Disable in Sleep option - I2C (Slave) with Address Mask • Programmable Code Protection • mTouch® Sensing Oscillator module: • In-Circuit Serial ProgrammingTM (ICSPTM) via Two - Up to eight input channels Pins • Multiplexed Master Clear with Pull-up/Input Pin • Industrial and Extended Temperature Range • Power-Saving Sleep mode  2010-2016 Microchip Technology Inc. DS40001417C-page 1

PIC16(L)F722A/723A PIC16(L)F72X Family Types h s Device Data Sheet Index Program MemoryFlash (words) Data SRAM(bytes) gh-Endurance FlaMemory (bytes) (2)I/O’s 8-bit ADC (ch) CapSense (ch) Timers(8/16-bit) AUSART 2SSP (IC/SPI) CCP (1)Debug XLP Hi PIC16(L)F707 (1) 8192 363 0 36 14 32 4/2 1 1 2 I Y PIC16(L)F720 (2) 2048 128 128 18 12 — 2/1 1 1 1 I Y PIC16(L)F721 (2) 4096 256 128 18 12 — 2/1 1 1 1 I Y PIC16(L)F722 (4) 2048 128 0 25 11 8 2/1 1 1 2 I Y PIC16(L)F722A (3) 2048 128 0 25 11 8 2/1 1 1 2 I Y PIC16(L)F723 (4) 4096 192 0 25 11 8 2/1 1 1 2 I Y PIC16(L)F723A (3) 4096 192 0 25 11 8 2/1 1 1 2 I Y PIC16(L)F724 (4) 4096 192 0 36 14 16 2/1 1 1 2 I Y PIC16(L)F726 (4) 8192 368 0 25 11 8 2/1 1 1 2 I Y PIC16(L)F727 (4) 8192 368 0 36 14 16 2/1 1 1 2 I Y Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header. 2: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS41418 PIC16(L)F707 Data Sheet, 40/44-Pin Flash, 8-bit Microcontrollers 2: DS41430 PIC16(L)F720/721 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers 3: DS41417 PIC16(L)F722A/723A Data Sheet, 28-Pin Flash, 8-bit Microcontrollers 4: DS41341 PIC16(L)F72X Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers DS40001417C-page 2  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A Pin Diagrams – 28-PIN SPDIP/SOIC/SSOP/QFN/UQFN (PIC16(L)F722A/723A) SPDIP, SOIC, SSOP VPP/MCLR/RE3 1 28 RB7/ICSPDAT VCAP(3)/SS(2)/AN0/RA0 2 27 RB6/ICSPCLK AN1/RA1 3 26 RB5/AN13/CPS5/T1G AN2/RA2 4 25 RB4/AN11/CPS4 VREF/AN3/RA3 5 A 24 RB3/AN9/CPS3/CCP2(1) A 3 T0CKI/CPS6/RA4 6 23 72 23 RB2/AN8/CPS2 VCAP(3)/SS(2)/CPS7/AN4/RA5 7 A/7 2A/ 22 RB1/AN10/CPS1 VSS 8 22 72 21 RB0/AN12/CPS0/INT 7 F CLKIN/OSC1/RA7 9 F L 20 VDD 6 6 VCAP(3)/CLKOUT/OSC2/RA6 10 C1 C1 19 VSS T1CKI/T1OSO/RC0 11 PI PI 18 RC7/RX/DT CCP2(1)/T1OSI/RC1 12 17 RC6/TX/CK CCP1/RC2 13 16 RC5/SDO SCL/SCK/RC3 14 15 RC4/SDI/SDA QFN, UQFN (3) CAP T1G V 5/ 4 N1(2)N0/SS/ CLR/VPP SPDAT SPCLK N13/CPS N11/CPS AA M C C A A 1/0/ 3/ 7/I 6/I 5/ 4/ AA E B B B B RR R R R R R 8 7 6 5 4 3 2 2 2 2 2 2 2 2 AN2/RA2 1 21 RB3/AN9/CPS3/CCP2(1) VREF/AN3/RA3 2 20 RB2/AN8/CPS2 T0CKI/CPS6/RA4 3 PIC16F722A/723A 19 RB1/AN10/CPS1 VCAP(3)/SS(2)/CPS7/AN4/RA5 4 PIC16LF722A/723A 18 RB0/AN12/CPS0/INT VSS 5 17 VDD CLKIN/OSC1/RA7 6 16 VSS VCAP(3)/CLKOUT/OSC2/RA6 7 15 RC7/RX/DT 0 1 2 3 4 8 9 1 1 1 1 1 0 1 2 3 4 5 6 C C C C C C C R R R R R R R KI/T1OSO/(1)2/T1OSI/ CCP1/ SCL/SCK/ SDA/SDI/ SDO/ CK/TX/ C P 1 C T C Note 1: CCP2 pin location may be selected as RB3 or RC1. 2: SS pin location may be selected as RA5 or RA0. 3: PIC16F722A/723A devices only.  2010-2016 Microchip Technology Inc. DS40001417C-page 3

PIC16(L)F722A/723A TABLE 1: 28-PIN SPDIP/SOIC/SSOP/QFN/UQFN SUMMARY (PIC16(L)F722A/723A) 28-Pin 28-Pin SPDIP, I/O QFN, A/D Cap Sensor Timers CCP AUSART SSP Interrupt Pull Up Basic SOIC, UQFN SSOP RA0 2 27 AN0 — — — — SS(3) — — VCAP(4) RA1 3 28 AN1 — — — — — — — — RA2 4 1 AN2 — — — — — — — — RA3 5 2 AN3/VREF — — — — — — — — RA4 6 3 — CPS6 T0CKI — — — — — — RA5 7 4 AN4 CPS7 — — — SS(3) — — VCAP(4) RA6 10 7 — — — — — — — — OSC2/CLKOUT/VCAP(4) RA7 9 6 — — — — — — — — OSC1/CLKIN RB0 21 18 AN12 CPS0 — — — — IOC/INT Y — RB1 22 19 AN10 CPS1 — — — — IOC Y — RB2 23 20 AN8 CPS2 — — — — IOC Y — RB3 24 21 AN9 CPS3 — CCP2(2) — — IOC Y — RB4 25 22 AN11 CPS4 — — — — IOC Y — RB5 26 23 AN13 CPS5 T1G — — — IOC Y — RB6 27 24 — — — — — — IOC Y ICSPCLK/ICDCLK RB7 28 25 — — — — — — IOC Y ICSPDAT/ICDDAT RC0 11 8 — — T1OSO/T1CKI — — — — — — RC1 12 9 — — T1OSI CCP2(2) — — — — — RC2 13 10 — — — CCP1 — — — — — RC3 14 11 — — — — — SCK/SCL — — — RC4 15 12 — — — — SDI/SDA — — — RC5 16 13 — — — — — SDO — — — RC6 17 14 — — — — TX/CK — — — — RC7 18 15 — — — — RX/DT — — — — RE3 1 26 — — — — — — — Y(1) MCLR/VPP — 20 17 — — — — — — — — VDD — 8,19 5,16 — — — — — — — — VSS Note 1: Pull up enabled only with external MCLR configuration. 2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register. 3: RA5 is the default pin location for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register. 4: PIC16F722A/723A devices only. Note: The PIC16F722A/723A devices have an internal low dropout voltage regulator. An external capacitor must be connected to one of the available VCAP pins to stabilize the regulator. For more information, see Section5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF722A/723A devices do not have the voltage regulator and therefore no external capacitor is required. DS40001417C-page 4  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A Table of Contents 1.0 Device Overview .........................................................................................................................................................................7 2.0 Memory Organization................................................................................................................................................................ 11 3.0 Resets....................................................................................................................................................................................... 23 4.0 Interrupts................................................................................................................................................................................... 33 5.0 Low Dropout (LDO) Voltage Regulator..................................................................................................................................... 41 6.0 I/O Ports.................................................................................................................................................................................... 42 7.0 Oscillator Module....................................................................................................................................................................... 71 8.0 Device Configuration..................................................................................................................................................................77 9.0 Analog-to-Digital Converter (ADC) Module............................................................................................................................... 80 10.0 Fixed Voltage Reference........................................................................................................................................................... 90 11.0 Timer0 Module.......................................................................................................................................................................... 91 12.0 Timer1 Module with Gate Control............................................................................................................................................ 103 13.0 Timer2 Module........................................................................................................................................................................ 115 14.0 Capacitive Sensing Module..................................................................................................................................................... 108 15.0 Capture/Compare/PWM (CCP) Module.................................................................................................................................. 114 16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART).......................................................... 124 17.0 SSP Module Overview............................................................................................................................................................ 145 18.0 Program Memory Read........................................................................................................................................................... 167 19.0 Power-Down Mode (Sleep)..................................................................................................................................................... 170 20.0 In-Circuit Serial Programming™ (ICSP™).............................................................................................................................. 172 21.0 Instruction Set Summary......................................................................................................................................................... 173 22.0 Development Support.............................................................................................................................................................. 182 23.0 Electrical Specifications........................................................................................................................................................... 186 24.0 DC and AC Characteristics Graphs and Charts...................................................................................................................... 214 25.0 Packaging Information............................................................................................................................................................. 249 Appendix A: Data Sheet Revision History......................................................................................................................................... 261 Appendix B: Migrating From Other PIC® Devices............................................................................................................................. 261 The Microchip Website..................................................................................................................................................................... 262 Customer Change Notification Service............................................................................................................................................. 262 Customer Support .............................................................................................................................................................................262 Product Identification System............................................................................................................................................................263  2010-2016 Microchip Technology Inc. DS40001417C-page 5

PIC16(L)F722A/723A TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. DS40001417C-page 6  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 1.0 DEVICE OVERVIEW The PIC16(L)F722A/723A devices are covered by this data sheet. They are available in 28-pin packages. Figure1-1 shows a block diagram of the PIC16(L)F722A/723A devices. Table1-1 shows the pinout descriptions.  2010-2016 Microchip Technology Inc. DS40001417C-page 7

PIC16(L)F722A/723A FIGURE 1-1: PIC16(L)F722A/723A BLOCK DIAGRAM CCCooonnnfffiiiggguuurrraaatttiiiooonnn PORTA 111333 DDDaaatttaaa BBBuuusss 888 RA0 PPPrrrooogggrrraaammm CCCooouuunnnttteeerrr RA1 RA2 Flash RA3 Program RA4 Memory 888 LLLeeevvveeelll SSStttaaaccckkk RA5 RAM (((111333---bbbiiittt))) RA6 RA7 PPPrrroooBBBggguuurrrsssaaammm 111444 RRRAAAMMM AAAddddddrrr 9 PORTB RB0 RB1 AAAddddddrrr MMMUUUXXX IIInnnssstttrrruuuccctttiiiooonnn Rrreeeggg RB2 DDDiiirrreeecccttt AAAddddddrrr 777 IIInnndddiiirrreeecccttt RB3 888 AAAddddddrrr RB4 RB5 FFFSSSRRR Rrreeeggg RB6 RB7 SSSTTTAAATTTUUUSSS Rrreeeggg PORTC 888 RC0 RRCC11 RC2 PPPooowwweeerrr---uuuppp 333 MMMUUUXXX RC3 TTTiiimmmeeerrr RC4 RC5 IIInnnssstttrrruuuccctttiiiooonnn OOOsssccciiillllllaaatttooorrr DDDeCCCeecccoooooodnnnddetttrrree oooa lll&&nd SSStttaaarrrttt---uuuppp TTTiiimmmeeerrr AAALLLUUU RRCC67 PPPooowwweeerrr---ooonnn OSC1/CLKIN RRReeessseeettt 888 PORTE RE3 TTTiiimmmiiinnnggg WWWaaatttccchhhdddoooggg OSC2/CLKOUT GGGeeennneeerrraaatttiiiooonnn TTTiiimmmeeerrr WWW Rrreeeggg BBBrrrooowwwnnn---ooouuuttt RRReeessseeettt LDO(1) IIInnnttteeerrrnnnaaalll Regulator OOOsssccciiillllllaaatttooorrr BBBllloooccckkk CCP1 CCP1 MMMCCCLLLRRR VVVDDDDDD VVVSSSSSS CCP2 CCP2 T1OSI Timer1 32kHz T1OSO Oscillator SSSDDDIII/// SSSCCCKKK/// TX/CKRX/DT SSSDDDOOOSSSDDDAAA SSSCCCLLL SSSSSS TTT000CCCKKKIII T1G TTT111CCCKKKIII TTTiiimmmeeerrr000 TTTiiimmmeeerrr111 TTTiiimmmeeerrr222 AAUUSSAARRTT SSSyyynnnccchhhrrrooonnnooouuusss VREF SSSeeerrriiiaaalll PPPooorrrttt Analog-To-Digital Converter Capacitive Sensing Module AN0 AN1 AN2 AN3 AN4 AN8 AN9 AN10AN11AN12AN13 CPS0CPS1 CPS2CPS3CPS4CPS5 CPS6 CPS7 Note 1: PIC16F722A/723A only. DS40001417C-page 8  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 1-1: PIC16F722A/723A PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/SS/VCAP RA0 TTL CMOS General purpose I/O. AN0 AN — A/D Channel 0 input. SS ST — Slave Select input. VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F722A/723A only). RA1/AN1 RA1 TTL CMOS General purpose I/O. AN1 AN — A/D Channel 1 input. RA2/AN2 RA2 TTL CMOS General purpose I/O. AN2 AN — A/D Channel 2 input. RA3/AN3/VREF RA3 TTL CMOS General purpose I/O. AN3 AN — A/D Channel 3 input. VREF AN — A/D Voltage Reference input. RA4/CPS6/T0CKI RA4 TTL CMOS General purpose I/O. CPS6 AN — Capacitive sensing input 6. T0CKI ST — Timer0 clock input. RA5/AN4/CPS7/SS/VCAP RA5 TTL CMOS General purpose I/O. AN4 AN — A/D Channel 4 input. CPS7 AN — Capacitive sensing input 7. SS ST — Slave Select input. VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F722A/723A only). RA6/OSC2/CLKOUT/VCAP RA6 TTL CMOS General purpose I/O. OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F722A/723A only). RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O. OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes). CLKIN CMOS — External clock input (EC mode). CLKIN ST — RC oscillator connection (RC mode). RB0/AN12/CPS0/INT RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individu- ally enabled pull up. AN12 AN — A/D Channel 12 input. CPS0 AN — Capacitive sensing input 0. INT ST — External interrupt. RB1/AN10/CPS1 RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individu- ally enabled pull up. AN10 AN — A/D Channel 10 input. CPS1 AN — Capacitive sensing input 1. RB2/AN8/CPS2 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individu- ally enabled pull up. AN8 AN — A/D Channel 8 input. CPS2 AN — Capacitive sensing input 2. RB3/AN9/CPS3/CCP2 RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individu- ally enabled pull up. AN9 AN — A/D Channel 9 input. CPS3 AN — Capacitive sensing input 3. CCP2 ST CMOS Capture/Compare/PWM2. RB4/AN11/CPS4 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individu- ally enabled pull up. AN11 AN — A/D Channel 11 input. CPS4 AN — Capacitive sensing input 4. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels  2010-2016 Microchip Technology Inc. DS40001417C-page 9

PIC16(L)F722A/723A TABLE 1-1: PIC16F722A/723A PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RB5/AN13/CPS5/T1G RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individu- ally enabled pull up. AN13 AN — A/D Channel 13 input. CPS5 AN — Capacitive sensing input 5. T1G ST — Timer1 gate input. RB6/ICSPCLK/ICDCLK RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individu- ally enabled pull up. ICSPCLK ST — Serial Programming Clock. ICDCLK ST — In-Circuit Debug Clock. RB7/ICSPDAT/ICDDAT RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individu- ally enabled pull up. ICSPDAT ST CMOS ICSP™ Data I/O. ICDDAT ST — In-Circuit Data I/O. RC0/T1OSO/T1CKI RC0 ST CMOS General purpose I/O. T1OSO XTAL XTAL Timer1 oscillator connection. T1CKI ST — Timer1 clock input. RC1/T1OSI/CCP2 RC1 ST CMOS General purpose I/O. T1OSI XTAL XTAL Timer1 oscillator connection. CCP2 ST CMOS Capture/Compare/PWM2. RC2/CCP1 RC2 ST CMOS General purpose I/O. CCP1 ST CMOS Capture/Compare/PWM1. RC3/SCK/SCL RC3 ST CMOS General purpose I/O. SCK ST CMOS SPI clock. SCL I2C OD I2C clock. RC4/SDI/SDA RC4 ST CMOS General purpose I/O. SDI ST — SPI data input. SDA I2C OD I2C data input/output. RC5/SDO RC5 ST CMOS General purpose I/O. SDO — CMOS SPI data output. RC6/TX/CK RC6 ST CMOS General purpose I/O. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. RC7/RX/DT RC7 ST CMOS General purpose I/O. RX ST — USART asynchronous input. DT ST CMOS USART synchronous data. RE3/MCLR/VPP RE3 TTL — General purpose input. MCLR ST — Master Clear with internal pull up. VPP HV — Programming voltage. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note: The PIC16F722A/723A devices have an internal low dropout voltage regulator. An external capacitor must be connected to one of the available VCAP pins to stabilize the regulator. For more information, see Section5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF722A/723A devices do not have the voltage regulator and therefore no external capacitor is required. DS40001417C-page 10  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 2.0 MEMORY ORGANIZATION FIGURE 2-2: PROGRAM MEMORY MAP AND STACK FOR THE 2.1 Program Memory Organization PIC16(L)F723A The PIC16(L)F722A/723A has a 13-bit program PC<12:0> counter capable of addressing a 2K x14 program memory space for the PIC16(L)F722A (0000h-07FFh) CALL, RETURN 13 and a 4K x14 program memory space for the RETFIE, RETLW PIC16(L)F723A (0000h-0FFFh). Accessing a location above the memory boundaries for the PIC16(L)F722A Stack Level 1 will cause a wrap-around within the first 2Kx14 Stack Level 2 program memory space. Accessing a location above the memory boundaries for the PIC16(L)F723A will Stack Level 8 cause a wrap-around within the first 4K x 14 program memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h. RESET Vector 0000h FIGURE 2-1: PROGRAM MEMORY MAP Interrupt Vector 0004H AND STACK FOR THE 0005h PIC16(L)F722A Page 0 On-chip 07FFh Program PC<12:0> 0800h Memory Page 1 CALL, RETURN 13 0FFFh RETFIE, RETLW 1000h Wraps to Page 0 Stack Level 1 17FFh Stack Level 2 1800h Wraps to Page 1 Stack Level 8 1FFFh RESET Vector 0000h Interrupt Vector 0004H On-chip 0005h Program Page 0 Memory 07FFh 0800h Wraps to Page 0 0FFFh 1000h Wraps to Page 0 17FFh 1800h Wraps to Page 0 1FFFh  2010-2016 Microchip Technology Inc. DS40001417C-page 11

PIC16(L)F722A/723A 2.2 Data Memory Organization 2.2.1 GENERAL PURPOSE REGISTER FILE The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPRs) The register file is organized as 128x8 bits in the and the Special Function Registers (SFRs). Bits RP0 PIC16(L)F722A and 192x8 bits in the PIC16(L)F723A. and RP1 are bank select bits. Each register is accessed either directly or indirectly through the File Select Register (FSR), (Refer to RP1 RP0 Section2.5 “Indirect Addressing, INDF and FSR 0 0  Bank 0 is selected Registers”). 0 1  Bank 1 is selected 2.2.2 SPECIAL FUNCTION REGISTERS 1 0  Bank 2 is selected The Special Function Registers are registers used by 1 1  Bank 3 is selected the CPU and peripheral functions for controlling the Each bank extends up to 7Fh (128 bytes). The lower desired operation of the device (refer to Table2-1). locations of each bank are reserved for the Special These registers are static RAM. Function Registers. Above the Special Function The Special Function Registers can be classified into Registers are the General Purpose Registers, two sets: core and peripheral. The Special Function implemented as static RAM. All implemented banks Registers associated with the “core” are described in contain Special Function Registers. Some frequently this section. Those related to the operation of the used Special Function Registers from one bank are peripheral features are described in the section of that mirrored in another bank for code reduction and peripheral feature. quicker access. DS40001417C-page 12  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 2-3: PIC16(L)F722A SPECIAL FUNCTION REGISTERS File Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION 81h TMR0 101h OPTION 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h ANSELA 185h PORTB 06h TRISB 86h 106h ANSELB 186h PORTC 07h TRISC 87h 107h 187h 08h 88h CPSCON0 108h 188h PORTE 09h TRISE 89h CPSCON1 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch PIR2 0Dh PIE2 8Dh PMADRL 10Dh Reserved 18Dh TMR1L 0Eh PCON 8Eh PMDATH 10Eh Reserved 18Eh TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh Reserved 18Fh T1CON 10h OSCCON 90h 110h 190h TMR2 11h OSCTUNE 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD/SSPMSK93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPR1L 15h WPUB 95h 115h 195h CCPR1H 16h IOCB 96h 116h 196h CCP1CON 17h 97h 117h 197h RCSTA 18h TXSTA 98h 118h 198h TXREG 19h SPBRG 99h 119h 199h RCREG 1Ah 9Ah 11Ah 19Ah CCPR2L 1Bh 9Bh 11Bh 19Bh CCPR2H 1Ch APFCON 9Ch 11Ch 19Ch CCP2CON 1Dh FVRCON 9Dh 11Dh 19Dh ADRES 1Eh 9Eh 11Eh 19Eh ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh 20h A0h 120h 1A0h General Purpose Register 32 Bytes General BFh Purpose Register C0h 96 Bytes EFh 16Fh 1EFh F0h 170h 1F0h Accesses Accesses Accesses 70h-7Fh 70h-7Fh 70h-7Fh 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Legend: = Unimplemented data memory locations, read as ‘0’. * = Not a physical register.  2010-2016 Microchip Technology Inc. DS40001417C-page 13

PIC16(L)F722A/723A FIGURE 2-4: PIC16(L)F723A SPECIAL FUNCTION REGISTERS File Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION 81h TMR0 101h OPTION 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h ANSELA 185h PORTB 06h TRISB 86h 106h ANSELB 186h PORTC 07h TRISC 87h 107h 187h 08h 88h CPSCON0 108h 188h PORTE 09h TRISE 89h CPSCON1 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch PIR2 0Dh PIE2 8Dh PMADRL 10Dh Reserved 18Dh TMR1L 0Eh PCON 8Eh PMDATH 10Eh Reserved 18Eh TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh Reserved 18Fh T1CON 10h OSCCON 90h 110h 190h TMR2 11h OSCTUNE 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD/SSPMSK93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPR1L 15h WPUB 95h 115h 195h CCPR1H 16h IOCB 96h 116h 196h CCP1CON 17h 97h 117h 197h RCSTA 18h TXSTA 98h 118h 198h TXREG 19h SPBRG 99h 119h 199h RCREG 1Ah 9Ah 11Ah 19Ah CCPR2L 1Bh 9Bh 11Bh 19Bh CCPR2H 1Ch APFCON 9Ch 11Ch 19Ch CCP2CON 1Dh FVRCON 9Dh 11Dh 19Dh ADRES 1Eh 9Eh 11Eh 19Eh ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh 20h A0h General Purpose 120h 1A0h Register General 16 Bytes 12Fh Purpose General Register 130h Purpose 80 Bytes Register 96 Bytes EFh 16Fh 1EFh Accesses F0h Accesses 170h Accesses 1F0h 70h-7Fh 70h-7Fh 70h-7Fh 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Legend: = Unimplemented data memory locations, read as ‘0’. * = Not a physical register. DS40001417C-page 14  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A - TABLE 2-1: PIC16(L)F722A/723A SPECIAL FUNCTION REGISTER SUMMARY Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOR Bank 0 00h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,30 01h TMR0 Timer0 Module Register xxxx xxxx 91,30 02h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 21,30 03h(2) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18,30 04h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 22,30 05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx 43,30 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 52,30 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 62,30 09h PORTE — — — — RE3 — — — ---- xxxx 69,30 0Ah(1, 2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 21,30 0Bh(2) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 36,30 0Ch PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 39,30 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 40,30 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 99,30 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 99,30 10h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 0000 00-0 103,30 11h TMR2 Timer2 Module Register 0000 0000 106,30 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 107,30 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 147,30 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 164,30 15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 116,30 16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 116,30 17h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 115,30 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 134,30 19h TXREG USART Transmit Data Register 0000 0000 133,30 1Ah RCREG USART Receive Data Register 0000 0000 131,30 1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx 116,30 1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx 116,30 1Dh CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 115,30 1Eh ADRES A/D Result Register xxxx xxxx 86,30 1Fh ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 85,30 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Accessible only when SSPM<3:0> = 1001. 4: Accessible only when SSPM<3:0>  1001. 5: This bit is always ‘1’ as RE3 is input-only.  2010-2016 Microchip Technology Inc. DS40001417C-page 15

PIC16(L)F722A/723A TABLE 2-1: PIC16(L)F722A/723A SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOR Bank 1 80h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,30 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19,30 82h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 21,30 83h(2) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18,30 84h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 22,30 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 43,30 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 52,30 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 62,30 89h TRISE — — — — TRISE3(5) — — — ---- 1111 69,30 8Ah(1, 2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 21,30 8Bh(2) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 36,30 8Ch PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 37,31 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 38,31 8Eh PCON — — — — — — POR BOR ---- --qq 20,31 8Fh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO T1GVAL T1GSS1 T1GSS0 0000 0x00 104,31 DONE 90h OSCCON — — IRCF1 IRCF0 ICSL ICSS — — --10 qq-- 73,31 91h OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 74,31 92h PR2 Timer2 Period Register 1111 1111 106,31 93h SSPADD(4) Synchronous Serial Port (I2C mode) Address Register 0000 0000 155,31 93h SSPMSK(3) Synchronous Serial Port (I2C mode) Address Mask Register 1111 1111 166,31 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 153,31 95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 52,31 96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 53,31 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 133,31 99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 135,31 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch APFCON — — — — — — SSSEL CCP2SEL ---- --00 42,31 9Dh FVRCON FVRRDY FVREN — — — — ADFVR1 ADFVR0 q0-- --00 90,31 9Eh — Unimplemented — — 9Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 0000 --00 86,31 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Accessible only when SSPM<3:0> = 1001. 4: Accessible only when SSPM<3:0>  1001. 5: This bit is always ‘1’ as RE3 is input-only. DS40001417C-page 16  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 2-1: PIC16(L)F722A/723A SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOR Bank 2 100h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,30 101h TMR0 Timer0 Module Register xxxx xxxx 91,30 102h(2) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 21,30 103h(2) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18,30 104h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 22,30 105h — Unimplemented — — 106h — Unimplemented — — 107h — Unimplemented — — 108h CPSCON0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 112,31 109h CPSCON1 — — — — — CPSCH2 CPSCH1 CPSCH0 ---- 0000 113,31 10Ah(1, 2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 21,30 10Bh(2) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 36,30 10Ch PMDATL Program Memory Read Data Register Low Byte xxxx xxxx 167,31 10Dh PMADRL Program Memory Read Address Register Low Byte xxxx xxxx 167,31 10Eh PMDATH — — Program Memory Read Data Register High Byte --xx xxxx 167,31 10Fh PMADRH — — — Program Memory Read Address Register High Byte ---x xxxx 167,31 Bank 3 180h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,30 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19,30 182h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 21,30 183h(2) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18,30 184h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 22,30 185h ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 44,31 186h ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 53,31 187h — Unimplemented — — 18Ah(1, 2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 21,30 18Bh(2) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 36,30 18Ch PMCON1 Reserved — — — — — — RD 1--- ---0 168,31 18Dh — Unimplemented — — 18Eh — Unimplemented — — 18Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Accessible only when SSPM<3:0> = 1001. 4: Accessible only when SSPM<3:0>  1001. 5: This bit is always ‘1’ as RE3 is input-only.  2010-2016 Microchip Technology Inc. DS40001417C-page 17

PIC16(L)F722A/723A 2.2.2.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register2-1, contains: as ‘000u u1uu’ (where u = unchanged). • the arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, • the Reset status SWAPF and MOVWF instructions are used to alter the • the bank select bits for data memory (SRAM) STATUS register, because these instructions do not The STATUS register can be the destination for any affect any Status bits. For other instructions not instruction, like any other register. If the STATUS affecting any Status bits (Refer to Section21.0 register is the destination for an instruction that affects “Instruction Set Summary”). the Z, DC or C bits, then the write to these three bits is Note1: The C and DC bits operate as Borrow disabled. These bits are set or cleared according to the and Digit Borrow out bits, respectively, in device logic. Furthermore, the TO and PD bits are not subtraction. writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 2-1: STATUS: STATUS REGISTER R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS40001417C-page 18  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 2.2.2.2 OPTION register Note: To achieve a 1:1 prescaler assignment for The OPTION register, shown in Register2-2, is a Timer0, assign the prescaler to the WDT readable and writable register, which contains various by setting PSA bit of the OPTION register control bits to configure: to ‘1’. Refer to Section12.3 “Timer1 • Timer0/WDT prescaler Prescaler”. • External RB0/INT interrupt • Timer0 • Weak pull ups on PORTB REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull ups are disabled 0 = PORTB pull ups are enabled by individual bits in the WPUB register bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128  2010-2016 Microchip Technology Inc. DS40001417C-page 19

PIC16(L)F722A/723A 2.2.2.3 PCON Register The Power Control (PCON) register contains flag bits (refer to Table3-2) to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register2-3. REGISTER 2-3: PCON: POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-q R/W-q — — — — — — POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown q = Value depends on condition bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) Note 1: Set BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR. DS40001417C-page 20  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 2.3 PCL and PCLATH Note1: There are no Status bits to indicate stack The Program Counter (PC) is 13 bits wide. The low overflow or stack underflow conditions. byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not 2: There are no instructions/mnemonics directly readable or writable and comes from called PUSH or POP. These are actions PCLATH. On any Reset, the PC is cleared. Figure2-5 that occur from the execution of the shows the two situations for the loading of the PC. The CALL, RETURN, RETLW and RETFIE upper example in Figure2-5 shows how the PC is instructions or the vectoring to an loaded on a write to PCL (PCLATH<4:0>  PCH). interrupt address. The lower example in Figure2-5 shows how the PC is loaded during a CALL or GOTO instruction 2.4 Program Memory Paging (PCLATH<4:3>  PCH). All devices are capable of addressing a continuous 8K FIGURE 2-5: LOADING OF PC IN word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow DIFFERENT SITUATIONS branching within any 2K program memory page. When PCH PCL doing a CALL or GOTO instruction, the upper 2 bits of Instruction with the address are provided by PCLATH<4:3>. When 12 8 7 0 PCL as PC Destination doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the PCLATH<4:0> 8 5 ALU Result desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is POPed off the stack. Therefore, PCLATH manipulation of the PCLATH<4:3> bits is not required PCH PCL for the RETURN instructions (which POPs the address 12 1110 8 7 0 from the stack). PC GOTO, CALL Note: The contents of the PCLATH register are 2 PCLATH<4:3> 11 Opcode<10:0> unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH PCLATH register for any subsequent subroutine calls or GOTO instructions. 2.3.1 COMPUTED GOTO Example2-1 shows the calling of a subroutine in A computed GOTO is accomplished by adding an offset page1 of the program memory. This example assumes to the program counter (ADDWF PCL). When perform- that PCLATH is saved and restored by the Interrupt ing a table read using a computed GOTO method, care Service Routine (if interrupts are used). should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to EXAMPLE 2-1: CALL OF A SUBROUTINE Application Note AN556, Implementing a Table Read IN PAGE 1 FROM PAGE 0 (DS00556). ORG 500h PAGESELSUB_P1 ;Select page 1 2.3.2 STACK ;(800h-FFFh) All devices have an 8-levelx13-bit wide hardware CALL SUB1_P1;Call subroutine in stack (refer to Figures2-1 and2-2). The stack space is : ;page 1 (800h-FFFh) not part of either program or data space and the Stack : Pointer is not readable or writable. The PC is PUSHed ORG 900h ;page 1 (800h-FFFh) SUB1_P1 onto the stack when a CALL instruction is executed or : ;called subroutine an interrupt causes a branch. The stack is POPed in ;page 1 (800h-FFFh) the event of a RETURN, RETLW or a RETFIE instruction : execution. PCLATH is not affected by a PUSH or POP RETURN ;return to operation. ;Call subroutine The stack operates as a circular buffer. This means that ;in page 0 ;(000h-7FFh) after the stack has been PUSHed eight times, the ninth PUSH overwrites the value that was stored from the first PUSH. The tenth PUSH overwrites the second PUSH (and so on).  2010-2016 Microchip Technology Inc. DS40001417C-page 21

PIC16(L)F722A/723A 2.5 Indirect Addressing, INDF and EXAMPLE 2-2: INDIRECT ADDRESSING FSR Registers MOVLW020h ;initialize pointer MOVWFFSR ;to RAM The INDF register is not a physical register. Addressing BANKISEL020h the INDF register will cause indirect addressing. NEXTCLRFINDF ;clear INDF register Indirect addressing is possible by using the INDF INCFFSR ;inc pointer BTFSSFSR,4 ;all done? register. Any instruction using the INDF register GOTONEXT ;no clear next actually accesses data pointed to by the File Select CONTINUE ;yes continue Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit of the STATUS register, as shown in Figure2-6. A simple program to clear RAM location 020h-02Fh using indirect addressing is shown in Example2-2. FIGURE 2-6: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1 RP0 6 From Opcode 0 IRP 7 File Select Register0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 180h Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note: For memory map detail, refer to Figures2-3 and 2-4. DS40001417C-page 22  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 3.0 RESETS Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal The PIC16(L)F722A/723A differentiates between operation. TO and PD bits are set or cleared differently various kinds of Reset: in different Reset situations, as indicated in Table3-3. a) Power-on Reset (POR) These bits are used in software to determine the nature of the Reset. b) WDT Reset during normal operation c) WDT Reset during Sleep A simplified block diagram of the On-Chip Reset Circuit is shown in Figure3-1. d) MCLR Reset during normal operation e) MCLR Reset during Sleep The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section23.0 “Electrical f) Brown-out Reset (BOR) Specifications” for pulse width specifications. Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on: • Power-on Reset (POR) • MCLR Reset • MCLR Reset during Sleep • WDT Reset • Brown-out Reset (BOR) FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT MCLRE MCLR/VPP Sleep WDT WDT Module Time-out Reset POR Power-on Reset VDD Brown-out(1) Reset BOREN OST/PWRT OST Chip_Reset 10-bit Ripple Counter OSC1/ CLKIN PWRT WDTOSC 11-bit Ripple Counter Enable PWRT Enable OST Note 1: Refer to the Configuration Word Register 1 (Register8-1).  2010-2016 Microchip Technology Inc. DS40001417C-page 23

PIC16(L)F722A/723A TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 x 1 1 Power-on Reset or LDO Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during Sleep or interrupt wake-up from Sleep TABLE 3-2: RESET CONDITION FOR SPECIAL REGISTERS(2) Program STATUS PCON Condition Counter Register Register Power-on Reset 0000h 0001 1xxx ---- --0x MCLR Reset during normal operation 0000h 000u uuuu ---- --uu MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu WDT Reset 0000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 0000h 0001 1uuu ---- --u0 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as ‘0’. DS40001417C-page 24  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 3.1 MCLR 3.3 Power-up Timer (PWRT) The PIC16(L)F722A/723A has a noise filter in the The Power-up Timer provides a fixed 64ms (nominal) MCLR Reset path. The filter will detect and ignore time-out on power-up only, from POR or Brown-out small pulses. Reset. The Power-up Timer operates from the WDT oscillator. For more information, see Section7.3 It should be noted that a Reset does not drive the “Internal Clock Modes”. The chip is kept in Reset as MCLR pin low. long as PWRT is active. The PWRT delay allows the Voltages applied to the pin that exceed its specification VDD to rise to an acceptable level. A Configuration bit, can result in both MCLR Resets and excessive current PWRTE, can disable (if set) or enable (if cleared or pro- beyond the device specification during the ESD event. grammed) the Power-up Timer. The Power-up Timer For this reason, Microchip recommends that the MCLR should be enabled when Brown-out Reset is enabled, pin no longer be tied directly to VDD. The use of an RC although it is not required. network, as shown in Figure3-2, is suggested. The Power-up Timer delay will vary from chip-to-chip An internal MCLR option is enabled by clearing the and vary due to: MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated • VDD variation internally. When the MCLRE = 1, the RE3/MCLR pin • Temperature variation becomes an external Reset input. In this mode, the • Process variation RE3/MCLR pin has a weak pull up to VDD. In-Circuit See DC parameters for details (Section23.0 Serial Programming is not affected by selecting the “Electrical Specifications”). internal MCLR option. Note: The Power-up Timer is enabled by the FIGURE 3-2: RECOMMENDED MCLR PWRTE bit in the Configuration Word. CIRCUIT 3.4 Watchdog Timer (WDT) VDD PIC® MCU The WDT has the following features: R1 • Shares an 8-bit prescaler with Timer0 10k • Time-out period is from 17 ms to 2.2 seconds, nominal MCLR • Enabled by a Configuration bit C1 WDT is cleared under certain conditions described in 0.1 F Table3-1. 3.4.1 WDT OSCILLATOR The WDT derives its time base from 31kHz internal oscillator. 3.2 Power-on Reset (POR) Note: When the Oscillator Start-up Timer (OST) The on-chip POR circuit holds the chip in Reset until VDD is invoked, the WDT is held in Reset, has reached a high enough level for proper operation. A because the WDT Ripple Counter is used maximum rise time for VDD is required. See by the OST to perform the oscillator delay Section23.0 “Electrical Specifications” for details. If count. When the OST count has expired, the BOR is enabled, the maximum rise time specification the WDT will begin counting (if enabled). does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section3.5 “Brown-Out Reset (BOR)”). When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, Power-up Trouble Shooting (DS00607).  2010-2016 Microchip Technology Inc. DS40001417C-page 25

PIC16(L)F722A/723A 3.4.2 WDT CONTROL The WDTE bit is located in the Configuration Word Register 1. When set, the WDT runs continuously. The PSA and PS<2:0> bits of the OPTION register control the WDT period. See Section11.0 “Timer0 Module” for more information. FIGURE 3-1: WATCHDOG TIMER BLOCK DIAGRAM T1GSS=11 TMR1GE From TMR0 WDTE Clock Source Low-Power WDT OSC 0 Postscaler Divide by 1 512 8 PS<2:0> TO TMR0 PSA 0 1 WDT Reset To T1G WDTE TABLE 3-1: WDT STATUS Conditions WDT WDTE = 0 Cleared CLRWDT Command Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST DS40001417C-page 26  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 3.5 Brown-Out Reset (BOR) If VDD falls below VBOR for greater than parameter (TBOR) (see Section23.0 “Electrical Specifica- Brown-out Reset is enabled by programming the tions”), the brown-out situation will reset the device. BOREN<1:0> bits in the Configuration register. The This will occur regardless of VDD slew rate. A Reset is brown-out trip point is selectable from two trip points not ensured to occur if VDD falls below VBOR for more via the BORV bit in the Configuration register. than parameter (TBOR). Between the POR and BOR, complete voltage range If VDD drops below VBOR while the Power-up Timer is coverage for execution protection can be running, the chip will go back into a Brown-out Reset implemented. and the Power-up Timer will be re-initialized. Once VDD Two bits are used to enable the BOR. When rises above VBOR, the Power-up Timer will execute a BOREN=11, the BOR is always enabled. When 64ms Reset. BOREN=10, the BOR is enabled, but disabled during Note: When erasing Flash program memory, the Sleep. When BOREN=0X, the BOR is disabled. BOR is forced to enabled at the minimum BOR setting to ensure that any code protection circuitry is operating properly. FIGURE 3-3: BROWN-OUT SITUATIONS VDD VBOR Internal Reset 64 ms(1) VDD VBOR Internal < 64 ms Reset 64 ms(1) VDD VBOR Internal Reset 64 ms(1) Note 1: 64ms delay only if PWRTE bit is programmed to ‘0’.  2010-2016 Microchip Technology Inc. DS40001417C-page 27

PIC16(L)F722A/723A 3.6 Time-out Sequence 3.7 Power Control (PCON) Register On power-up, the time-out sequence is as follows: first, The Power Control (PCON) register has two Status bits PWRT time out is invoked after POR has expired, then to indicate what type of Reset that last occurred. OST is activated after the PWRT time out has expired. Bit0 is BOR (Brown-out Reset). BOR is unknown on The total time out will vary based on oscillator configu- Power-on Reset. It must then be set by the user and ration and PWRTE bit status. For example, in EC mode checked on subsequent Resets to see if BOR = 0, with PWRTE bit = 1 (PWRT disabled), there will be no indicating that a brown-out has occurred. The BOR time-out at all. Figure3-4, Figure3-5 and Figure3-6 Status bit is a “don’t care” and is not necessarily depict time-out sequences. predictable if the brown-out circuit is disabled Since the time outs occur from the POR pulse, if MCLR (BOREN<1:0> = 00 in the Configuration Word register). is kept low long enough, the time-outs will expire. Then, Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on bringing MCLR high will begin execution immediately Reset and unaffected otherwise. The user must write a (see Figure3-5). This is useful for testing purposes or ‘1’ to this bit following a Power-on Reset. On a to synchronize more than one PIC16(L)F722A/723A subsequent Reset, if POR is ‘0’, it will indicate that a device operating in parallel. Power-on Reset has occurred (i.e., VDD may have Table3-3 shows the Reset conditions for some special gone too low). registers. For more information, see Section3.5 “Brown-Out Reset (BOR)”. TABLE 3-2: TIME OUT IN VARIOUS SITUATIONS Power-up Brown-out Reset Wake-up from Oscillator Configuration Sleep PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 XT, HS, LP(1) TPWRT + 1024 • 1024 • TOSC TPWRT + 1024 • 1024 • TOSC 1024 • TOSC TOSC TOSC RC, EC, INTOSC TPWRT — TPWRT — — Note 1: LP mode with T1OSC disabled. TABLE 3-3: RESET BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 u 1 1 Power-on Reset 1 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown DS40001417C-page 28  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset  2010-2016 Microchip Technology Inc. DS40001417C-page 29

PIC16(L)F722A/723A TABLE 3-4: INITIALIZATION CONDITION FOR REGISTERS Power-on Reset/ MCLR Reset/ Wake-up from Sleep through Register Address Brown-out Reset(1) WDT Reset Interrupt/Time out W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/ xxxx xxxx xxxx xxxx uuuu uuuu 100h/180h TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/ 0000 0000 0000 0000 PC + 1(3) 102h/182h STATUS 03h/83h/ 0001 1xxx 000q quuu(4) uuuq quuu(4) 103h/183h FSR 04h/84h/ xxxx xxxx uuuu uuuu uuuu uuuu 104h/184h PORTA 05h xxxx xxxx xxxx xxxx uuuu uuuu PORTB 06h xxxx xxxx xxxx xxxx uuuu uuuu PORTC 07h xxxx xxxx xxxx xxxx uuuu uuuu PORTE 09h ---- x--- ---- x--- ---- u--- PCLATH 0Ah/8Ah/ ---0 0000 ---0 0000 ---u uuuu 10Ah/18Ah INTCON 0Bh/8Bh/ 0000 000x 0000 000x uuuu uuuu(2) 10Bh/18Bh PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2) PIR2 0Dh ---- ---0 ---- ---0 ---- ---u TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 00-0 uuuu uu-u uuuu uu-u TMR2 11h 0000 0000 0000 0000 uuuu uuuu T2CON 12h -000 0000 -000 0000 -uuu uuuu SSPBUF 13h xxxx xxxx xxxx xxxx uuuu uuuu SSPCON 14h 0000 0000 0000 0000 uuuu uuuu CCPR1L 15h xxxx xxxx xxxx xxxx uuuu uuuu CCPR1H 16h xxxx xxxx xxxx xxxx uuuu uuuu CCP1CON 17h --00 0000 --00 0000 --uu uuuu RCSTA 18h 0000 000x 0000 000x uuuu uuuu TXREG 19h 0000 0000 0000 0000 uuuu uuuu RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu CCPR2L 1Bh xxxx xxxx xxxx xxxx uuuu uuuu CCPR2H 1Ch xxxx xxxx xxxx xxxx uuuu uuuu CCP2CON 1Dh --00 0000 --00 0000 --uu uuuu ADRES 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1Fh --00 0000 --00 0000 --uu uuuu OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu TRISA 85h 1111 1111 1111 1111 uuuu uuuu TRISB 86h 1111 1111 1111 1111 uuuu uuuu TRISC 87h 1111 1111 1111 1111 uuuu uuuu TRISE 89h ---- 1--- ---- 1--- ---- u--- Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table3-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. DS40001417C-page 30  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 3-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Power-on Reset/ MCLR Reset/ Wake-up from Sleep through Register Address Brown-out Reset(1) WDT Reset Interrupt/Time out PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu PIE2 8Dh ---- ---0 ---- ---0 ---- ---u PCON 8Eh ---- --qq ---- --uu(1,5) ---- --uu T1GCON 8Fh 0000 0x00 uuuu uxuu uuuu uxuu OSCCON 90h --10 qq-- --10 qq-- --uu qq-- OSCTUNE 91h --00 0000 --uu uuuu --uu uuuu PR2 92h 1111 1111 1111 1111 uuuu uuuu SSPADD 93h 0000 0000 0000 0000 uuuu uuuu SSPMSK 93h 1111 1111 1111 1111 uuuu uuuu SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu WPUB 95h 1111 1111 1111 1111 uuuu uuuu IOCB 96h 0000 0000 0000 0000 uuuu uuuu TXSTA 98h 0000 -010 0000 -010 uuuu -uuu SPBRG 99h 0000 0000 0000 0000 uuuu uuuu APFCON 9Ch ---- --00 ---- --00 ---- --uu FVRCON 9Dh q000 --00 q000 --00 uuuu --uu ADCON1 9Fh -000 --00 -000 --00 -uuu --uu CPSCON0 108h 0--- 0000 0--- 0000 u--- uuuu CPSCON1 109h ---- 0000 ---- 0000 ---- uuuu PMDATL 10Ch xxxx xxxx xxxx xxxx uuuu uuuu PMADRL 10Dh xxxx xxxx xxxx xxxx uuuu uuuu PMDATH 10Eh --xx xxxx --xx xxxx --uu uuuu PMADRH 10Fh ---x xxxx ---x xxxx ---u uuuu ANSELA 185h --11 1111 --11 1111 --uu uuuu ANSELB 186h --11 1111 --11 1111 --uu uuuu PMCON1 18Ch 1--- ---0 1--- ---0 u--- ---u Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table3-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.  2010-2016 Microchip Technology Inc. DS40001417C-page 31

PIC16(L)F722A/723A TABLE 3-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 0000h 0001 1xxx ---- --0x MCLR Reset during normal operation 0000h 000u uuuu ---- --uu MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu WDT Reset 0000h 0000 uuuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 0000h 0001 1xxx ---- --10 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page STATUS IRP RP1 RP0 TO PD Z DC C 18 PCON — — — — — — POR BOR 20 Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS40001417C-page 32  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 4.0 INTERRUPTS The PIC16(L)F722A/723A device family has 12 interrupt sources, differentiated by corresponding The PIC16(L)F722A/723A device family features an interrupt enable and flag bits: interruptible core, allowing certain events to preempt • Timer0 Overflow Interrupt normal program flow. An Interrupt Service Routine (ISR) is used to determine the source of the interrupt • External Edge Detect on INT Pin Interrupt and act accordingly. Some interrupts can be configured • PORTB Change Interrupt to wake the MCU from Sleep mode. • Timer1 Gate Interrupt • A/D Conversion Complete Interrupt • AUSART Receive Interrupt • AUSART Transmit Interrupt • SSP Event Interrupt • CCP1 Event Interrupt • Timer2 Match with PR2 Interrupt • Timer1 Overflow Interrupt • CCP2 Event Interrupt A block diagram of the interrupt logic is shown in Figure4-1. FIGURE 4-1: INTERRUPT LOGIC IOC-RB0 IOCB0 IOC-RB1 IOCB1 SSPIF SSPIE IOC-RB2 IOCB2 TXIF TXIE IOC-RB3 IOCB3 RCIF RCIE Wake-up (If in Sleep mode)(1) IOC-RB4 T0IF IOCB4 TMR2IF T0IE Interrupt to CPU TMR2IE IOC-RB5 INTF IOCB5 INTE TMR1IF RBIF IOC-RB6 TMR1IE RBIE IOCB6 ADIF IOC-RB7 ADIE PEIE IOCB7 TMR1GIF GIE TMR1GIE CCP1IF CCP1IE CCP2IF CCP2IE Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, these peripherals will not wake the part from Sleep. See Section19.1 “Wake-up from Sleep”.  2010-2016 Microchip Technology Inc. DS40001417C-page 33

PIC16(L)F722A/723A 4.1 Operation interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded Interrupts are disabled upon any device Reset. They through its interrupt flag, but will not cause the are enabled by setting the following bits: processor to redirect to the interrupt vector. • GIE bit of the INTCON register The RETFIE instruction exits the ISR by popping the • Interrupt Enable bit(s) for the specific interrupt previous address from the stack and setting the GIE bit. event(s) For additional information on a specific interrupt’s • PEIE bit of the INTCON register (if the Interrupt operation, refer to its peripheral chapter. Enable bit of the interrupt event is contained in the PIE1 and PIE2 registers) Note1: Individual interrupt flag bits are set, regardless of the state of any other The INTCON, PIR1 and PIR2 registers record enable bits. individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE 2: All interrupts will be ignored while the GIE and individual interrupt enable bits. bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced The following events happen when an interrupt event when the GIE bit is set again. occurs while the GIE bit is set: • Current prefetched instruction is flushed 4.2 Interrupt Latency • GIE bit is cleared Interrupt latency is defined as the time from when the • Current Program Counter (PC) is pushed onto the interrupt event occurs to the time code execution at the stack interrupt vector begins. The latency for synchronous • PC is loaded with the interrupt vector 0004h interrupts is three instruction cycles. For asynchronous The ISR determines the source of the interrupt by interrupts, the latency is three to four instruction cycles, polling the interrupt flag bits. The interrupt flag bits must depending on when the interrupt occurs. See Figure4-2 be cleared before exiting the ISR to avoid repeated for timing details. FIGURE 4-2: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 (3) CLKOUT (4) INT pin (1) (1) (2) INTF flag (5) Interrupt Latency (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section23.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS40001417C-page 34  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 4.3 Interrupts During Sleep following the ISR from using invalid data. Examples of key registers include the W, STATUS, FSR and Some interrupts can be used to wake from Sleep. To PCLATH registers. wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source Note: The microcontroller does not normally must have the appropriate interrupt enable bit(s) set require saving the PCLATH register. prior to entering Sleep. However, if computed GOTO’s are used, the PCLATH register must be saved at the On waking from Sleep, if the GIE bit is also set, the beginning of the ISR and restored when processor will branch to the interrupt vector. Otherwise, the ISR is complete to ensure correct the processor will continue executing instructions after program flow. the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before The code shown in Example4-1 can be used to do the branching to the ISR. Refer to Section19.0 “Power- following. Down Mode (Sleep)” for more details. • Save the W register • Save the STATUS register 4.4 INT Pin • Save the PCLATH register The external interrupt, INT pin, causes an • Execute the ISR program asynchronous, edge-triggered interrupt. The INTEDG bit • Restore the PCLATH register of the OPTION register determines on which edge the • Restore the STATUS register interrupt will occur. When the INTEDG bit is set, the • Restore the W register rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The Since most instructions modify the W register, it must INTF bit of the INTCON register will be set when a valid be saved immediately upon entering the ISR. The edge appears on the INT pin. If the GIE and INTE bits SWAPF instruction is used when saving and restoring are also set, the processor will redirect program the W and STATUS registers because it will not affect execution to the interrupt vector. This interrupt is any bits in the STATUS register. It is useful to place disabled by clearing the INTE bit of the INTCON register. W_TEMP in shared memory because the ISR cannot predict which bank will be selected when the interrupt 4.5 Context Saving occurs. The processor will branch to the interrupt vector by When an interrupt occurs, only the return PC value is loading the PC with 0004h. The PCLATH register will saved to the stack. If the ISR modifies or uses an remain unchanged. This requires the ISR to ensure instruction that modifies key registers, their values that the PCLATH register is set properly before using must be saved at the beginning of the ISR and restored an instruction that causes PCLATH to be loaded into when the ISR completes. This prevents instructions the PC. See Section2.3 “PCL and PCLATH” for details on PC operation. EXAMPLE 4-1: SAVING W, STATUS AND PCLATH REGISTERS IN RAM MOVWFW_TEMP ;Copy W to W_TEMP register SWAPFSTATUS,W ;Swap status to be saved into W ;Swaps are used because they do not affect the status bits BANKSELSTATUS_TEMP ;Select regardless of current bank MOVWFSTATUS_TEMP ;Copy status to bank zero STATUS_TEMP register MOVF PCLATH,W ;Copy PCLATH to W register MOVWF PCLATH_TEMP ;Copy W register to PCLATH_TEMP : :(ISR) ;Insert user code here : BANKSELSTATUS_TEMP ;Select regardless of current bank MOVF PCLATH_TEMP,W ; MOVWF PCLATH ;Restore PCLATH SWAPFSTATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWFSTATUS ;Move W into STATUS register SWAPFW_TEMP,F ;Swap W_TEMP SWAPFW_TEMP,W ;Swap W_TEMP into W  2010-2016 Microchip Technology Inc. DS40001417C-page 35

PIC16(L)F722A/723A 4.5.1 INTCON REGISTER Note: Interrupt flag bits are set when an interrupt The INTCON register is a readable and writable condition occurs, regardless of the state of register, which contains the various enable and flag bits its corresponding enable bit or the global for TMR0 register overflow, PORTB change and enable bit, GIE of the INTCON register. external RB0/INT/SEG0 pin interrupts. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 4-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE(1) T0IF(2) INTF RBIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3 RBIE: PORTB Change Interrupt Enable bit(1) 1 = Enables the PORTB change interrupt 0 = Disables the PORTB change interrupt bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0 RBIF: PORTB Change Interrupt Flag bit 1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in software) 0 = None of the PORTB general purpose I/O pins have changed state Note 1: The appropriate bits in the IOCB register must also be set. 2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. DS40001417C-page 36  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 4.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register4-2. set to enable any peripheral interrupt. REGISTER 4-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enable the Timer1 gate acquisition complete interrupt 0 = Disable the Timer1 gate acquisition complete interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt  2010-2016 Microchip Technology Inc. DS40001417C-page 37

PIC16(L)F722A/723A 4.5.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register4-3. set to enable any peripheral interrupt. REGISTER 4-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt DS40001417C-page 38  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 4.5.4 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register4-4. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 4-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Timer1 gate is inactive 0 = Timer1 gate is active bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = A/D conversion complete (must be cleared in software) 0 = A/D conversion has not completed or has not been started bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is not full bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The Transmission/Reception is complete (must be cleared in software) 0 = Waiting to Transmit/Receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = A Timer2 to PR2 match occurred (must be cleared in software) 0 = No Timer2 to PR2 match occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow  2010-2016 Microchip Technology Inc. DS40001417C-page 39

PIC16(L)F722A/723A 4.5.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register4-5. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 4-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture Mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 36 OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 19 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 37 PIE2 — — — — — — — CCP2IE 38 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 39 PIR2 — — — — — — — CCP2IF 40 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM. DS40001417C-page 40  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 5.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F722A/723A devices differ from the PIC16LF722A/723A devices due to an internal Low Dropout (LDO) voltage regulator. The PIC16F722A/ 723A devices contain an internal LDO, while the PIC16LF722A/723A ones do not. The lithography of the die allows a maximum operating voltage of 3.6V on the internal digital logic. In order to continue to support 5.0V designs, a LDO voltage regulator is integrated on the die. The LDO voltage regulator allows for the internal digital logic to operate at 3.2V, while I/O’s operate at 5.0V (VDD). The LDO voltage regulator requires an external bypass capacitor for stability. One of three pins, denoted as VCAP, can be configured for the external bypass capacitor. It is recommended that the capacitor be a ceramic cap between 0.1 to 1.0 µF. The VCAP pin is not intended to supply power to external loads. An external voltage regulator should be used if this functionality is required. In addition, external devices should not supply power to the VCAP pin. On power-up, the external capacitor will look like a large load on the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor. After the cap is fully charged, the device is released from Reset. For more information, refer to Section23.0 “Electrical Specifications”. See Configuration Word 2 register (Register8-2) for VCAP enable bits.  2010-2016 Microchip Technology Inc. DS40001417C-page 41

PIC16(L)F722A/723A 6.0 I/O PORTS There are as many as thirty-five general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 6.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register6-1. For this device family, the following functions can be moved between different pins: • SS (Slave Select) • CCP2 REGISTER 6-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SSSEL CCP2SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’. bit 1 SSSEL: SS Input Pin Selection bit 0 = SS function is on RA5/AN4/CPS7/SS/VCAP 1 = SS function is on RA0/AN0/SS/VCAP bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit 0 = CCP2 function is on RC1/T1OSI/CCP2 1 = CCP2 function is on RB3/CCP2 DS40001417C-page 42  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 6.2 PORTA and the TRISA Registers TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always PORTA is a 8-bit wide, bidirectional port. The read ‘0’. corresponding data direction register is TRISA Note: The ANSELA register must be initialized (Register6-3). Setting a TRISA bit (= 1) will make the to configure an analog channel as a digital corresponding PORTA pin an input (i.e., disable the input. Pins configured as analog inputs output driver). Clearing a TRISA bit (= 0) will make the will read ‘0’. corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch EXAMPLE 6-1: INITIALIZING PORTA on the selected pin). Example6-1 shows how to initialize PORTA. BANKSELPORTA ; CLRF PORTA ;Init PORTA Reading the PORTA register (Register6-2) reads the BANKSELANSELA ; status of the pins, whereas writing to it will write to the CLRF ANSELA ;digital I/O PORT latch. All write operations are read-modify-write BANKSELTRISA ; operations. Therefore, a write to a port implies that the MOVLW 0Ch ;Set RA<3:2> as inputs port pins are read, this value is modified and then MOVWF TRISA ;and set RA<7:4,1:0> written to the PORT data latch. ;as outputs The TRISA register (Register6-3) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the REGISTER 6-2: PORTA: PORTA REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RA<7:0>: PORTA I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 6-3: TRISA: PORTA TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output  2010-2016 Microchip Technology Inc. DS40001417C-page 43

PIC16(L)F722A/723A 6.2.1 ANSELA REGISTER The ANSELA register (Register6-4) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. REGISTER 6-4: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS40001417C-page 44  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 6.2.2 PIN DESCRIPTIONS AND 6.2.2.6 RA5/AN4/CPS7/SS/VCAP DIAGRAMS Figure6-4 shows the diagram for this pin. This pin is Each PORTA pin is multiplexed with other functions. The configurable to function as one of the following: pins and their combined functions are briefly described • General purpose I/O here. For specific information about individual functions • Analog input for the ADC such as the A/D Converter (ADC), refer to the • Capacitive sensing input appropriate section in this data sheet. • Slave select input for the SSP(1) 6.2.2.1 RA0/AN0/SS/VCAP • Voltage regulator capacitor pin (PIC16F722A/ Figure6-1 shows the diagram for this pin. This pin is 723A only) configurable to function as one of the following: Note1: SS pin location may be selected as RA5 • General purpose I/O or RA0. • Analog input for the ADC • Slave select input for the SSP(1) 6.2.2.7 RA6/OSC2/CLKOUT/VCAP • Voltage regulator capacitor pin (PIC16F722A/ Figure6-5 shows the diagram for this pin. This pin is 723A only) configurable to function as one of the following: Note1: SS pin location may be selected as RA5 • General purpose I/O or RA0. • Crystal/resonator connection • Clock output 6.2.2.2 RA1/AN1 • Voltage regulator capacitor pin (PIC16F722A/ Figure6-2 shows the diagram for this pin. This pin is 723A only) configurable to function as one of the following: 6.2.2.8 RA7/OSC1/CLKIN • General purpose I/O Figure6-6 shows the diagram for this pin. This pin is • Analog input for the ADC configurable to function as one of the following: 6.2.2.3 RA2/AN2 • General purpose I/O Figure6-2 shows the diagram for this pin. This pin is • Crystal/resonator connection configurable to function as one of the following: • Clock input • General purpose I/O • Analog input for the ADC 6.2.2.4 RA3/AN3/VREF Figure6-2 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • Analog input for the ADC • Voltage reference input for the ADC 6.2.2.5 RA4/CPS6/T0CKI Figure6-3 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • Capacitive sensing input • Clock input for Timer0 The Timer0 clock input function works independently of any TRIS register setting. Effectively, if TRISA4=0, the PORTA4 register bit will output to the pad and clock Timer0 at the same time.  2010-2016 Microchip Technology Inc. DS40001417C-page 45

PIC16(L)F722A/723A FIGURE 6-1: BLOCK DIAGRAM OF RA0 PIC16F722A/723A only To Voltage Regulator VCAPEN = 00 Data Bus VDD D Q WR CK I/O Pin Q PORTA D Q VSS WR CK TRISA Q RD TRISA ANSA0 RD PORTA TO SSP SS Input To A/D Converter DS40001417C-page 46  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 6-2: RA<3:1> BLOCK DIAGRAM Data Bus VDD D Q WR CK I/O Pin Q PORTA D Q VSS WR CK TRISA Q RD TRISA ANSAx RD PORTA To A/D Converter FIGURE 6-3: BLOCK DIAGRAM OF RA4 Data Bus VDD D Q WR CK I/O Pin Q PORTA D Q VSS WR CK TRISA Q RD TRISA ANSA4 RD PORTA To Timer0 Clock MUX To Cap Sensor  2010-2016 Microchip Technology Inc. DS40001417C-page 47

PIC16(L)F722A/723A FIGURE 6-4: BLOCK DIAGRAM OF RA5 PIC16F722A/723A only To Voltage Regulator VCAPEN = 01 Data Bus VDD D Q WR CK I/O Pin Q PORTA D Q VSS WR CK TRISA Q RD TRISA ANSA5 RD PORTA To SSP SS Input To A/D Converter To Cap Sensor DS40001417C-page 48  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 6-5: BLOCK DIAGRAM OF RA6 PIC16F722A/723A only To Voltage Regulator VCAPEN = 10 Oscillator CLKOUT(1) Enable Circuit VDD RA7/OSC1 Data Bus I/O Pin FOSC/4 1 D Q 0 WR CK Q PORTA VSS D Q WR CK TRISA Q RD TRISA FOSC = LP or XT or HS (00X OR 010) RD PORTA Note1: CLKOUT Enable = 1 when FOSC = RC or INTOSC (No I/O Selected). FIGURE 6-6: BLOCK DIAGRAM OF RA7 Oscillator Data Bus Circuit VDD RA6/OSC2 I/O Pin D Q WR CK Q PORTA D Q VSS WR CK TRISA Q RD TRISA OSC = INTOSC or INTOSCIO RD PORTA  2010-2016 Microchip Technology Inc. DS40001417C-page 49

PIC16(L)F722A/723A TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/ ADON 85 DONE ADCON1 — ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 86 ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 44 APFCON — — — — — — SSSEL CCP2SEL 42 CPSCON0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 112 CPSCON1 — — — — — CPSCH2 CPSCH1 CPSCH0 113 OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 19 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 43 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 152 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 43 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. TABLE 6-2: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page CONFIG2(1) 13:8 — — — — — — — — 78 7:0 — — VCAPEN1 VCAPEN0 WDTE — — — Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Note 1: PIC16F722A/723A only. DS40001417C-page 50  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 6.3 PORTB and TRISB Registers 6.3.1 ANSELB REGISTER PORTB is an 8-bit wide, bidirectional port. The The ANSELB register (Register6-9) is used to corresponding data direction register is TRISB configure the Input mode of an I/O pin to analog. (Register6-6). Setting a TRISB bit (= 1) will make the Setting the appropriate ANSELB bit high will cause all corresponding PORTB pin an input (i.e., put the digital reads on the pin to be read as ‘0’ and allow corresponding output driver in a High-Impedance mode). analog functions on the pin to operate correctly. Clearing a TRISB bit (= 0) will make the corresponding The state of the ANSELB bits has no affect on digital PORTB pin an output (i.e., enable the output driver and output functions. A pin with TRIS clear and ANSELB put the contents of the output latch on the selected pin). set will still operate as a digital output, but the Input Example6-2 shows how to initialize PORTB. mode will be analog. This can cause unexpected Reading the PORTB register (Register6-5) reads the behavior when executing read-modify-write status of the pins, whereas writing to it will write to the instructions on the affected port. PORT latch. All write operations are read-modify-write 6.3.2 WEAK PULL UPS operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written Each of the PORTB pins has an individually configurable to the PORT data latch. internal weak pull up. Control bits WPUB<7:0> enable or The TRISB register (Register6-6) controls the PORTB disable each pull up (see Register6-7). Each weak pull pin output drivers, even when they are being used as up is automatically turned off when the port pin is analog inputs. The user should ensure the bits in the configured as an output. All pull ups are disabled on a TRISB register are maintained set when using them as Power-on Reset by the RBPU bit of the OPTION register. analog inputs. I/O pins configured as analog input always 6.3.3 INTERRUPT-ON-CHANGE read ‘0’. Example6-2 shows how to initialize PORTB. All of the PORTB pins are individually configurable as an EXAMPLE 6-2: INITIALIZING PORTB interrupt-on-change pin. Control bits IOCB<7:0> enable or disable the interrupt function for each pin. Refer to BANKSELPORTB ; Register6-8. The interrupt-on-change feature is CLRF PORTB ;Init PORTB disabled on a Power-on Reset. BANKSELANSELB CLRF ANSELB ;Make RB<7:0> digital For enabled interrupt-on-change pins, the present value BANKSELTRISB ; is compared with the old value latched on the last read MOVLW B’11110000’;Set RB<7:4> as inputs of PORTB to determine which bits have changed or ;and RB<3:0> as outputs mismatched the old value. The ‘mismatch’ outputs of MOVWF TRISB ; the last read are OR’d together to set the PORTB Change Interrupt flag bit (RBIF) in the INTCON register. This interrupt can wake the device from Sleep. The user, Note: The ANSELB register must be initialized in the Interrupt Service Routine, clears the interrupt by: to configure an analog channel as a digital a) Any read or write of PORTB. This will end the input. Pins configured as analog inputs mismatch condition. will read ‘0’. b) Clear the flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading or writing PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After these Resets, the RBIF flag will continue to be set if a mismatch is present. Note: When a pin change occurs at the same time as a read operation on PORTB, the RBIF flag will always be set. If multiple PORTB pins are configured for the interrupt-on-change, the user may not be able to identify which pin changed state.  2010-2016 Microchip Technology Inc. DS40001417C-page 51

PIC16(L)F722A/723A REGISTER 6-5: PORTB: PORTB REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RB<7:0>: PORTB I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 6-6: TRISB: PORTB TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output REGISTER 6-7: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 WPUB<7:0>: Weak Pull-up Register bits 1 = Pull up enabled 0 = Pull up disabled Note 1: Global RBPU bit of the OPTION register must be cleared for individual pull ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. DS40001417C-page 52  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A REGISTER 6-8: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled REGISTER 6-9: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Function on Pins RB<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.  2010-2016 Microchip Technology Inc. DS40001417C-page 53

PIC16(L)F722A/723A 6.3.4 PIN DESCRIPTIONS AND 6.3.4.6 RB5/AN13/CPS5/T1G DIAGRAMS Figure6-10 shows the diagram for this pin. This pin is Each PORTB pin is multiplexed with other functions. The configurable to function as one of the following: pins and their combined functions are briefly described • General purpose I/O here. For specific information about individual functions • Analog input for the ADC such as the SSP, I2C or interrupts, refer to the appropriate • Capacitive sensing input section in this data sheet. • Timer1 gate input 6.3.4.1 RB0/AN12/CPS0/INT 6.3.4.7 RB6/ICSPCLK Figure6-7 shows the diagram for this pin. This pin is configurable to function as one of the following: Figure6-11 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • a general purpose I/O • Analog input for the ADC • In-Circuit Serial Programming clock • Capacitive sensing input • External edge triggered interrupt 6.3.4.8 RB7/ICSPDAT 6.3.4.2 RB1/AN10/CPS1 Figure6-12 shows the diagram for this pin. This pin is configurable to function as one of the following: Figure6-8 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • In-Circuit Serial Programming data • General purpose I/O • Analog input for the ADC • Capacitive sensing input 6.3.4.3 RB2/AN8/CPS2 Figure6-8 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • Analog input for the ADC • Capacitive sensing input 6.3.4.4 RB3/AN9/CPS3/CCP2 Figure6-9 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • Analog input for the ADC • Capacitive sensing input • Capture 2 input, Compare 2 output, and PWM2 output Note: CCP2 pin location may be selected as RB3 or RC1. 6.3.4.5 RB4/AN11/CPS4 Figure6-8 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • Analog input for the ADC • Capacitive sensing input DS40001417C-page 54  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 6-7: BLOCK DIAGRAM OF RB0 Data Bus D Q VDD WR CK WPUB Q Weak RD RBPU VDD WPUB D Q WR CK I/O Pin Q PORTB D Q VSS WR CK TRISB Q RD TRISB ANSB0 RD PORTB D Q WR CK Q Q D IOCB EN Q3 RD IOCB Q D EN Interrupt-on- Change RD PORTB To External Interrupt Logic To A/D Converter To Cap Sensor  2010-2016 Microchip Technology Inc. DS40001417C-page 55

PIC16(L)F722A/723A FIGURE 6-8: BLOCK DIAGRAM OF RB4, RB<2:1> Data Bus D Q VDD WR CK WPUB Q Weak RD RBPU VDD WPUB D Q WR CK I/O Pin Q PORTB D Q VSS WR CK TRISB Q RD TRISB ANSB<4,2,1> RD PORTB D Q WR CK Q Q D IOCB EN Q3 To A/D Converter RD IOCB Q D To Cap Sensor EN Interrupt-on- Change RD PORTB DS40001417C-page 56  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 6-9: BLOCK DIAGRAM OF RB3 Data Bus D Q VDD WR CK WPUB Q Weak CCP2OUT Enable VDD RD RBPU WPUB CCP2OUT 1 D Q 0 I/O Pin WR CK Q PORTB VSS D Q WR CK TRISB Q RD TRISB ANSB<5,3> RD PORTB D Q WR CK Q Q D IOCB EN Q3 RD IOCB Q D EN Interrupt-on- Change RD PORTB To CCP2(1) To A/D Converter To Cap Sensor Note 1: CCP2 input is controlled by CCP2SEL in the APFCON register.  2010-2016 Microchip Technology Inc. DS40001417C-page 57

PIC16(L)F722A/723A FIGURE 6-10: BLOCK DIAGRAM OF RB5 Data Bus D Q VDD WR CK WPUB Q Weak CCP2OUT Enable VDD RD RBPU WPUB CCP2OUT 1 D Q 0 I/O Pin WR CK Q PORTB VSS D Q WR CK TRISB Q RD TRISB ANSB<5,3> RD PORTB D Q WR CK Q Q D IOCB EN Q3 RD IOCB Q D EN Interrupt-on- Change RD PORTB To Timer1 Gate To A/D Converter To Cap Sensor DS40001417C-page 58  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 6-11: BLOCK DIAGRAM OF RB6 ICSP™ Mode Debug Data Bus D Q VDD WR CK WPUB Q Weak RD RBPU VDD WPUB PORT_ICDCLK 1 D Q 0 WR CK I/O Pin Q PORTB D Q VSS 0 WR CK TRISB Q 1 RD TRISB TRIS_ICDCLK RD PORTB D Q WR CK Q Q D IOCB EN Q3 RD IOCB Q D EN Interrupt-on- Change RD PORTB ICSPCLK  2010-2016 Microchip Technology Inc. DS40001417C-page 59

PIC16(L)F722A/723A FIGURE 6-12: BLOCK DIAGRAM OF RB7 ICSP™ Mode Debug Data Bus D Q VDD WR CK WPUB Q Weak RD RBPU VDD WPUB PORT_ICDDAT 1 D Q 0 WR CK I/O Pin Q PORTB D Q VSS 0 WR CK TRISB Q 1 RD TRISB TRIS_ICDDAT RD PORTB D Q WR CK Q Q D IOCB EN Q3 RD IOCB Q D EN Interrupt-on- Change RD PORTB ICSPDAT_IN DS40001417C-page 60  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 6-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/ ADON 85 DONE ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 53 APFCON — — — — — — SSSEL CCP2SEL 42 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 115 CPSCON0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 112 CPSCON1 — — — — — CPSCH2 CPSCH1 CPSCH0 113 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 36 IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 53 OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 19 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 104 DONE TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 52 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 52 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.  2010-2016 Microchip Technology Inc. DS40001417C-page 61

PIC16(L)F722A/723A 6.4 PORTC and TRISC Registers The TRISC register (Register6-11) controls the PORTC pin output drivers, even when they are being used as PORTC is a 8-bit wide, bidirectional port. The analog inputs. The user should ensure the bits in the corresponding data direction register is TRISC TRISC register are maintained set when using them as (Register6-11). Setting a TRISC bit (= 1) will make the analog inputs. I/O pins configured as analog input always corresponding PORTC pin an input (i.e., put the read ‘0’. corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding EXAMPLE 6-3: INITIALIZING PORTC PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). BANKSELPORTC ; Example6-3 shows how to initialize PORTC. CLRF PORTC ;Init PORTC BANKSELTRISC ; Reading the PORTC register (Register6-10) reads the MOVLW B‘00001100’ ;Set RC<3:2> as inputs status of the pins, whereas writing to it will write to the MOVWF TRISC ;and set RC<7:4,1:0> PORT latch. All write operations are read-modify-write ;as outputs operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written The location of the CCP2 function is controlled by the to the PORT data latch. CCP2SEL bit in the APFCON register (refer to Register6-1). REGISTER 6-10: PORTC: PORTC REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 6-11: TRISC: PORTC TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output DS40001417C-page 62  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 6.4.1 RC0/T1OSO/T1CKI 6.4.8 RC7/RX/DT Figure6-13 shows the diagram for this pin. This pin is Figure6-20 shows the diagram for this pin. This pin is configurable to function as one of the following: configurable to function as one of the following: • General purpose I/O • General purpose I/O • Timer1 oscillator output • Asynchronous serial input • Timer1 clock input • Synchronous serial data I/O 6.4.2 RC1/T1OSI/CCP2 Figure6-14 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • Timer1 oscillator input • Capture 2 input, Compare 2 output, and PWM2 output Note: CCP2 pin location may be selected as RB3 or RC1. 6.4.3 RC2/CCP1 Figure6-15 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • Capture 1 input, Compare 1 output, and PWM1 output 6.4.4 RC3/SCK/SCL Figure6-16 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • SPI clock • I2C clock 6.4.5 RC4/SDI/SDA Figure6-17 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • SPI data input • I2C data I/O 6.4.6 RC5/SDO Figure6-18 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • SPI data output 6.4.7 RC6/TX/CK Figure6-19 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose I/O • Asynchronous serial output • Synchronous clock I/O  2010-2016 Microchip Technology Inc. DS40001417C-page 63

PIC16(L)F722A/723A FIGURE 6-13: BLOCK DIAGRAM OF RC0 Oscillator Data Bus Circuit VDD RC1/T1OSI D Q WR CK I/O Pin Q PORTC D Q VSS WR CK TRISC Q RD TRISC T1OSCEN RD PORTC To Timer1 CLK Input FIGURE 6-14: BLOCK DIAGRAM OF RC1 CCP2OUT Oscillator Data Bus Enable Circuit VDD RC0/T1OSO CCP2OUT 1 D Q 0 WR CK I/O Pin Q PORTC D Q VSS WR CK TRISC Q RD TRISC T1OSCEN RD PORTC To CCP2(1) Input Note 1: CCP2 input is controlled by CCP2SEL in the APFCON register. DS40001417C-page 64  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 6-15: BLOCK DIAGRAM OF RC2 CCP1OUT Enable Data Bus VDD CCP1OUT 1 D Q 0 WR CK I/O Pin Q PORTC D Q VSS WR CK TRISC Q RD TRISC RD PORTC To CCP1 Input FIGURE 6-16: BLOCK DIAGRAM OF RC3 SSPM = SPI Mode SCK_MASTER 1 VDD SSPEN Data Bus 0 1 D Q 0 (2) I/O Pin WR CK Q PORTC SCL VSS D Q WR CK TRISC Q RD TRISC To SSP SPI CLOCK Input 01 RD 10 PORTC SSPEN SSPM = I2C Mode TO SSP I2C SCL Input I2C(1) Note 1: I2C Schmitt Trigger has special input levels. 2: I2C Slew Rate limiting controlled by SMP bit of SSPSTAT register.  2010-2016 Microchip Technology Inc. DS40001417C-page 65

PIC16(L)F722A/723A FIGURE 6-17: BLOCK DIAGRAM OF RC4 SSPEN SSPM = I2C Mode VDD Data Bus 1 D Q 0 (2) I/O Pin WR CK Q PORTC VSS D Q WR CK TRISC Q RD TRISC To SSP SPI Data Input 01 RD PORTC 10 SDA from SSP To SSP I2C SDA Input I2C(1) Note 1: I2C Schmitt Trigger has special input levels. 2: I2C Slew Rate limiting controlled by SMP bit of SSPSTAT register. FIGURE 6-18: BLOCK DIAGRAM OF RC5 SSPEN SSPM = SPI Mode VDD Data Bus SDO 1 D Q 0 I/O Pin WR CK Q PORTC VSS D Q SDO EN TRWISRC CK Q RD TRISC RD PORTC DS40001417C-page 66  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 6-19: BLOCK DIAGRAM OF RC6 SYNC USART_TX 0 VDD USART_CK 1 1 Data Bus D Q 0 WR CK I/O Pin Q PORTC D Q VSS WR CK TRISC Q RD TRISC RD PORTC SPEN TXEN 0 CSRC 1 SYNC To USART Sync Clock Input FIGURE 6-20: BLOCK DIAGRAM OF RC7 SPEN SYNC Data Bus VDD USART_DT 1 D Q 0 WR CK I/O Pin Q PORTC D Q VSS WR CK TRISC Q RD TRISC RD PORTC SPEN SYNC TXEN SREN CREN To USART Data Input  2010-2016 Microchip Technology Inc. DS40001417C-page 67

PIC16(L)F722A/723A TABLE 6-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON — — — — — — SSSEL CCP2SEL 42 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 115 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 115 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 62 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 134 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 152 SSPSTAT SMP CKE D/A P S R/W UA BF 153 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 103 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 133 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 62 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. DS40001417C-page 68  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 6.5 PORTE and TRISE Registers PORTE(1) is an 1-bit wide, input-only port. RE3 is input- only and its TRIS bit will always read as ‘1’. Reading the PORTE register (Register6-12) reads the status of the pins. RE3 reads ‘0’ when MCLRE = 1. REGISTER 6-12: PORTE: PORTE REGISTER U-0 U-0 U-0 U-0 R-x U-0 U-0 U-0 — — — — RE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 RE3: PORTE I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 2-0 Unimplemented: Read as ‘0’ REGISTER 6-13: TRISE: PORTE TRI-STATE REGISTER U-0 U-0 U-0 U-0 R-1 U-0 U-0 U-0 — — — — TRISE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 TRISE3: RE3 Port Tri-state Control bit This bit is always ‘1’ as RE3 is an input-only bit 2-0 Unimplemented: Read as ‘0’ TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page PORTE — — — — RE3 — — — 69 TRISE — — — — TRISE3(1) — — — 69 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE Note1: This bit is always ‘1’ as RE3 is input-only.  2010-2016 Microchip Technology Inc. DS40001417C-page 69

PIC16(L)F722A/723A 6.5.1 RE3/MCLR/VPP Figure6-21 shows the diagram for this pin. This pin is configurable to function as one of the following: • General purpose input • Master Clear Reset with weak pull up • Programming voltage reference input FIGURE 6-21: BLOCK DIAGRAM OF RE3 VDD ICSP™ Mode Detect Weak In-Circuit Serial Programming™ Mode High-Voltage Detect I/O Pin MCLR Circuit MCLR Pulse Filter VSS Data Bus RD TRISE VSS RD PORTE Power for Programming Flash DS40001417C-page 70  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 7.0 OSCILLATOR MODULE Clock source modes are configured by the FOSC bits in Configuration Word 1 (CONFIG1). The oscillator module can be configured for one of eight modes of 7.1 Overview operation. The oscillator module has a wide variety of clock sources 1. RC – External Resistor-Capacitor (RC) with and selection features that allow it to be used in a wide FOSC/4 output on OSC2/CLKOUT. range of applications while maximizing performance and 2. RCIO – External Resistor-Capacitor (RC) with minimizing power consumption. Figure7-1 illustrates a I/O on OSC2/CLKOUT. block diagram of the oscillator module. 3. INTOSC – Internal oscillator with FOSC/4 output Clock sources can be configured from external on OSC2 and I/O on OSC1/CLKIN. oscillators, quartz crystal resonators, ceramic resonators 4. INTOSCIO – Internal oscillator with I/O on and Resistor-Capacitor (RC) circuits. In addition, the OSC1/CLKIN and OSC2/CLKOUT. system can be configured to use an internal calibrated 5. EC – External clock with I/O on OSC2/CLKOUT. high-frequency oscillator as clock source, with a choice of selectable speeds via software. 6. HS – High Gain Crystal or Ceramic Resonator mode. 7. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode. 8. LP – Low-Power Crystal mode. FIGURE 7-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FOSC<2:0> External Oscillator (Configuration Word 1) OSC2 Sleep LP, XT, HS, RC, EC OSC1 X U M System Clock Internal Oscillator IRCF<1:0> (CPU and Peripherals) (OSCCON Register) INTOSC 500kHz 0 X 16 MHz/500 kHz U 11 M 32x 1 8 MHz/250 kHz PLL 10 X aler 4 MHz/125 kHz MU sc 01 st o P 2 MHz/62.5 kHz 00 PLLEN (Configuration Word 1)  2010-2016 Microchip Technology Inc. DS40001417C-page 71

PIC16(L)F722A/723A 7.2 Clock Source Modes 7.3.2 FREQUENCY SELECT BITS (IRCF) Clock source modes can be classified as external or The output of the 500 kHz INTOSC and 16 MHz internal. INTOSC, with Phase-Locked Loop enabled, connect to a postscaler and multiplexer (see Figure7-1). The • Internal clock source (INTOSC) is contained Internal Oscillator Frequency Select bits (IRCF) of the within the oscillator module and derived from a OSCCON register select the frequency output of the 500kHz high precision oscillator. The oscillator internal oscillator. Depending upon the PLLEN bit, one module has eight selectable output frequencies, of four frequencies of two frequency sets can be with a maximum internal frequency of 16 MHz. selected via software: • External clock modes rely on external circuitry for If PLLEN = 1, frequency selection is as follows: the clock source. Examples are: oscillator mod- ules (EC mode), quartz crystal resonators or • 16 MHz ceramic resonators (LP, XT and HS modes) and • 8 MHz (Default after Reset) Resistor-Capacitor (RC) mode circuits. • 4 MHz The system clock can be selected between external or • 2 MHz internal clock sources via the FOSC bits of the If PLLEN = 0, frequency selection is as follows: Configuration Word 1. • 500 kHz 7.3 Internal Clock Modes • 250 kHz (Default after Reset) • 125 kHz The oscillator module has eight output frequencies • 62.5 kHz derived from a 500 kHz high precision oscillator. The IRCF bits of the OSCCON register select the Note: Following any Reset, the IRCF<1:0> bits postscaler applied to the clock source dividing the of the OSCCON register are set to ‘10’ and frequency by 1, 2, 4 or 8. Setting the PLLEN bit of the the frequency selection is set to 8MHz or Configuration Word 1 locks the internal clock source to 250kHz. The user can modify the IRCF 16 MHz before the postscaler is selected by the IRCF bits to select a different frequency. bits. The PLLEN bit must be set or cleared at the time There is no start-up delay before a new frequency of programming; therefore, only the upper or low four selected in the IRCF bits takes effect. This is because clock source frequencies are selectable in software. the old and new frequencies are derived from INTOSC via the postscaler and multiplexer. 7.3.1 INTOSC AND INTOSCIO MODES Start-up delay specifications are located in Table23-2 The INTOSC and INTOSCIO modes configure the in Section23.0 “Electrical Specifications”. internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the CONFIG1 register. See Section8.0 “Device Configuration” for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/ CLKOUT are available for general purpose I/O. DS40001417C-page 72  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 7.4 Oscillator Control The Oscillator Control (OSCCON) register (Figure7-1) displays the status and allows frequency selection of the internal oscillator (INTOSC) system clock. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • Status Locked bits (ICSL) • Status Stable bits (ICSS) REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 U-0 R/W-1 R/W-0 R-q R-q U-0 U-0 — — IRCF1 IRCF0 ICSL ICSS — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 IRCF<1:0>: Internal Oscillator Frequency Select bits When PLLEN = 1 (16MHz INTOSC) 11 = 16MHz 10 = 8MHz (POR value) 01 = 4MHz 00 = 2MHz When PLLEN = 0 (500kHz INTOSC) 11 = 500kHz 10 = 250kHz (POR value) 01 = 125kHz 00 = 62.5kHz bit 3 ICSL: Internal Clock Oscillator Status Locked bit (2% Stable) 1 = 16MHz/500kHz Internal Oscillator (HFIOSC) is in lock 0 = 16MHz/500kHz Internal Oscillator (HFIOSC) has not yet locked bit 2 ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable) 1 = 16MHz/500kHz Internal Oscillator (HFIOSC) has stabilized to its maximum accuracy 0 = 16MHz/500kHz Internal Oscillator (HFIOSC) has not yet reached its maximum accuracy bit 1-0 Unimplemented: Read as ‘0’  2010-2016 Microchip Technology Inc. DS40001417C-page 73

PIC16(L)F722A/723A 7.5 Oscillator Tuning When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. Code The INTOSC is factory-calibrated but can be adjusted execution continues during this shift. There is no in software by writing to the OSCTUNE register indication that the shift has occurred. (Register7-2). The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number. REGISTER 7-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 01 1111 = Maximum frequency 01 1110 = • • • 00 0001 = 00 0000 = Oscillator module is running at the factory-calibrated frequency. 11 1111 = • • • 10 0000 = Minimum frequency DS40001417C-page 74  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 7.6 External Clock Modes XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode 7.6.1 OSCILLATOR START-UP TIMER (OST) current consumption is the medium of the three modes. This mode is best suited to drive resonators with a If the oscillator module is configured for LP, XT or HS medium drive level specification. modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations on the OSC1 pin before the device is HS Oscillator mode selects the highest gain setting of the released from Reset. This occurs following a Power-on internal inverter-amplifier. HS mode current consumption Reset (POR) and when the Power-up Timer (PWRT) is the highest of the three modes. This mode is best has expired (if configured), or a wake-up from Sleep. suited for resonators that require a high drive setting. During this time, the program counter does not Figure7-3 and Figure7-4 show typical circuits for increment and program execution is suspended. The quartz crystal and ceramic resonators, respectively. OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and FIGURE 7-3: QUARTZ CRYSTAL is providing a stable system clock to the oscillator OPERATION (LP, XT OR module. HS MODE) 7.6.2 EC MODE PIC® MCU The External Clock (EC) mode allows an externally generated logic level as the system clock source. When OSC1/CLKIN operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available C1 To Internal for general purpose I/O. Figure7-2 shows the pin Logic connections for EC mode. QCruyasrttazl RF(2) Sleep The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up C2 RS(1) OSC2/CLKOUT from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the Note 1: A series resistor (RS) may be required for effect of halting the device while leaving all data intact. quartz crystals with low drive level. Upon restarting the external clock, the device will 2: The value of RF varies with the Oscillator mode resume operation as if no time had elapsed. selected. FIGURE 7-2: EXTERNAL CLOCK (EC) MODE OPERATION Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the Clock from OSC1/CLKIN manufacturer data sheets for specifications Ext. System and recommended application. PIC® MCU 2: Always verify oscillator performance over I/O OSC2/CLKOUT(1) the VDD and temperature range that is expected for the application. Note 1: Alternate pin functions are described in 3: For oscillator design assistance, reference Section6.1 “Alternate Pin Function”. the following Microchip Applications Notes: • AN826, Crystal Oscillator Basics and 7.6.3 LP, XT, HS MODES Crystal Selection for rfPIC® and PIC® The LP, XT and HS modes support the use of quartz Devices (DS00826) crystal resonators or ceramic resonators connected to • AN849, Basic PIC® Oscillator Design OSC1 and OSC2 (Figure7-3). The mode selects a low, (DS00849) medium or high gain setting of the internal inverter- • AN943, Practical PIC® Oscillator amplifier to support various resonator types and speed. Analysis and Design (DS00943) LP Oscillator mode selects the lowest gain setting of the • AN949, Making Your Oscillator Work internal inverter-amplifier. LP mode current consumption (DS00949) is the least of the three modes. This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals.  2010-2016 Microchip Technology Inc. DS40001417C-page 75

PIC16(L)F722A/723A FIGURE 7-4: CERAMIC RESONATOR FIGURE 7-5: EXTERNAL RC MODES OPERATION (XT OR HS MODE) VDD PIC® MCU PIC® MCU REXT OSC1/CLKIN Internal OSC1/CLKIN Clock CEXT C1 To Internal Logic VSS RP(3) RF(2) Sleep FOSC/4 or OSC2/CLKOUT(1) I/O(2) C2 Ceramic RS(1) OSC2/CLKOUT Recommended values: 10 k  REXT  100 k, <3V Resonator 3 k  REXT  100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. Note 1: Alternate pin functions are described in Section6.1 “Alternate Pin Function”. 2: The value of RF varies with the Oscillator mode selected. 2: Output depends upon RC or RCIO clock mode. 3: An additional parallel feedback resistor (RP) In RCIO mode, the RC circuit is connected to OSC1. may be required for proper ceramic resonator OSC2 becomes an additional general purpose I/O pin. operation. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values 7.6.4 EXTERNAL RC MODES and the operating temperature. Other factors affecting The external Resistor-Capacitor (RC) modes support the oscillator frequency are: the use of an external RC circuit. This allows the • threshold voltage variation designer maximum flexibility in frequency choice while • component tolerances keeping costs to a minimum when clock accuracy is not • packaging variations in capacitance required. There are two modes: RC and RCIO. The user also needs to take into account variation due In RC mode, the RC circuit connects to OSC1. OSC2/ to tolerance of external RC components used. CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure7-5 shows the external RC mode connections. TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON — — IRCF1 IRCF0 ICSL ICSS — — 73 OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 74 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. TABLE 7-2: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — DEBUG PLLEN — BORV BOREN1 BOREN0 CONFIG1 77 7:0 — CP MCLRE PWRTE WDTE FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. DS40001417C-page 76  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 8.0 DEVICE CONFIGURATION 8.1 Configuration Words Device configuration consists of Configuration Word 1 There are several Configuration Word bits that allow and Configuration Word 2 registers, code protection different oscillator and memory protection options. and device ID. These are implemented as Configuration Word 1 register at 2007h and Configuration Word 2 register at 2008h. These registers are only accessible during programming. REGISTER 8-1: CONFIG1: CONFIGURATION WORD REGISTER 1 R/P-1 R/P-1 U-1(4) R/P-1 R/P-1 R/P-1 DEBUG PLLEN — BORV BOREN1 BOREN0 bit 13 bit 8 U-1(4) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13 DEBUG: In-Circuit Debugger Mode bit 1 = In-circuit debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins 0 = In-circuit debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger bit 12 PLLEN: INTOSC PLL Enable bit 0 = INTOSC frequency is 500kHz 1 = INTOSC frequency is 16MHz (32x) bit 11 Unimplemented: Read as ‘1’ bit 10 BORV: Brown-out Reset Voltage selection bit 0 = Brown-out Reset Voltage (VBOR) set to 2.5V nominal 1 = Brown-out Reset Voltage (VBOR) set to 1.9V nominal bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1) 0x = BOR disabled (preconditioned state) 10 = BOR enabled during operation and disabled in Sleep 11 = BOR enabled bit 7 Unimplemented: Read as ‘1’ bit 6 CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 5 MCLRE: RE3/MCLR Pin Function Select bit(3) 1 = RE3/MCLR pin function is MCLR 0 = RE3/MCLR pin function is digital input, MCLR internally tied to VDD bit 4 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire program memory will be erased when the code protection is turned off. 3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. 4: MPLAB® X IDE masks unimplemented Configuration bits to ‘0’.  2010-2016 Microchip Technology Inc. DS40001417C-page 77

PIC16(L)F722A/723A REGISTER 8-1: CONFIG1: CONFIGURATION WORD REGISTER 1 (CONTINUED) bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 =RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN 110 =RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN 101 =INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 100 =INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 011 =EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN 010 =HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 001 =XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 000 =LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire program memory will be erased when the code protection is turned off. 3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. 4: MPLAB® X IDE masks unimplemented Configuration bits to ‘0’. REGISTER 8-2: CONFIG2: CONFIGURATION WORD REGISTER 2 U-1(1) U-1(1) U-1(1) U-1(1) U-1(1) U-1(1) — — — — — — bit 13 bit 8 U-1(1) U-1(1) R/P-1 R/P-1 U-1(1) U-1(1) U-1(1) U-1(1) — — VCAPEN1 VCAPEN0 — — — — bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13-6 Unimplemented: Read as ‘1’ bit 5-4 VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits For the PIC16LF722A/723A: These bits are ignored. All VCAP pin functions are disabled. For the PIC16F722A/723A: 00 = VCAP functionality is enabled on RA0 01 = VCAP functionality is enabled on RA5 10 = VCAP functionality is enabled on RA6 11 = All VCAP functions are disabled (not recommended) bit 3-0 Unimplemented: Read as ‘1’ Note 1: MPLAB® X IDE masks unimplemented Configuration bits to ‘0’. DS40001417C-page 78  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 8.2 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP™ for verification purposes. Note: The entire Flash program memory will be erased when the code protection is turned off. See the “PIC16(L)F72X Memory Programming Specification” (DS41332) for more information. 8.3 User ID Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are read- able and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are reported when using MPLAB IDE. See the “PIC16(L)F72X Memory Programming Specification” (DS41332) for more information.  2010-2016 Microchip Technology Inc. DS40001417C-page 79

PIC16(L)F722A/723A 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 8-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 8-bit binary result via successive approximation and stores the conversion result into the ADC result register (ADRES). Figure9-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. FIGURE 9-1: ADC BLOCK DIAGRAM AVDD ADREF = 0x ADREF = 11 VREF+ ADREF = 10 AN0 0000 AN1 0001 AN2 0010 AN3 0011 AN4 0100 Reserved 0101 Reserved 0110 Reserved 0111 ADC AN8 1000 GO/DONE 8 AN9 1001 AN10 1010 ADRES AN11 1011 AN12 1100 ADON AN13 1101 VSS Reserved 1110 FVREF 1111 CHS<3:0> DS40001417C-page 80  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 9.1 ADC Configuration For correct conversion, the appropriate TAD specifica- tion must be met. Refer to the A/D conversion require- When configuring and using the ADC the following ments in Section23.0 “Electrical Specifications” for functions must be considered: more information. Table9-1 gives examples of appro- • Port configuration priate ADC clock selections. • Channel selection Note: Unless using the FRC, any changes in the • ADC voltage reference selection system clock frequency will change the • ADC conversion clock source ADC clock frequency, which may • Interrupt control adversely affect the ADC result. • Results formatting 9.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section6.0 “I/O Ports” for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. 9.1.2 CHANNEL SELECTION The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section9.2 “ADC Operation” for more information. 9.1.3 ADC VOLTAGE REFERENCE The ADREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be either VDD, an external voltage source or the internal Fixed Voltage Reference. The negative voltage reference is always connected to the ground reference. See Section10.0 “Fixed Voltage Reference” for more details. 9.1.4 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: • FOSC/2 • FOSC/4 • FOSC/8 • FOSC/16 • FOSC/32 • FOSC/64 • FRC (dedicated internal oscillator) The time to complete one bit conversion is defined as TAD. One full 8-bit conversion requires 10 TAD periods as shown in Figure9-2.  2010-2016 Microchip Technology Inc. DS40001417C-page 81

PIC16(L)F722A/723A TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Clock Source Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s Fosc/8 001 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3) Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3) Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.0 s(3) Fosc/64 110 3.2 s 4.0 s 8.0 s(3) 16.0 s(3) 64.0 s(3) FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 1.6 s for VDD. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES Tcy to TAD TAD0 TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit ADRES register is loaded, GO/DONE bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input DS40001417C-page 82  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 9.1.5 INTERRUPTS 9.2.3 TERMINATING A CONVERSION The ADC module allows for the ability to generate an If a conversion must be terminated before completion, interrupt upon completion of an Analog-to-Digital the GO/DONE bit can be cleared in software. The conversion. The ADC interrupt flag is the ADIF bit in the ADRES register will be updated with the partially com- PIR1 register. The ADC interrupt enable is the ADIE bit plete Analog-to-Digital conversion sample. Incomplete in the PIE1 register. The ADIF bit must be cleared in bits will match the last bit converted. software. Note: A device Reset forces all registers to their Note1: The ADIF bit is set at the completion of Reset state. Thus, the ADC module is every conversion, regardless of whether turned off and any pending conversion is or not the ADC interrupt is enabled. terminated. 2: The ADC operates during Sleep only 9.2.4 ADC OPERATION DURING SLEEP when the FRC oscillator is selected. The ADC module can operate during Sleep. This This interrupt can be generated while the device is requires the ADC clock source to be set to the FRC operating or while in Sleep. If the device is in Sleep, the option. When the FRC clock source is selected, the interrupt will wake-up the device. Upon waking from ADC waits one additional instruction before starting the Sleep, the next instruction following the SLEEP instruc- conversion. This allows the SLEEP instruction to be tion is always executed. If the user is attempting to executed, which can reduce system noise during the wake-up from Sleep and resume in-line code execu- conversion. If the ADC interrupt is enabled, the device tion, the GIE and PEIE bits of the INTCON register will wake-up from Sleep when the conversion must be disabled. If the GIE and PEIE bits of the completes. If the ADC interrupt is disabled, the ADC INTCON register are enabled, execution will switch to module is turned off after the conversion completes, the Interrupt Service Routine. although the ADON bit remains set. Please refer to Section9.1.5 “Interrupts” for more When the ADC clock source is something other than information. FRC, a SLEEP instruction causes the present conver- sion to be aborted and the ADC module is turned off, 9.2 ADC Operation although the ADON bit remains set. 9.2.1 STARTING A CONVERSION 9.2.5 SPECIAL EVENT TRIGGER To enable the ADC module, the ADON bit of the The Special Event Trigger of the CCP module allows ADCON0 register must be set to a ‘1’. Setting the GO/ periodic ADC measurements without software inter- DONE bit of the ADCON0 register to a ‘1’ will start the vention. When this trigger occurs, the GO/DONE bit is Analog-to-Digital conversion. set by hardware and the Timer1 counter resets to zero. Note: The GO/DONE bit should not be set in the Using the Special Event Trigger does not assure proper same instruction that turns on the ADC. ADC timing. It is the user’s responsibility to ensure that Refer to Section9.2.6 “A/D Conversion the ADC timing requirements are met. Procedure”. Refer to Section15.0 “Capture/Compare/PWM (CCP) Module” for more information. 9.2.2 COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF Interrupt Flag bit • Update the ADRES register with new conversion result  2010-2016 Microchip Technology Inc. DS40001417C-page 83

PIC16(L)F722A/723A 9.2.6 A/D CONVERSION PROCEDURE EXAMPLE 9-1: A/D CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd reference, Frc clock ;and AN0 input. 1. Configure Port: ; • Disable pin output driver (Refer to the TRIS ;Conversion start & polling for completion register) ; are included. • Configure pin as analog (Refer to the ANSEL ; register) BANKSEL ADCON1 ; MOVLW B’01110000’;ADC Frc clock, 2. Configure the ADC module: ;VDD reference • Select ADC conversion clock MOVWF ADCON1 ; • Configure voltage reference BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input • Select ADC input channel BANKSEL ANSELA ; • Turn on ADC module BSF ANSELA,0 ;Set RA0 to analog 3. Configure ADC interrupt (optional): BANKSEL ADCON0 ; • Clear ADC interrupt flag MOVLW B’00000001’;AN0, On MOVWF ADCON0 ; • Enable ADC interrupt CALL SampleTime ;Acquisiton delay • Enable peripheral interrupt BSF ADCON0,GO ;Start conversion • Enable global interrupt(1) BTFSC ADCON0,GO ;Is conversion done? 4. Wait the required acquisition time(2). GOTO $-1 ;No, test again BANKSEL ADRES ; 5. Start conversion by setting the GO/DONE bit. MOVF ADRES,W ;Read result 6. Wait for ADC conversion to complete by one of MOVWF RESULT ;store in GPR space the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result. 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section9.3 “A/D Acquisition Requirements”. DS40001417C-page 84  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = AN0 0001 = AN1 0010 = AN2 0011 = AN3 0100 = AN4 0101 = Reserved 0110 = Reserved 0111 = Reserved 1000 = AN8 1001 = AN9 1010 = AN10 1011 = AN11 1100 = AN12 1101 = AN13 1110 = Reserved 1111 = Fixed Voltage Reference (FVREF) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current  2010-2016 Microchip Technology Inc. DS40001417C-page 85

PIC16(L)F722A/723A REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from a dedicated RC oscillator) bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 ADREF<1:0>: Voltage Reference Configuration bits 0x = VREF is connected to VDD 10 = VREF is connected to external VREF (RA3/AN3) 11 = VREF is connected to internal Fixed Voltage Reference REGISTER 9-3: ADRES: ADC RESULT REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: ADC Result Register bits 8-bit conversion result. DS40001417C-page 86  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 9.3 A/D Acquisition Requirements impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected For the ADC to meet its specified accuracy, the charge (or changed), an A/D acquisition must be done before holding capacitor (CHOLD) must be allowed to fully the conversion can be started. To calculate the mini- charge to the input channel voltage level. The Analog mum acquisition time, Equation9-1 may be used. This Input model is shown in Figure9-3. The source imped- equation assumes that 1/2 LSb error is used (256 steps ance (RS) and the internal sampling switch (RSS) for the ADC). The 1/2 LSb error is the maximum error impedance directly affect the time required to charge allowed for the ADC to meet its specified resolution. the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure9-3. The maximum recommended imped- ance for analog sources is 10 k. As the source EQUATION 9-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– ------n----+----1------------ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb 2 –1 –TC  ---------- RC VAPPLIED1–e  = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– ------n---+-----1------------ ;combining [1] and [2]   2  –1 Note: Where n = number of bits of the ADC. Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/511) = –10pF1k+7k+10k ln(0.001957) = 1.12µs Therefore: TACQ = 2µs+1.12µs+50°C- 25°C0.05µs/°C = 4.42µs Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification.  2010-2016 Microchip Technology Inc. DS40001417C-page 87

PIC16(L)F722A/723A FIGURE 9-3: ANALOG INPUT MODEL VDD Sampling Switch VT  0.6V Rs ANx RIC  1k SS Rss VA C5 PpIFN VT  0.6V I LEAKAGE(1) CHOLD = 10 pF VSS/VREF- 6V 5V RSS Legend: CHOLD = Sample/Hold Capacitance VDD4V 3V CPIN = Input Capacitance 2V I LEAKAGE = Leakage current at the pin due to various junctions 5 6 7 891011 RIC = Interconnect Resistance Sampling Switch RSS = Resistance of Sampling Switch (k) SS = Sampling Switch VT = Threshold Voltage Note1: Refer to Section23.0 “Electrical Specifications”. FIGURE 9-4: ADC TRANSFER FUNCTION Full-Scale Range FFh FEh FDh de FCh 1 LSB ideal o C FBh ut p ut Full-Scale O C 04h Transition D A 03h 02h 01h 00h Analog Input Voltage 1 LSB ideal VSS Zero-Scale VREF Transition DS40001417C-page 88  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/ ADON 85 DONE ADCON1 — ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 86 ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 44 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 53 ADRES A/D Result Register Byte 86 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 115 FVRCON FVRRDY FVREN — — — — ADFVR1 ADFVR0 90 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 36 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 37 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 39 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 43 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 52 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for ADC module.  2010-2016 Microchip Technology Inc. DS40001417C-page 89

PIC16(L)F722A/723A 10.0 FIXED VOLTAGE REFERENCE This device contains an internal voltage regulator. To provide a reference for the regulator, a band gap reference is provided. This band gap is also user accessible via an A/D converter channel. User level band gap functions are controlled by the FVRCON register, which is shown in Register10-1. REGISTER 10-1: FVRCON: FIXED VOLTAGE REFERENCE REGISTER R-q R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 FVRRDY FVREN — — — — ADFVR1 ADFVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown q = Value depends on condition bit 7 FVRRDY: Fixed Voltage Reference Ready Flag bit 0 = Fixed Voltage Reference output is not active or stable 1 = Fixed Voltage Reference output is ready for use bit 6 FVREN(1): Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled bit 5-2 Unimplemented: Read as ‘0’ bit 1-0 ADFVR<1:0>: A/D Converter Fixed Voltage Reference Selection bits 00 = A/D Converter Fixed Voltage Reference Peripheral output is off. 01 = A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(1) 11 = A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(1) Note1: Fixed Voltage Reference output cannot exceed VDD. DS40001417C-page 90  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 11.0 TIMER0 MODULE When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The Timer0 module is an 8-bit timer/counter with the following features: Note: The value written to the TMR0 register can be adjusted, in order to account for • 8-bit timer/counter register (TMR0) the two instruction cycle delay when • 8-bit prescaler (shared with Watchdog Timer) TMR0 is written. • Programmable internal or external clock source • Programmable external clock edge selection 11.1.2 8-BIT COUNTER MODE • Interrupt on overflow In 8-Bit Counter mode, the Timer0 module will increment • TMR0 can be used to gate Timer1 on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSOSC) signal. Figure11-1 is a block diagram of the Timer0 module. 8-Bit Counter mode using the T0CKI pin is selected by 11.1 Timer0 Operation setting the T0CS bit in the OPTION register to ‘1’ and resetting the T0XCS bit in the CPSCON0 register to ‘0’. The Timer0 module can be used as either an 8-bit timer 8-Bit Counter Mode using the Capacitive Sensing or an 8-bit counter. Oscillator (CPSOSC) signal is selected by setting the T0CS bit in the OPTION register to ‘1’ and setting the 11.1.1 8-BIT TIMER MODE T0XCS bit in the CPSCON0 register to ‘1’. The Timer0 module will increment every instruction The rising or falling transition of the incrementing edge cycle, if used without a prescaler. 8-Bit Timer mode is for either input source is determined by the T0SE bit in selected by clearing the T0CS bit of the OPTION the OPTION register. register. FIGURE 11-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER FOSC/4 Data Bus T0XCS 0 8 T0CKI 1 0 1 2S YTNCCY TMR0 0 Set Flag bit T0IF Cap. Sensing 0 Oscillator 1 T0SE T0CS 8-Bit on Overflow Prescaler PSA Overflow to Timer1 1 T1GSS=11 TMR1GE PSA WDTE 8 Low-Power PS<2:0> WDT OSC 1 WDT Time-out Divide by 0 512 PSA  2010-2016 Microchip Technology Inc. DS40001417C-page 91

PIC16(L)F722A/723A 11.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are eight prescaler options for the Timer0 mod- ule ranging from 1:2 to 1:256. The pres ca le values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. Note: When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. 11.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from PH to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit can only be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 11.1.5 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section23.0 “Electrical Specifications”. DS40001417C-page 92  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A REGISTER 11-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull ups are disabled 0 = PORTB pull ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin or CPSOSC signal 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits BIT VALUE TMR0 RATE WDT RATE 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 TABLE 11-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CPSCON0 CPSON — — — CPS- CPSRNG0 CPSOUT T0XCS 112 RNG1 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 36 OPTION_RE RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 93 G TMR0 Timer0 Module Register — TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 43 Legend: – = Un implemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.  2010-2016 Microchip Technology Inc. DS40001417C-page 93

PIC16(L)F722A/723A 12.0 TIMER1 MODULE WITH GATE • Selectable Gate Source Polarity CONTROL • Gate Toggle Mode • Gate Single-pulse Mode The Timer1 module is a 16-bit timer/counter with the • Gate Value Status following features: • Gate Event Interrupt • 16-bit timer/counter register pair (TMR1H:TMR1L) Figure12-1 is a block diagram of the Timer1 module. • Programmable internal or external clock source • 3-bit prescaler • Dedicated LP oscillator circuit • Synchronous or asynchronous operation • Multiple Timer1 gate (count enable) sources • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with CCP) FIGURE 12-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 T1GSPM From Timer0 01 T1G_IN 0 Data Bus Overflow 0 T1GVAL D Q FrMomat cThim PeRr22 10 D Q 1 SAicnqg.l eC Ponutlrsoel 1 Q1 EN T1GRDCON From WDT 11 Overflow CK Q T1GGO/DONE Interrupt Set TMR1ON R det TMR1GIF T1GPOL T1GTM TMR1GE Set flag bit TMR1ON TMR1IF on Overflow TMR1(2) EN Synchronized TMR1H TMR1L T1CLK 0 Clock Input Q D 1 TMR1CS<1:0> T1SYNC T1OSO/T1CKI OUT Cap. Sensing 11 T1OSC Oscillator Prescaler Synchronize(3) 1 1, 2, 4, 8 det T1OSI 10 EN 2 0 FOSC T1CKPS<1:0> Internal 01 T1OSCEN Clock IFnOteSrCn/a2l Sleep Input FOSC/4 Clock Internal 00 (1) Clock T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. DS40001417C-page 94  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 12.1 Timer1 Operation 12.2 Clock Source Selection The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> and T1OSCEN bits of the T1CON which is accessed through the TMR1H:TMR1L register register are used to select the clock source for Timer1. pair. Writes to TMR1H or TMR1L directly update the Table12-2 displays the clock source selections. counter. 12.2.1 INTERNAL CLOCK SOURCE When used with an internal clock source, the module is a timer and increments on every instruction cycle. When the internal clock source is selected the When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples can be used as either a timer or counter and incre- of FISC as determined by the Timer1 prescaler. ments on every selected edge of the external source. 12.2.2 EXTERNAL CLOCK SOURCE Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, When the external clock source is selected, the Timer1 respectively. Table12-1 displays the Timer1 enable module may work as a timer or a counter. selections. When enabled to count, Timer1 is increment ed on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these TABLE 12-1: TIMER1 ENABLE external clock sources can be synchronized to the SELECTIONS microcontroller system clock or they can run Timer1 asynchronously. TMR1ON TMR1GE Operation When used as a timer with a clock oscillator, an 0 0 Off external 32.768kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. 0 1 Off 1 0 Always On Note: In Counter mode, a falling edge must be registered by the counter prior to the first 1 1 Count Enabled incrementing rising edge after any one or more of the following conditions: •Timer1 enabled after POR •Write to TMR1H or TMR1L •Timer1 is disabled •Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON= 1) when T1CKI is low. TABLE 12-2: CLOCK SOURCE SELECTIONS TMR1CS1 TMR1CS0 T1OSCEN Clock Source 0 1 x System Clock (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 1 x Capacitive Sensing Oscillator 1 0 0 External Clocking on T1CKI Pin 1 0 1 Oscillator Circuit on T1OSI/T1OSO Pins  2010-2016 Microchip Technology Inc. DS40001417C-page 95

PIC16(L)F722A/723A 12.3 Timer1 Prescaler 12.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER Timer1 has four prescaler options allowing 1, 2, 4 or 8 MODE divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The Reading TMR1H or TMR1L while the timer is running prescale counter is not directly readable or writable; from an external asynchronous clock will ensure a valid however, the prescaler counter is cleared upon a write to read (taken care of in hardware). However, the user TMR1H or TMR1L. should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the 12.4 Timer1 Oscillator timer may overflow between the reads. For writes, it is recommended that the user simply stop A dedicated low-power 32.768kHz oscillator circuit is the timer and write the desired values. A write built-in between pins T1OSI (input) and T1OSO contention may occur by writing to the timer registers, (amplifier output). This internal circuit is to be used in while the register is incrementing. This may produce an conjunction with an external 32.768kHz crystal. unpredictable value in the TMR1H:TMR1L register pair. The oscillator circuit is enabled by setting the T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. 12.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section12.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. DS40001417C-page 96  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 12.6 Timer1 Gate 12.6.2.1 T1G Pin Gate Operation Timer1 can be configured to count freely or the count The T1G pin is one source for Timer1 gate control. It can be enabled and disabled using Timer1 gate can be used to supply an external source to the Timer1 circuitry. This is also referred to as Timer1 Gate Count gate circuitry. Enable. 12.6.2.2 Timer0 Overflow Gate Operation Timer1 gate can also be driven by multiple selectable When Timer0 increments from FFh to 00h, a low-to- sources. high pulse will automatically be generated and 12.6.1 TIMER1 GATE COUNT ENABLE internally supplied to the Timer1 gate circuitry. The Timer1 gate is enabled by setting the TMR1GE bit 12.6.2.3 Timer2 Match Gate Operation of the T1GCON register. The polarity of the Timer1 gate The TMR2 register will increment until it matches the is configured using the T1GPOL bit of the T1GCON value in the PR2 register. On the very next increment register. cycle, TMR2 will be reset to 00h. When this Reset When Timer1 Gate (T1G) input is active, Timer1 will occurs, a low-to-high pulse will automatically be increment on the rising edge of the Timer1 clock generated and internally supplied to the Timer1 gate source. When Timer1 gate input is inactive, no circuitry. incrementing will occur and Timer1 will hold the current count. See Figure12-4 for timing details. 12.6.2.4 Watchdog Overflow Gate Operation The Watchdog Timer oscillator, prescaler and counter TABLE 12-3: TIMER1 GATE ENABLE will be automatically turned on when TMR1GE=1 and SELECTIONS T1GSS selects the WDT as a gate source for Timer1 (T1GSS=11). TMR1ON does not factor into the T1CLK T1GPOL T1G Timer1 Operation oscillator, prescaler and counter enable. See Table.  0 0 Counts The PSA and PS bits of the OPTION register still  0 1 Holds Count control what time-out interval is selected. Changing the  1 0 Holds Count prescaler during operation may result in a spurious capture.  1 1 Counts Enabling the Watchdog Timer oscillator does not 12.6.2 TIMER1 GATE SOURCE automatically enable a Watchdog Reset or Wake-up SELECTION from Sleep upon counter overflow. The Timer1 gate source can be selected from one of Note: When using the WDT as a gate source for four different sources. Source selection is controlled by Timer1, operations that clear the Watchdog the T1GSS bits of the T1GCON register. The polarity Timer (CLRWDT, SLEEP instructions) will for each available source is also selectable. Polarity affect the time interval being measured for selection is controlled by the T1GPOL bit of the capacitive sensing. This includes waking T1GCON register. from Sleep. All other interrupts that might wake the device from Sleep should be TABLE 12-4: TIMER1 GATE SOURCES disabled to prevent them from disturbing the measurement period. T1GSS Timer1 Gate Source As the gate signal coming from the WDT counter will 00 Timer1 Gate Pin generate different pulse widths depending on if the 01 Overflow of Timer0 WDT is enabled, when the CLRWDT instruction is (TMR0 increments from FFh to 00h) executed, and so on, Toggle mode must be used. A 10 Timer2 match PR2 specific sequence is required to put the device into the (TMR2 increments to match PR2) correct state to capture the next WDT counter interval. 11 Count Enabled by WDT Overflow (Watchdog Time-out interval expired)  2010-2016 Microchip Technology Inc. DS40001417C-page 97

PIC16(L)F722A/723A TABLE 12-2: WDT/TIMER1 GATE INTERACTION TMR1GE = 1 WDT Oscillator WDT Available for WDTE and WDT Reset Wake-up Enable T1G Source T1GSS = 11 1 N Y Y Y N 1 Y Y Y Y Y 0 Y Y N N Y 0 N N N N N 12.6.3 TIMER1 GATE TOGGLE MODE 12.6.4 TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Toggle mode is enabled, it is possi- ble to measure the full-cycle length of a Timer1 gate When Timer1 Gate Single-Pulse mode is enabled, it is signal, as opposed to the duration of a single level possible to capture a single pulse gate event. Timer1 pulse. Gate Single-Pulse mode is first enabled by setting the The Timer1 gate source is routed through a flip-flop that T1GSPM bit in the T1GCON register. Next, the changes state on every incrementing edge of the sig- T1GGO/DONE bit in the T1GCON register must be set. nal. See Figure12-5 for timing details. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the Timer1 Gate Toggle mode is enabled by setting the pulse, the T1GGO/DONE bit will automatically be T1GTM bit of the T1GCON register. When the T1GTM cleared. No other gate events will be allowed to bit is cleared, the flip-flop is cleared and held clear. This increment Timer1 until the T1GGO/DONE bit is once is necessary in order to control which edge is again set in software. measured. Clearing the T1GSPM bit of the T1GCON register will Note: Enabling Toggle mode at the same time also clear the T1GGO/DONE bit. See Figure12-6 for as changing the gate polarity may result in timing details. indeterminate operation. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure12-7 for timing details. 12.6.5 TIMER1 GATE VALUE STATUS When Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). 12.6.6 TIMER1 GATE EVENT INTERRUPT When Timer1 gate event interrupt is enabled, it is pos- sible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). DS40001417C-page 98  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 12.7 Timer1 Interrupt The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON The Timer1 register pair (TMR1H:TMR1L) increments register is set, the device will call the Interrupt Service to FFFFh and rolls over to 0000h. When Timer1 rolls Routine (0004h). over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set 12.9 CCP Capture/Compare Time Base these bits: The CCP module uses the TMR1H:TMR1L register • TMR1ON bit of the T1CON register pair as the time base when operating in Capture or • TMR1IE bit of the PIE1 register Compare mode. • PEIE bit of the INTCON register In Capture mode, the value in the TMR1H:TMR1L • GIE bit of the INTCON register register pair is copied into the CCPR1H:CCPR1L The interrupt is cleared by clearing the TMR1IF bit in register pair on a configured event. the Interrupt Service Routine. In Compare mode, an event is triggered when the value Note: The TMR1H:TMR1L register pair and the CCPR1H:CCPR1L register pair matches the value in TMR1IF bit should be cleared before the TMR1H:TMR1L register pair. This event can be a enabling interrupts. Special Event Trigger. For more information, see Section15.0 “Capture/ 12.8 Timer1 Operation During Sleep Compare/PWM (CCP) Module”. Timer1 can only operate during Sleep when setup in 12.10 CCP Special Event Trigger Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the When the CCP is configured to trigger a special event, counter. To set up the timer to wake the device: the trigger will clear the TMR1H:TMR1L register pair. • TMR1ON bit of the T1CON register must be set This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a • TMR1IE bit of the PIE1 register must be set CCP interrupt. • PEIE bit of the INTCON register must be set In this mode of operation, the CCPR1H:CCPR1L • T1SYNC bit of the T1CON register must be set register pair becomes the period register for Timer1. • TMR1CS bits of the T1CON register must be configured Timer1 should be synchronized to the FOSC/4 to utilize the Special Event Trigger. Asynchronous operation of • T1OSCEN bit of the T1CON register must be Timer1 can cause a Special Event Trigger to be configured missed. • TMR1GIE bit of the T1GCON register must be configured In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section9.2.5 “Special Event Trigger”. FIGURE 12-3: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2010-2016 Microchip Technology Inc. DS40001417C-page 99

PIC16(L)F722A/723A FIGURE 12-4: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N N + 1 N + 2 N + 3 N + 4 FIGURE 12-5: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 DS40001417C-page 100  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 12-6: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N N + 1 N + 2 Cleared by TMR1GIF Cleared by software Set by hardware on software falling edge of T1GVAL  2010-2016 Microchip Technology Inc. DS40001417C-page 101

PIC16(L)F722A/723A FIGURE 12-7: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N N + 1 N + 2 N + 3 N + 4 Set by hardware on Cleared by TMR1GIF Cleared by software falling edge of T1GVAL software DS40001417C-page 102  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 12.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register12-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 =Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC) 10 =Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 =Timer1 clock source is system clock (FOSC) 00 =Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS<1:0> = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMR1CS<1:0> = 0X This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 (Clears Timer1 gate flip-flop)  2010-2016 Microchip Technology Inc. DS40001417C-page 103

PIC16(L)F722A/723A 12.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register12-2, is used to control Timer1 gate. REGISTER 12-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0 TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 DONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled. 0 = Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single Pulse Mode bit 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 gate pin 01 = Timer0 Overflow output 10 = TMR2 Match PR2 output 11 = Watchdog Timer scaler overflow Watchdog Timer oscillator is turned on if TMR1GE = 1, regardless of the state of TMR1ON DS40001417C-page 104  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 53 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 115 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 115 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 36 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 37 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 39 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 99 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 99 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 52 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 62 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 103 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 104 DONE Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.  2010-2016 Microchip Technology Inc. DS40001417C-page 105

PIC16(L)F722A/723A 13.0 TIMER2 MODULE The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to The Timer2 module is an 8-bit timer with the following 00h and the PR2 register is set to FFh. features: Timer2 is turned on by setting the TMR2ON bit in the • 8-bit timer register (TMR2) T2CON register to a ‘1’. Timer2 is turned off by clearing • 8-bit period register (PR2) the TMR2ON bit to a ‘0’. • Interrupt on TMR2 match with PR2 The Timer2 prescaler is controlled by the T2CKPS bits • Software programmable prescaler (1:1, 1:4, 1:16) in the T2CON register. The Timer2 postscaler is • Software programmable postscaler (1:1 to 1:16) controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared See Figure13-1 for a block diagram of Timer2. when: 13.1 Timer2 Operation • A write to TMR2 occurs. • A write to T2CON occurs. The clock input to the Timer2 module is the system • Any device Reset occurs (Power-on Reset, MCLR instruction clock (FOSC/4). The clock is fed into the Reset, Watchdog Timer Reset, or Brown-out Timer2 prescaler, which has prescale options of 1:1, Reset). 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. Note: TMR2 is not cleared when T2CON is written. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: • TMR2 is reset to 00h on the next increment cycle. • The Timer2 postscaler is incremented. The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. FIGURE 13-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 bit TMR2IF Output Prescaler Reset FOSC/4 TMR2 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T2CKPS<1:0> PR2 4 TOUTPS<3:0> DS40001417C-page 106  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is On 0 = Timer2 is Off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 36 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 37 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 39 PR2 Timer2 Module Period Register 106 TMR2 Holding Register for the 8-bit TMR2 Register 106 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 107 Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.  2010-2016 Microchip Technology Inc. DS40001417C-page 107

PIC16(L)F722A/723A 14.0 CAPACITIVE SENSING sensing module. The capacitive sensing module MODULE requires software and at least one timer resource to determine the change in frequency. Key features of this The capacitive sensing module allows for an interaction module include: with an end user without a mechanical interface. In a • Analog MUX for monitoring multiple inputs typical application, the capacitive sensing module is • Capacitive sensing oscillator attached to a pad on a printed circuit board (PCB), which • Multiple timer resources is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive • Software control load is added, causing a frequency shift in the capacitive • Operation during Sleep FIGURE 14-1: CAPACITIVE SENSING BLOCK DIAGRAM Timer0 Module Set T0CS T0XCS T0IF FOSC/4 0 Overflow T0CKI 0 TMR0 1 1 CPSCH<2:0> CPSON(1) Timer1 Module CPS0 CPSON T1CS<1:0> CPS1 CPS2 FOSC Capacitive CPS3 Sensing FOSC/4 CPSCLK CPS4 Oscillator T1OSC/ EN TMR1H:TMR1L CPS5 CPSOSC T1CKI CPSOUT CPS6 CPS7 CPSRNG<1:0> T1GSEL<1:0> T1G Timer1 Gate Control Logic Watchdog Timer Module Timer2 Module WDT Event Overflow Set TMR2 Postscaler LP WDT WDT Overflow TMR2IF OSC Scaler PS<2:0> Note 1: If CPSON=0, disabling capacitive sensing, no channel is selected. DS40001417C-page 108  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 14.1 Analog MUX 14.4.1 TIMER0 The capacitive sensing module can monitor up to 8 To select Timer0 as the timer resource for the capacitive inputs. The capacitive sensing inputs are defined as sensing module: CPS<7:0>. To determine if a frequency change has • Set the T0XCS bit of the CPSCON0 register occurred the user must: • Clear the T0CS bit of the OPTION register • Select the appropriate CPS pin by setting the When Timer0 is chosen as the timer resource, the CPSCH<2:0> bits of the CPSCON1 register capacitive sensing oscillator will be the clock source for • Set the corresponding ANSEL bit Timer0. Refer to Section11.0 “Timer0 Module” for • Set the corresponding TRIS bit additional information. • Run the software algorithm 14.4.2 TIMER1 Selection of the CPSx pin while the module is enabled To select Timer1 as the timer resource for the will cause the capacitive sensing oscillator to be on the capacitive sensing module, set the TMR1CS<1:0> of CPSx pin. Failure to set the corresponding ANSEL and the T1CON register to ‘11’. When Timer1 is chosen as TRIS bits can cause the capacitive sensing oscillator to the timer resource, the capacitive sensing oscillator will stop, leading to false frequency readings. be the clock source for Timer1. Because the Timer1 module has a gate control, developing a time base for 14.2 Capacitive Sensing Oscillator the frequency measurement can be simplified using The capacitive sensing oscillator consists of a constant either: current source and a constant current sink, to produce • The Timer0 overflow flag a triangle waveform. The CPSOUT bit of the • The Timer2 overflow flag CPSCON0 register shows the status of the capacitive • The WDT overflow flag sensing oscillator, whether it is a sinking or sourcing current. The oscillator is designed to drive a capacitive It is recommended that one of these flags, in conjunc- load (single PCB pad) and at the same time, be a clock tion with the toggle mode of the Timer1 gate, is used to source to either Timer0 or Timer1. The oscillator has develop the fixed-time base required by the software three different current settings as defined by CPS- portion of the capacitive sensing module. Refer to RNG<1:0> of the CPSCON0 register. The different cur- Section12.0 “Timer1 Module with Gate Control” for rent settings for the oscillator serve two purposes: additional information. • Maximize the number of counts in a timer for a TABLE 14-1: TIMER1 ENABLE FUNCTION fixed-time base • Maximize the count differential in the timer during TMR1ON TMR1GE Timer1 Operation a change in frequency 0 0 Off 0 1 Off 14.3 Timer Resources 1 0 On To measure the change in frequency of the capacitive 1 1 Count Enabled by input sensing oscillator, a fixed-time base is required. For the period of the fixed-time base, the capacitive sensing oscillator is used to clock either Timer0 or Timer1. The frequency of the capacitive sensing oscillator is equal to the number of counts in the timer divided by the period of the fixed-time base. 14.4 Fixed-Time Base To measure the frequency of the capacitive sensing oscillator, a fixed-time base is required. Any timer resource or software loop can be used to establish the fixed-time base. It is up to the end user to determine the method in which the fixed-time base is generated. Note: The fixed-time base can not be generated by the timer resource the capacitive sensing oscillator is clocking.  2010-2016 Microchip Technology Inc. DS40001417C-page 109

PIC16(L)F722A/723A 14.5 Software Control 14.5.3 FREQUENCY THRESHOLD The software portion of the capacitive sensing module The frequency threshold should be placed midway is required to determine the change in frequency of the between the value of nominal frequency and the capacitive sensing oscillator. This is accomplished by reduced frequency of the capacitive sensing oscillator. the following: Refer to Application Note AN1103, Software Handling for Capacitive Sensing (DS01103) for more detailed • Setting a fixed-time base to acquire counts on information the software required for capacitive Timer0 or Timer1 sensing module. • Establishing the nominal frequency for the Note: For more information on general capacitive capacitive sensing oscillator sensing refer to Application Notes: • Establishing the reduced frequency for the capacitive sensing oscillator due to an additional •AN1101, Introduction to Capacitive capacitive load Sensing (DS01101) • Set the frequency threshold •AN1102, Layout and Physical Design Guidelines for Capacitive Sensing 14.5.1 NOMINAL FREQUENCY (DS01102) (NO CAPACITIVE LOAD) To determine the nominal frequency of the capacitive sensing oscillator: • Remove any extra capacitive load on the selected CPSx pin • At the start of the fixed-time base, clear the timer resource • At the end of the fixed-time base, save the value in the timer resource The value of the timer resource is the number of oscillations of the capacitive sensing oscillator for the given time base. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed-time base. 14.5.2 REDUCED FREQUENCY (ADDITIONAL CAPACITIVE LOAD) The extra capacitive load will cause the frequency of the capacitive sensing oscillator to decrease. To determine the reduced frequency of the capacitive sensing oscillator: • Add a typical capacitive load on the selected CPSx pin • Use the same fixed-time base as the nominal frequency measurement • At the start of the fixed-time base, clear the timer resource • At the end of the fixed-time base, save the value in the timer resource The value of the timer resource is the number of oscillations of the capacitive sensing oscillator with an additional capacitive load. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed- time base. This frequency should be less than the value obtained during the nominal frequency measurement. DS40001417C-page 110  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 14.6 Operation During Sleep The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts. One way to acquire the Timer1 counts while in Sleep is to have Timer1 gated with the overflow of the Watchdog Timer. This can be accomplished using the following steps: 1. Configure the Watchdog Time-out overflow as the Timer1’s gate source T1GSS<1:0> = 11. 2. Set Timer1 gate to toggle mode by setting the T1GTM bit of the T1GCON register. 3. Set the TMR1GE bit of the T1GCON register. 4. Set TMR1ON bit of the T1CON register. 5. Enable capacitive sensing module with the appropriate current settings and pin selection. 6. Clear Timer1. 7. Put the part to Sleep. 8. On the first WDT overflow, the capacitive sens- ing oscillator will begin to increment Timer1. Then put the part to Sleep. 9. On the second WDT overflow Timer1 will stop incrementing. Then run the software routine to determine if a frequency change has occurred. Refer to Section12.0 “Timer1 Module with Gate Control” for additional information. Note1: When using the WDT to set the interval on Timer1, any other source that wakes the part up early will cause the WDT overflow to be delayed, affecting the value captured by Timer1. 2: Timer0 does not operate when in Sleep, and therefore cannot be used for capacitive sense measurements in Sleep.  2010-2016 Microchip Technology Inc. DS40001417C-page 111

PIC16(L)F722A/723A REGISTER 14-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R-0 R/W-0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CPSON: Capacitive Sensing Module Enable bit 1 = Capacitive sensing module is operating 0 = Capacitive sensing module is shut off and consumes no operating current bit 6-4 Unimplemented: Read as ‘0’ bit 3-2 CPSRNG<1:0>: Capacitive Sensing Oscillator Range bits 00 = Oscillator is Off. 01 = Oscillator is in low range. Charge/discharge current is nominally 0.1µA. 10 = Oscillator is in medium range. Charge/discharge current is nominally 1.2µA. 11 = Oscillator is in high range. Charge/discharge current is nominally 18µA. bit 1 CPSOUT: Capacitive Sensing Oscillator Status bit 1 = Oscillator is sourcing current (Current flowing out the pin) 0 = Oscillator is sinking current (Current flowing into the pin) bit 0 T0XCS: Timer0 External Clock Source Select bit If T0CS = 1 The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0: 1 = Timer0 Clock Source is the capacitive sensing oscillator 0 = Timer0 Clock Source is the T0CKI pin If T0CS = 0 Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4. DS40001417C-page 112  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A REGISTER 14-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CPSCH2 CPSCH1 CPSCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 CPSCH<2:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected. If CPSON = 1: 000 = channel 0, (CPS0) 001 = channel 1, (CPS1) 010 = channel 2, (CPS2) 011 = channel 3, (CPS3) 100 = channel 4, (CPS4) 101 = channel 5, (CPS5) 110 = channel 6, (CPS6) 111 = channel 7, (CPS7) TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 44 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 53 OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 19 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 37 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 39 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 103 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 107 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 43 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 52 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the capacitive sensing module.  2010-2016 Microchip Technology Inc. DS40001417C-page 113

PIC16(L)F722A/723A 15.0 CAPTURE/COMPARE/PWM TABLE 15-1: CCP MODE – TIMER (CCP) MODULE RESOURCES REQUIRED CCP Mode Timer Resource The Capture/Compare/PWM module is a peripheral which allows the user to time and control different Capture Timer1 events. In Capture mode, the peripheral allows the Compare Timer1 timing of the duration of an event. The Compare mode PWM Timer2 allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. The timer resources used by the module are shown in Table15-1. Additional information on CCP modules is available in the Application Note AN594, Using the CCP Modules (DS00594). TABLE 15-2: INTERACTION OF TWO CCP MODULES CCP1 Mode CCP2 Mode Interaction Capture Capture Same TMR1 time base Capture Compare Same TMR1 time base(1, 2) Compare Compare Same TMR1 time base(1, 2) PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt). The rising edges will be aligned. PWM Capture None PWM Compare None Note 1: If CCP2 is configured as a Special Event Trigger, CCP1 will clear Timer1, affecting the value captured on the CCP2 pin. 2: If CCP1 is in Capture mode and CCP2 is configured as a Special Event Trigger, CCP2 will clear Timer1, affecting the value captured on the CCP1 pin. Note: CCPRx and CCPx throughout this document refer to CCPR1 or CCPR2 and CCP1 or CCP2, respectively. DS40001417C-page 114  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A REGISTER 15-1: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCP Mode Select bits 0000 = Capture/Compare/PWM Off (resets CCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCPxIF bit of the PIRx register is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit of the PIRx register is set) 1001 = Compare mode, clear output on match (CCPxIF bit of the PIRx register is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set of the PIRx register, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit of the PIRx register is set, TMR1 is reset and A/D conversion(1) is started if the ADC module is enabled. CCPx pin is unaffected.) 11xx = PWM mode. Note1: A/D conversion start feature is available only on CCP2.  2010-2016 Microchip Technology Inc. DS40001417C-page 115

PIC16(L)F722A/723A 15.1 Capture Mode 15.1.3 SOFTWARE INTERRUPT In Capture mode, CCPRxH:CCPRxL captures the When the Capture mode is changed, a false capture 16-bit value of the TMR1 register when an event occurs interrupt may be generated. The user should keep the on pin CCPx. An event is defined as one of the CCPxIE interrupt enable bit of the PIEx register clear to following and is configured by the CCPxM<3:0> bits of avoid false interrupts. Additionally, the user should the CCPxCON register: clear the CCPxIF interrupt flag bit of the PIRx register following any change in operating mode. • Every falling edge Note: Clocking Timer1 from the system clock • Every rising edge (FOSC) should not be used in Capture • Every 4th rising edge mode. In order for Capture mode to • Every 16th rising edge recognize the trigger event on the CCPx When a capture is made, the Interrupt Request Flag bit pin, Timer1 must be clocked from the CCPxIF of the PIRx register is set. The interrupt flag instruction clock (FOSC/4) or from an must be cleared in software. If another capture occurs external clock source. before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new 15.1.4 CCP PRESCALER captured value (refer to Figure15-1). There are four prescaler settings specified by the CCPxM<3:0> bits of the CCPxCON register. Whenever 15.1.1 CCPx PIN CONFIGURATION the CCP module is turned off, or the CCP module is not In Capture mode, the CCPx pin should be configured in Capture mode, the prescaler counter is cleared. Any as an input by setting the associated TRIS control bit. Reset will clear the prescaler counter. Either RC1 or RB3 can be selected as the CCP2 pin. Switching from one capture prescaler to another does not Refer to Section6.1 “Alternate Pin Function” for clear the prescaler and may generate a false interrupt. To more information. avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the Note: If the CCPx pin is configured as an output, prescaler (refer to Example15-1). a write to the port can cause a capture condition. EXAMPLE 15-1: CHANGING BETWEEN CAPTURE PRESCALERS FIGURE 15-1: CAPTURE MODE OPERATION BLOCK BANKSELCCP1CON ;Set Bank bits to point DIAGRAM ;to CCP1CON CLRF CCP1CON ;Turn CCP module off Set Flag bit CCPxIF MOVLW NEW_CAPT_PS;Load the W reg with (PIRx register) Prescaler ; the new prescaler  1, 4, 16 ; move value and CCP ON CCPx CCPRxH CCPRxL MOVWF CCP1CON ;Load CCP1CON with this ; value and Capture Edge Detect Enable 15.1.5 CAPTURE DURING SLEEP TMR1H TMR1L Capture mode depends upon the Timer1 module for CCPxCON<3:0> proper operation. There are two options for driving the System Clock (FOSC) Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock 15.1.2 TIMER1 MODE SELECTION source. Timer1 must be running in Timer mode or Synchronized If Timer1 is clocked by FOSC/4, then Timer1 will not Counter mode for the CCP module to use the capture increment during Sleep. When the device wakes from feature. In Asynchronous Counter mode or when Sleep, Timer1 will continue from its previous state. Timer1 is clocked at FOSC, the capture operation may If Timer1 is clocked by an external clock source, then not work. Capture mode will operate as defined in Section15.1 “Capture Mode”. DS40001417C-page 116  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 53 APFCON — — — — — — SSSEL CCP2SEL 42 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 115 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 115 CCPRxL Capture/Compare/PWM Register X Low Byte 116 CCPRxH Capture/Compare/PWM Register X High Byte 116 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 36 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 37 PIE2 — — — — — — — CCP2IE 38 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 39 PIR2 — — — — — — — CCP2IF 40 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 103 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 104 DONE TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 99 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 99 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 52 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 62 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture.  2010-2016 Microchip Technology Inc. DS40001417C-page 117

PIC16(L)F722A/723A 15.2 Compare Mode 15.2.2 TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is In Compare mode, Timer1 must be running in either constantly compared against the TMR1 register pair Timer mode or Synchronized Counter mode. The value. When a match occurs, the CCPx module may: compare operation may not work in Asynchronous Counter mode. • Toggle the CCPx output Note: Clocking Timer1 from the system clock • Set the CCPx output (FOSC) should not be used in Compare • Clear the CCPx output mode. For the Compare operation of the • Generate a Special Event Trigger TMR1 register to the CCPRx register to • Generate a Software Interrupt occur, Timer1 must be clocked from the The action on the pin is based on the value of the instruction clock (FOSC/4) or from an CCPxM<3:0> control bits of the CCPxCON register. external clock source. All Compare modes can generate an interrupt. 15.2.3 SOFTWARE INTERRUPT MODE FIGURE 15-2: COMPARE MODE When Software Interrupt mode is chosen OPERATION BLOCK (CCPxM<3:0>=1010), the CCPxIF bit in the PIRx register is set and the CCPx module does not assert DIAGRAM control of the CCPx pin (refer to the CCPxCON CCPxCON<3:0> register). Mode Select 15.2.4 SPECIAL EVENT TRIGGER Set CCPxIF Interrupt Flag (PIRx) When Special Event Trigger mode is chosen 4 CCPx CCPRxH CCPRxL (CCPxM<3:0>=1011), the CCPx module does the following: Q S Output Comparator R Logic Match • Resets Timer1 • Starts an ADC conversion if ADC is enabled TMR1H TMR1L TRIS (CCP2 only) Output Enable The CCPx module does not assert control of the CCPx Special Event Trigger pin in this mode (refer to the CCPxCON register). Special Event Trigger will: The Special Event Trigger output of the CCP occurs • Clear TMR1H and TMR1L registers. immediately upon a match between the TMR1H, • NOT set interrupt flag bit TMR1IF of the PIR1 register. TMR1L register pair and the CCPRxH, CCPRxL • Set the GO/DONE bit to start the ADC conversion register pair. The TMR1H, TMR1L register pair is not (CCP2 only). reset until the next rising edge of the Timer1 clock. This allows the CCPRxH, CCPRxL register pair to 15.2.1 CCPx PIN CONFIGURATION effectively provide a 16-bit programmable period The user must configure the CCPx pin as an output by register for Timer1. clearing the associated TRIS bit. Note1: The Special Event Trigger from the CCP Either RC1 or RB3 can be selected as the CCP2 pin. module does not set interrupt flag bit Refer to Section6.1 “Alternate Pin Function” for TMR1IF of the PIR1 register. more information. 2: Removing the match condition by Note: Clearing the CCPxCON register will force changing the contents of the CCPRxH the CCPx compare output latch to the and CCPRxL register pair, between the default low level. This is not the PORT I/O clock edge that generates the Special data latch. Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. 15.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. DS40001417C-page 118  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 15-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/ ADON 85 DONE ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 53 APFCON — — — — — — SSSEL CCP2SEL 42 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 115 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 115 CCPRxL Capture/Compare/PWM Register X Low Byte 116 CCPRxH Capture/Compare/PWM Register X High Byte 116 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 36 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 37 PIE2 — — — — — — — CCP2IE 38 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 39 PIR2 — — — — — — — CCP2IF 40 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 103 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 104 DONE TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 99 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 99 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 52 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 62 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Compare.  2010-2016 Microchip Technology Inc. DS40001417C-page 119

PIC16(L)F722A/723A 15.3 PWM Mode The PWM output (Figure15-4) has a time base (period) and a time that the output stays high (duty The PWM mode generates a Pulse-Width Modulated cycle). signal on the CCPx pin. The duty cycle, period and resolution are determined by the following registers: FIGURE 15-4: CCP PWM OUTPUT • PR2 • T2CON Period • CCPRxL Pulse Width • CCPxCON TMR2 = PR2 In Pulse-Width Modulation (PWM) mode, the CCP TMR2 = CCPRxL:CCPxCON<5:4> module produces up to a 10-bit resolution PWM output TMR2 = 0 on the CCPx pin. Figure15-3 shows a simplified block diagram of PWM 15.3.1 CCPX PIN CONFIGURATION operation. Figure15-4 shows a typical waveform of the PWM In PWM mode, the CCPx pin is multiplexed with the signal. PORT data latch. The user must configure the CCPx pin as an output by clearing the associated TRIS bit. For a step-by-step procedure on how to set up the CCP module for PWM operation, refer to Section15.3.8 Either RC1 or RB3 can be selected as the CCP2 pin. “Setup for PWM Operation”. Refer to Section6.1 “Alternate Pin Function” for more information. FIGURE 15-3: SIMPLIFIED PWM BLOCK Note: Clearing the CCPxCON register will DIAGRAM relinquish CCPx control of the CCPx pin. CCPxCON<5:4> Duty Cycle Registers CCPRxL CCPRxH(2) (Slave) CCPx Comparator R Q S TMR2 (1) TRIS Comparator Clear Timer2, toggle CCPx pin and latch duty cycle PR2 Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. 2: In PWM mode, CCPRxH is a read-only register. DS40001417C-page 120  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 15.3.2 PWM PERIOD EQUATION 15-2: PULSE WIDTH The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the Pulse Width = CCPRxL:CCPxCON<5:4>  formula of Equation15-1. TOSC  (TMR2 Prescale Value) EQUATION 15-1: PWM PERIOD Note: TOSC = 1/FOSC PWM Period = PR2+14TOSC EQUATION 15-3: DUTY CYCLE RATIO (TMR2 Prescale Value) Note: TOSC = 1/FOSC Duty Cycle Ratio = ---C----C----P----R---x---L---:--C----C----P----x---C----O----N----<----5---:--4--->------ 4PR2+1 When TMR2 is equal to PR2, the following three events occur on the next increment cycle: The CCPRxH register and a 2-bit internal latch are • TMR2 is cleared used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. • The CCPx pin is set. (Exception: If the PWM duty cycle=0%, the pin will not be set.) The 8-bit timer TMR2 register is concatenated with • The PWM duty cycle is latched from CCPRxL into either the 2-bit internal system clock (FOSC), or 2 bits of CCPRxH. the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. Note: The Timer2 postscaler (refer to When the 10-bit time base matches the CCPRxH and Section13.1 “Timer2 Operation”) is not 2-bit latch, then the CCPx pin is cleared (refer to used in the determination of the PWM Figure15-3). frequency. 15.3.3 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB<1:0> bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPRxH register is read-only. Equation15-2 is used to calculate the PWM pulse width. Equation15-3 is used to calculate the PWM duty cycle ratio.  2010-2016 Microchip Technology Inc. DS40001417C-page 121

PIC16(L)F722A/723A 15.3.4 PWM RESOLUTION EQUATION 15-4: PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution log4PR2+1 Resolution = ------------------------------------------ bits will result in 1024 discrete duty cycles, whereas an 8-bit log2 resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is Note: If the pulse-width value is greater than the 255. The resolution is a function of the PR2 register period, the assigned PWM pin(s) will value as shown by Equation15-4. remain unchanged. TABLE 15-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 15-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 15.3.5 OPERATION IN SLEEP MODE 15.3.8 SETUP FOR PWM OPERATION In Sleep mode, the TMR2register will not increment The following steps should be taken when configuring and the state of the module will not change. If the CCPx the CCP module for PWM operation: pin is driving a value, it will continue to drive that value. 1. Disable the PWM pin (CCPx) output driver(s) by When the device wakes up, TMR2 will continue from its setting the associated TRIS bit(s). previous state. 2. Load the PR2 register with the PWM period value. 15.3.6 CHANGES IN SYSTEM CLOCK 3. Configure the CCP module for the PWM mode FREQUENCY by loading the CCPxCON register with the appropriate values. The PWM frequency is derived from the system clock 4. Load the CCPRxL register and the DCxBx bits of frequency (FOSC). Any changes in the system clock fre- the CCPxCON register, with the PWM duty cycle quency will result in changes to the PWM frequency. value. Refer to Section7.0 “Oscillator Module” for additional details. 5. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 15.3.7 EFFECTS OF RESET register. See Note below. Any Reset will force all ports to Input mode and the • Configure the T2CKPS bits of the T2CON CCP registers to their Reset states. register with the Timer2 prescale value. • Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output pin: • Wait until Timer2 overflows, TMR2IF bit of the PIR1 register is set. See Note below. • Enable the PWM pin (CCPx) output driver(s) by clearing the associated TRIS bit(s). Note: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. DS40001417C-page 122  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 15-7: SUMMARY OF REGISTERS ASSOCIATED WITH PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 53 APFCON — — — — — — SSSEL CCP2SEL 42 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 115 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 115 CCPRxL Capture/Compare/PWM Register X Low Byte 116 CCPRxH Capture/Compare/PWM Register X High Byte 116 PR2 Timer2 Period Register 106 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 107 TMR2 Timer2 Module Register 106 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 52 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 62 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.  2010-2016 Microchip Technology Inc. DS40001417C-page 123

PIC16(L)F722A/723A 16.0 ADDRESSABLE UNIVERSAL The AUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (AUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Addressable Universal Synchronous • Address detection in 9-bit mode Asynchronous Receiver Transmitter (AUSART) • Input buffer overrun error detection module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and • Received character framing error detection data buffers necessary to perform an input or output • Half-duplex synchronous master serial data transfer independent of device program • Half-duplex synchronous slave execution. The AUSART, also known as a Serial • Sleep operation Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex Block diagrams of the AUSART transmitter and synchronous system. Full-Duplex mode is useful for receiver are shown in Figure16-1 and Figure16-2. communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. FIGURE 16-1: AUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREG Register TXIF 8 MSb LSb TX/CK (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT SPEN Baud Rate Generator FOSC ÷ n TX9 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 0 0 SPBRG BRGH x 1 0 DS40001417C-page 124  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 16-2: AUSART RECEIVE BLOCK DIAGRAM SPEN CREN OERR RX/DT MSb RSR Register LSb Panind BCuoffnetrrol DReactaovery Stop (8) 7 • • • 1 0 START Baud Rate Generator FOSC RX9 ÷ n n + 1 Multiplier x4 x16 x64 SYNC 1 0 0 FIFO SPBRG BRGH x 1 0 FERR RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE The operation of the AUSART module is controlled through two registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) These registers are detailed in Register16-1 and Register16-2, respectively.  2010-2016 Microchip Technology Inc. DS40001417C-page 125

PIC16(L)F722A/723A 16.1 AUSART Asynchronous Mode The AUSART transmits and receives data using the Note 1: When the SPEN bit is set the RX/DT I/O standard non-return-to-zero (NRZ) format. NRZ is pin is automatically configured as an input, implemented with two levels: a VOH Mark state which regardless of the state of the represents a ‘1’ data bit, and a VOL Space state which corresponding TRIS bit and whether or not represents a ‘0’ data bit. NRZ refers to the fact that the AUSART receiver is enabled. The RX/ consecutively transmitted data bits of the same value DT pin data can be read via a normal stay at the output level of that bit without returning to a PORT read but PORT latch data output is neutral level between each bit transmission. An NRZ precluded. transmission port idles in the Mark state. Each character 2: The TXIF transmitter interrupt flag is set transmission consists of one Start bit followed by eight when the TXEN enable bit is set. or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the 16.1.1.2 Transmitting Data Stop bits are always marks. The most common data A transmission is initiated by writing a character to the format is eight bits. Each transmitted bit persists for a TXREG register. If this is the first character, or the period of 1/(Baud Rate). An on-chip dedicated 8-bit previous character has been completely flushed from Baud Rate Generator is used to derive standard baud the TSR, the data in the TXREG is immediately rate frequencies from the system oscillator. Refer to transferred to the TSR register. If the TSR still contains Table16-5 for examples of baud rate configurations. all or part of a previous character, the new character The AUSART transmits and receives the LSb first. The data is held in the TXREG until the Stop bit of the AUSART’s transmitter and receiver are functionally previous character has been transmitted. The pending independent, but share the same data format and baud character in the TXREG is then transferred to the TSR rate. Parity is not supported by the hardware, but can in one TCY immediately following the Stop bit be implemented in software and stored as the ninth transmission. The transmission of the Start bit, data bits data bit. and Stop bit sequence commences immediately following the transfer of the data to the TSR from the 16.1.1 AUSART ASYNCHRONOUS TXREG. TRANSMITTER 16.1.1.3 Transmit Interrupt Flag The AUSART transmitter block diagram is shown in Figure16-1. The heart of the transmitter is the serial The TXIF interrupt flag bit of the PIR1 register is set Transmit Shift Register (TSR), which is not directly whenever the AUSART transmitter is enabled and no accessible by software. The TSR obtains its data from character is being held for transmission in the TXREG. the transmit buffer, which is the TXREG register. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been 16.1.1.1 Enabling the Transmitter queued for transmission in the TXREG. The TXIF flag bit The AUSART transmitter is enabled for asynchronous is not cleared immediately upon writing TXREG. TXIF operations by configuring the following three control becomes valid in the second instruction cycle following bits: the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit • TXEN = 1 is read-only, it cannot be set or cleared by software. • SYNC = 0 The TXIF interrupt can be enabled by setting the TXIE • SPEN = 1 interrupt enable bit of the PIE1 register. However, the All other AUSART control bits are assumed to be in TXIF flag bit will be set whenever the TXREG is empty, their default state. regardless of the state of TXIE enable bit. Setting the TXEN bit of the TXSTA register enables the To use interrupts when transmitting data, set the TXIE transmitter circuitry of the AUSART. Clearing the SYNC bit only when there is more data to send. Clear the bit of the TXSTA register configures the AUSART for TXIE interrupt enable bit upon writing the last character asynchronous operation. Setting the SPEN bit of the of the transmission to the TXREG. RCSTA register enables the AUSART and automatically configures the TX/CK I/O pin as an output. DS40001417C-page 126  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 16.1.1.4 TSR Status 16.1.1.6 Asynchronous Transmission Setup: The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRG register and the BRGH bit to status of the TSR register. This is a read-only bit. The achieve the desired baud rate (Refer to TRMT bit is set when the TSR register is empty and is Section16.2 “AUSART Baud Rate Generator cleared when a character is transferred to the TSR (BRG)”). register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit. No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 con- poll this bit to determine the TSR status. trol bit. A set ninth data bit will indicate that the Note: The TSR register is not mapped in data eight Least Significant data bits are an address memory, so it is not available to the user. when the receiver is set for address detection. 4. Enable the transmission by setting the TXEN 16.1.1.5 Transmitting 9-Bit Characters control bit. This will cause the TXIF interrupt bit to be set. The AUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set, the 5. If interrupts are desired, set the TXIE interrupt AUSART will shift nine bits out for each character trans- enable bit of the PIE1 register. An interrupt will mitted. The TX9D bit of the TXSTA register is the ninth, occur immediately provided that the GIE and and Most Significant, data bit. When transmitting 9-bit PEIE bits of the INTCON register are also set. data, the TX9D data bit must be written before writing 6. If 9-bit transmission is selected, the ninth bit the eight Least Significant bits into the TXREG. All nine should be loaded into the TX9D data bit. bits of data will be transferred to the TSR shift register 7. Load 8-bit data into the TXREG register. This immediately after the TXREG is written. will start the transmission. A special 9-bit Address mode is available for use with multiple receivers. Refer to Section16.1.2.7 “Address Detection” for more information on the Address mode. FIGURE 16-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag)  2010-2016 Microchip Technology Inc. DS40001417C-page 127

PIC16(L)F722A/723A FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit (Transmit Buffer 1 TCY Word 1 Word 2 Empty Flag) 1 TCY TRMT bit Word 1 Word 2 Reg(T. rEamnspmtyi tF Slahgif)t Transmit Shift Reg. Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 16-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 TXREG AUSART Transmit Data Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for asynchronous transmission. DS40001417C-page 128  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 16.1.2 AUSART ASYNCHRONOUS 16.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit, systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data Figure16-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts the baud rate, whereas the serial Receive Shift character reception, without generating an error, and Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data are immediately transferred to a two character First-In recovery circuit counts a full bit time to the center of the First-Out (FIFO) memory. The FIFO buffering allows next bit. The bit is then sampled by a majority detect reception of two complete characters and the start of a circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. third character before software must start servicing the This repeats until all data bits have been sampled and AUSART receiver. The FIFO and RSR registers are not shifted into the RSR. One final bit time is measured and directly accessible by software. Access to the received the level sampled. This is the Stop bit, which is always data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this 16.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this character. Refer to Section16.1.2.4 “Receive The AUSART receiver is enabled for asynchronous Framing Error” for more information on framing operation by configuring the following three control bits: errors. • CREN = 1 Immediately after all data bits and the Stop bit have • SYNC = 0 been received, the character in the RSR is transferred • SPEN = 1 to the AUSART receive FIFO and the RCIF interrupt All other AUSART control bits are assumed to be in flag bit of the PIR1 register is set. The top character in their default state. the FIFO is transferred out of the FIFO by reading the RCREG register. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the AUSART. Clearing the SYNC bit Note: If the receive FIFO is overrun, no additional of the TXSTA register configures the AUSART for characters will be received until the overrun asynchronous operation. Setting the SPEN bit of the condition is cleared. Refer to RCSTA register enables the AUSART and automatically Section16.1.2.5 “Receive Overrun configures the RX/DT I/O pin as an input. Error” for more information on overrun errors. Note: When the SPEN bit is set the TX/CK I/O 16.1.2.3 Receive Interrupts pin is automatically configured as an The RCIF interrupt flag bit of the PIR1 register is set output, regardless of the state of the whenever the AUSART receiver is enabled and there is corresponding TRIS bit and whether or an unread character in the receive FIFO. The RCIF not the AUSART transmitter is enabled. interrupt flag bit is read-only, it cannot be set or cleared The PORT latch is disconnected from the by software. output driver so it is not possible to use the TX/CK pin as a general purpose output. RCIF interrupts are enabled by setting all of the following bits: • RCIE, Receive Interrupt Enable bit of the PIE1 register • PEIE, Peripheral Interrupt Enable bit of the INTCON register • GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit of the PIR1 register will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.  2010-2016 Microchip Technology Inc. DS40001417C-page 129

PIC16(L)F722A/723A 16.1.2.4 Receive Framing Error 16.1.2.7 Address Detection Each character in the receive FIFO buffer has a A special Address Detection mode is available for use corresponding framing error Status bit. A framing error when multiple receivers share the same transmission indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA FERR bit of the RCSTA register. The FERR bit register. represents the status of the top unread character in the Address detection requires 9-bit character reception. receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters before reading the RCREG. with the ninth data bit set will be transferred to the The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt unread character in the receive FIFO. A framing error bit of the PIR1 register. All other characters will be (FERR = 1) does not preclude reception of additional ignored. characters. It is not necessary to clear the FERR bit. Upon receiving an address character, user software Reading the next character from the FIFO buffer will determines if the address matches its own. Upon advance the FIFO to the next character and the next address match, user software must disable address corresponding framing error. detection by clearing the ADDEN bit before the next The FERR bit can be forced clear by clearing the SPEN Stop bit occurs. When user software detects the end of bit of the RCSTA register which resets the AUSART. the message, determined by the message protocol Clearing the CREN bit of the RCSTA register does not used, software places the receiver back into the affect the FERR bit. A framing error by itself does not Address Detection mode by setting the ADDEN bit. generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. 16.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by setting the AUSART by clearing the SPEN bit of the RCSTA register. 16.1.2.6 Receiving 9-bit Characters The AUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the AUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG. DS40001417C-page 130  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 16.1.2.8 Asynchronous Reception Setup: 16.1.2.9 9-bit Address Detection Mode Setup 1. Initialize the SPBRG register and the BRGH bit This mode would typically be used in RS-485 systems. to achieve the desired baud rate (refer to To set up an Asynchronous Reception with Address Section16.2 “AUSART Baud Rate Generator Detect Enable: (BRG)”). 1. Initialize the SPBRG register and the BRGH bit 2. Enable the serial port by setting the SPEN bit. to achieve the desired baud rate (refer to The SYNC bit must be clear for asynchronous Section16.2 “AUSART Baud Rate Generator operation. (BRG)”). 3. If interrupts are desired, set the RCIE bit of the 2. Enable the serial port by setting the SPEN bit. PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous INTCON register. operation. 4. If 9-bit reception is desired, set the RX9 bit. 3. If interrupts are desired, set the RCIE bit of the 5. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the 6. The RCIF interrupt flag bit of the PIR1 register INTCON register. will be set when a character is transferred from 4. Enable 9-bit reception by setting the RX9 bit. the RSR to the receive buffer. An interrupt will be 5. Enable address detection by setting the ADDEN generated if the RCIE bit of the PIE1 register bit. was also set. 6. Enable reception by setting the CREN bit. 7. Read the RCSTA register to get the error flags 7. The RCIF interrupt flag bit of the PIR1 register and, if 9-bit data reception is enabled, the ninth will be set when a character with the ninth bit set data bit. is transferred from the RSR to the receive buffer. 8. Get the received eight Least Significant data bits An interrupt will be generated if the RCIE from the receive buffer by reading the RCREG interrupt enable bit of the PIE1 register was also register. set. 9. If an overrun occurred, clear the OERR flag by 8. Read the RCSTA register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. FIGURE 16-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 RCREG RCREG Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.  2010-2016 Microchip Technology Inc. DS40001417C-page 131

PIC16(L)F722A/723A TABLE 16-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RCREG AUSART Receive Data Register 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for asynchronous reception. DS40001417C-page 132  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: AUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as ‘0’ bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Synchronous mode.  2010-2016 Microchip Technology Inc. DS40001417C-page 133

PIC16(L)F722A/723A REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit(1) 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care Synchronous mode: Must be set to ‘0’ bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Note1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure TRISx=1. DS40001417C-page 134  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 16.2 AUSART Baud Rate Generator EXAMPLE 16-1: CALCULATING BAUD (BRG) RATE ERROR The Baud Rate Generator (BRG) is an 8-bit timer that For a device with FOSC of 16 MHz, desired baud rate of 9600, and Asynchronous mode with SYNC = 0 and BRGH is dedicated to the support of both the asynchronous = 0 (as seen in Table16-3): and synchronous AUSART operation. The SPBRG register determines the period of the free Desired Baud Rate = -------------F----O----S---C--------------- running baud rate timer. In Asynchronous mode the 64SPBRG+1 multiplier of the baud rate period is determined by the Solving for SPBRG: BRGH bit of the TXSTA register. In Synchronous mode, the BRGH bit is ignored. SPBRG = ----------------------F----O----S---C------------------------–1 Table16-3 contains the formulas for determining the 64Desired Baud Rate baud rate. Example16-1 provides a sample calculation for determining the baud rate and baud rate error. = -1---6---0---0---0---0---0---0--–1 649600 Typical baud rates and error values for various asynchronous modes have been computed for your = 25.042 = 25 convenience and are shown in Table16-3. It may be advantageous to use the high baud rate (BRGH = 1), to 16000000 Actual Baud Rate = --------------------------- reduce the baud rate error. 6425+1 Writing a new value to the SPBRG register causes the = 9615 BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before Actual Baud Rate–Desired Baud Rate  % Error = -------------------------------------------------------------------------------------------------- 100 outputting the new baud rate.  Desired Baud Rate  9615–9600 = ------------------------------ 100 = 0.16%  9600  TABLE 16-3: BAUD RATE FORMULAS Configuration Bits AUSART Mode Baud Rate Formula SYNC BRGH 0 0 Asynchronous FOSC/[64 (n+1)] 0 1 Asynchronous FOSC/[16 (n+1)] 1 x Synchronous FOSC/[4 (n+1)] Legend: x = Don’t care, n = value of SPBRG register TABLE 16-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.  2010-2016 Microchip Technology Inc. DS40001417C-page 135

PIC16(L)F722A/723A TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0 FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.0000 MHz FOSC = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1201 0.08 207 1200 0.00 143 2400 2404 0.16 129 2400 0.00 119 2403 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.26 27 10416 -0.01 23 10165 -2.42 16 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k — — — 57.60k 0.00 7 — — — 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1 BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.0000 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.82k -1.36 21 57.60k 0.00 19 58.8k 2.12 16 57.60k 0.00 11 115.2k 113.64k -1.36 10 115.2k 0.00 9 — — — 115.2k 0.00 5 DS40001417C-page 136  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — —  2010-2016 Microchip Technology Inc. DS40001417C-page 137

PIC16(L)F722A/723A 16.3 AUSART Synchronous Mode 16.3.1.2 Synchronous Master Transmission Synchronous serial communications are typically used Data is transferred out of the device on the RX/DT pin. in systems with a single master and one or more The RX/DT and TX/CK pin output drivers are slaves. The master device contains the necessary automatically enabled when the AUSART is configured circuitry for baud rate generation and supplies the clock for synchronous master transmit operation. for all devices in the system. Slave devices can take A transmission is initiated by writing a character to the advantage of the master clock by eliminating the TXREG register. If the TSR still contains all or part of a internal clock generation circuitry. previous character, the new character data is held in There are two signal lines in Synchronous mode: a the TXREG until the last bit of the previous character bidirectional data line and a clock line. Slaves use the has been transmitted. If this is the first character, or the external clock supplied by the master to shift the serial previous character has been completely flushed from data into and out of their respective receive and the TSR, the data in the TXREG is immediately transmit shift registers. Since the data line is transferred to the TSR. The transmission of the bidirectional, synchronous operation is half-duplex character commences immediately following the only. Half-duplex refers to the fact that master and transfer of the data to the TSR from the TXREG. slave devices can receive and transmit data but not Each data bit changes on the leading edge of the both simultaneously. The AUSART can operate as master clock and remains valid until the subsequent either a master or slave device. leading clock edge. Start and Stop bits are not used in synchronous Note: The TSR register is not mapped in data transmissions. memory, so it is not available to the user. 16.3.1 SYNCHRONOUS MASTER MODE 16.3.1.3 Synchronous Master Transmission The following bits are used to configure the AUSART Setup: for Synchronous Master operation: 1. Initialize the SPBRG register and the BRGH bit • SYNC = 1 to achieve the desired baud rate (refer to • CSRC = 1 Section16.2 “AUSART Baud Rate Generator • SREN = 0 (for transmit); SREN = 1 (for receive) (BRG)”). • CREN = 0 (for transmit); CREN = 1 (for receive) 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. • SPEN = 1 3. Disable Receive mode by clearing bits SREN Setting the SYNC bit of the TXSTA register configures and CREN. the device for synchronous operation. Setting the CSRC 4. Enable Transmit mode by setting the TXEN bit. bit of the TXSTA register configures the device as a 5. If 9-bit transmission is desired, set the TX9 bit. master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, 6. If interrupts are desired, set the TXIE bit of the otherwise the device will be configured to receive. Setting PIE1 register and the GIE and PEIE bits of the the SPEN bit of the RCSTA register enables the INTCON register. AUSART. 7. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. 16.3.1.1 Master Clock 8. Start transmission by loading data to the TXREG Synchronous data transfers use a separate clock line, register. which is synchronous with the data. A device configured as a master transmits the clock on the TX/ CK line. The TX/CK pin output driver is automatically enabled when the AUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. DS40001417C-page 138  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 16-6: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK pin Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Synchronous Master mode, SPBRG = 0, continuous transmission of two 8-bit words. FIGURE 16-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit TABLE 16-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 TXREG AUSART Transmit Data Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous master transmission.  2010-2016 Microchip Technology Inc. DS40001417C-page 139

PIC16(L)F722A/723A 16.3.1.4 Synchronous Master Reception 16.3.1.7 Receiving 9-bit Characters Data is received at the RX/DT pin. The RX/DT pin The AUSART supports 9-bit character reception. When output driver is automatically disabled when the the RX9 bit of the RCSTA register is set, the AUSART AUSART is configured for synchronous master receive will shift nine bits into the RSR for each character operation. received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread In Synchronous mode, reception is enabled by setting character in the receive FIFO. When reading 9-bit data either the Single Receive Enable bit (SREN of the from the receive FIFO buffer, the RX9D data bit must RCSTA register) or the Continuous Receive Enable bit be read before reading the eight Least Significant bits (CREN of the RCSTA register). from the RCREG. When SREN is set and CREN is clear, only as many Address detection in Synchronous modes is not clock cycles are generated as there are data bits in a supported, therefore the ADDEN bit of the RCSTA single character. The SREN bit is automatically cleared register must be cleared. at the completion of one character. When CREN is set, clocks are continuously generated until CREN is 16.3.1.8 Synchronous Master Reception cleared. If CREN is cleared in the middle of a character Setup: the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both 1. Initialize the SPBRG register for the appropriate set, then SREN is cleared at the completion of the first baud rate. Set or clear the BRGH bit, as character and CREN takes precedence. required, to achieve the desired baud rate. To initiate reception, set either SREN or CREN. Data is 2. Enable the synchronous master serial port by sampled at the RX/DT pin on the trailing edge of the setting bits SYNC, SPEN and CSRC. TX/CK clock pin and is shifted into the Receive Shift 3. Ensure bits CREN and SREN are clear. Register (RSR). When a complete character is 4. If interrupts are desired, set the RCIE bit of the received into the RSR, the RCIF bit of the PIR1 register PIE1 register and the GIE and PEIE bits of the is set and the character is automatically transferred to INTCON register. the two character receive FIFO. The Least Significant 5. If 9-bit reception is desired, set bit RX9. eight bits of the top character in the receive FIFO are 6. Verify address detection is disabled by clearing available in RCREG. The RCIF bit remains set as long the ADDEN bit of the RCSTA register. as there are un-read characters in the receive FIFO. 7. Start reception by setting the SREN bit or for 16.3.1.5 Slave Clock continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF of the PIR1 register will be Synchronous data transfers use a separate clock line, set when reception of a character is complete. which is synchronous with the data. A device configured An interrupt will be generated if the RCIE as a slave receives the clock on the TX/CK line. The TX/ interrupt enable bit of the PIE1 register was set. CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or 9. Read the RCSTA register to get the ninth bit (if receive operation. Serial data bits change on the leading enabled) and determine if any error occurred edge to ensure they are valid at the trailing edge of each during reception. clock. One data bit is transferred for each clock cycle. 10. Read the 8-bit received data by reading the Only as many clock cycles should be received as there RCREG register. are data bits. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA 16.3.1.6 Receive Overrun Error register or by clearing the SPEN bit, which The receive FIFO buffer can hold two characters. An resets the AUSART. overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register. DS40001417C-page 140  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RCREG AUSART Receive Data Register 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous master reception.  2010-2016 Microchip Technology Inc. DS40001417C-page 141

PIC16(L)F722A/723A 16.3.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the AUSART for Synchronous slave operation: 1. The first character will immediately transfer to the TSR register and transmit. • SYNC = 1 2. The second word will remain in TXREG register. • CSRC = 0 3. The TXIF bit will not be set. • SREN = 0 (for transmit); SREN = 1 (for receive) 4. After the first character has been shifted out of • CREN = 0 (for transmit); CREN = 1 (for receive) TSR, the TXREG register will transfer the second • SPEN = 1 character to the TSR and the TXIF bit will now be Setting the SYNC bit of the TXSTA register configures the set. device for synchronous operation. Clearing the CSRC bit 5. If the PEIE and TXIE bits are set, the interrupt of the TXSTA register configures the device as a slave. will wake the device from Sleep and execute the Clearing the SREN and CREN bits of the RCSTA register next instruction. If the GIE bit is also set, the ensures that the device is in the Transmit mode, program will call the Interrupt Service Routine. otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the 16.3.2.2 Synchronous Slave Transmission AUSART. Setup: 16.3.2.1 AUSART Synchronous Slave 1. Set the SYNC and SPEN bits and clear the CSRC bit. Transmit 2. Clear the CREN and SREN bits. The operation of the Synchronous Master and Slave 3. If using interrupts, ensure that the GIE and PEIE modes are identical (refer to Section16.3.1.2 bits of the INTCON register are set and set the “Synchronous Master Transmission”), except in the TXIE bit. case of the Sleep mode. 4. If 9-bit transmission is desired, set the TX9 bit. 5. Enable transmission by setting the TXEN bit. 6. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. 7. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 8. Start transmission by writing the Least Significant eight bits to the TXREG register. TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 TXREG AUSART Transmit Data Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave transmission. DS40001417C-page 142  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 16.3.2.3 AUSART Synchronous Slave 16.3.2.4 Synchronous Slave Reception Reception Setup: The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the modes is identical (Section16.3.1.4 “Synchronous CSRC bit. Master Reception”), with the following exceptions: 2. If interrupts are desired, set the RCIE bit of the • Sleep PIE1 register and the GIE and PEIE bits of the INTCON register. • CREN bit is always set, therefore the receiver is never Idle 3. If 9-bit reception is desired, set the RX9 bit. • SREN bit, which is a “don’t care” in Slave mode 4. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. A character may be received while in Sleep mode by 5. Set the CREN bit to enable reception. setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data 6. The RCIF bit of the PIR1 register will be set to the RCREG register. If the RCIE interrupt enable bit when reception is complete. An interrupt will be of the PIE1 register is set, the interrupt generated will generated if the RCIE bit of the PIE1 register wake the device from Sleep and execute the next was set. instruction. If the GIE bit is also set, the program will 7. If 9-bit mode is enabled, retrieve the Most branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTA register. 8. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register. TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RCREG AUSART Receive Data Register 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.  2010-2016 Microchip Technology Inc. DS40001417C-page 143

PIC16(L)F722A/723A 16.4 AUSART Operation During Sleep 16.4.2 SYNCHRONOUS TRANSMIT DURING SLEEP The AUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the To transmit during Sleep, all the following conditions system clock and therefore can not generate the must be met before entering Sleep mode: necessary signals to run the Transmit or Receive Shift • RCSTA and TXSTA Control registers must be registers during Sleep. configured for Synchronous Slave Transmission Synchronous Slave mode uses an externally generated (refer to Section16.3.2.2 “Synchronous Slave clock to run the Transmit and Receive Shift registers. Transmission Setup:”). • The TXIF interrupt flag must be cleared by writing 16.4.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the SLEEP TSR and transmit buffer. To receive during Sleep, all the following conditions • If interrupts are desired, set the TXIE bit of the must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON register. • RCSTA and TXSTA Control registers must be configured for Synchronous Slave Reception Upon entering Sleep mode, the device will be ready to (refer to Section16.3.2.4 “Synchronous Slave accept clocks on TX/CK pin and transmit data on the Reception Setup:”). RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the • If interrupts are desired, set the RCIE bit of the pending byte in the TXREG will transfer to the TSR and PIE1 register and the PEIE bit of the INTCON the TXIF flag will be set, thereby waking the processor register. from Sleep. At this point, the TXREG is available to • The RCIF interrupt flag must be cleared by accept another character for transmission, which will reading RCREG to unload any pending clear the TXIF flag. characters in the receive buffer. Upon waking from Sleep, the instruction following the Upon entering Sleep mode, the device will be ready to SLEEP instruction will be executed. If the Global accept data and clocks on the RX/DT and TX/CK pins, Interrupt Enable (GIE) bit is also set then the Interrupt respectively. When the data word has been completely Service Routine at address 0004h will be called. clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set, thereby waking the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 0004h will be called. DS40001417C-page 144  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 17.0 SSP MODULE OVERVIEW A typical SPI connection between microcontroller devices is shown in Figure17-1. Addressing of more The Synchronous Serial Port (SSP) module is a serial than one slave device is accomplished via multiple interface useful for communicating with other hardware slave select lines. External hardware and peripherals or microcontroller devices. These additional I/O pins must be used to support multiple peripheral devices may be serial EEPROMs, shift slave select addressing. This prevents extra overhead registers, display drivers, A/D converters, etc. The SSP in software for communication. module can operate in one of two modes: For SPI communication, typically three pins are used: • Serial Peripheral Interface (SPI) • Serial Data Out (SDO) • Inter-Integrated Circuit (I2C) • Serial Data In (SDI) • Serial Clock (SCK) 17.1 SPI Mode Additionally, a fourth pin may be used when in a Slave The SPI mode allows eight bits of data to be synchro- mode of operation: nously transmitted and received, simultaneously. The • Slave Select (SS) SSP module can be operated in one of two SPI modes: • Master mode • Slave mode SPI is a full-duplex protocol, with all communication being bidirectional and initiated by a master device. All clocking is provided by the master device and all bits are transmitted, MSb first. Care must be taken to ensure that all devices on the SPI bus are setup to allow all controllers to send and receive data at the same time. FIGURE 17-1: TYPICAL SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK Slave Select General I/O SS Processor 1 (optional) Processor 2  2010-2016 Microchip Technology Inc. DS40001417C-page 145

PIC16(L)F722A/723A FIGURE 17-2: SPI MODE BLOCK DIAGRAM Internal Data Bus Read Write SSPBUF Reg SSPSR Reg SDI bit 0 Shift bit 7 Clock SDO SS RA5/SS Control Enable RA0/SS SSSEL 2 Clock Select Edge Select TMR2 2 Output Edge Select Prescaler FOSC SCK 4, 16, 64 TRISx 4 SSPM<3:0> DS40001417C-page 146  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 17.1.1 MASTER MODE 17.1.1.3 Master Mode Setup In Master mode, data transfer can be initiated at any In Master mode, the data is transmitted/received as time because the master controls the SCK line. Master soon as the SSPBUF register is loaded with a byte mode determines when the slave (Figure17-1, value. If the master is only going to receive, SDO output Processor 2) transmits data via control of the SCK line. could be disabled (programmed and used as an input). The SSPSR register will continue to shift in the signal 17.1.1.1 Master Mode Operation present on the SDI pin at the programmed clock rate. The SSP consists of a transmit/receive shift register When initializing SPI Master mode operation, several (SSPSR) and a buffer register (SSPBUF). The SSPSR options need to be specified. This is accomplished by register shifts the data in and out of the device, MSb programming the appropriate control bits in the first. The SSPBUF register holds the data that is written SSPCON and SSPSTAT registers. These control bits out of the master until the received data is ready. Once allow the following to be specified: the eight bits of data have been received, the byte is • SCK as clock output moved to the SSPBUF register. The Buffer Full Status • Idle state of SCK (CKP bit) bit, BF of the SSPSTAT register, and the SSP Interrupt Flag bit, SSPIF of the PIR1 register, are then set. • Data input sample phase (SMP bit) • Output data on rising/falling edge of SCK (CKE bit) Any write to the SSPBUF register during transmission/ reception of data will be ignored and the Write Collision • Clock bit rate Detect bit, WCOL of the SSPCON register, will be set. In Master mode, the SPI clock rate (bit rate) is user User software must clear the WCOL bit so that it can be selectable to be one of the following: determined if the following write(s) to the SSPBUF • FOSC/4 (or TCY) register completed successfully. • FOSC/16 (or 4  TCY) When the application software is expecting to receive • FOSC/64 (or 16  TCY) valid data, the SSPBUF should be read before the next • (Timer2 output)/2 byte of data is written to the SSPBUF. The BF bit of the SSPSTAT register is set when SSPBUF has been This allows a maximum data rate of 5Mbps loaded with the received data (transmission is (atFOSC=20MHz). complete). When the SSPBUF is read, the BF bit is Figure17-3 shows the waveforms for Master mode. cleared. This data may be irrelevant if the SPI is only a The clock polarity is selected by appropriately transmitter. The SSP interrupt may be used to programming the CKP bit of the SSPCON register. determine when the transmission/reception is When the CKE bit is set, the SDO data is valid before complete and the SSPBUF must be read and/or there is a clock edge on SCK. The sample time of the written. If interrupts are not used, then software polling input data is shown based on the state of the SMP bit can be done to ensure that a write collision does not and can occur at the middle or end of the data output occur. Example17-1 shows the loading of the SSPBUF time. The time when the SSPBUF is loaded with the (SSPSR) for data transmission. received data is shown. Note: The SSPSR is not directly readable or 17.1.1.4 Sleep in Master Mode writable and can only be accessed by addressing the SSPBUF register. In Master mode, all module clocks are halted and the transmission/reception will remain in their current state, 17.1.1.2 Enabling Master I/O paused, until the device wakes from Sleep. After the To enable the serial port, the SSPEN bit of the device wakes up from Sleep, the module will continue SSPCON register, must be set. To reset or reconfigure to transmit/receive data. SPI mode, clear the SSPEN bit, re-initialize the SSPCON register and then set the SSPEN bit. If a Master mode of operation is selected in the SSPM bits of the SSPCON register, the SDI, SDO and SCK pins will be assigned as serial port pins. For these pins to function as serial port pins, they must have their corresponding data direction bits set or cleared in the associated TRIS register as follows: • SDI configured as input • SDO configured as output • SCK configured as output  2010-2016 Microchip Technology Inc. DS40001417C-page 147

PIC16(L)F722A/723A FIGURE 17-3: SPI MASTER MODE WAVEFORM Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER BANKSEL SSPSTAT ; LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)? GOTO LOOP ;No BANKSEL SSPBUF ; MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS40001417C-page 148  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 17.1.2 SLAVE MODE 17.1.2.2 Enabling Slave I/O For any SPI device acting as a slave, the data is To enable the serial port, the SSPEN bit of the transmitted and received as external clock pulses SSPCON register must be set. If a Slave mode of appear on SCK pin. This external clock must meet the operation is selected in the SSPM bits of the SSPCON minimum high and low times as specified in the register, the SDI, SDO and SCK pins will be assigned electrical specifications. as serial port pins. For these pins to function as serial port pins, they must 17.1.2.1 Slave Mode Operation have their corresponding data direction bits set or The SSP consists of a transmit/receive shift register cleared in the associated TRIS register as follows: (SSPSR) and a buffer register (SSPBUF). The SSPSR • SDI configured as input shifts the data in and out of the device, MSb first. The • SDO configured as output SSPBUF holds the data that was written to the SSPSR until the received data is ready. • SCK configured as input The slave has no control as to when data will be Optionally, a fourth pin, Slave Select (SS) may be used clocked in or out of the device. All data that is to be in Slave mode. Slave Select may be configured to transmitted, to a master or another slave, must be operate on one of the following pins via the SSSEL bit in loaded into the SSPBUF register before the first clock the APFCON register. pulse is received. • RA5/AN4/SS Once eight bits of data have been received: • RA0/AN0/SS • Received byte is moved to the SSPBUF register Upon selection of a Slave Select pin, the appropriate • BF bit of the SSPSTAT register is set bits must be set in the ANSELA and TRISA registers. Slave Select must be set as an input by setting the • SSPIF bit of the PIR1 register is set corresponding bit in TRISA, and digital I/O must be Any write to the SSPBUF register during transmission/ enabled on the SS pin by clearing the corresponding bit reception of data will be ignored and the Write Collision of the ANSELA register. Detect bit, WCOL of the SSPCON register, will be set. User software must clear the WCOL bit so that it can be 17.1.2.3 Slave Mode Setup determined if the following write(s) to the SSPBUF When initializing the SSP module to SPI Slave mode, register completed successfully. compatibility must be ensured with the master device. The user’s firmware must read SSPBUF, clearing the This is done by programming the appropriate control BF flag, or the SSPOV bit of the SSPCON register will bits of the SSPCON and SSPSTAT registers. These be set with the reception of the next byte and control bits allow the following to be specified: communication will be disabled. • SCK as clock input A SPI module transmits and receives at the same time, • Idle state of SCK (CKP bit) occasionally causing dummy data to be transmitted/ • Data input sample phase (SMP bit) received. It is up to the user to determine which data is • Output data on rising/falling edge of SCK (CKE bit) to be used and what can be discarded. Figure17-4 and Figure17-5 show example waveforms of Slave mode operation.  2010-2016 Microchip Technology Inc. DS40001417C-page 149

PIC16(L)F722A/723A FIGURE 17-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS40001417C-page 150  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 17.1.2.4 Slave Select Operation When the SPI module resets, the bit counter is cleared to ‘0’. This can be done by either forcing the SS pin to The SS pin allows Synchronous Slave mode operation. a high level or clearing the SSPEN bit. Figure17-6 The SPI must be in Slave mode with SS pin control shows the timing waveform for such a synchronization enabled (SSPM<3:0> = 0100). The associated TRIS bit event. for the SS pin must be set, making SS an input. In Slave Select mode, when: Note: SSPSR must be reinitialized by writing to the SSPBUF register before the data can • SS = 0, The device operates as specified in be clocked out of the slave again. Section17.1.2 “Slave Mode”. • SS = 1, The SPI module is held in Reset and the 17.1.2.5 Sleep in Slave Mode SDO pin will be tri-stated. While in Sleep mode, the slave can transmit/receive data. The SPI Transmit/Receive Shift register operates Note1: When the SPI is in Slave mode with SS asynchronously to the device on the externally supplied pin control enabled (SSPM<3:0>= 0100), clock source. This allows the device to be placed in the SPI module will reset if the SS pin is Sleep mode and data to be shifted into the SPI driven high. Transmit/Receive Shift register. When all eight bits 2: If the SPI is used in Slave mode with CKE have been received, the SSP Interrupt Flag bit will be set, the SS pin control must be enabled. set and if enabled, will wake the device from Sleep. FIGURE 17-6: SLAVE SELECT SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SSPSR must be reinitialized by writing to the SSPBUF register before the data can be clocked out of the slave again. SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF  2010-2016 Microchip Technology Inc. DS40001417C-page 151

PIC16(L)F722A/723A REGISTER 17-1: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins(1) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. Note 1: When enabled, these pins must be properly configured as input or output. DS40001417C-page 152  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A REGISTER 17-2: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode bit 6 CKE: SPI Clock Edge Select bit SPI mode, CKP = 0: 1 = Data stable on rising edge of SCK 0 = Data stable on falling edge of SCK SPI mode, CKP = 1: 1 = Data stable on falling edge of SCK 0 = Data stable on rising edge of SCK bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty  2010-2016 Microchip Technology Inc. DS40001417C-page 153

PIC16(L)F722A/723A TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 44 APFCON — — — — — — SSSEL CCP2SEL 42 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 36 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 37 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 39 PR2 Timer2 Period Register 106 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 147 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 152 SSPSTAT SMP CKE D/A P S R/W UA BF 153 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 43 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 62 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 107 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode. DS40001417C-page 154  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 17.2 I2C Mode FIGURE 17-8: TYPICAL I2C CONNECTIONS The SSP module, in I2C mode, implements all slave functions, except general call support. It provides interrupts on Start and Stop bits in hardware to facilitate VDD VDD firmware implementations of the master functions. The SSP module implements the I2C Standard mode specifications: • I2C Slave mode (7-bit address) Master Slave 1 • I2C Slave mode (10-bit address) SDA SDA • Start and Stop bit interrupts enabled to support SCL SCL firmware Master mode • Address masking Slave 2 Two pins are used for data transfer; the SCL pin (clock SDA line) and the SDA pin (data line). The user must SCL configure the two pin’s data direction bits as inputs in the appropriate TRIS register. Upon enabling I2C (optional) mode, the I2C slew rate limiters in the I/O pads are controlled by the SMP bit of SSPSTAT register. The The SSP module has six registers for I2C operation. SSP module functions are enabled by setting the They are: SSPEN bit of SSPCON register. • SSP Control (SSPCON) register Data is sampled on the rising edge and shifted out on • SSP Status (SSPSTAT) register the falling edge of the clock. This ensures that the SDA • Serial Receive/Transmit Buffer (SSPBUF) register signal is valid during the SCL high time. The SCL clock input must have minimum high and low times for proper • SSP Shift Register (SSPSR), not directly operation. Refer to Section23.0 “Electrical accessible Specifications”. • SSP Address (SSPADD) register • SSP Address Mask (SSPMSK) register FIGURE 17-7: I2C MODE BLOCK DIAGRAM 17.2.1 HARDWARE SETUP Selection of I2C mode, with the SSPEN bit of the Internal SSPCON register set, forces the SCL and SDA pins to Data Bus be open drain, provided these pins are programmed as Read Write inputs by setting the appropriate TRISC bits. The SSP module will override the input state with the output data, SSPBUF Reg when required, such as for Acknowledge and slave- SCL transmitter sequences. Shift Note: Pull-up resistors must be provided Clock externally to the SCL and SDA pins for SSPSR Reg proper operation of the I2C module. SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Stop bit Detect  2010-2016 Microchip Technology Inc. DS40001417C-page 155

PIC16(L)F722A/723A 17.2.2 START AND STOP CONDITIONS 17.2.3 ACKNOWLEDGE During times of no data transfer (Idle time), both the After the valid reception of an address or data byte, the clock line (SCL) and the data line (SDA) are pulled high hardware automatically will generate the Acknowledge through external pull-up resistors. The Start and Stop (ACK) pulse and load the SSPBUF register with the conditions determine the start and stop of data trans- received value currently in the SSPSR register. There mission. The Start condition is defined as a high-to-low are certain conditions that will cause the SSP module transition of the SDA line while SCL is high. The Stop not to generate this ACK pulse. They include any or all condition is defined as a low-to-high transition of the of the following: SDA line while SCL is high. • The Buffer Full bit, BF of the SSPSTAT register, Figure17-9 shows the Start and Stop conditions. A was set before the transfer was received. master device generates these conditions for starting • The SSP Overflow bit, SSPOV of the SSPCON and terminating data transfer. Due to the definition of register, was set before the transfer was received. the Start and Stop conditions, when data is being • The SSP module is being operated in Firmware transmitted, the SDA line can only change state when Master mode. the SCL line is low. In such a case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF of the PIR1 register is set. Table17-2 shows the results of when a data transfer byte is received, given the status of bits BF and SSPOV. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. FIGURE 17-9: START AND STOP CONDITIONS SDA SCL S P Change of Change of Data Allowed Data Allowed Start Stop Condition Condition TABLE 17-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Set bit SSPIF Transfer is Received SSPSR  SSPBUF Generate ACK (SSP Interrupt occurs Pulse BF SSPOV if enabled) 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition. DS40001417C-page 156  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 17.2.4 ADDRESSING If data is requested by the master, once the slave has been addressed: Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, 1. Receive repeated Start condition. the eight bits are shifted into the SSPSR register. All 2. Receive repeat of high byte address with R/W = 1, incoming bits are sampled with the rising edge of the indicating a read. clock line (SCL). 3. BF bit is set and the CKP bit is cleared, stopping SCL and indicating a read request. 17.2.4.1 7-bit Addressing 4. SSPBUF is written, setting BF, with the data to In 7-bit Addressing mode (Figure17-10), the value of send to the master device. register SSPSR<7:1> is compared to the value of 5. CKP is set in software, releasing the SCL line. register SSPADD<7:1>. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the 17.2.4.3 Address Masking addresses match, and the BF and SSPOV bits are The Address Masking register (SSPMSK) is only clear, the following events occur: accessible while the SSPM bits of the SSPCON • The SSPSR register value is loaded into the register are set to ‘1001’. In this register, the user can SSPBUF register. select which bits of a received address the hardware • The BF bit is set. will compare when determining an address match. Any • An ACK pulse is generated. bit that is set to a zero in the SSPMSK register, the • SSP interrupt flag bit, SSPIF of the PIR1 register, corresponding bit in the received address byte and is set (interrupt is generated if enabled) on the SSPADD register are ignored when determining an falling edge of the ninth SCL pulse. address match. By default, the register is set to all ones, requiring a complete match of a 7-bit address or 17.2.4.2 10-bit Addressing the lower eight bits of a 10-bit address. In 10-bit Address mode, two address bytes need to be received by the slave (Figure17-11). The five Most Significant bits (MSbs) of the first address byte specify if it is a 10-bit address. The R/W bit of the SSPSTAT register must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows for reception: 1. Load SSPADD register with high byte of address. 2. Receive first (high) byte of address (bits SSPIF, BF and UA of the SSPSTAT register are set). 3. Read the SSPBUF register (clears bit BF). 4. Clear the SSPIF flag bit. 5. Update the SSPADD register with second (low) byte of address (clears UA bit and releases the SCL line). 6. Receive low byte of address (bits SSPIF, BF and UA are set). 7. Update the SSPADD register with the high byte of address. If match releases SCL line, this will clear bit UA. 8. Read the SSPBUF register (clears bit BF). 9. Clear flag bit SSPIF.  2010-2016 Microchip Technology Inc. DS40001417C-page 157

PIC16(L)F722A/723A 17.2.5 RECEPTION When the R/W bit of the received address byte is clear, the master will write data to the slave. If an address match occurs, the received address is loaded into the SSPBUF register. An address byte overflow will occur if that loaded address is not read from the SSPBUF before the next complete byte is received. An SSP interrupt is generated for each data transfer byte. The BF, R/W and D/A bits of the SSPSTAT register are used to determine the status of the last received byte. FIGURE 17-10: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) R/W = 0 Receiving Address ACK Receiving Data ACK Receiving Data ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF Cleared in software Bus Master sends Stop condition BF SSPBUF register is read SSPOV Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. DS40001417C-page 158  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 17-11: I2C SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS) ACKACK 9P Bus mastersends Stopcondition SSPOV is setbecause SSPBUF isstill full. ACK is not sent. 0 D 8 1 D 7 e a Byte D3D2 56 n softwar eceive Dat D4D5 34 Cleared i R D6 2 7 D 1 K C 9 A D0 8 untilD has Receive Data Byte D4D2D5D3D1D6 234576 Cleared in software Cleared by hardware whenSSPADD is updated with highbyte of address d low SPAD D7 1 Clock is helupdate of Staken place ACK A0 89 Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of Address ACKA6A5A4A7A3A2A1 91234567 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardwarewhen SSPADD is updatedwith low byte of address UA is set indicatingthat SSPADD needs tobe updated eive First Byte of Address R/WA8A900111 2345786 Cleared in software SSPBUF is writtenwith contents of SSPSR UA is set indicatingthat the SSPADD needs tobe updated c Re 1 1 S SDA SCL SSPIF BF SSPOV UA KP C  2010-2016 Microchip Technology Inc. DS40001417C-page 159

PIC16(L)F722A/723A 17.2.6 TRANSMISSION Following the eighth falling clock edge, control of the SDA line is released back to the master so that the When the R/W bit of the received address byte is set master can acknowledge or not acknowledge the and an address match occurs, the R/W bit of the response. If the master sends a not acknowledge, the SSPSTAT register is set and the slave will respond to slave’s transmission is complete and the slave must the master by reading out data. After the address match, monitor for the next Start condition. If the master an ACK pulse is generated by the slave hardware and acknowledges, control of the bus is returned to the the SCL pin is held low (clock is automatically stretched) slave to transmit another byte of data. Just as with the until the slave is ready to respond. See Section17.2.7 previous byte, the clock is stretched by the slave, data “Clock Stretching”. The data the slave will transmit must be loaded into the SSPBUF and CKP must be set must be loaded into the SSPBUF register, which sets to release the clock line (SCL). the BF bit. The SCL line is released by setting the CKP bit of the SSPCON register. An SSP interrupt is generated for each transferred data byte. The SSPIF flag bit of the PIR1 register initiates an SSP interrupt, and must be cleared by software before the next byte is transmitted. The BF bit of the SSPSTAT register is cleared on the falling edge of the eighth received clock pulse. The SSPIF flag bit is set on the falling edge of the ninth clock pulse. FIGURE 17-12: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address R/W Transmitting Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Data in SCL held low sampled while CPU responds to SSPIF SSPIF Cleared in software BF Dummy reatdo ocfl eSaSr PBBFU flFag SSPBUF is written in software SFreormvic SeS RPo uIntitneerrupt CKP Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) DS40001417C-page 160  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 2 FIGURE 17-13: I C SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS) Bus Mastersends Stopconditionck is held low untilP is set to ‘’1 ACKTransmitting Data Byte D7D6D5D4D3D1D2D0 123457896P Cleared in software Write of SSPBUFCompletion ofDummy read of SSPBUFdata transmissionto clear BF flagclears BF flag CKP is set in software, initiates transmission CKP is automatically cleared in hardware holding SCL low CloCK CK = 1 A 9 W R/ 8 8 s A 7 s Bus Mastersends Restartscondition Receive First Byte of Addre 11110A9 123456Sr Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with highbyte of address. K Clock is held low untilClock is held low untilupdate of SSPADD has update of SSPADD hastaken placetaken place0Receive Second Byte of Address ACA7A6A5A4A3A2A1A0K 9123456789 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address. UA is set indicating thatSSPADD needs to beupdated R/W = e First Byte of Address 110A9A8AC 345678 SSPBUF is written withcontents of SSPSR UA is set indicating thatthe SSPADD needs to beupdated eiv 1 2 c e R 1 1 S F SDA SCL SSPI BF UA CKP  2010-2016 Microchip Technology Inc. DS40001417C-page 161

PIC16(L)F722A/723A 17.2.7 CLOCK STRETCHING Refer to Application Note AN554, Software During any SCL low phase, any device on the I2C bus Implementation of I2C™ Bus Master (DS00554) for more information. may hold the SCL line low and delay, or pause, the transmission of data. This “stretching” of a transmission 17.2.9 MULTI-MASTER MODE allows devices to slow down communication on the bus. The SCL line must be constantly sampled by the In Multi-Master mode, the interrupt generation on the master to ensure that all devices on the bus have detection of the Start and Stop conditions allow the released SCL for more data. determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP Stretching usually occurs after an ACK bit of a module is disabled. The Stop (P) and Start (S) bits will transmission, delaying the first bit of the next byte. The toggle based on the Start and Stop conditions. Control SSP module hardware automatically stretches for two of the I2C bus may be taken when the P bit of the conditions: SSPSTAT register is set or when the bus is Idle, and • After a 10-bit address byte is received (update both the S and P bits are clear. When the bus is busy, SSPADD register) enabling the SSP Interrupt will generate the interrupt • Anytime the CKP bit of the SSPCON register is when the Stop condition occurs. cleared by hardware In Multi-Master operation, the SDA line must be The module will hold SCL low until the CKP bit is set. monitored to see if the signal level is the expected This allows the user slave software to update SSPBUF output level. This check only needs to be done when a with data that may not be readily available. In 10-bit high level is output. If a high level is expected and a low addressing modes, the SSPADD register must be level is present, the device needs to release the SDA updated after receiving the first and second address and SCL lines (set TRIS bits). There are two stages bytes. The SSP module will hold the SCL line low until where this arbitration of the bus can be lost. They are the SSPADD has a byte written to it. The UA bit of the the address transfer and data transfer stages. SSPSTAT register will be set, along with SSPIF, When the slave logic is enabled, the slave continues to indicating an address update is needed. receive. If arbitration was lost during the address transfer stage, communication to the device may be in 17.2.8 FIRMWARE MASTER MODE progress. If addressed, an ACK pulse will be Master mode of operation is supported in firmware generated. If arbitration was lost during the data using interrupt generation on the detection of the Start transfer stage, the device will need to re-transfer the and Stop conditions. The Stop (P) and Start (S) bits of data at a later time. the SSPSTAT register are cleared from a Reset or Refer to Application Note AN578, Use of the SSP when the SSP module is disabled (SSPEN cleared). Module in the I2C™ Multi-Master Environment The Stop (P) and Start (S) bits will toggle based on the (DS00578) for more information. Start and Stop conditions. Control of the I2C bus may be taken when the P bit is set or the bus is Idle and both the S and P bits are clear. In Firmware Master mode, the SCL and SDA lines are manipulated by setting/clearing the corresponding TRIS bit(s). The output level is always low, irrespective of the value(s) in the corresponding PORT register bit(s). When transmitting a ‘1’, the TRIS bit must be set (input) and a ‘0’, the TRIS bit must be clear (output). The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt will occur if enabled): • Start condition • Stop condition • Data transfer byte transmitted/received Firmware Master mode of operation can be done with either the Slave mode Idle (SSPM<3:0>=1011), or with either of the Slave modes in which interrupts are enabled. When both master and slave functionality is enabled, the software needs to differentiate the source(s) of the interrupt. DS40001417C-page 162  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 17.2.10 CLOCK SYNCHRONIZATION 17.2.11 SLEEP OPERATION When the CKP bit is cleared, the SCL output is held low While in Sleep mode, the I2C module can receive once it is sampled low. Therefore, the CKP bit will not addresses of data, and when an address match or stretch the SCL line until an external I2C master device complete byte transfer occurs, wake the processor has already asserted the SCL line low. The SCL output from Sleep (if SSP interrupt is enabled). will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high-time requirement for SCL (Figure17-14). FIGURE 17-14: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX-1 SCL Master device asserts clock CKP Master device deasserts clock WR SSPCON  2010-2016 Microchip Technology Inc. DS40001417C-page 163

PIC16(L)F722A/723A REGISTER 17-3: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Release control of SCL 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = Reserved 1001 = Load SSPMSK register at SSPADD SFR Address(1) 1010 = Reserved 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: When this mode is selected, any reads or writes to the SSPADD SFR address accesses the SSPMSK register. 2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit. DS40001417C-page 164  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A REGISTER 17-4: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: SPI Data Input Sample Phase bit 1 = Slew Rate Control (limiting) disabled. Operating in I2C Standard mode (100kHz and 1MHz). 0 = Slew Rate Control (limiting) enabled. Operating in I2C Fast mode (400kHz). bit 6 CKE: SPI Clock Edge Select bit This bit must be maintained clear. Used in SPI mode only. bit 5 D/A: DATA/ADDRESS bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit This bit is cleared when the SSP module is disabled, or when the Start bit is detected last. 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last. 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: READ/WRITE bit Information This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or ACK bit. 1 = Read 0 = Write bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit: 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty  2010-2016 Microchip Technology Inc. DS40001417C-page 165

PIC16(L)F722A/723A REGISTER 17-5: SSPMSK: SSP MASK REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave Mode, 10-bit Address I2C Slave Mode, 10-bit Address (SSPM<3:0> = 0111): 1 = The received address bit ‘0’ is compared to SSPADD<0> to detect I2C address match 0 = The received address bit ‘0’ is not used to detect I2C address match All other SSP modes: this bit has no effect. REGISTER 17-6: SSPADD: SSP I2C ADDRESS REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADD<7:0>: Address bits Received address TABLE 17-7: SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 36 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 39 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 37 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 147 SSPADD Synchronous Serial Port (I2C mode) Address Register 155 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 164 SSPMSK(2) Synchronous Serial Port (I2C mode) Address Mask Register 166 SSPSTAT SMP(1) CKE(1) D/A P S R/W UA BF 165 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 62 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in I2C mode. Note 1: Maintain these bits clear in I2C mode. 2: Accessible only when SSPM<3:0> = 1001. DS40001417C-page 166  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 18.0 PROGRAM MEMORY READ The value written to the PMADRH:PMADRL register pair determines which program memory location is The Flash program memory is readable during normal read. The read operation will be initiated by setting the operation over the full VDD range of the device. To read RD bit of the PMCON1 register. The program memory data from program memory, five Special Function Flash controller takes two instructions to complete the Registers (SFRs) are used: read. As a consequence, after the RD bit has been set, • PMCON1 the next two instructions will be ignored. To avoid conflict with program execution, it is recommended that • PMDATL the two instructions following the setting of the RD bit • PMDATH are NOP. When the read completes, the result is placed • PMADRL in the PMDATLH:PMDATL register pair. Refer to • PMADRH Example18-1 for sample code. Note: Code-protect does not effect the CPU from performing a read operation on the program memory. For more information, refer to Section8.2 “Code Protection” EXAMPLE 18-1: PROGRAM MEMORY READ BANKSELPMADRL ; MOVF MS_PROG_ADDR, W; MOVWF PMADRH ;MS Byte of Program Address to read MOVF LS_PROG_ADDR, W; MOVWF PMADRL ;LS Byte of Program Address to read BANKSELPMCON1 ; RequiredSequence BNNSOOFPP PMCON1, ;RADn;yI niintsitartuec tRieoands here are ignored as program ;memory is read in second cycle after BSF BANKSELPMDATL ; MOVF PMDATL, W;W = LS Byte of Program Memory Read MOVWF LOWPMBYTE; MOVF PMDATH, W;W = MS Byte of Program Memory Read MOVWF HIGHPMBYTE;  2010-2016 Microchip Technology Inc. DS40001417C-page 167

PIC16(L)F722A/723A REGISTER 18-1: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER R-1 U-0 U-0 U-0 U-0 U-0 U-0 R/S-0 Reserved — —l — — — — RD bit 7 bit 0 Legend: S = Setable bit, cleared in hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Reserved: Read as ‘1’. Maintain this bit set. bit 6-1 Unimplemented: Read as ‘0’ bit 0 RD: Read Control bit 1 = Initiates an program memory read (The RD is cleared in hardware; the RD bit can only be set (not cleared) in software). 0 = Does not initiate a program memory read REGISTER 18-2: PMDATH: PROGRAM MEMORY DATA HIGH REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — PMD13 PMD12 PMD11 PMD10 PMD9 PMD8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a Program Memory Read command. REGISTER 18-3: PMDATL: PROGRAM MEMORY DATA LOW REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PMD7 PMD6 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after a Program Memory Read command. DS40001417C-page 168  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A REGISTER 18-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — PMA12 PMA11 PMA10 PMA9 PMA8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PMA<12:8>: Program Memory Read Address bits REGISTER 18-5: PMADRL: PROGRAM MEMORY ADDRESS LOW REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 PMA<7:0>: Program Memory Read Address bits TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY READ Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page PMCON1 Reserved — — — — — — RD 168 PMADRH — — — Program Memory Read Address Register High Byte 169 PMADRL Program Memory Read Address Register Low Byte 169 PMDATH — — Program Memory Read Data Register High Byte 168 PMDATL Program Memory Read Data Register Low Byte 168 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Program Memory Read.  2010-2016 Microchip Technology Inc. DS40001417C-page 169

PIC16(L)F722A/723A 19.0 POWER-DOWN MODE (SLEEP) The following peripheral interrupts can wake the device from Sleep: The Power-down mode is entered by executing a 1. TMR1 Interrupt. Timer1 must be operating as an SLEEP instruction. asynchronous counter. If the Watchdog Timer is enabled: 2. USART Receive Interrupt (Synchronous Slave • WDT will be cleared but keeps running. mode only) • PD bit of the STATUS register is cleared. 3. A/D conversion (when A/D clock source is RC) • TO bit of the STATUS register is set. 4. Interrupt-on-change • Oscillator driver is turned off. 5. External Interrupt from INT pin • Timer1 oscillator is unaffected 6. Capture event on CCP1 or CCP2 • I/O ports maintain the status they had before 7. SSP Interrupt in SPI or I2C Slave mode SLEEP was executed (driving high, low or high- Other peripherals cannot generate interrupts since impedance). during Sleep, no on-chip clocks are present. For lowest current consumption in this mode, all I/O When the SLEEP instruction is being executed, the next pins should be either at VDD or VSS, with no external instruction (PC + 1) is pre-fetched. For the device to circuitry drawing current from the I/O pin. I/O pins that wake-up through an interrupt event, the corresponding are high-impedance inputs should be pulled high or low interrupt enable bit must be set (enabled). Wake-up is externally to avoid switching currents caused by float- regardless of the state of the GIE bit. If the GIE bit is ing inputs. The T0CKI input should also be at VDD or clear (disabled), the device continues execution at the VSS for lowest current consumption. The contribution instruction after the SLEEP instruction. If the GIE bit is from on-chip pull ups on PORTB should be considered. set (enabled), the device executes the instruction after The MCLR pin must be at a logic high level when the SLEEP instruction, then branches to the interrupt external MCLR is enabled. address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user Note: A Reset generated by a WDT time out should have a NOP after the SLEEP instruction. does not drive MCLR pin low. Note: If the global interrupts are disabled (GIE is 19.1 Wake-up from Sleep cleared), but any interrupt source has both its interrupt enable bit and the The device can wake-up from Sleep through one of the corresponding interrupt flag bits set, the following events: device will immediately wake-up from Sleep. The SLEEP instruction is 1. External Reset input on MCLR pin. completely executed. 2. Watchdog Timer wake-up (if WDT was enabled). The WDT is cleared when the device wakes up from 3. Interrupt from RB0/INT pin, PORTB change or a Sleep, regardless of the source of wake-up. peripheral interrupt. The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. DS40001417C-page 170  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 19.2 Wake-up Using Interrupts Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to When global interrupts are disabled (GIE cleared) and become set before the SLEEP instruction completes. To any interrupt source has both its interrupt enable bit determine whether a SLEEP instruction executed, test and interrupt flag bit set, one of the following will occur: the PD bit. If the PD bit is set, the SLEEP instruction • If the interrupt occurs before the execution of a was executed as a NOP. SLEEP instruction, the SLEEP instruction will To ensure that the WDT is cleared, a CLRWDT instruction complete as a NOP. Therefore, the WDT and WDT should be executed before a SLEEP instruction. prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. FIGURE 19-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) CLKOUT(4) TOST(2) INT pin INTF flag (INTCON reg.) Interrupt Latency(3) GIE bit Processor in (INTCON reg.) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC - 1) Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. 3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. 4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference. TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 53 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 36 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 37 PIE2 — — — — — — — CCP2IE 38 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 39 PIR2 — — — — — — — CCP2IF 40 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.  2010-2016 Microchip Technology Inc. DS40001417C-page 171

PIC16(L)F722A/723A 20.0 IN-CIRCUIT SERIAL The device is placed into Program/Verify mode by PROGRAMMING™ (ICSP™) holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP from 0v to VPP. In ICSP™ programming allows customers to manufacture Program/Verify mode the Program Memory, User IDs circuit boards with unprogrammed devices. Programming and the Configuration Words are programmed through can be done after the assembly process allowing the serial communications. The ICSPDAT pin is a device to be programmed with the most recent firmware bidirectional I/O used for transferring the serial data and or a custom firmware. Five pins are needed for ICSP™ the ISCPCLK pin is the clock input. For more information programming: on ICSP™ refer to the “PIC16(L)F72X Memory • ICSPCLK Programming Specification” (DS41332). • ICSPDAT Note: The ICD 2 produces a VPP voltage greater • MCLR/VPP than the maximum VPP specification of the • VDD PIC16(L)F722A/723A. When using this • VSS programmer, an external circuit, such as the AC164112 MPLAB ICD 2 VPP voltage limiter, is required to keep the VPP voltage within the device specifications. FIGURE 20-1: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming VDD Device to be Signals Programmed VDD VDD 10k VPP MCLR/VPP GND VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). DS40001417C-page 172  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 21.0 INSTRUCTION SET SUMMARY TABLE 21-1: OPCODE FIELD DESCRIPTIONS The PIC16(L)F722A/723A instruction set is highly orthogonal and is comprised of three basic categories: Field Description • Byte-oriented operations f Register file address (0x00 to 0x7F) • Bit-oriented operations W Working register (accumulator) • Literal and control operations b Bit address within an 8-bit file register Each PIC16 instruction is a 14-bit word divided into an k Literal field, constant data or label opcode, which specifies the instruction type and one or x Don’t care location (= 0 or 1). more operands, which further specify the operation of The assembler will generate code with x = 0. the instruction. The formats for each of the categories It is the recommended form of use for is presented in Figure21-1, while the various opcode compatibility with all Microchip software tools. fields are summarized in Table21-1. d Destination select; d = 0: store result in W, Table21-2 lists the instructions recognized by the d = 1: store result in file register f. MPASMTM assembler. Default is d = 1. For byte-oriented instructions, ‘f’ represents a file PC Program Counter register designator and ‘d’ represents a destination TO Time-out bit designator. The file register designator specifies which C Carry bit file register is to be used by the instruction. DC Digit carry bit The destination designator specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is Z Zero bit placed in the W register. If ‘d’ is one, the result is placed PD Power-down bit in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field FIGURE 21-1: GENERAL FORMAT FOR designator, which selects the bit affected by the INSTRUCTIONS operation, while ‘f’ represents the address of the file in which the bit is located. Byte-oriented file register operations 13 8 7 6 0 For literal and control operations, ‘k’ represents an 8- OPCODE d f (FILE #) bit or 11-bit constant, or literal value. d = 0 for destination W One instruction cycle consists of four oscillator periods; d = 1 for destination f for an oscillator frequency of 4 MHz, this gives a f = 7-bit file register address nominal instruction execution time of 1s. All instructions are executed within a single instruction Bit-oriented file register operations cycle, unless a conditional test is true, or the program 13 10 9 7 6 0 counter is changed as a result of an instruction. When OPCODE b (BIT #) f (FILE #) this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. b = 3-bit bit address f = 7-bit file register address All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a Literal and control operations hexadecimal digit. General 21.1 Read-Modify-Write Operations 13 8 7 0 OPCODE k (literal) Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) k = 8-bit immediate value operation. The register is read, the data is modified, and the result is stored according to either the instruc- CALL and GOTO instructions only tion, or the destination designator ‘d’. A read operation 13 11 10 0 is performed on a register even if the instruction writes OPCODE k (literal) to that register. k = 11-bit immediate value For example, a CLRF PORTB instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unin- tended consequence of clearing the condition that set the RBIF flag.  2010-2016 Microchip Technology Inc. DS40001417C-page 173

PIC16(L)F722A/723A TABLE 21-2: PIC16(L)F722A/723A INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP – No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call Subroutine 2 10 0kkk kkkk kkkk CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE – Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS40001417C-page 174  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 21.2 Instruction Descriptions ADDLW Add literal and W BCF Bit Clear f Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b Operands: 0  k  255 Operands: 0  f  127 0  b  7 Operation: (W) + k  (W) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: The contents of the W register are added to the 8-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared. and the result is placed in the W register. ADDWF Add W and f BSF Bit Set f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b Operands: 0  f  127 Operands: 0  f  127 d 0,1 0  b  7 Operation: (W) + (f)  (destination) Operation: 1  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set. with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSC f,b Operands: 0  k  255 Operands: 0  f  127 0  b  7 Operation: (W) .AND. (k)  (W) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: The contents of W register are AND’ed with the 8-bit literal ‘k’. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next The result is placed in the W reg- instruction is executed. ister. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. ANDWF AND W with f Syntax: [ label ] ANDWF f,d Operands: 0  f  127 d 0,1 Operation: (W) .AND. (f)  (destination) Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.  2010-2016 Microchip Technology Inc. DS40001417C-page 175

PIC16(L)F722A/723A BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0  f  127 Operands: None 0  b < 7 Operation: 00h  WDT Operation: skip if (f<b>) = 1 0  WDT prescaler, 1  TO Status Affected: None 1  PD Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Status Affected: TO, PD instruction is executed. If bit ‘b’ is ‘1’, then the next Description: CLRWDT instruction resets the instruction is discarded and a NOP Watchdog Timer. It also resets the is executed instead, making this a prescaler of the WDT. 2-cycle instruction. Status bits TO and PD are set. CALL Call Subroutine COMF Complement f Syntax: [ label ] CALL k Syntax: [ label ] COMF f,d Operands: 0  k  2047 Operands: 0  f  127 Operation: (PC)+ 1 TOS, d  [0,1] k  PC<10:0>, Operation: (f)  (destination) (PCLATH<4:3>)  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are Description: Call Subroutine. First, return complemented. If ‘d’ is ‘0’, the address (PC + 1) is pushed onto result is stored in W. If ‘d’ is ‘1’, the stack. The 11-bit immediate the result is stored back in address is loaded into PC bits register ‘f’. <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a 2-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Decrement register ‘f’. If ‘d’ is ‘0’, cleared and the Z bit is set. the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h  (W) 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS40001417C-page 176  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. If the result is ‘1’, the next If the result is ‘1’, the next instruction is executed. If the instruction is executed. If the result is ‘0’, then a NOP is result is ‘0’, a NOP is executed executed instead, making it a instead, making it a 2-cycle 2-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<4:3>  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the 8-bit literal ‘k’. The The 11-bit immediate value is result is placed in the loaded into PC bits <10:0>. The W register. upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Inclusive OR the W register with incremented. If ‘d’ is ‘0’, the result register ‘f’. If ‘d’ is ‘0’, the result is is placed in the W register. If ‘d’ is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’.  2010-2016 Microchip Technology Inc. DS40001417C-page 177

PIC16(L)F722A/723A MOVF Move f MOVWF Move W to f Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: (W)  (f) Operation: (f)  (dest) Status Affected: None Status Affected: Z Description: Move data from W register to Description: The contents of register f is register ‘f’. moved to a destination dependent Words: 1 upon the status of d. If d = 0, Cycles: 1 destination is W register. If d = 1, the destination is file register f Example: MOVW OPTION itself. d = 1 is useful to test a file F register since status flag Z is Before Instruction affected. OPTION= 0xFF Words: 1 W = 0x4F After Instruction Cycles: 1 OPTION= 0x4F Example: MOVF FSR, 0 W = 0x4F After Instruction W = value in FSR register Z = 1 MOVLW Move literal to W NOP No Operation Syntax: [ label ] MOVLW k Syntax: [ label ] NOP Operands: 0  k  255 Operands: None Operation: k  (W) Operation: No operation Status Affected: None Status Affected: None Description: The 8-bit literal ‘k’ is loaded into W Description: No operation. register. The “don’t cares” will Words: 1 assemble as ‘0’s. Cycles: 1 Words: 1 Example: NOP Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A DS40001417C-page 178  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k Operands: None Operands: 0  k  255 Operation: TOS  PC, Operation: k  (W); 1  GIE TOS  PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is Description: The W register is loaded with the POPed and Top-of-Stack (TOS) is 8-bit literal ‘k’. The program loaded in the PC. Interrupts are counter is loaded from the top of enabled by setting Global the stack (the return address). Interrupt Enable bit, GIE This is a 2-cycle instruction. (INTCON<7>). This is a 2-cycle Words: 1 instruction. Cycles: 2 Words: 1 Example: CALL TABLE;W contains Cycles: 2 table Example: RETFIE ;offset value TABLE • ;W now has table value After Interrupt • PC = TOS • GIE= 1 ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS  PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a 2-cycle instruc- tion.  2010-2016 Microchip Technology Inc. DS40001417C-page 179

PIC16(L)F722A/723A RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP Operands: 0  f  127 Operands: None d  [0,1] Operation: 00h  WDT, Operation: See description below 0  WDT prescaler, 1  TO, Status Affected: C 0  PD Description: The contents of register ‘f’ are Status Affected: TO, PD rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is result is placed in the W register. cleared. Time-out Status bit, TO If ‘d’ is ‘1’, the result is stored is set. Watchdog Timer and its back in register ‘f’. prescaler are cleared. The processor is put into Sleep C Register f mode with the oscillator stopped. Words: 1 Cycles: 1 Example: RLF REG1,0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 1100 1100 C = 1 RRF Rotate Right f through Carry SUBLW Subtract W from literal Syntax: [ label ] RRF f,d Syntax: [ label ] SUBLW k Operands: 0  f  127 Operands: 0 k 255 d  [0,1] Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s Description: The contents of register ‘f’ are complement method) from the 8-bit rotated one bit to the right through literal ‘k’. The result is placed in the the Carry flag. If ‘d’ is ‘0’, the W register. result is placed in the W register. If ‘d’ is ‘1’, the result is placed C = 0 W  k back in register ‘f’. C = 1 W  k C Register f DC = 0 W<3:0>  k<3:0> DC = 1 W<3:0>  k<3:0> DS40001417C-page 180  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 f 127 Operands: 0 k 255 d  [0,1] Operation: (W) .XOR. k W) Operation: (f) - (W) destination) Status Affected: Z Status Affected: C, DC, Z Description: The contents of the W register Description: Subtract (2’s complement method) are XOR’ed with the 8-bit W register from register ‘f’. If ‘d’ is literal ‘k’. The result is placed in ‘0’, the result is stored in the W the W register. register. If ‘d’ is ‘1’, the result is stored back in register ‘f. C = 0 W  f C = 1 W  f DC = 0 W<3:0>  f<3:0> DC = 1 W<3:0>  f<3:0> SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f<3:0>)  (destination<7:4>), Operation: (W) .XOR. (f) destination) (f<7:4>)  (destination<3:0>) Status Affected: Z Status Affected: None Description: Exclusive OR the contents of the Description: The upper and lower nibbles of W register with register ‘f’. If ‘d’ is register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is stored in the W ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. placed in register ‘f’.  2010-2016 Microchip Technology Inc. DS40001417C-page 181

PIC16(L)F722A/723A 22.0 DEVELOPMENT SUPPORT 22.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker DS40001417C-page 182  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 22.2 MPLAB XC Compilers 22.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 22.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 22.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process  2010-2016 Microchip Technology Inc. DS40001417C-page 183

PIC16(L)F722A/723A 22.6 MPLAB X SIM Software Simulator 22.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 22.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 22.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 22.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS40001417C-page 184  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 22.11 Demonstration/Development 22.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2010-2016 Microchip Technology Inc. DS40001417C-page 185

PIC16(L)F722A/723A 23.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias.......................................................................................................-40°C to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F722A/723A ................................................................... -0.3V to +6.5V Voltage on VCAP pin with respect to VSS, PIC16F722A/723A ............................................................ -0.3V to +4.0V Voltage on VDD with respect to VSS, PIC16LF722A/723A ................................................................. -0.3V to +4.0V Voltage on MCLR with respect to Vss .................................................................................................-0.3V to +9.0V Voltage on all other pins with respect to VSS ............................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)...............................................................................................................................800 mW Maximum current out of VSS pin...................................................................................................................... 95 mA Maximum current into VDD pin......................................................................................................................... 70 mA Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA Maximum output current sunk by any I/O pin....................................................................................................25 mA Maximum output current sourced by any I/O pin...............................................................................................25 mA Maximum current sunk by all ports(2), -40°C  TA  +85°C for industrial........................................................200 mA Maximum current sunk by all ports(2), -40°C  TA  +125°C for extended........................................................90 mA Maximum current sourced by all ports(2), 40°C  TA  +85°C for industrial................................................... 140 mA Maximum current sourced by all ports(2), -40°C  TA  +125°C for extended...................................................65 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001417C-page 186  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 23.1 DC Characteristics: PIC16(L)F722A/723A-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) PIC16LF722A/723A Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F722A/723A Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. D001 VDD Supply Voltage PIC16LF722A/723A 1.8 — 3.6 V FOSC  16MHz: HFINTOSC, EC 1.8 — 3.6 V FOSC  4MHz 2.3 — 3.6 V FOSC  20MHz, EC 2.5 — 3.6 V FOSC  20MHz, HS D001 PIC16F722A/723A 1.8 — 5.5 V FOSC  16 MHz: HFINTOSC, EC 1.8 — 5.5 V FOSC  4 MHz 2.3 — 5.5 V FOSC  20 MHz, EC 2.5 — 5.5 V FOSC  20 MHz, HS D002* VDR RAM Data Retention Voltage(1) PIC16LF722A/723A 1.5 — — V Device in Sleep mode D002* PIC16F722A/723A 1.7 — — V Device in Sleep mode VPOR* Power-on Reset Release Voltage — 1.6 — V VPORR* Power-on Reset Rearm Voltage PIC16LF722A/723A — 0.8 — V Device in Sleep mode PIC16F722A/723A — 1.7 — V Device in Sleep mode D003 VFVR Fixed Voltage Reference Voltage, -5.5 — 5.5 % VFVR = 1.024V, VDD  2.5V Initial Accuracy -5.5 — 5.5 % VFVR = 2.048V, VDD  2.5V -5.5 — 5.5 % VFVR = 4.096V, VDD 4.75V; -40 TA85°C -6 — 6 % VFVR = 1.024V, VDD  2.5V -6 — 6 % VFVR = 2.048V, VDD  2.5V -6 — 6 % VFVR = 4.096V, VDD 4.75V; -40 TA125°C D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See Section3.2 “Power-on Reset Power-on Reset signal (POR)” for details. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.  2010-2016 Microchip Technology Inc. DS40001417C-page 187

PIC16(L)F722A/723A FIGURE 23-1: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) TPOR(3) Note 1: When NPOR is low, the device is held in Reset. 2: TPOR 1s typical. 3: TVLOW 2.7s typical. DS40001417C-page 188  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 23.2 DC Characteristics: PIC16(L)F722A/723A-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) PIC16LF722A/723A Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F722A/723A Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D009 LDO Regulator — 350 — A — HS, EC OR INTOSC/INTOSCIO (8-16MHZ) Clock modes with all VCAP pins disabled — 50 — A — All VCAP pins disabled — 30 — A — VCAP enabled on RA0, RA5 or RA6 — 5 — A — LP Clock mode and Sleep (requires FVR and BOR to be disabled) D010 — 7.0 12 A 1.8 FOSC = 32kHz — 9.0 14 A 3.0 LP Oscillator mode (Note 4), -40°C  TA  +85°C D010 — 11 20 A 1.8 FOSC = 32kHz — 14 22 A 3.0 LP Oscillator mode (Note 4), -40°C  TA  +85°C — 15 24 A 5.0 D011 — 7.0 12 A 1.8 FOSC = 32kHz — 9.0 18 A 3.0 LP Oscillator mode -40°C  TA  +125°C D011 — 11 21 A 1.8 FOSC = 32kHz — 14 25 A 3.0 LP Oscillator mode (Note 4) -40°C  TA  +125°C — 15 27 A 5.0 D011 — 110 150 A 1.8 FOSC = 1MHz — 150 215 A 3.0 XT Oscillator mode D011 — 120 175 A 1.8 FOSC = 1MHz — 180 250 A 3.0 XT Oscillator mode (Note 5) — 240 300 A 5.0 D012 — 230 300 A 1.8 FOSC = 4MHz — 400 600 A 3.0 XT Oscillator mode D012 — 250 350 A 1.8 FOSC = 4MHz — 420 650 A 3.0 XT Oscillator mode (Note 5) — 500 750 A 5.0 D013 — 125 180 A 1.8 FOSC = 1MHz — 230 270 A 3.0 EC Oscillator mode D013 — 150 205 A 1.8 FOSC = 1MHz — 225 320 A 3.0 EC Oscillator mode (Note 5) — 250 410 A 5.0 Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k 4: FVR and BOR are disabled. 5: 0.1F capacitor on VCAP (RA0).  2010-2016 Microchip Technology Inc. DS40001417C-page 189

PIC16(L)F722A/723A 23.2 DC Characteristics: PIC16(L)F722A/723A-I/E (Industrial, Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF722A/723A Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F722A/723A Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D014 — 290 330 A 1.8 FOSC = 4MHz — 460 500 A 3.0 EC Oscillator mode D014 — 300 430 A 1.8 FOSC = 4MHz — 450 655 A 3.0 EC Oscillator mode (Note 5) — 500 730 A 5.0 D015 — 100 130 A 1.8 FOSC = 500kHz — 120 150 A 3.0 MFINTOSC mode D015 — 115 195 A 1.8 FOSC = 500kHz — 135 200 A 3.0 MFINTOSC mode (Note 5) — 150 220 A 5.0 D016 — 650 800 A 1.8 FOSC = 8MHz — 1000 1200 A 3.0 HFINTOSC mode D016 — 625 850 A 1.8 FOSC = 8MHz — 1000 1200 A 3.0 HFINTOSC mode (Note 5) — 1100 1500 A 5.0 D017 — 1.0 1.2 mA 1.8 FOSC = 16MHz — 1.5 1.85 mA 3.0 HFINTOSC mode D017 — 1 1.2 mA 1.8 FOSC = 16MHz — 1.5 1.7 mA 3.0 HFINTOSC mode (Note 5) — 1.7 2.1 mA 5.0 D018 — 210 240 A 1.8 FOSC = 4MHz — 340 380 A 3.0 EXTRC mode (Note 3, Note 5) D018 — 225 320 A 1.8 FOSC = 4MHz — 360 445 A 3.0 EXTRC mode (Note 3, Note 5) — 410 650 A 5.0 D019 — 1.6 1.9 mA 3.0 FOSC = 20MHz — 2.0 2.8 mA 3.6 HS Oscillator mode D019 — 1.6 2 mA 3.0 FOSC = 20MHz — 1.9 3.2 mA 5.0 HS Oscillator mode (Note 5) Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k 4: FVR and BOR are disabled. 5: 0.1F capacitor on VCAP (RA0). DS40001417C-page 190  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 23.3 DC Characteristics: PIC16(L)F722A/723A-I/E (Power-Down) Standard Operating Conditions (unless otherwise stated) PIC16LF722A/723A Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F722A/723A Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D020 — 0.02 0.7 3.9 A 1.8 WDT, BOR, FVR, and T1OSC — 0.08 1.0 4.3 A 3.0 disabled, all Peripherals Inactive D020 — 4.3 10.2 17 A 1.8 WDT, BOR, FVR, and T1OSC — 5 10.5 18 A 3.0 disabled, all Peripherals Inactive — 5.5 11.8 21 A 5.0 D021 — 0.5 1.7 4.1 A 1.8 LPWDT Current (Note 1) — 0.8 2.5 4.8 A 3.0 D021 — 6 13.5 16.4 A 1.8 LPWDT Current (Note 1) — 6.5 14.5 16.8 A 3.0 — 7.5 16 18.7 A 5.0 D021A — 8.5 14 19 A 1.8 FVR current (Note 1. Note 3) — 8.5 14 20 A 3.0 D021A — 23 44 48 A 1.8 FVR current (Note 1, Note 3, — 25 45 55 A 3.0 Note 5) — 26 60 70 A 5.0 D022 — — — — A 1.8 BOR Current (Note 1, Note 3) — 7.5 12 22 A 3.0 D022 — — — — A 1.8 BOR Current (Note 1, Note 3, — 23 42 49 A 3.0 Note 5) — 25 46 50 A 5.0 D026 — 0.6 2 — A 1.8 T1OSC Current (Note 1) — 1.8 3.0 — A 3.0 D026 — 4.5 11.1 — A 1.8 T1OSC Current (Note 1) — 6 12.5 — A 3.0 — 7 13.5 — A 5.0 † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled. 4: A/D oscillator source is FRC. 5: 0.1F capacitor on VCAP (RA0).  2010-2016 Microchip Technology Inc. DS40001417C-page 191

PIC16(L)F722A/723A 23.3 DC Characteristics: PIC16(L)F722A/723A-I/E (Power-Down) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF722A/723A Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F722A/723A Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D027 — 0.06 0.7 5.0 A 1.8 A/D Current (Note 1, Note 4), no — 0.08 1.0 5.5 A 3.0 conversion in progress D027 — 6 10.7 18 A 1.8 A/D Current (Note 1, Note 4), no — 7 10.6 20 A 3.0 conversion in progress — 7.2 11.9 22 A 5.0 D027A — 250 400 — A 1.8 A/D Current (Note 1, Note 4), — 250 400 — A 3.0 conversion in progress D027A — 280 430 — A 1.8 A/D Current (Note 1, Note 4, — 280 430 — A 3.0 Note 5), conversion in progress — 280 430 — A 5.0 D028 — 2.2 3.2 14.4 A 1.8 Cap Sense Low Power — 3.3 4.4 15.6 A 3.0 Oscillator mode D028 — 6.5 13 21 A 1.8 Cap Sense Low Power — 8 14 23 A 3.0 Oscillator mode — 8 14 25 A 5.0 D028A — 4.2 6 17 A 1.8 Cap Sense Medium Power — 6 7 18 A 3.0 Oscillator mode D028A — 8.5 15.5 23 A 1.8 Cap Sense Medium Power — 11 17 24 A 3.0 Oscillator mode — 11 18 27 A 5.0 D028B — 12 14 25 A 1.8 Cap Sense High Power — 32 35 44 A 3.0 Oscillator mode D028B — 16 20 31 A 1.8 Cap Sense High Power — 36 41 50 A 3.0 Oscillator mode — 42 49 58 A 5.0 † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled. 4: A/D oscillator source is FRC. 5: 0.1F capacitor on VCAP (RA0). DS40001417C-page 192  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 23.4 DC Characteristics: PIC16(L)F722A/723A-I/E Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature-40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage I/O PORT: D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V D030A — — 0.15VDD V 1.8V  VDD  4.5V D031 with Schmitt Trigger buffer — — 0.2VDD V 2.0V  VDD  5.5V with I2C levels — — 0.3VDD V D032 MCLR, OSC1 (RC mode)(1) — — 0.2VDD V D033A OSC1 (HS mode) — — 0.3VDD V VIH Input High Voltage I/O ports: — — D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V D040A 0.25VDD + — — V 1.8V  VDD  4.5V 0.8 D041 with Schmitt Trigger buffer 0.8VDD — — V 2.0V  VDD  5.5V with I2C levels 0.7VDD — — V D042 MCLR 0.8VDD — — V D043A OSC1 (HS mode) 0.7VDD — — V D043B OSC1 (RC mode) 0.9VDD — — V (Note 1) IIL Input Leakage Current(2) D060 I/O ports — ± 5 ± 125 nA VSS  VPIN  VDD, Pin at high- impedance, 85°C ± 5 ± 1000 nA 125°C D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD, 85°C IPUR PORTB Weak Pull-up Current D070* 25 100 200 VDD = 3.3V, VPIN = VSS 25 140 300 A VDD = 5.0V, VPIN = VSS VOL Output Low Voltage(4) D080 I/O ports IOL = 8 mA, VDD = 5V — — 0.6 V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V VOH Output High Voltage(4) D090 I/O ports IOH = 3.5 mA, VDD = 5V VDD - 0.7 — — V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF Program Flash Memory Legend: TBD = To Be Determined * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode.  2010-2016 Microchip Technology Inc. DS40001417C-page 193

PIC16(L)F722A/723A 23.4 DC Characteristics: PIC16(L)F722A/723A-I/E (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature-40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. D130 EP Cell Endurance 100 1k — E/W Temperature during programming: 10°C  TA  40°C D131 VDD for Read VMIN — — V Voltage on MCLR/VPP during 8.0 — 9.0 V Temperature during programming: Erase/Program 10°C  TA  40°C VDD for Bulk Erase 2.7 3 — V Temperature during programming: 10°C  TA  40°C D132 VPEW VDD for Write or Row Erase 2.7 — — V VMIN = Minimum operating voltage VMAX = Maximum operating voltage IPPPGM Current on MCLR/VPP during — — 5.0 mA Temperature during programming: Erase/Write 10°C  TA  40°C IDDPGM Current on VDD during Erase/ — 5.0 mA Temperature during programming: Write 10°C  TA  40°C D133 TPEW Erase/Write cycle time — 2.8 ms Temperature during programming: 10°C  TA  40°C D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated VCAP Capacitor Charging D135 Charging current — 200 — A D135A Source/sink capability when — 0.0 — mA charging complete Legend: TBD = To Be Determined * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode. DS40001417C-page 194  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 23.5 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance Junction to Ambient 60.0 C/W 28-pin SPDIP package 69.7 C/W 28-pin SOIC package 71.0 C/W 28-pin SSOP package 52.5 C/W 28-pin UQFN 4x4mm package 30.0 C/W 28-pin QFN 6x6mm package TH02 JC Thermal Resistance Junction to Case 29.0 C/W 28-pin SPDIP package 18.9 C/W 28-pin SOIC package 24.0 C/W 28-pin SSOP package 16.7 C/W 28-pin UQFN 4x4mm package 5.0 C/W 28-pin QFN 6x6mm package TH03 TJMAX Maximum Junction Temperature 150 C TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature 3: TJ = Junction Temperature  2010-2016 Microchip Technology Inc. DS40001417C-page 195

PIC16(L)F722A/723A 23.6 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O PORT t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 23-2: LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins, 15 pF for OSC2 output DS40001417C-page 196  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 23.7 AC Characteristics: PIC16F722A/723A-I/E FIGURE 23-3: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) FIGURE 23-4: PIC16F722A/723A VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C 5.5 V) 3.6 ( D D V 2.5 2.3 2.0 1.8 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table23-1 for each Oscillator mode’s supported frequencies.  2010-2016 Microchip Technology Inc. DS40001417C-page 197

PIC16(L)F722A/723A FIGURE 23-5: PIC16LF722A/723A VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C V) 3.6 ( D D V 2.5 2.3 2.0 1.8 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table23-1 for each Oscillator mode’s supported frequencies. FIGURE 23-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 + 5% 85 ± 3% C) ° 60 ( e r u at r e ± 2% p 25 m e T 0 -20 + 5% -40 1.8 2.0 2.5 3.0 3.3(2)3.5 4.0 4.5 5.0 5.5 VDD (V) Note 1: This chart covers both regulator enabled and regulator disabled states. 2: Regulator Nominal voltage. DS40001417C-page 198  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 23-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode DC — 4 MHz XT Oscillator mode DC — 20 MHz HS Oscillator mode DC — 20 MHz EC Oscillator mode Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 20 MHz HS Oscillator mode, VDD 2.7V DC — 4 MHz RC Oscillator mode OS02 TOSC External CLKIN Period(1) 27 —  s LP Oscillator mode 250 —  ns XT Oscillator mode 50 —  ns HS Oscillator mode 50 —  ns EC Oscillator mode Oscillator Period(1) — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode, VDD 2.7V 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC OS04* TosH, External CLKIN High, 2 — — s LP oscillator TosL External CLKIN Low 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TosR, External CLKIN Rise, 0 —  ns LP oscillator TosF External CLKIN Fall 0 —  ns XT oscillator 0 —  ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.  2010-2016 Microchip Technology Inc. DS40001417C-page 199

PIC16(L)F722A/723A TABLE 23-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Freq. Sym. Characteristic Min. Typ† Max. Units Conditions No. Tolerance OS08 HFOSC Internal Calibrated HFINTOSC 2% — 16.0 — MHz 0°C  TA  +85°C, Frequency(2) VDD 2.5V 5% — 16.0 — MHz -40°C  TA  +125°C OS08A MFOSC Internal Calibrated MFINTOSC 2% — 500 — kHz 0°C  TA  +85°C Frequency(2) VDD 2.5V 5% — 500 10 kHz -40°C  TA  +125°C OS10* TIOSC ST HFINTOSC Wake-up from Sleep — — 5 8 s Start-up Time MFINTOSC Wake-up from Sleep — — 20 30 s Start-up Time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. 3: By design. FIGURE 23-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19 DS40001417C-page 200  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 23-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS11 TosH2ckL Fosc to CLKOUT (1) — — 70 ns VDD = 3.3-5.0V OS12 TosH2ckH Fosc to CLKOUT (1) — — 72 ns VDD = 3.3-5.0V OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3-5.0V OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns VDD = 3.3-5.0V (I/O in hold time) OS17 TioV2osH Port input valid to Fosc(Q2 cycle) 20 — — ns (I/O in setup time) OS18 TioR Port output rise time(2) — 40 72 ns VDD = 2.0V — 15 32 VDD = 3.3-5.0V OS19 TioF Port output fall time(2) — 28 55 ns VDD = 2.0V — 15 30 VDD = 3.3-5.0V OS20* Tinp INT pin input high or low time 25 — — ns OS21* Trbp PORTB interrupt-on-change new input TCY — — ns level time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode. FIGURE 23-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low.  2010-2016 Microchip Technology Inc. DS40001417C-page 201

PIC16(L)F722A/723A FIGURE 23-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2ms delay if PWRTE = 0 and VREGEN=1. DS40001417C-page 202  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 23-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s VDD = 3.3-5V, -40°C to +85°C 5 — — s VDD = 3.3-5V 31 TWDTLP Low Power Watchdog Timer Time- 10 18 27 ms VDD = 3.3V-5V out Period (No Prescaler) 32 TOST Oscillator Start-up Timer Period(1), (2) — 1024 — Tosc (Note 3) 33* TPWRT Power-up Timer Period, PWRTE=0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low — — 2.0 s or Watchdog Timer Reset 35 VBOR Brown-out Reset Voltage 2.38 2.5 2.73 V BORV=2.5V 1.80 1.9 2.11 BORV=1.9V 36* VHYST Brown-out Reset Hysteresis 0 25 50 mV -40°C to +85°C 37* TBORDC Brown-out Reset DC Response 1 3 5 s VDD  VBOR, -40°C to +85°C Time 10 VDD  VBOR * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. FIGURE 23-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1  2010-2016 Microchip Technology Inc. DS40001417C-page 203

PIC16(L)F722A/723A TABLE 23-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value Period 30 or TCY + 40 (1, 2, 4, 8) N Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range 32.4 32.768 33.1 kHz (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync mode Increment * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 23-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure23-2 for load conditions. TABLE 23-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. CC01* TccL CCPx Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCPx Input Period 3TCY + 40 — — ns N = prescale value (1, 4 or 16) N * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001417C-page 204  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 23-7: PIC16F722A/723A A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD01 NR Resolution — — 8 bit AD02 EIL Integral Error — — ±1.7 LSb VREF = 3.0V AD03 EDL Differential Error — — ±1 LSb No missing codes VREF = 3.0V AD04 EOFF Offset Error — — ±2.2 LSb VREF = 3.0V AD05 EGN Gain Error — — ±1.5 LSb VREF = 3.0V AD06 VREF Reference Voltage(3) 1.8 — VDD V AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended Impedance of — — 50 k Can go higher if external 0.01F capacitor is Analog Voltage Source present on input pin. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. TABLE 23-8: PIC16F722A/723A A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD130* TAD A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal RC Oscillator 1.0 2.0 6.0 s ADCS<1:0> = 11 (ADRC mode) Period AD131 TCNV Conversion Time (not including — 10.5 — TAD Set GO/DONE bit to conversion Acquisition Time)(1) complete AD132* TACQ Acquisition Time — 1.0 — s * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle.  2010-2016 Microchip Technology Inc. DS40001417C-page 205

PIC16(L)F722A/723A FIGURE 23-12: PIC16F722A/723A A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 (TOSC/2(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. FIGURE 23-13: PIC16F722A/723A A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. DS40001417C-page 206  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 23-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US120 US122 Note: Refer to Figure23-2 for load conditions. TABLE 23-9: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. US120 TCKH2DTV SYNC XMIT (Master and Slave) 3.0-5.5V — 80 ns Clock high to data-out valid 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time 3.0-5.5V — 45 ns (Master mode) 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns FIGURE 23-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure23-2 for load conditions. TABLE 23-10: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK  (DT hold time) 10 — ns US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns  2010-2016 Microchip Technology Inc. DS40001417C-page 207

PIC16(L)F722A/723A FIGURE 23-16: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SCK (CKP = 1) SP79 SP78 SP80 SDO MSb bit 6 - - - - - -1 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure23-2 for load conditions. FIGURE 23-17: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SP78 SDO MSb bit 6 - - - - - -1 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure23-2 for load conditions. DS40001417C-page 208  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 23-18: SPI SLAVE MODE TIMING (CKE=0) SS SP70 SCK SP83 (CKP = 0) SP71 SP72 SP78 SP79 SCK (CKP = 1) SP79 SP78 SP80 SDO MSb bit 6 - - - - - -1 LSb SP75, SP76 SP77 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure23-2 for load conditions. FIGURE 23-19: SPI SLAVE MODE TIMING (CKE=1) SP82 SS SP70 SCK SP83 (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure23-2 for load conditions.  2010-2016 Microchip Technology Inc. DS40001417C-page 209

PIC16(L)F722A/723A TABLE 23-11: SPI MODE REQUIREMENTS Param Symbol Characteristic Min. Typ† Max. Units Conditions No. SP70* TSSL2SCH, SS to SCK or SCK input TCY — — ns TSSL2SCL SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns SP73* TDIV2SCH, Setup time of SDI data input to SCK edge 100 — — ns TDIV2SCL SP74* TSCH2DIL, Hold time of SDI data input to SCK edge 100 — — ns TSCL2DIL SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns 1.8-5.5V — 25 50 ns SP76* TDOF SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time 3.0-5.5V — 10 25 ns (Master mode) 1.8-5.5V — 25 50 ns SP79* TSCF SCK output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, SDO data output valid after 3.0-5.5V — — 50 ns TSCL2DOV SCK edge 1.8-5.5V — — 145 ns SP81* TDOV2SCH, SDO data output setup to SCK edge Tcy — — ns TDOV2SCL SP82* TSSL2DOV SDO data output valid after SS edge — — 50 ns SP83* TSCH2SSH, SS after SCK edge 1.5 TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 23-20: I2C BUS START/STOP BITS TIMING SCL SP91 SP93 SP90 SP92 SDA Start Stop Condition Condition Note: Refer to Figure23-2 for load conditions. DS40001417C-page 210  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 23-12: I2C BUS START/STOP BITS REQUIREMENTS Param Symbol Characteristic Min. Typ Max. Units Conditions No. SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — Start condition SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first Hold time 400 kHz mode 600 — — clock pulse is generated SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. FIGURE 23-21: I2C BUS DATA TIMING SP103 SP100 SP102 SP101 SCL SP90 SP106 SP107 SP91 SP92 SDA In SP110 SP109 SP109 SDA Out Note: Refer to Figure23-2 for load conditions.  2010-2016 Microchip Technology Inc. DS40001417C-page 211

PIC16(L)F722A/723A TABLE 23-13: I2C BUS DATA REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP Module 1.5TCY — SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP Module 1.5TCY — SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 300 ns CB is specified to be from 0.1CB 10-400 pF SP103* TF SDA and SCL fall 100 kHz mode — 250 ns time 400 kHz mode 20 + 250 ns CB is specified to be from 0.1CB 10-400 pF SP106* THD:DAT Data input hold 100 kHz mode 0 — ns time 400 kHz mode 0 0.9 s SP107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2) time 400 kHz mode 100 — ns SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free before a new transmis- 400 kHz mode 1.3 — s sion can start SP111 CB Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT=1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS40001417C-page 212  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A TABLE 23-14: CAP SENSE OSCILLATOR SPECIFICATIONS Param. Symbol Characteristic Min. Typ† Max. Units Conditions No. CS01 ISRC Current Source High — -5.8 -6 A -40, -85°C Medium — -1.1 -3.2 A Low — -0.2 -0.9 A CS02 ISNK Current Sink High — 6.6 6 A Medium — 1.3 3.2 A -40, -85°C Low — 0.24 0.9 A CS03 VCHYST Cap Hysteresis High — 525 — mV Medium — 375 — mV VCTH-VCTL Low — 280 — mV * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 23-22: CAP SENSE OSCILLATOR VCTH VCTL ISRC ISNK Enabled Enabled  2010-2016 Microchip Technology Inc. DS40001417C-page 213

PIC16(L)F722A/723A 24.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean+3) or (mean-3) respectively, where  is a standard deviation, over the whole temperature range. FIGURE 24-1: PIC16F722A/723A MAXIMUM IDD vs. FOSC OVER VDD, EC MODE, VCAP = 0.1µF 2,200.00 Typical: Statistical Mean @25°C 5V 2,000.00 Maximum: Mean (Worst-Case Temp) + 3 3.6V (-40°C to 125°C) 1,800.00 3V 1,600.00 2.5V 1,400.00 A) 1,200.00 µ (D D 1,000.00 I 1.8V 800.00 600.00 400.00 200.00 0.00 1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz VDD (V) DS40001417C-page 214  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-2: PIC16LF722A/723A MAXIMUM IDD vs. FOSC OVER VDD, EC MODE 2,400 Typical: Statistical Mean @25°C 2,200 Maximum: Mean (Worst-Case Temp) + 3 3.6V 2,000 (-40°C to 125°C) 3.3V 1,800 3V 1,600 2.5V 1,400 A) µ (D 1,200 ID 2V 1,000 1.8V 800 600 400 200 0 1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz FOSC FIGURE 24-3: PIC16F722A/723A TYPICAL IDD vs. FOSC OVER VDD, EC MODE, VCAP = 0.1µF 2,000 Typical: Statistical Mean @25°C 5V 1,800 Maximum: Mean (Worst-Case Temp) + 3 3.6V (-40°C to 125°C) 3V 1,600 1,400 2.5V 1,200 A) µ (D 1,000 D I 1.8V 800 600 400 200 0 1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz FOSC  2010-2016 Microchip Technology Inc. DS40001417C-page 215

PIC16(L)F722A/723A FIGURE 24-4: PIC16LF722A/723A TYPICAL IDD vs. FOSC OVER VDD, EC MODE 2,200 Typical: Statistical Mean @25°C 2,000 Maximum: Mean (Worst-Case Temp) + 3 3.6V (-40°C to 125°C) 1,800 3.3V 1,600 3V 1,400 2.5V A) µ 1,200 (D D I 2V 1,000 1.8V 800 600 400 200 0 1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz F OSC FIGURE 24-5: PIC16F722A/723A MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE, VCAP = 0.1µF 600 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 4 MHz 500 (-40°C to 125°C) 400 A) (µD 300 D 1 MHz I 200 100 0 1.8 2 2.5 3 3.3 3.6 4.2 4.5 5 VDD (V) DS40001417C-page 216  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-6: PIC16LF722A/723A MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE 500 4 MHz Typical: Statistical Mean @25°C 450 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 400 350 300 A) (µD 250 D I 200 150 1 MHz 100 50 0 1.8 2 2.5 3 3.3 3.6 VDD (V) FIGURE 24-7: PIC16F722A/723A TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE, VCAP = 0.1µF 450 Typical: Statistical Mean @25°C 400 Maximum: Mean (Worst-Case Temp) + 3 4 MHz (-40°C to 125°C) 350 300 250 A) µ (DD 200 I 150 1 MHz 100 50 0 1.8 2 2.5 3 3.3 3.6 4.2 4.5 5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001417C-page 217

PIC16(L)F722A/723A FIGURE 24-8: PIC16LF722A/723A TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE 450 Typical: Statistical Mean @25°C 4 MHz 400 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 350 300 250 A) µ (D ID 200 150 1 MHz 100 50 0 1.8 2 2.5 3 3.3 3.6 VDD (V) FIGURE 24-9: PIC16F722A/723A MAXIMUM IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1µF 2.4 Typical: Statistical Mean @25°C 2.2 5V Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 4.5V 2 3.6V 1.8 3V 1.6 1.4 A) m 1.2 (D D I 1 0.8 0.6 0.4 0.2 0 4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz Fosc DS40001417C-page 218  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-10: PIC16LF722A/723A MAXIMUM IDD vs. FOSC OVER VDD, HS MODE 2.50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 3.6V (-40°C to 125°C) 2.00 3.3V 3V 1.50 A) 2.5V m (D D I 1.00 0.50 0.00 4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz Fosc FIGURE 24-11: PIC16F722A/723A TYPICAL IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1µF Typical: Statistical Mean @25°C 2.00 Maximum: Mean (Worst-Case Temp) + 3 5V (-40°C to 125°C) 4.5V 3.6V 3V 1.50 A) m (D D 1.00 I 0.50 0.00 4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz Fosc  2010-2016 Microchip Technology Inc. DS40001417C-page 219

PIC16(L)F722A/723A FIGURE 24-12: PIC16LF722A/723A TYPICAL IDD vs. FOSC OVER VDD, HS MODE 2.50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 2.00 3.6V 3.3V 3V 1.50 A) m 2.5V (D D I 1.00 0.50 0.00 4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz Fosc FIGURE 24-13: PIC16F722A/723A MAXIMUM IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1µF 600 Typical: Statistical Mean @25°C 4 MHz Maximum: Mean (Worst-Case Temp) + 3 500 (-40°C to 125°C) 400 A) 300 (µD 1 MHz D I 200 100 0 1.8 2 2.5 3 3.3 3.6 4.2 4.5 5 VDD (V) DS40001417C-page 220  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-14: PIC16LF722A/723A MAXIMUM IDD vs. VDD OVER FOSC, XT MODE 600 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 4 MHz (-40°C to 125°C) 500 400 µA) 300 (D D I 1 MHz 200 100 0 1.8 2 2.5 3 3.3 3.6 VDD (V) FIGURE 24-15: PIC16F722A/723A TYPICAL IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1µF 600 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 500 (-40°C to 125°C) 4 MHz 400 A) µ (D 300 D I 1 MHz 200 100 0 1.8 2 2.5 3 3.3 3.6 4.2 4.5 5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001417C-page 221

PIC16(L)F722A/723A FIGURE 24-16: PIC16LF722A/723A TYPICAL IDD vs. VDD OVER FOSC, XT MODE 600 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 500 4 MHz 400 A) µ 300 (D D I 1 MHz 200 100 0 1.8 2 2.5 3 3.3 3.6 VDD (V) FIGURE 24-17: PIC16F722A/723A IDD vs. VDD, LP MODE, VCAP = 0.1µF 20.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 17.5 32 kHz Maximum A) µ 15.0 (DD VDD (V) I 32 kHz Typical 12.5 10.0 1.8 3 5 VDD (V) DS40001417C-page 222  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-18: PIC16LF722A/723A IDD vs. VDD, LP MODE 30 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 25 32 kHz Maximum 20 A) µ (D D I 15 32 kHz Typical 10 5 1.8 3 3.3 3.6 VDD (V) FIGURE 24-19: PIC16F722A/723A MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF 210 Typical: Statistical Mean @25°C 200 Maximum: Mean (Worst-Case Temp) + 3 5V (-40°C to 125°C) 190 180 3.6V 170 A) 2.5V µ 160 (D D I 150 1.8V 140 130 120 110 62.5 kHz 125 kHz 250 kHz 500 kHz FOSC  2010-2016 Microchip Technology Inc. DS40001417C-page 223

PIC16(L)F722A/723A FIGURE 24-20: PIC16LF722A/723A MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE 170 Typical: Statistical Mean @25°C 3.6V Maximum: Mean (Worst-Case Temp) + 3 160 (-40°C to 125°C) 150 3V A) 140 2.5V µ (D D I 130 1.8V 120 110 100 62.5 kHz 125 kHz 250 kHz 500 kHz FOSC FIGURE 24-21: PIC16F722A/723A MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF 2,000 Typical: Statistical Mean @25°C 5V 1,800 Maximum: Mean (Worst-Case Temp) + 3 3.6V (-40°C to 125°C) 1,600 2.5V 1,400 1,200 A) (µD 1,000 1.8V D I 800 600 400 200 0 2 MHz 4 MHz 8 MHz 16 MHz FOSC DS40001417C-page 224  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-22: PIC16LF722A/723A MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE 2,250 s Typical: Statistical Mean @25°C 3.6V 2,000 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1,750 3V 1,500 2.5V A) 1,250 µ (D D I 1.8V 1,000 750 500 250 0 2 MHz 4 MHz 8 MHz 16 MHz FOSC FIGURE 24-23: PIC16F722A/723A TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 150 (-40°C to 125°C) 5V 140 3.6V 130 A) 2.5V µ (D ID 120 1.8V 110 100 90 80 62.5 kHz 125 kHz 250 kHz 500 kHz FOSC  2010-2016 Microchip Technology Inc. DS40001417C-page 225

PIC16(L)F722A/723A FIGURE 24-24: PIC16LF722A/723A TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE 140 3.6V Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 130 (-40°C to 125°C) 3V 120 2.5V 110 A) µ (D ID 100 1.8V 90 80 70 62.5 kHz 125 kHz 250 kHz 500 kHz FOSC FIGURE 24-25: PIC16F722A/723A TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF 2,000 1,800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 5V (-40°C to 125°C) 3.6V 1,600 1,400 2.5V 1,200 A) µ 1,000 (D 1.8V D I 800 600 400 200 0 2 MHz 4 MHz 8 MHz 16 MHz FOSC DS40001417C-page 226  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-26: PIC16LF722A/723A TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE 2,000 Typical: Statistical Mean @25°C 3.6V 1,800 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1,600 3V 1,400 2.5V 1,200 A) µ (DD 1,000 I 1.8V 800 600 400 200 0 2 MHz 4 MHz 8 MHz 16 MHz VDD (V) FIGURE 24-27: PIC16F722A/723A MAXIMUM BASE IPD vs. VDD, VCAP = 0.1µF 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 20 125°C 15 A) µ (D 85°C P I 10 5 0 1.8V 2V 3V 3.6V 4V 5V 5.5V VDD (V)  2010-2016 Microchip Technology Inc. DS40001417C-page 227

PIC16(L)F722A/723A FIGURE 24-28: PIC16LF722A/723A MAXIMUM BASE IPD vs. VDD 7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 6 (-40°C to 125°C) 125°C 5 4 A) µ (D P I 3 2 85°C 1 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-29: PIC16F722A/723A TYPICAL BASE IPD vs. VDD, VCAP = 0.1µF 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 7 (-40°C to 125°C) 6 25°C A) 5 µ (D P I 4 3 2 1.8V 2V 3V 3.6V 4V 5V 5.5V VDD (V) DS40001417C-page 228  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-30: PIC16LF722A/723A TYPICAL BASE IPD vs. VDD 250 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 200 25°C 150 A) n (D P I 100 50 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-31: PIC16F722A/723A FIXED VOLTAGE REFERENCE IPD vs. VDD, VCAP = 0.1µF 70 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 Max. 125°C 60 (-40°C to 125°C) 50 Max. 85°C 40 A) µ (D 30 P I Typ. 25°C 20 10 0 1.8V 2V 3V 3.6V 5V 5.5V VDD (V)  2010-2016 Microchip Technology Inc. DS40001417C-page 229

PIC16(L)F722A/723A FIGURE 24-32: PIC16LF722A/723A FIXED VOLTAGE REFERENCE IPD vs. VDD 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 20 15 Max. 85°C A) µ (D P I 10 Typ. 25°C 5 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-33: PIC16F722A/723A BOR IPD vs. VDD, VCAP = 0.1µF 70 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 60 (-40°C to 125°C) Max. 125°C 50 40 A) Max. 85°C µ (D IP 30 Typ. 25°C 20 10 0 2V 3V 3.6V 5V 5.5V VDD (V) DS40001417C-page 230  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-34: PIC16LF722A/723A BOR IPD vs. VDD 30 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 25 (-40°C to 125°C) Max. 125°C 20 A) µ 15 (D P I Max. 85°C 10 Typ. 25°C 5 0 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-35: PIC16F722A/723A CAP SENSE HIGH POWER IPD vs. VDD, VCAP = 0.1µF 70 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 Max. 125°C 60 (-40°C to 125°C) Max. 85°C 50 Typ. 25°C 40 A) µ (D P I 30 20 10 0 1.8V 2V 3V 3.6V 5V 5.5V VDD (V)  2010-2016 Microchip Technology Inc. DS40001417C-page 231

PIC16(L)F722A/723A FIGURE 24-36: PIC16LF722A/723A CAP SENSE HIGH POWER IPD vs. VDD 60 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 50 Max. 125°C Max. 85°C 40 Typ. 25°C A) µ 30 (D P I 20 10 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-37: PIC16F722A/723A CAP SENSE MEDIUM POWER IPD vs. VDD, VCAP = 0.1µF 30 Typical: Statistical Mean @25°C Max. 125°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 25 20 Max. 85°C A) 15 µ (D IP Typ. 25°C 10 5 0 1.8V 2V 3V 3.6V 5V 5.5V VDD (V) DS40001417C-page 232  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-38: PIC16LF722A/723A CAP SENSE MEDIUM POWER IPD vs. VDD 20 Typical: Statistical Mean @25°C Max. 125°C Maximum: Mean (Worst-Case Temp) + 3 18 (-40°C to 125°C) 16 14 12 A) (µD 10 P I 8 Max. 85°C 6 Typ. 25°C 4 2 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-39: PIC16F722A/723A CAP SENSE LOW POWER IPD vs. VDD, VCAP = 0.1µF 30 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 Max. 125°C 25 (-40°C to 125°C) 20 A) 15 Max. 85°C µ (D P I 10 Typ. 25°C 5 0 1.8V 2V 3V 3.6V 5V 5.5V VDD (V)  2010-2016 Microchip Technology Inc. DS40001417C-page 233

PIC16(L)F722A/723A FIGURE 24-40: PIC16LF722A/723A CAP SENSE LOW POWER IPD vs. VDD 18 Typical: Statistical Mean @25°C Max. 125°C Maximum: Mean (Worst-Case Temp) + 3 16 (-40°C to 125°C) 14 12 10 A) (µD 8 P I 6 Max. 85°C 4 Typ. 25°C 2 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-41: PIC16F722A/723A T1OSC 32 kHz IPD vs. VDD, VCAP = 0.1µF 16 Typical: Statistical Mean @25°C Max. 85°C Maximum: Mean (Worst-Case Temp) + 3 14 (-40°C to 125°C) 12 10 Typ. 25° C µA) 8 (D P I 6 4 2 0 1.8V 2V 3V 3.6V 5V 5.5V VDD (V) DS40001417C-page 234  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-42: PIC16LF722A/723A T1OSC 32 kHz IPD vs. VDD 4.0 Typical: Statistical Mean @25°C Max. 85°C Maximum: Mean (Worst-Case Temp) + 3 3.5 (-40°C to 125°C) 3.0 2.5 Typ. A) 2.0 µ (D P I 1.5 1.0 0.5 0.0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-43: PIC16F722A/723A TYPICAL ADC IPD vs. VDD, VCAP = 0.1µF 7.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Typ. 25°C 7.0 6.5 A) µ (D IP 6.0 5.5 5.0 1.8V 2V 3V 3.6V 5V 5.5V VDD (V)  2010-2016 Microchip Technology Inc. DS40001417C-page 235

PIC16(L)F722A/723A FIGURE 24-44: PIC16LF722A/723A TYPICAL ADC IPD vs. VDD 250 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Typ. 25°C 200 150 A) n (D P I 100 50 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-45: PIC16F722A/723A ADC IPD vs. VDD, VCAP = 0.1µF 25 Typical: Statistical Mean @25°C Max. 125°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 20 A) 15 µ (D P I Max. 85°C 10 5 1.8V 2V 3V 3.6V 5V 5.5V VDD (V) DS40001417C-page 236  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-46: PIC16LF722A/723A ADC IPD vs. VDD 8 Typical: Statistical Mean @25°C 7 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 6 5 µA) 4 (D P I 3 2 Max. 85°C 1 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-47: PIC16F722A/723A WDT IPD vs. VDD, VCAP = 0.1µF 18 Typical: Statistical Mean @25°C Max. 85°C Maximum: Mean (Worst-Case Temp) + 3 16 (-40°C to 125°C) 14 12 10 A) Typ. 25°C µ 8 (D P I 6 4 2 0 1.8V 2V 3V 3.6V 5V 5.5V VDD (V)  2010-2016 Microchip Technology Inc. DS40001417C-page 237

PIC16(L)F722A/723A FIGURE 24-48: PIC16LF722A/723A WDT IPD vs. VDD 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 Max. 85°C 3.0 (-40°C to 125°C) 2.5 2.0 A) µ (PD 1.5 I Typ. 25°C 1.0 0.5 0.0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 24-49: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 1.8 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C 1.6 Minimum: Mean - 3 (-40°C to 125°C) 1.4 Max. -40° 1.2 V) (N Typ. 25° VI 1 Min. 125° 0.8 0.6 0.4 1.8 3.6 5.5 VDD (V) DS40001417C-page 238  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-50: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 3.5 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C 3.0 Minimum: Mean - 3 (-40°C to 125°C) VIH Max. -40°C 2.5 2.0 V) (N VI 1.5 VIH M in. 125°C 1.0 0.5 0.0 1.8 3.6 5.5 VDD (V) FIGURE 24-51: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 3.0 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C 2.5 Minimum: Mean - 3 (-40°C to 125°C) VIL Max. -40°C 2.0 (V)N 1.5 VI 1.0 VIL Min. 125°C 0.5 0.0 1.8 3.6 5.5 VDD (V)  2010-2016 Microchip Technology Inc. DS40001417C-page 239

PIC16(L)F722A/723A FIGURE 24-52: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V 5.6 Maximum: Mean + 3 (-40°C to 125°C) 5.5 Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 5.4 V) (OH 5.3 Max. -40° V Typ. 25° 5.2 Min. 125° 5.1 5 -0.2 -1.0 -1.8 -2.6 -3.4 -4.2 -5.0 IOH (mA) FIGURE 24-53: VOH vs. IOH OVER TEMPERATURE, VDD = 3.6V 3.8 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 3.6 3.4 Max. -40° V) (H 3.2 VO Typ. 25° 3 Min. 125° 2.8 2.6 -0.2 -1.0 -1.8 -2.6 -3.4 -4.2 -5.0 IOH (mA) DS40001417C-page 240  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-54: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V 2 Maximum: Mean + 3 (-40°C to 125°C) 1.8 Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 1.6 Max. -40° 1.4 1.2 V) 1 Typ. 25° (H O V 0.8 0.6 Min. 125° 0.4 0.2 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 IOH (mA) FIGURE 24-55: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V 0.5 Maximum: Mean + 3 (-40°C to 125°C) 0.45 Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 0.4 0.35 Max. 125° 0.3 0.25 V) (L VO 0.2 Typ. 25° 0.15 0.1 Min. -40° 0.05 0 5.0 6.0 7.0 8.0 9.0 10.0 IOL (mA)  2010-2016 Microchip Technology Inc. DS40001417C-page 241

PIC16(L)F722A/723A FIGURE 24-56: VOL vs. IOL OVER TEMPERATURE, VDD = 3.6 0.9 Maximum: Mean + 3 (-40°C to 125°C) 0.8 Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 0.7 0.6 Max. 125° 0.5 V) (L VO 0.4 Typ. 25° 0.3 0.2 Min. -40° 0.1 0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 IOL (mA) FIGURE 24-57: VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V 1.2 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 1 0.8 Max. 125° V) 0.6 (L O V 0.4 0.2 Min. -40° 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 IOL (mA) DS40001417C-page 242  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-58: PIC16F722A/723A PWRT PERIOD 105 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 95 Max. -40°C 85 s) m E ( M 75 TI Typ. 25°C 65 Min. 125°C 55 45 1.8V 2V 2.2V 2.4V 3V 3.6V 4V 4.5V 5V 5.5V VDD FIGURE 24-59: PIC16F722A/723A WDT TIME-OUT PERIOD 24.00 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 22.00 (-40°C to 125°C) Max. -40°C 20.00 18.00 Typ. 25°C s) m E ( 16.00 M TI 14.00 Min. 125°C 12.00 10.00 1.8V 2V 2.2V 2.4V 3V 3.6V 4V 4.5V 5V VDD  2010-2016 Microchip Technology Inc. DS40001417C-page 243

PIC16(L)F722A/723A FIGURE 24-60: PIC16F722A/723A HFINTOSC WAKE-UP FROM SLEEP START-UP TIME 6.0 Typical: Statistical Mean @25°C 5.5 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5.0 4.5 Max. 4.0 us) 3.5 E ( M TI 3.0 Typ. 2.5 2.0 1.5 1.0 1.8V 2V 3V 3.6V 4V 4.5V 5V 5.5V VDD FIGURE 24-61: PIC16F722A/723A A/D INTERNAL RC OSCILLATOR PERIOD 6.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5.0 4.0 s) µ d ( 3.0 erio Max. P Min. 2.0 1.0 0.0 1.8V 3.6V 5.5V VDD(V) DS40001417C-page 244  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-62: PIC16F722A/723A CAP SENSE OUTPUT CURRENT, POWER MODE = HIGH 20000 15000 Min. Sink -40°C Typ. Sink 25°C 10000 A) n 5000 Max. Sink 85°C nt ( e urr C 0 Min. Source 85°C -5000 Typ. Source 25°C -10000 Max. Source -40°C -15000 1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5 VDD(V) FIGURE 24-63: PIC16F722A/723A CAP SENSE OUTPUT CURRENT, POWER MODE = MEDIUM 3000 Max. Sink -40°C 2000 Typ. Sink 25°C 1000 Min. Sink 85°C A) n nt ( e 0 urr Min. Source 85°C C -1000 Typ. Source 25°C -2000 Max. Source -40°C -3000 1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5 VDD(V)  2010-2016 Microchip Technology Inc. DS40001417C-page 245

PIC16(L)F722A/723A FIGURE 24-64: PIC16F722A/723A CAP SENSE OUTPUT CURRENT, POWER MODE = LOW 600 Max. Sink 85°C 400 Typ. Sink 25°C 200 Min. Sink -40°C 0 A) n nt ( Min. Source 85°C e -200 urr C Typ. Source 25°C -400 -600 Max. Source -40°C -800 1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5 VDD(V) FIGURE 24-65: PIC16F722A/723A CAP SENSOR HYSTERESIS, POWER MODE = HIGH 700 Max. 125°C Max. 85°C 600 Typ. 25°C V m 500 Min. 0°C Min. -40°C 400 300 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5 VDD(V) DS40001417C-page 246  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A FIGURE 24-66: PIC16F722A/723A CAP SENSOR HYSTERESIS, POWER MODE = MEDIUM 550 500 Max. 125°C 450 Max. 85°C mV 400 Typ. 25°C 350 Min. 0°C 300 Min. -40°C 250 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5 VDD(V) FIGURE 24-67: PIC16F722A/723A CAP SENSOR HYSTERESIS, POWER MODE = LOW 450 Max. 125°C 400 Max. 85°C 350 V m 300 Typ. 25°C 250 Min. 0°C 200 Min -40°C 150 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5 VDD(V)  2010-2016 Microchip Technology Inc. DS40001417C-page 247

PIC16(L)F722A/723A FIGURE 24-68: TYPICAL FVR (X1 AND X2) VS. SUPPLY VOLTAGE (V) NORMALIZED AT 3.0V 1.5 1 0.5 %) e ( g n a h 0 C nt e c er P -0.5 -1 -1.5 1.8 2.5 3 3.6 4.2 5.5 Voltage FIGURE 24-69: TYPICAL FVR CHANGE VS. TEMPERATURE NORMALIZED AT 25°C 1.5 1 0.5 0 %) e ( g -0.5 n a h C nt -1 e c er P -1.5 -2 -2.5 -3 -40 0 45 85 125 Temperature (°C) DS40001417C-page 248  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 25.0 PACKAGING INFORMATION 25.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC16F722A -I/SP e3 0810017 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 XXXXXXXX 16F722A XXXXXXXX -I/ML e3 YYWWNNN 0810017 28-Lead UQFN (4x4x0.5 mm) Example PIC16 PIN 1 PIN 1 F722A -E/MV e3 810017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC® designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PICmicro® device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2010-2016 Microchip Technology Inc. DS40001417C-page 249

PIC16(L)F722A/723A 25.1 Package Marking Information (Continued) 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX PIC16F722A -I/SO e3 XXXXXXXXXXXXXXXXXXXX 0810017 XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP (5.30 mm) Example PIC16F722A -I/SS e3 0810017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC® designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PICmicro® device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS40001417C-page 250  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A 25.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)(cid:26)(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1  2010-2016 Microchip Technology Inc. DS40001417C-page 251

PIC16(L)F722A/723A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)#(cid:21)(cid:7)(cid:8)(cid:9)$(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)&(cid:6)(cid:9)(cid:23)’(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)()((cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)#$! *(cid:12)(cid:18)+(cid:9)(cid:27),--(cid:9)(cid:28)(cid:28)(cid:9).(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13)&(cid:18)+ !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)- (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# @ (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)(cid:29)1 DS40001417C-page 252  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)#(cid:21)(cid:7)(cid:8)(cid:9)$(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)&(cid:6)(cid:9)(cid:23)’(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)()((cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)#$! *(cid:12)(cid:18)+(cid:9)(cid:27),--(cid:9)(cid:28)(cid:28)(cid:9).(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13)&(cid:18)+ !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2010-2016 Microchip Technology Inc. DS40001417C-page 253

PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001417C-page 254  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2016 Microchip Technology Inc. DS40001417C-page 255

PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001417C-page 256  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2016 Microchip Technology Inc. DS40001417C-page 257

PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001417C-page 258  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)+/(cid:12)(cid:13)(cid:11)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)0(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:10)(cid:24)(cid:9)(cid:25)(cid:9)-,(cid:26)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:10)0(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:30)(cid:4)(cid:20)(cid:3)(cid:4) (cid:30)(cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)A (cid:23)A <A 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)-1  2010-2016 Microchip Technology Inc. DS40001417C-page 259

PIC16(L)F722A/723A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001417C-page 260  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A APPENDIX A: DATA SHEET APPENDIX B: MIGRATING FROM REVISION HISTORY OTHER PIC® DEVICES Revision A (April 2010) This discusses some of the issues in migrating from Original release of this data sheet. other PIC® devices to the PIC16F722A/723A family of devices. Revision B (January 2012) Updated the data sheet to new format; Updated Figure Note: This device has been designed to perform 9-1 and Register 9-1; Updated the Packaging to the parameters of its data sheet. It has Information section; Updated the Product Identification been tested to an electrical specification System section; Other minor corrections. designed to determine its conformance with these parameters. Due to process Revision C (03/2016) differences in the manufacture of this device, this device may have different Updated Table 2-1, Table 6-1 and Table 6-3; Updated performance characteristics than its Register 14-2; Other minor corrections. earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. Note: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the oscillator mode may be required. B.1 PIC16F77 to PIC16F722A/723A TABLE B-1: FEATURE COMPARISON PIC16F722A/ Feature PIC16F77 723A Max. Operating Speed 20MHz 20MHz Max. Program 8K 4K Memory (Words) Max. SRAM (Bytes) 368 192 A/D Resolution 8-bit 8-bit Timers (8/16-bit) 2/1 2/1 Oscillator Modes 4 8 Brown-out Reset Y Y Internal Pull ups RB<7:0> RB<7:0> Interrupt-on-change RB<7:4> RB<7:0> Comparator 0 0 USART Y Y Extended WDT N N Software Control N N Option of WDT/BOR INTOSC Frequencies None 500kHz - 16MHz Clock Switching N N  2010-2016 Microchip Technology Inc. DS40001417C-page 261

PIC16(L)F722A/723A THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Product Support – Data sheets and errata, appli- • Technical Support cation notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, representa- documents, latest software releases and archived tive or Field Application Engineer (FAE) for support. software Local sales offices are also available to help custom- ers. A listing of sales offices and locations is included in • General Technical Support – Frequently Asked the back of this document. Questions (FAQ), technical support requests, online discussion groups, Microchip consultant Technical support is available through the website program member listing at: http://www.microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Cus- tomer Change Notification” and follow the registration instructions. DS40001417C-page 262  2010-2016 Microchip Technology Inc.

PIC16(L)F722A/723A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) _ X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC16F722A-E/SP 301 = Extended Option Range Temp., SPDIP package, QTP pattern #301 b) PIC16F722A-I/SO = Industrial Temp., Device: PIC16F722A, PIC16LF722A SOIC package PIC16F723A, PIC16LF723A Tape and Reel Blank= Standard packaging (tube or tray) Option: T = Tape and Reel(1) Temperature I = -40C to+85C (Industrial) Range: E = -40C to+125C (Extended) Note 1: Tape and Reel identifier only Package: MV = UQFN appears in the catalog part number ML = QFN description. This identifier is used for SO = SOIC ordering purposes and is not printed SP = SPDIP on the device package. Check with SS = SSOP your Microchip Sales Office for package availability with the Tape Pattern: 3-Digit Pattern Code for QTP (blank otherwise) and Reel option.  2010-2016 Microchip Technology Inc. DS40001417C-page 263

PIC16(L)F722A/723A NOTES: DS40001417C-page 264  2010-2016 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, and may be superseded by updates. It is your responsibility to dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, ensure that your application meets with your specifications. KEELOQ logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MICROCHIP MAKES NO REPRESENTATIONS OR MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, WARRANTIES OF ANY KIND WHETHER EXPRESS OR RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O IMPLIED, WRITTEN OR ORAL, STATUTORY OR are registered trademarks of Microchip Technology OTHERWISE, RELATED TO THE INFORMATION, Incorporated in the U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR ClockWorks, The Embedded Control Solutions Company, FITNESS FOR PURPOSE. Microchip disclaims all liability ETHERSYNCH, Hyper Speed Control, HyperLight Load, arising from this information and its use. Use of Microchip IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are devices in life support and/or safety applications is entirely at registered trademarks of Microchip Technology Incorporated the buyer’s risk, and the buyer agrees to defend, indemnify and in the U.S.A. hold harmless Microchip from any and all damages, claims, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, suits, or expenses resulting from such use. No licenses are BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, conveyed, implicitly or otherwise, under any Microchip dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, intellectual property rights unless otherwise stated. EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of Tempe, Arizona; Gresham, Oregon and design centers in California Microchip Technology Inc. in other countries. and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademarks of Microchip Technology devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. QUALITY MANAGEMENT SYSTEM © 2010-2016, Microchip Technology Incorporated, Printed in CERTIFIED BY DNV the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0337-1 == ISO/TS 16949 ==  2010-2016 Microchip Technology Inc. DS40001417C-page 265

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16F726-E/SP PIC16F726-I/SP PIC16LF726-I/SS PIC16LF727-I/PT PIC16LF724-I/PT PIC16LF727-I/P PIC16LF724-I/P PIC16LF726-I/SP PIC16F726-E/MV PIC16F726-I/MV PIC16F726T-I/MV PIC16F722A-E/ML PIC16F722A-E/MV PIC16F722A-E/SO PIC16F722A-E/SP PIC16F722A-E/SS PIC16F722A-I/ML PIC16F722A-I/MV PIC16F722A-I/SO PIC16F722A-I/SP PIC16F722A-I/SS PIC16F722AT-I/ML PIC16F722AT-I/MV PIC16F722AT-I/SO PIC16F722AT-I/SS PIC16F723A-E/ML PIC16F723A-E/MV PIC16F723A-E/SO PIC16F723A-E/SP PIC16F723A-E/SS PIC16F723A-I/ML PIC16F723A-I/MV PIC16F723A-I/SO PIC16F723A-I/SP PIC16F723A-I/SS PIC16F723AT-I/ML PIC16F723AT-I/MV PIC16F723AT-I/SO PIC16F723AT-I/SS PIC16LF722A-E/ML PIC16LF722A-E/MV PIC16LF722A- E/SO PIC16LF722A-E/SP PIC16LF722A-E/SS PIC16LF722A-I/ML PIC16LF722A-I/MV PIC16LF722A-I/SO PIC16LF722A-I/SP PIC16LF722A-I/SS PIC16LF722AT-I/ML PIC16LF722AT-I/MV PIC16LF722AT-I/SO PIC16LF722AT-I/SS PIC16LF723A-E/ML PIC16LF723A-E/MV PIC16LF723A-E/SO PIC16LF723A-E/SP PIC16LF723A-E/SS PIC16LF723A-I/ML PIC16LF723A-I/MV PIC16LF723A-I/SO PIC16LF723A-I/SP PIC16LF723A- I/SS PIC16LF723AT-I/ML PIC16LF723AT-I/MV PIC16LF723AT-I/SO PIC16LF723AT-I/SS PIC16F724-E/ML PIC16F724-E/P PIC16F724-E/PT PIC16F724-I/ML PIC16F724-I/P PIC16F724-I/PT PIC16F724T-I/ML PIC16F724T- I/PT PIC16F726-E/ML PIC16F726-E/SO PIC16F726-E/SS PIC16F726-I/ML PIC16F726-I/SO PIC16F726-I/SS PIC16F726T-I/ML PIC16F726T-I/SO PIC16F726T-I/SS PIC16F727-E/ML PIC16F727-E/P PIC16F727-E/PT PIC16F727-I/ML PIC16F727-I/P PIC16F727-I/PT PIC16F727T-I/ML PIC16F727T-I/PT PIC16LF727T-I/PT PIC16LF724T-I/PT PIC16LF726T-I/SO PIC16LF727-E/PT PIC16LF724-I/ML PIC16LF724-E/ML PIC16LF726-E/SP PIC16LF726T-I/SS