PIC16F631/677/685/687/689/690 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers High-Performance RISC CPU Low-Power Features • Only 35 Instructions to Learn: • Standby Current: - All single-cycle instructions except branches - 50nA @ 2.0V, typical • Operating Speed: • Operating Current: - DC – 20MHz oscillator/clock input - 11A @ 32kHz, 2.0V, typical - DC – 200ns instruction cycle - 220A @ 4MHz, 2.0V, typical • Interrupt Capability • Watchdog Timer Current: • 8-Level Deep Hardware Stack - <1A @ 2.0V, typical • Direct, Indirect and Relative Addressing modes Peripheral Features Special Microcontroller Features • 17 I/O Pins and 1 Input-Only Pin: • Precision Internal Oscillator: - High current source/sink for direct LED drive - Factory calibrated to ±1% - Interrupt-on-Change pin - Software selectable frequency range of - Individually programmable weak pull-ups 8MHz to 32kHz - Ultra Low-Power Wake-up (ULPWU) - Software tunable • Analog Comparator Module with: - Two-Speed Start-up mode - Two analog comparators - Crystal fail detect for critical applications - Programmable on-chip voltage reference - Clock mode switching during operation for (CVREF) module (% of VDD) power savings - Comparator inputs and outputs externally • Power-Saving Sleep mode accessible • Wide Operating Voltage Range (2.0V-5.5V) - SR Latch mode • Industrial and Extended Temperature Range - Timer 1 Gate Sync Latch • Power-on Reset (POR) - Fixed 0.6V VREF • Power-up Timer (PWRTE) and Oscillator Start-up • A/D Converter: Timer (OST) - 10-bit resolution and 12 channels • Brown-out Reset (BOR) with Software Control • Timer0: 8-Bit Timer/Counter with 8-Bit Option Programmable Prescaler • Enhanced Low-Current Watchdog Timer (WDT) • Enhanced Timer1: with On-Chip Oscillator (Software selectable - 16-bit timer/counter with prescaler nominal 268 Seconds with Full Prescaler) with - External Timer1 Gate (count enable) Software Enable - Option to use OSC1 and OSC2 in LP mode • Multiplexed Master Clear/Input Pin as Timer1 oscillator if INTOSC mode • Programmable Code Protection selected • High Endurance Flash/EEPROM Cell: • Timer2: 8-Bit Timer/Counter with 8-Bit Period - 100,000 write Flash endurance Register, Prescaler and Postscaler - 1,000,000 write EEPROM endurance • Enhanced Capture, Compare, PWM+ Module: - Flash/Data EEPROM retention: > 40 years - 16-bit Capture, max resolution 12.5ns • Enhanced USART Module: - Compare, max resolution 200ns - Supports RS-485, RS-232 and LIN 2.0 - 10-bit PWM with 1, 2 or 4 output channels, - Auto-Baud Detect programmable “dead time”, max frequency - Auto-wake-up on Start bit 20kHz - PWM output steering control • Synchronous Serial Port (SSP): - SPI mode (Master and Slave) • I2C™ (Master/Slave modes): - I2C™ address mask • In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins  2005-2015 Microchip Technology Inc. DS40001262F-page 1

PIC16F631/677/685/687/689/690 Program Data Memory Memory 10-bit A/D Timers Device I/O Comparators SSP ECCP+ EUSART (ch) 8/16-bit Flash SRAM EEPROM (words) (bytes) (bytes) PIC16F631 1024 64 128 18 — 2 1/1 No No No PIC16F677 2048 128 256 18 12 2 1/1 Yes No No PIC16F685 4096 256 256 18 12 2 2/1 No Yes No PIC16F687 2048 128 256 18 12 2 1/1 Yes No Yes PIC16F689 4096 256 256 18 12 2 1/1 Yes No Yes PIC16F690 4096 256 256 18 12 2 2/1 Yes Yes Yes PIC16F631 Pin Diagram 20-pin PDIP, SOIC, SSOP VDD 1 20 VSS RA5/T1CKI/OSC1/CLKIN 2 19 RA0/C1IN+/ICSPDAT/ULPWU RA4/T1G/OSC2/CLKOUT 3 18 RA1/C12IN0-/ICSPCLK RA3/MCLR/VPP 4 31 17 RA2/T0CKI/INT/C1OUT RC5 5 F6 16 RC0/C2IN+ 6 RC4/C2OUT 6 1 15 RC1/C12IN1- C RC3/C12IN3- 7 PI 14 RC2/C12IN2- RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6 TABLE 1: PIC16F631 PIN SUMMARY I/O Pin Analog Comparators Timers Interrupt Pull-up Basic RA0 19 AN0/ULPWU C1IN+ — IOC Y ICSPDAT RA1 18 AN1 C12IN0- — IOC Y ICSPCLK RA2 17 — C1OUT T0CKI IOC/INT Y — RA3 4 — — — IOC Y(1) MCLR/VPP RA4 3 — — T1G IOC Y OSC2/CLKOUT RA5 2 — — T1CKI IOC Y OSC1/CLKIN RB4 13 — — — IOC Y — RB5 12 — — — IOC Y — RB6 11 — — — IOC Y — RB7 10 — — — IOC Y — RC0 16 AN4 C2IN+ — — — — RC1 15 AN5 C12IN1- — — — — RC2 14 AN6 C12IN2- — — — — RC3 7 AN7 C12IN3- — — — — RC4 6 — C2OUT — — — — RC5 5 — — — — — — RC6 8 — — — — — — RC7 9 — — — — — — — 1 — — — — — VDD — 20 — — — — — VSS Note 1: Pull-up enabled only with external MCLR configuration. DS40001262F-page 2  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 PIC16F677 Pin Diagram 20-pin PDIP, SOIC, SSOP VDD 1 20 VSS RA5/T1CKI/OSC1/CLKIN 2 19 RA0/AN0/C1IN+/ICSPDAT/ULPWU RA4/AN3/T1G/OSC2/CLKOUT 3 18 RA1/AN1/C12IN0-/VREF/ICSPCLK RA3/MCLR/VPP 4 7 17 RA2/AN2/T0CKI/INT/C1OUT 7 RC5 5 F6 16 RC0/AN4/C2IN+ RC4/C2OUT 6 16 15 RC1/AN5/C12IN1- C RC3/AN7C12IN3- 7 PI 14 RC2/AN6/C12IN2- RC6/AN8/SS 8 13 RB4/AN10/SDI/SDA RC7/AN9/SDO 9 12 RB5/AN11 RB7 10 11 RB6/SCK/SCL TABLE 2: PIC16F631 PIN SUMMARY I/O Pin Analog Comparators Timers Interrupt Pull-up Basic RA0 19 AN0/ULPWU C1IN+ — IOC Y ICSPDAT RA1 18 AN1 C12IN0- — IOC Y ICSPCLK RA2 17 — C1OUT T0CKI IOC/INT Y — RA3 4 — — — IOC Y(1) MCLR/VPP RA4 3 — — T1G IOC Y OSC2/CLKOUT RA5 2 — — T1CKI IOC Y OSC1/CLKIN RB4 13 — — — IOC Y — RB5 12 — — — IOC Y — RB6 11 — — — IOC Y — RB7 10 — — — IOC Y — RC0 16 AN4 C2IN+ — — — — RC1 15 AN5 C12IN1- — — — — RC2 14 AN6 C12IN2- — — — — RC3 7 AN7 C12IN3- — — — — RC4 6 — C2OUT — — — — RC5 5 — — — — — — RC6 8 — — — — — — RC7 9 — — — — — — — 1 — — — — — VDD — 20 — — — — — VSS Note 1: Pull-up enabled only with external MCLR configuration.  2005-2015 Microchip Technology Inc. DS40001262F-page 3

PIC16F631/677/685/687/689/690 PIC16F685 Pin Diagram 20-pin PDIP, SOIC, SSOP VDD 1 20 VSS RA5/T1CKI/OSC1/CLKIN 2 19 RA0/AN0/C1IN+/ICSPDAT/ULPWU RA4/AN3/T1G/OSC2/CLKOUT 3 18 RA1/AN1/C12IN0-/VREF/ICSPCLK RA3/MCLR/VPP 4 5 17 RA2/AN2/T0CKI/INT/C1OUT 8 RC5/CCP1/P1A 5 F6 16 RC0/AN4/C2IN+ RC4/C2OUT/P1B 6 16 15 RC1/AN5/C12IN1- C RC3/AN7/C12IN3-/P1C 7 PI 14 RC2/AN6/C12IN2-/P1D RC6/AN8 8 13 RB4/AN10 RC7/AN9 9 12 RB5/AN11 RB7 10 11 RB6 TABLE 3: PIC16F685 PIN SUMMARY I/O Pin Analog Comparators Timers ECCP Interrupt Pull-up Basic RA0 19 AN0/ULPWU C1IN+ — — IOC Y ICSPDAT RA1 18 AN1/VREF C12IN0- — — IOC Y ICSPCLK RA2 17 AN2 C1OUT T0CKI — IOC/INT Y — RA3 4 — — — — IOC Y(1) MCLR/VPP RA4 3 AN3 — T1G — IOC Y OSC2/CLKOUT RA5 2 — — T1CKI — IOC Y OSC1/CLKIN RB4 13 AN10 — — — IOC Y — RB5 12 AN11 — — — IOC Y — RB6 11 — — — — IOC Y — RB7 10 — — — — IOC Y — RC0 16 AN4 C2IN+ — — — — — RC1 15 AN5 C12IN1- — — — — — RC2 14 AN6 C12IN2- — P1D — — — RC3 7 AN7 C12IN3- — P1C — — — RC4 6 — C2OUT — P1B — — — RC5 5 — — — CCP1/P1A — — — RC6 8 AN8 — — — — — — RC7 9 AN9 — — — — — — — 1 — — — — — — VDD — 20 — — — — — — VSS Note 1: Pull-up activated only with external MCLR configuration. DS40001262F-page 4  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 PIC16F687/689 Pin Diagram 20-pin PDIP, SOIC, SSOP VDD 1 20 VSS RA5/T1CKI/OSC1/CLKIN 2 19 RA0/AN0/C1IN+/ICSPDAT/ULPWU RA4/AN3/T1G/OSC2/CLKOUT 3 9 18 RA1/AN1/C12IN0-/VREF/ICSPCLK RA3/MCLR/VPP 4 68 17 RA2/AN2/T0CKI/INT/C1OUT RC5 5 87/ 16 RC0/AN4/C2IN+ 6 RC4/C2OUT 6 F 15 RC1/AN5/C12IN1- 6 RC3/AN7/C12IN3- 7 C1 14 RC2/AN6/C12IN2- RC6/AN8/SS 8 PI 13 RB4/AN10/SDI/SDA RC7/AN9/SDO 9 12 RB5/AN11/RX/DT RB7/TX/CK 10 11 RB6/SCK/SCL TABLE 4: PIC16F687/689 PIN SUMMARY I/O Pin Analog Comparators Timers EUSART SSP Interrupt Pull-up Basic RA0 19 AN0/ULPWU C1IN+ — — — IOC Y ICSPDAT RA1 18 AN1/VREF C12IN0- — — — IOC Y ICSPCLK RA2 17 AN2 C1OUT T0CKI — — IOC/INT Y RA3 4 — — — — — IOC Y(1) MCLR/VPP RA4 3 AN3 — T1G — — IOC Y OSC2/CLKOUT RA5 2 — — T1CKI — — IOC Y OSC1/CLKIN RB4 13 AN10 — — — SDI/SDA IOC Y — RB5 12 AN11 — — RX/DT — IOC Y — RB6 11 — — — — SCL/SCK IOC Y — RB7 10 — — — TX/CK — IOC Y — RC0 16 AN4 C2IN+ — — — — — — RC1 15 AN5 C12IN1- — — — — — — RC2 14 AN6 C12IN2- — — — — — — RC3 7 AN7 C12IN3- — — — — — — RC4 6 — C2OUT — — — — — — RC5 5 — — — — — — — — RC6 8 AN8 — — — SS — — — RC7 9 AN9 — — — SDO — — — — 1 — — — — — — — VDD — 20 — — — — — — — VSS Note1: Pull-up activated only with external MCLR configuration.  2005-2015 Microchip Technology Inc. DS40001262F-page 5

PIC16F631/677/685/687/689/690 PIC16F690 Pin Diagram (PDIP, SOIC, SSOP) 20-pin PDIP, SOIC, SSOP VDD 1 20 VSS RA5/T1CKI/OSC1/CLKIN 2 19 RA0/AN0/C1IN+/ICSPDAT/ULPWU RA4/AN3/T1G/OSC2/CLKOUT 3 18 RA1/AN1/C12IN0-/VREF/ICSPCLK RA3/MCLR/VPP 4 0 17 RA2/AN2/T0CKI/INT/C1OUT 9 RC5/CCP1/P1A 5 6 16 RC0/AN4/C2IN+ F RC4/C2OUT/P1B 6 16 15 RC1/AN5/C12IN1- RC3/AN7/C12IN3-/P1C 7 PIC 14 RC2/AN6/C12IN2-/P1D RC6/AN8/SS 8 13 RB4/AN10/SDI/SDA RC7/AN9/SDO 9 12 RB5/AN11/RX/DT RB7/TX/CK 10 11 RB6/SCK/SCL TABLE 5: PIC16F690 PIN SUMMARY I/O Pin Analog Comparators Timers ECCP EUSART SSP Interrupt Pull-up Basic RA0 19 AN0/ULPWU C1IN+ — — — — IOC Y ICSPDAT RA1 18 AN1/VREF C12IN0- — — — — IOC Y ICSPCLK RA2 17 AN2 C1OUT T0CKI — — — IOC/INT Y RA3 4 — — — — — — IOC Y(1) MCLR/VPP RA4 3 AN3 — T1G — — — IOC Y OSC2/CLKOUT RA5 2 — — T1CKI — — — IOC Y OSC1/CLKIN RB4 13 AN10 — — — — SDI/SDA IOC Y — RB5 12 AN11 — — — RX/DT — IOC Y — RB6 11 — — — — SCL/SCK IOC Y — RB7 10 — — — — TX/CK — IOC Y — RC0 16 AN4 C2IN+ — — — — — — — RC1 15 AN5 C12IN1- — — — — — — — RC2 14 AN6 C12IN2- — P1D — — — — — RC3 7 AN7 C12IN3- — P1C — — — — — RC4 6 — C2OUT — P1B — — — — — RC5 5 — — — CCP1/P1A — — — — — RC6 8 AN8 — — — — SS — — — RC7 9 AN9 — — — — SDO — — — — 1 — — — — — — — — VDD — 20 — — — — — — — — VSS Note 1: Pull-up activated only with external MCLR configuration. DS40001262F-page 6  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 PIC16F631/677/685/687/689/690 Pin Diagram (QFN) 20-pin QFN U W UT ULP OSC2/CLKO C1/CLKIN +/ICSPDAT/ 3/T1G/ CKI/OS 0/C1IN N 1 N A T A 4/ 5/ D S 0/ A A D S A R R V V R 20 19 18 17 16 RA3/MCLR/VPP 1 15 RA1/AN1/C12IN0-/VREF/ICSPCLK RC5/CCP1/P1A(1) 2 14 RA2/AN2/T0CKI/INT/C1OUT PIC16F631/677/ RC4/C2OUT/P1B(1) 3 13 RC0/AN4/C2IN+ 685/687/689/690 RC3/AN7/C12IN3-/P1C(1) 4 12 RC1/AN5/C12IN1- RC6/AN8/SS(2) 5 11 RC2/AN6/C12IN2-/P1D(1) 0 6 7 8 9 1 2) 3) 2) 3) 2) (O (K (L (T (A D C C D D RC7/AN9/S RB7/TX/ RB6/SCK/S 5/AN11/RX/ AN10/SDI/S RB 4/ B R Note 1: CCP1/P1A, P1B, P1C and P1D are available on PIC16F685/PIC16F690 only. 2: SS, SDO, SDI/SDA and SCL/SCK are available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 3: RX/DT and TX/CK are available on PIC16F687/PIC16F689/PIC16F690 only.  2005-2015 Microchip Technology Inc. DS40001262F-page 7

PIC16F631/677/685/687/689/690 Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Memory Organization.................................................................................................................................................................24 3.0 Oscillator Module (With Fail-Safe Clock Monitor).......................................................................................................................45 4.0 I/O Ports.....................................................................................................................................................................................57 5.0 Timer0 Module...........................................................................................................................................................................79 6.0 Timer1 Module with Gate Control...............................................................................................................................................82 7.0 Timer2 Module...........................................................................................................................................................................89 8.0 Comparator Module....................................................................................................................................................................91 9.0 Analog-to-Digital Converter (ADC) Module..............................................................................................................................105 10.0 Data EEPROM and Flash Program Memory Control...............................................................................................................117 11.0 Enhanced Capture/Compare/PWM Module.............................................................................................................................125 12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................148 13.0 SSP Module Overview.............................................................................................................................................................175 14.0 Special Features of the CPU....................................................................................................................................................193 15.0 Instruction Set Summary..........................................................................................................................................................212 16.0 Development Support...............................................................................................................................................................221 17.0 Electrical Specifications............................................................................................................................................................225 18.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................258 19.0 Packaging Information..............................................................................................................................................................285 The Microchip Web Site.....................................................................................................................................................................295 Customer Change Notification Service..............................................................................................................................................295 Customer Support..............................................................................................................................................................................295 Product Identification System.............................................................................................................................................................296 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E- mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS40001262F-page 8  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 1.0 DEVICE OVERVIEW Block Diagrams and pinout descriptions of the devices are as follows: The PIC16F631/677/685/687/689/690 devices are • PIC16F631 (Figure1-1, Table1-1) covered by this data sheet. They are available in 20-pin PDIP, SOIC, TSSOP and QFN packages. • PIC16F677 (Figure1-2, Table1-2) • PIC16F685 (Figure1-3, Table1-3) • PIC16F687/PIC16F689 (Figure1-4, Table1-4) • PIC16F690 (Figure1-5, Table1-5) FIGURE 1-1: PIC16F631 BLOCK DIAGRAM INT Configuration 13 Data Bus 8 PORTA Program Counter Flash RA0 1K x 14 RA1 RA2 Program RAM 8-Level Stack (13-bit) RA3 Memory 64 bytes RA4 File RA5 Registers Program 14 Bus RAM Addr 9 PORTB Addr MUX Instruction Reg Direct Addr 7 Indirect RB4 8 Addr RB5 RB6 FSR Reg RB7 STATUS Reg 8 PORTC RC0 3 RC1 MUX Power-up RC2 Timer RC3 Instruction RC4 Decode and Oscillator RC5 Control Start-up Timer ALU RC6 OSC1/CLKI Power-on 8 RC7 Reset Timing OSC2/CLKO Generation Watchdog W Reg Timer Brown-out Reset Internal Oscillator Block MCLR VDD VSS C1IN- C1IN+ C1OUTC2IN- C2IN+ C2OUT ULPWU T0CKI T1G T1CKI EEDAT 128 Bytes Data EEPROM 2 Ultra Low-Power Timer0 Timer1 EEADR Analog Comparators Wake-up and Reference 8  2005-2015 Microchip Technology Inc. DS40001262F-page 9

PIC16F631/677/685/687/689/690 FIGURE 1-2: PIC16F677 BLOCK DIAGRAM INT Configuration 13 Data Bus 8 PORTA Program Counter Flash RA0 2K x 14 RA1 RA2 Program RAM 8-Level Stack (13-bit) RA3 Memory 128 bytes RA4 File RA5 Registers Program 14 Bus RAM Addr 9 PORTB Addr MUX Instruction Reg Direct Addr 7 Indirect RB4 8 Addr RB5 RB6 FSR Reg RB7 STATUS Reg 8 PORTC RC0 3 MUX RC1 Power-up RC2 Timer RC3 Instruction RC4 Decode and Oscillator Control Start-up Timer ALU RC5 RC6 OSC1/CLKI Power-on 8 RC7 Reset Timing OSC2/CLKO Generation Watchdog W Reg Timer Brown-out Reset Internal Oscillator Block MCLR VDD VSS SDI/ SCK/ ULPWU T0CKI T1G T1CKI SDOSDA SCL SS Ultra Low-Power Synchronous Timer0 Timer1 Wake-up Serial Port AN8AN9AN10AN11 EEDAT 8 256 Bytes 2 Data Analog-to-Digital Converter Analog Comparators EEPROM and Reference EEADR VREFAN0AN1AN2AN3AN4AN5AN6AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT DS40001262F-page 10  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 1-3: PIC16F685 BLOCK DIAGRAM INT Configuration 13 8 Data Bus PORTA Program Counter Flash RA0 4K x 14 RA1 Program RAM RA2 Memory 8-Level Stack (13-bit) 256 bytes RA3 File RA4 Registers RA5 Program 14 Bus RAM Addr 9 PORTB Addr MUX Instruction Reg Direct Addr 7 Indirect RB4 8 Addr RB5 RB6 FSR Reg RB7 STATUS Reg 8 PORTC RC0 3 MUX RC1 Power-up RC2 Timer RC3 Instruction Decode and Oscillator RC4 Control Start-up Timer ALU RC5 RC6 OSC1/CLKI Power-on 8 RC7 Reset Timing OSC2/CLKO Generation Watchdog W Reg Timer Brown-out Reset Internal Oscillator Block MCLR VDD VSS CCP1/ ULPWU T0CKI T1G T1CKI P1A P1B P1C P1D Ultra Low-Power Timer0 Timer1 Timer2 ECCP+ Wake-up AN8AN9AN10 AN11 EEDAT 8 256 Bytes 2 Data Analog-to-Digital Converter Analog Comparators EEPROM and Reference EEADR VREFAN0AN1AN2AN3AN4AN5AN6AN7 C1IN- C1IN+ C1OUTC2IN- C2IN+ C2OUT  2005-2015 Microchip Technology Inc. DS40001262F-page 11

PIC16F631/677/685/687/689/690 FIGURE 1-4: PIC16F687/PIC16F689 BLOCK DIAGRAM INT Configuration 13 8 Data Bus PORTA Program Counter Flash RA0 2K(1)/4K x 14 RA1 Program RAM RA2 Memory 8-Level Stack (13-bit) 128(1)/256 bytes RA3 File RA4 Registers RA5 Program 14 Bus RAM Addr 9 PORTB Addr MUX Instruction Reg Direct Addr 7 Indirect RB4 8 Addr RB5 FSR Reg RB6 RB7 STATUS Reg 8 PORTC RC0 3 MUX RC1 Power-up RC2 Timer RC3 Instruction Decode and Oscillator RC4 Control Start-up Timer ALU RC5 RC6 OSC1/CLKI Power-on 8 RC7 Reset Timing OSC2/CLKO Generation Watchdog W Reg Timer Brown-out Reset Internal Oscillator Block MCLR VDD VSS SDI/ SCK/ ULPWU T0CKI T1G T1CKI TX/CK RX/DT SDOSDA SCL SS Ultra Low-Power Synchronous Timer0 Timer1 EUSART Wake-up Serial Port AN8AN9AN10 AN11 EEDAT 8 256 Bytes 2 Data Analog-to-Digital Converter Analog Comparators EEPROM and Reference EEADR VREFAN0AN1AN2AN3AN4AN5AN6AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT Note 1: PIC16F687 only. DS40001262F-page 12  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 1-5: PIC16F690 BLOCK DIAGRAM INT Configuration 13 8 Data Bus PORTA Program Counter Flash RA0 4k x 14 RA1 Program RAM RA2 Memory 8-Level Stack (13-bit) 256 bytes RA3 File RA4 Registers RA5 Program 14 Bus RAM Addr 9 PORTB Addr MUX Instruction Reg Direct Addr 7 Indirect RB4 8 Addr RB5 FSR Reg RB6 RB7 STATUS Reg 8 PORTC RC0 3 MUX RC1 Power-up RC2 Timer RC3 Instruction Decode and Oscillator RC4 Control Start-up Timer ALU RC5 RC6 OSC1/CLKI Power-on 8 RC7 Reset Timing OSC2/CLKO Generation Watchdog W Reg Timer Brown-out Reset Internal Oscillator Block MCLR VDD VSS CCP1/ SDI/ SCK/ ULPWU T0CKI T1G T1CKI TX/CK RX/DT P1A P1B P1CP1D SDOSDA SCL SS Ultra Low-Power Synchronous Timer0 Timer1 Timer2 EUSART ECCP+ Wake-up Serial Port AN8AN9AN10AN11 EEDAT 8 256 Bytes 2 Data Analog-to-Digital Converter Analog Comparators EEPROM and Reference EEADR VREFAN0AN1AN2AN3AN4AN5AN6AN7 C1IN- C1IN+ C1OUTC2IN- C2IN+ C2OUT  2005-2015 Microchip Technology Inc. DS40001262F-page 13

PIC16F631/677/685/687/689/690 TABLE 1-1: PINOUT DESCRIPTION – PIC16F631 Input Output Name Function Description Type Type RA0/C1IN+/ICSPDAT/ULPWU RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. C1IN+ AN — Comparator C1 non-inverting input. ICSPDAT ST CMOS ICSP™ Data I/O. ULPWU AN — Ultra Low-Power Wake-up input. RA1/C12IN0-/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. C12IN0- AN — Comparator C1 or C2 inverting input. ICSPCLK ST — ICSP™ clock. RA2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. T0CKI ST — Timer0 clock input. INT ST — External interrupt pin. C1OUT — CMOS Comparator C1 output. RA3/MCLR/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on- change. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RA4/T1G/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. T1G ST — Timer1 gate input. OSC2 — XTAL Crystal/Resonator. CLKOUT — CMOS FOSC/4 output. RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. T1CKI ST — Timer1 clock input. OSC1 XTAL — Crystal/Resonator. CLKIN ST — External clock input/RC oscillator connection. RB4 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. RB5 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. RB6 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. RB7 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. RC0/C2IN+ RC0 ST CMOS General purpose I/O. C2IN+ AN — Comparator C2 non-inverting input. RC1/C12IN1- RC1 ST CMOS General purpose I/O. C12IN1- AN — Comparator C1 or C2 inverting input. RC2/C12IN2- RC2 ST CMOS General purpose I/O. C12IN2- AN — Comparator C1 or C2 inverting input. RC3/C12IN3- RC3 ST CMOS General purpose I/O. C12IN3- AN — Comparator C1 or C2 inverting input. RC4/C2OUT RC4 ST CMOS General purpose I/O. C2OUT — CMOS Comparator C2 output. RC5 RC5 ST CMOS General purpose I/O. Legend: AN = Analog input or output CMOS=CMOS compatible input or output TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels HV = High Voltage XTAL= Crystal DS40001262F-page 14  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 1-1: PINOUT DESCRIPTION – PIC16F631 (CONTINUED) Input Output Name Function Description Type Type RC6 RC6 ST CMOS General purpose I/O. RC7 RC7 ST CMOS General purpose I/O. VSS VSS Power — Ground reference. VDD VDD Power — Positive supply. Legend: AN = Analog input or output CMOS=CMOS compatible input or output TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels HV = High Voltage XTAL= Crystal  2005-2015 Microchip Technology Inc. DS40001262F-page 15

PIC16F631/677/685/687/689/690 TABLE 1-2: PINOUT DESCRIPTION – PIC16F677 Input Output Name Function Description Type Type RA0/AN0/C1IN+/ICSPDAT/ RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. ULPWU Individually enabled pull-up. AN0 AN — A/D Channel 0 input. C1IN+ AN — Comparator C1 non-inverting input. ICSPDAT ST CMOS ICSP™ Data I/O. ULPWU AN — Ultra Low-Power Wake-up input. RA1/AN1/C12IN0-/VREF/ RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. ICSPCLK Individually enabled pull-up. AN1 AN — A/D Channel 1 input. C12IN0- AN — Comparator C1 or C2 inverting input. VREF AN — External Voltage Reference for A/D. ICSPCLK ST — ICSP™ clock. RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN2 AN — A/D Channel 2 input. T0CKI ST — Timer0 clock input. INT ST — External interrupt pin. C1OUT — CMOS Comparator C1 output. RA3/MCLR/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on- change. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RA4/AN3/T1G/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN3 AN — A/D Channel 3 input. T1G ST — Timer1 gate input. OSC2 — XTAL Crystal/Resonator. CLKOUT — CMOS FOSC/4 output. RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. T1CKI ST — Timer1 clock input. OSC1 XTAL — Crystal/Resonator. CLKIN ST — External clock input/RC oscillator connection. RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN10 AN — A/D Channel 10 input. SDI ST — SPI data input. SDA ST OD I2C™ data input/output. RB5/AN11 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN11 AN — A/D Channel 11 input. RB6/SCK/SCL RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. SCK ST CMOS SPI clock. SCL ST OD I2C™ clock. Legend: AN = Analog input or output CMOS=CMOS compatible input or output TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels HV = High Voltage XTAL= Crystal DS40001262F-page 16  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 1-2: PINOUT DESCRIPTION – PIC16F677 (CONTINUED) Input Output Name Function Description Type Type RB7 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O. AN4 AN — A/D Channel 4 input. C2IN+ AN — Comparator C2 non-inverting input. RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O. AN5 AN — A/D Channel 5 input. C12IN1- AN — Comparator C1 or C2 inverting input. RC2/AN6/C12IN2- RC2 ST CMOS General purpose I/O. AN6 AN — A/D Channel 6 input. C12IN2- AN — Comparator C1 or C2 inverting input. RC3/AN7/C12IN3- RC3 ST CMOS General purpose I/O. AN7 AN — A/D Channel 7 input. C12IN3- AN — Comparator C1 or C2 inverting input. RC4/C2OUT RC4 ST CMOS General purpose I/O. C2OUT — CMOS Comparator C2 output. RC5 RC5 ST CMOS General purpose I/O. RC6/AN8/SS RC6 ST CMOS General purpose I/O. AN8 AN — A/D Channel 8 input. SS ST — Slave Select input. RC7/AN9/SDO RC7 ST CMOS General purpose I/O. AN9 AN — A/D Channel 9 input. SDO — CMOS SPI data output. VSS VSS Power — Ground reference. VDD VDD Power — Positive supply. Legend: AN = Analog input or output CMOS=CMOS compatible input or output TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels HV = High Voltage XTAL= Crystal  2005-2015 Microchip Technology Inc. DS40001262F-page 17

PIC16F631/677/685/687/689/690 TABLE 1-3: PINOUT DESCRIPTION – PIC16F685 Input Output Name Function Description Type Type RA0/AN0/C1IN+/ICSPDAT/ RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on- ULPWU change. Individually enabled pull-up. AN0 AN — A/D Channel 0 input. C1IN+ AN — Comparator C1 positive input. ICSPDAT TTL CMOS ICSP™ Data I/O. ULPWU AN — Ultra Low-Power Wake-up input. RA1/AN1/C12IN0-/VREF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN1 AN — A/D Channel 1 input. C12IN0- AN — Comparator C1 or C2 negative input. VREF AN — External Voltage Reference for A/D. ICSPCLK ST — ICSP™ clock. RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN2 AN — A/D Channel 2 input. T0CKI ST — Timer0 clock input. INT ST — External interrupt pin. C1OUT — CMOS Comparator C1 output. RA3/MCLR/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on- change. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RA4/AN3/T1G/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN3 AN — A/D Channel 3 input. T1G ST — Timer1 gate input. OSC2 — XTAL Crystal/Resonator. CLKOUT — CMOS FOSC/4 output. RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. T1CKI ST — Timer1 clock input. OSC1 XTAL — Crystal/Resonator. CLKIN ST — External clock input/RC oscillator connection. RB4/AN10 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN10 AN — A/D Channel 10 input. RB5/AN11 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN11 AN — A/D Channel 11 input. RB6 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. RB7 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O. AN4 AN — A/D Channel 4 input. C2IN+ AN — Comparator C2 positive input. Legend: AN = Analog input or output CMOS=CMOS compatible input or output TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels HV = High Voltage XTAL= Crystal DS40001262F-page 18  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 1-3: PINOUT DESCRIPTION – PIC16F685 (CONTINUED) Input Output Name Function Description Type Type RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O. AN5 AN — A/D Channel 5 input. C12IN1- AN — Comparator C1 or C2 negative input. RC2/AN6/C12IN2-/P1D RC2 ST CMOS General purpose I/O. AN6 AN — A/D Channel 6 input. C12IN2- AN — Comparator C1 or C2 negative input. P1D — CMOS PWM output. RC3/AN7/C12IN3-/P1C RC3 ST CMOS General purpose I/O. AN7 AN — A/D Channel 7 input. C12IN3- AN — Comparator C1 or C2 negative input. P1C — CMOS PWM output. RC4/C2OUT/P1B RC4 ST CMOS General purpose I/O. C2OUT — CMOS Comparator C2 output. P1B — CMOS PWM output. RC5/CCP1/P1A RC5 ST CMOS General purpose I/O. CCP1 ST CMOS Capture/Compare input. P1A ST CMOS PWM output. RC6/AN8 RC6 ST CMOS General purpose I/O. AN8 AN — A/D Channel 8 input. RC7/AN9 RC7 ST CMOS General purpose I/O. AN9 AN — A/D Channel 9 input. VSS VSS Power — Ground reference. VDD VDD Power — Positive supply. Legend: AN = Analog input or output CMOS=CMOS compatible input or output TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels HV = High Voltage XTAL= Crystal  2005-2015 Microchip Technology Inc. DS40001262F-page 19

PIC16F631/677/685/687/689/690 TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689 Input Output Name Function Description Type Type RA0/AN0/C1IN+/ICSPDAT/ RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on- ULPWU change. Individually enabled pull-up. AN0 AN — A/D Channel 0 input. C1IN+ AN — Comparator C1 positive input. ICSPDAT TTL CMOS ICSP™ Data I/O. ULPWU AN — Ultra Low-Power Wake-up input. RA1/AN1/C12IN0-/VREF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN1 AN — A/D Channel 1 input. C12IN0- AN — Comparator C1 or C2 negative input. VREF AN — External Voltage Reference for A/D. ICSPCLK ST — ICSP™ clock. RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN2 AN — A/D Channel 2 input. T0CKI ST — Timer0 clock input. INT ST — External Interrupt. C1OUT — CMOS Comparator C1 output. RA3/MCLR/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on-change. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RA4/AN3/T1G/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN3 AN — A/D Channel 3 input. T1G ST — Timer1 gate input. OSC2 — XTAL Crystal/Resonator. CLKOUT — CMOS FOSC/4 output. RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. T1CKI ST — Timer1 clock input. OSC1 XTAL — Crystal/Resonator. CLKIN ST — External clock input/RC oscillator connection. RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN10 AN — A/D Channel 10 input. SDI ST — SPI data input. SDA ST OD I2C™ data input/output. RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN11 AN — A/D Channel 11 input. RX ST — EUSART asynchronous input. DT ST CMOS EUSART synchronous data. Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels HV = High Voltage XTAL= Crystal DS40001262F-page 20  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689 (CONTINUED) Input Output Name Function Description Type Type RB6/SCK/SCL RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. SCK ST CMOS SPI clock. SCL ST OD I2C™ clock. RB7/TX/CK RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. TX — CMOS EUSART asynchronous output. CK ST CMOS EUSART synchronous clock. RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O. AN4 AN — A/D Channel 4 input. C2IN+ AN — Comparator C2 positive input. RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O. AN5 AN — A/D Channel 5 input. C12IN1- AN — Comparator C1 or C2 negative input. RC2/AN6/C12IN2- RC2 ST CMOS General purpose I/O. AN6 AN — A/D Channel 6 input. C12IN2- AN — Comparator C1 or C2 negative input. RC3/AN7/C12IN3- RC3 ST CMOS General purpose I/O. AN7 AN — A/D Channel 7 input. C12IN3- AN — Comparator C1 or C2 negative input. RC4/C2OUT RC4 ST CMOS General purpose I/O. C2OUT — CMOS Comparator C2 output. RC5 RC5 ST CMOS General purpose I/O. RC6/AN8/SS RC6 ST CMOS General purpose I/O. AN8 AN — A/D Channel 8 input. SS ST — Slave Select input. RC7/AN9/SDO RC7 ST CMOS General purpose I/O. AN9 AN — A/D Channel 9 input. SDO — CMOS SPI data output. VSS VSS Power — Ground reference. VDD VDD Power — Positive supply. Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels HV = High Voltage XTAL= Crystal  2005-2015 Microchip Technology Inc. DS40001262F-page 21

PIC16F631/677/685/687/689/690 TABLE 1-5: PINOUT DESCRIPTION – PIC16F690 Input Output Name Function Description Type Type RA0/AN0/C1IN+/ICSPDAT/ RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on- ULPWU change. Individually enabled pull-up. AN0 AN — A/D Channel 0 input. C1IN+ AN — Comparator C1 positive input. ICSPDAT TTL CMOS ICSP™ Data I/O. ULPWU AN — Ultra Low-Power Wake-up input. RA1/AN1/C12IN0-/VREF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN1 AN — A/D Channel 1 input. C12IN0- AN — Comparator C1 or C2 negative input. VREF AN — External Voltage Reference for A/D. ICSPCLK ST — ICSP™ clock. RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN2 AN — A/D Channel 2 input. T0CKI ST — Timer0 clock input. INT ST — External interrupt. C1OUT — CMOS Comparator C1 output. RA3/MCLR/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on- change. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RA4/AN3/T1G/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN3 AN — A/D Channel 3 input. T1G ST — Timer1 gate input. OSC2 — XTAL Crystal/Resonator. CLKOUT — CMOS FOSC/4 output. RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. T1CKI ST — Timer1 clock input. OSC1 XTAL — Crystal/Resonator. CLKIN ST — External clock input/RC oscillator connection. RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN10 AN — A/D Channel 10 input. SDI ST — SPI data input. SDA ST OD I2C™ data input/output. RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. AN11 AN — A/D Channel 11 input. RX ST — EUSART asynchronous input. DT ST CMOS EUSART synchronous data. Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels HV = High Voltage XTAL= Crystal DS40001262F-page 22  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 1-5: PINOUT DESCRIPTION – PIC16F690 (CONTINUED) Input Output Name Function Description Type Type RB6/SCK/SCL RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. SCK ST CMOS SPI clock. SCL ST OD I2C™ clock. RB7/TX/CK RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on- change. Individually enabled pull-up. TX — CMOS EUSART asynchronous output. CK ST CMOS EUSART synchronous clock. RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O. AN4 AN — A/D Channel 4 input. C2IN+ AN — Comparator C2 positive input. RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O. AN5 AN — A/D Channel 5 input. C12IN1- AN — Comparator C1 or C2 negative input. RC2/AN6/C12IN2-/P1D RC2 ST CMOS General purpose I/O. AN6 AN — A/D Channel 6 input. C12IN2- AN — Comparator C1 or C2 negative input. P1D — CMOS PWM output. RC3/AN7/C12IN3-/P1C RC3 ST CMOS General purpose I/O. AN7 AN — A/D Channel 7 input. C12IN3- AN — Comparator C1 or C2 negative input. P1C — CMOS PWM output. RC4/C2OUT/P1B RC4 ST CMOS General purpose I/O. C2OUT — CMOS Comparator C2 output. P1B — CMOS PWM output. RC5/CCP1/P1A RC5 ST CMOS General purpose I/O. CCP1 ST CMOS Capture/Compare input. P1A ST CMOS PWM output. RC6/AN8/SS RC6 ST CMOS General purpose I/O. AN8 AN — A/D Channel 8 input. SS ST — Slave Select input. RC7/AN9/SDO RC7 ST CMOS General purpose I/O. AN9 AN — A/D Channel 9 input. SDO — CMOS SPI data output. VSS VSS Power — Ground reference. VDD VDD Power — Positive supply. Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels HV = High Voltage XTAL= Crystal  2005-2015 Microchip Technology Inc. DS40001262F-page 23

PIC16F631/677/685/687/689/690 2.0 MEMORY ORGANIZATION FIGURE 2-2: PROGRAM MEMORY MAP AND STACK FOR THE 2.1 Program Memory Organization PIC16F685/689/690 The PIC16F631/677/685/687/689/690 has a 13-bit program counter capable of addressing an 8Kx14 PC<12:0> program memory space. Only the first 1Kx14 (0000h- CALL, RETURN 13 03FFh) is physically implemented for the PIC16F631, RETFIE, RETLW the first 2Kx14 (0000h-07FFh) for the PIC16F677/ PIC16F687, and the first 4Kx14 (0000h-0FFFh) for Stack Level 1 the PIC16F685/PIC16F689/PIC16F690. Accessing a Stack Level 2 location above these boundaries will cause a wrap- around. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures2-1 through 2-3). Stack Level 8 FIGURE 2-1: PROGRAM MEMORY MAP Reset Vector 0000h AND STACK FOR THE PIC16F631 Interrupt Vector 0004h 0005h Page 0 On-Chip PC<12:0> 07FFh Program 0800h Memory CALL, RETURN 13 Page 1 RETFIE, RETLW 0FFFh 1000h Stack Level 1 Access 0-FFFh Stack Level 2 1FFFh Stack Level 8 Reset Vector 0000h FIGURE 2-3: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F677/PIC16F687 Interrupt Vector 0004h On-Chip 0005h Page 0 Memory 03FFh PC<12:0> 0400h CALL, RETURN 13 Access 0-3FFh RETFIE, RETLW 1FFFh Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h On-Chip 0005h Page 0 Memory 07FFh 0800h Access 0-7FFh 1FFFh DS40001262F-page 24  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 2.2 Data Memory Organization The data memory (see Figures2-6 through2-8) is partitioned into four banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. The General Purpose Registers, implemented as static RAM, are located in the last 96 locations of each Bank. Register locations F0h-FFh in Bank 1, 170h-17Fh in Bank 2 and 1F0h-1FFh in Bank 3 point to addresses 70h-7Fh in Bank0. The actual number of General Purpose Resisters (GPR) in each Bank depends on the device. Details are shown in Figures2-4 through2-8. All other RAM is unimplemented and returns ‘0’ when read. RP<1:0> of the STATUS register are the bank select bits: RP1 RP0 0 0  Bank 0 is selected 0 1  Bank 1 is selected 1 0  Bank 2 is selected 1 1  Bank 3 is selected 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 x 8 in the PIC16F687 and 256 x 8 in the PIC16F685/PIC16F689/ PIC16F690. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Tables2-1 through2-4). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Registers related to the operation of peripheral features are described in the section of that peripheral feature.  2005-2015 Microchip Technology Inc. DS40001262F-page 25

PIC16F631/677/685/687/689/690 FIGURE 2-4: PIC16F631 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h PORTA 105h TRISA 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h PORTC 107h TRISC 187h 08h 88h 108h 188h 09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh T1CON 10h OSCTUNE 90h 110h 190h 11h 91h 111h 191h 12h 92h 112h 192h 13h 93h 113h 193h 14h 94h 114h 194h 15h WPUA 95h WPUB 115h 195h 16h IOCA 96h IOCB 116h 196h 17h WDTCON 97h 117h 197h 18h 98h VRCON 118h 198h 19h 99h CM1CON0 119h 199h 1Ah 9Ah CM2CON0 11Ah 19Ah 1Bh 9Bh CM2CON1 11Bh 19Bh 1Ch 9Ch 11Ch 19Ch 1Dh 9Dh 11Dh 19Dh 1Eh 9Eh ANSEL 11Eh SRCON 19Eh 1Fh 9Fh 11Fh 19Fh 20h A0h 120h 1A0h 3Fh General 40h Purpose Registers 6Fh EFh 16Fh 1EFh 64 Bytes 70h accesses F0h accesses 170h accesses 1F0h 7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. DS40001262F-page 26  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 2-5: PIC16F677 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h PORTA 105h TRISA 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h PORTC 107h TRISC 187h 08h 88h 108h 188h 09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh T1CON 10h OSCTUNE 90h 110h 190h 11h 91h 111h 191h 12h 92h 112h 192h SSPBUF 13h SSPADD(2) 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h 15h WPUA 95h WPUB 115h 195h 16h IOCA 96h IOCB 116h 196h 17h WDTCON 97h 117h 197h 18h 98h VRCON 118h 198h 19h 99h CM1CON0 119h 199h 1Ah 9Ah CM2CON0 11Ah 19Ah 1Bh 9Bh CM2CON1 11Bh 19Bh 1Ch 9Ch 11Ch 19Ch 1Dh 9Dh 11Dh 19Dh ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh 19Fh 20h General A0h 120h 1A0h Purpose Register General Purpose 32 Bytes BFh Register C0h 96 Bytes EFh 16Fh 1EFh accesses F0h accesses 170h accesses 1F0h 7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. 2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions. See Registers13-2 and13-3 for more details.  2005-2015 Microchip Technology Inc. DS40001262F-page 27

PIC16F631/677/685/687/689/690 FIGURE 2-6: PIC16F685 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h PORTA 105h TRISA 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h PORTC 107h TRISC 187h 08h 88h 108h 188h 09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh 18Fh T1CON 10h OSCTUNE 90h 110h 190h TMR2 11h 91h 111h 191h T2CON 12h PR2 92h 112h 192h 13h 93h 113h 193h 14h 94h 114h 194h CCPR1L 15h WPUA 95h WPUB 115h 195h CCPR1H 16h IOCA 96h IOCB 116h 196h CCP1CON 17h WDTCON 97h 117h 197h 18h 98h VRCON 118h 198h 19h 99h CM1CON0 119h 199h 1Ah 9Ah CM2CON0 11Ah 19Ah 1Bh 9Bh CM2CON1 11Bh 19Bh PWM1CON 1Ch 9Ch 11Ch 19Ch ECCPAS 1Dh 9Dh 11Dh PSTRCON 19Dh ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh 19Fh 20h A0h 120h 1A0h General General General Purpose Purpose Purpose Register Register Register 80 Bytes 80 Bytes 96 Bytes EFh 16Fh accesses F0h accesses 170h accesses 1F0h 7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. DS40001262F-page 28  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 2-7: PIC16F687/PIC16F689 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h PORTA 105h TRISA 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h PORTC 107h TRISC 187h 08h 88h 108h 188h 09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh TMR1L 0Eh PCON 8Eh EEDATH(3) 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh EEADRH(3) 10Fh 18Fh T1CON 10h OSCTUNE 90h 110h 190h 11h 91h 111h 191h 12h 92h 112h 192h SSPBUF 13h SSPADD(2) 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h 15h WPUA 95h WPUB 115h 195h 16h IOCA 96h IOCB 116h 196h 17h WDTCON 97h 117h 197h RCSTA 18h TXSTA 98h VRCON 118h 198h TXREG 19h SPBRG 99h CM1CON0 119h 199h RCREG 1Ah SPBRGH 9Ah CM2CON0 11Ah 19Ah 1Bh BAUDCTL 9Bh CM2CON1 11Bh 19Bh 1Ch 9Ch 11Ch 19Ch 1Dh 9Dh 11Dh 19Dh ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh 19Fh 20h A0h 120h 1A0h General General Purpose Purpose Register General Register 32 Bytes Purpose BFh 80 Bytes Register 48 Bytes C0h (PIC16F689 (PIC16F689 only) 96 Bytes only) EFh accesses F0h accesses 170h accesses 1F0h 7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. 2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions. See Registers13-2 and13-3 for more details. 3: PIC16F689 only.  2005-2015 Microchip Technology Inc. DS40001262F-page 29

PIC16F631/677/685/687/689/690 FIGURE 2-8: PIC16F690 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h PORTA 105h TRISA 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h PORTC 107h TRISC 187h 08h 88h 108h 188h 09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh 18Eh TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh 18Fh T1CON 10h OSCTUNE 90h 110h 190h TMR2 11h 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD(2) 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPR1L 15h WPUA 95h WPUB 115h 195h CCPR1H 16h IOCA 96h IOCB 116h 196h CCP1CON 17h WDTCON 97h 117h 197h RCSTA 18h TXSTA 98h VRCON 118h 198h TXREG 19h SPBRG 99h CM1CON0 119h 199h RCREG 1Ah SPBRGH 9Ah CM2CON0 11Ah 19Ah 1Bh BAUDCTL 9Bh CM2CON1 11Bh 19Bh PWM1CON 1Ch 9Ch 11Ch 19Ch ECCPAS 1Dh 9Dh 11Dh PSTRCON 19Dh ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh 19Fh 20h A0h 120h 1A0h General General General Purpose Purpose Purpose Register Register Register 80 Bytes 80 Bytes 96 Bytes EFh 16Fh accesses F0h accesses 170h accesses 1F0h 7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. 2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions. See Registers13-2 and13-3 for more details. DS40001262F-page 30  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 2-1: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOR Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200 01h TMR0 Timer0 Module Register xxxx xxxx 79,200 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200 03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 35,200 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200 05h PORTA(7) — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx 57,200 06h PORTB(7) RB7 RB6 RB5 RB4 — — — — xxxx ---- 67,200 07h PORTC(7) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 74,200 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 43,200 0Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 37,200 0Ch PIR1 — ADIF(4) RCIF(2) TXIF(2) SSPIF(5) CCP1IF(3) TMR2IF(3) TMR1IF -000 0000 40,200 0Dh PIR2 OSFIF C2IF C1IF EEIF — — — — 0000 ---- 41,200 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 85,200 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 85,200 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 87,200 11h TMR2(3) Timer2 Module Register 0000 0000 89,200 12h T2CON(3) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 90,200 13h SSPBUF(5) Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 178,200 14h SSPCON(5, 6) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 177,200 15h CCPR1L(3) Capture/Compare/PWM Register 1 (LSB) xxxx xxxx 126,200 16h CCPR1H(3) Capture/Compare/PWM Register 1 (MSB) xxxx xxxx 126,200 17h CCP1CON(3) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 125,200 18h RCSTA(2) SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 158,200 19h TXREG(2) EUSART Transmit Data Register 0000 0000 150 1Ah RCREG(2) EUSART Receive Data Register 0000 0000 155 1Bh — Unimplemented — — 1Ch PWM1CON(3) PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 143,200 1Dh ECCPAS(3) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 140,200 1Eh ADRESH(4) A/D Result Register High Byte xxxx xxxx 113,200 1Fh ADCON0(4) ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 111,200 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F687/PIC16F689/PIC16F690 only. 3: PIC16F685/PIC16F690 only. 4: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. 5: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 6: When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK register. See Registers13-2 and13-3 for more detail. 7: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets).  2005-2015 Microchip Technology Inc. DS40001262F-page 31

PIC16F631/677/685/687/689/690 TABLE 2-2: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOR Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200 81h OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 36,200 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200 83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 35,200 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200 85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 57,200 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 68,201 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 74,200 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 43,200 8Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 37,200 8Ch PIE1 — ADIE(4) RCIE(2) TXIE(2) SSPIE(5) CCP1IE(3) TMR2IE(3) TMR1IE -000 0000 38,201 8Dh PIE2 OSFIE C2IE C1IE EEIE — — — — 0000 ---- 39,201 8Eh PCON — — ULPWUE SBOREN — — POR BOR --01 --qq 42,201 8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 46,201 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 50,201 91h — Unimplemented — — 92h PR2(3) Timer2 Period Register 1111 1111 89,201 93h SSPADD(5, 7) Synchronous Serial Port (I2C mode) Address Register 0000 0000 184,201 93h SSPMSK(5, 7) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 187,201 94h SSPSTAT(5) SMP CKE D/A P S R/W UA BF 0000 0000 176,201 95h WPUA(6) — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 60,201 96h IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 60,201 97h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 208,201 98h TXSTA(2) CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 157,201 99h SPBRG(2) BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 160,201 9Ah SPBRGH(2) BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 160,201 9Bh BAUDCTL(2) ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 159,201 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh ADRESL(4) A/D Result Register Low Byte xxxx xxxx 113,201 9Fh ADCON1(4) — ADCS2 ADCS1 ADCS0 — — — — -000 ---- 112,201 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F687/PIC16F689/PIC16F690 only. 3: PIC16F685/PIC16F690 only. 4: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. 5: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 6: RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word. 7: Accessible only when SSPCON register bits SSPM<3:0> = 1001. DS40001262F-page 32  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 2-3: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOR Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200 101h TMR0 Timer0 Module Register xxxx xxxx 79,200 102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200 103h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 35,200 104h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200 105h PORTA(4) — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx 57,200 106h PORTB(4) RB7 RB6 RB5 RB4 — — — — xxxx ---- 67,200 107h PORTC(4) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 74,200 108h — Unimplemented — — 109h — Unimplemented — — 10Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 43,200 10Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 37,200 10Ch EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 118,201 10Dh EEADR EEADR7(3) EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 118,201 10Eh EEDATH(2) — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 118,201 10Fh EEADRH(2) — — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 118,201 110h — Unimplemented — — 111h — Unimplemented — — 112h — Unimplemented — — 113h — Unimplemented — — 114h — Unimplemented — — 115h WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 68,201 116h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 68,201 117h — Unimplemented — — 118h VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 103,201 119h CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 96,201 11Ah CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 97,201 11Bh CM2CON1 MC1OUT MC2OUT — — — — T1GSS C2SYNC 00-- --10 99,201 11Ch — Unimplemented — — 11Dh — Unimplemented — — 11Eh ANSEL ANS7 ANS6 ANS5 ANS4 ANS3(3) ANS2(3) ANS1 ANS0 1111 1111 59,201 11Fh ANSELH(3) — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 113,201 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F685/PIC16F689/PIC16F690 only. 3: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. 4: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets).  2005-2015 Microchip Technology Inc. DS40001262F-page 33

PIC16F631/677/685/687/689/690 TABLE 2-4: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOR Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200 181h OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 36,200 182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200 183h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 35,200 184h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200 185h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 57,200 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 68,201 187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 74,201 188h — Unimplemented — — 189h — Unimplemented — — 18Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 43,200 18Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 37,200 18Ch EECON1 EEPGD(2) — — — WRERR WREN WR RD x--- x000 119,201 18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 117,201 18Eh — Unimplemented — — 18Fh — Unimplemented — — 190h — Unimplemented — — 191h — Unimplemented — — 192h — Unimplemented — — 193h — Unimplemented — — 194h — Unimplemented — — 195h — Unimplemented — — 196h — Unimplemented — — 197h — Unimplemented — — 198h — Unimplemented — — 199h — Unimplemented — — 19Ah — Unimplemented — — 19Bh — Unimplemented — — 19Ch — Unimplemented — — 19Dh PSTRCON(2) — — — STRSYNC STRD STRC STRB STRA ---0 0001 144,201 19Eh SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — — 0000 00-- 101,201 19Fh — Unimplemented — — Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F685/PIC16F690 only. DS40001262F-page 34  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 2.2.2.1 STATUS Register For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register2-1, contains: as ‘000u u1uu’ (where u = unchanged). • the arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, • the Reset status SWAPF and MOVWF instructions are used to alter the • the bank select bits for data memory (GPR and STATUS register, because these instructions do not SFR) affect any Status bits. For other instructions not affect- The STATUS register can be the destination for any ing any Status bits, see Section15.0 “Instruction Set instruction, like any other register. If the STATUS Summary” register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the Note1: The C and DC bits operate as a Borrow device logic. Furthermore, the TO and PD bits are not and Digit Borrow out bit, respectively, in writable. Therefore, the result of an instruction with the subtraction. See the SUBLW and SUBWF STATUS register as destination may be different than instructions for examples. intended. REGISTER 2-1: STATUS: STATUS REGISTER R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.  2005-2015 Microchip Technology Inc. DS40001262F-page 35

PIC16F631/677/685/687/689/690 2.2.2.2 OPTION Register The OPTION register, shown in Register2-2, is a Note: To achieve a 1:1 prescaler assignment for readable and writable register, which contains various Timer0, assign the prescaler to the WDT control bits to configure: by setting PSA bit of the OPTION register • Timer0/WDT prescaler to ‘1’. See Section6.3 “Timer1 Pres- caler”. • External RA2/INT interrupt • Timer0 • Weak pull-ups on PORTA/PORTB REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RABPU: PORTA/PORTB Pull-up Enable bit 1 = PORTA/PORTB pull-ups are disabled 0 = PORTA/PORTB pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on RA2/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 DS40001262F-page 36  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 2.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt The INTCON register, shown in Register2-3, is a condition occurs, regardless of the state of readable and writable register, which contains the various its corresponding enable bit or the global enable and flag bits for TMR0 register overflow, PORTA enable bit, GIE of the INTCON register. change and external RA2/AN2/T0CKI/INT/C1OUT pin User software should ensure the interrupts. appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RABIE(1,3) T0IF(2) INTF RABIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: RA2/INT External Interrupt Enable bit 1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt bit 3 RABIE: PORTA/PORTB Change Interrupt Enable bit(1,3) 1 = Enables the PORTA/PORTB change interrupt 0 = Disables the PORTA/PORTB change interrupt bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: RA2/INT External Interrupt Flag bit 1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur bit 0 RABIF: PORTA/PORTB Change Interrupt Flag bit 1 = When at least one of the PORTA or PORTB general purpose I/O pins changed state (must be cleared in software) 0 = None of the PORTA or PORTB general purpose I/O pins have changed state Note 1: IOCA or IOCB register must also be enabled. 2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. 3: Includes ULPWU interrupt.  2005-2015 Microchip Technology Inc. DS40001262F-page 37

PIC16F631/677/685/687/689/690 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register2-4. set to enable any peripheral interrupt. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE(5) RCIE(3) TXIE(3) SSPIE(4) CCP1IE(2) TMR2IE(1) TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit(5) 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit(3) 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit(5) 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit(4) 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit(2) 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1) 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC16F685/PIC16F690 only. 2: PIC16F685/PIC16F689/PIC16F690 only. 3: PIC16F687/PIC16F689/PIC16F690 only. 4: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. DS40001262F-page 38  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 2.2.2.5 PIE2 Register The PIE2 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register2-5. set to enable any peripheral interrupt. REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 OSFIE C2IE C1IE EEIE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables oscillator fail interrupt 0 = Disables oscillator fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables Comparator C2 interrupt 0 = Disables Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables Comparator C1 interrupt 0 = Disables Comparator C1 interrupt bit 4 EEIE: EE Write Operation Interrupt Enable bit 1 = Enables write operation interrupt 0 = Disables write operation interrupt bit 3-0 Unimplemented: Read as ‘0’  2005-2015 Microchip Technology Inc. DS40001262F-page 39

PIC16F631/677/685/687/689/690 2.2.2.6 PIR1 Register The PIR1 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register2-6. condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIF(5) RCIF(3) TXIF(3) SSPIF(4) CCP1IF(2) TMR2IF(1) TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Converter Interrupt Flag bit(5) 1 = A/D conversion complete (must be cleared in software) 0 = A/D conversion has not completed or has not been started bit 5 RCIF: EUSART Receive Interrupt Flag bit(3) 1 = The EUSART receive buffer is full (cleared by reading RCREG) 0 = The EUSART receive buffer is not full bit 4 TXIF: EUSART Transmit Interrupt Flag bit(3) 1 = The EUSART transmit buffer is empty (cleared by writing to TXREG) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit(4) 1 = The Transmission/Reception is complete (must be cleared in software) 0 = Waiting to Transmit/Receive bit 2 CCP1IF: CCP1 Interrupt Flag bit(2) Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit(1) 1 = A Timer2 to PR2 match occurred (must be cleared in software) 0 = No Timer2 to PR2 match occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow Note 1: PIC16F685/PIC16F690 only. 2: PIC16F685/PIC16F689/PIC16F690 only. 3: PIC16F687/PIC16F689/PIC16F690 only. 4: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. DS40001262F-page 40  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 2.2.2.7 PIR2 Register The PIR2 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register2-7. condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 OSFIF C2IF C1IF EEIF — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 6 C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed bit 4 EEIF: EE Write Operation Interrupt Flag bit 1 = Write operation completed (must be cleared in software) 0 = Write operation has not completed or has not started bit 3-0 Unimplemented: Read as ‘0’  2005-2015 Microchip Technology Inc. DS40001262F-page 41

PIC16F631/677/685/687/689/690 2.2.2.8 PCON Register The Power Control (PCON) register (see Register2-8) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR. REGISTER 2-8: PCON: POWER CONTROL REGISTER U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x — — ULPWUE SBOREN(1) — — POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit 1 = Ultra Low-Power Wake-up enabled 0 = Ultra Low-Power Wake-up disabled bit 4 SBOREN: Software BOR Enable bit(1) 1 = BOR enabled 0 = BOR disabled bit 3-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR. DS40001262F-page 42  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 2.3 PCL and PCLATH 2.3.2 STACK The Program Counter (PC) is 13 bits wide. The low byte The PIC16F631/677/685/687/689/690 devices have an comes from the PCL register, which is a readable and 8-levelx13-bit wide hardware stack (see Figures2-2 writable register. The high byte (PC<12:8>) is not directly and 2-3). The stack space is not part of either program readable or writable and comes from PCLATH. On any or data space and the Stack Pointer is not readable or Reset, the PC is cleared. Figure2-9 shows the two writable. The PC is PUSHed onto the stack when a situations for the loading of the PC. The upper example CALL instruction is executed or an interrupt causes a in Figure2-9 shows how the PC is loaded on a write to branch. The stack is POPed in the event of a RETURN, PCL (PCLATH<4:0>  PCH). The lower example in RETLW or a RETFIE instruction execution. PCLATH is Figure2-9 shows how the PC is loaded during a CALL or not affected by a PUSH or POP operation. GOTO instruction (PCLATH<4:3>  PCH). The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth FIGURE 2-9: LOADING OF PC IN push overwrites the value that was stored from the first DIFFERENT SITUATIONS push. The tenth push overwrites the second push (and so on). PCH PCL Instruction with Note1: There are no Status bits to indicate stack 12 8 7 0 PCL as PC Destination overflow or stack underflow conditions. 2: There are no instructions/mnemonics PCLATH<4:0> 8 5 ALU Result called PUSH or POP. These are actions that occur from the execution of the PCLATH CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an PCH PCL interrupt address. 12 11 10 8 7 0 PC GOTO, CALL 2.4 Indirect Addressing, INDF and PCLATH<4:3> 11 FSR Registers 2 OPCODE<10:0> The INDF register is not a physical register. Addressing PCLATH the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF 2.3.1 MODIFYING PCL register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register Executing any instruction with the PCL register as the (FSR). Reading INDF itself indirectly will produce 00h. destination simultaneously causes the Program Writing to the INDF register indirectly results in a no Counter PC<12:8> bits (PCH) to be replaced by the operation (although Status bits may be affected). An contents of the PCLATH register. This allows the entire effective 9-bit address is obtained by concatenating the contents of the program counter to be changed by 8-bit FSR and the IRP bit of the STATUS register, as writing the desired upper five bits to the PCLATH shown in Figure2-10. register. When the lower eight bits are written to the PCL register, all 13 bits of the program counter will A simple program to clear RAM location 20h-2Fh using change to the values contained in the PCLATH register indirect addressing is shown in Example2-1. and those being written to the PCL register. A computed GOTO is accomplished by adding an offset EXAMPLE 2-1: INDIRECT ADDRESSING to the program counter (ADDWF PCL). Care should be MOVLW 0x20 ;initialize pointer exercised when jumping into a look-up table or MOVWF FSR ;to RAM program branch table (computed GOTO) by modifying NEXT CLRF INDF ;clear INDF register the PCL register. Assuming that PCLATH is set to the INCF FSR ;inc pointer table start address, if the table length is greater than BTFSS FSR,4 ;all done? 255 instructions or if the lower eight bits of the memory GOTO NEXT ;no clear next CONTINUE ;yes continue address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table. For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556).  2005-2015 Microchip Technology Inc. DS40001262F-page 43

PIC16F631/677/685/687/689/690 FIGURE 2-10: DIRECT/INDIRECT ADDRESSING PIC16F631/677/685/687/689/690 Direct Addressing Indirect Addressing RP1 RP0 6 From Opcode 0 IRP 7 File Select Register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 180h Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail, see Figures2-6,2-7 and2-8. DS40001262F-page 44  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 3.0 OSCILLATOR MODULE (WITH The Oscillator module can be configured in one of eight FAIL-SAFE CLOCK MONITOR) clock modes. 1. EC – External clock with I/O on OSC2/CLKOUT. 3.1 Overview 2. LP – 32kHz Low-Power Crystal mode. 3. XT – Medium Gain Crystal or Ceramic Resonator The Oscillator module has a wide variety of clock Oscillator mode. sources and selection features that allow it to be used 4. HS – High Gain Crystal or Ceramic Resonator in a wide range of applications while maximizing perfor- mode. mance and minimizing power consumption. Figure3-1 illustrates a block diagram of the Oscillator module. 5. RC – External Resistor-Capacitor (RC) with FOSC/4 output on OSC2/CLKOUT. Clock sources can be configured from external 6. RCIO – External Resistor-Capacitor (RC) with oscillators, quartz crystal resonators, ceramic resonators I/O on OSC2/CLKOUT. and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two 7. INTOSC – Internal oscillator with FOSC/4 output on OSC2 and I/O on OSC1/CLKIN. internal oscillators, with a choice of speeds selectable via software. Additional clock features include: 8. INTOSCIO – Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT. • Selectable system clock source between external or internal via software. Clock Source modes are configured by the FOSC<2:0> • Two-Speed Start-up mode, which minimizes bits in the Configuration Word register (CONFIG). The latency between external oscillator start-up and internal clock can be generated from two internal code execution. oscillators. The HFINTOSC is a calibrated high- frequency oscillator. The LFINTOSC is an uncalibrated • Fail-Safe Clock Monitor (FSCM) designed to low-frequency oscillator. detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. FIGURE 3-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FOSC<2:0> (Configuration Word Register) External Oscillator SCS<0> (OSCCON Register) OSC2 Sleep LP, XT, HS, RC, RCIO, EC OSC1 IRCF<2:0> UX (OSCCON Register) M System Clock (CPU and Peripherals) 8 MHz 111 INTOSC Internal Oscillator 4 MHz 110 2 MHz 101 er 1 MHz HFINTOSC cal 100 UX 8 MHz sts 500 kHz 011 M o P 250 kHz 010 125 kHz 001 LFINTOSC 31 kHz 000 31 kHz Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)  2005-2015 Microchip Technology Inc. DS40001262F-page 45

PIC16F631/677/685/687/689/690 3.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • Frequency Status bits (HTS, LTS) • System clock control bits (OSTS, SCS) REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0 — IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 111 =8MHz 110 =4MHz (default) 101 =2MHz 100 =1MHz 011 =500kHz 010 =250kHz 001 =125kHz 000 =31kHz (LFINTOSC) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG register 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC) bit 2 HTS: HFINTOSC Status bit (High Frequency – 8MHz to 125kHz) 1 = HFINTOSC is stable 0 = HFINTOSC is not stable bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31kHz) 1 = LFINTOSC is stable 0 = LFINTOSC is not stable bit 0 SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> of the CONFIG register Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled. DS40001262F-page 46  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 3.3 Clock Source Modes 3.4 External Clock Modes Clock Source modes can be classified as external or 3.4.1 OSCILLATOR START-UP TIMER (OST) internal. If the Oscillator module is configured for LP, XT or HS • External Clock modes rely on external circuitry for modes, the Oscillator Start-up Timer (OST) counts the clock source. Examples are: Oscillator mod- 1024 oscillations from OSC1. This occurs following a ules (EC mode), quartz crystal resonators or Power-on Reset (POR) and when the Power-up Timer ceramic resonators (LP, XT and HS modes) and (PWRT) has expired (if configured), or a wake-up from Resistor-Capacitor (RC) mode circuits. Sleep. During this time, the program counter does not • Internal clock sources are contained internally increment and program execution is suspended. The within the Oscillator module. The Oscillator OST ensures that the oscillator circuit, using a quartz module has two internal oscillators: the 8MHz crystal resonator or ceramic resonator, has started and High-Frequency Internal Oscillator (HFINTOSC) is providing a stable system clock to the Oscillator and the 31kHz Low-Frequency Internal Oscillator module. When switching between clock sources, a (LFINTOSC). delay is required to allow the new clock to stabilize. The system clock can be selected between external or These oscillator delays are shown in Table3-1. internal clock sources via the System Clock Select In order to minimize latency between external oscillator (SCS) bit of the OSCCON register. See Section3.6 start-up and code execution, the Two-Speed Clock “Clock Switching” for additional information. Start-up mode can be selected (see Section3.7 “Two- Speed Clock Start-up Mode”). TABLE 3-1: OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Oscillator Delay LFINTOSC 31kHz Sleep/POR Oscillator Warm-up Delay (TWARM) HFINTOSC 125kHz to 8MHz Sleep/POR EC, RC DC – 20MHz 2 cycles LFINTOSC (31kHz) EC, RC DC – 20MHz 1 cycle of each Sleep/POR LP, XT, HS 32kHz to 20MHz 1024 Clock Cycles (OST) LFINTOSC (31kHz) HFINTOSC 125kHz to 8MHz 1s (approx.) 3.4.2 EC MODE FIGURE 3-2: EXTERNAL CLOCK (EC) MODE OPERATION The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is Clock from OSC1/CLKIN connected to the OSC1 input and the OSC2 is available Ext. System for general purpose I/O. Figure3-2 shows the pin PIC® MCU connections for EC mode. I/O OSC2/CLKOUT(1) The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up Note 1: Alternate pin functions are listed in the from Sleep. Because the PIC® MCU design is fully Section1.0 “Device Overview”. static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.  2005-2015 Microchip Technology Inc. DS40001262F-page 47

PIC16F631/677/685/687/689/690 3.4.3 LP, XT, HS MODES FIGURE 3-3: QUARTZ CRYSTAL OPERATION (LP, XT OR The LP, XT and HS modes support the use of quartz HS MODE) crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure3-3). The mode selects a low, medium or high gain setting of the internal inverter- PIC® MCU amplifier to support various resonator types and speed. OSC1/CLKIN LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption C1 To Internal is the least of the three modes. This mode is designed to Logic dcrryivseta olsn)l.y 32.768 kHz tuning-fork type crystals (watch QCruyasrttazl RF(2) Sleep XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode C2 RS(1) OSC2/CLKOUT current consumption is the medium of the three modes. This mode is best suited to drive resonators with a Note 1: A series resistor (RS) may be required for medium drive level specification. quartz crystals with low drive level. HS Oscillator mode selects the highest gain setting of the 2: The value of RF varies with the Oscillator mode internal inverter-amplifier. HS mode current consumption selected (typically between 2M to 10M. is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure3-3 and Figure3-4 show typical circuits for FIGURE 3-4: CERAMIC RESONATOR quartz crystal and ceramic resonators, respectively. OPERATION . (XT OR HS MODE) Note1: Quartz crystal characteristics vary accord- ing to type, package and manufacturer. The PIC® MCU user should consult the manufacturer data sheets for specifications and recommended OSC1/CLKIN application. 2: Always verify oscillator performance over C1 To Internal Logic the VDD and temperature range that is expected for the application. RP(3) RF(2) Sleep 3: For oscillator design assistance, reference the following Microchip Applications Notes: • AN826, “Crystal Oscillator Basics and C2 Ceramic RS(1) OSC2/CLKOUT Crystal Selection for rfPIC® and PIC® Resonator Devices” (DS00826) Note 1: A series resistor (RS) may be required for • AN849, “Basic PIC® Oscillator Design” ceramic resonators with low drive level. (DS00849) 2: The value of RF varies with the Oscillator mode • AN943, “Practical PIC® Oscillator selected (typically between 2M to 10M. Analysis and Design” (DS00943) 3: An additional parallel feedback resistor (RP) • AN949, “Making Your Oscillator Work” may be required for proper ceramic resonator (DS00949) operation. DS40001262F-page 48  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 3.4.4 EXTERNAL RC MODES 3.5 Internal Clock Modes The external Resistor-Capacitor (RC) modes support The Oscillator module has two independent, internal the use of an external RC circuit. This allows the oscillators that can be configured or selected as the designer maximum flexibility in frequency choice while system clock source. keeping costs to a minimum when clock accuracy is not 1. The HFINTOSC (High-Frequency Internal required. There are two modes: RC and RCIO. Oscillator) is factory calibrated and operates at In RC mode, the RC circuit connects to OSC1. OSC2/ 8MHz. The frequency of the HFINTOSC can be CLKOUT outputs the RC oscillator frequency divided user-adjusted via software using the OSCTUNE by 4. This signal may be used to provide a clock for register (Register3-2). external circuitry, synchronization, calibration, test or 2. The LFINTOSC (Low-Frequency Internal other application requirements. Figure3-5 shows the Oscillator) is uncalibrated and operates at external RC mode connections. 31kHz. FIGURE 3-5: EXTERNAL RC MODES The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register. VDD PIC® MCU The system clock can be selected between external or REXT internal clock sources via the System Clock Selection (SCS) bit of the OSCCON register. See Section3.6 OSC1/CLKIN Internal Clock “Clock Switching” for more information. CEXT 3.5.1 INTOSC AND INTOSCIO MODES VSS The INTOSC and INTOSCIO modes configure the FOSC/4 or OSC2/CLKOUT(1) internal oscillators as the system clock source when I/O(2) the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word register (CONFIG). Recommended values: 10 k  REXT  100 k, <3V 3 k  REXT  100 k, 3-5V In INTOSC mode, OSC1/CLKIN is available for general CEXT > 20 pF, 2-5V purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT Note 1: Alternate pin functions are listed in the signal may be used to provide a clock for external Section1.0 “Device Overview”. circuitry, synchronization, calibration, test or other 2: Output depends upon RC or RCIO Clock application requirements. mode. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT In RCIO mode, the RC circuit is connected to OSC1. are available for general purpose I/O. OSC2 becomes an additional general purpose I/O pin. The RC oscillator frequency is a function of the supply 3.5.2 HFINTOSC voltage, the resistor (REXT) and capacitor (CEXT) values The High-Frequency Internal Oscillator (HFINTOSC) is and the operating temperature. Other factors affecting a factory calibrated 8MHz internal clock source. The the oscillator frequency are: frequency of the HFINTOSC can be altered via • threshold voltage variation software using the OSCTUNE register (Register3-2). • component tolerances The output of the HFINTOSC connects to a postscaler • packaging variations in capacitance and multiplexer (see Figure3-1). One of seven The user also needs to take into account variation due frequencies can be selected via software using the to tolerance of external RC components used. IRCF<2:0> bits of the OSCCON register. See Section3.5.4 “Frequency Select Bits (IRCF)” for more information. The HFINTOSC is enabled by selecting any frequency between 8MHz and 125kHz by setting the IRCF<2:0> bits of the OSCCON register000. Then, set the System Clock Source (SCS) bit of the OSCCON register to ‘1’ or enable Two-Speed Start-up by setting the IESO bit in the Configuration Word register (CONFIG) to ‘1’. The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not.  2005-2015 Microchip Technology Inc. DS40001262F-page 49

PIC16F631/677/685/687/689/690 3.5.2.1 OSCTUNE Register When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new The HFINTOSC is factory calibrated but can be frequency. Code execution continues during this shift. adjusted in software by writing to the OSCTUNE There is no indication that the shift has occurred. register (Register3-2). OSCTUNE does not affect the LFINTOSC frequency. The default value of the OSCTUNE register is ‘0’. The Operation of features that depend on the LFINTOSC value is a 5-bit two’s complement number. clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = • • • 00001 = 00000 = Oscillator module is running at the factory-calibrated frequency. 11111 = • • • 10000 = Minimum frequency DS40001262F-page 50  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 3.5.3 LFINTOSC 3.5.5 HFINTOSC AND LFINTOSC CLOCK SWITCH TIMING The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31kHz internal clock source. When switching between the LFINTOSC and the The output of the LFINTOSC connects to a postscaler HFINTOSC, the new oscillator may already be shut down to save power (see Figure3-6). If this is the case, and multiplexer (see Figure3-1). Select 31kHz, via software, using the IRCF<2:0> bits of the OSCCON there is a delay after the IRCF<2:0> bits of the OSCCON register are modified before the frequency register. See Section3.5.4 “Frequency Select Bits (IRCF)” for more information. The LFINTOSC is also the selection takes place. The LTS and HTS bits of the OSCCON register will reflect the current active status frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). of the LFINTOSC and HFINTOSC oscillators. The timing of a frequency selection is as follows: The LFINTOSC is enabled by selecting 31kHz 1. IRCF<2:0> bits of the OSCCON register are (IRCF<2:0> bits of the OSCCON register=000) as the system clock source (SCS bit of the OSCCON modified. register= 1), or when any of the following are enabled: 2. If the new clock is shut down, a clock start-up delay is started. • Two-Speed Start-up IESO bit of the Configuration 3. Clock switch circuitry waits for a falling edge of Word register = 1 and IRCF<2:0> bits of the the current clock. OSCCON register = 000 4. CLKOUT is held low and the clock switch • Power-up Timer (PWRT) circuitry waits for a rising edge in the new clock. • Watchdog Timer (WDT) 5. CLKOUT is now connected with the new clock. • Fail-Safe Clock Monitor (FSCM) LTS and HTS bits of the OSCCON register are The LF Internal Oscillator (LTS) bit of the OSCCON updated as required. register indicates whether the LFINTOSC is stable or 6. Clock switch is complete. not. See Figure3-1 for more details. 3.5.4 FREQUENCY SELECT BITS (IRCF) If the internal oscillator speed selected is between The output of the 8MHz HFINTOSC and 31kHz 8MHz and 125kHz, there is no start-up delay before LFINTOSC connects to a postscaler and multiplexer the new frequency is selected. This is because the old (see Figure3-1). The Internal Oscillator Frequency and new frequencies are derived from the HFINTOSC Select bits IRCF<2:0> of the OSCCON register select via the postscaler and multiplexer. the frequency output of the internal oscillators. One of Start-up delay specifications are located in the eight frequencies can be selected via software: oscillator tables of Section17.0 “Electrical • 8 MHz Specifications”. • 4 MHz (Default after Reset) • 2 MHz • 1 MHz • 500 kHz • 250 kHz • 125 kHz • 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 4MHz. The user can modify the IRCF bits to select a different frequency.  2005-2015 Microchip Technology Inc. DS40001262F-page 51

PIC16F631/677/685/687/689/690 FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <2:0> 0 0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC   IRCF <2:0> 0 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <2:0> = 0 ¼ 0 System Clock DS40001262F-page 52  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 3.6 Clock Switching When the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is The system clock source can be switched between enabled (see Section3.4.1 “Oscillator Start-up Timer external and internal clock sources via software using (OST)”). The OST will suspend program execution until the System Clock Select (SCS) bit of the OSCCON 1024 oscillations are counted. Two-Speed Start-up register. mode minimizes the delay in code execution by operating from the internal oscillator as the OST is 3.6.1 SYSTEM CLOCK SELECT (SCS) BIT counting. When the OST count reaches 1024 and the The System Clock Select (SCS) bit of the OSCCON OSTS bit of the OSCCON register is set, program register selects the system clock source that is used for execution switches to the external oscillator. the CPU and peripherals. 3.7.1 TWO-SPEED START-UP MODE • When the SCS bit of the OSCCON register = 0, CONFIGURATION the system clock source is determined by configuration of the FOSC<2:0> bits in the Two-Speed Start-up mode is configured by the Configuration Word register (CONFIG). following settings: • When the SCS bit of the OSCCON register = 1, • IESO (of the Configuration Word register) = 1; the system clock source is chosen by the internal Internal/External Switchover bit (Two-Speed Start- oscillator frequency selected by the IRCF<2:0> up mode enabled). bits of the OSCCON register. After a Reset, the • SCS (of the OSCCON register) = 0. SCS bit of the OSCCON register is always • FOSC<2:0> bits in the Configuration Word cleared. register (CONFIG) configured for LP, XT or HS Note: Any automatic clock switch, which may mode. occur from Two-Speed Start-up or Fail- Two-Speed Start-up mode is entered after: Safe Clock Monitor, does not update the SCS bit of the OSCCON register. The user • Power-on Reset (POR) and, if enabled, after can monitor the OSTS bit of the OSCCON Power-up Timer (PWRT) has expired, or register to determine the current system • Wake-up from Sleep. clock source. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two- 3.6.2 OSCILLATOR START-UP TIME-OUT speed Start-up is disabled. This is because the external STATUS (OSTS) BIT clock oscillator does not require any stabilization time The Oscillator Start-up Time-out Status (OSTS) bit of after POR or an exit from Sleep. the OSCCON register indicates whether the system clock is running from the external clock source, as 3.7.2 TWO-SPEED START-UP defined by the FOSC<2:0> bits in the Configuration SEQUENCE Word register (CONFIG), or from the internal clock 1. Wake-up from Power-on Reset or Sleep. source. In particular, OSTS indicates that the Oscillator 2. Instructions begin execution by the internal Start-up Timer (OST) has timed out for LP, XT or HS oscillator at the frequency set in the IRCF<2:0> modes. bits of the OSCCON register. 3. OST enabled to count 1024 clock cycles. 3.7 Two-Speed Clock Start-up Mode 4. OST timed out, wait for falling edge of the Two-Speed Start-up mode provides additional power internal oscillator. savings by minimizing the latency between external 5. OSTS is set. oscillator start-up and code execution. In applications 6. System clock held low until the next falling edge that make heavy use of the Sleep mode, Two-Speed of new clock (LP, XT or HS mode). Start-up will remove the external oscillator start-up 7. System clock is switched to external clock time from the time spent awake and can reduce the source. overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear.  2005-2015 Microchip Technology Inc. DS40001262F-page 53

PIC16F631/677/685/687/689/690 3.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP HFINTOSC TTOST OSC1 0 1 1022 1023 OSC2 Program Counter P C - N PC PC + 1 System Clock DS40001262F-page 54  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 3.8 Fail-Safe Clock Monitor 3.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset, to continue operating should the external oscillator fail. executing a SLEEP instruction or toggling the SCS bit The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bit is toggled, the Oscillator Start-up Timer (OST) has expired. The the OST is restarted. While the OST is running, the FSCM is enabled by setting the FCMEN bit in the device continues to operate from the INTOSC selected Configuration Word register (CONFIG). The FSCM is in OSCCON. When the OST times out, the Fail-Safe applicable to all external Oscillator modes (LP, XT, HS, condition is cleared and the device will be operating EC, RC and RCIO). from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. FIGURE 3-8: FSCM BLOCK DIAGRAM 3.8.4 RESET OR WAKE-UP FROM SLEEP Clock Monitor The FSCM is designed to detect an oscillator failure Latch after the Oscillator Start-up Timer (OST) has expired. External S Q The OST is used after waking up from Sleep and after Clock any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as LFINTOSC soon as the Reset or wake-up has completed. When Oscillator ÷ 64 R Q the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing 31 kHz 488 Hz code while the OST is operating. (~32 s) (~2 ms) Note: Due to the wide range of oscillator start-up Sample Clock Clock times, the Fail-Safe circuit is not active Failure during oscillator start-up (i.e., after exiting Detected Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify 3.8.1 FAIL-SAFE DETECTION the oscillator start-up and that the system The FSCM module detects a failed oscillator by clock switchover has successfully comparing the external oscillator to the FSCM sample completed. clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure3-8. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half- cycle of the sample clock elapses before the primary clock goes low. 3.8.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2005-2015 Microchip Technology Inc. DS40001262F-page 55

PIC16F631/677/685/687/689/690 FIGURE 3-9: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets(1) CONFIG(2) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000 OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register14-1) for operation of all register bits. DS40001262F-page 56  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 4.0 I/O PORTS operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written There are as many as eighteen general purpose I/O to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1. pins available. Depending on which peripherals are The TRISA register controls the PORTA pin output enabled, some or all of the pins may not be available as drivers, even when they are being used as analog inputs. general purpose I/O. In general, when a peripheral is The user should ensure the bits in the TRISA register are enabled, the associated pin may not be used as a maintained set when using them as analog inputs. I/O general purpose I/O pin. pins configured as analog input always read ‘0’. 4.1 PORTA and the TRISA Registers Note: The ANSEL register must be initialized to configure an analog channel as a digital PORTA is a 6-bit wide, bidirectional port. The input. Pins configured as analog inputs corresponding data direction register is TRISA will read ‘0’. (Register4-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the EXAMPLE 4-1: INITIALIZING PORTA output driver). Clearing a TRISA bit (= 0) will make the BCF STATUS,RP0;Bank 0 corresponding PORTA pin an output (i.e., enables output BCF STATUS,RP1; driver and puts the contents of the output latch on the CLRF PORTA ;Init PORTA selected pin). The exception is RA3, which is input only BSF STATUS,RP1;Bank 2 and its TRIS bit will always read as ‘1’. Example4-1 CLRF ANSEL ;digital I/O shows how to initialize PORTA. BSF STATUS,RP0;Bank 1 BCF STATUS,RP1; Reading the PORTA register (Register4-1) reads the MOVLW 0Ch ;Set RA<3:2> as inputs status of the pins, whereas writing to it will write to the MOVWF TRISA ;and set RA<5:4,1:0> PORT latch. All write operations are read-modify-write ;as outputs BCF STATUS,RP0;Bank 0 REGISTER 4-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x R/W-x R-x R/W-x R/W-x R/W-x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 4-2: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISA<5:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: TRISA<3> always reads ‘1’. 2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.  2005-2015 Microchip Technology Inc. DS40001262F-page 57

PIC16F631/677/685/687/689/690 4.2 Additional Pin Functions 4.2.3 INTERRUPT-ON-CHANGE Every PORTA pin on this device family has an interrupt- Each PORTA pin is individually configurable as an on-change option and a weak pull-up option. RA0 also interrupt-on-change pin. Control bits IOCAx enable or has an Ultra Low-Power Wake-up option. The next disable the interrupt function for each pin. Refer to three sections describe these functions. Register4-6. The interrupt-on-change is disabled on a Power-on Reset. 4.2.1 ANSEL AND ANSELH REGISTERS For enabled interrupt-on-change pins, the values are The ANSEL and ANSELH registers are used to disable compared with the old value latched on the last read of the input buffers of I/O pins, which allow analog voltages PORTA. The ‘mismatch’ outputs of the last read are to be applied to those pins without causing excessive OR’d together to set the PORTA Change Interrupt Flag current. Setting the ANSx bit of a corresponding pin will bit (RABIF) in the INTCON register (Register2-6). cause all digital reads of that pin to return ‘0’ and also This interrupt can wake the device from Sleep. The permit analog functions of that pin to operate correctly. user, in the Interrupt Service Routine, clears the The state of the ANSx bit has no effect on the digital interrupt by: output function of its corresponding pin. A pin with the a) Any read or write of PORTA. This will end the TRISx bit clear and ANSx bit set will operate as a digital mismatch condition, then, output, together with the analog input function of that b) Clear the flag bit RABIF. pin. Pins with the ANSx bit set always read ‘0’, which can cause unexpected behavior when executing read A mismatch condition will continue to set flag bit RABIF. or write operations on the port due to the read-modify- Reading PORTA will end the mismatch condition and write sequence of all such operations. allow flag bit RABIF to be cleared. The latch holding the last read value is not affected by a MCLR nor BOR 4.2.2 WEAK PULL-UPS Reset. After these Resets, the RABIF flag will continue to be set if a mismatch is present. Each of the PORTA pins, except RA3, has an individually configurable internal weak pull-up. Control Note: If a change on the I/O pin should occur bits WPUAx enable or disable each pull-up. Refer to when the read operation is being exe- Register4-4. Each weak pull-up is automatically turned cuted (start of the Q2 cycle), then the off when the port pin is configured as an output. The RABIF interrupt flag may not getset. pull-ups are disabled on a Power-on Reset by the RABPU bit of the OPTION register. A weak pull-up is automatically enabled for RA3 when configured as MCLR and disabled when RA3 is an I/O. There is no software control of the MCLR pull-up. DS40001262F-page 58  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 4-4: ANSELH: ANALOG SELECT HIGH REGISTER(2) U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — ANS11 ANS10 ANS9 ANS8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ANS<11:8>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.  2005-2015 Microchip Technology Inc. DS40001262F-page 59

PIC16F631/677/685/687/689/690 REGISTER 4-5: WPUA: PORTA REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPUA<5:4>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPUA<2:0>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global RABPU bit of the OPTION register must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0). 3: The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word. 4: WPUA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. REGISTER 4-6: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCA<5:0>: Interrupt-on-change PORTA Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. DS40001262F-page 60  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 4.2.4 ULTRA LOW-POWER WAKE-UP A series resistor between RA0 and the external capacitor provides overcurrent protection for the RA0/ The Ultra Low-Power Wake-up (ULPWU) on RA0 allows AN0/C1IN+/ICSPDAT/ULPWU pin and can allow for a slow falling voltage to generate an interrupt-on-change software calibration of the time-out (see Figure4-1). A on RA0 without excess current consumption. The mode timer can be used to measure the charge time and is selected by setting the ULPWUE bit of the PCON discharge time of the capacitor. The charge time can register. This enables a small current sink, which can be then be adjusted to provide the desired interrupt delay. used to discharge a capacitor on RA0. This technique will compensate for the affects of Follow these steps to use this feature: temperature, voltage and component accuracy. The a) Charge the capacitor on RA0 by configuring the Ultra Low-Power Wake-up peripheral can also be RA0 pin to output (= 1). configured as a simple Programmable Low-Voltage Detect or temperature sensor. b) Configure RA0 as an input. c) Enable interrupt-on-change for RA0. Note: For more information, refer to Application d) Set the ULPWUE bit of the PCON register to Note AN879, “Using the Microchip Ultra begin the capacitor discharge. Low-Power Wake-up Module” (DS00879). e) Execute a SLEEP instruction. EXAMPLE 4-2: ULTRA LOW-POWER When the voltage on RA0 drops below VIL, an interrupt WAKE-UP INITIALIZATION will be generated which will cause the device to wake- up and execute the next instruction. If the GIE bit of the BCF STATUS,RP0 ;Bank 0 INTCON register is set, the device will then call the BCF STATUS,RP1 ; interrupt vector (0004h). See Section4.4.2 “Interrupt- BSF PORTA,0 ;Set RA0 data latch on-change” and Section14.3.3 “PORTA/PORTB BSF STATUS,RP1 ;Bank 2 Interrupt” for more information. BCF ANSEL,0 ;RA0 to digital I/O BSF STATUS,RP0 ;Bank 1 This feature provides a low-power technique for BCF STATUS,RP1 ; periodically waking up the device from Sleep. The BCF TRISA,0 ;Output high to time-out is dependent on the discharge time of the RC CALL CapDelay ;charge capacitor circuit on RA0. See Example4-2 for initializing the BSF PCON,ULPWUE ;Enable ULP Wake-up Ultra Low-Power Wake-up module. BSF IOCA,0 ;Select RA0 IOC BSF TRISA,0 ;RA0 to input MOVLW B’10001000’ ;Enable interrupt MOVWF INTCON ;and clear flag BCF STATUS,RP0 ;Bank 0 SLEEP ;Wait for IOC NOP ;  2005-2015 Microchip Technology Inc. DS40001262F-page 61

PIC16F631/677/685/687/689/690 4.2.5 PIN DESCRIPTIONS AND 4.2.5.1 RA0/AN0/C1IN+/ICSPDAT/ULPWU DIAGRAMS Figure4-2 shows the diagram for this pin. The RA0/ Each PORTA pin is multiplexed with other functions. The AN0/C1IN+/ICSPDAT/ULPWU pin is configurable to pins and their combined functions are briefly described function as one of the following: here. For specific information about individual functions • a general purpose I/O such as the comparator or the A/D Converter (ADC), • an analog input for the ADC (except PIC16F631) refer to the appropriate section in this data sheet. • an analog input to Comparator C1 • In-Circuit Serial Programming™ data • an analog input for the Ultra Low-Power Wake-up FIGURE 4-1: BLOCK DIAGRAM OF RA0 Analog(1) Input Mode VDD Data Bus D Q Weak WR CK Q WPUA RABPU RD WPUA VDD D Q WR CK I/O Pin Q PORTA VSS - + VT D Q TRWISRA CK Q IULP 0 1 RD TRISA Analog(1) VSS Input Mode ULPWUE RD PORTA D Q Q D WR CK Q IOCA EN Q3 RD IOCA Q D EN Interrupt-on-Change RD PORTA To Comparator To A/D Converter(2) Note 1: ANSEL determines Analog Input mode. 2: Not implemented on PIC16F631. DS40001262F-page 62  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 4.2.5.2 RA1/AN1/C12IN0-/VREF/ICSPCLK 4.2.5.3 RA2/AN2/T0CKI/INT/C1OUT Figure4-2 shows the diagram for this pin. The RA1/ Figure4-3 shows the diagram for this pin. The RA2/AN2/ AN1/C12IN0-/VREF/ICSPCLK pin is configurable to T0CKI/INT/C1OUT pin is configurable to function as one function as one of the following: of the following: • a general purpose I/O • a general purpose I/O • an analog input for the ADC (except PIC16F631) • an analog input for the ADC (except PIC16F631) • an analog input to Comparator C1 or C2 • the clock input for Timer0 • a voltage reference input for the ADC • an external edge triggered interrupt • In-Circuit Serial Programming clock • a digital output from Comparator C1 FIGURE 4-2: BLOCK DIAGRAM OF RA1 FIGURE 4-3: BLOCK DIAGRAM OF RA2 Analog(1) Analog(1) Data Bus D Q Input Mode VDD Data Bus D Q Input Mode VDD WWPRUA CK Q Weak WWPURA CK Q Weak RD RABPU RD RABPU WPUA WPUA C1OUT Enable D Q VDD D Q VDD POWRRTA CK Q POWRRTA CK Q C1OUT 1 I/O Pin 0 I/O Pin D Q D Q TRWIRSA CK Q VSS TRWIRSA CK Q VSS Analog(1) Analog(1) RD Input Mode RD Input Mode TRISA TRISA RD RD PORTA PORTA D Q D Q IOWCRA CK Q Q D IOWCRA CK Q Q D EN Q3 EN Q3 RD RD IOCA Q D IOCA Q D EN EN Interrupt-on- Interrupt-on- Change Change RD PORTA RD PORTA To Comparator To A/D Converter(2) To Timer0 To INT Note 1: ANSEL determines Analog Input mode. To A/D Converter(2) 2: Not implemented on PIC16F631. Note 1: ANSEL determines Analog Input mode. 2: Not implemented on PIC16F631.  2005-2015 Microchip Technology Inc. DS40001262F-page 63

PIC16F631/677/685/687/689/690 4.2.5.4 RA3/MCLR/VPP 4.2.5.5 RA4/AN3/T1G/OSC2/CLKOUT Figure4-4 shows the diagram for this pin. The RA3/ Figure4-5 shows the diagram for this pin. The RA4/ MCLR/VPP pin is configurable to function as one of the AN3/T1G/OSC2/CLKOUT pin is configurable to following: function as one of the following: • a general purpose input • a general purpose I/O • as Master Clear Reset with weak pull-up • an analog input for the ADC (except PIC16F631) • a Timer1 gate input FIGURE 4-4: BLOCK DIAGRAM OF RA3 • a crystal/resonator connection • a clock output VDD MCLRE Weak FIGURE 4-5: BLOCK DIAGRAM OF RA4 Data Bus MCLRE Analog(3) Reset I nPpinut Input Mode CLK(1) TRRDISA VSS Data Bus D Q Modes VDD RD MCLRE VSS WR CK Q Weak PORTA WPUA D Q RD RABPU WR CK Q Q D WPUA Oscillator IOCA Circuit EN Q3 OSC1 RD CLKOUT VDD IOCA Q D Enable FOSC/4 1 EN D Q Interrupt-on- Change WR CK 0 I/O Pin Q PORTA CLKOUT RD PORTA Enable VSS D Q INTOSC/ WR CK RC/EC(2) TRISA Q CLKOUT RD Enable TRISA Analog Input Mode RD PORTA D Q Q D WR CK Q IOCA EN Q3 RD IOCA Q D EN Interrupt-on- Change RD PORTA To T1G To A/D Converter(4) Note1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. 2: With CLKOUT option. 3: ANSEL determines Analog Input mode. 4: Not implemented on PIC16F631. DS40001262F-page 64  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 4.2.5.6 RA5/T1CKI/OSC1/CLKIN Figure4-6 shows the diagram for this pin. The RA5/ T1CKI/OSC1/CLKIN pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 clock input • a crystal/resonator connection • a clock input FIGURE 4-6: BLOCK DIAGRAM OF RA5 INTOSC Mode TMR1LPEN(1) Data Bus D Q VDD WR CK Q Weak WPUA RABPU RD WPUA Oscillator Circuit OSC2 VDD D Q WR CK Q PORTA I/O Pin D Q WR CK TRISA Q VSS INTOSC RD Mode TRISA (2) RD PORTA D Q Q D WR CK Q IOCA EN Q3 RD IOCA Q D EN Interrupt-on- Change RD PORTA To TMR1 or CLKGEN Note 1:Timer1 LP Oscillator enabled. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed.  2005-2015 Microchip Technology Inc. DS40001262F-page 65

PIC16F631/677/685/687/689/690 TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets ADCON0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 WPUA — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 --11 -111 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. DS40001262F-page 66  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 4.3 PORTB and TRISB Registers 4.4.1 WEAK PULL-UPS PORTB is a 4-bit wide, bidirectional port. The Each of the PORTB pins has an individually configurable corresponding data direction register is TRISB (Register internal weak pull-up. Control bits WPUB<7:4> enable or 4-6). Setting a TRISB bit (= 1) will make the disable each pull-up (see Register4-9). Each weak corresponding PORTB pin an input (i.e., put the pullup is automatically turned off when the port pin is corresponding output driver in a High-Impedance mode). configured as an output. All pull-ups are disabled on a Clearing a TRISB bit (= 0) will make the corresponding Power-on Reset by the RABPU bit of the OPTION register. PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). 4.4.2 INTERRUPT-ON-CHANGE Example 4-3 shows how to initialize PORTB. Reading the PORTB register (Register 4-5) reads the status of the Four of the PORTB pins are individually configurable as pins, whereas writing to it will write to the PORT latch. All an interrupt-on-change pin. Control bits IOCB<7:4> write operations are read-modify-write operations. enable or disable the interrupt function for each pin. Therefore, a write to a port implies that the port pins are Refer to Register4-10. The interrupt-on-change feature read, this value is modified and then written to the PORT is disabled on a Power-on Reset. data latch. For enabled interrupt-on-change pins, the present The TRISB register controls the PORTB pin output value is compared with the old value latched on the last drivers, even when they are being used as analog inputs. read of PORTB to determine which bits have changed The user should ensure the bits in the TRISB register are or mismatch the old value. The ‘mismatch’ outputs are maintained set when using them as analog inputs. I/O OR’d together to set the PORTB Change Interrupt flag pins configured as analog input always read ‘0’. bit (RABIF) in the INTCON register (Register2-3). This interrupt can wake the device from Sleep. The user, EXAMPLE 4-3: INITIALIZING PORTB in the Interrupt Service Routine, clears the interrupt by: BCF STATUS,RP0 ;Bank 0 a) Any read or write of PORTB. This will end the BCF STATUS,RP1 ; mismatch condition. CLRF PORTB ;Init PORTB b) Clear the flag bit RABIF. BSF STATUS,RP0 ;Bank 1 A mismatch condition will continue to set flag bit RABIF. MOVLW FFh ;Set RB<7:4> as inputs MOVWF TRISB ; Reading or writing PORTB will end the mismatch BCF STATUS,RP0 ;Bank 0 condition and allow flag bit RABIF to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After these Resets, the RABIF flag will continue to be set if a mismatch is present. Note: The ANSELH register must be initialized to configure an analog channel as a digital Note: If a change on the I/O pin should occur input. Pins configured as analog inputs when the read operation is being executed will read ‘0’. (start of the Q2 cycle), then the RABIF interrupt flag may not getset. Furthermore, since a read or write on a port affects all bits 4.4 Additional PORTB Pin Functions of that port, care must be taken when using PORTB pins RB<7:4> on the device family device have multiple pins in Interrupt-on-Change mode. an interrupt-on-change option and a weak pull-up Changes on one pin may not be seen while option. The following three sections describe these servicing changes on another pin. PORTB pin functions. REGISTER 4-7: PORTB: PORTB REGISTER R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 RB7 RB6 RB5 RB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 RB<7:4>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL bit 3-0 Unimplemented: Read as ‘0’  2005-2015 Microchip Technology Inc. DS40001262F-page 67

PIC16F631/677/685/687/689/690 REGISTER 4-8: TRISB: PORTB TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 TRISB7 TRISB6 TRISB5 TRISB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 TRISB<7:4>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output bit 3-0 Unimplemented: Read as ‘0’ REGISTER 4-9: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 WPUB7 WPUB6 WPUB5 WPUB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 WPUB<7:4>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: Global RABPU bit of the OPTION register must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISB<7:4> = 0). REGISTER 4-10: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IOCB7 IOCB6 IOCB5 IOCB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTB Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled bit 3-0 Unimplemented: Read as ‘0’ DS40001262F-page 68  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 4.4.3 PIN DESCRIPTIONS AND 4.4.3.1 RB4/AN10/SDI/SDA DIAGRAMS Figure4-7 shows the diagram for this pin. The RB4/ Each PORTB pin is multiplexed with other functions. The AN10/SDI/SDA(1) pin is configurable to function as one pins and their combined functions are briefly described of the following: here. For specific information about individual functions • a general purpose I/O such as the SSP, I2C™ or interrupts, refer to the • an analog input for the ADC (except PIC16F631) appropriate section in this data sheet. • a SPI data I/O • an I2C data I/O Note1: SDI and SDA are available on PIC16F677/PIC16F687/PIC16F689/ PIC16F690 only. FIGURE 4-7: BLOCK DIAGRAM OF RB4 Analog(1) Data Bus Input Mode D Q VDD WR CK WPUB Q Weak RD RABPU WPUB SSPEN VDD D Q SSPSR WR CK 01 Q PORTB 10 I/O Pin D Q From 01 WR CK SSP TRISB Q VSS 10 RD Analog(1) TRISB Input Mode RD PORTB D Q Q D WR CK Q IOCB EN Q3 RD IOCB Q D ST EN Interrupt-on- Change RD PORTB To SSPSR To A/D Converter(2) Available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. Note 1: ANSEL determines Analog Input mode. 2: Not implemented on PIC16F631.  2005-2015 Microchip Technology Inc. DS40001262F-page 69

PIC16F631/677/685/687/689/690 4.4.3.2 RB5/AN11/RX/DT(1, 2) FIGURE 4-8: BLOCK DIAGRAM OF RB5 Figure4-8 shows the diagram for this pin. The RB5/ Analog(1) AN11/RX/DT pin is configurable to function as one of Data Bus Input Mode the following: D Q VDD • a general purpose I/O WWPURB CK Q Weak • an analog input for the ADC (except PIC16F631) • an asynchronous serial input RD RABPU WPUB • a synchronous serial data I/O SYNC SPEN Note1: RX and DT are available on PIC16F687/ PIC16F689/PIC16F690 only. VDD D Q EUSART 2: AN11 is not implemented on PIC16F631. DT WR CK 01 Q PORTB 10 I/O Pin From D Q EUSART 01 WR CK TRISB Q 10 VSS RD Analog(1) TRISB Input Mode RD PORTB D Q Q D WR CK Q IOCB EN Q3 RD IOCB Q D ST EN Interrupt-on- Change RD PORTB To EUSART RX/DT To A/D Converter(2) Available on PIC16F687/PIC16F689/PIC16F690 only. Note 1: ANSEL determines Analog Input mode. 2: Not implemented on PIC16F631. DS40001262F-page 70  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 4.4.3.3 RB6/SCK/SCL FIGURE 4-9: BLOCK DIAGRAM OF RB6 Figure4-9 shows the diagram for this pin. The RB6/ SCK/SCL(1) pin is configurable to function as one of the Data Bus D Q VDD following: WR CK Q Weak • a general purpose I/O WPUB • a SPI clock RD RABPU • an I2C™ clock WPUB Note1: SCK and SCL are available on PIC16F677/PIC16F687/PIC16F689/ SSPEN VDD D Q PIC16F690 only. SSP Clock WR CK 01 Q PORTB 10 I/O Pin From D Q SSP 01 WR CK TRISB Q VSS 10 RD TRISB RD PORTB D Q Q D WR CK Q IOCB EN Q3 RD IOCB Q D ST EN Interrupt-on- Change RD PORTB To SSP Available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.  2005-2015 Microchip Technology Inc. DS40001262F-page 71

PIC16F631/677/685/687/689/690 4.4.3.4 RB7/TX/CK FIGURE 4-10: BLOCK DIAGRAM OF RB7 Figure4-10 shows the diagram for this pin. The RB7/ TX/CK(1) pin is configurable to function as one of the Data Bus D Q VDD following: • a general purpose I/O WWPURB CK Q Weak • an asynchronous serial output RD RABPU • a synchronous clock I/O WPUB SPEN Note1: TX and CK are available on PIC16F687/ TXEN PIC16F689/PIC16F690 only. SYNC EUSART CK 01 EUSART TX D Q 10 VDD POWRRTB CK Q 01 10 D Q I/O Pin WR CK ‘1’ 01 TRISB Q VSS 10 RD TRISB RD PORTB D Q Q D WR CK Q IOCB EN Q3 RD IOCB Q D EN Interrupt-on- Change RD PORTB Available on PIC16F687/PIC16F689/PIC16F690 only. DS40001262F-page 72  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 0000 ---- INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ---- TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ---- Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by PORTB.  2005-2015 Microchip Technology Inc. DS40001262F-page 73

PIC16F631/677/685/687/689/690 4.5 PORTC and TRISC Registers The TRISC register controls the PORTC pin output drivers, even when they are being used as analog inputs. PORTC is a 8-bit wide, bidirectional port. The The user should ensure the bits in the TRISC register are corresponding data direction register is TRISC (Register maintained set when using them as analog inputs. I/O 4-10). Setting a TRISC bit (= 1) will make the pins configured as analog input always read ‘0’. corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Note: The ANSEL and ANSELH registers must Clearing a TRISC bit (= 0) will make the corresponding be initialized to configure an analog PORTC pin an output (i.e., enable the output driver and channel as a digital input. Pins configured put the contents of the output latch on the selected pin). as analog inputs will read ‘0’. Example 4-4 shows how to initialize PORTC. Reading the PORTC register (Register 4-9) reads the status of the EXAMPLE 4-4: INITIALIZING PORTC pins, whereas writing to it will write to the PORT latch. All BCF STATUS,RP0 ;Bank 0 write operations are read-modify-write operations. BCF STATUS,RP1 ; Therefore, a write to a port implies that the port pins are CLRF PORTC ;Init PORTC read, this value is modified and then written to the PORT BSF STATUS,RP1 ;Bank 2 data latch. CLRF ANSEL ;digital I/O BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 ; MOVLW 0Ch ;Set RC<3:2> as inputs MOVWF TRISC ;and set RC<5:4,1:0> ;as outputs BCF STATUS,RP0 ;Bank 0 REGISTER 4-11: PORTC: PORTC REGISTER R/W-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 4-12: TRISC: PORTC TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TRISC<7:0>: PORTC Tri-State Control bit 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output DS40001262F-page 74  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 4.5.1 RC0/AN4/C2IN+ 4.5.3 RC2/AN6/C12IN2-/P1D The RC0 is configurable to function as one of the The RC2/AN6/P1D(1) is configurable to function as following: one of the following: • a general purpose I/O • a general purpose I/O • an analog input for the ADC (except PIC16F631) • an analog input for the ADC (except PIC16F631) • an analog input to Comparator C2 • a PWM output • an analog input to Comparator C1 or C2 4.5.2 RC1/AN5/C12IN1- Note1: P1D is available on PIC16F685/ The RC1 is configurable to function as one of the PIC16F690 only. following: • a general purpose I/O 4.5.4 RC3/AN7/C12IN3-/P1C • an analog input for the ADC The RC3/AN7/P1C(1) is configurable to function as one • an analog input to Comparator C1 or C2 of the following: FIGURE 4-11: BLOCK DIAGRAM OF RC0 • a general purpose I/O AND RC1 • an analog input for the ADC (except PIC16F631) • a PWM output Data Bus • a PWM output • an analog input to Comparator C1 or C2 VDD D Q Note1: P1C is available on PIC16F685/ WR CK PORTC Q PIC16F690 only. I/O Pin FIGURE 4-12: BLOCK DIAGRAM OF RC2 D Q AND RC3 WR CK TRISC Q VSS Data Bus Analog Input CCP1OUT RD Mode(1) Enable TRISC D Q VDD PORRDTC POWRRTC CK Q CCP1OUT 01 To Comparators 10 I/O Pin To A/D Converter(2) D Q WR CK TRISC Q VSS Note 1: ANSEL determines Analog Input mode. Analog Input 2: Not implemented on PIC16F631. Mode(1) RD TRISC RD PORTC To Comparators To A/D Converter(2) Available on PIC16F685/PIC16F690 only. Note 1: ANSEL determines Analog Input mode. 2: Not implemented on PIC16F631.  2005-2015 Microchip Technology Inc. DS40001262F-page 75

PIC16F631/677/685/687/689/690 4.5.5 RC4/C2OUT/P1B 4.5.6 RC5/CCP1/P1A The RC4/C2OUT/P1B(1, 2) is configurable to function The RC5/CCP1/P1A(1) is configurable to function as as one of the following: one of the following: • a general purpose I/O • a general purpose I/O • a digital output from Comparator C2 • a digital input/output for the Enhanced CCP • a PWM output • a PWM output Note 1: Enabling both C2OUT and P1B will cause Note1: CCP1 and P1A are available on a conflict on RC4 and create PIC16F685/PIC16F690 only. unpredictable results. Therefore, if C2OUT is enabled, the ECCP+ can not be FIGURE 4-14: BLOCK DIAGRAM OF RC5 used in Half-Bridge or Full-Bridge mode and vise-versa. Data bus CCP1OUT 2: P1B is available on PIC16F685/ Enable PIC16F690 only. D Q VDD WR CK FIGURE 4-13: BLOCK DIAGRAM OF RC4 PORTC Q CCP1OUT 01 10 I/O Pin C2OUT EN D Q CCP1OUT EN WR CK C2OUT EN TRISC Q VSS C2OUT VDD RD CCP1OUT EN CCP1OUT 01 TRISC RD Data Bus 10 I/O Pin PORTC D Q To Enhanced CCP WR CK Q VSS PORTC Available on PIC16F685/PIC16F690 only. D Q WR CK TRISC Q RD TRISC RD PORTC Available on PIC16F685/PIC16F690 only. DS40001262F-page 76  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 4.5.7 RC6/AN8/SS 4.5.8 RC7/AN9/SDO The RC6/AN8/SS(1,2) is configurable to function as one The RC7/AN9/SDO(1,2) is configurable to function as of the following: one of the following: • a general purpose I/O • a general purpose I/O • an analog input for the ADC (except PIC16F631) • an analog input for the ADC (except PIC16F631) • a slave select input • a serial data output Note 1: SS is available on PIC16F687/PIC16F689/ Note1: SDO is available on PIC16F687/ PIC16F690 only. PIC16F689/PIC16F690 only. 2: AN8 is not implemented on PIC16F631. 2: AN9 is not implemented on PIC16F631. FIGURE 4-15: BLOCK DIAGRAM OF RC6 FIGURE 4-16: BLOCK DIAGRAM OF RC7 Data Bus PORT/SDO Select D Q VDD Data Bus SDO 01 WR CK PORTC Q D Q 10 VDD I/O Pin WR CK Q D Q PORTC WR CK I/O Pin TRISC Q VSS D Q Analog Input RD Mode(1) TRWIRSC CK Q VSS TRISC Analog Input Mode(1) RD RD PORTC TRISC To SS Input RD To A/D Converter(2) PORTC To A/D Converter(2) Available on PIC16F685/PIC16F690 only. Note 1: ANSEL determines Analog Input mode. 2: Not implemented on PIC16F631. Available on PIC16F685/PIC16F690 only. Note 1: ANSEL determines Analog Input mode. 2: Not implemented on PIC16F631.  2005-2015 Microchip Technology Inc. DS40001262F-page 77

PIC16F631/677/685/687/689/690 TABLE 4-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 ANSELH — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111 CCP1CON(2) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 CM2CON1 MC1OUT MC2OUT — — — — T1GSS C2SYNC 00-- --10 00-- --10 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001 SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — — 0000 00-- 0000 00-- SSPCON(1) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Note 1: PIC16F687/PIC16F689/PIC16F690 only. 2: PIC16F685/PIC16F690 only. DS40001262F-page 78  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 5.0 TIMER0 MODULE 5.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the When used as a timer, the Timer0 module can be used following features: as either an 8-bit timer or an 8-bit counter. • 8-bit timer/counter register (TMR0) 5.1.1 8-BIT TIMER MODE • 8-bit prescaler (shared with Watchdog Timer) When used as a timer, the Timer0 module will • Programmable internal or external clock source increment every instruction cycle (without prescaler). • Programmable external clock edge selection Timer mode is selected by clearing the T0CS bit of the • Interrupt on overflow OPTION register to ‘0’. Figure5-1 is a block diagram of the Timer0 module. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. 5.1.2 8-BIT COUNTER MODE When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER FOSC/4 Data Bus 0 8 1 Sync 2 1 TMR0 cycles T0CKI 0 pin 0 T0SE T0CS 8-bit Set Flag bit T0IF on Overflow Prescaler PSA 1 8 WDTE PSA SWDTEN PS<2:0> 1 WDT 16-bit Time-out Prescaler 0 16 31kHz Watchdog INTOSC Timer PSA WDTPS<3:0> Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word register.  2005-2015 Microchip Technology Inc. DS40001262F-page 79

PIC16F631/677/685/687/689/690 5.1.3 SOFTWARE PROGRAMMABLE When changing the prescaler assignment from the PRESCALER WDT to the Timer0 module, the following instruction sequence must be executed (see Example5-2). A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer EXAMPLE 5-2: CHANGING PRESCALER (WDT), but not both simultaneously. The prescaler (WDTTIMER0) assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit CLRWDT ;Clear WDT and must be cleared to a ‘0’. ;prescaler There are eight prescaler options for the Timer0 mod- BANKSEL OPTION_REG ; MOVLW b’11110000’;Mask TMR0 select and ule ranging from 1:2 to 1:256. The prescale values are ANDWF OPTION_REG,W;prescaler bits selectable via the PS<2:0> bits of the OPTION register. IORLW b’00000011’;Set prescale to 1:16 In order to have a 1:1 prescaler value for the Timer0 MOVWF OPTION_REG ; module, the prescaler must be assigned to the WDT module. 5.1.4 TIMER0 INTERRUPT The prescaler is not readable or writable. When the Timer0 will generate an interrupt when the TMR0 prescaler is assigned to the Timer0 module, all register overflows from FFh to 00h. The T0IF interrupt instructions writing to the TMR0 register will clear the flag bit of the INTCON register is set every time the prescaler. TMR0 register overflows, regardless of whether or not When the prescaler is assigned to WDT, a CLRWDT the Timer0 interrupt is enabled. The T0IF bit must be instruction will clear the prescaler along with the WDT. cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register. 5.1.3.1 Switching Prescaler Between Timer0 and WDT Modules Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is As a result of having the prescaler assigned to either frozen during Sleep. Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler 5.1.5 USING TIMER0 WITH AN values. When changing the prescaler assignment from EXTERNAL CLOCK Timer0 to the WDT module, the instruction sequence shown in Example5-1, must be executed. When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accom- EXAMPLE 5-1: CHANGING PRESCALER plished by sampling the prescaler output on the Q2 and (TIMER0WDT) Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must BANKSELTMR0 ; meet the timing requirements as shown in CLRWDT ;Clear WDT Section17.0 “Electrical Specifications”. CLRF TMR0 ;Clear TMR0 and ;prescaler BANKSELOPTION_REG ; BSF OPTION_REG,PSA;Select WDT CLRWDT ; ; MOVLW b’11111000’;Mask prescaler ANDWF OPTION_REG,W; bits IORLW b’00000101’;Set WDT prescaler MOVWF OPTION_REG ; to 1:32 DS40001262F-page 80  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RABPU: PORTA/PORTB Pull-up Enable bit 1 = Pull-ups on PORTA/PORTB are disabled 0 = Pull-ups on PORTA/PORTB are disabled by individual WPUAx control bits bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits BIT VALUE TMR0 RATE WDT RATE 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Note 1: A dedicated 16-bit WDT postscaler is available. See Section14.5 “Watchdog Timer (WDT)” for more information. TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 0000 0000 0000 OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.  2005-2015 Microchip Technology Inc. DS40001262F-page 81

PIC16F631/677/685/687/689/690 6.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 3-bit prescaler • Optional LP oscillator • Synchronous or asynchronous operation • Timer1 gate (count enable) via comparator or T1G pin • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function (PIC16F685/PIC16F690 only) • Special Event Trigger (with ECCP) (PIC16F685/PIC16F690 only) • Comparator output synchronization to Timer1 clock Figure6-1 is a block diagram of the Timer1 module. 6.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter. 6.2 Clock Source Selection The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source is supplied externally. Clock FOSC T1OSCEN TMR1CS Source Mode FOSC/4 x xxx 0 T1CKI pin 0 xxx 1 T1LPOSC 1 LP or 1 INTOSCIO DS40001262F-page 82  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 6-1: TIMER1 BLOCK DIAGRAM TMR1GE T1GINV TMR1ON Set flag bit TMR1IF on To C2 Comparator Module Overflow TMR1(2) Timer1 Clock Synchronized EN 0 clock input TMR1H TMR1L 1 Oscillator (1) T1SYNC OSC1/T1CKI 1 Prescaler Synchronize(3) FOSC/4 1, 2, 4, 8 det Internal 0 OSC2/T1G Clock 2 T1CKPS<1:0> TMR1CS 1 INTOSC Without CLKOUT SYNCC2OUT(4) 0 T1OSCEN T1GSS Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 4: SYNCC2OUT is synchronized when the C2SYNC bit of the CM2CON1 register is set.  2005-2015 Microchip Technology Inc. DS40001262F-page 83

PIC16F631/677/685/687/689/690 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the Note: The oscillator requires a start-up and TMR1H:TMR1L register pair will increment on multiples stabilization time before use. Thus, of FOSC as determined by the Timer1 prescaler. T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 6.5 Timer1 Operation in module may work as a timer or a counter. Asynchronous Counter Mode When counting, Timer1 is incremented on the rising If control bit T1SYNC of the T1CON register is set, the edge of the external clock input T1CKI. In addition, the external clock input is not synchronized. The timer Counter mode clock can be synchronized to the increments asynchronously to the internal phase microcontroller system clock or run asynchronously. clocks. If external clock source is selected then the If an external clock oscillator is needed (and the timer will continue to run during Sleep and can microcontroller is using the INTOSC without CLKOUT), generate an interrupt on overflow, which will wake-up Timer1 can use the LP oscillator as a clock source. the processor. However, special precautions in Note1: In Counter mode, a falling edge must be software are needed to read/write the timer (see Section6.5.1 “Reading and Writing Timer1 in registered by the counter prior to the first incrementing rising edge after any one or Asynchronous Counter Mode”). more of the following conditions: Note: When switching from synchronous to •Timer1 enabled after POR reset asynchronous operation, it is possible to skip an increment. When switching from •Write to TMR1H or TMR1L asynchronous to synchronous operation, •Timer1 is disabled it is possible to produce an additional •Timer1 is disabled (TMR1ON 0) when increment. T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI 6.5.1 READING AND WRITING TIMER1 IN is low. ASYNCHRONOUS COUNTER 2: See Figure6-2 MODE Reading TMR1H or TMR1L while the timer is running 6.3 Timer1 Prescaler from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user Timer1 has four prescaler options allowing 1, 2, 4 or 8 should keep in mind that reading the 16-bit timer in two divisions of the clock input. The T1CKPS bits of the 8-bit values itself, poses certain problems, since the T1CON register control the prescale counter. The timer may overflow between the reads. prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to For writes, it is recommended that the user simply stop TMR1H or TMR1L. the timer and write the desired values. A write contention may occur by writing to the timer registers, 6.4 Timer1 Oscillator while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. A low-power 32.768 kHz crystal oscillator is built-in between pins OSC1 (input) and OSC2 (amplifier 6.6 Timer1 Gate output). The oscillator is enabled by setting the T1OSCEN control bit of the T1CON register. The The Timer1 gate (when enabled) allows Timer1 to count oscillator will continue to run during Sleep. when Timer1 gate is active. Timer1 gate source is software configurable to be the T1G pin or the output of The Timer1 oscillator is shared with the system LP Comparator C2. This allows the device to directly time oscillator. Thus, Timer1 can use this mode only when external events using T1G or analog events using the primary system clock is derived from the internal Comparator C2. See the CM2CON1 register oscillator or when the oscillator is in the LP mode. The (Register8-3) for selecting the Timer1 gate source. This user must provide a software time delay to ensure feature can simplify the software for a Delta-Sigma A/D proper oscillator start-up. converter and many other applications. TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled. RA5 and RA4 bits read as ‘0’ and TRISA5 and TRISA4 bits read as ‘1’. DS40001262F-page 84  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in Note: TMR1GE bit of the T1CON register must the TMR1H:TMR1L register pair. This event can be a be set to use either T1G or C2OUT as the Special Event Trigger. Timer1 gate source. See the CM2CON1 register (Register8-3) for more informa- For more information, see Section11.0 “Enhanced tion on selecting the Timer1 gate source. Capture/Compare/PWM Module”. Timer1 gate can be inverted using the T1GINV bit of 6.10 ECCP Special Event Trigger the T1CON register, whether it originates from the T1G pin or Comparator C2 output. This configures Timer1 to When the ECCP is configured to trigger a special measure either the active-high or active-low time event, the trigger will clear the TMR1H:TMR1L register between events. pair. This special event does not cause a Timer1 inter- rupt. The ECCP module may still be configured to 6.7 Timer1 Interrupt generate a ECCP interrupt. In this mode of operation, the CCPR1H:CCPR1L The Timer1 register pair (TMR1H:TMR1L) increments register pair becomes the period register for Timer1. to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is Timer1 should be synchronized to the FOSC to utilize set. To enable the interrupt on rollover, you must set the Special Event Trigger. Asynchronous operation of these bits: Timer1 can cause a Special Event Trigger to be missed. • TMR1ON bit of the T1CON register • TMR1IE bit of the PIE1 register In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the ECCP, the write • PEIE bit of the INTCON register will take precedence. • GIE bit of the INTCON register For more information, see Section11.2.4 “Special The interrupt is cleared by clearing the TMR1IF bit in Event Trigger”. the Interrupt Service Routine. Note: The TMR1H:TTMR1L register pair and 6.11 Comparator Synchronization the TMR1IF bit should be cleared before enabling interrupts. The same clock used to increment Timer1 can also be used to synchronize the comparator output. This feature is enabled in the Comparator module. 6.8 Timer1 Operation During Sleep When using the comparator for Timer1 gate, the Timer1 can only operate during Sleep when setup in comparator output should be synchronized to Timer1. Asynchronous Counter mode. In this mode, an external This ensures Timer1 does not miss an increment if the crystal or clock source can be used to increment the comparator changes. counter. To set up the timer to wake the device: For more information, see Section8.8.2 • TMR1ON bit of the T1CON register must be set “Synchronizing Comparator C2 output to Timer1”. • TMR1IE bit of the PIE1 register must be set • PEIE bit of the INTCON register must be set • T1SYNC bit of the T1CON register must be set • TMR1CS bit of the T1CON register must be set • T1OSCEN bit of the T1CON register (can be set) The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). 6.9 ECCP Capture/Compare Time Base The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event.  2005-2015 Microchip Technology Inc. DS40001262F-page 85

PIC16F631/677/685/687/689/690 FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. DS40001262F-page 86  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 6.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register6-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 6-1: T1CON: TIMER 1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active-high (Timer1 counts when Timer1 gate signal is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 6 TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 Gate function 0 = Timer1 is always counting bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value bit 3 T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register, as a Timer1 gate source.  2005-2015 Microchip Technology Inc. DS40001262F-page 87

PIC16F631/677/685/687/689/690 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets CM2CON1 MC1OUT MC2OUT — — — — T1GSS C2SYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 0000 0000 0000 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. DS40001262F-page 88  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 7.0 TIMER2 MODULE The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to The Timer2 module is an 8-bit timer with the following 00h and the PR2 register is set to FFh. features: Timer2 is turned on by setting the TMR2ON bit in the • 8-bit timer register (TMR2) T2CON register to a ‘1’. Timer2 is turned off by clearing • 8-bit period register (PR2) the TMR2ON bit to a ‘0’. • Interrupt on TMR2 match with PR2 The Timer2 prescaler is controlled by the T2CKPS bits • Software programmable prescaler (1:1, 1:4, 1:16) in the T2CON register. The Timer2 postscaler is • Software programmable postscaler (1:1 to 1:16) controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared See Figure7-1 for a block diagram of Timer2. when: 7.1 Timer2 Operation • A write to TMR2 occurs. • A write to T2CON occurs. The clock input to the Timer2 module is the system • Any device Reset occurs (Power-on Reset, MCLR instruction clock (FOSC/4). The clock is fed into the Reset, Watchdog Timer Reset or Brown-out Timer2 prescaler, which has prescale options of 1:1, Reset). 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. Note: TMR2 is not cleared when T2CON is written. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: • TMR2 is reset to 00h on the next increment cycle. • The Timer2 postscaler is incremented The match output of the Timer2/PR2 comparator is fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. FIGURE 7-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 bit TMR2IF Output Prescaler Reset FOSC/4 TMR2 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T2CKPS<1:0> PR2 4 TOUTPS<3:0>  2005-2015 Microchip Technology Inc. DS40001262F-page 89

PIC16F631/677/685/687/689/690 REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 =Prescaler is 1 01 =Prescaler is 4 1x =Prescaler is 16 Note 1: PIC16F685/PIC16F690 only. TABLE 7-1: SUMMARY OF ASSOCIATED TIMER2(1) REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. Note 1: PIC16F685/PIC16F690 only. DS40001262F-page 90  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 8.0 COMPARATOR MODULE FIGURE 8-1: SINGLE COMPARATOR Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and VIN+ + providing a digital indication of their relative magnitudes. Output The comparators are very useful mixed signal building VIN- – blocks because they provide analog functionality independent of program execution. The Analog Comparator module includes the following features: • Independent comparator control VIN- • Programmable input selection VIN+ • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change • Wake-up from Sleep Output • PWM shutdown • Timer1 gate (count enable) Note: The black areas of the output of the • Output synchronization to Timer1 clock input comparator represents the uncertainty • SR Latch due to input offsets and response time. • Programmable and Fixed Voltage Reference Note: Only Comparator C2 can be linked to Timer1. 8.1 Comparator Overview A single comparator is shown in Figure8-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level.  2005-2015 Microchip Technology Inc. DS40001262F-page 91

PIC16F631/677/685/687/689/690 FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> 2 C1POL To D Q Data Bus Q1 C12IN0- 0 EN RD_CM1CON0 C12IN1- 1 MUX Set C1IF D Q C12IN2- 2 Q3*RD_CM1CON0 EN C12IN3- 3 CL NRESET C1ON(1) To other peripherals C1R C1VIN- - C1IN+ 0 C1 C1OUT C1OUT (to SR latch) C1VIN+ MUX + FixedRef 1 0 C1POL MUX CVREF 1 Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. C1VREN 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM C2POL To D Q Data Bus Q1 EN RD_CM2CON0 C2CH<1:0> Set C2IF 2 D Q Q3*RD_CM2CON0 C12IN0- 0 C2ON(1) ENCL NRESET C12IN1- 1 C2VIN- MUX C12IN2- 2 C2VIN+ C2 C2OUT C12IN3- 3 C2SYNC C2POL C2R 0 SYNCC2OUT MUX to Timer1 Gate, SR latch D Q 1 and other peripherals C2IN+ 0 MUX From TMR1 Clock FixedRef 1 0 MUX CVREF 1 Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate. C2VREN 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. DS40001262F-page 92  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 8.2 Comparator Control 8.2.4 COMPARATOR OUTPUT SELECTION Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 The output of the comparator can be monitored by and CM2CON0 for Comparator C2. In addition, reading either the CxOUT bit of the CMxCON0 register Comparator C2 has a second control register, or the MCxOUT bit of the CM2CON1 register. In order CM2CON1, for controlling the interaction with Timer1 and to make the output available for an external connection, simultaneous reading of both comparator outputs. the following conditions must be true: The CM1CON0 and CM2CON0 registers (see Registers • CxOE bit of the CMxCON0 register must be set 8-1 and 8-2, respectively) contain the control and Status • Corresponding TRIS bit must be cleared bits for the following: • CxON bit of the CMxCON0 register must be set • Enable Note1: The CxOE bit overrides the PORT data • Input selection latch. Setting the CxON has no impact on • Reference selection the port override. • Output selection 2: The internal output of the comparator is • Output polarity latched with each instruction cycle. Unless otherwise specified, external 8.2.1 COMPARATOR ENABLE outputs are not latched. Setting the CxON bit of the CMxCON0 register enables 8.2.5 COMPARATOR OUTPUT POLARITY the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current Inverting the output of the comparator is functionally consumption. equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by 8.2.2 COMPARATOR INPUT SELECTION setting the CxPOL bit of the CMxCON0 register. The CxCH<1:0> bits of the CMxCON0 register direct Clearing the CxPOL bit results in a non-inverted output. one of four analog input pins to the comparator Table8-1 shows the output state versus input inverting input. conditions, including polarity control. TABLE 8-1: COMPARATOR OUTPUT Note: To use CxIN+ and C12INx- pins as analog inputs, the appropriate bits must be set in STATE VS. INPUT CONDITIONS the ANSEL register and the Input Condition CxPOL CxOUT corresponding TRIS bits must also be set to disable the output drivers. CxVIN- > CxVIN+ 0 0 CxVIN- < CxVIN+ 0 1 8.2.3 COMPARATOR REFERENCE CxVIN- > CxVIN+ 1 1 SELECTION CxVIN- < CxVIN+ 1 0 Setting the CxR bit of the CMxCON0 register directs an internal voltage reference or an analog input pin to the 8.3 Comparator Response Time non-inverting input of the comparator. See Section8.9 “Comparator SR Latch” for more information on the The comparator output is indeterminate for a period of Internal Voltage Reference module. time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section17.0 “Electrical Specifications” for more details.  2005-2015 Microchip Technology Inc. DS40001262F-page 93

PIC16F631/677/685/687/689/690 8.4 Comparator Interrupt Operation FIGURE 8-4: COMPARATOR INTERRUPT TIMING W/O The comparator interrupt flag can be set whenever CMxCON0 READ there is a change in the output value of the comparator. Changes are recognized by means of a mismatch Q1 circuit which consists of two latches and an exclusive- Q3 or gate (see Figure8-2 and Figure8-3). One latch is updated with the comparator output level when the CxIN+ TRT CMxCON0 register is read. This latch retains the value Cxout until the next read of the CMxCON0 register or the Set CxIF (edge) occurrence of a Reset. The other latch of the mismatch CxIF circuit is updated on every Q1 system clock. A reset by software mismatch condition will occur when a comparator output change is clocked through the second latch on FIGURE 8-5: COMPARATOR the Q1 clock cycle. At this point the two mismatch INTERRUPT TIMING WITH latches have opposite output levels which is detected CMxCON0 READ by the exclusive-or gate and fed to the interrupt circuitry. The mismatch condition persists until either Q1 the CMxCON0 register is read or the comparator output returns to the previous state. Q3 CxIN+ TRT Note 1: A write operation to the CMxCON0 Cxout register will also clear the mismatch condition because all writes include a read Set CxIF (edge) operation at the beginning of the write CxIF cycle. cleared by CMxCON0 read reset by software 2: Comparator interrupts will operate correctly regardless of the state of CxOE. The comparator interrupt is set by the mismatch edge Note1: If a change in the CMxCON0 register and not the mismatch level. This means that the inter- (CxOUT) should occur when a read rupt flag can be reset without the additional step of operation is being executed (start of the reading or writing the CMxCON0 register to clear the Q2 cycle), then the CxIF of the PIR1 mismatch registers. When the mismatch registers are register interrupt flag may not get set. cleared, an interrupt will occur upon the comparator’s 2: When either comparator is first enabled, return to the previous state, otherwise no interrupt will bias circuitry in the Comparator module be generated. may cause an invalid output from the Software will need to maintain information about the comparator until the bias circuitry is status of the comparator output, as read from the stable. Allow about 1 s for bias settling CMxCON0 register, or CM2CON1 register, to determine then clear the mismatch condition and the actual change that has occurred. interrupt flags before enabling comparator interrupts. The CxIF bit of the PIR1 register is the comparator interrupt flag. This bit must be reset in software by clearing it to ‘0’. Since it is also possible to write a ‘1’ to this register, an interrupt can be generated. The CxIE bit of the PIE1 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CxIF bit of the PIR1 register will still be set if an interrupt condition occurs. DS40001262F-page 94  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 8.5 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section17.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CxIE bit of the PIE1 register and the PEIE bit of the INTCON register must be set. The instruction following the Sleep instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. 8.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their OFF states.  2005-2015 Microchip Technology Inc. DS40001262F-page 95

PIC16F631/677/685/687/689/690 REGISTER 8-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT = 0 when C1VIN+ > C1VIN- C1OUT = 1 when C1VIN+ < C1VIN- If C1POL = 0 (non-inverted polarity): C1OUT = 1 when C1VIN+ > C1VIN- C1OUT = 0 when C1VIN+ < C1VIN- bit 5 C1OE: Comparator C1 Output Enable bit 1 = C1OUT is present on the C1OUT pin(1) 0 = C1OUT is internal only bit 4 C1POL: Comparator C1 Output Polarity Select bit 1 = C1OUT logic is inverted 0 = C1OUT logic is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 C1R: Comparator C1 Reference Select bit (non-inverting input) 1 = C1VIN+ connects to C1VREF output 0 = C1VIN+ connects to C1IN+ pin bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit 00 = C1VIN- of C1 connects to C12IN0- pin 01 = C1VIN- of C1 connects to C12IN1- pin 10 = C1VIN- of C1 connects to C12IN2- pin 11 = C1VIN- of C1 connects to C12IN3- pin Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding PORT TRIS bit = 0. DS40001262F-page 96  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 REGISTER 8-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT = 0 when C2VIN+ > C2VIN- C2OUT = 1 when C2VIN+ < C2VIN- If C2POL = 0 (non-inverted polarity): C2OUT = 1 when C2VIN+ > C2VIN- C2OUT = 0 when C2VIN+ < C2VIN- bit 5 C2OE: Comparator C2 Output Enable bit 1 = C2OUT is present on C2OUT pin(1) 0 = C2OUT is internal only bit 4 C1POL: Comparator C1 Output Polarity Select bit 1 = C1OUT logic is inverted 0 = C1OUT logic is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input) 1 = C2VIN+ connects to C2VREF 0 = C2VIN+ connects to C2IN+ pin bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits 00 = C2VIN- of C2 connects to C12IN0- pin 01 = C2VIN- of C2 connects to C12IN1- pin 10 = C2VIN- of C2 connects to C12IN2- pin 11 = C2VIN- of C2 connects to C12IN3- pin Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding PORT TRIS bit = 0.  2005-2015 Microchip Technology Inc. DS40001262F-page 97

PIC16F631/677/685/687/689/690 8.7 Analog Input Connection Considerations Note1: When reading a PORT register, all pins configured as analog inputs will read as a A simplified circuit for an analog input is shown in ‘0’. Pins configured as digital inputs will Figure8-6. Since the analog input pins share their con- convert as an analog input, according to nection with a digital input, they have reverse biased the input specification. ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the 2: Analog levels on any pin defined as a input voltage deviates from this range by more than digital input, may cause the input buffer to 0.6V in either direction, one of the diodes is forward consume more current than is specified. biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. FIGURE 8-6: ANALOG INPUT MODEL VDD Rs < 10K VT  0.6V RIC To Comparator AIN VA C5 PpIFN VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage Note 1: See Section17.0 “Electrical Specifications” DS40001262F-page 98  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 8.8 Additional Comparator Features 8.8.2 SYNCHRONIZING COMPARATOR C2 OUTPUT TO TIMER1 There are three additional comparator features: The Comparator C2 output can be synchronized with • Timer1 count enable (gate) Timer1 by setting the C2SYNC bit of the CM2CON1 • Synchronizing output with Timer1 register. When enabled, the C2 output is latched on the • Simultaneous read of comparator outputs falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after 8.8.1 COMPARATOR C2 GATING TIMER1 the prescaling function. To prevent a race condition, the This feature can be used to time the duration or interval comparator output is latched on the falling edge of the of analog events. Clearing the T1GSS bit of the Timer1 clock source and Timer1 increments on the CM2CON1 register will enable Timer1 to increment rising edge of its clock source. See the Comparator based on the output of Comparator C2. This requires Block Diagram (Figure8-3) and the Timer1 Block that Timer1 is on and gating is enabled. See Diagram (Figure6-1) for more information. Section6.0 “Timer1 Module with Gate Control” for 8.8.3 SIMULTANEOUS COMPARATOR details. OUTPUT READ It is recommended to synchronize the comparator with Timer1 by setting the C2SYNC bit when the comparator The MC1OUT and MC2OUT bits of the CM2CON1 is used as the Timer1 gate source. This ensures Timer1 register are mirror copies of both comparator outputs. does not miss an increment if the comparator changes The ability to read both outputs simultaneously from a during an increment. single register eliminates the timing skew of reading separate registers. Note1: Obtaining the status of C1OUT or C2OUT by reading CM2CON1 does not affect the comparator interrupt mismatch registers. REGISTER 8-3: CM2CON1: COMPARATOR C2 CONTROL REGISTER 1 R-0 R-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 MC1OUT MC2OUT — — — — T1GSS C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5-2 Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit(1) 1 = Timer1 gate source is T1G 0 = Timer1 gate source is SYNCC2OUT. bit 0 C2SYNC: Comparator C2 Output Synchronization bit(2) 1 = Output is synchronous to falling edge of Timer1 clock 0 = Output is asynchronous Note 1: Refer to Section6.6 “Timer1 Gate”. 2: Refer to Figure8-3.  2005-2015 Microchip Technology Inc. DS40001262F-page 99

PIC16F631/677/685/687/689/690 8.9 Comparator SR Latch 8.9.2 LATCH OUTPUT The SR Latch module provides additional control of the The SR<1:0> bits of the SRCON register control the comparator outputs. The module consists of a single latch output multiplexers and determine four possible SR latch and output multiplexers. The SR latch can be output configurations. In these four configurations, the set, reset or toggled by the comparator outputs. The SR CxOUT I/O port logic is connected to: latch may also be set or reset, independent of • C1OUT and C2OUT comparator output, by control bits in the SRCON control • C1OUT and SR latch Q register. The SR latch output multiplexers select • C2OUT and SR latch Q whether the latch outputs or the comparator outputs are • SR latch Q and Q directed to the I/O port logic for eventual output to a pin. After any Reset, the default output configuration is the 8.9.1 LATCH OPERATION unlatched C1OUT and C2OUT mode. This maintains The latch is a Set-Reset latch that does not depend on a compatibility with devices that do not have the SR latch clock source. Each of the Set and Reset inputs are feature. active-high. Each latch input is connected to a The applicable TRIS bits of the corresponding ports comparator output and a software controlled pulse must be cleared to enable the port pin output drivers. generator. The latch can be set by C1OUT or the PULSS Additionally, the CxOE comparator output enable bits of bit of the SRCON register. The latch can be reset by the CMxCON0 registers must be set in order to make the C2OUT or the PULSR bit of the SRCON register. The comparator or latch outputs available on the output pins. latch is reset-dominant, therefore, if both Set and Reset The latch configuration enable states are completely inputs are high, the latch will go to the Reset state. Both independent of the enable states for the comparators. the PULSS and PULSR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch set or reset operation. FIGURE 8-7: SR LATCH SIMPLIFIED BLOCK DIAGRAM SR0 C1OE PULSS Pulse Gen(2) 0 C1OUT (from comparator) MUX S Q 1 C1OUT pin(3) C1SEN SR Latch(1) C2OE SYNCC2OUT (from comparator) R Q 1 C2REN MUX 0 C2OUT pin(3) PULSR Pulse SR1 Gen(2) Note 1: If R=1 and S=1 simultaneously, Q=0, Q=1 2: Pulse generator causes a 1/2 Q-state (1 Tosc) pulse width. 3: Output shown for reference only. See I/O port pin block diagram for more detail. DS40001262F-page 100  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 REGISTER 8-4: SRCON: SR LATCH CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 U-0 SR1(2) SR0(2) C1SEN C2REN PULSS PULSR — — bit 7 bit 0 Legend: S = Bit is set only R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SR1: SR Latch Configuration bit(2) 1 = C2OUT pin is the latch Q output 0 = C2OUT pin is the C2 comparator output bit 6 SR0: SR Latch Configuration bits(2) 1 = C1OUT pin is the latch Q output 0 = C1OUT pin is the Comparator C1 output bit 5 C1SEN: C1 Set Enable bit 1 = C1 comparator output sets SR latch 0 = C1 comparator output has no effect on SR latch bit 4 C2REN: C2 Reset Enable bit 1 = C2 comparator output resets SR latch 0 = C2 comparator output has no effect on SR latch bit 3 PULSS: Pulse the SET Input of the SR Latch bit 1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware. 0 = Does not trigger pulse generator bit 2 PULSR: Pulse the Reset Input of the SR Latch bit 1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware. 0 = Does not trigger pulse generator bit 1-0 Unimplemented: Read as ‘0’ Note 1: The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on the pin), regardless of the SR latch operation. 2: To enable an SR latch output to the pin, the appropriate CxOE and TRIS bits must be properly configured.  2005-2015 Microchip Technology Inc. DS40001262F-page 101

PIC16F631/677/685/687/689/690 8.10 Comparator Voltage Reference 8.10.3 OUTPUT CLAMPED TO VSS The comparator voltage reference module provides an The CVREF output voltage can be set to Vss with no internally generated voltage reference for the compara- power consumption by clearing the VP6EN bit of the tors. The following features are available: VRCON register. • Independent from Comparator operation This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current. • Two 16-level voltage ranges • Output clamped to VSS 8.10.4 OUTPUT RATIOMETRIC TO VDD • Ratiometric with VDD The comparator voltage reference is VDD derived and • Fixed Reference (0.6) therefore, the CVREF output changes with fluctuations in The VRCON register (Register8-5) controls the VDD. The tested absolute accuracy of the Comparator Voltage Reference module shown in Figure8-8. Voltage Reference can be found in Section17.0 “Electrical Specifications”. 8.10.1 INDEPENDENT OPERATION The comparator voltage reference is independent of the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference. 8.10.2 OUTPUT VOLTAGE SELECTION The CVREF voltage reference has two ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON register. The CVREF output voltage is determined by the following equations: EQUATION 8-1: CVREF OUTPUT VOLTAGE VRR = 1 (low range): CVREF = (VR<3:0>/24)VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR<3:0>VDD/32) The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure8-8. DS40001262F-page 102  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 8.10.5 FIXED VOLTAGE REFERENCE 8.10.7 VOLTAGE REFERENCE SELECTION The Fixed Voltage Reference is independent of VDD, with a nominal output voltage of 0.6V. This reference Multiplexers on the output of the Voltage Reference can be enabled by setting the VP6EN bit of the VRCON module enable selection of either the CVREF or Fixed register to ‘1’. This reference is always enabled when Voltage Reference for use by the comparators. the HFINTOSC oscillator is active. Setting the C1VREN bit of the VRCON register enables 8.10.6 FIXED VOLTAGE REFERENCE current to flow in the CVREF voltage divider and selects the CVREF voltage for use by C1. Clearing the C1VREN STABILIZATION PERIOD bit selects the fixed voltage for use by C1. When the Fixed Voltage Reference module is enabled, Setting the C2VREN bit of the VRCON register enables it will require some time for the reference and its current to flow in the CVREF voltage divider and selects amplifier circuits to stabilize. The user program must the CVREF voltage for use by C2. Clearing the C2VREN include a small delay routine to allow the module to bit selects the fixed voltage for use by C2. settle. See the electrical specifications section for the minimum delay requirement. When both the C1VREN and C2VREN bits are cleared, current flow in the CVREF voltage divider is disabled minimizing the power drain of the voltage reference peripheral. FIGURE 8-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR Analog MUX 15 CVREF(1) To Comparators and ADC Module 0 VR<3:0>(1) C1VREN 4 C2VREN VP6EN Sleep HFINTOSC enable EN Fixed Ref 0.6V Fixed Voltage To Comparators Reference and ADC Module Note 1: Care should be taken to ensure VREF remains within the comparator Common mode input range. See Section17.0 “Electrical Specifica- tions” for more detail.  2005-2015 Microchip Technology Inc. DS40001262F-page 103

PIC16F631/677/685/687/689/690 REGISTER 8-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1VREN: Comparator 1 Voltage Reference Enable bit 1 = CVREF circuit powered on and routed to C1VREF input of Comparator C1 0 = 0.6 Volt constant reference routed to C1VREF input of Comparator C1 bit 6 C2VREN: Comparator 2 Voltage Reference Enable bit 1 = CVREF circuit powered on and routed to C2VREF input of Comparator C2 0 = 0.6 Volt constant reference routed to C2VREF input of Comparator C2 bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 VP6EN: 0.6V Reference Enable bit 1 = Enabled 0 = Disabled bit 3-0 VR<3:0>: Comparator Voltage Reference CVREF Value Selection bits (0  VR<3:0>  15) When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 0000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 CM2CON1 MC1OUT MC2OUT — — — — T1GSS C2SYNC 00-- --10 00-- --10 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE2 OSFIE C2IE C1IE EEIE — — — — 0000 ---- 0000 ---- PIR2 OSFIF C2IF C1IF EEIF — — — — 0000---- 0000---- PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — — 0000 00-- 0000 00-- TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator. DS40001262F-page 104  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 9.0 ANALOG-TO-DIGITAL Figure9-1 shows the block diagram of the ADC. CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). Note: The ADC module applies to PIC16F677/ PIC16F685/PIC16F687/PIC16F689/ PIC16F690 devices only. The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. FIGURE 9-1: ADC BLOCK DIAGRAM VDD VCFG = 0 VREF VCFG = 1 RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA4/AN3/T1G/OSC2/CLKOUT RC0/AN4/C2IN+ RC1/AN5/C12IN1- RC2/AN6/C12IN2-/P1D(1) RC3/AN7/C12IN3-/P1C(1) ADC RC6/AN8/SS(2) GO/DONE 10 RC7/AN9/SDO(2) 0 = Left Justify RB4/AN10/SDI/SDA(2) ADFM 1 = Right Justify RB5/AN11/RX/DT(2) ADON 10 CVREF VSS ADRESH ADRESL VP6 Reference CHS Note 1: P1C and P1D available on PIC16F685/PIC16F690 only. 2: SS, SDO, SDA, RX and DT available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 3: ADC module applies to the PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 devices only.  2005-2015 Microchip Technology Inc. DS40001262F-page 105

PIC16F631/677/685/687/689/690 9.1 ADC Configuration 9.1.3 ADC VOLTAGE REFERENCE When configuring and using the ADC the following The VCFG bit of the ADCON0 register provides control functions must be considered: of the positive voltage reference. The positive voltage reference can be either VDD or an external voltage • Port configuration source. The negative voltage reference is always • Channel selection connected to the ground reference. • ADC voltage reference selection 9.1.4 CONVERSION CLOCK • ADC conversion clock source • Interrupt control The source of the conversion clock is software • Results formatting selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: 9.1.1 PORT CONFIGURATION • FOSC/2 The ADC can be used to convert both analog and digital • FOSC/4 signals. When converting analog signals, the I/O pin • FOSC/8 should be configured for analog by setting the associated • FOSC/16 TRIS and ANSEL bits. See the corresponding port • FOSC/32 section for more information. • FOSC/64 Note: Analog voltages on any pin that is defined • FRC (dedicated internal oscillator) as a digital input may cause the input buf- fer to conduct excess current. The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods 9.1.2 CHANNEL SELECTION as shown in Figure9-2. The CHS bits of the ADCON0 register determine which For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in channel is connected to the sample and hold circuit. Section17.0 “Electrical Specifications” for more When changing channels, a delay is required before information. Table9-1 gives examples of appropriate starting the next conversion. Refer to Section9.2 ADC clock selections. “ADC Operation” for more information. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. DS40001262F-page 106  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V, VREF > 2.5V) ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 100 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 200 ns(2) 500 ns(2) 1.0 s(2) 4.0 s FOSC/8 001 400 ns(2) 1.0 s(2) 2.0 s 8.0 s(3) FOSC/16 101 800 ns(2) 2.0 s 4.0 s 16.0 s(3) FOSC/32 010 1.6 s 4.0 s 8.0 s(3) 32.0 s(3) FOSC/64 110 3.2 s 8.0 s(3) 16.0 s(3) 64.0 s(3) FRC x11 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 4 s for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY to TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding Capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input 9.1.5 INTERRUPTS Please see Section9.1.5 “Interrupts” for more information. The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the interrupt service routine.  2005-2015 Microchip Technology Inc. DS40001262F-page 107

PIC16F631/677/685/687/689/690 9.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure9-3 shows the two output formats. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result DS40001262F-page 108  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 9.2 ADC Operation 9.2.5 SPECIAL EVENT TRIGGER An ECCP Special Event Trigger allows periodic ADC 9.2.1 STARTING A CONVERSION measurements without software intervention. When To enable the ADC module, the ADON bit of the this trigger occurs, the GO/DONE bit is set by hardware ADCON0 register must be set to a ‘1’. Setting the GO/ and the Timer1 counter resets to zero. DONE bit of the ADCON0 register to a ‘1’ will start the Using the Special Event Trigger does not assure proper Analog-to-Digital conversion. ADC timing. It is the user’s responsibility to ensure that Note: The GO/DONE bit should not be set in the the ADC timing requirements are met. same instruction that turns on the ADC. See Section11.0 “Enhanced Capture/Compare/ Refer to Section9.2.6 “A/D Conversion PWM Module” for more information. Procedure”. 9.2.6 A/D CONVERSION PROCEDURE 9.2.2 COMPLETION OF A CONVERSION This is an example procedure for using the ADC to When the conversion is complete, the ADC module will: perform an Analog-to-Digital conversion: • Clear the GO/DONE bit 1. Configure Port: • Set the ADIF flag bit • Disable pin output driver (See TRIS register) • Update the ADRESH:ADRESL registers with new • Configure pin as analog conversion result 2. Configure the ADC module: • Select ADC conversion clock 9.2.3 TERMINATING A CONVERSION • Configure voltage reference If a conversion must be terminated before completion, • Select ADC input channel the GO/DONE bit can be cleared in software. The • Select result format ADRESH:ADRESL registers will not be updated with the partially complete Analog-to-Digital conversion • Turn on ADC module sample. Instead, the ADRESH:ADRESL register pair 3. Configure ADC interrupt (optional): will retain the value of the previous conversion. Addi- • Clear ADC interrupt flag tionally, a 2TAD delay is required before another acqui- • Enable ADC interrupt sition can be initiated. Following this delay, an input • Enable peripheral interrupt acquisition is automatically started on the selected • Enable global interrupt(1) channel. 4. Wait the required acquisition time(2). Note: A device Reset forces all registers to their 5. Start conversion by setting the GO/DONE bit. Reset state. Thus, the ADC module is turned off and any pending conversion is 6. Wait for ADC conversion to complete by one of terminated. the following: • Polling the GO/DONE bit 9.2.4 ADC OPERATION DURING SLEEP • Waiting for the ADC interrupt (interrupts enabled) The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC 7. Read ADC Result option. When the FRC clock source is selected, the 8. Clear the ADC interrupt flag (required if interrupt ADC waits one additional instruction before starting the is enabled). conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device Note1: The global interrupt can be disabled if the will wake-up from Sleep when the conversion user is attempting to wake-up from Sleep completes. If the ADC interrupt is disabled, the ADC and resume in-line code execution. module is turned off after the conversion completes, 2: See Section9.3 “A/D Acquisition although the ADON bit remains set. Requirements”. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conver- sion to be aborted and the ADC module is turned off, although the ADON bit remains set.  2005-2015 Microchip Technology Inc. DS40001262F-page 109

PIC16F631/677/685/687/689/690 EXAMPLE 9-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSELADCON1; MOVLWB’01110000’;ADC Frc clock MOVWFADCON1; BANKSELTRISA; BSF TRISA,0;Set RA0 to input BANKSELANSEL; BSF ANSEL,0;Set RA0 to analog BANKSELADCON0; MOVLWB’10000001’;Right justify, MOVWFADCON0; Vdd Vref, AN0, On CALLSampleTime;Acquisiton delay BSF ADCON0,GO;Start conversion BTFSCADCON0,GO;Is conversion done? GOTO$-1;No, test again BANKSELADRESH; MOVFADRESH,W;Read upper 2 bits MOVWFRESULTHI;store in GPR space BANKSELADRESL; MOVFADRESL,W;Read lower 8 bits MOVWFRESULTLO;Store in GPR space 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. DS40001262F-page 110  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = AN0 0001 = AN1 0010 = AN2 0011 = AN3 0100 = AN4 0101 = AN5 0110 = AN6 0111 = AN7 1000 = AN8 1001 = AN9 1010 = AN10 1011 = AN11 1100 = CVREF 1101 = 0.6V Fixed Voltage Reference 1110 = Reserved. Do not use. 1111 = Reserved. Do not use. bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current  2005-2015 Microchip Technology Inc. DS40001262F-page 111

PIC16F631/677/685/687/689/690 REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCS2 ADCS1 ADCS0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 bit 3-0 Unimplemented: Read as ‘0’ DS40001262F-page 112  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 REGISTER 9-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 9-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES1 ADRES0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 9-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — — — — ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 9-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result  2005-2015 Microchip Technology Inc. DS40001262F-page 113

PIC16F631/677/685/687/689/690 9.3 A/D Acquisition Requirements an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition For the ADC to meet its specified accuracy, the charge time, Equation9-1 may be used. This equation holding capacitor (CHOLD) must be allowed to fully assumes that 1/2 LSb error is used (1024 steps for the charge to the input channel voltage level. The Analog ADC). The 1/2 LSb error is the maximum error allowed Input model is shown in Figure9-4. The source for the ADC to meet its specified resolution. impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure9-4. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), EQUATION 9-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– ------n----+----1------------ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb 2 –1 –TC  ---------- RC VAPPLIED1–e  = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– ------n---+-----1------------ ;combining [1] and [2]   2  –1 Note: Where n = number of bits of the ADC. Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/2047) = –10pF1k+7k+10k ln(0.0004885) = 1.37µs Therefore: TACQ = 2ΜS+1.37ΜS+50°C- 25°C0.05ΜS/°C = 4.67ΜS DS40001262F-page 114  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification. FIGURE 9-4: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC  1k SS Rss VA C5 PpIFN VT = 0.6V I LEAKAGE(1) CHOLD = 10 pF VSS/VREF- 6V 5V RSS Legend: CPIN = Input Capacitance VDD4V VT = Threshold Voltage 3V 2V I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance 5 6 7 891011 SS = Sampling Switch Sampling Switch CHOLD = Sample/Hold Capacitance (k) Note 1: See Section17.0 “Electrical Specifications”. FIGURE 9-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh de 3FCh 1 LSB ideal o C 3FBh ut p ut Full-Scale O C 004h Transition D A 003h 002h 001h 000h Analog Input Voltage 1 LSB ideal VSS/VREF- Zero-Scale VDD/VREF+ Transition  2005-2015 Microchip Technology Inc. DS40001262F-page 115

PIC16F631/677/685/687/689/690 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets ADCON0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ---- ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 ANSELH — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111 ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ---- PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. DS40001262F-page 116  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 10.0 DATA EEPROM AND FLASH 10.1 EEADR and EEADRH Registers PROGRAM MEMORY The EEADR and EEADRH registers can address up to CONTROL a maximum of 256bytes of data EEPROM or up to a maximum of 4K words of program EEPROM. Data EEPROM memory is readable and writable and the Flash program memory (PIC16F685/PIC16F689/ When selecting a program address value, the MSB of PIC16F690 only) is readable during normal operation the address is written to the EEADRH register and the (full VDD range). These memories are not directly LSB is written to the EEADR register. When selecting a mapped in the register file space. Instead, they are indi- data address value, only the LSB of the address is rectly addressed through the Special Function Regis- written to the EEADR register. ters (SFRs). There are six SFRs used to access these 10.1.1 EECON1 AND EECON2 REGISTERS memories: EECON1 is the control register for EE memory • EECON1 accesses. • EECON2 Control bit EEPGD (PIC16F685/PIC16F689/PIC16F690) • EEDAT determines if the access will be a program or data mem- • EEDATH (PIC16F685/PIC16F689/PIC16F690 only) ory access. When clear, as it is when reset, any subse- • EEADR quent operations will operate on the data memory. When • EEADRH (PIC16F685/PIC16F689/PIC16F690 only) set, any subsequent operations will operate on the pro- When interfacing the data memory block, EEDAT holds gram memory. Program memory can only be read. the 8-bit data for read/write, and EEADR holds the Control bits RD and WR initiate read and write, address of the EEDAT location being accessed. These respectively. These bits cannot be cleared, only set, in devices, except for the PIC16F631, have 256 bytes of software. They are cleared in hardware at completion data EEPROM with an address range from 0h to 0FFh. of the read or write operation. The inability to clear the The PIC16F631 has 128 bytes of data EEPROM with WR bit in software prevents the accidental, premature an address range from 0h to 07Fh. termination of a write operation. When accessing the program memory block of the The WREN bit, when set, will allow a write operation to PIC16F685/PIC16F689/PIC16F690 devices, the EEDAT data EEPROM. On power-up, the WREN bit is clear. and EEDATH registers form a 2-byte word that holds the The WRERR bit is set when a write operation is 14-bit data for read/write, and the EEADR and EEADRH interrupted by a MCLR or a WDT Time-out Reset registers form a 2-byte word that holds the 12-bit address during normal operation. In these situations, following of the EEPROM location being read. These devices Reset, the user can check the WRERR bit and rewrite (PIC16F685/PIC16F689/PIC16F690) have 4K words of the location. program EEPROM with an address range from 0h to Interrupt flag bit EEIF of the PIR2 register is set when 0FFFh. The program memory allows one-word reads. write is complete. It must be cleared in the software. The EEPROM data memory allows byte read and write. EECON2 is not a physical register. Reading EECON2 A byte write automatically erases the location and will read all ‘0’s. The EECON2 register is used writes the new data (erase before write). exclusively in the data EEPROM write sequence. The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. When the device is code-protected, the CPU may continue to read and write the data EEPROM memory and read the program memory. When code-protected, the device programmer can no longer access data or program memory.  2005-2015 Microchip Technology Inc. DS40001262F-page 117

PIC16F631/677/685/687/689/690 REGISTER 10-1: EEDAT: EEPROM DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EEDAT<7:0>: Eight Least Significant Address bits to Write to or Read from data EEPROM or Read from program memory REGISTER 10-2: EEADR: EEPROM ADDRESS REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEADR7(1) EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EEADR<7:0>: Eight Least Significant Address bits for EEPROM Read/Write Operation(1) or Read from program memory Note 1: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. REGISTER 10-3: EEDATH: EEPROM DATA HIGH BYTE REGISTER(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 EEDATH<5:0>: Six Most Significant Data bits from program memory Note 1: PIC16F685/PIC16F689/PIC16F690 only. REGISTER 10-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER(1) U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 EEADRH<3:0>: Specifies the four Most Significant Address bits or high bits for program memory reads DS40001262F-page 118  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 REGISTER 10-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER(1) (CONTINUED) Note 1: PIC16F685/PIC16F689/PIC16F690 only. REGISTER 10-5: EECON1: EEPROM CONTROL REGISTER R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD(1) — — — WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Program/Data EEPROM Select bit(1) 1 = Accesses program memory 0 = Accesses data memory bit 6-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOR Reset) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM bit 1 WR: Write Control bit EEPGD = 1: This bit is ignored EEPGD = 0: 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in software.) 0 = Does not initiate a memory read Note 1: PIC16F685/PIC16F689/PIC16F690 only.  2005-2015 Microchip Technology Inc. DS40001262F-page 119

PIC16F631/677/685/687/689/690 10.1.2 READING THE DATA EEPROM 10.1.3 WRITING TO THE DATA EEPROM MEMORY MEMORY To read a data memory location, the user must write the To write an EEPROM data location, the user must first address to the EEADR register, clear the EEPGD write the address to the EEADR register and the data control bit of the EECON1 register, and then set control to the EEDAT register. Then the user must follow a bit RD. The data is available at the very next cycle, in specific sequence to initiate the write for each byte. the EEDAT register; therefore, it can be read in the next The write will not initiate if the specific sequence is not instruction. EEDAT will hold this value until another followed exactly (write 55h to EECON2, write AAh to read or until it is written to by the user (during a write EECON2, then set WR bit) for each byte. Interrupts operation). should be disabled during this codesegment. Additionally, the WREN bit in EECON1 must be set to EXAMPLE 10-1: DATA EEPROM READ enable write. This mechanism prevents accidental BANKSELEEADR ; writes to data EEPROM due to errant (unexpected) MOVF DATA_EE_ADDR, W; code execution (i.e., lost programs). The user should MOVWF EEADR ;Data Memory keep the WREN bit clear at all times, except when ;Address to read updating EEPROM. The WREN bit is not cleared BANKSELEECON1 ; byhardware. BCF EECON1, EEPGD;Point to DATA memory BSF EECON1, RD ;EE Read After a write sequence has been initiated, clearing the BANKSELEEDAT ; WREN bit will not affect this write cycle. The WR bit will MOVF EEDAT, W ;W = EEDAT be inhibited from being set unless the WREN bit is set. BANKSELPORTA ;Bank 0 At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. EXAMPLE 10-2: DATA EEPROM WRITE BANKSELEEADR ; MOVFDATA_EE_ADDR, W; MOVWFEEADR ;Data Memory Address to write MOVFDATA_EE_DATA, W; MOVWFEEDAT ;Data Memory Value to write BANKSELEECON1 ; BCF EECON1, EEPGD;Point to DATA memory BSF EECON1, WREN;Enable writes BCF INTCON, GIE ;Disable INTs. BTFSCINTCON, GIE;SEE AN576 GOTO$-2 MOVLW55h ; RequiredSequence MMMOOOVVVWLWFWFEAEEAEChCOONN22 ;;;WWrriittee 5A5Ahh BSF EECON1, WR ;Set WR bit to begin write BSF INTCON, GIE ;Enable INTs. SLEEP ;Wait for interrupt to signal write complete (optional) BCF EECON1, WREN;Disable writes BANKSEL0x00 ;Bank 0 DS40001262F-page 120  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 10.1.4 READING THE FLASH PROGRAM EEDAT and EEDATH registers will hold this value until MEMORY (PIC16F685/PIC16F689/ another read or until it is written to by the user. PIC16F690) Note1: The two instructions following a program To read a program memory location, the user must memory read are required to be NOPs. write the Least and Most Significant address bits to the This prevents the user from executing a EEADR and EEADRH registers, set the EEPGD con- 2-cycle instruction on the next instruction trol bit of the EECON1 register, and then set control bit after the RD bit is set. RD. Once the read control bit is set, the program mem- 2: If the WR bit is set when EEPGD = 1, it ory Flash controller will use the second instruction will be immediately reset to ‘0’ and no cycle to read the data. This causes the second instruc- operation will take place. tion immediately following the “BSF EECON1,RD” instruction to be ignored. The data is available in the very next cycle, in the EEDAT and EEDATH registers; therefore, it can be read as two bytes in the following instructions. EXAMPLE 10-3: FLASH PROGRAM READ BANKSELEEADR ; MOVF MS_PROG_EE_ADDR, W ; MOVWF EEADRH ;MS Byte of Program Address to read MOVF LS_PROG_EE_ADDR, W ; MOVWF EEADR ;LS Byte of Program Address to read BANKSELEECON1 ; BSF EECON1, EEPGD ;Point to PROGRAM memory BSF EECON1, RD ;EE Read Required; Sequence NOP ;First instruction after BSF EECON1,RD executes normally NOP ;Any instructions here are ignored as program ;memory is read in second cycle after BSF EECON1,RD ; BANKSELEEDAT ; MOVF EEDAT, W ;W = LS Byte of Program Memory MOVWF LOWPMBYTE ; MOVF EEDATH, W ;W = MS Byte of Program EEDAT MOVWF HIGHPMBYTE ; BANKSEL0x00 ;Bank 0  2005-2015 Microchip Technology Inc. DS40001262F-page 121

PIC16F631/677/685/687/689/690 FIGURE 10-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Table 0-1: Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 Flash ADDR PC PC + 1 EEADRH,EEADR PPCC ++ 33 PC + 4 PC + 5 Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDAT INSTR (PC + 3) INSTR (PC + 4) INSTR(PC - 1) BSF EECON1,RD INSTR(PC + 1) Forced NOP INSTR(PC + 3) INSTR(PC + 4) executed here executed here executed here executed here executed here executed here RD bit EEDATH EEDAT Register EERHLT DS40001262F-page 122  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 10.2 Write Verify When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is Depending on the application, good programming recommended to code-protect the program memory practice may dictate that the value written to the data when code-protecting data memory and programming EEPROM should be verified (see Example10-4) to the unused program memory with NOP instructions. desired value to be written. EXAMPLE 10-4: WRITE VERIFY BANKSELEEDAT ; MOVF EEDAT, W ;EEDAT not changed ;from previous write BANKSELEECON1 ; BSF EECON1, RD ;YES, Read the ;value written BANKSELEEDAT ; XORWF EEDAT, W ; BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue BANKSEL0x00 ;Bank 0 10.2.1 USING THE DATA EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM (specification D124) without exceeding the total number of write cycles to a single byte (specifications D120 and D120A). If this is the case, then a refresh of the array must be performed. For this reason, variables that do not change (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. 10.3 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64ms duration) prevents EEPROMwrite. The write initiate sequence and the WREN bit together help prevent an accidental write during: • Brown-out • Power Glitch • Software Malfunction 10.4 Data EEPROM Operation During Code-Protect Data memory can be code-protected by programming the CPD bit in the Configuration Word register (Register14-1) to ‘0’.  2005-2015 Microchip Technology Inc. DS40001262F-page 123

PIC16F631/677/685/687/689/690 TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets EECON1 EEPGD(1) — — — WRERR WREN WR RD x--- x000 0--- q000 EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---- EEADR EEADR7(2) EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 EEADRH(1) — — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 ---- 0000 EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 EEDATH(1) — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 0000 0000 0000 PIE2 OSFIE C2IE C1IE EEIE — — — — 0000 ---- 0000 ---- PIR2 OSFIF C2IF C1IF EEIF — — — — 0000 ---- 0000 ---- Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by data EEPROM module. Note 1: PIC16F685/PIC16F689/PIC16F690 only. 2: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only. DS40001262F-page 124  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 11.0 ENHANCED CAPTURE/ Table11-1 shows the timer resources required by the COMPARE/PWM MODULE ECCP module. The Enhanced Capture/Compare/PWM module is a TABLE 11-1: ECCP MODE – TIMER peripheral which allows the user to time and control RESOURCES REQUIRED different events. In Capture mode, the peripheral ECCP Mode Timer Resource allows the timing of the duration of an event. The Compare mode allows the user to trigger an external Capture Timer1 event when a predetermined amount of time has Compare Timer1 expired. The PWM mode can generate a Pulse-Width PWM Timer2 Modulated signal of varying frequency and duty cycle. REGISTER 11-1: CCP1CON: ENHANCED CCP1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 P1M<1:0>: PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx =P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 =Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 =Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 =Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 =Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: ECCP Mode Select bits 0000 =Capture/Compare/PWM off (resets ECCP module) 0001 =Unused (reserved) 0010 =Compare mode, toggle output on match (CCP1IF bit is set) 0011 =Unused (reserved) 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, set output on match (CCP1IF bit is set) 1001 =Compare mode, clear output on match (CCP1IF bit is set) 1010 =Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 =Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2, and starts an A/D conversion, if the ADC module is enabled) 1100 =PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 =PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 =PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 =PWM mode; P1A, P1C active-low; P1B, P1D active-low  2005-2015 Microchip Technology Inc. DS40001262F-page 125

PIC16F631/677/685/687/689/690 11.1 Capture Mode 11.1.2 TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode or Synchronized 16-bit value of the TMR1 register when an event occurs Counter mode for the CCP module to use the capture on pin CCP1. An event is defined as one of the feature. In Asynchronous Counter mode, the capture following and is configured by the CCP1M<3:0> bits of operation may not work. the CCP1CON register: 11.1.3 SOFTWARE INTERRUPT • Every falling edge When the Capture mode is changed, a false capture • Every rising edge interrupt may be generated. The user should keep the • Every 4th rising edge CCP1IE interrupt enable bit of the PIE1 register clear to • Every 16th rising edge avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag following any change in operating mode. must be cleared in software. If another capture occurs 11.1.4 CCP PRESCALER before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new There are four prescaler settings specified by the captured value (see Figure11-1). CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP 11.1.1 CCP1 PIN CONFIGURATION module is not in Capture mode, the prescaler counter In Capture mode, the CCP1 pin should be configured is cleared. Any Reset will clear the prescaler counter. as an input by setting the associated TRIS control bit. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To Note: If the CCP1 pin is configured as an output, avoid this unexpected operation, turn the module off by a write to the port can cause a capture clearing the CCP1CON register before changing the condition. prescaler (see Example11-1). FIGURE 11-1: CAPTURE MODE EXAMPLE 11-1: CHANGING BETWEEN OPERATION BLOCK CAPTURE PRESCALERS DIAGRAM BANKSELCCP1CON ;Set Bank bits to point Set Flag bit CCP1IF ; to CCP1CON (PIR1 register) Prescaler CLRF CCP1CON ;Turn CCP module off  1, 4, 16 MOVLW NEW_CAPT_PS;Load the W reg with CCP1 CCPR1H CCPR1L ; the new prescaler pin ; move value and CCP ON and Capture MOVWF CCP1CON ;Load CCP1CON with this Edge Detect Enable ; value TMR1H TMR1L CCP1CON<3:0> System Clock (FOSC) DS40001262F-page 126  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 11.2 Compare Mode 11.2.2 TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is In Compare mode, Timer1 must be running in either constantly compared against the TMR1 register pair Timer mode or Synchronized Counter mode. The value. When a match occurs, the CCP module may: compare operation may not work in Asynchronous Counter mode. • Toggle the CCP1 output • Set the CCP1 output 11.2.3 SOFTWARE INTERRUPT MODE • Clear the CCP1 output When Generate Software Interrupt mode is chosen • Generate a Special Event Trigger (CCP1M<3:0>=1010), the CCP module does not • Generate a Software Interrupt assert control of the CCP1 pin (see the CCP1CON register). The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. 11.2.4 SPECIAL EVENT TRIGGER All Compare modes can generate an interrupt. When Special Event Trigger mode is chosen (CCP1M<3:0>=1011), the CCP module does the FIGURE 11-2: COMPARE MODE following: OPERATION BLOCK • Resets Timer1 DIAGRAM • Starts an ADC conversion if ADC is enabled CCP1CON<3:0> Mode Select The CCP module does not assert control of the CCP1 pin in this mode (see the CCP1CON register). Set CCP1IF Interrupt Flag The Special Event Trigger output of the CCP occurs (PIR1) CCP1 4 immediately upon a match between the TMR1H, Pin CCPR1H CCPR1L TMR1L register pair and the CCPR1H, CCPR1L Q S register pair. The TMR1H, TMR1L register pair is not Output Comparator R Logic Match reset until the next rising edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to TMR1H TMR1L TRIS effectively provide a 16-bit programmable period Output Enable register for Timer1. Special Event Trigger Note1: The Special Event Trigger from the CCP Special Event Trigger will: module does not set interrupt flag bit • Clear TMR1H and TMR1L registers. TMR1IF of the PIR1 register. • NOT set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by • Set the GO/DONE bit to start the ADC conversion. changing the contents of the CCPR1H and CCPR1L register pair, between the 11.2.1 CCP1 PIN CONFIGURATION clock edge that generates the Special Event Trigger and the clock edge that The user must configure the CCP1 pin as an output by generates the Timer1 Reset, will clearing the associated TRIS bit. preclude the Reset from occurring. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the port I/O data latch.  2005-2015 Microchip Technology Inc. DS40001262F-page 127

PIC16F631/677/685/687/689/690 11.3 PWM Mode The PWM output (Figure11-4) has a time base (period) and a time that the output stays high (duty The PWM mode generates a Pulse-Width Modulated cycle). signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: FIGURE 11-4: CCP PWM OUTPUT • PR2 • T2CON Period • CCPR1L Pulse Width • CCP1CON TMR2 = PR2 In Pulse-Width Modulation (PWM) mode, the CCP TMR2 = CCPR1L:CCP1CON<5:4> module produces up to a 10-bit resolution PWM output TMR2 = 0 on the CCP1 pin. Since the CCP1 pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCP1 pin output driver. Note: Clearing the CCP1CON register will relinquish CCP1 control of the CCP1 pin. Figure11-3 shows a simplified block diagram of PWM operation. Figure11-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section11.3.7 “Setup for PWM Operation”. FIGURE 11-3: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty Cycle Registers CCPR1L CCPR1H(2) (Slave) CCP1 Comparator R Q S TMR2 (1) TRIS Comparator Clear Timer2, toggle CCP1 pin and latch duty cycle PR2 Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. 2: In PWM mode, CCPR1H is a read-only register. DS40001262F-page 128  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 11.3.1 PWM PERIOD EQUATION 11-2: PULSE WIDTH The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the Pulse Width = CCPR1L:CCP1CON<5:4>  formula of Equation11-1. TOSC  (TMR2 Prescale Value) EQUATION 11-1: PWM PERIOD EQUATION 11-3: DUTY CYCLE RATIO PWM Period = PR2+14TOSC (TMR2 Prescale Value) CCPR1L:CCP1CON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------- 4PR2+1 Note: TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events The CCPR1H register and a 2-bit internal latch are occur on the next increment cycle: used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. • TMR2 is cleared The 8-bit timer TMR2 register is concatenated with • The CCP1 pin is set. (Exception: If the PWM duty either the 2-bit internal system clock (FOSC), or two bits cycle=0%, the pin will not be set.) of the prescaler, to create the 10-bit time base. The • The PWM duty cycle is latched from CCPR1L into system clock is used if the Timer2 prescaler is set to 1:1. CCPR1H. When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (see Figure11- Note: The Timer2 postscaler (see Section7.1 3). “Timer2 Operation”) is not used in the determination of the PWM frequency. 11.3.3 PWM RESOLUTION 11.3.2 PWM DUTY CYCLE The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution The PWM duty cycle is specified by writing a 10-bit will result in 1024 discrete duty cycles, whereas an 8-bit value to multiple registers: CCPR1L register and resolution will result in 256 discrete duty cycles. DC1B<1:0> bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1B<1:0> The maximum PWM resolution is ten bits when PR2 is bits of the CCP1CON register contain the two LSbs. 255. The resolution is a function of the PR2 register CCPR1L and DC1B<1:0> bits of the CCP1CON value as shown by Equation11-4. register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period EQUATION 11-4: PWM RESOLUTION completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H log4PR2+1 register is read-only. Resolution = ------------------------------------------ bits log2 Equation11-2 is used to calculate the PWM pulse width. Equation11-3 is used to calculate the PWM duty cycle Note: If the pulse width value is greater than the ratio. period the assigned PWM pin(s) will remain unchanged. TABLE 11-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 11-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5  2005-2015 Microchip Technology Inc. DS40001262F-page 129

PIC16F631/677/685/687/689/690 11.3.4 OPERATION IN SLEEP MODE 11.4 PWM (Enhanced Mode) In Sleep mode, the TMR2register will not increment The Enhanced PWM Mode can generate a PWM signal and the state of the module will not change. If the CCP1 on up to four different output pins with up to ten bits of pin is driving a value, it will continue to drive that value. resolution. It can do this through four different PWM When the device wakes up, TMR2 will continue from its Output modes: previous state. • Single PWM 11.3.5 CHANGES IN SYSTEM CLOCK • Half-Bridge PWM FREQUENCY • Full-Bridge PWM, Forward mode The PWM frequency is derived from the system clock • Full-Bridge PWM, Reverse mode frequency. Any changes in the system clock frequency To select an Enhanced PWM mode, the P1M bits of the will result in changes to the PWM frequency. See CCP1CON register must be set appropriately. Section3.0 “Oscillator Module (With Fail-Safe The PWM outputs are multiplexed with I/O pins and are Clock Monitor)” for additional details. designated P1A, P1B, P1C and P1D. The polarity of the 11.3.6 EFFECTS OF RESET PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. Any Reset will force all ports to Input mode and the Table11-4 shows the pin assignments for each CCP registers to their Reset states. Enhanced PWM mode. 11.3.7 SETUP FOR PWM OPERATION Figure11-5 shows an example of a simplified block The following steps should be taken when configuring diagram of the Enhanced PWM module. the CCP module for PWM operation: Note: To prevent the generation of an 1. Disable the PWM pin (CCP1) output driver by incomplete waveform when the PWM is setting the associated TRIS bit. first enabled, the ECCP module waits until 2. Set the PWM period by loading the PR2 register. the start of a new PWM period before generating a PWM signal. 3. Configure the CCP module for the PWM mode by loading the CCP1CON register with the appropriate values. 4. Set the PWM duty cycle by loading the CCPR1L register and DC1B<1:0> bits of the CCP1CON register. 5. Configure and start Timer2: •Clear the TMR2IF interrupt flag bit of the PIR1 register. •Set the Timer2 prescale value by loading the T2CKPS bits of the T2CON register. •Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output after a new PWM cycle has started: •Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCP1 pin output driver by clearing the associated TRIS bit. DS40001262F-page 130  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 11-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DC1B<1:0> P1M<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L CCP1/P1A CCP1/P1A TRIS CCPR1H (Slave) P1B P1B Output TRIS Comparator R Q Controller P1C P1C TMR2 (1) S TRIS P1D P1D Comparator Clear Timer2, TRIS toggle PWM pin and latch duty cycle PR2 PWM1CON Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. Note1: The TRIS register value for each PWM output must be configured appropriately. 2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins. 3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions TABLE 11-4: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode P1M<1:0> CCP1/P1A P1B P1C P1D Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Pulse Steering enables outputs in Single mode.  2005-2015 Microchip Technology Inc. DS40001262F-page 131

PIC16F631/677/685/687/689/690 FIGURE 11-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse PR2+1 P1M<1:0> Signal 0 Width Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section11.4.6 “Programmable Dead-Band Delay mode”). DS40001262F-page 132  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 11-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) P1M<1:0> Signal 0 Pulse PR2+1 Width Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section11.4.6 “Programmable Dead-Band Delay mode”).  2005-2015 Microchip Technology Inc. DS40001262F-page 133

PIC16F631/677/685/687/689/690 11.4.1 HALF-BRIDGE MODE Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must In Half-Bridge mode, two pins are used as outputs to be cleared to configure P1A and P1B as outputs. drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM FIGURE 11-8: EXAMPLE OF HALF- output signal is output on the P1B pin (see Figure11- BRIDGE PWM OUTPUT 6). This mode can be used for Half-Bridge applications, as shown in Figure11-9, or for Full-Bridge applications, Period Period where four power switches are being modulated with two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay P1A(2) can be used to prevent shoot-through current in Half- td Bridge power devices. The value of the PDC<6:0> bits of td the PWM1CON register sets the number of instruction P1B(2) cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output (1) (1) (1) remains inactive during the entire cycle. See Section11.4.6 “Programmable Dead-Band Delay td = Dead-Band Delay mode” for more details of the dead-band delay Note 1: At this time, the TMR2 register is equal to the operations. PR2 register. 2: Output signals are shown as active-high. FIGURE 11-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A - Load FET Driver + P1B - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver P1A Load FET FET Driver Driver P1B DS40001262F-page 134  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 11.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure11-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure11-11. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure11-11. P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 11-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D  2005-2015 Microchip Technology Inc. DS40001262F-page 135

PIC16F631/677/685/687/689/690 FIGURE 11-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS40001262F-page 136  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 11.4.2.1 Direction Change in Full-Bridge The Full-Bridge mode does not provide dead-band Mode delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation In the Full-Bridge mode, the P1M1 bit in the CCP1CON where dead-band delay is required. This situation register allows users to control the forward/reverse occurs when both of the following conditions are true: direction. When the application firmware changes this direction control bit, the module will change to the new 1. The direction of the PWM output changes when direction on the next PWM cycle. the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including A direction change is initiated in software by changing the power device and driver circuit, is greater the P1M1 bit of the CCP1CON register. The following than the turn-on time. sequence occurs prior to the end of the current PWM period: Figure11-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty • The modulated outputs (P1B and P1D) are placed cycle. In this example, at time t1, the output P1A and in their inactive state. P1D become inactive, while output P1C becomes • The associated unmodulated outputs (P1A and active. Since the turn-off time of the power devices is P1C) are switched to drive in the opposite longer than the turn-on time, a shoot-through current direction. will flow through power devices QC and QD (see • PWM modulation resumes at the beginning of the Figure11-10) for the duration of ‘t’. The same next period. phenomenon will occur to power devices QA and QB See Figure11-12 for an illustration of this sequence. for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 11-12: EXAMPLE OF PWM DIRECTION CHANGE Signal Period(1) Period P1A (Active-High) P1B (Active-High) Pulse Width P1C (Active-High) (2) P1D (Active-High) Pulse Width Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is (1/Fosc)  TMR2 prescale value.  2005-2015 Microchip Technology Inc. DS40001262F-page 137

PIC16F631/677/685/687/689/690 FIGURE 11-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential T = TOFF – TON Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver. 11.4.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high- impedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). The CCP1M<1:0> bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enabled is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. DS40001262F-page 138  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 11.4.4 ENHANCED PWM AUTO- A shutdown condition is indicated by the ECCPASE SHUTDOWN MODE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating The PWM mode supports an Auto-Shutdown mode that normally. If the bit is a ‘1’, the PWM outputs are in the will disable the PWM outputs when an external shutdown state. shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This When a shutdown event occurs, two things happen: mode is used to help prevent the PWM from damaging The ECCPASE bit is set to ‘1’. The ECCPASE will the application. remain set until cleared in firmware or an auto-restart The auto-shutdown sources are selected using the occurs (see Section11.4.5 “Auto-Restart Mode”). ECCPASx bits of the ECCPAS register. A shutdown The enabled PWM pins are asynchronously placed in event may be generated by: their shutdown states. The PWM output pins are • A logic ‘0’ on the INT pin grouped into pairs [P1A/P1C] and [P1B/P1D]. The state of each pin pair is determined by the PSSAC and • Comparator C1 PSSBD bits of the ECCPAS register. Each pin pair may • Comparator C2 be placed into one of three states: • Setting the ECCPASE bit in firmware • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) FIGURE 11-14: AUTO-SHUTDOWN BLOCK DIAGRAM ECCPAS<2:0> PSSAC<0> 1 P1A_DRV 111 0 110 101 PSSAC<1> P1A 100 TRISx INT 011 From Comparator C2 010 PSSBD<0> 1 From Comparator C1 001 P1B_DRV 0 000 PRSEN PSSBD<1> R S P1B TRISx From Data Bus ECCPASE D Q Write to ECCPASE PSSAC<0> 1 P1C_DRV 0 PSSAC<1> P1C TRISx PSSBD<0> 1 P1D_DRV 0 PSSBD<1> P1D TRISx  2005-2015 Microchip Technology Inc. DS40001262F-page 139

PIC16F631/677/685/687/689/690 REGISTER 11-2: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits 000 =Auto-Shutdown is disabled 001 =Comparator C1 output high 010 =Comparator C2 output high(1) 011 =Either Comparators output is high 100 =VIL on INT pin 101 =VIL on INT pin or Comparator C1 output high 110 =VIL on INT pin or Comparator C2 output high 111 =VIL on INT pin or either Comparators output is high bit 3-2 PSSACn: Pins P1A and P1C Shutdown State Control bits 00 = Drive pins P1A and P1C to ‘0’ 01 = Drive pins P1A and P1C to ‘1’ 1x = Pins P1A and P1C tri-state bit 1-0 PSSBDn: Pins P1B and P1D Shutdown State Control bits 00 = Drive pins P1B and P1D to ‘0’ 01 = Drive pins P1B and P1D to ‘1’ 1x = Pins P1B and P1D tri-state Note 1: If C2SYNC is enabled, the shutdown will be delayed by Timer1. Note1: The auto-shutdown condition is a level- based signal, not an edge-based signal. As long as the level is present, the auto- shutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period. DS40001262F-page 140  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 11-15: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0) ShutdownEvent ECCPASE bit PWM Activity PWM Period ECCPASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes 11.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automati- cally restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register. If auto-restart is enabled, the ECCPASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPASE bit will be cleared via hardware and normal operation will resume. FIGURE 11-16: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) ShutdownEvent ECCPASE bit PWM Activity PWM Period Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes  2005-2015 Microchip Technology Inc. DS40001262F-page 141

PIC16F631/677/685/687/689/690 11.4.6 PROGRAMMABLE DEAD-BAND FIGURE 11-17: EXAMPLE OF HALF- DELAY MODE BRIDGE PWM OUTPUT In Half-Bridge applications where all power switches Period Period are modulated at the PWM frequency, the power Pulse Width switches normally require more time to turn off than to turn on. If both the upper and lower power switches are P1A(2) switched at the same time (one turned on, and the td other turned off), both switches may be on for a short td period of time until one switch completely turns off. P1B(2) During this brief interval, a very high current (shoot- through current) will flow through both power switches, (1) (1) (1) shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during td = Dead-Band Delay switching, turning on either of the power switches is normally delayed to allow the other switch to Note 1: At this time, the TMR2 register is equal to the completely turn off. PR2 register. In Half-Bridge mode, a digitally programmable dead- 2: Output signals are shown as active-high. band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure11-8 for illustration. The lower seven bits of the associated PWM1CON register (Register11-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 11-18: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A V - Load FET Driver + P1B V - V- DS40001262F-page 142  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 REGISTER 11-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits PDCn =Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active  2005-2015 Microchip Technology Inc. DS40001262F-page 143

PIC16F631/677/685/687/689/690 11.4.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the Note: The associated TRIS bits must be set to PWM pins to be the modulated signal. Additionally, the output (‘0’) to enable the pin output driver same PWM signal can be simultaneously available on in order to see the PWM signal on the pin. multiple pins. While the PWM Steering mode is active, CCP1M<1:0> Once the Single Output mode is selected bits of the CCP1CON register select the PWM output (CCP1M<3:2>=11 and P1M<1:0>=00 of the polarity for the P1<D:A> pins. CCP1CON register), the user firmware can bring out The PWM auto-shutdown operation also applies to the same PWM signal to one, two, three or four output PWM Steering mode as described in Section11.4.4 pins by setting the appropriate STR<D:A> bits of the “Enhanced PWM Auto-shutdown mode”. An auto- PSTRCON register, as shown in Figure11-19. shutdown event will only affect pins that have PWM outputs enabled. REGISTER 11-4: PSTRCON: PULSE STEERING CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRD: Steering Enable bit D 1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1D pin is assigned to port pin bit 2 STRC: Steering Enable bit C 1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1C pin is assigned to port pin bit 1 STRB: Steering Enable bit B 1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1B pin is assigned to port pin bit 0 STRA: Steering Enable bit A 1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2>=11 and P1M<1:0>=00. DS40001262F-page 144  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 11-19: SIMPLIFIED STEERING BLOCK DIAGRAM STRA P1A Signal P1A pin CCP1M1 1 PORT Data 0 TRIS STRB P1B pin CCP1M0 1 PORT Data 0 TRIS STRC P1C pin CCP1M1 1 PORT Data 0 TRIS STRD P1D pin CCP1M0 1 PORT Data 0 TRIS Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0>=00 and CCP1M<3:2>=11. 2: Single PWM output requires setting at least one of the STRx bits.  2005-2015 Microchip Technology Inc. DS40001262F-page 145

PIC16F631/677/685/687/689/690 11.4.7.1 Steering Synchronization Figures 11-20 and 11-21 illustrate the timing diagrams of the PWM steering depending on the STRSYNC The STRSYNC bit of the PSTRCON register gives the setting. user two selections of when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRCON register. In this case, the output signal at the P1<D:A> pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. When the STRSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. FIGURE 11-20: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0) PWM Period PWM STRn P1<D:A> PORT Data PORT Data P1n = PWM FIGURE 11-21: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) PWM STRn P1<D:A> PORT Data PORT Data P1n = PWM DS40001262F-page 146  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 11-5: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND PWM Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 CM2CON1 MC1OUT MC2OUT — — — — T1GSS C2SYNC 00-- --10 00-- --10 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 0000 0000 0000 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001 PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 0000 0000 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR2 Timer2 Module Register 0000 0000 0000 0000 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM.  2005-2015 Microchip Technology Inc. DS40001262F-page 147

PIC16F631/677/685/687/689/690 12.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer • Half-duplex synchronous master independent of device program execution. The • Half-duplex synchronous slave EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous Interface (SCI), can be configured as a full-duplex modes asynchronous system or half-duplex synchronous • Sleep operation system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT The EUSART module implements the following terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems: with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate circuits, serial EEPROMs or other microcontrollers. • Wake-up on Break reception These devices typically do not have internal clocks for • 13-bit Break character transmit baud rate generation and require the external clock signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and receiver are shown in Figure12-1 and Figure12-2. FIGURE 12-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREG Register TXIF 8 MSb LSb TX/CK pin (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT SPEN Baud Rate Generator FOSC ÷ n TX9 BRG16 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 X 0 0 0 SPBRGH SPBRG BRGH X 1 1 0 0 BRG16 X 1 0 1 0 DS40001262F-page 148  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 12-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN OERR RCIDL RX/DT pin MSb RSR Register LSb Panind BCuoffnetrrol DReactaovery Stop (8) 7 • • • 1 0 START Baud Rate Generator FOSC RX9 ÷ n BRG16 n + 1 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 FIFO SPBRGH SPBRG BRGH X 1 1 0 0 FERR RX9D RCREG Register BRG16 X 1 0 1 0 8 Data Bus RCIF Interrupt RCIE The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCTL) These registers are detailed in Register12-1, Register12-2 and Register12-3, respectively.  2005-2015 Microchip Technology Inc. DS40001262F-page 149

PIC16F631/677/685/687/689/690 12.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the Note 1: When the SPEN bit is set the RX/DT I/O standard non-return-to-zero (NRZ) format. NRZ is pin is automatically configured as an input, implemented with two levels: a VOH mark state which regardless of the state of the correspond- represents a ‘1’ data bit, and a VOL space state which ing TRIS bit and whether or not the represents a ‘0’ data bit. NRZ refers to the fact that EUSART receiver is enabled. The RX/DT consecutively transmitted data bits of the same value pin data can be read via a normal PORT stay at the output level of that bit without returning to a read but PORT latch data output is pre- neutral level between each bit transmission. An NRZ cluded. transmission port idles in the mark state. Each character 2: The TXIF transmitter interrupt flag is set transmission consists of one Start bit followed by eight when the TXEN enable bit is set. or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the 12.1.1.2 Transmitting Data Stop bits are always marks. The most common data A transmission is initiated by writing a character to the format is 8 bits. Each transmitted bit persists for a period TXREG register. If this is the first character, or the of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud previous character has been completely flushed from Rate Generator is used to derive standard baud rate the TSR, the data in the TXREG is immediately frequencies from the system oscillator. See Table12-5 transferred to the TSR register. If the TSR still contains for examples of baud rate configurations. all or part of a previous character, the new character The EUSART transmits and receives the LSb first. The data is held in the TXREG until the Stop bit of the EUSART’s transmitter and receiver are functionally previous character has been transmitted. The pending independent, but share the same data format and baud character in the TXREG is then transferred to the TSR rate. Parity is not supported by the hardware, but can in one TCY immediately following the Stop bit be implemented in software and stored as the ninth transmission. The transmission of the Start bit, data bits data bit. and Stop bit sequence commences immediately following the transfer of the data to the TSR from the 12.1.1 EUSART ASYNCHRONOUS TXREG. TRANSMITTER 12.1.1.3 Transmit Interrupt Flag The EUSART transmitter block diagram is shown in Figure12-1. The heart of the transmitter is the serial The TXIF interrupt flag bit of the PIR1 register is set Transmit Shift Register (TSR), which is not directly whenever the EUSART transmitter is enabled and no accessible by software. The TSR obtains its data from character is being held for transmission in the TXREG. the transmit buffer, which is the TXREG register. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been 12.1.1.1 Enabling the Transmitter queued for transmission in the TXREG. The TXIF flag bit The EUSART transmitter is enabled for asynchronous is not cleared immediately upon writing TXREG. TXIF operations by configuring the following three control becomes valid in the second instruction cycle following bits: the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit • TXEN = 1 is read-only, it cannot be set or cleared by software. • SYNC = 0 The TXIF interrupt can be enabled by setting the TXIE • SPEN = 1 interrupt enable bit of the PIE1 register. However, the All other EUSART control bits are assumed to be in TXIF flag bit will be set whenever the TXREG is empty, their default state. regardless of the state of TXIE enable bit. Setting the TXEN bit of the TXSTA register enables the To use interrupts when transmitting data, set the TXIE transmitter circuitry of the EUSART. Clearing the SYNC bit only when there is more data to send. Clear the bit of the TXSTA register configures the EUSART for TXIE interrupt enable bit upon writing the last character asynchronous operation. Setting the SPEN bit of the of the transmission to the TXREG. RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. DS40001262F-page 150  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 12.1.1.4 TSR Status 12.1.1.6 Asynchronous Transmission Set-up: The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRG register pair and status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired TRMT bit is set when the TSR register is empty and is baud rate (see Section12.3 “EUSART Baud cleared when a character is transferred to the TSR Rate Generator (BRG)”). register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit. No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 con- poll this bit to determine the TSR status. trol bit. A set ninth data bit will indicate that the Note: The TSR register is not mapped in data eight Least Significant data bits are an address memory, so it is not available to the user. when the receiver is set for address detection. 4. Enable the transmission by setting the TXEN 12.1.1.5 Transmitting 9-Bit Characters control bit. This will cause the TXIF interrupt bit The EUSART supports 9-bit character transmissions. to be set. When the TX9 bit of the TXSTA register is set the 5. If interrupts are desired, set the TXIE interrupt EUSART will shift nine bits out for each character trans- enable bit of the PIE1 register. An interrupt will mitted. The TX9D bit of the TXSTA register is the ninth, occur immediately provided that the GIE and and Most Significant, data bit. When transmitting 9-bit PEIE bits of the INTCON register are also set. data, the TX9D data bit must be written before writing 6. If 9-bit transmission is selected, the ninth bit the eight Least Significant bits into the TXREG. All nine should be loaded into the TX9D data bit. bits of data will be transferred to the TSR shift register 7. Load 8-bit data into the TXREG register. This immediately after the TXREG is written. will start the transmission. A special 9-bit Address mode is available for use with multiple receivers. See Section12.1.2.7 “Address Detection” for more information on the Address mode. FIGURE 12-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 12-4: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Transmit Buffer Reg. Empty Flag) 1 TCY TRMT bit Word 1 Word 2 (Transmit Shift Transmit Shift Reg Transmit Shift Reg Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions.  2005-2015 Microchip Technology Inc. DS40001262F-page 151

PIC16F631/677/685/687/689/690 TABLE 12-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 RCREG EUSART Receive Data Register 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ---- TXREG EUSART Transmit Data Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission. DS40001262F-page 152  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 12.1.2 EUSART ASYNCHRONOUS 12.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit, systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data Figure12-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts the baud rate, whereas the serial Receive Shift character reception, without generating an error, and Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data are immediately transferred to a two character First-In- recovery circuit counts a full bit time to the center of the First-Out (FIFO) memory. The FIFO buffering allows next bit. The bit is then sampled by a majority detect reception of two complete characters and the start of a circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. third character before software must start servicing the This repeats until all data bits have been sampled and EUSART receiver. The FIFO and RSR registers are not shifted into the RSR. One final bit time is measured and directly accessible by software. Access to the received the level sampled. This is the Stop bit, which is always data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this 12.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this character. See Section12.1.2.4 “Receive Framing The EUSART receiver is enabled for asynchronous Error” for more information on framing errors. operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have • CREN = 1 been received, the character in the RSR is transferred • SYNC = 0 to the EUSART receive FIFO and the RCIF interrupt • SPEN = 1 flag bit of the PIR1 register is set. The top character in All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the their default state. RCREG register. Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun of the TXSTA register configures the EUSART for condition is cleared. See Section12.1.2.5 asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more RCSTA register enables the EUSART and automatically information on overrun errors. configures the RX/DT I/O pin as an input. If the RX/DT pin is shared with an analog peripheral the analog I/O 12.1.2.3 Receive Interrupts function must be disabled by clearing the corresponding The RCIF interrupt flag bit of the PIR1 register is set ANSEL bit. whenever the EUSART receiver is enabled and there is Note: When the SPEN bit is set the TX/CK I/O an unread character in the receive FIFO. The RCIF pin is automatically configured as an interrupt flag bit is read-only, it cannot be set or cleared output, regardless of the state of the by software. corresponding TRIS bit and whether or RCIF interrupts are enabled by setting all of the not the EUSART transmitter is enabled. following bits: The PORT latch is disconnected from the • RCIE interrupt enable bit of the PIE1 register output driver so it is not possible to use the • PEIE peripheral interrupt enable bit of the TX/CK pin as a general purpose output. INTCON register • GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.  2005-2015 Microchip Technology Inc. DS40001262F-page 153

PIC16F631/677/685/687/689/690 12.1.2.4 Receive Framing Error 12.1.2.7 Address Detection Each character in the receive FIFO buffer has a A special Address Detection mode is available for use corresponding framing error Status bit. A framing error when multiple receivers share the same transmission indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA FERR bit of the RCSTA register. The FERR bit register. represents the status of the top unread character in the Address detection requires 9-bit character reception. receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters before reading the RCREG. with the ninth data bit set will be transferred to the The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt unread character in the receive FIFO. A framing error bit. All other characters will be ignored. (FERR = 1) does not preclude reception of additional Upon receiving an address character, user software characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon Reading the next character from the FIFO buffer will address match, user software must disable address advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next corresponding framing error. Stop bit occurs. When user software detects the end of The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit. affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. 12.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated If a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 12.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG. DS40001262F-page 154  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 12.1.2.8 Asynchronous Reception Set-up: 12.1.2.9 9-bit Address Detection Mode Set-up 1. Initialize the SPBRGH, SPBRG register pair and This mode would typically be used in RS-485 systems. the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section12.3 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRG register pair and 2. Enable the serial port by setting the SPEN bit. the BRGH and BRG16 bits to achieve the The SYNC bit must be clear for asynchronous desired baud rate (see Section12.3 “EUSART operation. Baud Rate Generator (BRG)”). 3. If interrupts are desired, set the RCIE bit of the 2. Enable the serial port by setting the SPEN bit. PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous INTCON register. operation. 4. If 9-bit reception is desired, set the RX9 bit. 3. If interrupts are desired, set the RCIE bit of the 5. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the 6. The RCIF interrupt flag bit will be set when a INTCON register. character is transferred from the RSR to the 4. Enable 9-bit reception by setting the RX9 bit. receive buffer. An interrupt will be generated if 5. Enable address detection by setting the ADDEN the RCIE interrupt enable bit was also set. bit. 7. Read the RCSTA register to get the error flags 6. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 7. The RCIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 8. Get the received 8 Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit register. was also set. 9. If an overrun occurred, clear the OERR flag by 8. Read the RCSTA register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. FIGURE 12-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 RCREG RCREG RCIDL Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.  2005-2015 Microchip Technology Inc. DS40001262F-page 155

PIC16F631/677/685/687/689/690 TABLE 12-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 RCREG EUSART Receive Data Register 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ---- TXREG EUSART Transmit Data Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception. DS40001262F-page 156  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 12.2 Clock Accuracy with The first (preferred) method uses the OSCTUNE Asynchronous Operation register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution The factory calibrates the internal oscillator block out- changes to the system clock source. See Section3.5 put (INTOSC). However, the INTOSC frequency may “Internal Clock Modes” for more information. drift as VDD or temperature changes, and this directly The other method adjusts the value in the Baud Rate affects the asynchronous baud rate. Two methods may Generator. This can be done automatically with the be used to adjust the baud rate clock, but both require Auto-Baud Detect feature (see Section12.3.1 “Auto- a reference clock source of some kind. Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. REGISTER 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2005-2015 Microchip Technology Inc. DS40001262F-page 157

PIC16F631/677/685/687/689/690 REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001262F-page 158  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 REGISTER 12-3: BAUDCTL: BAUD RATE CONTROL REGISTER R-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the RB7/TX/CK pin 0 = Transmit non-inverted data to the RB7/TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2005-2015 Microchip Technology Inc. DS40001262F-page 159

PIC16F631/677/685/687/689/690 12.3 EUSART Baud Rate Generator If the system clock is changed during an active receive (BRG) operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to The Baud Rate Generator (BRG) is an 8-bit or 16-bit make sure that the receive operation is Idle before timer that is dedicated to the support of both the changing the system clock. asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the EXAMPLE 12-1: CALCULATING BAUD BRG16 bit of the BAUDCTL register selects 16-bit RATE ERROR mode. For a device with FOSC of 16 MHz, desired baud rate The SPBRGH, SPBRG register pair determines the of 9600, Asynchronous mode, 8-bit BRG: period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate Desired Baud Rate = ----------------------------F----O----S---C------------------------------ 64[SPBRGH:SPBRG]+1 period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCTL register. In Solving for SPBRGH:SPBRG: Synchronous mode, the BRGH bit is ignored. FOSC --------------------------------------------- Table12-3 contains the formulas for determining the Desired Baud Rate X = ---------------------------------------------–1 baud rate. Example12-1 provides a sample calculation 64 for determining the baud rate and baud rate error. 16000000 ------------------------ Typical baud rates and error values for various 9600 = ------------------------–1 asynchronous modes have been computed for your 64 convenience and are shown in Table12-3. It may be = 25.042 = 25 decimal advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate Calculated Baud Rate = --1---6---0---0---0---0---0---0---- 6425+1 error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. = 9615 Writing a new value to the SPBRGH, SPBRG register Calc. Baud Rate–Desired Baud Rate pair causes the BRG timer to be reset (or cleared). This Error = -------------------------------------------------------------------------------------------- Desired Baud Rate ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. 9615–9600 = ---------------------------------- = 0.16% 9600 TABLE 12-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH, SPBRG register pair TABLE 12-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator. DS40001262F-page 160  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 1202 0.16 103 2400 2404 0.16 129 2400 0.00 119 2400 0.00 71 2404 0.16 51 9600 9470 -1.36 32 9600 0.00 29 9600 0.00 17 9615 0.16 12 10417 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 10417 0.00 11 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 — — — 57.6k — — — 57.60k 0.00 7 57.60k 0.00 2 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300 0.16 207 300 0.00 191 300 0.16 103 300 0.16 51 1200 1202 0.16 51 1200 0.00 47 1202 0.16 25 1202 0.16 12 2400 2404 0.16 25 2400 0.00 23 2404 0.16 12 — — — 9600 — — — 9600 0.00 5 — — — — — — 10417 10417 0.00 5 — — — 10417 0.00 2 — — — 19.2k — — — 19.20k 0.00 2 — — — — — — 57.6k — — — 57.60k 0.00 0 — — — — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — 2404 0.16 207 9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51 10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19231 0.16 25 57.6k 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8 115.2k 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —  2005-2015 Microchip Technology Inc. DS40001262F-page 161

PIC16F631/677/685/687/689/690 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51 2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25 9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — — 10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5 19.2k 19.23k 0.16 12 19.2k 0.00 11 — — — — — — 57.6k — — — 57.60k 0.00 3 — — — — — — 115.2k — — — 115.2k 0.00 1 — — — — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 299.9 -0.02 1666 1200 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 1199 -0.08 416 2400 2399 -0.03 520 2400 0.00 479 2400 0.00 287 2404 0.16 207 9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51 10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19.23k 0.16 25 57.6k 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8 115.2k 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.1 0.04 832 300.0 0.00 767 299.8 -0.108 416 300.5 0.16 207 1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51 2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25 9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — — 10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5 19.2k 19.23k 0.16 12 19.20k 0.00 11 — — — — — — 57.6k — — — 57.60k 0.00 3 — — — — — — 115.2k — — — 115.2k 0.00 1 — — — — — — DS40001262F-page 162  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 300.0 0.00 6666 1200 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 1200 -0.02 1666 2400 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 2401 0.04 832 9600 9597 -0.03 520 9600 0.00 479 9600 0.00 287 9615 0.16 207 10417 10417 0.00 479 10425 0.08 441 10433 0.16 264 10417 0 191 19.2k 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 19.23k 0.16 103 57.6k 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 57.14k -0.79 34 115.2k 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 117.6k 2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.01 3332 300.0 0.00 3071 299.9 -0.02 1666 300.1 0.04 832 1200 1200 0.04 832 1200 0.00 767 1199 -0.08 416 1202 0.16 207 2400 2398 0.08 416 2400 0.00 383 2404 0.16 207 2404 0.16 103 9600 9615 0.16 103 9600 0.00 95 9615 0.16 51 9615 0.16 25 10417 10417 0.00 95 10473 0.53 87 10417 0.00 47 10417 0.00 23 19.2k 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 25 19.23k 0.16 12 57.6k 58.82k 2.12 16 57.60k 0.00 15 55.56k -3.55 8 — — — 115.2k 111.1k -3.55 8 115.2k 0.00 7 — — — — — —  2005-2015 Microchip Technology Inc. DS40001262F-page 163

PIC16F631/677/685/687/689/690 12.3.1 AUTO-BAUD DETECT and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. Note1: If the WUE bit is set with the ABDEN bit, In the Auto-Baud Detect (ABD) mode, the clock to the auto-baud detection will occur on the byte BRG is reversed. Rather than the BRG clocking the following the Break character (see incoming RX signal, the RX signal is timing the BRG. Section12.3.2 “Auto-Wake-up on The Baud Rate Generator is used to time the period of Break”). a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the that it has five rising edges including the Stop bit edge. incoming character baud rate is within the range of the selected BRG clock source. Setting the ABDEN bit of the BAUDCTL register starts Some combinations of oscillator frequency the auto-baud calibration sequence (Figure12-6). and EUSART baud rates are not possible. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of 3: During the auto-baud process, the auto- the receive line, after the Start bit, the SPBRG begins baud counter starts counting at 1. Upon counting up using the BRG counter clock as shown in completion of the auto-baud sequence, to Table12-6. The fifth rising edge will occur on the RX pin achieve maximum accuracy, subtract 1 at the end of the eighth bit period. At that time, an from the SPBRGH:SPBRG register pair. accumulated value totaling the proper BRG period is left in the SPBRGH, SPBRG register pair, the ABDEN TABLE 12-6: BRG COUNTER CLOCK RATES bit is automatically cleared and the RCIF interrupt flag BRG Base BRG ABD is set. The value in the RCREG needs to be read to BRG16 BRGH Clock Clock clear the RCIF interrupt. RCREG content should be discarded. When calibrating for modes that do not use 0 0 FOSC/64 FOSC/512 the SPBRGH register the user can verify that the 0 1 FOSC/16 FOSC/128 SPBRG register did not overflow by checking for 00h in the SPBRGH register. 1 0 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 1 1 FOSC/4 FOSC/32 and BRGH bits as shown in Table12-6. During ABD, Note: During the ABD sequence, SPBRG and both the SPBRGH and SPBRG registers are used as a SPBRGH registers are both used as a 16-bit 16-bit counter, independent of the BRG16 bit setting. counter, independent of BRG16 setting. While calibrating the baud rate period, the SPBRGH FIGURE 12-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRG XXh 1Ch SPBRGH XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode DS40001262F-page 164  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 12.3.2 AUTO-WAKE-UP ON BREAK 12.3.2.1 Special Considerations During Sleep mode, all clocks to the EUSART are Break Character suspended. Because of this, the Baud Rate Generator To avoid character errors or character fragments during is inactive and a proper character reception cannot be a wake-up event, the wake-up character must be all performed. The Auto-Wake-up feature allows the zeros. controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. When the wake-up is enabled the function works independent of the low time on the data stream. If the The Auto-Wake-up feature is enabled by setting the WUE bit is set and a valid non-zero character is WUE bit of the BAUDCTL register. Once set, the normal received, the low time from the Start bit to the first rising receive sequence on RX/DT is disabled, and the edge will be interpreted as the wake-up event. The EUSART remains in an Idle state, monitoring for a wake- remaining bits in the character will be received as a up event independent of the CPU mode. A wake-up fragmented character and subsequent characters can event consists of a high-to-low transition on the RX/DT result in framing or overrun errors. line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) Therefore, the initial character in the transmission must be all ‘0’s. This must be ten or more bit times, 13-bit The EUSART module generates an RCIF interrupt times recommended for LIN bus, or any number of bit coincident with the wake-up event. The interrupt is times for standard RS-232 devices. generated synchronously to the Q clocks in normal CPU operating modes (Figure12-7), and asynchronously if Oscillator Startup Time the device is in Sleep mode (Figure12-8). The interrupt Oscillator start-up time must be considered, especially condition is cleared by reading the RCREG register. in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync The WUE bit is automatically cleared by the low-to-high Break (or wake-up signal) character must be of transition on the RX line at the end of the Break. This sufficient length, and be followed by a sufficient signals to the user that the Break event is over. At this interval, to allow enough time for the selected oscillator point, the EUSART module is in Idle mode waiting to to start and provide proper initialization of the EUSART. receive the next character. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. FIGURE 12-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set.  2005-2015 Microchip Technology Inc. DS40001262F-page 165

PIC16F631/677/685/687/689/690 FIGURE 12-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RX/DT Line Note 1 RCIF Cleared due to User Read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. 12.3.3 BREAK CHARACTER SEQUENCE 12.3.4 RECEIVING A BREAK CHARACTER The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break special Break character sequences that are required by character in two ways. the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the Received data To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is bits of the TXSTA register. The Break character trans- assumed to have been initialized to the expected baud mission is then initiated by a write to the TXREG. The rate. value of data written to TXREG will be ignored and all A Break character has been received when; ‘0’s will be transmitted. • RCIF bit is set The SENDB bit is automatically reset by hardware after • FERR bit is set the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte • RCREG = 00h following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature character in the LIN specification). described in Section12.3.2 “Auto-Wake-up on The TRMT bit of the TXSTA register indicates when the Break”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an transmit operation is active or Idle, just as it does during RCIF interrupt, and receive the next data byte followed normal transmission. See Figure12-9 for the timing of by another interrupt. the Break character sequence. Note that following a Break character, the user will 12.3.3.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature. The following sequence will start a message frame For both methods, the user can set the ABDEN bit of header made up of a Break, followed by an auto-baud the BAUDCTL register before placing the EUSART in Sync byte. This sequence is typical of a LIN bus Sleep mode. master. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to enable the Break sequence. 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. DS40001262F-page 166  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 12-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit)  2005-2015 Microchip Technology Inc. DS40001262F-page 167

PIC16F631/677/685/687/689/690 12.4 EUSART Synchronous Mode 12.4.1.2 Clock Polarity Synchronous serial communications are typically used A clock polarity option is provided for Microwire in systems with a single master and one or more compatibility. Clock polarity is selected with the SCKP slaves. The master device contains the necessary bit of the BAUDCTL register. Setting the SCKP bit sets circuitry for baud rate generation and supplies the clock the clock Idle state as high. When the SCKP bit is set, for all devices in the system. Slave devices can take the data changes on the falling edge of each clock. advantage of the master clock by eliminating the Clearing the SCKP bit sets the Idle state as low. When internal clock generation circuitry. the SCKP bit is cleared, the data changes on the rising edge of each clock. There are two signal lines in Synchronous mode: a bidi- rectional data line and a clock line. Slaves use the 12.4.1.3 Synchronous Master Transmission external clock supplied by the master to shift the serial Data is transferred out of the device on the RX/DT pin. data into and out of their respective receive and trans- The RX/DT and TX/CK pin output drivers are automat- mit shift registers. Since the data line is bidirectional, ically enabled when the EUSART is configured for synchronous operation is half-duplex only. Half-duplex synchronous master transmit operation. refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. A transmission is initiated by writing a character to the The EUSART can operate as either a master or slave TXREG register. If the TSR still contains all or part of a device. previous character the new character data is held in the TXREG until the last bit of the previous character has Start and Stop bits are not used in synchronous been transmitted. If this is the first character, or the pre- transmissions. vious character has been completely flushed from the 12.4.1 SYNCHRONOUS MASTER MODE TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character com- The following bits are used to configure the EUSART mences immediately following the transfer of the data for Synchronous Master operation: to the TSR from the TXREG. • SYNC = 1 Each data bit changes on the leading edge of the • CSRC = 1 master clock and remains valid until the subsequent • SREN = 0 (for transmit); SREN = 1 (for receive) leading clock edge. • CREN = 0 (for transmit); CREN = 1 (for receive) Note: The TSR register is not mapped in data • SPEN = 1 memory, so it is not available to the user. Setting the SYNC bit of the TXSTA register configures 12.4.1.4 Synchronous Master Transmission the device for synchronous operation. Setting the CSRC Set-up: bit of the TXSTA register configures the device as a mas- ter. Clearing the SREN and CREN bits of the RCSTA reg- 1. Initialize the SPBRGH, SPBRG register pair and ister ensures that the device is in the Transmit mode, the BRGH and BRG16 bits to achieve the otherwise the device will be configured to receive. Setting desired baud rate (see Section12.3 “EUSART the SPEN bit of the RCSTA register enables the Baud Rate Generator (BRG)”). EUSART. If the RX/DT or TX/CK pins are shared with an 2. Enable the synchronous master serial port by analog peripheral the analog I/O functions must be setting bits SYNC, SPEN, and CSRC. disabled by clearing the corresponding ANSEL bits. 3. Disable Receive mode by clearing bits SREN and CREN. 12.4.1.1 Master Clock 4. Enable Transmit mode by setting the TXEN bit. Synchronous data transfers use a separate clock line, 5. If 9-bit transmission is desired, set the TX9 bit. which is synchronous with the data. A device config- ured as a master transmits the clock on the TX/CK line. 6. If interrupts are desired, set the TXIE bit of the The TX/CK pin output driver is automatically enabled PIE1 register and the GIE and PEIE bits of the when the EUSART is configured for synchronous INTCON register. transmit or receive operation. Serial data bits change 7. If 9-bit transmission is selected, the ninth bit on the leading edge to ensure they are valid at the trail- should be loaded in the TX9D bit. ing edge of each clock. One clock cycle is generated 8. Start transmission by loading data to the TXREG for each data bit. Only as many clock cycles are register. generated as there are data bits. DS40001262F-page 168  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 12-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. FIGURE 12-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 12-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 RCREG EUSART Receive Data Register 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ---- TXREG EUSART Transmit Data Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.  2005-2015 Microchip Technology Inc. DS40001262F-page 169

PIC16F631/677/685/687/689/690 12.4.1.5 Synchronous Master Reception set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the Data is received at the RX/DT pin. The RX/DT pin SPEN bit which resets the EUSART. output driver is automatically disabled when the EUSART is configured for synchronous master receive 12.4.1.8 Receiving 9-bit Characters operation. The EUSART supports 9-bit character reception. When In Synchronous mode, reception is enabled by setting the RX9 bit of the RCSTA register is set the EUSART either the Single Receive Enable bit (SREN of the will shift 9-bits into the RSR for each character RCSTA register) or the Continuous Receive Enable bit received. The RX9D bit of the RCSTA register is the (CREN of the RCSTA register). ninth, and Most Significant, data bit of the top unread When SREN is set and CREN is clear, only as many character in the receive FIFO. When reading 9-bit data clock cycles are generated as there are data bits in a from the receive FIFO buffer, the RX9D data bit must single character. The SREN bit is automatically cleared be read before reading the eight Least Significant bits at the completion of one character. When CREN is set, from the RCREG. clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character 12.4.1.9 Synchronous Master Reception Set- the CK clock stops immediately and the partial charac- up: ter is discarded. If SREN and CREN are both set, then 1. Initialize the SPBRGH, SPBRG register pair for SREN is cleared at the completion of the first character the appropriate baud rate. Set or clear the and CREN takes precedence. BRGH and BRG16 bits, as required, to achieve To initiate reception, set either SREN or CREN. Data is the desired baud rate. sampled at the RX/DT pin on the trailing edge of the 2. Enable the synchronous master serial port by TX/CK clock pin and is shifted into the Receive Shift setting bits SYNC, SPEN and CSRC. Register (RSR). When a complete character is 3. Ensure bits CREN and SREN are clear. received into the RSR, the RCIF bit is set and the char- 4. If interrupts are desired, set the RCIE bit of the acter is automatically transferred to the two character PIE1 register and the GIE and PEIE bits of the receive FIFO. The Least Significant eight bits of the top INTCON register. character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are un-read 5. If 9-bit reception is desired, set bit RX9. characters in the receive FIFO. 6. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 12.4.1.6 Slave Clock 7. Interrupt flag bit RCIF will be set when reception Synchronous data transfers use a separate clock line, of a character is complete. An interrupt will be which is synchronous with the data. A device configured generated if the enable bit RCIE was set. as a slave receives the clock on the TX/CK line. The TX/ 8. Read the RCSTA register to get the ninth bit (if CK pin output driver is automatically disabled when the enabled) and determine if any error occurred device is configured for synchronous slave transmit or during reception. receive operation. Serial data bits change on the leading 9. Read the 8-bit received data by reading the edge to ensure they are valid at the trailing edge of each RCREG register. clock. One data bit is transferred for each clock cycle. 10. If an overrun error occurs, clear the error by Only as many clock cycles should be received as there either clearing the CREN bit of the RCSTA are data bits. register or by clearing the SPEN bit which resets the EUSART. 12.4.1.7 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is DS40001262F-page 170  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 12-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 RCREG EUSART Receive Data Register 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ---- TXREG EUSART Transmit Data Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.  2005-2015 Microchip Technology Inc. DS40001262F-page 171

PIC16F631/677/685/687/689/690 12.4.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the EUSART for Synchronous slave operation: 1. The first character will immediately transfer to the TSR register and transmit. • SYNC = 1 2. The second word will remain in TXREG register. • CSRC = 0 3. The TXIF bit will not be set. • SREN = 0 (for transmit); SREN = 1 (for receive) 4. After the first character has been shifted out of • CREN = 0 (for transmit); CREN = 1 (for receive) TSR, the TXREG register will transfer the second • SPEN = 1 character to the TSR and the TXIF bit will now be Setting the SYNC bit of the TXSTA register configures the set. device for synchronous operation. Clearing the CSRC bit 5. If the PEIE and TXIE bits are set, the interrupt of the TXSTA register configures the device as a slave. will wake the device from Sleep and execute the Clearing the SREN and CREN bits of the RCSTA register next instruction. If the GIE bit is also set, the ensures that the device is in the Transmit mode, program will call the Interrupt Service Routine. otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the 12.4.2.2 Synchronous Slave Transmission EUSART. If the RX/DT or TX/CK pins are shared with an Set-up: analog peripheral the analog I/O functions must be 1. Set the SYNC and SPEN bits and clear the disabled by clearing the corresponding ANSEL bits. CSRC bit. 12.4.2.1 EUSART Synchronous Slave 2. Clear the CREN and SREN bits. Transmit 3. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the The operation of the Synchronous Master and Slave INTCON register. modes are identical (see Section12.4.1.3 4. If 9-bit transmission is desired, set the TX9 bit. “Synchronous Master Transmission”), except in the case of the Sleep mode. 5. Enable transmission by setting the TXEN bit. 6. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 7. Start transmission by writing the Least Significant eight bits to the TXREG register. TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 RCREG EUSART Receive Data Register 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ---- TXREG EUSART Transmit Data Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. DS40001262F-page 172  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 12.4.2.3 EUSART Synchronous Slave 12.4.2.4 Synchronous Slave Reception Set- Reception up: The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the modes is identical (Section12.4.1.5 “Synchronous CSRC bit. Master Reception”), with the following exceptions: 2. If interrupts are desired, set the RCIE bit of the • Sleep PIE1 register and the GIE and PEIE bits of the INTCON register. • CREN bit is always set, therefore the receiver is never Idle 3. If 9-bit reception is desired, set the RX9 bit. • SREN bit, which is a “don’t care” in Slave mode 4. Set the CREN bit to enable reception. 5. The RCIF bit will be set when reception is A character may be received while in Sleep mode by complete. An interrupt will be generated if the setting the CREN bit prior to entering Sleep. Once the RCIE bit was set. word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the 6. If 9-bit mode is enabled, retrieve the Most interrupt generated will wake the device from Sleep Significant bit from the RX9D bit of the RCSTA and execute the next instruction. If the GIE bit is also register. set, the program will branch to the interrupt vector. 7. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. 8. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 RCREG EUSART Receive Data Register 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000 TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ---- TXREG EUSART Transmit Data Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.  2005-2015 Microchip Technology Inc. DS40001262F-page 173

PIC16F631/677/685/687/689/690 12.5 EUSART Operation During Sleep 12.5.2 SYNCHRONOUS TRANSMIT DURING SLEEP The EUSART WILL remain active during Sleep only in the Synchronous Slave mode. All other modes require To transmit during Sleep, all the following conditions the system clock and therefore cannot generate the must be met before entering Sleep mode: necessary signals to run the Transmit or Receive Shift • RCSTA and TXSTA Control registers must be registers during Sleep. configured for Synchronous Slave Transmission Synchronous Slave mode uses an externally generated (see Section12.4.2.2 “Synchronous Slave clock to run the Transmit and Receive Shift registers. Transmission Set-up:”). • The TXIF interrupt flag must be cleared by writing 12.5.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the SLEEP TSR and transmit buffer. To receive during Sleep, all the following conditions 9. If interrupts are desired, set the TXIE bit of the must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON register. • RCSTA and TXSTA Control registers must be • Interrupt enable bits TXIE of the PIE1 register and configured for Synchronous Slave Reception (see PEIE of the INTCON register must set. Section12.4.2.4 “Synchronous Slave Reception Set-up:”). Upon entering Sleep mode, the device will be ready to • If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the PIE1 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been INTCON register. completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and • The RCIF interrupt flag must be cleared by read- the TXIF flag will be set. Thereby, waking the processor ing RCREG to unload any pending characters in from Sleep. At this point, the TXREG is available to the receive buffer. accept another character for transmission, which will Upon entering Sleep mode, the device will be ready to clear the TXIF flag. accept data and clocks on the RX/DT and TX/CK pins, Upon waking from Sleep, the instruction following the respectively. When the data word has been completely SLEEP instruction will be executed. If the GIE Global clocked in by the external device, the RCIF interrupt Interrupt Enable bit is also set then the Interrupt flag bit of the PIR1 register will be set. Thereby, waking Service Routine at address 0004h will be called. the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE Global Interrupt Enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. DS40001262F-page 174  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 13.0 SSP MODULE OVERVIEW FIGURE 13-1: SSP BLOCK DIAGRAM (SPIMODE) The Synchronous Serial Port (SSP) module is a serial interface used to communicate with other peripheral or Internal microcontroller devices. These peripheral devices Data Bus may be serial EEPROMs, shift registers, display Read Write drivers, A/D converters, etc. The SSP module can operate in one of two modes: SSPBUF Reg • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) Refer to Application Note AN578, “Use of the SSP SSPSR Reg Module in the Multi-Master Environment” (DS00578). SDI/SDA bit 0 Shift Clock 13.1 SPI Mode SDO Peripheral OE This section contains register definitions and operational characteristics of the SPI module. The SPI mode allows eight bits of data to be SS Control Enable synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are SS Edge used: Select • Serial Data Out (SDO) 2 • Serial Data In (SDI) Clock Select • Serial Clock (SCK) SSPM<3:0> Additionally, a fourth pin may be used when in a Slave TMR2 Output mode of operation: 4 2 • Slave Select (SS) Edge Select Prescaler TCY Note1: When the SPI is in Slave mode with SS SCK/ 4, 16, 64 pin control enabled (SSPM<3:0> bits of SCL TRISB<6> the SSPCON register = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE=1, then the SS pin control must be enabled. 3: When the SPI is in Slave mode with SS pin control enabled (SSPM<3:0> bits of the SSPCON register = 0100), the state of the SS pin can affect the state read back from the TRISC<4> bit. The peripheral OE signal from the SSP module into PORTC controls the state that is read back from the TRISC<4> bit (see Section17.0 “Electrical Specifications” for information on PORTC). If read-write-modify instructions, such as BSF, are performed on the TRISC register while the SS pin is high, this will cause the TRISC<7> bit to be set, thus disabling the SDO output.  2005-2015 Microchip Technology Inc. DS40001262F-page 175

PIC16F631/677/685/687/689/690 REGISTER 13-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER(1) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I 2 C™ mode: This bit must be maintained clear bit 6 CKE: SPI Clock Edge Select bit SPI mode, CKP = 0: 1 = Data transmitted on rising edge of SCK (Microwire alternate) 0 = Data transmitted on falling edge of SCK SPI mode, CKP = 1: 1 = Data transmitted on falling edge of SCK (Microwire default) 0 = Data transmitted on rising edge of SCK I 2 C mode: This bit must be maintained clear bit 5 D/A: DATA/ADDRESS bit (I2C mode only)(2) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the Start bit is detected last. SSPEN is cleared. 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last. SSPEN is cleared. 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: READ/WRITE bit Information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or ACK bit. 1 = Read 0 = Write bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I 2 C mode only): 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty Note 1: PIC16F687/PIC16F689/PIC16F690 only. 2: Does not update if receive was ignored. DS40001262F-page 176  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 REGISTER 13-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new recep- tion (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I 2 C™ mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In SPI mode: 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level (Microwire default) 0 = Idle state for clock is a low level (Microwire alternate) In I 2 C mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = Reserved 1001 = Load SSPMSK register at SSPADD SFR address(2) 1010 = Reserved 1011 = I2C Firmware Controlled Master mode (slave IDLE) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: PIC16F687/PIC16F689/PIC16F690 only. 2: When this mode is selected, any reads or writes to the SSPADD SFR address actually accesses the SSPMSK register.  2005-2015 Microchip Technology Inc. DS40001262F-page 177

PIC16F631/677/685/687/689/690 13.2 Operation When the application software is expecting to receive valid data, the SSPBUF should be read before the next When initializing the SPI, several options need to be byte of data to transfer is written to the SSPBUF. Buffer specified. This is done by programming the appropriate Full bit BF of the SSPSTAT register indicates when control bits (SSPCON<5:0> and SSPSTAT<7:6>). SSPBUF has been loaded with the received data These control bits allow the following to be specified: (transmission is complete). When the SSPBUF is read, • Master mode (SCK is the clock output) the BF bit is cleared. This data may be irrelevant if the • Slave mode (SCK is the clock input) SPI is only a transmitter. Generally, the SSP interrupt is used to determine when the transmission/reception • Clock Polarity (Idle state of SCK) has completed. The SSPBUF must be read and/or • Data Input Sample Phase (middle or end of data written. If the interrupt method is not going to be used, output time) then software polling can be done to ensure that a write • Clock Edge (output data on rising/falling edge of collision does not occur. Example13-1 shows the SCK) loading of the SSPBUF (SSPSR) for data transmission. • Clock Rate (Master mode only) The SSPSR is not directly readable or writable and can • Slave Select mode (Slave mode only) only be accessed by addressing the SSPBUF register. The SSP consists of a transmit/receive shift register Additionally, the SSP Status register (SSPSTAT) (SSPSR) and a buffer register (SSPBUF). The SSPSR indicates the various status conditions. shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full Status bit BF of the SSPSTAT register, and the interrupt flag bit SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the Write Collision Detect bit, WCOL of the SSPCON register, will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. EXAMPLE 13-1: LOADING THE SSPBUF (SSPSR) REGISTER BSF STATUS,RP0 ;Bank 1 BCF STATUS,RP1 ; LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)? GOTO LOOP ;No BCF STATUS,RP0 ;Bank 0 MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS40001262F-page 178  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 13.3 Enabling SPI I/O 13.4 Typical Connection To enable the serial port, SSP Enable bit SSPEN of the Figure13-2 shows a typical connection between two SSPCON register must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1) SPI mode, clear the SSPEN bit, re-initialize the initiates the data transfer by sending the SCK signal. SSPCON registers and then set the SSPEN bit. This Data is shifted out of both shift registers on their configures the SDI, SDO, SCK and SS pins as serial programmed clock edge and latched on the opposite port pins. For the pins to behave as the serial port edge of the clock. Both processors should be function, some must have their data direction bits (in programmed to the same Clock Polarity (CKP), then the TRISB and TRISC registers) appropriately both controllers would send and receive data at the programmed. That is: same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads • SDI is automatically controlled by the SPI module to three scenarios for data transmission: • SDO must have TRISC<7> bit cleared • Master sends data–Slave sends dummy data • SCK (Master mode) must have TRISB<6> bit cleared • Master sends data–Slave sends data • SCK (Slave mode) must have TRISB<6> bit set • Master sends dummy data–Slave sends data • SS must have TRISC<6> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRISB and TRISC) registers to the opposite value. FIGURE 13-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK Processor 1 Processor 2  2005-2015 Microchip Technology Inc. DS40001262F-page 179

PIC16F631/677/685/687/689/690 13.5 Master Mode The clock polarity is selected by appropriately programming the CKP bit of the SSPCON register. This The master can initiate the data transfer at any time then, would give waveforms for SPI communication as because it controls the SCK. The master determines shown in Figure13-3, Figure13-5 and Figure13-6, when the slave (Processor 2, Figure13-2) is to where the MSB is transmitted first. In Master mode, the broadcast data by the software protocol. SPI clock rate (bit rate) is user programmable to be one In Master mode, the data is transmitted/received as of the following: soon as the SSPBUF register is written to. If the SPI is • FOSC/4 (or TCY) only going to receive, the SDO output could be • FOSC/16 (or 4 • TCY) disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the • FOSC/64 (or 16 • TCY) SDI pin at the programmed clock rate. As each byte is • Timer2 output/2 (No SSP module, PIC16F690 received, it will be loaded into the SSPBUF register as only) if a normal received byte (interrupts and Status bits Figure13-3 shows the waveforms for Master mode. appropriately set). This could be useful in receiver When the CKE bit is set, the SDO data is valid before applications as a Line Activity Monitor mode. there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 13-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF DS40001262F-page 180  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 13.6 Slave Mode even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/pull-down resistors In Slave mode, the data is transmitted and received as may be desirable, depending on the application. the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Note1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0>= While in Slave mode, the external clock is supplied by 0100), the SPI module will reset if the SS the external clock source on the SCK pin. This external pin is set to VDD. clock must meet the minimum high and low times as specified in the electrical specifications. 2: If the SPI is used in Slave Mode with CKE set, then the SS pin control must be While in Sleep mode, the slave can transmit/receive enabled. data. When a byte is received, the device will wake-up from Sleep. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to 13.7 Slave Select Synchronization a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can The SS pin allows a Synchronous Slave mode. The SPI be connected to the SDI pin. When the SPI needs to must be in Slave mode with SS pin control enabled operate as a receiver, the SDO pin can be configured (SSPCON<3:0> = 04h). The pin must not be driven low as an input. This disables transmissions from the SDO. for the SS pin to function as an input. The data latch The SDI can always be left as an input (SDI function) must be high. When the SS pin is low, transmission and since it cannot create a bus conflict. reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, FIGURE 13-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF  2005-2015 Microchip Technology Inc. DS40001262F-page 181

PIC16F631/677/685/687/689/690 FIGURE 13-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 13-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS40001262F-page 182  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 13.8 Sleep Operation 13.10 Bus Mode Compatibility In Master mode, all module clocks are halted and the Table13-1 shows the compatibility between the transmission/reception will remain in that state until the standard SPI modes and the states of the CKP and device wakes from Sleep. After the device returns to CKE control bits. Normal mode, the module will continue to transmit/ receive data. TABLE 13-1: SPI BUS MODES In Slave mode, the SPI Transmit/Receive Shift register Control Bits State Standard SPI Mode operates asynchronously to the device. This allows the Terminology device to be placed in Sleep mode and data to be CKP CKE shifted into the SPI Transmit/Receive Shift register. 0, 0 0 1 When all eight bits have been received, the SSP inter- 0, 1 0 0 rupt flag bit will be set and if enabled, will wake the device from Sleep. 1, 0 1 1 1, 1 1 0 13.9 Effects of a Reset There is also a SMP bit which controls when the data is A Reset disables the SSP module and terminates the sampled. current transfer. TABLE 13-2: REGISTERS ASSOCIATED WITH SPI OPERATION(1) Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh/8Bh/ INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x 10Bh/18Bh 0Ch PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 86h/186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- 87h/187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 8Ch PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode. Note 1: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.  2005-2015 Microchip Technology Inc. DS40001262F-page 183

PIC16F631/677/685/687/689/690 13.11 SSP I2C Operation The SSPCON register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) The SSP module in I2C mode, fully implements all slave allow one of the following I2C modes to be selected: functions, except general call support, and provides • I2C Slave mode (7-bit address) interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The • I2C Slave mode (10-bit address) SSP module implements the Standard mode • I2C Slave mode (7-bit address), with Start and specifications, as well as 7-bit and 10-bit addressing. Stop bit interrupts enabled to support Firmware Master mode Two pins are used for data transfer. These are the RB6/ SCK/SCL pin, which is the clock (SCL), and the RB4/ • I2C Slave mode (10-bit address), with Start and AN10/SDI/SDA pin, which is the data (SDA). Stop bit interrupts enabled to support Firmware Master mode The SSP module functions are enabled by setting SSP • I2C Start and Stop bit interrupts enabled to enable bit SSPEN (SSPCON<5>). support Firmware Master mode; Slave is idle FIGURE 13-7: SSP BLOCK DIAGRAM Selection of any I2C mode with the SSPEN bit set (I2C™ MODE) forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISB bits. Pull-up resistors Internal Data Bus must be provided externally to the SCL and SDA pins for proper operation of the I2C module. Read Write RB6/ SCK/ 13.12 Slave Mode SSPBUF Reg SCL In Slave mode, the SCL and SDA pins must be Shift configured as inputs (TRISB<6,4> are set). The SSP Clock module will override the input state with the output data SSPSR Reg when required (slave-transmitter). RB4/ MSb LSb When an address is matched, or the data transfer after AN10/ SDI/SDA an address match is received, the hardware Match Detect Addr Match automatically will generate the Acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. SSPMSK Reg There are certain conditions that will cause the SSP module not to give this ACK pulse. They include (either or both): SSPADD Reg a) The Buffer Full bit BF of the SSPSTAT register Start and Set, Reset was set before the transfer was received. Stop bit Detect S, P bits (SSPSTAT Reg) b) The overflow bit SSPOV of the SSPCON register was set before the transfer was received. The SSP module has six registers for the I2C operation, In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF of the PIR1 register is which are listed below. set. Table13-3 shows the results of when a data • SSP Control register (SSPCON) transfer byte is received, given the status of bits BF and • SSP Status register (SSPSTAT) SSPOV. The shaded cells show the condition where • Serial Receive/Transmit Buffer (SSPBUF) user software did not properly clear the overflow • SSP Shift register (SSPSR) – Not directly condition. Flag bit BF is cleared by reading the accessible SSPBUF register, while bit SSPOV is cleared through software. • SSP Address register (SSPADD) • SSP Mask register (SSPMSK) The SCL clock input must have a minimum high and low for proper operation. For high and low times of the I2C specification, as well as the requirements of the SSP module, see Section17.0 “Electrical Specifications”. DS40001262F-page 184  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 13.12.1 ADDRESSING The sequence of events for 10-bit address is as follows, with steps 7-9 for slave-transmitter: Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, 1. Receive first (high) byte of address (bits SSPIF, the eight bits are shifted into the SSPSR register. All BF and bit UA (SSPSTAT<1>) are set). incoming bits are sampled with the rising edge of the 2. Update the SSPADD register with second (low) clock (SCL) line. The value of register SSPSR<7:1> is byte of address (clears bit UA and releases the compared to the value of the SSPADD register. The SCL line). address is compared on the falling edge of the eighth 3. Read the SSPBUF register (clears bit BF) and clock (SCL) pulse. If the addresses match, and the BF clear flag bit SSPIF. and SSPOV bits are clear, the following events occur: 4. Receive second (low) byte of address (bits a) The SSPSR register value is loaded into the SSPIF, BF and UA are set). SSPBUF register. 5. Update the SSPADD register with the first (high) b) The buffer full bit, BF is set. byte of address; if match releases SCL line, this c) An ACK pulse is generated. will clear bit UA. d) SSP interrupt flag bit, SSPIF of the PIR1 register 6. Read the SSPBUF register (clears bit BF) and is set (interrupt is generated if enabled) on the clear flag bit SSPIF. falling edge of the ninth SCL pulse. 7. Receive repeated Start condition. In 10-bit Address mode, two address bytes need to be 8. Receive first (high) byte of address (bits SSPIF received by the slave (Figure13-8). The five Most and BF are set). Significant bits (MSbs) of the first address byte specify 9. Read the SSPBUF register (clears bit BF) and if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must clear flag bit SSPIF. specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. TABLE 13-3: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Set bit SSPIF Transfer is Received Generate ACK SSPSR SSPBUF (SSP Interrupt occurs Pulse if enabled) BF SSPOV 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.  2005-2015 Microchip Technology Inc. DS40001262F-page 185

PIC16F631/677/685/687/689/690 13.12.2 RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF of the SSPSTAT register is set, or bit SSPOV of the SSPCON register is set. This is an error condition due to the user’s firm- ware. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF of the PIR1 register must be cleared in software. The SSPSTAT register is used to determine the status of the byte. FIGURE 13-8: I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) R/W = 0 Receiving Address ACK Receiving Data ACK Receiving Data ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF (PIR1<3>) Cleared in software Bus Master terminates transfer BF (SSPSTAT<0>) SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. DS40001262F-page 186  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 13.12.3 SSP MASK REGISTER This register must be initiated prior to setting An SSP Mask (SSPMSK) register is available in I2C SSPM<3:0> bits to select the I2C Slave mode (7-bit or 10-bit address). Slave mode as a mask for the value held in the SSPSR register during an address comparison This register can only be accessed when the appropriate operation. A zero (‘0’) bit in the SSPMSK register has mode is selected by bits (SSPM<3:0> of SSPCON). the effect of making the corresponding bit in the The SSP Mask register is active during: SSPSR register a ‘don’t care’. • 7-bit Address mode: address compare of A<7:1>. This register is reset to all ‘1’s upon any Reset • 10-bit Address mode: address compare of A<7:0> condition and, therefore, has no effect on standard only. The SSP mask has no effect during the SSP operation until written with a mask value. reception of the first (high) byte of the address. REGISTER 13-3: SSPMSK: SSP MASK REGISTER(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address(2) I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111): 1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match Note1: When SSPCON bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK register. The SSPEN bit of the SSPCON register should be zero when accessing the SSPMSK register. 2: In all other SSP modes, this bit has no effect.  2005-2015 Microchip Technology Inc. DS40001262F-page 187

PIC16F631/677/685/687/689/690 FIGURE 13-9: I2C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS) ers nt. ACKACK 9P Bus mastterminatetransfer SSPOV is setbecause SSPBUF isstill full. ACK is not se 0 D 8 1 e D 7 ar eceive Data Byte D4D3D5D2 3456 Cleared in softw R 6 D 2 7 D 1 K C 9 A D0 8 gh d low untilSPADD has Receive Data Byte D4D2D5D3D1D6D7 1234576 Cleared in software Cleared by hardware whenSSPADD is updated with hibyte of address Clock is helClock is held low untilupdate of Supdate of SSPADD has taken placetaken placeFirst Byte of AddressR/W = Receive Second Byte of Address0ACKACKA8A6A5A4A9A7A3A2A100A011 8934578961234567 Cleared in softwareed in software SSPBUF is writtenDummy read of SSPBUFto clear BF flagwith contents of SSPSR >) UA is set indicatingCleared by hardwarethat the SSPADD needs towhen SSPADD is updatedbe updatedwith low byte of address UA is set indicatingthat SSPADD needs tobe updated es not reset to ‘’ when SEN = )00 Receive 11 12 Clear AT<0>) PCON<6 AT<1>) (CKP do SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST CKP DS40001262F-page 188  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 13.12.4 TRANSMISSION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and When the R/W bit of the incoming address byte is set the SSPSTAT register is used to determine the status and an address match occurs, the R/W bit of the of the byte. Flag bit SSPIF is set on the falling edge of SSPSTAT register is set. The received address is the ninth clock pulse. loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RB6/SCK/SCL is held As a slave-transmitter, the ACK pulse from the master low. The transmit data must be loaded into the receiver is latched on the rising edge of the ninth SCL SSPBUF register, which also loads the SSPSR input pulse. If the SDA line was high (not ACK), then register. Then, pin RB6/SCK/SCL should be enabled the data transfer is complete. When the ACK is latched by setting bit CKP (SSPCON<4>). The master must by the slave, the slave logic is reset (resets SSPSTAT monitor the SCL pin prior to asserting another clock register) and the slave then monitors for another pulse. The slave devices may be holding off the master occurrence of the Start bit. If the SDA line was low by stretching the clock. The eight data bits are shifted (ACK), the transmit data must be loaded into the out on the falling edge of the SCL input. This ensures SSPBUF register, which also loads the SSPSR that the SDA signal is valid during the SCL high time register. Then pin RB6/SCK/SCL should be enabled by (Figure13-10). setting bit CKP. FIGURE 13-10: I2C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address R/W = 1 Transmitting Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Data in SCL held low sampled while CPU responds to SSPIF SSPIF (PIR1<3>) Cleared in software BF (SSPSTAT<0>) From SSP Interrupt SSPBUF is written in software Service Routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set)  2005-2015 Microchip Technology Inc. DS40001262F-page 189

PIC16F631/677/685/687/689/690 FIGURE 13-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) ers nt. ACK 9P Bus mastterminatetransfer SSPOV is setbecause SSPBUF isstill full. ACK is not se 0 D 8 1 e D 7 ar eceive Data Byte D4D3D5D2 3465 Cleared in softw R 6 D 2 7 D 1 K C 9 A D0 8 gh d low untilSPADD has Receive Data Byte D5D4D3D1D2D6D7 1234576 Cleared in software Cleared by hardware whenSSPADD is updated with hibyte of address Clock is helClock is held low untilupdate of Supdate of SSPADD has taken placetaken placeR/W = 0Receive Second Byte of Addresseceive First Byte of AddressACKACKA8A6A4A9A7A5A3A2A100A01111 349125678123894567 Cleared in softwareCleared in software AT<0>) SSPBUF is writtenDummy read of SSPBUFto clear BF flagwith contents of SSPSR PCON<6>) AT<1>) UA is set indicatingCleared by hardwarethat the SSPADD needs towhen SSPADD is updatedbe updatedwith low byte of address UA is set indicatingthat SSPADD needs tobe updated (CKP does not reset to ‘’ when SEN = )00 R SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST CKP DS40001262F-page 190  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 13.13 Master Mode 13.14 Multi-Master Mode Master mode of operation is supported in firmware In Multi-Master mode, the interrupt generation on the using interrupt generation on the detection of the Start detection of the Start and Stop conditions, allows the and Stop conditions. The Stop (P) and Start (S) bits are determination of when the bus is free. The Stop (P) and cleared from a Reset or when the SSP module is Start (S) bits are cleared from a Reset or when the SSP disabled. The Stop (P) and Start (S) bits will toggle module is disabled. The Stop (P) and Start (S) bits will based on the Start and Stop conditions. Control of the toggle based on the Start and Stop conditions. Control I2C bus may be taken when the P bit is set or the bus of the I2C bus may be taken when bit P (SSPSTAT<4>) is idle and both the S and P bits are clear. is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will In Master mode, the SCL and SDA lines are generate the interrupt when the Stop condition occurs. manipulated by clearing the corresponding TRISB<6,4> bit(s). The output level is always low, In Multi-Master operation, the SDA line must be irrespective of the value(s) in PORTB<6,4>. So when monitored to see if the signal level is the expected transmitting data, a ‘1’ data bit must have the output level. This check only needs to be done when a TRISB<4> bit set (input) and a ‘0’ data bit must have high level is output. If a high level is expected and a low the TRISB<4> bit cleared (output). The same scenario level is present, the device needs to release the SDA is true for the SCL line with the TRISB<6> bit. Pull-up and SCL lines (set TRISB<6,4>). There are two stages resistors must be provided externally to the SCL and where this arbitration can be lost, these are: SDA pins for proper operation of the I2C module. • Address Transfer The following events will cause the SSP Interrupt Flag • Data Transfer bit, SSPIF, to be set (SSP Interrupt will occur if When the slave logic is enabled, the slave continues to enabled): receive. If arbitration was lost during the address • Start condition transfer stage, communication to the device may be in • Stop condition progress. If addressed, an ACK pulse will be generated. • Data transfer byte transmitted/received If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. Master mode of operation can be done with either the Slave mode idle (SSPM<3:0> = 1011), or with the 13.14.1 CLOCK SYNCHRONIZATION AND Slave active. When both Master and Slave modes are THE CKP BIT enabled, the software needs to differentiate the source(s) of the interrupt. When the CKP bit is cleared, the SCL output is forced to ‘0’; however, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure13-12).  2005-2015 Microchip Technology Inc. DS40001262F-page 191

PIC16F631/677/685/687/689/690 FIGURE 13-12: CLOCK SYNCHRONIZATION TIMING Table 0-1: Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 SDA DX DX-1 SCL Master device asserts clock CKP Master device deasserts clock WR SSPCON TABLE 13-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION(1) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh/8Bh/ INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x 10Bh/18Bh 0Ch PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- 93h SSPMSK(2) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111 94h SSPSTAT SMP(3) CKE(3) D/A P S R/W UA BF 0000 0000 0000 0000 8Ch PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IF TMR1IF -000 0000 -000 0000 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the SSP module. Note 1: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only. 2: SSPMSK register (Register13-3) can be accessed by reading or writing to SSPADD register with bits SSPM<3:0> = 1001. See Registers13-2 and13-3 for more details. 3: Maintain these bits clear. DS40001262F-page 192  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 14.0 SPECIAL FEATURES OF THE 14.1 Configuration Bits CPU The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various The PIC16F631/677/685/687/689/690 have a host of device configurations as shown in Register14-2. features intended to maximize system reliability, These bits are mapped in program memory location minimize cost through elimination of external compo- 2007h. nents, provide power saving features and offer code protection. These features are: Note: Address 2007h is beyond the user program memory space. It belongs to the special • Reset configuration memory space (2000h- - Power-on Reset (POR) 3FFFh), which can be accessed only during - Power-up Timer (PWRT) programming. See “PIC12F6XX/16F6XX - Oscillator Start-up Timer (OST) Memory Programming Specification” - Brown-out Reset (BOR) (DS41204) for more information. • Interrupts • Watchdog Timer (WDT) • Oscillator selection • Sleep • Code protection • ID Locations • In-Circuit Serial Programming The PIC16F631/677/685/687/689/690 have two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power- up Timer to provide at least a 64ms Reset. With these three functions-on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-down mode. The user can wake-up from Sleep through: • External Reset • Watchdog Timer Wake-up • An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register14-2).  2005-2015 Microchip Technology Inc. DS40001262F-page 193

PIC16F631/677/685/687/689/690 REGISTER 14-1: CONFIG: CONFIGURATION WORD REGISTER Reserved Reserved FCMEN IESO BOREN1(1) BOREN0(1) CPD(2 bit 13 bit 7 CP(3) MCLRE(4) PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 6 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13-12 Reserved: Reserved bits. Do Not Use. bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 10 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled 0 = Internal External Switchover mode is disabled bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR disabled bit 7 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 6 CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 5 MCLRE: MCLR Pin Function Select bit(4) 1 = MCLR pin function is MCLR 0 = MCLR pin function is digital input, MCLR internally tied to VDD bit 4 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 =RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 110 =RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 101 =INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 011 =EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN 010 =HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off. 3: The entire program memory will be erased when the code protection is turned off. 4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. DS40001262F-page 194  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 14.2 Reset They are not affected by a WDT Wake-up since this is viewed as the resumption of normal operation. TO and The PIC16F631/677/685/687/689/690 differentiates PD bits are set or cleared differently in different Reset between various kinds of Reset: situations, as indicated in Table14-2. These bits are a) Power-on Reset (POR) used in software to determine the nature of the Reset. b) WDT Reset during normal operation See Table14-4 for a full description of Reset states of all registers. c) WDT Reset during Sleep d) MCLR Reset during normal operation A simplified block diagram of the On-Chip Reset Circuit is shown in Figure14-1. e) MCLR Reset during Sleep f) Brown-out Reset (BOR) The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section17.0 “Electrical Some registers are not affected in any Reset condition; Specifications” for pulse-width specifications. their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on: • Power-on Reset • MCLR Reset • MCLR Reset during Sleep • WDT Reset • Brown-out Reset (BOR) FIGURE 14-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/VPP pin Sleep WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out(1) Reset BOREN SBOREN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1/ CLKI pin PWRT LFINTOSC 11-bit Ripple Counter Enable PWRT Enable OST Note 1: Refer to the Configuration Word register (Register14-1).  2005-2015 Microchip Technology Inc. DS40001262F-page 195

PIC16F631/677/685/687/689/690 14.2.1 POWER-ON RESET (POR) FIGURE 14-2: RECOMMENDED MCLR CIRCUIT The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. A maximum rise time for VDD is required. See VDD PIC16F685 Section17.0 “Electrical Specifications” for details. If the BOR is enabled, the maximum rise time specification R1 1kor greater) does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section14.2.4 MCLR “Brown-out Reset (BOR)”). Note: The POR circuit does not produce an C1 internal Reset when VDD declines. To re- 0.1 F (optional, not critical) enable the POR, VDD must reach Vss for a minimum of 100s. When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., 14.2.3 POWER-UP TIMER (PWRT) voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the The Power-up Timer provides a fixed 64ms (nominal) device must be held in Reset until the operating time-out on power-up only, from POR or Brown-out conditions are met. Reset. The Power-up Timer operates from the 31kHz LFINTOSC oscillator. For more information, see For additional information, refer to Application Note Section3.5 “Internal Clock Modes”. The chip is kept AN607, “Power-up Trouble Shooting” (DS00607). in Reset as long as PWRT is active. The PWRT delay 14.2.2 MCLR allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable PIC16F631/677/685/687/689/690 has a noise filter in (if cleared or programmed) the Power-up Timer. The the MCLR Reset path. The filter will detect and ignore Power-up Timer should be enabled when Brown-out small pulses. Reset is enabled, although it is not required. It should be noted that a WDT Reset does not drive The Power-up Timer delay will vary from chip-to-chip MCLR pin low. and vary due to: The behavior of the ESD protection on the MCLR pin • VDD variation has been altered from early devices of this family. • Temperature variation Voltages applied to the pin that exceed its specification • Process variation can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. See DC parameters for details (Section17.0 “Electrical For this reason, Microchip recommends that the MCLR Specifications”). pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure14-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RA3/MCLR pin becomes an external Reset input. In this mode, the RA3/MCLR pin has a weak pull-up to VDD. However, for robustness in noisy environments, the circuit shown in Figure14-2 is still recommended. DS40001262F-page 196  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 14.2.4 BROWN-OUT RESET (BOR) On any Reset (Power-on, Brown-out Reset, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises The BOREN0 and BOREN1 bits in the Configuration above VBOR (see Figure14-3). The Power-up Timer Word register select one of four BOR modes. Two will now be invoked, if enabled and will keep the chip in modes have been added to allow software or hardware Reset an additional 64ms. control of the BOR enable. When BOREN<1:0>=01, the SBOREN bit (PCON<4>) enables/disables the Note: The Power-up Timer is enabled by the BOR allowing it to be controlled in software. By PWRTE bit in the Configuration Word selecting BOREN<1:0>, the BOR is automatically register. disabled in Sleep to conserve power and enabled on wake-up. In this mode, the SBOREN bit is disabled. If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset See Register14-2 for the Configuration Word definition. and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a If VDD falls below VBOR for greater than parameter 64ms Reset. (TBOR) (see Section17.0 “Electrical Specifications”), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not insured to occur if VDD falls below VBOR for less than parameter (TBOR). FIGURE 14-3: BROWN-OUT SITUATIONS VDD VBOR Internal Reset 64 ms(1) VDD VBOR Internal < 64 ms Reset 64 ms(1) VDD VBOR Internal Reset 64 ms(1) Note 1: 64ms delay only if PWRTE bit is programmed to ‘0’.  2005-2015 Microchip Technology Inc. DS40001262F-page 197

PIC16F631/677/685/687/689/690 14.2.5 TIME-OUT SEQUENCE 14.2.6 POWER CONTROL (PCON) REGISTER On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then The Power Control register PCON (address 8Eh) has OST is activated after the PWRT time-out has expired. two Status bits to indicate what type of Reset that last The total time-out will vary based on oscillator occurred. configuration and PWRTE bit status. For example, in Bit0 is BOR (Brown-out Reset). BOR is unknown on EC mode with PWRTE bit erased (PWRT disabled), Power-on Reset. It must then be set by the user and there will be no time-out at all. Figures14-4,14-5 checked on subsequent Resets to see if BOR = 0, and14-6 depict time-out sequences. The device can indicating that a Brown-out has occurred. The BOR execute code from the INTOSC while OST is active by Status bit is a “don’t care” and is not necessarily enabling Two-Speed Start-up or Fail-Safe Monitor (see predictable if the brown-out circuit is disabled Section3.7.2 “Two-speed Start-up Sequence” and (BOREN<1:0> =00 in the Configuration Word Section3.8 “Fail-Safe Clock Monitor”). register). Since the time-outs occur from the POR pulse, if MCLR Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on is kept low long enough, the time-outs will expire. Then, Reset and unaffected otherwise. The user must write a bringing MCLR high will begin execution immediately ‘1’ to this bit following a Power-on Reset. On a (see Figure14-5). This is useful for testing purposes or subsequent Reset, if POR is ‘0’, it will indicate that a to synchronize more than one PIC16F631/677/685/ Power-on Reset has occurred (i.e., VDD may have 687/689/690 device operating in parallel. gone too low). Table14-5 shows the Reset conditions for some For more information, see Section4.2.4 “Ultra Low- special registers, while Table14-4 shows the Reset Power Wake-up” and Section14.2.4 “Brown-out conditions for all the registers. Reset (BOR)”. TABLE 14-1: TIME-OUT IN VARIOUS SITUATIONS Power-up Brown-out Reset Wake-up from Oscillator Configuration Sleep PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 XT, HS, LP TPWRT + 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC 1024 • TOSC 1024 • TOSC LP, T1OSCIN = 1 TPWRT — TPWRT — — RC, EC, INTOSC TPWRT — TPWRT — — TABLE 14-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 x 1 1 Power-on Reset u 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown TABLE 14-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PCON — — ULPWUE SBOREN — — POR BOR --01 --qq --0u --uu STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS40001262F-page 198  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 14-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 14-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset  2005-2015 Microchip Technology Inc. DS40001262F-page 199

PIC16F631/677/685/687/689/690 TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER Wake-up from Sleep MCLR Reset through Interrupt Register Address Power-on Reset WDT Reset Wake-up from Sleep Brown-out Reset(1) through WDT Time-out W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/ xxxx xxxx xxxx xxxx uuuu uuuu 100h/180h TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/ 0000 0000 0000 0000 PC + 1(3) 102h/182h STATUS 03h/83h/ 0001 1xxx 000q quuu(4) uuuq quuu(4) 103h/183h FSR 04h/84h/ xxxx xxxx uuuu uuuu uuuu uuuu 104h184h PORTA 05h/105h --xx xxxx --uu uuuu --uu uuuu PORTB 06h/106h xxxx ---- uuuu ---- uuuu ---- PORTC 07h/107h xxxx xxxx uuuu uuuu uuuu uuuu PCLATH 0Ah/8Ah/ ---0 0000 ---0 0000 ---u uuuu 10Ah/18Ah INTCON 0Bh/8Bh/ 0000 000x 0000 000u uuuu uuuu(2) 10Bh/18Bh PIR1 0Ch -000 0000 -000 0000 -uuu uuuu(2) PIR2 0Dh 0000 ---- 0000 ---- uuuu ----(2) TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu uuuu uuuu TMR2 11h 0000 0000 0000 0000 uuuu uuuu T2CON 12h -000 0000 -000 0000 -uuu uuuu SSPBUF 13h xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 14h 0000 0000 0000 0000 uuuu uuuu CCPR1L 15h xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 16h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 17h 0000 0000 0000 0000 uuuu uuuu RCSTA 18h 0000 000x 0000 000x uuuu uuuu TXREG 19h 0000 0000 0000 0000 uuuu uuuu RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu PWM1CON 1Ch 0000 0000 0000 0000 uuuu uuuu ECCPAS 1Dh 0000 0000 0000 0000 uuuu uuuu ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1Fh 0000 0000 0000 0000 uuuu uuuu OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu TRISA 85h/185h --11 1111 --11 1111 --uu uuuu Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table14-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. 6: Accessible only when SSPM<3:0> = 1001. DS40001262F-page 200  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER (CONTINUED) Wake-up from Sleep MCLR Reset through Interrupt Register Address Power-on Reset WDT Reset (Continued) Wake-up from Sleep Brown-out Reset(1) through WDT Time-out TRISB 86h/186h 1111 ---- 1111 ---- uuuu ---- TRISC 87h/187h 1111 1111 1111 1111 uuuu uuuu PIE1 8Ch -000 0000 -000 0000 -uuu uuuu PIE2 8Dh 0000 ---- 0000 ---- uuuu uuuu PCON 8Eh --01 --0x --0u --uq1, 5) --uu --uu OSCCON 8Fh -110 q000 -110 q000 -uuu uuuu OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu PR2 92h 1111 1111 1111 1111 uuuu uuuu SSPADD 93h 0000 0000 1111 1111 uuuu uuuu SSPMSK(6) 93h ---- ---- 1111 1111 uuuu uuuu SSPSTAT 94h 0000 0000 1111 1111 uuuu uuuu WPUA 95h --11 -111 --11 -111 uuuu uuuu IOCA 96h --00 0000 --00 0000 --uu uuuu WDTCON 97h ---0 1000 ---0 1000 ---u uuuu TXSTA 98h 0000 0010 0000 0010 uuuu uuuu SPBRG 99h 0000 0000 0000 0000 uuuu uuuu SPBRGH 9Ah 0000 0000 0000 0000 uuuu uuuu BAUDCTL 9Bh 01-0 0-00 01-0 0-00 uu-u u-uu ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 9Fh -000 ---- -000 ---- -uuu ---- EEDAT 10Ch 0000 0000 0000 0000 uuuu uuuu EEADR 10Dh 0000 0000 0000 0000 uuuu uuuu EEDATH 10Eh --00 0000 --00 0000 --uu uuuu EEADRH 10Fh ---- 0000 ---- 0000 ---- uuuu WPUB 115h 1111 ---- 1111 ---- uuuu ---- IOCB 116h 0000 ---- 0000 ---- uuuu ---- VRCON 118h 0000 0000 0000 0000 uuuu uuuu CM1CON0 119h 0000 -000 0000 -000 uuuu -uuu CM2CON0 11Ah 0000 -000 0000 -000 uuuu -uuu CM2CON1 11Bh 00-- --00 00-- --10 uu-- --uu ANSEL 11Eh 1111 1111 1111 1111 uuuu uuuu ANSELH 11Fh ---- 1111 ---- 1111 ---- uuuu EECON1 18Ch x--- x000 u--- q000 ---- uuuu EECON2 18Dh ---- ---- ---- ---- ---- ---- PSTRCON 19Dh ---0 0001 ---0 0001 ---u uuuu SRCON 19EH 0000 00-- 0000 00-- uuuu uu-- Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table14-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. 6: Accessible only when SSPM<3:0> = 1001. TABLE 14-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS  2005-2015 Microchip Technology Inc. DS40001262F-page 201

PIC16F631/677/685/687/689/690 Program Status PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx --01 --0x MCLR Reset during normal operation 000h 000u uuuu --0u --uu MCLR Reset during Sleep 000h 0001 0uuu --0u --uu WDT Reset 000h 0000 uuuu --0u --uu WDT Wake-up PC + 1 uuu0 0uuu --uu --uu Brown-out Reset 000h 0001 1uuu --01 --u0 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu --uu --uu Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. DS40001262F-page 202  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 14.3 Interrupts When an interrupt is serviced: • The GIE is cleared to disable any further interrupt. The PIC16F631/677/685/687/689/690 have multiple sources of interrupt: • The return address is pushed onto the stack. • The PC is loaded with 0004h. • External Interrupt RA2/INT • TMR0 Overflow Interrupt For external interrupt events, such as the INT pin, • PORTA/PORTB Change Interrupts PORTA/PORTB change interrupts, the interrupt • 2 Comparator Interrupts latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event • A/D Interrupt (except PIC16F631) occurs (see Figure14-8). The latency is the same for • Timer1 Overflow Interrupt one or 2-cycle instructions. Once in the Interrupt • Timer2 Match Interrupt (PIC16F685/PIC16F690 Service Routine, the source(s) of the interrupt can be only) determined by polling the interrupt flag bits. The • EEPROM Data Write Interrupt interrupt flag bit(s) must be cleared in software before • Fail-Safe Clock Monitor Interrupt re-enabling interrupts to avoid multiple interrupt • Enhanced CCP Interrupt (PIC16F685/PIC16F690 requests. only) Note1: Individual interrupt flag bits are set, • EUSART Receive and Transmit interrupts regardless of the status of their (PIC16F687/PIC16F689/PIC16F690 only) corresponding mask bit or the GIE bit. The Interrupt Control register (INTCON) and Peripheral 2: When an instruction that clears the GIE Interrupt Request Register 1 (PIR1) record individual bit is executed, any interrupts that were interrupt requests in flag bits. The INTCON register pending for execution in the next cycle also has individual and global interrupt enable bits. are ignored. The interrupts, which were A Global Interrupt Enable bit, GIE (INTCON<7>), ignored, are still pending to be serviced enables (if set) all unmasked interrupts, or disables (if when the GIE bit is set again. cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the For additional information on Timer1, Timer2, INTCON, PIE1 and PIE2 registers, respectively. GIE is comparators, A/D, data EEPROM, EUSART, SSP or cleared on Reset. Enhanced CCP modules, refer to the respective peripheral section. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which 14.3.1 RA2/INT INTERRUPT re-enables unmasked interrupts. External interrupt on RA2/INT pin is edge-triggered; The following interrupt flags are contained in the either rising if the INTEDG bit (OPTION_REG<6>) is INTCON register: set, or falling, if the INTEDG bit is clear. When a valid • INT Pin Interrupt edge appears on the RA2/INT pin, the INTF bit • PORTA/PORTB Change Interrupts (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF • TMR0 Overflow Interrupt bit must be cleared in software in the Interrupt Service The peripheral interrupt flags are contained in the PIR1 Routine before re-enabling this interrupt. The RA2/INT and PIR2 registers. The corresponding interrupt enable interrupt can wake-up the processor from Sleep, if the bits are contained in PIE1 and PIE2 registers. INTE bit was set prior to going into Sleep. The status of The following interrupt flags are contained in the PIR1 the GIE bit decides whether or not the processor register: branches to the interrupt vector following wake-up (0004h). See Section14.6 “Power-Down Mode • A/D Interrupt (Sleep)” for details on Sleep and Figure14-10 for • EUSART Receive and Transmit Interrupts timing of wake-up from Sleep through RA2/INT • Timer1 Overflow Interrupt interrupt. • Synchronous Serial Port (SSP) Interrupt Note: The ANSEL and CM2CON0 registers • Enhanced CCP1 Interrupt must be initialized to configure an analog • Timer1 Overflow Interrupt channel as a digital input. Pins configured • Timer2 Match Interrupt as analog inputs will read ‘0’. The following interrupt flags are contained in the PIR2 register: • Fail-Safe Clock Monitor Interrupt • 2 Comparator Interrupts • EEPROM Data Write Interrupt  2005-2015 Microchip Technology Inc. DS40001262F-page 203

PIC16F631/677/685/687/689/690 14.3.2 TIMER0 INTERRUPT 14.3.3 PORTA/PORTB INTERRUPT An overflow (FFh  00h) in the TMR0 register will set An input change on PORTA or PORTB change sets the the T0IF (INTCON<2>) bit. The interrupt can be RABIF (INTCON<0>) bit. The interrupt can be enabled/ enabled/disabled by setting/clearing T0IE (INTCON<5>) disabled by setting/clearing the RABIE (INTCON<3>) bit. See Section5.0 “Timer0 Module” for operation of bit. Plus, individual pins can be configured through the the Timer0 module. IOCA or IOCB registers. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RABIF interrupt flag may not get set. See Section4.2.3 “Interrupt-on-change” for more information. FIGURE 14-7: INTERRUPT LOGIC IOC-RA0 IOCA0 IOC-RA1 IOCA1 IOC-RA2 IOCA2 IOC-RA3 IOCA3 SSPIF SSPIE IOC-RA4 IOCA4 TXIF TXIE IOC-RA5 IOCA5 RCIF RCIE Wake-up (If in Sleep mode)(1) IOC-RB4 T0IF IOCB4 TMR2IF T0IE Interrupt to CPU TMR2IE IOC-RB5 INTF IOCB5 INTE TMR1IF RABIF TMR1IE IOC-RB6 RABIE IOCB6 C1IF C1IE PEIE IOC-RB7 IOCB7 C2IF GIE C2IE ADIF ADIE EEIF EEIE Note 1: Some peripherals depend upon the system OSFIF clock for operation. Since the system clock is OSFIE suspended during Sleep, these peripherals will not wake the part from Sleep. See CCP1IF Section14.6.1 “Wake-up from Sleep”. CCP1IE DS40001262F-page 204  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 14-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 (3) CLKOUT (4) INT pin (1) (1) (2) INTF flag (5) Interrupt Latency (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section17.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. TABLE 14-6: SUMMARY OF INTERRUPT REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIE2 OSFIE C2IE C1IE EEIE — — — — 0000 ---- 0000 ---- PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 PIR2 OSFIF C2IF C1IF EEIF — — — — 0000 ---- 0000 ---- Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the Interrupt module.  2005-2015 Microchip Technology Inc. DS40001262F-page 205

PIC16F631/677/685/687/689/690 14.4 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Since the upper 16 bytes of all GPR banks are common in the PIC16F631/677/685/687/689/690 (see Figures2-2 and2-3), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, make it easier to context save and restore. The same code shown in Example14-1 can be used to: • Store the W register • Store the STATUS register • Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register Note: The PIC16F631/677/685/687/689/690 normally does not require saving the PCLATH. However, if computed GOTO’s are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR. EXAMPLE 14-1: SAVING STATUS AND W REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W DS40001262F-page 206  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 14.5 Watchdog Timer (WDT) 14.5.2 WDT CONTROL The WDT has the following features: The WDTE bit is located in the Configuration Word register. When set, the WDT runs continuously. • Operates from the LFINTOSC (31 kHz) When the WDTE bit in the Configuration Word register • Contains a 16-bit prescaler is set, the SWDTEN bit of the WDTCON register has no • Shares an 8-bit prescaler with Timer0 effect. If WDTE is clear, then the SWDTEN bit can be • Time-out period is from 1 ms to 268 seconds used to enable and disable the WDT. Setting the bit will • Configuration bit and software controlled enable it and clearing the bit will disable it. WDT is cleared under certain conditions described in The PSA and PS<2:0> bits of the OPTION register Table14-7. have the same function as in previous versions of the PIC16F631/677/685/687/689/690 Family of microcon- 14.5.1 WDT OSCILLATOR trollers. See Section5.0 “Timer0 Module” for more The WDT derives its time base from the 31kHz information. LFINTOSC. The LTS bit of the OSCCON register does not reflect that the LFINTOSC is enabled. The value of WDTCON is ‘---0 1000’ on all Resets. This gives a nominal time base of 17ms. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled). FIGURE 14-9: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source 0 Prescaler(1) 16-bit WDT Prescaler 1 8 PSA PS<2:0> 31kHz WDTPS<3:0> To TMR0 LFINTOSC Clock 0 1 PSA WDTE from the Configuration Word Register SWDTEN from WDTCON WDT Time-out Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information. TABLE 14-7: WDT STATUS Conditions WDT WDTE = 0 Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST  2005-2015 Microchip Technology Inc. DS40001262F-page 207

PIC16F631/677/685/687/689/690 REGISTER 14-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note1: If WDTE Configuration bit=1, then WDT is always enabled, irrespective of this control bit. If WDTE Configuration bit=0, then it is possible to turn WDT on/off with this control bit. TABLE 14-8: SUMMARY OF WATCHDOG TIMER REGISTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets CONFIG(1) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register14-1 for operation of all Configuration Word register bits. DS40001262F-page 208  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 14.6 Power-Down Mode (Sleep) When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to The Power-Down mode is entered by executing a wake-up through an interrupt event, the corresponding SLEEP instruction. interrupt enable bit must be set (enabled). Wake-up If the Watchdog Timer is enabled: occurs regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at • WDT will be cleared but keeps running. the instruction after the SLEEP instruction. If the GIE bit • PD bit in the STATUS register is cleared. is set (enabled), the device executes the instruction • TO bit is set. after the SLEEP instruction, then branches to the inter- • Oscillator driver is turned off. rupt address (0004h). In cases where the execution of • I/O ports maintain the status they had before the instruction following SLEEP is not desirable, the SLEEP was executed (driving high, low or high- user should have a NOP after the SLEEP instruction. impedance). Note: If the global interrupts are disabled (GIE is For lowest current consumption in this mode, all I/O pins cleared), but any interrupt source has both should be either at VDD or VSS, with no external circuitry its interrupt enable bit and the drawing current from the I/O pin and the comparators corresponding interrupt flag bits set, the and CVREF should be disabled. I/O pins that are high- device will immediately wake-up from impedance inputs should be pulled high or low externally Sleep. The SLEEP instruction is completely to avoid switching currents caused by floating inputs. executed. The T0CKI input should also be at VDD or VSS for lowest The WDT is cleared when the device wakes up from current consumption. The contribution from on-chip pull- Sleep, regardless of the source of wake-up. ups on PORTA should be considered. The MCLR pin must be at a logic high level. 14.6.2 WAKE-UP USING INTERRUPTS Note: It should be noted that a Reset generated When global interrupts are disabled (GIE cleared) and by a WDT time-out does not drive MCLR any interrupt source has both its interrupt enable bit pin low. and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a 14.6.1 WAKE-UP FROM SLEEP SLEEP instruction, the SLEEP instruction will The device can wake-up from Sleep through one of the complete as a NOP. Therefore, the WDT and WDT following events: prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit 1. External Reset input on MCLR pin. will not be cleared. 2. Watchdog Timer Wake-up (if WDT was enabled). • If the interrupt occurs during or after the execu- 3. Interrupt from RA2/INT pin, PORTA change or a tion of a SLEEP instruction, the device will imme- peripheral interrupt. diately wake-up from Sleep. The SLEEP The first event will cause a device Reset. The two latter instruction will be completely executed before the events are considered a continuation of program exe- wake-up. Therefore, the WDT and WDT prescaler cution. The TO and PD bits in the STATUS register can and postscaler (if enabled) will be cleared, the TO be used to determine the cause of device Reset. The bit will be set and the PD bit will be cleared. PD bit, which is set on power-up, is cleared when Sleep Even if the flag bits were checked before executing a is invoked. TO bit is cleared if WDT Wake-up occurred. SLEEP instruction, it may be possible for flag bits to The following peripheral interrupts can wake the device become set before the SLEEP instruction completes. To from Sleep: determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction 1. TMR1 interrupt. Timer1 must be operating as an was executed as a NOP. asynchronous counter. 2. ECCP Capture mode interrupt. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. 3. A/D conversion (when A/D clock source is FRC). 4. EEPROM write operation completion. 5. Comparator output changes state. 6. Interrupt-on-change. 7. External Interrupt from INT pin. 8. EUSART Break detect, I2C slave. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present.  2005-2015 Microchip Technology Inc. DS40001262F-page 209

PIC16F631/677/685/687/689/690 FIGURE 14-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency(3) GIE bit Processor in (INTCON<7>) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC – 1) Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. 3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. 4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference. 14.7 Code Protection This allows customers to manufacture boards with unprogrammed devices and then program the micro- If the code protection bit(s) have not been controller just before shipping the product. This also programmed, the on-chip program memory can be allows the most recent firmware or a custom firmware read out using ICSP™ for verification purposes. to be programmed. Note: The entire data EEPROM and Flash The device is placed into a Program/Verify mode by program memory will be erased when the holding the RA0/AN0/C1IN+/ICSPDAT/ULPWU and code protection is switched from on to off. RA1/AN1/C12IN-/VREF/ICSPCLK pins low, while See the “PIC12F6XX/16F6XX Memory raising the MCLR (VPP) pin from VIL to VIHH. See the Programming Specification” (DS41204) “PIC12F6XX/16F6XX Memory Programming for more information. Specification” (DS41204) for more information. RA0 becomes the programming data and RA1 becomes the 14.8 ID Locations programming clock. Both RA0 and RA1 are Schmitt Trigger inputs in this mode. Four memory locations (2000h-2003h) are designated After Reset, to place the device into Program/Verify as ID locations where the user can store checksum or mode, the Program Counter (PC) is at location 00h. A other code identification numbers. These locations are 6-bit command is then supplied to the device. not accessible during normal execution but are Depending on the command, 14 bits of program data readable and writable during Program/Verify mode. are then supplied to or from the device, depending on Only the Least Significant seven bits of the ID locations whether the command was a load or a read. For are used. complete details of serial programming, please refer to the “PIC12F6XX/16F6XX Memory Programming 14.9 In-Circuit Serial Programming Specification” (DS41204). The PIC16F631/677/685/687/689/690 microcontrollers A typical In-Circuit Serial Programming connection is can be serially programmed while in the end applica- shown in Figure14-11. tion circuit. This is simply done with two lines for clock and data and three other lines for: • power • ground • programming voltage DS40001262F-page 210  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 14-11: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections External Connector * PIC16F631/677/ Signals 685/687/689/690 +5V VDD 0V VSS VPP RA3/MCLR/VPP CLK RA1 Data I/O RA0 * * * To Normal Connections * Isolation devices (as required)  2005-2015 Microchip Technology Inc. DS40001262F-page 211

PIC16F631/677/685/687/689/690 15.0 INSTRUCTION SET SUMMARY TABLE 15-1: OPCODE FIELD DESCRIPTIONS The PIC16F690 instruction set is highly orthogonal and is comprised of three basic categories: Field Description • Byte-oriented operations f Register file address (0x00 to 0x7F) • Bit-oriented operations W Working register (accumulator) • Literal and control operations b Bit address within an 8-bit file register Each PIC16 instruction is a 14-bit word divided into an k Literal field, constant data or label opcode, which specifies the instruction type and one or x Don’t care location (= 0 or 1). more operands, which further specify the operation of The assembler will generate code with x = 0. the instruction. The formats for each of the categories It is the recommended form of use for is presented in Figure15-1, while the various opcode compatibility with all Microchip software tools. fields are summarized in Table15-1. d Destination select; d = 0: store result in W, Table15-2 lists the instructions recognized by the d = 1: store result in file register f. MPASMTM assembler. Default is d = 1. For byte-oriented instructions, ‘f’ represents a file PC Program Counter register designator and ‘d’ represents a destination TO Time-out bit designator. The file register designator specifies which C Carry bit file register is to be used by the instruction. DC Digit carry bit The destination designator specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is Z Zero bit placed in the W register. If ‘d’ is one, the result is placed PD Power-down bit in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field FIGURE 15-1: GENERAL FORMAT FOR designator, which selects the bit affected by the INSTRUCTIONS operation, while ‘f’ represents the address of the file in which the bit is located. Byte-oriented file register operations 13 8 7 6 0 For literal and control operations, ‘k’ represents an OPCODE d f (FILE #) 8-bit or 11-bit constant, or literal value. d = 0 for destination W One instruction cycle consists of four oscillator periods; d = 1 for destination f for an oscillator frequency of 4 MHz, this gives a normal f = 7-bit file register address instruction execution time of 1s. All instructions are executed within a single instruction cycle, unless a Bit-oriented file register operations conditional test is true, or the program counter is 13 10 9 7 6 0 changed as a result of an instruction. When this occurs, OPCODE b (BIT #) f (FILE #) the execution takes two instruction cycles, with the second cycle executed as a NOP. b = 3-bit bit address f = 7-bit file register address All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a Literal and control operations hexadecimal digit. General 15.1 Read-Modify-Write Operations 13 8 7 0 OPCODE k (literal) Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (RMW) k = 8-bit immediate value operation. The register is read, the data is modified, and the result is stored according to either the instruc- CALL and GOTO instructions only tion, or the destination designator ‘d’. A read operation 13 11 10 0 is performed on a register even if the instruction writes OPCODE k (literal) to that register. k = 11-bit immediate value For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag. DS40001262F-page 212  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 15-2: PIC16F684 INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP – No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call Subroutine 2 10 0kkk kkkk kkkk CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE – Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.  2005-2015 Microchip Technology Inc. DS40001262F-page 213

PIC16F631/677/685/687/689/690 15.2 Instruction Descriptions ADDLW Add literal and W BCF Bit Clear f Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b Operands: 0  k  255 Operands: 0  f  127 0  b  7 Operation: (W) + k  (W) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: The contents of the W register are added to the 8-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared. and the result is placed in the W register. ADDWF Add W and f BSF Bit Set f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b Operands: 0  f  127 Operands: 0  f  127 d 0,1 0  b  7 Operation: (W) + (f)  (destination) Operation: 1  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set. with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSC f,b Operands: 0  k  255 Operands: 0  f  127 0  b  7 Operation: (W) .AND. (k)  (W) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: The contents of W register are AND’ed with the 8-bit literal ‘k’. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next The result is placed in the W reg- instruction is executed. ister. If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. ANDWF AND W with f Syntax: [ label ] ANDWF f,d Operands: 0  f  127 d 0,1 Operation: (W) .AND. (f)  (destination) Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001262F-page 214  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0  f  127 Operands: None 0  b < 7 Operation: 00h  WDT Operation: skip if (f<b>) = 1 0  WDT prescaler, 1  TO Status Affected: None 1  PD Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Status Affected: TO, PD instruction is executed. If bit ‘b’ is ‘1’, then the next Description: CLRWDT instruction resets the instruction is discarded and a NOP Watchdog Timer. It also resets the is executed instead, making this a prescaler of the WDT. 2-cycle instruction. Status bits TO and PD are set. CALL Call Subroutine COMF Complement f Syntax: [ label ] CALL k Syntax: [ label ] COMF f,d Operands: 0  k  2047 Operands: 0  f  127 Operation: (PC)+ 1 TOS, d  [0,1] k  PC<10:0>, Operation: (f)  (destination) (PCLATH<4:3>)  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are Description: Call Subroutine. First, return complemented. If ‘d’ is ‘0’, the address (PC + 1) is pushed onto result is stored in W. If ‘d’ is ‘1’, the stack. The 11-bit immediate the result is stored back in address is loaded into PC bits register ‘f’. <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a 2-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Decrement register ‘f’. If ‘d’ is ‘0’, cleared and the Z bit is set. the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h  (W) 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set.  2005-2015 Microchip Technology Inc. DS40001262F-page 215

PIC16F631/677/685/687/689/690 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. If the result is ‘1’, the next If the result is ‘1’, the next instruction is executed. If the instruction is executed. If the result is ‘0’, then a NOP is result is ‘0’, a NOP is executed executed instead, making it a instead, making it a 2-cycle 2-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<4:3>  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the 8-bit literal ‘k’. The The 11-bit immediate value is result is placed in the W register. loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Inclusive OR the W register with incremented. If ‘d’ is ‘0’, the result register ‘f’. If ‘d’ is ‘0’, the result is is placed in the W register. If ‘d’ is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. DS40001262F-page 216  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 MOVF Move f MOVWF Move W to f Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: (W)  (f) Operation: (f)  (dest) Status Affected: None Status Affected: Z Description: Move data from W register to Description: The contents of register ‘f’ is register ‘f’. moved to a destination dependent Words: 1 upon the status of ‘d’. If d = 0, Cycles: 1 destination is W register. If d = 1, the destination is file register ‘f’ Example: MOVW OPTION itself. d = 1 is useful to test a file F register since status flag Z is Before Instruction affected. OPTION= 0xFF Words: 1 W = 0x4F After Instruction Cycles: 1 OPTION= 0x4F Example: MOVF FSR, 0 W = 0x4F After Instruction W = value in FSR register Z = 1 MOVLW Move literal to W NOP No Operation Syntax: [ label ] MOVLW k Syntax: [ label ] NOP Operands: 0  k  255 Operands: None Operation: k  (W) Operation: No operation Status Affected: None Status Affected: None Description: The 8-bit literal ‘k’ is loaded into W Description: No operation. register. The “don’t cares” will Words: 1 assemble as ‘0’s. Cycles: 1 Words: 1 Example: NOP Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A  2005-2015 Microchip Technology Inc. DS40001262F-page 217

PIC16F631/677/685/687/689/690 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k Operands: None Operands: 0  k  255 Operation: TOS  PC, Operation: k  (W); 1  GIE TOS  PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is Description: The W register is loaded with the POPed and Top-of-Stack (TOS) is 8-bit literal ‘k’. The program loaded in the PC. Interrupts are counter is loaded from the top of enabled by setting Global the stack (the return address). Interrupt Enable bit, GIE This is a 2-cycle instruction. (INTCON<7>). This is a 2-cycle Words: 1 instruction. Cycles: 2 Words: 1 Example: CALL TABLE;W contains Cycles: 2 table Example: RETFIE ;offset value TABLE • ;W now has After Interrupt • ;table value PC = TOS • GIE= 1 • ADDWF PC;W = offset RETLW k1;Begin table RETLW k2 ; • • • RETLW kn ;End of table Before Instruction W = 0x07 After Instruction W = value of k8 RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS  PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a 2-cycle instruc- tion. DS40001262F-page 218  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP Operands: 0  f  127 Operands: None d  [0,1] Operation: 00h  WDT, Operation: See description below 0  WDT prescaler, 1  TO, Status Affected: C 0  PD Description: The contents of register ‘f’ are Status Affected: TO, PD rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is result is placed in the W register. cleared. Time-out Status bit, TO If ‘d’ is ‘1’, the result is stored is set. Watchdog Timer and its back in register ‘f’. prescaler are cleared. The processor is put into Sleep C Register f mode with the oscillator stopped. Words: 1 Cycles: 1 Example: RLF REG1,0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 1100 1100 C = 1 RRF Rotate Right f through Carry SUBLW Subtract W from literal Syntax: [ label ] RRF f,d Syntax: [ label ] SUBLW k Operands: 0  f  127 Operands: 0 k 255 d  [0,1] Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s Description: The contents of register ‘f’ are complement method) from the 8-bit rotated one bit to the right through literal ‘k’. The result is placed in the the Carry flag. If ‘d’ is ‘0’, the W register. result is placed in the W register. If ‘d’ is ‘1’, the result is placed C = 0 W  k back in register ‘f’. C = 1 W  k C Register f DC = 0 W<3:0>  k<3:0> DC = 1 W<3:0>  k<3:0>  2005-2015 Microchip Technology Inc. DS40001262F-page 219

PIC16F631/677/685/687/689/690 SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 f 127 Operands: 0 k 255 d  [0,1] Operation: (W) .XOR. k W) Operation: (f) - (W) destination) Status Affected: Z Status Affected: C, DC, Z Description: The contents of the W register Description: Subtract (2’s complement method) are XOR’ed with the 8-bit W register from register ‘f’. If ‘d’ is literal ‘k’. The result is placed in ‘0’, the result is stored in the W the W register. register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. C = 0 W  f C = 1 W  f DC = 0 W<3:0>  f<3:0> DC = 1 W<3:0>  f<3:0> SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f<3:0>)  (destination<7:4>), Operation: (W) .XOR. (f) destination) (f<7:4>)  (destination<3:0>) Status Affected: Z Status Affected: None Description: Exclusive OR the contents of the Description: The upper and lower nibbles of W register with register ‘f’. If ‘d’ is register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is stored in the W ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. placed in register ‘f’. DS40001262F-page 220  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 16.0 DEVELOPMENT SUPPORT 16.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2005-2015 Microchip Technology Inc. DS40001262F-page 221

PIC16F631/677/685/687/689/690 16.2 MPLAB XC Compilers 16.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 16.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 16.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001262F-page 222  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 16.6 MPLAB X SIM Software Simulator 16.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 16.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 16.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 16.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2005-2015 Microchip Technology Inc. DS40001262F-page 223

PIC16F631/677/685/687/689/690 16.11 Demonstration/Development 16.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001262F-page 224  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 17.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ...............................................................................................-0.3V to +13.5V Voltage on all other pins with respect to VSS ...........................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)...............................................................................................................................800 mW Maximum current out of VSS pin.....................................................................................................................300 mA Maximum current into VDD pin........................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)20 mA Maximum output current sunk by any I/O pin....................................................................................................25 mA Maximum output current sourced by any I/O pin..............................................................................................25 mA Maximum current sunk by PORTA, PORTB and PORTC (combined)............................................................200 mA Maximum current sourced PORTA, PORTB and PORTC (combined)............................................................200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD -  IOH} +  {(VDD - VOH) x IOH} + (VOL x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100  should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to VSS.  2005-2015 Microchip Technology Inc. DS40001262F-page 225

PIC16F631/677/685/687/689/690 FIGURE 17-1: PIC16F631/677/685/687/689/690 VOLTAGE-FREQUENCY GRAPH, -40°C  TA  +125°C 5.5 5.0 4.5 V) 4.0 ( D D V 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 17-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 C) ± 2% ° 60 ( e r u at r e p 25 ± 1% m e T 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001262F-page 226  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 17.1 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min. Typ† Max. Units Conditions No. VDD Supply Voltage 2.0 — 5.5 V FOSC < = 8 MHz: HFINTOSC, EC D001 2.0 — 5.5 V FOSC < = 4 MHz D001C 3.0 — 5.5 V FOSC < = 10 MHz D001D 4.5 — 5.5 V FOSC < = 20 MHz D002* VDR RAM Data Retention 1.5 — — V Device in Sleep mode Voltage(1) D003 VPOR VDD Start Voltage to — VSS — V See Section14.2.1 “Power-on Reset ensure internal Power-on (POR)” for details. Reset signal D004* SVDD VDD Rise Rate to ensure 0.05 — — V/ms See Section14.2.1 “Power-on Reset internal Power-on Reset (POR)” for details. signal * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.  2005-2015 Microchip Technology Inc. DS40001262F-page 227

PIC16F631/677/685/687/689/690 17.2 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40C  TA  +85C for industrial -40°C  TA  +125°C for extended Conditions Param Device Characteristics Min. Typ† Max. Units No. VDD Note D010 Supply Current (IDD)(1, 2) — 13 19 A 2.0 FOSC = 32kHz — 22 30 A 3.0 LP Oscillator mode — 33 60 A 5.0 D011* — 140 240 A 2.0 FOSC = 1MHz — 220 380 A 3.0 XT Oscillator mode — 380 550 A 5.0 D012 — 260 360 A 2.0 FOSC = 4MHz — 420 650 A 3.0 XT Oscillator mode — 0.8 1.1 mA 5.0 D013* — 130 220 A 2.0 FOSC = 1MHz — 215 360 A 3.0 EC Oscillator mode — 360 520 A 5.0 D014 — 220 340 A 2.0 FOSC = 4MHz — 375 550 A 3.0 EC Oscillator mode — 0.65 1.0 mA 5.0 D015 — 8 20 A 2.0 FOSC = 31kHz — 16 40 A 3.0 LFINTOSC mode — 31 65 A 5.0 D016* — 340 450 A 2.0 FOSC = 4MHz — 500 700 A 3.0 HFINTOSC mode — 0.8 1.2 mA 5.0 D017 — 410 650 A 2.0 FOSC = 8MHz — 700 950 A 3.0 HFINTOSC mode — 1.30 1.65 mA 5.0 D018 — 230 400 A 2.0 FOSC = 4MHz — 400 680 A 3.0 EXTRC mode(3) — 0.63 1.1 mA 5.0 D019 — 3.8 5.0 mA 4.5 FOSC = 20MHz — 4.0 5.45 mA 5.0 HS Oscillator mode † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. 4: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. DS40001262F-page 228  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 17.2 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40C  TA  +85C for industrial -40°C  TA  +125°C for extended Conditions Param Device Characteristics Min. Typ† Max. Units No. VDD Note D020 Power-down Base — 0.05 1.2 A 2.0 WDT, BOR, Comparators, VREF and Current(IPD)(2) — 0.15 1.5 A 3.0 T1OSC disabled — 0.35 1.8 A 5.0 — 90 500 nA 3.0 -40°C  TA  +25°C D021 — 1.0 2.2 A 2.0 WDT Current(1) — 2.0 4.0 A 3.0 — 3.0 7.0 A 5.0 D022 — 42 60 A 3.0 BOR Current(1) — 85 122 A 5.0 D023 — 32 45 A 2.0 Comparator Current(1), both — 60 78 A 3.0 comparators enabled — 120 160 A 5.0 D024 — 30 36 A 2.0 CVREF Current(1) (high range) — 45 55 A 3.0 — 75 95 A 5.0 D024a* — 39 47 A 2.0 CVREF Current(1) (low range) — 59 72 A 3.0 — 98 124 A 5.0 D025 — 2.0 5.0 A 2.0 T1OSC Current, 32.768kHz — 2.5 5.5 A 3.0 — 3.0 7.0 A 5.0 D026 — 0.30 1.6 A 3.0 A/D Current(1), no conversion in — 0.36 1.9 A 5.0 progress D027 — 90 125 A 3.0 VP6 Current — 125 162 A 5.0 † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. 4: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.  2005-2015 Microchip Technology Inc. DS40001262F-page 229

PIC16F631/677/685/687/689/690 17.3 DC Characteristics: PIC16F631/677/685/687/689/690-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Characteristics Min. Typ† Max. Units No. VDD Note D020E Power-down Base — 0.05 9 A 2.0 WDT, BOR, Comparators, VREF and Current(IPD)(2) — 0.15 11 A 3.0 T1OSC disabled — 0.35 15 A 5.0 — 90 500 nA 3.0 -40°C  TA  +25°C D021E — 1.0 17.5 A 2.0 WDT Current(1) — 2.0 19 A 3.0 — 3.0 22 A 5.0 D022E — 42 65 A 3.0 BOR Current(1) — 85 127 A 5.0 D023E — 32 45 A 2.0 Comparator Current(1), both — 60 78 A 3.0 comparators enabled — 120 160 A 5.0 D024E — 30 70 A 2.0 CVREF Current(1) (high range) — 45 90 A 3.0 — 75 120 A 5.0 D024AE* — 39 91 A 2.0 CVREF Current(1) (low range) — 59 117 A 3.0 — 98 156 A 5.0 D025E — 2.0 18 A 2.0 T1OSC Current — 2.5 21 A 3.0 — 3.0 24 A 5.0 D026E — 0.30 12 A 3.0 A/D Current(1), no conversion in — 0.36 16 A 5.0 progress D027E — 90 130 A 3.0 VP6 Current — 125 170 A 5.0 † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. 4: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. DS40001262F-page 230  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 17.4 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage I/O Port: D030 with TTL buffer Vss — 0.8 V 4.5V  VDD  5.5V D030A Vss — 0.15 VDD V 2.0V  VDD  4.5V D031 with Schmitt Trigger buffer Vss — 0.2 VDD V 2.0V  VDD  5.5V D032 MCLR, OSC1 (RC mode)(1) VSS — 0.2 VDD V D033 OSC1 (XT and LP modes) VSS — 0.3 V D033A OSC1 (HS mode) VSS — 0.3 VDD V VIH Input High Voltage I/O Ports: — D040 with TTL buffer 2.0 — VDD V 4.5V  VDD 5.5V D040A 0.25 VDD + 0.8 — VDD V 2.0V  VDD  4.5V D041 with Schmitt Trigger buffer 0.8 VDD — VDD V 2.0V  VDD  5.5V D042 MCLR 0.8 VDD — VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V D043A OSC1 (HS mode) 0.7 VDD — VDD V D043B OSC1 (RC mode) 0.9 VDD — VDD V (Note 1) IIL Input Leakage Current(2) D060 I/O ports — 0.1 1 A VSS VPIN VDD, Pin at high-impedance D061 MCLR(3) — 0.1 5 A VSS VPIN VDD D063 OSC1 — 0.1 5 A VSS VPIN VDD, XT, HS and LP oscillator configuration D070* IPUR PORTA Weak Pull-up Current 50 250 400 A VDD = 5.0V, VPIN = VSS VOL Output Low Voltage(5) D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.) VOH Output High Voltage(5) D090 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.) D100 IULP Ultra Low-Power Wake-up — 200 — nA See Application Note AN879, Current “Using the Microchip Ultra Low-Power Wake-up Module” (DS00879) Capacitive Loading Specs on Output Pins * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section10.2.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode.  2005-2015 Microchip Technology Inc. DS40001262F-page 231

PIC16F631/677/685/687/689/690 17.4 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF Data EEPROM Memory D120 ED Byte Endurance 100K 1M — E/W -40°C  TA +85°C D120A ED Byte Endurance 10K 100K — E/W +85°C  TA +125°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON1 to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 5 6 ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C  TA +85°C Cycles before Refresh(4) Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C  TA +85°C D130A ED Cell Endurance 1K 10K — E/W +85°C  TA +125°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VPEW VDD for Erase/Write 4.5 — 5.5 V D133 TPEW Erase/Write cycle time — 2 2.5 ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section10.2.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode. DS40001262F-page 232  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 17.5 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance 62.4 C/W 20-pin PDIP package Junction to Ambient 85.2 C/W 20-pin SOIC package 108.1 C/W 20-pin SSOP package 40 C/W 20-pin QFN 4x4mm package TH02 JC Thermal Resistance 28.1 C/W 20-pin PDIP package Junction to Case 24.2 C/W 20-pin SOIC package 32.2 C/W 20-pin SSOP package 2.5 C/W 20-pin QFN 4x4mm package TH03 TDIE Die Temperature 150 C For derated power calculations TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD (Note 1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TDIE - TA)/JA (Note 2, 3) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature. 3: Maximum allowable power dissipation is the lower value of either the absolute maximum total power dissipation or derated power.  2005-2015 Microchip Technology Inc. DS40001262F-page 233

PIC16F631/677/685/687/689/690 17.6 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O Port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 17-3: LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL=50 pFfor all pins 15 pF for OSC2 output DS40001262F-page 234  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 17.7 AC Characteristics: PIC16F631/677/685/687/689/690 (Industrial, Extended) FIGURE 17-4: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 17-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode DC — 4 MHz XT Oscillator mode DC — 20 MHz HS Oscillator mode DC — 20 MHz EC Oscillator mode Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 20 MHz HS Oscillator mode DC — 4 MHz RC Oscillator mode OS02 TOSC External CLKIN Period(1) 27 —  s LP Oscillator mode 250 —  ns XT Oscillator mode 50 —  ns HS Oscillator mode 50 —  ns EC Oscillator mode Oscillator Period(1) — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC OS04* TOSH, External CLKIN High, 2 — — s LP oscillator TOSL External CLKIN Low 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TOSR, External CLKIN Rise, 0 —  ns LP oscillator TOSF External CLKIN Fall 0 —  ns XT oscillator 0 —  ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.  2005-2015 Microchip Technology Inc. DS40001262F-page 235

PIC16F631/677/685/687/689/690 TABLE 17-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Freq. Sym. Characteristic Min. Typ† Max. Units Conditions No. Tolerance OS06 TWARM Internal Oscillator Switch — — — 2 TOSC Slowest clock when running(3) OS07 TSC Fail-Safe Sample Clock — — 21 — ms LFINTOSC/64 Period(1) OS08 HFOSC Internal Calibrated 1% 7.92 8.0 8.08 MHz VDD = 3.5V, 25°C HFINTOSC Frequency(2) 2% 7.84 8.0 8.16 MHz 2.5V VDD  5.5V, 0°C  TA  +85°C 5% 7.60 8.0 8.40 MHz 2.0V VDD  5.5V, -40°C  TA  +85°C (Ind.), -40°C  TA  +125°C (Ext.) OS09* LFOSC Internal Uncalibrated — 15 31 45 kHz LFINTOSC Frequency OS10* TIOSC ST HFINTOSC Oscillator — 5.5 12 24 s VDD = 2.0V, -40°C to +85°C Wake-up from Sleep — 3.5 7 14 s VDD = 3.0V, -40°C to +85°C Start-up Time — 3 6 11 s VDD = 5.0V, -40°C to +85°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. 3: By design. DS40001262F-page 236  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 17-5: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19 TABLE 17-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS11 TOSH2CKL FOSC to CLKOUT (1) — — 70 ns VDD = 5.0V OS12 TOSH2CKH FOSC to CLKOUT (1) — — 72 ns VDD = 5.0V OS13 TCKL2IOV CLKOUT to port out valid(1) — — 20 ns OS14 TIOV2CKH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns OS15 TOSH2IOV FOSC (Q1 cycle) to port out valid — 50 70* ns VDD = 5.0V OS16 TOSH2IOI FOSC (Q2 cycle) to port input invalid 50 — — ns VDD = 5.0V (I/O in hold time) OS17 TIOV2OSH Port input valid to FOSC(Q2 cycle) 20 — — ns (I/O in setup time) OS18 TIOR Port output rise time(2) — 15 72 ns VDD = 2.0V — 40 32 VDD = 5.0V OS19 TIOF Port output fall time(2) — 28 55 ns VDD = 2.0V — 15 30 VDD = 5.0V OS20* TINP INT pin input high or low time 25 — — ns OS21* TRAP PORTA interrupt-on-change new input TCY — — ns level time * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode.  2005-2015 Microchip Technology Inc. DS40001262F-page 237

PIC16F631/677/685/687/689/690 FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 17-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33* (due to BOR) * 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. DS40001262F-page 238  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +85°C 5 — — s VDD = 5V 31 TWDT Watchdog Timer Time-out 10 17 25 ms VDD = 5V, -40°C to +85°C Period (No Prescaler) 10 17 30 ms VDD = 5V 32 TOST Oscillation Start-up Timer — 1024 — TOSC (Note 3) Period(1, 2) 33* TPWRT Power-up Timer Period 40 65 140 ms 34* TIOZ I/O High-impedance from — — 2.0 s MCLR Low or Watchdog Timer Reset 35 VBOR Brown-out Reset Voltage 2.0 — 2.2 V (Note 4) 36* VHYST Brown-out Reset Hysteresis — 50 — mV 37* TBOR Brown-out Reset Minimum 100 — — s VDD  VBOR Detection Period * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper- ation and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended.  2005-2015 Microchip Technology Inc. DS40001262F-page 239

PIC16F631/677/685/687/689/690 FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value Period 30 or TCY + 40 (1, 2, 4, 8) N Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range — 32.768 — kHz (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync Increment mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001262F-page 240  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (ECCP) CCP1 (Capture mode) CC01 CC02 CC03 Note: Refer to Figure17-3 for load conditions. TABLE 17-6: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCP1 Input Period 3TCY + 40 — — ns N = prescale N value (1, 4 or 16) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2005-2015 Microchip Technology Inc. DS40001262F-page 241

PIC16F631/677/685/687/689/690 TABLE 17-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Comparator Specifications Operating temperature -40°C  TA  +125°C Param. Sym. Characteristics Min. Typ. Max. Units Comments No. CM01 VOS Input Offset Voltage —  5.0  10 mV CM02 VCM Input Common Mode Voltage 0 — VDD - 1.5 V CM03* CMRR Common Mode Rejection Ratio +55 — — db CM04* TRT Response Time Falling — 150 600 ns (Note 1) Rising — 200 1000 ns CM05* TMC2COV Comparator Mode Change to Output — — 10 s Valid * These parameters are characterized but not tested. Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV. TABLE 17-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristics Min. Typ† Max. Units Comments No. CV01* CLSB Step Size(2) — VDD/24 — V Low Range (VRR = 1) — VDD/32 — V High Range (VRR = 0) CV02* CACC Absolute Accuracy — —  1/2 LSb Low Range (VRR = 1) — — 1/2 LSb High Range (VRR = 0) CV03* CR Unit Resistor Value (R) — 2k —  CV04* CST Settling Time(1) — — 10 s * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. 2: See Section8.10 “Comparator Voltage Reference” for more information. TABLE 17-9: VOLTAGE (VR) REFERENCE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VR Voltage Reference Specifications Operating temperature -40°C  TA  +125°C Param Symbol Characteristics Min. Typ. Max. Units Comments No. VR01 VROUT VR voltage output 0.5 0.6 0.7 V VR02* TSTABLE Settling Time — 10 100* s * These parameters are characterized but not tested. DS40001262F-page 242  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 17-10: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RB7/TX/CK pin 121 121 RB5/AN11/RX/DT pin 120 122 Note: Refer to Figure17-3 for load conditions. TABLE 17-10: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. 120 TCKH2DTV SYNC XMIT (Master & Slave) — 40 ns Clock high to data-out valid 121 TCKRF Clock out rise time and fall time (Master mode) — 20 ns 122 TDTRF Data-out rise time and fall time — 20 ns FIGURE 17-11: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RB7/TX/CK pin 125 RB5/AN11/RX/DT pin 126 Note: Refer to Figure17-3 for load conditions. TABLE 17-11: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. 125 TDTV2CKL SYNC RCV (Master & Slave) Data-hold before CK  (DT hold time) 10 — ns 126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns  2005-2015 Microchip Technology Inc. DS40001262F-page 243

PIC16F631/677/685/687/689/690 FIGURE 17-12: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure17-3 for load conditions. FIGURE 17-13: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure17-3 for load conditions. DS40001262F-page 244  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 17-14: SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure17-3 for load conditions. FIGURE 17-15: SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure17-3 for load conditions.  2005-2015 Microchip Technology Inc. DS40001262F-page 245

PIC16F631/677/685/687/689/690 TABLE 17-12: SPI MODE REQUIREMENTS Param Symbol Characteristic Min. Typ† Max. Units Conditions No. 70* TSSL2SCH, SS to SCK or SCK input TCY — — ns TSSL2SCL 71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns 72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns 73* TDIV2SCH, Setup time of SDI data input to SCK edge 100 — — ns TDIV2SCL 74* TSCH2DIL, Hold time of SDI data input to SCK edge 100 — — ns TSCL2DIL 75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns 2.0-5.5V — 25 50 ns 76* TDOF SDO data output fall time — 10 25 ns 77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns 78* TSCR SCK output rise time 3.0-5.5V — 10 25 ns (Master mode) 2.0-5.5V — 25 50 ns 79* TSCF SCK output fall time (Master mode) — 10 25 ns 80* TSCH2DOV, SDO data output valid after 3.0-5.5V — — 50 ns TSCL2DOV SCK edge 2.0-5.5V — — 145 ns 81* TDOV2SCH, SDO data output setup to SCK edge Tcy — — ns TDOV2SCL 82* TSSL2DOV SDO data output valid after SS edge — — 50 ns 83* TSCH2SSH, SS after SCK edge 1.5TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 17-16: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure17-3 for load conditions. DS40001262F-page 246  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 17-13: I2C™ BUS START/STOP BITS REQUIREMENTS Param Symbol Characteristic Min. Typ. Max. Units Conditions No. 90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — Start condition 91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first Hold time 400 kHz mode 600 — — clock pulse is generated 92* TSU:STO Stop condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO Stop condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. FIGURE 17-17: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure17-3 for load conditions.  2005-2015 Microchip Technology Inc. DS40001262F-page 247

PIC16F631/677/685/687/689/690 TABLE 17-14: I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. 100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP Module 1.5TCY — 101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP Module 1.5TCY — 102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF 103* TF SDA and SCL fall 100 kHz mode — 300 ns time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF 90* TSU:STA Start condition 100 kHz mode 4.7 — s Only relevant for setup time 400 kHz mode 0.6 — s Repeated Start condition 91* THD:STA Start condition hold 100 kHz mode 4.0 — s After this period the first time 400 kHz mode 0.6 — s clock pulse is generated 106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2) time 400 kHz mode 100 — ns 92* TSU:STO Stop condition 100 kHz mode 4.7 — s setup time 400 kHz mode 0.6 — s 109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns 110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free before a new transmission 400 kHz mode 1.3 — s can start CB Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT=1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS40001262F-page 248  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 17-15: A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD01 NR Resolution — — 10 bits bit AD02 EIL Integral Error — — 1 LSb VREF = 5.12V AD03 EDL Differential Error — — 1 LSb No missing codes to 10 bits VREF = 5.12V AD04 EOFF Offset Error — — 1 LSb VREF = 5.12V AD04A — +1.5 +3.0 LSb (PIC16F677 only) AD07 EGN Gain Error — — 1 LSb VREF = 5.12V AD06 VREF Reference Voltage(3) 2.2 — — V AD06A 2.5 VDD Absolute minimum to ensure 1LSb accuracy AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended — — 10 k Impedance of Analog Voltage Source AD09* IREF VREF Input Current(3) 10 — 1000 A During VAIN acquisition. Based on differential of VHOLD to VAIN. — — 50 A During A/D conversion cycle * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input. 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module.  2005-2015 Microchip Technology Inc. DS40001262F-page 249

PIC16F631/677/685/687/689/690 FIGURE 17-18: A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 134 (TOSC/2)(1) 1 TCY 131 Q4 130 A/D CLK A/D Data 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped Sample 132 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 17-16: A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 130* TAD A/D Clock Period 1.5 — — s TOSC-based, VREF 2.5V 3.0* — — s TOSC-based, VREF full range A/D Internal RC ADCS<1:0> = 11 (RC mode) Oscillator Period 3.0* 6.0 9.0* s At VDD = 2.5V 2.0* 4.0 6.0* s At VDD = 5.0V 131 TCNV Conversion Time — 11 — TAD Set GO bit to new data in A/D Result (not including register Acquisition Time)(1) 132* TACQ Acquisition Time (2) 11.5 — s 5* — — s The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 4.1mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). 134 TGO Q4 to A/D Clock — TOSC/2 — — If the A/D clock source is selected as Start RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Table9-1 for minimum conditions. DS40001262F-page 250  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 17-19: A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO 134 (TOSC/2 + TCY)(1) 1 TCY 131 Q4 130 A/D CLK A/D Data 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped Sample 132 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 1: A/D CONVERSION REQUIREMENTS (SLEEP MODE) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 130* TAD A/D Internal RC ADCS<1:0> = 11 (RC mode) Oscillator Period 3.0* 6.0 9.0* s At VDD = 2.5V 2.0* 4.0 6.0* s At VDD = 5.0V 131 TCNV Conversion Time — 11 — TAD (not including Acquisition Time)(1) 132* TACQ Acquisition Time (2) 11.5 — s 5* — — s The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 4.1 mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). 134 TGO Q4 to A/D Clock — TOSC/2 + TCY — — If the A/D clock source is selected Start as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Table9-1 for minimum conditions.  2005-2015 Microchip Technology Inc. DS40001262F-page 251

PIC16F631/677/685/687/689/690 17.8 High Temperature Operation Note1: Writes are not allowed for Flash This section outlines the specifications for the following program memory above 125°C. devices operating in the high temperature range between -40°C and 150°C.(4) 2: All AC timing specifications are increased by 30%. This derating factor will include • PIC16F685 parameters such as TPWRT. • PIC16F687 3: The temperature range indicator in the • PIC16F689 catalog part number and device marking • PIC16F690 is “H” for -40°C to 150°C. When the value of any parameter is identical for both Example: PIC16F685T-H/SS indicates the 125°C Extended and the 150°C High Temp. the device is shipped in a Tape and reel temperature ranges, then that value will be found in the configuration, in the SSOP package, and standard specification tables shown earlier in this is rated for operation from -40°C to chapter, under the fields listed for the 125°C Extended 150°C. temperature range. If the value of any parameter is 4: AEC-Q100 reliability testing for devices unique to the 150°C High Temp. temperature range, intended to operate at 150°C is 1,000 then it will be listed here, in this section of the data hours. Any design in which the total oper- sheet. ating time from 125°C to 150°C will be If a Silicon Errata exists for the product and it lists a greater than 1,000 hours is not warranted modification to the 125°C Extended temperature range without prior written approval from value, one that is also shared at the 150°C High Temp. Microchip Technology Inc. temperature range, then that modified value will apply 5: Endurance of the data EEPROM to both temperature ranges. decreases with increasing temperature. It is recommended that the number of pro- gramming cycles to any individual address at temperatures above +125°C not exceed 25,000. Error correction tech- niques are advised for data requiring more programming cycles above +125°C. 6: DS80243 Table 1 refers to various revi- sions of the PIC16F685, but operation above +125°C will only be available for revision A6 or later. 7: The +150°C version of the PIC16F685 will not be offered in PDIP. It will only be offered in SSOP, SOIC, and QFN. TABLE 17-17: ABSOLUTE MAXIMUM RATINGS Parameter Source/Sink Value Units Max. Current: VDD Source 20 mA Max. Current: VSS Sink 50 mA Max. Current: Pin Source 5 mA Max. Current: Pin Sink 10 mA Max. Pin Current: at VOH Source 3 mA Max. Pin Current: at VOL Sink 8.5 mA Max. Port Current: A, B, and C Source 20 mA combined Max. Port Current: A, B, and C Sink 50 mA combined Max. Junction Temperature 155 °C Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001262F-page 252  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 17-20: VOLTAGE-FREQUENCY GRAPH, -40°C  TA  +150°C 6.0 5.5 5.0 V) 4.5 ( D D V 4.0 3.5 3.0 2.5 0 8 10 20 Frequency (MHz) Note1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 17-21: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 150 ± 7.5% 125 ± 5% 85 C) ± 2% ° 60 ( e r u t a r e p 25 ± 1% m e T 0 -40 2.1 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2005-2015 Microchip Technology Inc. DS40001262F-page 253

PIC16F631/677/685/687/689/690 TABLE 17-18: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V, VREF > 2.5V) ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns 250 ns 500 ns 2.0 s Fosc/4 100 200 ns 500 ns 1.0 s 4.0 s Fosc/8 001 400 ns 1.0 s 2.0 s 8.0 s Fosc/16 101 800 ns 2.0 s 4.0 s 16.0 s Fosc/32 010 1.6 s 4.0 s 8.0 s 32.0 s Fosc/64 110 3.2 s 8.0 s 16.0 s 64.0 s Frc x11 2-6 s 2-6 s 2-6 s 2-6 s Legend: Shaded cells should not be used for conversions at temperatures above +125°C. Note 1: TAD must be between 1.6 s and 4.0 s. DS40001262F-page 254  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 17-19: DC CHARACTERISTICS FOR IDD SPECIFICATIONS FOR PIC16F685/687/689/690-H (High Temp.) Condition Param Device Min. Typ. Max. Units No. Characteristics VDD Note D001 VDD 2.1 — 5.5 V — FOSC  8 MHz: HFINTOSC, EC 2.1 — 5.5 V — FOSC  4 MHz D010 Supply Current (IDD) — — 47 2.1 Fosc = 32 kHz — — 69 A 3.0 LP Oscillator — — 108 5.0 D011 — — 357 2.1 Fosc = 1 MHz — — 533 A 3.0 XT Oscillator — — 729 5.0 D012 — — 535 2.1 A Fosc = 4 MHz — — 875 3.0 XT Oscillator — — 1.32 mA 5.0 D013 — — 336 2.1 Fosc = 1 MHz — — 477 A 3.0 EC Oscillator — — 777 5.0 D014 — — 505 2.1 A Fosc = 4 MHz — — 724 3.0 EC Oscillator — — 1.30 mA 5.0 D015 — — 51 2.1 A Fosc = 31 kHz — — 92 3.0 LFINTOSC — — 117 mA 5.0 D016 — — 665 2.1 A Fosc = 4 MHz — — 970 3.0 HFINTOSC — — 1.56 mA 5.0 D017 — — 936 A 2.1 Fosc = 8 MHz — — 1.34 3.0 mA HFINTOSC — — 2.27 5.0 D018 — — 605 2.1 A Fosc = 4 MHz — — 903 3.0 EXTRC — — 1.43 mA 5.0 D019 — — 6.61 4.5 Fosc = 20 MHz mA — — 7.81 5.0 HS Oscillator  2005-2015 Microchip Technology Inc. DS40001262F-page 255

PIC16F631/677/685/687/689/690 TABLE 17-20: DC CHARACTERISTICS FOR IPD SPECIFICATIONS FOR PIC16F685/687/689/690-H (High Temp.) Condition Param Device Units Min. Typ. Max. No. Characteristics VDD Note D020E Power Down Base — — 27 2.1 IPD Base: WDT, BOR, Current (IPD) — — 29 A 3.0 Comparators, VREF and — — 32 5.0 T1OSC disabled D021E — — 55 2.1 — — 59 A 3.0 WDT Current — — 69 5.0 D022E — — 75 3.0 A BOR Current — — 147 5.0 D023E — — 73 2.1 Comparator current, both — — 117 A 3.0 comparators enabled — — 235 5.0 D024E — — 102 2.1 — — 128 A 3.0 CVREF current, high range — — 170 5.0 D024AE — — 133 2.1 — — 167 A 3.0 CVREF current, low range — — 222 5.0 D025E — — 36 2.1 — — 41 A 3.0 T1OSC current, 32 kHz — — 47 5.0 D026E — — 22 3.0 Analog-to-Digital current, A — — 24 5.0 no conversion in progress D027E — — 189 3.0 VP6 current (Fixed Voltage A — — 250 5.0 Reference) TABLE 17-21: LEAKAGE CURRENT SPECIFICATIONS FOR PIC16F685/687/689/690-H (High Temp.) Param Sym. Characteristic Min. Typ. Max. Units Conditions No. D061 IIL Input Leakage Current(1) — ±0.5 ±5.0 µA VSS VPIN VDD (RA3/MCLR) D062 IIL Input Leakage Current(2) 50 250 400 µA VDD = 5.0V (RA3/MCLR) Note 1: This specification applies when RA3/MCLR is configured as an input with the pull-up disabled. The leakage current for the RA3/MCLR pin is higher than for the standard I/O port pins. 2: This specification applies when RA3/MCLR is configured as the MCLR reset pin function with the weak pull-up enabled. TABLE 17-22: DATA EEPROM MEMORY ENDURANCE SPECIFICATIONS FOR PIC16F685/687/689/690-H (High Temp.) Param Sym. Characteristic Min. Typ. Max. Units Conditions No. D120A ED Byte Endurance 5K 50K — E/W 126°C TA 150°C DS40001262F-page 256  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 TABLE 17-23: OSCILLATOR PARAMETERS FOR PIC16F685/687/689/690-H (High Temp.) Param Frequency Sym. Characteristic Min. Typ. Max. Units Conditions No. Tolerance OS08 INTOSC Int. Calibrated INTOSC ±7.5% 7.4 8.0 8.6 MHz 2.1V VDD 5.5V Freq.(1) -40°C TA 150°C Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended. TABLE 17-24: WATCHDOG TIMER SPECIFICATIONS FOR PIC16F685/687/689/690-H (High Temp.) Param Sym. Characteristic Min. Typ. Max. Units Conditions No. 31 TWDT Watchdog Timer Time-out Period 10 20 70 ms 150°C Temperature (No Prescaler) TABLE 17-25: BROWN-OUT RESET SPECIFICATIONS FOR PIC16F685/687/689/690-H (High Temp.) Param Sym. Characteristic Min. Typ. Max. Units Conditions No. 35 VBOR Brown-Out Reset Voltage 2.0 — 2.3 V 150°C Temperature TABLE 17-26: COMPARATOR SPECIFICATIONS FOR PIC16F685/687/689/690-H (High Temp.) Param Sym. Characteristic Min. Typ. Max. Units Conditions No. CM01 VOS Input Offset Voltage — ±5 ±20 mV (VDD - 1.5)/2  2005-2015 Microchip Technology Inc. DS40001262F-page 257

PIC16F631/677/685/687/689/690 18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean+3) or (mean-3) respectively, where  is a standard deviation, over each temperature range. FIGURE 18-1: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 3.5 Typical: Statistical Mean @25°C 3.0 Maximum: Mean (Worst-case Temp) + 3 5.5V (-40°C to 125°C) 5.0V 2.5 A) 2.0 4.0V m (D D 1.5 I 3.0V 1.0 2.0V 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz FOSC DS40001262F-page 258  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EC Mode 4.0 Typical: Statistical Mean @25°C 5.5V 3.5 Maximum: Mean (Worst-cas e Temp) + 3 (-40°C to 125°C) 5.0V 3.0 2.5 4.0V A) m 2.0 (D D I 3.0V 1.5 2.0V 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz FOSC FIGURE 18-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) Typical IDD vs FOSC Over Vdd HS Mode 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-ca se Temp) + 3 (-40°C to 125°C) 5.5V 3.0 5.0V 2.5 4.5V A) m 2.0 (D D I 1.5 4.0V 1.0 3.5V 3.0V 0.5 0.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC  2005-2015 Microchip Technology Inc. DS40001262F-page 259

PIC16F631/677/685/687/689/690 FIGURE 18-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) Maximum IDD vs FOSC Over Vdd HS Mode 5.0 Typical: Statistical Mean @25°C 4.5 Maximum: Mean (Worst-case Temp) + 3 4.0 (-40°C to 125°C) 5.5V 3.5 5.0V 3.0 A) 4.5V m 2.5 (D D I 2.0 1.5 4.0V 3.5V 1.0 3.0V 0.5 0.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC FIGURE 18-5: TYPICAL IDD vs. VDD OVER FOSC (XT MODE) XT Mode 900 Typical: Statistical Mean @25°C 800 Maximum: Mean (Worst-ca se Temp) + 3 (-40°C to 125°C) 700 600 A) 500  4 MHz (D D 400 I 300 1 MHz 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001262F-page 260  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE) XT Mode 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 1,000 800 A)  4 MHz (D ID 600 400 1 MHz 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-7: IDD vs. VDD (LP MODE) 80 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3 70 (-40°C to 125°C) 60 A) 50 u 32 kHz Maximum (D D 40 I 30 32 kHz Typical 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2005-2015 Microchip Technology Inc. DS40001262F-page 261

PIC16F631/677/685/687/689/690 FIGURE 18-8: TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE) EXTRC Mode 800 Typical: Statistical Mean @25°C 700 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 600 500 4 MHz A)  400 (D D I 300 1 MHz 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-9: MAXIMUM IDD vs. VDD OVER FOSC (EXTRC MODE) EXTRC Mode 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 1,000 4 MHz 800 A)  (D ID 600 400 1 MHz 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001262F-page 262  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-10: IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz) LFINTOSC Mode, 31KHZ 80 Typical: Statistical Mean @25°C 70 Maximum: Mean (Worst-c ase Temp) + 3 (-40°C to 125°C) 60 50 Maximum A) (D 40 D I 30 Typical 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 1,600 Typical: Statistical Mean @25°C 5.5V 1,400 Maximum: Mean (Worst-c ase Temp) + 3 (-40°C to 125°C) 5.0V 1,200 1,000 4.0V A) (D 800 D 3.0V I 600 2.0V 400 200 0 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC  2005-2015 Microchip Technology Inc. DS40001262F-page 263

PIC16F631/677/685/687/689/690 FIGURE 18-12: MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 2,000 Typical: Statistical Mean @25°C 5.5V 1,800 Maximum: Mean (Worst-c ase Temp) + 3 (-40°C to 125°C) 5.0V 1,600 1,400 1,200 4.0V A) (DD 1,000 3.0V I 800 600 2.0V 400 200 0 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC FIGURE 18-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 0.35 0.30 A) 0.25  (D P 0.20 I 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001262F-page 264  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-14: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 Typical: Statistical Mean @25°C 16.0 MMaaxxiimmuumm:: MMeeaann +(W 3orst-case Temp) + 3 (-40°C to 125°C) 14.0 Max. 125°C 12.0 A) 10.0  (D P 8.0 I 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-15: COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED) 180 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3 140 (-40°C to 125°C) 120 Maximum A) 100 (D Typical P 80 I 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2005-2015 Microchip Technology Inc. DS40001262F-page 265

PIC16F631/677/685/687/689/690 FIGURE 18-16: BOR IPD vs. VDD OVER TEMPERATURE 160 Typical: Statistical Mean @25°C 140 Maximum: Mean (Worst-ca se Temp) + 3 (-40°C to 125°C) 120 100 Maximum A)  (D 80 P I Typical 60 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-17: TYPICAL WDT IPD vs. VDD OVER TEMPERATURE Typical 3.0 TTyyppicicaal:l: SSttaattisistticicaal l MMeeaann @@2255°°CC Maximum: Mean (Worst-case Temp) + 3 2.5 (-40°C to 125°C) 2.0 A) (D 1.5 P I 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001262F-page 266  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 20.0 Max. 125°C 15.0 Typical: Statistical Mean @25°C A) Maximum: Mean (Worst-case Temp) + 3  (D (-40°C to 125°C) P I 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-19: WDT PERIOD vs. VDD OVER TEMPERATURE 30 Typical: Statistical Mean @25°C 28 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) Max. (125°C) 26 Max. (85°C) 24 22 s) m e ( 20 m Ti Typical 18 16 14 Minimum 12 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2005-2015 Microchip Technology Inc. DS40001262F-page 267

PIC16F631/677/685/687/689/690 FIGURE 18-20: WDT PERIOD vs. TEMPERATURE OVER VDD (5.0V) Vdd = 5V 30 Typical: Statistical Mean @25°C 28 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 26 Maximum 24 22 s) m e ( 20 m Typical Ti 18 16 Minimum 14 12 10 -40°C 25°C 85°C 125°C Temperature (°C) FIGURE 18-21: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE) High Range 140 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3 120 (-40°C to 125°C) 100 Max. 125°C 80 A) (D Max. 85°C IP 60 Typical 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001262F-page 268  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-22: CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE) 180 Typical: Statistical Mean @25°C 160 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 140 120 Max. 125°C A) 100 (D Max. 85°C P 80 I Typical 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-23: TYPICAL VP6 REFERENCE IPD vs. VDD (25°C) VP6 Reference IPD vs. VDD (25×C) 160 140 120 100 A) Typical u D ( 80 P I 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2005-2015 Microchip Technology Inc. DS40001262F-page 269

PIC16F631/677/685/687/689/690 FIGURE 18-24: MAXIMUM VP6 REFERENCE IPD vs. VDD OVER TEMPERATURE Max VP6 Reference IPD vs. VDD Over Temperature 180 160 140 Max 125C 120 ) Max 85C A 100 u ( D P 80 I 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-25: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz) 30 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3 25 (-40°C to 125°C) Max. 125°C 20 A) u 15 (D Typ 25×C Max 85×C Max 125×C P I 2 2.022 4.98 17.54 2.5 2.247 5.23 19.02 10 3 2.472 5.49 20.29 3.5 2.453 5.79 21.50 Max. 85°C 4 2.433 6.08 22.45 4.5 2.711 6.54 23.30 5 5 2.989 7.00 24.00 5.5 3.112 7.34 Typ. 25°C 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001262F-page 270  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-26: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) Max. 125°C 0.6 0.5 Max. 85°C V) (L 0.4 O V 0.3 Typical 25°C 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 18-27: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C 0.40 MaximTuympi:c aMl:e Santa (tiWstoicraslt -Mcaesaen T@em25p×) C+ 3 Maximum: Mea s( -+4 03×C to 125×C) (-40°C to 125°C) Max. 125°C 0.35 Max. 85°C 0.30 0.25 V) (L Typ. 25°C O V 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA)  2005-2015 Microchip Technology Inc. DS40001262F-page 271

PIC16F631/677/685/687/689/690 FIGURE 18-28: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C 2.0 V) (H O V 1.5 Typical: Statistical Mean @25°C 1.0 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 18-29: VOH vs. IOH OVER TE(MPERAT, URE (VDD = 5).0V) 5.5 5.0 Max. -40°C Typ. 25°C 4.5 V) Min. 125°C (H O V 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) DS40001262F-page 272  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-30: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (TTL Input, -40×C TO 125×C) 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) Max. -40°C 1.3 Typ. 25°C V) (N 1.1 VI Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-31: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) VIH Min. -40°C 3.0 2.5 V) (N VI 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2005-2015 Microchip Technology Inc. DS40001262F-page 273

PIC16F631/677/685/687/689/690 FIGURE 18-32: COMPARATOR RESPONSE TIME (RISING EDGE) 531 806 1000 900 800 Max. 125°C 700 S) n e ( 600 Note: VCM = VDD - 1.5V)/2 m Ti V+ input = VCM Max. 85°C e 500 V- input = Transition from VCM + 100MV to VCM - 20MV s n o p 400 s e R 300 200 Typ. 25°C Min. -40°C 100 0 2.0 2.5 4.0 5.5 VDD (V) FIGURE 18-33: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 800 Max. 125°C 700 S) n 600 Note: VCM = VDD - 1.5V)/2 me ( V+ input = VCM Max. 85°C Ti 500 V- input = Transition from VCM - 100MV to VCM + 20MV e s n 400 o p s Re 300 Typ. 25°C 200 Min. -40°C 100 0 2.0 2.5 4.0 5.5 VDD (V) DS40001262F-page 274  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-34: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz) LFINTOSC 31Khz 45,000 40,000 Max. -40°C 35,000 Typ. 25°C 30,000 z) H y ( 25,000 c n e qu 20,000 Min. 85°C e r F Min. 125°C 15,000 10,000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3 5,000 (-40°C to 125°C) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-35: ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3 125°C (-40°C to 125°C) 6 85°C s)  25°C e ( 4 m Ti -40°C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2005-2015 Microchip Technology Inc. DS40001262F-page 275

PIC16F631/677/685/687/689/690 FIGURE 18-36: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 16 Typical: Statistical Mean @25°C 14 Maximum: Mean (Worst-case Temp) + 3 85°C (-40°C to 125°C) 12 25°C 10 s) -40°C  e ( 8 m Ti 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-37: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 25 Typical: Statistical Mean @25°C 20 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 15 s) 85°C  e ( m Ti 25°C 10 -40°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001262F-page 276  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-38: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 10 9 Typical: Statistical Mean @25°C 8 Maximum: Mean (Worst-case Temp) + 3 (-40°C to 125°C) 7 85°C 6 s) 25°C  e ( 5 m Ti -40°C 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 3 2 %) n ( 1 o ati br 0 ali m C -1 o e fr -2 g n a -3 h C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2005-2015 Microchip Technology Inc. DS40001262F-page 277

PIC16F631/677/685/687/689/690 FIGURE 18-40: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C) 5 4 3 %) n ( 2 o ati 1 r b Cali 0 m o -1 r e f ng -2 a h C -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-41: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 3 %) 2 n ( o 1 ati r alib 0 C m -1 o r e f -2 g n ha -3 C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD ( V) DS40001262F-page 278  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-42: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 3 %) 2 n ( o 1 ati r b 0 ali C m -1 o r e f -2 g n ha -3 C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD ( V) FIGURE 18-43: TYPICAL VP6 REFERENCE VOLTAGE vs. VDD (25°C) VP6 Reference Voltage vs. VDD (25×C) 0.65 0.64 0.63 0.62 0.61 ) V ( 6 0.60 P V 0.59 Typical 0.58 0.57 0.56 0.55 2 3 4 5 5.5 VDD (V)  2005-2015 Microchip Technology Inc. DS40001262F-page 279

PIC16F631/677/685/687/689/690 FIGURE 18-44: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (3V) Typical VP6 Reference Voltage vs. Temperature (VDD=3V) 0.66 0.64 Max. 0.62 V) 0.6 ( 6 P Typical V 0.58 Min. 0.56 0.54 0.52 -40°C 25°C 85°C 125°C Temperature (°C) FIGURE 18-45: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (5V) Typical VP6 Reference Voltage vs. Temperature (VDD=5V) 0.66 0.64 0.62 Max. V) 0.6 ( 6 P V 0.58 Typical 0.56 Min. 0.54 0.52 -40 °C 25 °C 85 °C 125 °C Temperature (°C) DS40001262F-page 280  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-46: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 25°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 25×C) 35 Parts=118 30 25 s rt a P of 20 r e b m 15 u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V) FIGURE 18-47: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 85°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 85×C) 40 35 Parts=118 30 s rt a P 25 of r e 20 b m u N 15 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V)  2005-2015 Microchip Technology Inc. DS40001262F-page 281

PIC16F631/677/685/687/689/690 FIGURE 18-48: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 125°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 125×C) 40 35 Parts=118 30 s rt a P 25 of r e 20 b m u N 15 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V) FIGURE 18-49: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, -40°C) Typical VP6 Reference Voltage Distribution (VDD=3V, -40×C) 30 Parts=118 25 s t 20 r a P f o r e 15 b m u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V) DS40001262F-page 282  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 FIGURE 18-50: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 25°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C) 30 25 Parts=118 s rt 20 a P f o r e 15 b m u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V) FIGURE 18-51: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 85°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 85×C) 35 30 Parts=118 25 s rt a P of 20 r e b m 15 u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V)  2005-2015 Microchip Technology Inc. DS40001262F-page 283

PIC16F631/677/685/687/689/690 FIGURE 18-52: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 125°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C) 30 25 Parts=118 s rt 20 a P of r e 15 b m u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V) FIGURE 18-53: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, -40°C) Typical VP6 Reference Voltage Distribution (VDD=5V, -40×C) 30 25 Parts=118 s rt 20 a P of r e 15 b m u N 10 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. Voltage (V) DS40001262F-page 284  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 19.0 PACKAGING INFORMATION 19.1 Package Marking Information 20-Lead PDIP Example XXXXXXXXXXXXXXXXX PIC16F685-I/P e3 XXXXXXXXXXXXXXXXX 0710017 YYWWNNN 20-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXX PIC16F685-I XXXXXXXXXXXXXX /SO e3 XXXXXXXXXXXXXX 0710017 YYWWNNN 20-Lead SSOP Example XXXXXXXXXXX PIC16F687 XXXXXXXXXXX -I/SSe3 YYWWNNN 0710017 20-Lead QFN Example XXXXXX 16F690 XXXXXX -I/ML e3 YWWNNN 710017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2005-2015 Microchip Technology Inc. DS40001262F-page 285

PIC16F631/677/685/687/689/690 19.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)(cid:10)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:3)(cid:3)(cid:9)(cid:24)(cid:14)(cid:11)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)(cid:10)(cid:16)(cid:18)(cid:10)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)255***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’5(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) (cid:14) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:25)(cid:19)&! (cid:28)7,8.(cid:3) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:14)9(cid:19)’(cid:19)&! (cid:18)(cid:28)7 7:(cid:18) (cid:18)(cid:7); 7"’)(cid:13)(cid:21)(cid:14)(cid:22)%(cid:14)(cid:31)(cid:19)(cid:25)! 7 (cid:16)(cid:4) (cid:31)(cid:19)&(cid:20)(cid:23) (cid:13) (cid:29)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3), (cid:24)(cid:22)(cid:10)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7) < < (cid:29)(cid:16)(cid:30)(cid:4) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:7)(cid:16) (cid:29)(cid:30)(cid:30)(cid:15) (cid:29)(cid:30)-(cid:4) (cid:29)(cid:30)(cid:6)(cid:15) 1(cid:11)!(cid:13)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7)(cid:30) (cid:29)(cid:4)(cid:30)(cid:15) < < (cid:3)(cid:23)(cid:22)"(cid:26)#(cid:13)(cid:21)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:23)(cid:22)"(cid:26)#(cid:13)(cid:21)(cid:14)=(cid:19)#&(cid:23) . (cid:29)-(cid:4)(cid:4) (cid:29)-(cid:30)(cid:4) (cid:29)-(cid:16)(cid:15) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)=(cid:19)#&(cid:23) .(cid:30) (cid:29)(cid:16)(cid:5)(cid:4) (cid:29)(cid:16)(cid:15)(cid:4) (cid:29)(cid:16)>(cid:4) : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2) (cid:29)(cid:6)>(cid:4) (cid:30)(cid:29)(cid:4)-(cid:4) (cid:30)(cid:29)(cid:4)?(cid:4) (cid:24)(cid:19)(cid:10)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) 9 (cid:29)(cid:30)(cid:30)(cid:15) (cid:29)(cid:30)-(cid:4) (cid:29)(cid:30)(cid:15)(cid:4) 9(cid:13)(cid:11)#(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:20) (cid:29)(cid:4)(cid:4)> (cid:29)(cid:4)(cid:30)(cid:4) (cid:29)(cid:4)(cid:30)(cid:15) 6(cid:10)(cid:10)(cid:13)(cid:21)(cid:14)9(cid:13)(cid:11)#(cid:14)=(cid:19)#&(cid:23) )(cid:30) (cid:29)(cid:4)(cid:5)(cid:15) (cid:29)(cid:4)?(cid:4) (cid:29)(cid:4)(cid:17)(cid:4) 9(cid:22)*(cid:13)(cid:21)(cid:14)9(cid:13)(cid:11)#(cid:14)=(cid:19)#&(cid:23) ) (cid:29)(cid:4)(cid:30)(cid:5) (cid:29)(cid:4)(cid:30)> (cid:29)(cid:4)(cid:16)(cid:16) : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)(cid:8)(cid:22)*(cid:14)(cid:3)(cid:10)(cid:11)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:14)+ (cid:13)1 < < (cid:29)(cid:5)-(cid:4) (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:30)(cid:29) (cid:31)(cid:19)(cid:25)(cid:14)(cid:30)(cid:14) (cid:19)!"(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:21)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14) (cid:11)(cid:21)(cid:27)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)*(cid:19)&(cid:23)(cid:19)(cid:25)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)&(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) +(cid:14)(cid:3)(cid:19)(cid:12)(cid:25)(cid:19)%(cid:19)(cid:20)(cid:11)(cid:25)&(cid:14),(cid:23)(cid:11)(cid:21)(cid:11)(cid:20)&(cid:13)(cid:21)(cid:19)!&(cid:19)(cid:20)(cid:29) -(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:25)#(cid:14).(cid:30)(cid:14)#(cid:22)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)"#(cid:13)(cid:14)’(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:29)(cid:14)(cid:18)(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:14)!(cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:13)$(cid:20)(cid:13)(cid:13)#(cid:14)(cid:29)(cid:4)(cid:30)(cid:4)/(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)!(cid:19)#(cid:13)(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)#(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18).(cid:14)0(cid:30)(cid:5)(cid:29)(cid:15)(cid:18)(cid:29) 1(cid:3),2 1(cid:11)!(cid:19)(cid:20)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)&(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)$(cid:11)(cid:20)&(cid:14) (cid:11)(cid:26)"(cid:13)(cid:14)!(cid:23)(cid:22)*(cid:25)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)!(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12),(cid:4)(cid:5)(cid:9)(cid:4)(cid:30)(cid:6)1 DS40001262F-page 286  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2015 Microchip Technology Inc. DS40001262F-page 287

PIC16F631/677/685/687/689/690 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001262F-page 288  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2015 Microchip Technology Inc. DS40001262F-page 289

PIC16F631/677/685/687/689/690 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9) !"(cid:14)(cid:19)#(cid:9) (cid:24)(cid:7)(cid:11)(cid:11)(cid:9)$(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20) (cid:21)(cid:9)(cid:22)(cid:9)%&(cid:23)(cid:3)(cid:9)(cid:24)(cid:24)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28) $(cid:10)(cid:29)(cid:9) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)255***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’5(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) D N E E1 NOTE1 1 2 e b c A A2 φ A1 L1 L 6(cid:25)(cid:19)&! (cid:18)(cid:28)99(cid:28)(cid:18).(cid:24).(cid:8)(cid:3) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:14)9(cid:19)’(cid:19)&! (cid:18)(cid:28)7 7:(cid:18) (cid:18)(cid:7); 7"’)(cid:13)(cid:21)(cid:14)(cid:22)%(cid:14)(cid:31)(cid:19)(cid:25)! 7 (cid:16)(cid:4) (cid:31)(cid:19)&(cid:20)(cid:23) (cid:13) (cid:4)(cid:29)?(cid:15)(cid:14)1(cid:3), : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)8(cid:13)(cid:19)(cid:12)(cid:23)& (cid:7) < < (cid:16)(cid:29)(cid:4)(cid:4) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:7)(cid:16) (cid:30)(cid:29)?(cid:15) (cid:30)(cid:29)(cid:17)(cid:15) (cid:30)(cid:29)>(cid:15) (cid:3)&(cid:11)(cid:25)#(cid:22)%%(cid:14) (cid:7)(cid:30) (cid:4)(cid:29)(cid:4)(cid:15) < < : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)=(cid:19)#&(cid:23) . (cid:17)(cid:29)(cid:5)(cid:4) (cid:17)(cid:29)>(cid:4) >(cid:29)(cid:16)(cid:4) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)=(cid:19)#&(cid:23) .(cid:30) (cid:15)(cid:29)(cid:4)(cid:4) (cid:15)(cid:29)-(cid:4) (cid:15)(cid:29)?(cid:4) : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2) ?(cid:29)(cid:6)(cid:4) (cid:17)(cid:29)(cid:16)(cid:4) (cid:17)(cid:29)(cid:15)(cid:4) 3(cid:22)(cid:22)&(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) 9 (cid:4)(cid:29)(cid:15)(cid:15) (cid:4)(cid:29)(cid:17)(cid:15) (cid:4)(cid:29)(cid:6)(cid:15) 3(cid:22)(cid:22)&(cid:10)(cid:21)(cid:19)(cid:25)& 9(cid:30) (cid:30)(cid:29)(cid:16)(cid:15)(cid:14)(cid:8).3 9(cid:13)(cid:11)#(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:20) (cid:4)(cid:29)(cid:4)(cid:6) < (cid:4)(cid:29)(cid:16)(cid:15) 3(cid:22)(cid:22)&(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13) (cid:3) (cid:4)@ (cid:5)@ >@ 9(cid:13)(cid:11)#(cid:14)=(cid:19)#&(cid:23) ) (cid:4)(cid:29)(cid:16)(cid:16) < (cid:4)(cid:29)-> (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:30)(cid:29) (cid:31)(cid:19)(cid:25)(cid:14)(cid:30)(cid:14) (cid:19)!"(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:21)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14) (cid:11)(cid:21)(cid:27)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)*(cid:19)&(cid:23)(cid:19)(cid:25)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)&(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:25)#(cid:14).(cid:30)(cid:14)#(cid:22)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)"#(cid:13)(cid:14)’(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:29)(cid:14)(cid:18)(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:14)!(cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:13)$(cid:20)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:29)(cid:16)(cid:4)(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)!(cid:19)#(cid:13)(cid:29) -(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)#(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18).(cid:14)0(cid:30)(cid:5)(cid:29)(cid:15)(cid:18)(cid:29) 1(cid:3),2 1(cid:11)!(cid:19)(cid:20)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)&(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)$(cid:11)(cid:20)&(cid:14) (cid:11)(cid:26)"(cid:13)(cid:14)!(cid:23)(cid:22)*(cid:25)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)!(cid:29) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)((cid:14)"!"(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)((cid:14)%(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)%(cid:22)(cid:21)’(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)"(cid:21)(cid:10)(cid:22)!(cid:13)!(cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12),(cid:4)(cid:5)(cid:9)(cid:4)(cid:17)(cid:16)1 DS40001262F-page 290  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2015 Microchip Technology Inc. DS40001262F-page 291

PIC16F631/677/685/687/689/690 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)’(cid:17)(cid:7)(cid:8)(cid:9)((cid:11)(cid:7)(cid:13))(cid:9)(cid:30)(cid:26)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)#(cid:7)*(cid:6)(cid:9)(cid:20)+(cid:5)(cid:21)(cid:9)(cid:22)(cid:9),-,-(cid:3)&.(cid:9)(cid:24)(cid:24)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)’((cid:30)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)255***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’5(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) (cid:14) D D2 EXPOSED PAD e E2 E 2 2 b 1 1 K N N TOPVIEW NOTE1 BOTTOMVIEW L A A3 A1 6(cid:25)(cid:19)&! (cid:18)(cid:28)99(cid:28)(cid:18).(cid:24).(cid:8)(cid:3) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:14)9(cid:19)’(cid:19)&! (cid:18)(cid:28)7 7:(cid:18) (cid:18)(cid:7); 7"’)(cid:13)(cid:21)(cid:14)(cid:22)%(cid:14)(cid:31)(cid:19)(cid:25)! 7 (cid:16)(cid:4) (cid:31)(cid:19)&(cid:20)(cid:23) (cid:13) (cid:4)(cid:29)(cid:15)(cid:4)(cid:14)1(cid:3), : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)8(cid:13)(cid:19)(cid:12)(cid:23)& (cid:7) (cid:4)(cid:29)>(cid:4) (cid:4)(cid:29)(cid:6)(cid:4) (cid:30)(cid:29)(cid:4)(cid:4) (cid:3)&(cid:11)(cid:25)#(cid:22)%%(cid:14) (cid:7)(cid:30) (cid:4)(cid:29)(cid:4)(cid:4) (cid:4)(cid:29)(cid:4)(cid:16) (cid:4)(cid:29)(cid:4)(cid:15) ,(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:7)- (cid:4)(cid:29)(cid:16)(cid:4)(cid:14)(cid:8).3 : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)=(cid:19)#&(cid:23) . (cid:5)(cid:29)(cid:4)(cid:4)(cid:14)1(cid:3), .$(cid:10)(cid:22)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)=(cid:19)#&(cid:23) .(cid:16) (cid:16)(cid:29)?(cid:4) (cid:16)(cid:29)(cid:17)(cid:4) (cid:16)(cid:29)>(cid:4) : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2) (cid:5)(cid:29)(cid:4)(cid:4)(cid:14)1(cid:3), .$(cid:10)(cid:22)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2)(cid:16) (cid:16)(cid:29)?(cid:4) (cid:16)(cid:29)(cid:17)(cid:4) (cid:16)(cid:29)>(cid:4) ,(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:14)=(cid:19)#&(cid:23) ) (cid:4)(cid:29)(cid:30)> (cid:4)(cid:29)(cid:16)(cid:15) (cid:4)(cid:29)-(cid:4) ,(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) 9 (cid:4)(cid:29)-(cid:4) (cid:4)(cid:29)(cid:5)(cid:4) (cid:4)(cid:29)(cid:15)(cid:4) ,(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:9)&(cid:22)(cid:9).$(cid:10)(cid:22)!(cid:13)#(cid:14)(cid:31)(cid:11)# A (cid:4)(cid:29)(cid:16)(cid:4) < < (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:30)(cid:29) (cid:31)(cid:19)(cid:25)(cid:14)(cid:30)(cid:14) (cid:19)!"(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:21)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14) (cid:11)(cid:21)(cid:27)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)*(cid:19)&(cid:23)(cid:19)(cid:25)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)&(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) (cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:19)!(cid:14)!(cid:11)*(cid:14)!(cid:19)(cid:25)(cid:12)"(cid:26)(cid:11)&(cid:13)#(cid:29) -(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)#(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18).(cid:14)0(cid:30)(cid:5)(cid:29)(cid:15)(cid:18)(cid:29) 1(cid:3),2 1(cid:11)!(cid:19)(cid:20)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)&(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)$(cid:11)(cid:20)&(cid:14) (cid:11)(cid:26)"(cid:13)(cid:14)!(cid:23)(cid:22)*(cid:25)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)!(cid:29) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)((cid:14)"!"(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)((cid:14)%(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)%(cid:22)(cid:21)’(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)"(cid:21)(cid:10)(cid:22)!(cid:13)!(cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12),(cid:4)(cid:5)(cid:9)(cid:30)(cid:16)?1 DS40001262F-page 292  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)255***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’5(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)  2005-2015 Microchip Technology Inc. DS40001262F-page 293

PIC16F631/677/685/687/689/690 APPENDIX A: DATA SHEET APPENDIX B: MIGRATING FROM REVISION HISTORY OTHER PIC® DEVICES Revision A (March 2005) This discusses some of the issues in migrating from This is a new data sheet. other PIC devices to the PIC16F6XX Family of devices. Revision B (May 2006) B.1 PIC16F676 to PIC16F685 Added 631/677 part numbers; Added pin summary TABLE B-1: FEATURE COMPARISON tables after pin diagrams; Incorporated Golden Chapters. Feature PIC16F676 PIC16F685 Max Operating 20MHz 20MHz Revision C (July 2006) Speed Max Program 1024 4096 Revised Section 4.2.1, ANSEL and ANSELH Memory (Words) Registers; Register 4-3, ANSEL Analog Select; Added Register 4-4, ANSELH Analog Select High; Section SRAM (bytes) 64 128 11.3.2, Revised CCP1<1:0> to DC1B<1:0>; Section A/D Resolution 10-bit 10-bit 11.3.7, Number 4 - Revised CCP1 to DC1B; Figure 11- Data EEPROM 128 256 5, Revised CCP1 to DC1B; Table 11-4, Revised P1M to (Bytes) P1M<1:0>; Section 12.3.1, Revised Paragraph 3; Timers (8/16-bit) 1/1 2/1 Revised Note 2; Revised Figure 12-6 Title. Oscillator Modes 8 8 Revision D (February 2007) Brown-out Reset Y Y Removed Preliminary status; Changed PICmicro to Internal Pull-ups RA0/1/2/4/5 RA0/1/2/4/5, PIC; Replaced Dev. Tool Section; Replaced Package MCLR Drawings. Interrupt-on-change RA0/1/2/3/4/5 RA0/1/2/3/4/5 Comparator 1 2 Revision E (March 2008) ECCP+ N Y Add Char Data charts; Updated EUSART Golden Ultra Low-Power N Y Chapter; Updated the Electrical Specification section; Wake-up Updated Package Drawings as needed. Extended WDT N Y Software Control N Y Revision F (April 2015) Option of WDT/BOR Added Section 17.8: High Temperature Operation in INTOSC 4MHz 31kHz-8MHz the Electrical Specifications section. Frequencies Clock Switching N Y Note: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. DS40001262F-page 294  2005-2015 Microchip Technology Inc.

PIC16F631/677/685/687/689/690 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://www.microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2005-2015 Microchip Technology Inc. DS40001262F-page 295

PIC16F631/677/685/687/689/690 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F685 - I/ML 301 = Industrial temp., QFN Range package, QTP pattern #301. b) PIC16F689 - I/SO = Industrial temp., SOIC package. Device: PIC16F631(1), PIC16F677(1), PIC16F685(1), c) PIC16F690T - E/SS = Extended temp., SSOP PIC16F687(1), PIC16F689(1), PIC16F690(1); package. VDD range 2.0V to 5.5V Temperature Range: I = -40C to +85C (Industrial) E = -40C to +125C (Extended) Package: ML = QFN (Quad Flat, no lead) P = PDIP SO = SOIC SS = SSOP Note 1: T= in tape and reel SSOP, SOIC and QFN packages only. Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) DS40001262F-page 296  2005-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2005-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-235-0 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2005-2015 Microchip Technology Inc. DS40001262F-page 297

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