PIC16F610/16HV610 PIC16F616/16HV616 Data Sheet 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers © 2009 Microchip Technology Inc. DS41288F

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of Microchip MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries. WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard, arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41288F-page 2 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers High-Performance RISC CPU: Peripheral Features: • Only 35 Instructions to Learn: • Shunt Voltage Regulator (PIC16HV610/616 only): - All single-cycle instructions except branches - 5 volt regulation • Operating Speed: - 4mA to 50mA shunt range - DC – 20MHz oscillator/clock input • 11 I/O Pins and 1 Input Only - DC – 200ns instruction cycle - High current source/sink for direct LED drive • Interrupt Capability - Interrupt-on-Change pins - Individually programmable weak pull-ups • 8-Level Deep Hardware Stack • Analog Comparator module with: • Direct, Indirect and Relative Addressing modes - Two analog comparators Special Microcontroller Features: - Programmable on-chip voltage reference (CVREF) module (% of VDD) • Precision Internal Oscillator: - Fixed Voltage Reference - Factory calibrated to ±1%, typical - Comparator inputs and outputs externally - User selectable frequency: 4MHz or 8 MHz accessible - SR Latch • Power-Saving Sleep mode - Built-In Hysteresis (user selectable) • Voltage Range: • Timer0: 8-Bit Timer/Counter with 8-Bit - PIC16F610/616: 2.0V to 5.5V Programmable Prescaler - PIC16HV610/616: 2.0V to user defined • Enhanced Timer1: maximum (see note) - 16-bit timer/counter with prescaler • Industrial and Extended Temperature Range - External Timer1 Gate (count enable) • Power-on Reset (POR) - Option to use OSC1 and OSC2 in LP mode • Power-up Timer (PWRT) and Oscillator Start-up as Timer1 oscillator if INTOSC mode Timer (OST) selected • Brown-out Reset (BOR) - Timer1 oscillator • Watchdog Timer (WDT) with Independent • In-Circuit Serial ProgrammingTM (ICSPTM) via Two Oscillator for Reliable Operation Pins • Multiplexed Master Clear with Pull-up/Input Pin PIC16F616/16HV616 only: • Programmable Code Protection • A/D Converter: • High Endurance Flash: - 10-bit resolution - 100,000 write Flash endurance - 8 external input channels - Flash retention: > 40 years - 2 internal reference channels Low-Power Features: • Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler • Standby Current: • Enhanced Capture, Compare, PWM module: - 50nA @ 2.0V, typical - 16-bit Capture, max. resolution 12.5ns • Operating Current: - 16-bit Compare, max. resolution 200ns - 20μA @ 32kHz, 2.0V, typical - 10-bit PWM with 1, 2 or 4 output channels, - 220μA @ 4MHz, 2.0V, typical programmable “dead time”, max. frequency 20kHz • Watchdog Timer Current: - 1μA @ 2.0V, typical Note: Voltage across internal shunt regulator cannot exceed 5V. © 2009 Microchip Technology Inc. DS41288F-page 3

PIC16F610/616/16HV610/616 Program Memory Data Memory 10-bit A/D Timers Device Flash SRAM (bytes) I/O (ch) Comparators 8/16-bit Voltage Range (words) PIC16F610 1024 64 11 — 2 1/1 2.0-5.5V PIC16HV610 1024 64 11 — 2 1/1 2.0-user defined PIC16F616 2048 128 11 8 2 2/1 2.0-5.5V PIC16HV616 2048 128 11 8 2 2/1 2.0-user defined PIC16F610/16HV610 14-Pin Diagram (PDIP, SOIC, TSSOP) VDD 1 14 VSS RA5/T1CKI/OSC1/CLKIN 2 10 13 RA0/C1IN+/ICSPDAT 6 RA4/T1G/OSC2/CLKOUT 3 HV 12 RA1/C12IN0-/ICSPCLK 6 RA3/MCLR/VPP 4 0/1 11 RA2/T0CKI/INT/C1OUT RC5 5 61 10 RC0/C2IN+ F RC4/C2OUT 6 16 9 RC1/C12IN1- C RC3/C12IN3- 7 PI 8 RC2/C12IN2- TABLE 1: PIC16F610/16HV610 14-PIN SUMMARY I/O Pin Comparators Timer Interrupts Pull-ups Basic RA0 13 C1IN+ — IOC Y ICSPDAT RA1 12 C12IN0- — IOC Y ICSPCLK RA2 11 C1OUT T0CKI INT/IOC Y — RA3(1) 4 — — IOC Y(2) MCLR/VPP RA4 3 — T1G IOC Y OSC2/CLKOUT RA5 2 — T1CKI IOC Y OSC1/CLKIN RC0 10 C2IN+ — — — — RC1 9 C12IN1- — — — — RC2 8 C12IN2- — — — — RC3 7 C12IN3- — — — — RC4 6 C2OUT — — — — RC5 5 — — — — — — 1 — — — — VDD — 14 — — — — VSS Note 1: Input only. 2: Only when pin is configured for external MCLR. DS41288F-page 4 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 PIC16F616/16HV616 14-Pin Diagram (PDIP, SOIC, TSSOP) VDD 1 14 VSS RA5/T1CKI/OSC1/CLKIN 2 16 13 RA0/AN0/C1IN+/ICSPDAT 6 RA4/AN3/T1G/OSC2/CLKOUT 3 HV 12 RA1/AN1/C12IN0-/VREF/ICSPCLK 6 RA3/MCLR/VPP 4 6/1 11 RA2/AN2/T0CKI/INT/C1OUT RC5/CCP1/P1A 5 61 10 RC0/AN4/C2IN+ F 6 RC4/C2OUT/P1B 6 1 9 RC1/AN5/C12IN1- C RC3/AN7/C12IN3-/P1C 7 PI 8 RC2/AN6/C12IN2-/P1D TABLE 2: PIC16F616/16HV616 14-PIN SUMMARY I/O Pin Analog Comparators Timer CCP Interrupts Pull-ups Basic RA0 13 AN0 C1IN+ — — IOC Y ICSPDAT RA1 12 AN1/VREF C12IN0- — — IOC Y ICSPCLK RA2 11 AN2 C1OUT T0CKI — INT/IOC Y — RA3(1) 4 — — — — IOC Y(2) MCLR/VPP RA4 3 AN3 — T1G — IOC Y OSC2/CLKOUT RA5 2 — — T1CKI — IOC Y OSC1/CLKIN RC0 10 AN4 C2IN+ — — — — — RC1 9 AN5 C12IN1- — — — — — RC2 8 AN6 C12IN2- — P1D — — — RC3 7 AN7 C12IN3- — P1C — — — RC4 6 — C2OUT — P1B — — — RC5 5 — — — CCP1/P1A — — — — 1 — — — — — — VDD — 14 — — — — — — VSS Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2009 Microchip Technology Inc. DS41288F-page 5

PIC16F610/616/16HV610/616 PIC16F610/16HV610 16-Pin Diagram (QFN) DD C C SS V N N V 6 5 4 3 1 1 1 1 RA5/T1CKI/OSC1/CLKIN 1 12 RA0/C1IN+/ICSPDAT RA4/T1G/OSC2/CLKOUT 2 PIC16F610/ 11 RA1/C12IN0-/ICSPCLK RA3/MCLR/VPP 3 PIC16HV610 10 RA2/T0CKI/INT/C1OUT RC5 4 9 RC0/C2IN1+ 5 6 7 8 UT N3- N2- N1- RC4/C2O RC3/C12I RC2/C12I RC1/C12I TABLE 3: PIC16F610/16HV610 16-PIN SUMMARY I/O Pin Comparators Timers Interrupts Pull-ups Basic RA0 12 C1IN+ — IOC Y ICSPDAT RA1 11 C12IN0- — IOC Y ICSPCLK RA2 10 C1OUT T0CKI INT/IOC Y — RA3(1) 3 — — IOC Y(2) MCLR/VPP RA4 2 — T1G IOC Y OSC2/CLKOUT RA5 1 — T1CKI IOC Y OSC1/CLKIN RC0 9 C2IN+ — — — — RC1 8 C12IN1- — — — — RC2 7 C12IN2- — — — — RC3 6 C12IN3- — — — — RC4 5 C2OUT — — — — RC5 4 — — — — — — 16 — — — — VDD — 13 — — — — VSS Note 1: Input only. 2: Only when pin is configured for external MCLR. DS41288F-page 6 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 PIC16F616/16HV616 16-Pin Diagram (QFN) DD C C SS V N N V 6 5 4 3 1 1 1 1 RA5/T1CKI/OSC1/CLKIN 1 12 RA0/AN0/C1IN+/ICSPDAT RA4/AN3/T1G/OSC2/CLKOUT 2 11 RA1/AN1/C12IN0-/VREF/ICSPCLK PIC16F616/ RA3/MCLR/VPP 3 PIC16HV616 10 RA2/AN2/T0CKI/INT/C1OUT RC5/CCP/P1A 4 9 RC0/AN4/C2IN1+ 5 6 7 8 RC4/C2OUT/P1B AN7/C12IN3-/P1C AN6/C12IN2-/P1D RC1/AN5/C12IN1- 3/ 2/ C C R R TABLE 4: PIC16F616/16HV616 16-PIN SUMMARY I/O Pin Analog Comparators Timers CCP Interrupts Pull-ups Basic RA0 12 AN0 C1IN+ — — IOC Y ICSPDAT RA1 11 AN1/VREF C12IN0- — — IOC Y ICSPCLK RA2 10 AN2 C1OUT T0CKI — INT/IOC Y — RA3(1) 3 — — — — IOC Y(2) MCLR/VPP RA4 2 AN3 — T1G — IOC Y OSC2/CLKOUT RA5 1 — — T1CKI — IOC Y OSC1/CLKIN RC0 9 AN4 C2IN+ — — — — — RC1 8 AN5 C12IN1- — — — — — RC2 7 AN6 C12IN2- — P1D — — — RC3 6 AN7 C12IN3- — P1C — — — RC4 5 — C2OUT — P1B — — — RC5 4 — — — CCP1/P1A — — — — 16 — — — — — — VDD — 13 — — — — — — VSS Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2009 Microchip Technology Inc. DS41288F-page 7

PIC16F610/616/16HV610/616 Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Memory Organization ................................................................................................................................................................13 3.0 Oscillator Module .......................................................................................................................................................................27 4.0 I/O Ports ....................................................................................................................................................................................33 5.0 Timer0 Module ..........................................................................................................................................................................45 6.0 Timer1 Module with Gate Control ..............................................................................................................................................49 7.0 Timer2 Module (PIC16F616/16HV616 only) .............................................................................................................................55 8.0 Comparator Module ...................................................................................................................................................................57 9.0 Analog-to-Digital Converter (ADC) Module (PIC16F616/16HV616 only) ..................................................................................73 10.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC16F616/16HV616 Only) ..................85 11.0 Voltage Regulator ....................................................................................................................................................................107 12.0 Special Features of the CPU ...................................................................................................................................................109 13.0 Instruction Set Summary..........................................................................................................................................................129 14.0 Development Support...............................................................................................................................................................139 15.0 Electrical Specifications............................................................................................................................................................143 16.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................173 17.0 Packaging Information..............................................................................................................................................................197 Appendix A:Data Sheet Revision History...........................................................................................................................................205 Appendix B: Migrating from other PIC® Devices................................................................................................................................206 Index................................................................................................................................................................................................. 207 The Microchip Web Site.....................................................................................................................................................................211 Customer Change Notification Service..............................................................................................................................................211 Customer Support..............................................................................................................................................................................211 Reader Response..............................................................................................................................................................................212 Product Identification System.............................................................................................................................................................213 Worldwide Sales and Service............................................................................................................................................................214 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41288F-page 8 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 1.0 DEVICE OVERVIEW The PIC16F610/616/16HV610/616 is covered by this data sheet. It is available in 14-pin PDIP, SOIC, TSSOP and 16-pin QFN packages. Block Diagrams and pinout descriptions of the devices are as follows: • PIC16F610/16HV610 (Figure1-1, Table1-1) • PIC16F616/16HV616 (Figure1-2, Table1-2) FIGURE 1-1: PIC16F610/16HV610 BLOCK DIAGRAM INT Configuration 13 Data Bus 8 PORTA Program Counter Flash RA0 1K X 14 RA1 Program RAM RA2 Memory 8-Level Stack 64 Bytes RA3 (13-Bit) File RA4 Registers RA5 Program 14 Bus RAM Addr 9 Addr MUX Instruction Reg PORTC Direct Addr 7 Indirect 8 Addr RC0 RC1 FSR Reg RC2 RC3 STATUS Reg 8 RC4 RC5 3 Power-up MUX Timer Instruction Oscillator Decode and Start-up Timer ALU Control Power-on Reset 8 Timing Watchdog OSC1/CLKIN Generation Timer W Reg Brown-out OSC2/CLKOUT Reset Internal Oscillator Shunt Regulator Block (PIC16HV610 only) MCLR VDD VSS T1G T1CKI Timer0 Timer1 T0CKI Comparator Voltage Reference 2 Analog Comparators Fixed Voltage Reference CCCCCCCC 22111111 OUIN+OU2IN2IN2IN2ININ+ T T3210 ---- © 2009 Microchip Technology Inc. DS41288F-page 9

PIC16F610/616/16HV610/616 FIGURE 1-2: PIC16F616/16HV616 BLOCK DIAGRAM INT Configuration 13 Data Bus 8 PORTA Program Counter Flash RA0 2K X 14 RA1 Program RAM RA2 Memory 8-Level Stack 128 Bytes RA3 (13-Bit) File RA4 Registers RA5 Program 14 Bus RAM Addr 9 Addr MUX Instruction Reg PORTC Direct Addr 7 Indirect 8 Addr RC0 RC1 FSR Reg RC2 RC3 STATUS Reg 8 RC4 RC5 3 Power-up MUX Timer Instruction Oscillator Decode and Start-up Timer ALU Control Power-on Reset 8 Timing Watchdog OSC1/CLKIN Generation Timer W Reg Brown-out OSC2/CLKOUT Reset Internal Oscillator Shunt Regulator Block (PIC16HV616 only) MCLR VDD VSS T1G T1CKI Timer0 Timer1 Timer2 T0CKI Comparator Voltage Reference 2 Analog Comparators Analog-To-Digital Converter ECCP Fixed Voltage Reference AAAAAAAA CCCCCCCC PPPC VREF N7N6N5N4N3N2N1N0 2OUT2IN+1OUT12IN3-12IN2-12IN1-12IN0-1IN+ 1D1C1BCP1/P1 A DS41288F-page 10 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 1-1: PIC16F610/16HV610 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/C1IN+/ICSPDAT RA0 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change C1IN+ AN — Comparator C1 non-inverting input ICSPDAT ST CMOS Serial Programming Data I/O RA1/C12IN0-/ICSPCLK RA1 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change C12IN0- AN — Comparators C1 and C2 inverting input ICSPCLK ST — Serial Programming Clock RA2/T0CKI/INT/C1OUT RA2 ST CMOS PORTA I/O with prog. pull-up and interrupt-on-change T0CKI ST — Timer0 clock input INT ST — External Interrupt C1OUT — CMOS Comparator C1 output RA3/MCLR/VPP RA3 TTL — PORTA input with interrupt-on-change MCLR ST — Master Clear w/internal pull-up VPP HV — Programming voltage RA4/T1G/OSC2/CLKOUT RA4 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change T1G ST — Timer1 gate (count enable) OSC2 — XTAL Crystal/Resonator CLKOUT — CMOS FOSC/4 output RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change T1CKI ST — Timer1 clock input OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection RC0/C2IN+ RC0 TTL CMOS PORTC I/O C2IN+ AN — Comparator C2 non-inverting input RC1/C12IN1- RC1 TTL CMOS PORTC I/O C12IN1- AN — Comparators C1 and C2 inverting input RC2/C12IN2- RC2 TTL CMOS PORTC I/O C12IN2- AN — Comparators C1 and C2 inverting input RC3/C12IN3- RC3 TTL CMOS PORTC I/O C12IN3- AN — Comparators C1 and C2 inverting input RC4/C2OUT RC4 TTL CMOS PORTC I/O C2OUT — CMOS Comparator C2 output RC5 RC5 TTL CMOS PORTC I/O VDD VDD Power — Positive supply VSS VSS Power — Ground reference Legend: AN = Analog input or output CMOS= CMOS compatible input or output HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL = Crystal © 2009 Microchip Technology Inc. DS41288F-page 11

PIC16F610/616/16HV610/616 TABLE 1-2: PIC16F616/16HV616 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/C1IN+/ICSPDAT RA0 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change AN0 AN — A/D Channel 0 input C1IN+ AN — Comparator C1 non-inverting input ICSPDAT ST CMOS Serial Programming Data I/O RA1/AN1/C12IN0-/VREF/ICSPCLK RA1 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change AN1 AN — A/D Channel 1 input C12IN0- AN — Comparators C1 and C2 inverting input VREF AN — External Voltage Reference for A/D ICSPCLK ST — Serial Programming Clock RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS PORTA I/O with prog. pull-up and interrupt-on-change AN2 AN — A/D Channel 2 input T0CKI ST — Timer0 clock input INT ST — External Interrupt C1OUT — CMOS Comparator C1 output RA3/MCLR/VPP RA3 TTL — PORTA input with interrupt-on-change MCLR ST — Master Clear w/internal pull-up VPP HV — Programming voltage RA4/AN3/T1G/OSC2/CLKOUT RA4 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change AN3 AN — A/D Channel 3 input T1G ST — Timer1 gate (count enable) OSC2 — XTAL Crystal/Resonator CLKOUT — CMOS FOSC/4 output RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change T1CKI ST — Timer1 clock input OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection RC0/AN4/C2IN+ RC0 TTL CMOS PORTC I/O AN4 AN — A/D Channel 4 input C2IN+ AN — Comparator C2 non-inverting input RC1/AN5/C12IN1- RC1 TTL CMOS PORTC I/O AN5 AN — A/D Channel 5 input C12IN1- AN — Comparators C1 and C2 inverting input RC2/AN6/C12IN2-/P1D RC2 TTL CMOS PORTC I/O AN6 AN — A/D Channel 6 input C12IN2- AN — Comparators C1 and C2 inverting input P1D — CMOS PWM output RC3/AN7/C12IN3-/P1C RC3 TTL CMOS PORTC I/O AN7 AN — A/D Channel 7 input C12IN3- AN — Comparators C1 and C2 inverting input P1C — CMOS PWM output RC4/C2OUT/P1B RC4 TTL CMOS PORTC I/O C2OUT — CMOS Comparator C2 output P1B — CMOS PWM output RC5/CCP1/P1A RC5 TTL CMOS PORTC I/O CCP1 ST CMOS Capture input/Compare output P1A — CMOS PWM output VDD VDD Power — Positive supply VSS VSS Power — Ground reference Legend: AN = Analog input or output CMOS= CMOS compatible input or output HV = High Voltage ST = Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL = Crystal DS41288F-page 12 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 2.0 MEMORY ORGANIZATION FIGURE 2-2: PROGRAM MEMORY MAP AND STACK FOR THE 2.1 Program Memory Organization PIC16F616/16HV616 The PIC16F610/616/16HV610/616 has a 13-bit PC<12:0> program counter capable of addressing an 8K x 14 CALL, RETURN 13 program memory space. Only the first 1K x 14 RETFIE, RETLW (0000h-3FF) for the PIC16F610/16HV610 and the first 2K x 14 (0000h-07FFh) for the PIC16F616/16HV616 is Stack Level 1 physically implemented. Accessing a location above Stack Level 2 these boundaries will cause a wraparound within the first 1K x 14 space (PIC16F610/16HV610) and 2K x 14 space (PIC16F616/16HV616). The Reset vector is at Stack Level 8 0000h and the interrupt vector is at 0004h (see Figure2-1). Reset Vector 0000h FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F610/16HV610 Interrupt Vector 0004h 0005h PC<12:0> On-chip Program CALL, RETURN 13 RETFIE, RETLW Memory 07FFh Stack Level 1 0800h Stack Level 2 1FFFh Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h On-chip Program Memory 03FFh 0400h 1FFFh © 2009 Microchip Technology Inc. DS41288F-page 13

PIC16F610/616/16HV610/616 2.2 Data Memory Organization 2.2.1 GENERAL PURPOSE REGISTER FILE The data memory (see Figure2-4) is partitioned into two banks, which contain the General Purpose The register file is organized as 64x8 in the Registers (GPR) and the Special Function Registers PIC16F610/16HV610 and 128x8 in the (SFR). The Special Function Registers are located in PIC16F616/16HV616. Each register is accessed, the first 32 locations of each bank. either directly or indirectly, through the File Select Reg- PIC16F610/16HV610 Register locations 40h-7Fh in ister (FSR) (see Section2.4 “Indirect Addressing, Bank 0 are General Purpose Registers, implemented INDF and FSR Registers”). as static RAM. PIC16F616/16HV616 Register 2.2.2 SPECIAL FUNCTION REGISTERS locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are General Purpose Registers, implemented as static The Special Function Registers are registers used by RAM. Register locations F0h-FFh in Bank 1 point to the CPU and peripheral functions for controlling the addresses 70h-7Fh in Bank0. All other RAM is desired operation of the device (see Table2-1). These unimplemented and returns ‘0’ when read. The RP0 bit registers are static RAM. of the STATUS register is the bank select bit. The special registers can be classified into two sets: RP0 core and peripheral. The Special Function Registers 0 → Bank 0 is selected associated with the “core” are described in this section. Those related to the operation of the peripheral features 1 → Bank 1 is selected are described in the section of that peripheral feature. Note: The IRP and RP1 bits of the STATUS register are reserved and should always be maintained as ‘0’s. DS41288F-page 14 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 2-3: DATA MEMORY MAP OF FIGURE 2-4: DATA MEMORY MAP OF THE PIC16F610/16HV610 THE PIC16F616/16HV616 File File File File Address Address Address Address Indirect Addr.(1) 00h Indirect Addr.(1) 80h Indirect Addr.(1) 00h Indirect Addr.(1) 80h TMR0 01h OPTION_REG 81h TMR0 01h OPTION_REG 81h PCL 02h PCL 82h PCL 02h PCL 82h STATUS 03h STATUS 83h STATUS 03h STATUS 83h FSR 04h FSR 84h FSR 04h FSR 84h PORTA 05h TRISA 85h PORTA 05h TRISA 85h 06h 86h 06h 86h PORTC 07h TRISC 87h PORTC 07h TRISC 87h 08h 88h 08h 88h 09h 89h 09h 89h PCLATH 0Ah PCLATH 8Ah PCLATH 0Ah PCLATH 8Ah INTCON 0Bh INTCON 8Bh INTCON 0Bh INTCON 8Bh PIR1 0Ch PIE1 8Ch PIR1 0Ch PIE1 8Ch 0Dh 8Dh 0Dh 8Dh TMR1L 0Eh PCON 8Eh TMR1L 0Eh PCON 8Eh TMR1H 0Fh 8Fh TMR1H 0Fh 8Fh T1CON 10h OSCTUNE 90h T1CON 10h OSCTUNE 90h 11h ANSEL 91h TMR2 11h ANSEL 91h 12h 92h T2CON 12h PR2 92h 13h 93h CCPR1L 13h 93h 14h 94h CCPR1H 14h 94h 15h WPUA 95h CCP1CON 15h WPUA 95h 16h IOCA 96h PWM1CON 16h IOCA 96h 17h 97h ECCPAS 17h 97h 18h 98h 18h 98h VRCON 19h SRCON0 99h VRCON 19h SRCON0 99h CM1CON0 1Ah SRCON1 9Ah CM1CON0 1Ah SRCON1 9Ah CM2CON0 1Bh 9Bh CM2CON0 1Bh 9Bh CM2CON1 1Ch 9Ch CM2CON1 1Ch 9Ch 1Dh 9Dh 1Dh 9Dh 1Eh 9Eh ADRESH 1Eh ADRESL 9Eh 1Fh 9Fh ADCON0 1Fh ADCON1 9Fh 20h A0h 20h General A0h Purpose Registers 32 Bytes BFh General 3Fh Purpose C0h 40h Registers 96 Bytes General Purpose Registers 64 Bytes 6Fh 70h F0h F0h Accesses 70h-7Fh Accesses 70h-7Fh Accesses 70h-7Fh 7Fh FFh 7Fh FFh Bank 0 Bank 1 Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. Note 1: Not a physical register. © 2009 Microchip Technology Inc. DS41288F-page 15

PIC16F610/616/16HV610/616 TABLE 2-1: PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOR Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 24, 116 01h TMR0 Timer0 Module’s Register xxxx xxxx 45, 116 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 24, 116 03h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 18, 116 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 24, 116 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 33, 116 06h — Unimplemented — — 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx 42, 116 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 24, 116 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 20, 116 0Ch PIR1 — ADIF(2) CCP1IF(2) C2IF C1IF — TMR2IF(2) TMR1IF -000 0-00 22, 116 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 49, 116 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 49, 116 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 52, 116 11h TMR2(2) Timer2 Module Register 0000 0000 55, 116 12h T2CON(2) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 56, 116 13h CCPR1L(2) Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 86, 116 14h CCPR1H(2) Capture/Compare/PWM Register 1 High Byte xxxx xxxx 86, 116 15h CCP1CON(2) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 85, 116 16h PWM1CON(2) PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 85, 116 17h ECCPAS(2) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 102, 116 18h — Unimplemented — — 19h VRCON C1VREN C2VREN VRR FVREN VR3 VR2 VR1 VR0 0000 0000 72, 116 1Ah CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 62, 116 1Bh CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 63, 116 1Ch CM2CON1 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 65, 116 1Dh — Unimplemented — — 1Eh ADRESH(2,3) Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 80, 116 1Fh ADCON0(2) ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 78, 116 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: PIC16F616/16HV616 only. 3: Read-only register. DS41288F-page 16 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 2-2: PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOR Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 24, 116 81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19, 116 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 24, 116 83h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 18, 116 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 24, 116 85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 33, 116 86h — Unimplemented — — 87h TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 42, 116 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 24, 116 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 20, 116 8Ch PIE1 — ADIE(3) CCP1IE(3) C2IE C1IE — TMR2IE(3) TMR1IE -000 0-00 21, 116 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOR ---- --qq 23, 116 8Fh — Unimplemented — — 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 31, 117 91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3(3) ANS2(3) ANS1 ANS0 1111 1111 34, 117 92h PR2(3) Timer2 Module Period Register 1111 1111 55, 117 93h — Unimplemented — — 94h — Unimplemented — — 95h WPUA — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 35, 117 96h IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 35, 117 97h — Unimplemented — — 98h — Unimplemented — — 99h SRCON0 SR1 SR0 C1SEN C2REN PULSS PULSR — SRCLKEN 0000 00-0 69, 117 9Ah SRCON1 SRCS1 SRCS0 — — — — — — 00-- ---- 69, 117 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh ADRESL(3,4) Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 80, 117 9Fh ADCON1(3) — ADCS2 ADCS1 ADCS0 — — — — -000 ---- 79, 117 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. 3: PIC16F616/16HV616 only. 4: Read-only Register. © 2009 Microchip Technology Inc. DS41288F-page 17

PIC16F610/616/16HV610/616 2.2.2.1 STATUS Register It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the The STATUS register, shown in Register2-1, contains: STATUS register, because these instructions do not • the arithmetic status of the ALU affect any Status bits. For other instructions not affect- • the Reset status ing any Status bits, see the Section13.0 “Instruction • the bank select bits for data memory (RAM) Set Summary”. The STATUS register can be the destination for any Note1: Bits IRP and RP1 of the STATUS register instruction, like any other register. If the STATUS are not used by the register is the destination for an instruction that affects PIC16F610/616/16HV610/616 and the Z, DC or C bits, then the write to these three bits is should be maintained as clear. Use of disabled. These bits are set or cleared according to the these bits is not recommended, since this device logic. Furthermore, the TO and PD bits are not may affect upward compatibility with writable. Therefore, the result of an instruction with the future products. STATUS register as destination may be different than 2: The C and DC bits operate as a Borrow intended. and Digit Borrow out bit, respectively, in For example, CLRF STATUS, will clear the upper three subtraction. See the SUBLW and SUBWF bits and set the Z bit. This leaves the STATUS register instructions for examples. as ‘000u u1uu’ (where u = unchanged). REGISTER 2-1: STATUS: STATUS REGISTER Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRP: This bit is reserved and should be maintained as ‘0’ bit 6 RP1: This bit is reserved and should be maintained as ‘0’ bit 5 RP0: Register Bank Select bit (used for direct addressing) 1 = Bank 1 (80h–FFh) 0 = Bank 0 (00h–7Fh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed. 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS41288F-page 18 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 2.2.2.2 OPTION Register Note: To achieve a 1:1 prescaler assignment for The OPTION register is a readable and writable regis- Timer0, assign the prescaler to the WDT ter, which contains various control bits to configure: by setting PSA bit to ‘1’ of the OPTION • Timer0/WDT prescaler register. See Section5.1.3 “Software • External RA2/INT interrupt Programmable Prescaler”. • Timer0 • Weak pull-ups on PORTA REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on RA2/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits BIT VALUE TIMER0 RATE WDT RATE 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 © 2009 Microchip Technology Inc. DS41288F-page 19

PIC16F610/616/16HV610/616 2.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt The INTCON register is a readable and writable condition occurs, regardless of the state of register, which contains the various enable and flag bits its corresponding enable bit or the global for TMR0 register overflow, PORTA change and enable bit, GIE of the INTCON register. external RA2/INT pin interrupts. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GIE PEIE T0IE INTE RAIE T0IF INTF RAIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: RA2/INT External Interrupt Enable bit 1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt bit 3 RAIE: PORTA Change Interrupt Enable bit(1) 1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow bit 1 INTF: RA2/INT External Interrupt Flag bit 1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur bit 0 RAIF: PORTA Change Interrupt Flag bit 1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software) 0 = None of the PORTA <5:0> pins have changed state Note 1: IOCA register must also be enabled. 2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit. DS41288F-page 20 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 2.2.2.4 PIE1 Register The PIE1 register contains the peripheral interrupt Note: Bit PEIE of the INTCON register must be enable bits, as shown in Register2-4. set to enable any peripheral interrupt. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit(1) 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 CCP1IE: CCP1 Interrupt Enable bit(1) 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 4 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 3 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1) 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’. © 2009 Microchip Technology Inc. DS41288F-page 21

PIC16F610/616/16HV610/616 2.2.2.5 PIR1 Register The PIR1 register contains the peripheral interrupt flag Note: Interrupt flag bits are set when an interrupt bits, as shown in Register2-5. condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Interrupt Flag bit(1) 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started bit 5 CCP1IF: CCP1 Interrupt Flag bit(1) Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 4 C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator C2 output has changed (must be cleared in software) 0 = Comparator C2 output has not changed bit 3 C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator C1 output has changed (must be cleared in software) 0 = Comparator C1 output has not changed bit 2 Unimplemented: Read as ‘0’ bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit(1) 1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match has not occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software) 0 = Timer1 has not overflowed Note 1: PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’. DS41288F-page 22 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 2.2.2.6 PCON Register The Power Control (PCON) register (see Table12-2) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register2-6. REGISTER 2-6: PCON: POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0(1) — — — — — — POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Reads as ‘0’ if Brown-out Reset is disabled. © 2009 Microchip Technology Inc. DS41288F-page 23

PIC16F610/616/16HV610/616 2.3 PCL and PCLATH 2.3.2 STACK The Program Counter (PC) is 13 bits wide. The low byte The PIC16F610/616/16HV610/616 Family has an comes from the PCL register, which is a readable and 8-levelx13-bit wide hardware stack (see Figure2-1). writable register. The high byte (PC<12:8>) is not directly The stack space is not part of either program or data readable or writable and comes from PCLATH. On any space and the Stack Pointer is not readable or writable. Reset, the PC is cleared. Figure2-5 shows the two The PC is PUSHed onto the stack when a CALL situations for the loading of the PC. The upper example instruction is executed or an interrupt causes a branch. in Figure2-5 shows how the PC is loaded on a write to The stack is POPed in the event of a RETURN, RETLW PCL (PCLATH<4:0> → PCH). The lower example in or a RETFIE instruction execution. PCLATH is not Figure2-5 shows how the PC is loaded during a CALL or affected by a PUSH or POP operation. GOTO instruction (PCLATH<4:3> → PCH). The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth FIGURE 2-5: LOADING OF PC IN push overwrites the value that was stored from the first DIFFERENT SITUATIONS push. The tenth push overwrites the second push (and so on). PCH PCL Instruction with Note1: There are no Status bits to indicate stack 12 8 7 0 PCL as PC Destination overflow or stack underflow conditions. 2: There are no instructions/mnemonics PCLATH<4:0> 8 5 ALU Result called PUSH or POP. These are actions that occur from the execution of the PCLATH CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an PCH PCL interrupt address. 12 11 10 8 7 0 PC GOTO, CALL 2.4 Indirect Addressing, INDF and PCLATH<4:3> 11 FSR Registers 2 OPCODE <10:0> The INDF register is not a physical register. Addressing PCLATH the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF 2.3.1 MODIFYING PCL register. Any instruction using the INDF register actually accesses data pointed to by the File Select Executing any instruction with the PCL register as the Register (FSR). Reading INDF itself indirectly will destination simultaneously causes the Program produce 00h. Writing to the INDF register indirectly Counter PC<12:8> bits (PCH) to be replaced by the results in a no operation (although Status bits may be contents of the PCLATH register. This allows the entire affected). An effective 9-bit address is obtained by contents of the program counter to be changed by concatenating the 8-bit FSR and the IRP bit of the writing the desired upper 5 bits to the PCLATH register. STATUS register, as shown in Figure2-7. When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the A simple program to clear RAM location 40h-4Fh using values contained in the PCLATH register and those indirect addressing is shown in Example2-1. being written to the PCL register. EXAMPLE 2-1: INDIRECT ADDRESSING A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be MOVLW 0x40 ;initialize pointer exercised when jumping into a look-up table or MOVWF FSR ;to RAM program branch table (computed GOTO) by modifying NEXT CLRF INDF ;clear INDF register the PCL register. Assuming that PCLATH is set to the INCF FSR, F ;inc pointer table start address, if the table length is greater than BTFSS FSR,4 ;all done? GOTO NEXT ;no clear next 255 instructions or if the lower 8 bits of the memory CONTINUE ;yes continue address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table. For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556). DS41288F-page 24 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC16F610/16HV610 Direct Addressing Indirect Addressing RP1(1) RP0 6 From Opcode 0 IRP(1) 7 File Select Register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 180h Data NOT USED(2) Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail, see Figure2-3. Unimplemented data memory locations, read as ‘0’. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. 2: Accesses in Bank 2 and Bank 3 are mirrored back into Bank 0 and Bank 1, respectively. FIGURE 2-7: DIRECT/INDIRECT ADDRESSING PIC16F616/16HV616 Direct Addressing Indirect Addressing RP1(1) RP0 6 From Opcode 0 IRP(1) 7 File Select Register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 180h Data NOT USED(2) Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail, see Figure2-4. Unimplemented data memory locations, read as ‘0’. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. 2: Accesses in Bank 2 and Bank 3 are mirrored back into Bank 0 and Bank 1, respectively. © 2009 Microchip Technology Inc. DS41288F-page 25

PIC16F610/616/16HV610/616 NOTES: DS41288F-page 26 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 3.0 OSCILLATOR MODULE The Oscillator module can be configured in one of eight clock modes. 3.1 Overview 1. EC – External clock with I/O on OSC2/CLKOUT. 2. LP – 32kHz Low-Power Crystal mode. The Oscillator module has a wide variety of clock 3. XT – Medium Gain Crystal or Ceramic Resonator sources and selection features that allow it to be used Oscillator mode. in a wide range of applications while maximizing perfor- mance and minimizing power consumption. Figure3-1 4. HS – High Gain Crystal or Ceramic Resonator illustrates a block diagram of the Oscillator module. mode. 5. RC – External Resistor-Capacitor (RC) with Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators FOSC/4 output on OSC2/CLKOUT. and Resistor-Capacitor (RC) circuits. In addition, the 6. RCIO – External Resistor-Capacitor (RC) with system clock source can be configured with a choice of I/O on OSC2/CLKOUT. two selectable speeds: internal or external system clock 7. INTOSC – Internal oscillator with FOSC/4 output source. on OSC2 and I/O on OSC1/CLKIN. 8. INTOSCIO – Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT. Clock Source modes are configured by the FOSC<2:0> bits in the Configuration Word register (CONFIG). The Internal Oscillator module provides a selectable system clock mode of either 4MHz (Postscaler) or 8MHz (INTOSC). FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FOSC<2:0> External Oscillator IOSCFS (Configuration Word Register) OSC2 Sleep LP, XT, HS, RC, RCIO, EC OSC1 X INTOSC U M System Clock Internal Oscillator (CPU and Peripherals) INTOSC 8 MHz Postscaler 4 MHz © 2009 Microchip Technology Inc. DS41288F-page 27

PIC16F610/616/16HV610/616 3.2 Clock Source Modes 3.3.2 OSCILLATOR START-UP TIMER (OST) Clock Source modes can be classified as external or internal. If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts • External Clock modes rely on external circuitry for 1024 oscillations from OSC1. This occurs following a the clock source. Examples are: Oscillator mod- Power-on Reset (POR) and when the Power-up Timer ules (EC mode), quartz crystal resonators or (PWRT) has expired (if configured), or a wake-up from ceramic resonators (LP, XT and HS modes) and Sleep. During this time, the program counter does not Resistor-Capacitor (RC) mode circuits. increment and program execution is suspended. The • Internal clock sources are contained internally OST ensures that the oscillator circuit, using a quartz within the Oscillator module. The Oscillator crystal resonator or ceramic resonator, has started and module has two selectable clock frequencies: is providing a stable system clock to the Oscillator 4MHz and 8MHz module. When switching between clock sources, a The system clock can be selected between external or delay is required to allow the new clock to stabilize. internal clock sources via the FOSC<2:0> bits of the These oscillator delays are shown in Table3-1. Configuration Word register. 3.3 External Clock Modes 3.3.1 EC MODE The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure3-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 3-2: EXTERNAL CLOCK (EC) MODE OPERATION Clock from OSC1/CLKIN Ext. System PIC® MCU I/O OSC2/CLKOUT(1) Note 1: Alternate pin functions are listed in the Section1.0 “Device Overview”. TABLE 3-1: OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Oscillator Delay Sleep/POR INTOSC 4MHz to 8MHz Oscillator Warm-Up Delay (TWARM) Sleep/POR EC, RC DC – 20MHz 2 Instruction Cycles Sleep/POR LP, XT, HS 32kHz to 20MHz 1024 Clock Cycles (OST) DS41288F-page 28 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 3.3.3 LP, XT, HS MODES Note 1: Quartz crystal characteristics vary according The LP, XT and HS modes support the use of quartz to type, package and manufacturer. The crystal resonators or ceramic resonators connected to user should consult the manufacturer data OSC1 and OSC2 (Figure3-3). The mode selects a low, sheets for specifications and recommended medium or high gain setting of the internal inverter- application. amplifier to support various resonator types and speed. 2: Always verify oscillator performance over LP Oscillator mode selects the lowest gain setting of the VDD and temperature range that is the internal inverter-amplifier. LP mode current expected for the application. consumption is the least of the three modes. This mode 3: For oscillator design assistance, reference is designed to drive only 32.768 kHz tuning-fork type the following Microchip Applications Notes: crystals (watch crystals). • AN826, “Crystal Oscillator Basics and XT Oscillator mode selects the intermediate gain Crystal Selection for rfPIC® and PIC® setting of the internal inverter-amplifier. XT mode Devices” (DS00826) current consumption is the medium of the three modes. • AN849, “Basic PIC® Oscillator Design” This mode is best suited to drive resonators with a (DS00849) medium drive level specification. • AN943, “Practical PIC® Oscillator HS Oscillator mode selects the highest gain setting of Analysis and Design” (DS00943) the internal inverter-amplifier. HS mode current • AN949, “Making Your Oscillator Work” consumption is the highest of the three modes. This (DS00949) mode is best suited for resonators that require a high drive setting. FIGURE 3-4: CERAMIC RESONATOR Figure3-3 and Figure3-4 show typical circuits for OPERATION quartz crystal and ceramic resonators, respectively. (XT OR HS MODE) FIGURE 3-3: QUARTZ CRYSTAL PIC® MCU OPERATION (LP, XT OR HS MODE) OSC1/CLKIN PIC® MCU C1 To Internal Logic OSC1/CLKIN RP(3) RF(2) Sleep C1 To Internal Logic QCruyasrttazl RF(2) Sleep C2 Ceramic RS(1) OSC2/CLKOUT Resonator Note 1: A series resistor (RS) may be required for C2 RS(1) OSC2/CLKOUT ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode Note 1: A series resistor (RS) may be required for selected (typically between 2MΩ to 10MΩ). quartz crystals with low drive level. 3: An additional parallel feedback resistor (RP) 2: The value of RF varies with the Oscillator mode may be required for proper ceramic resonator selected (typically between 2MΩ to 10MΩ). operation. © 2009 Microchip Technology Inc. DS41288F-page 29

PIC16F610/616/16HV610/616 3.3.4 EXTERNAL RC MODES 3.4 Internal Clock Modes The external Resistor-Capacitor (RC) modes support The Oscillator module provides a selectable system the use of an external RC circuit. This allows the clock source of either 4MHz or 8MHz. The selectable designer maximum flexibility in frequency choice while frequency is configured through the IOSCFS bit of the keeping costs to a minimum when clock accuracy is not Configuration Word. required. There are two modes: RC and RCIO. The frequency of the internal oscillator can be can be In RC mode, the RC circuit connects to OSC1. OSC2/ user-adjusted via software using the OSCTUNE CLKOUT outputs the RC oscillator frequency divided register. by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or 3.4.1 INTOSC AND INTOSCIO MODES other application requirements. Figure3-5 shows the The INTOSC and INTOSCIO modes configure the external RC mode connections. internal oscillators as the system clock source when the device is programmed using the oscillator selection FIGURE 3-5: EXTERNAL RC MODES or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section12.0 “Special VDD PIC® MCU Features of the CPU” for more information. In INTOSC mode, OSC1/CLKIN is available for general REXT purpose I/O. OSC2/CLKOUT outputs the selected OSC1/CLKIN Internal internal oscillator frequency divided by 4. The CLKOUT Clock signal may be used to provide a clock for external CEXT circuitry, synchronization, calibration, test or other VSS application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT FOSC/4 or OSC2/CLKOUT(1) are available for general purpose I/O. I/O(2) Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V 3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V CEXT > 20 pF, 2-5V Note 1: Alternate pin functions are listed in Section1.0 “Device Overview”. 2: Output depends upon RC or RCIO Clock mode. In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: • threshold voltage variation • component tolerances • packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. DS41288F-page 30 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 3.4.1.1 OSCTUNE Register The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. The oscillator is factory calibrated but can be adjusted in software by writing to the OSCTUNE register When the OSCTUNE register is modified, the frequency (Register3-1). will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = • • • 00001 = 00000 = Oscillator module is running at the manufacturer calibrated frequency. 11111 = • • • 10000 = Minimum frequency TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets(1) CONFIG(2) IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register12-1) for operation of all register bits. © 2009 Microchip Technology Inc. DS41288F-page 31

PIC16F610/616/16HV610/616 NOTES: DS41288F-page 32 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 4.0 I/O PORTS port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when There are as many as eleven general purpose I/O pins MCLRE = 1. and an input pin available. Depending on which The TRISA register controls the direction of the peripherals are enabled, some or all of the pins may not PORTApins, even when they are being used as be available as general purpose I/O. In general, when a analog inputs. The user must ensure the bits in the peripheral is enabled, the associated pin may not be TRISA register are maintained set when using them as used as a general purpose I/O pin. analog inputs. I/O pins configured as analog input 4.1 PORTA and the TRISA Registers always read ‘0’. Note: The ANSEL register must be initialized to PORTA is a 6-bit wide, bidirectional port. The configure an analog channel as a digital corresponding data direction register is TRISA input. Pins configured as analog inputs will (Register4-2). Setting a TRISA bit (= 1) will make the read ‘0’ and cannot generate an interrupt. corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the EXAMPLE 4-1: INITIALIZING PORTA corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the BCF STATUS,RP0 ;Bank 0 CLRF PORTA ;Init PORTA selected pin). The exception is RA3, which is input only BSF STATUS,RP0 ;Bank 1 and its TRIS bit will always read as ‘1’. Example4-1 CLRF ANSEL ;digital I/O shows how to initialize PORTA. MOVLW 0Ch ;Set RA<3:2> as inputs Reading the PORTA register (Register4-1) reads the MOVWF TRISA ;and set RA<5:4,1:0> status of the pins, whereas writing to it will write to the ;as outputs PORT latch. All write operations are read-modify-write BCF STATUS,RP0 ;Bank 0 operations. Therefore, a write to a port implies that the REGISTER 4-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x R/W-0 R-x R/W-0 R/W-0 R/W-0 — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Pin bit 1 = PORTA pin is > VIH 0 = PORTA pin is < VIL REGISTER 4-2: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISA<5:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: TRISA<3> always reads ‘1’. 2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2009 Microchip Technology Inc. DS41288F-page 33

PIC16F610/616/16HV610/616 4.2 Additional Pin Functions 4.2.3 INTERRUPT-ON-CHANGE Every PORTA pin on the PIC16F610/616/16HV610/ Each PORTA pin is individually configurable as an 616 has an interrupt-on-change option and a weak pull- interrupt-on-change pin. Control bits IOCAx enable or up option. The next three sections describe these disable the interrupt function for each pin. Refer to functions. Register4-5. The interrupt-on-change is disabled on a Power-on Reset. 4.2.1 ANSEL REGISTER For enabled interrupt-on-change pins, the values are The ANSEL register is used to configure the Input compared with the old value latched on the last read of mode of an I/O pin to analog. Setting the appropriate PORTA. The ‘mismatch’ outputs of the last read are ANSEL bit high will cause all digital reads on the pin to OR’d together to set the PORTA Change Interrupt Flag be read as ‘0’ and allow analog functions on the pin to bit (RAIF) in the INTCON register (Register2-3). operate correctly. This interrupt can wake the device from Sleep. The The state of the ANSEL bits has no affect on digital user, in the Interrupt Service Routine, clears the output functions. A pin with TRIS clear and ANSEL set interrupt by: will still operate as a digital output, but the Input mode a) Any read or write of PORTA. This will end the will be analog. This can cause unexpected behavior mismatch condition, then, when executing read-modify-write instructions on the b) Clear the flag bit RAIF. affected port. A mismatch condition will continue to set flag bit RAIF. 4.2.2 WEAK PULL-UPS Reading PORTA will end the mismatch condition and allow flag bit RAIF to be cleared. The latch holding the Each of the PORTA pins, except RA3, has an last read value is not affected by a MCLR nor BOR individually configurable internal weak pull-up. Control Reset. After these resets, the RAIF flag will continue to bits WPUAx enable or disable each pull-up. Refer to be set if a mismatch is present. Register4-4. Each weak pull-up is automatically turned off when the port pin is configured as an output. The Note: If a change on the I/O pin should occur pull-ups are disabled on a Power-on Reset by the when any PORTA operation is being RAPU bit of the OPTION register). A weak pull-up is executed, then the RAIF interrupt flag may automatically enabled for RA3 when configured as not getset. MCLR and disabled when RA3 is an input. There is no software control of the MCLR pull-up. REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANS7 ANS6 ANS5 ANS4 ANS3(2) ANS2(2) ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2: PIC16F616/HV616. DS41288F-page 34 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 REGISTER 4-4: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPUA<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPUA<2:0>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global RAPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0). 3: The RA3 pull-up is enabled when configured as MCLR and disabled as an input in the Configuration Word. 4: WPUA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. REGISTER 4-5: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCA<5:0>: Interrupt-on-change PORTA Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2009 Microchip Technology Inc. DS41288F-page 35

PIC16F610/616/16HV610/616 4.2.4 PIN DESCRIPTIONS AND 4.2.4.2 RA1/AN1(1)/C12IN0-/VREF(1)/ DIAGRAMS ICSPCLK Each PORTA pin is multiplexed with other functions. Figure4-1 shows the diagram for this pin. The RA1 pin The pins and their combined functions are briefly is configurable to function as one of the following: described here. For specific information about • a general purpose I/O individual functions such as the Comparator or the (1) • an analog input for the ADC ADC, refer to the appropriate section in this data sheet. • an analog inverting input to the comparator 4.2.4.1 RA0/AN0(1)/C1IN+/ICSPDAT • a voltage reference input for the ADC(1) Figure4-1 shows the diagram for this pin. The RA0 pin • In-Circuit Serial Programming clock is configurable to function as one of the following: Note1: PIC16F616/16HV616 only. • a general purpose I/O (1) • an analog input for the ADC • an analog non-inverting input to the comparator • In-Circuit Serial Programming data FIGURE 4-1: BLOCK DIAGRAM OF RA<1:0> Analog(1) Input Mode VDD Data Bus D Q Weak WR CK Q WPUA RAPU RD VDD WPUA D Q WR CK I/O Pin Q PORTA VSS D Q WR CK TRISA Q RD TRISA Analog(1) Input Mode RD PORTA D Q Q D WR CK Q IOCA EN Q1 RD IOCA Q D Q S(2) EN Interrupt-on- Change From other R RA<5:1> pins (RA0) RD PORTA RA<5:2, 0> pins (RA1) To Comparator Write ‘0’ to RAIF To A/D Converter(3) Note 1: Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC16F616/16HV616 only. DS41288F-page 36 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 4.2.4.3 RA2/AN2(1)/T0CKI/INT/C1OUT Figure4-2 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: • a general purpose I/O (1) • an analog input for the ADC • the clock input for TMR0 • an external edge triggered interrupt • a digital output from Comparator C1 Note1: PIC16F616/16HV616 only. FIGURE 4-2: BLOCK DIAGRAM OF RA2 Analog(1) Input Mode VDD Data Bus D Q Weak WR CK Q C1OE WPUA Enable RAPU RD VDD WPUA C1OE 1 D Q 0 I/O Pin WR CK Q PORTA VSS D Q WR CK TRISA Q RD TRISA Analog(1) Input Mode RD PORTA D Q Q D WR CK Q IOAC EN Q1 RD IOAC Q D Q S(2) EN Interrupt-on- Change From other R RA<5:3, 1:0> pins RD PORTA Write ‘0’ to RAIF To Timer0 To INT To A/D Converter(3) Note 1: Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. DS41288F-page 37

PIC16F610/616/16HV610/616 4.2.4.4 RA3/MCLR/VPP Figure4-3 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset with weak pull-up • High Voltage Programming voltage input FIGURE 4-3: BLOCK DIAGRAM OF RA3 VDD MCLRE Weak Data Bus MCLRE Reset Input Pin RD VSS TRISA MCLRE VSS RD PORTA D Q Q D WR CK Q IOCA EN Q1 RD IOCA Q D Q S(1) EN Interrupt-on- Change From other R RA<5:4, 2:0> pins RD PORTA Write ‘0’ to RAIF Note 1: Set has priority over Reset DS41288F-page 38 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 4.2.4.5 RA4/AN3(1)/T1G/OSC2/CLKOUT • a Timer1 gate (count enable) Figure4-4 shows the diagram for this pin. The RA4 pin • a crystal/resonator connection is configurable to function as one of the following: • a clock output • a general purpose I/O Note1: PIC16F616/16HV616 only. (1) • an analog input for the ADC FIGURE 4-4: BLOCK DIAGRAM OF RA4 Analog(3) Input Mode CLK(1) Data Bus Modes D Q VDD WR CK Q Weak WPUA RD RAPU WPUA Oscillator Circuit OSC1 CLKOUT VDD Enable FOSC/4 1 D Q 0 WR CK I/O Pin Q PORTA CLKOUT Enable VSS D Q INTOSC/ WR CK RC/EC(2) TRISA Q CLKOUT RD Enable TRISA Analog Input Mode RD PORTA D Q Q D WR CK Q IOCA EN Q1 RD IOCA Q D Q S(4) EN Interrupt-on- Change From other R RA<5, 3:0> pins RD PORTA To T1G Write ‘0’ to RAIF To A/D Converter(5) Note1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable. 2: With CLKOUT option. 3: Analog Input mode comes from ANSEL. 4: Set has priority over Reset. 5: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. DS41288F-page 39

PIC16F610/616/16HV610/616 4.2.4.6 RA5/T1CKI/OSC1/CLKIN • a general purpose I/O Figure4-5 shows the diagram for this pin. The RA5 pin • a Timer1 clock input is configurable to function as one of the following: • a crystal/resonator connection • a clock input FIGURE 4-5: BLOCK DIAGRAM OF RA5 INTOSC Mode TMR1LPEN(1) Data Bus D Q VDD WR CK Weak Q WPUA RAPU RD WPUA Oscillator Circuit OSC2 VDD D Q WR CK Q PORTA I/O Pin D Q WR CK TRISA Q VSS INTOSC RD Mode TRISA RD PORTA D Q Q D WR CK Q IOCA EN Q1 RD IOCA Q D Q S(2) EN Interrupt-on- Change From other R RA<4:0> pins RD PORTA Write ‘0’ to RAIF To Timer1 Note 1: Timer1 LP Oscillator enabled. 2: Set has priority over Reset. DS41288F-page 40 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets ANSEL ANS7 ANS6 ANS5 ANS4 ANS3(1) ANS2(1) ANS1 ANS0 1111 1111 1111 1111 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 --u0 u000 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 WPUA — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 --11 -111 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: For PIC16F616/HV616 only. © 2009 Microchip Technology Inc. DS41288F-page 41

PIC16F610/616/16HV610/616 4.3 PORTC and the TRISC Registers EXAMPLE 4-2: INITIALIZING PORTC PORTC is a general purpose I/O port consisting of 6 BCF STATUS,RP0 ;Bank 0 CLRF PORTC ;Init PORTC bidirectional pins. The pins can be configured for either BSF STATUS,RP0 ;Bank 1 digital I/O or analog input to A/D Converter (ADC) or CLRF ANSEL ;digital I/O Comparator. For specific information about individual MOVLW 0Ch ;Set RC<3:2> as inputs functions such as the Enhanced CCP or the ADC, refer MOVWF TRISC ;and set RC<5:4,1:0> to the appropriate section in this data sheet. ;as outputs BCF STATUS,RP0 ;Bank 0 Note: The ANSEL register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt. REGISTER 4-6: PORTC: PORTC REGISTER U-0 U-0 R/W-x R/W-x R/W-0 R/W-0 R/W-x R/W-x — — RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RC<5:0>: PORTC I/O Pin bit 1 = PORTC pin is > VIH 0 = PORTC pin is < VIL REGISTER 4-7: TRISC: PORTC TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISC<5:0>: PORTC Tri-State Control bit 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output DS41288F-page 42 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 4.3.1 RC0/AN4(1)/C2IN+ 4.3.3 RC2/AN6(1)/C12IN2-/P1D(1) The RC0 is configurable to function as one of the The RC2 is configurable to function as one of the following: following: • a general purpose I/O • a general purpose I/O (1) (1) • an analog input for the ADC • an analog input for the ADC • an analog non-inverting input to Comparator C2 • an analog input to Comparators C1 and C2 (1) • a digital output from the Enhanced CCP 4.3.2 RC1/AN5(1)/C12IN1- 4.3.4 RC3/AN7(1)/C12IN3-/P1C(1) The RC1 is configurable to function as one of the following: The RC3 is configurable to function as one of the • a general purpose I/O following: (1) • an analog input for the ADC • a general purpose I/O • an analog inverting input to the comparator • an analog input for the ADC(1) Note1: PIC16F616/16HV616 only. • an analog inverting input to Comparators C1 and C2 (1) FIGURE 4-6: BLOCK DIAGRAM OF RC0 • a digital output from the Enhanced CCP AND RC1 Note1: PIC16F616/16HV616 only. Data Bus FIGURE 4-7: BLOCK DIAGRAM OF RC2 VDD AND RC3 D Q Data Bus WR CK Q CCPOUT(2) PORTC Enable VDD I/O Pin D Q D Q WR CK PORTC Q CCPOUT 1 WR CK TRISC Q VSS Analog Input 0 I/O Pin Mode(1) D Q RD TRISC WR CK TRISC Q VSS Analog Input RD Mode(1) PORTC RD To Comparators TRISC To A/D Converter RD PORTC Note 1: Analog Input mode comes from ANSEL or To A/D Converter Comparator mode. Note 1: Analog Input mode comes from ANSEL. 2: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. DS41288F-page 43

PIC16F610/616/16HV610/616 4.3.5 RC4/C2OUT/P1B(1) 4.3.6 RC5/CCP1(1)/P1A(1) The RC4 is configurable to function as one of the The RC5 is configurable to function as one of the following: following: • a general purpose I/O • a general purpose I/O (1) • a digital output from Comparator C2 • a digital input/output for the Enhanced CCP • a digital output from the Enhanced CCP(1) Note1: PIC16F616/16HV616 only. Note1: PIC16F616/16HV616 only. FIGURE 4-9: BLOCK DIAGRAM OF RC5 2: Enabling both C2OUT and P1B will cause PIN a conflict on RC4 and create unpredictable results. Therefore, if C2OUT is enabled, Data bus the ECCP can not be used in Half-Bridge or Full-Bridge mode and vice-versa. D Q CCP1OUT(1) VDD Enable FIGURE 4-8: BLOCK DIAGRAM OF RC4 WR CK PORTC Q CCP1OUT(1)/ 1 P1A C2OE 0 I/O Pin CCP1M<3:0> D Q C2OE C2OUT VDD WR CK TRISC Q VSS CCP1M<3:0> CCPOUT/P1B 1 RD TRISC 0 Data Bus I/O Pin D Q RD PORTC WR CK Q VSS PORTC To Enhanced CCP D Q Note 1: PIC16F616/16HV616 only. WR CK TRISC Q RD TRISC RD PORTC Note 1: Port/Peripheral Select signals selects between PORT data and peripheral output. TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets ANSEL ANS7 ANS6 ANS5 ANS4 ANS3(1) ANS2(1) ANS1 ANS0 1111 1111 1111 1111 CCP1CON(1) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx --uu 00uu TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Note 1: PIC16F616/HV616 only. DS41288F-page 44 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 5.0 TIMER0 MODULE 5.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the When used as a timer, the Timer0 module can be used following features: as either an 8-bit timer or an 8-bit counter. • 8-bit timer/counter register (TMR0) 5.1.1 8-BIT TIMER MODE • 8-bit prescaler (shared with Watchdog Timer) When used as a timer, the Timer0 module will • Programmable internal or external clock source increment every instruction cycle (without prescaler). • Programmable external clock edge selection Timer mode is selected by clearing the T0CS bit of the • Interrupt on overflow OPTION register to ‘0’. Figure5-1 is a block diagram of the Timer0 module. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. 5.1.2 8-BIT COUNTER MODE When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER FOSC/4 Data Bus 0 8 1 Sync 1 TMR0 2 Tcy T0CKI 0 pin 0 T0SE T0CS 8-bit Set Flag bit T0IF on Overflow Prescaler PSA 1 8 PSA 3 PS<2:0> 1 WDT Time-out Watchdog WDTE 0 Timer PSA Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: WDTE bit is in the Configuration Word register. © 2009 Microchip Technology Inc. DS41288F-page 45

PIC16F610/616/16HV610/616 5.1.3 SOFTWARE PROGRAMMABLE When changing the prescaler assignment from the PRESCALER WDT to the Timer0 module, the following instruction sequence must be executed (see Example5-2). A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer EXAMPLE 5-2: CHANGING PRESCALER (WDT), but not both simultaneously. The prescaler (WDT→TIMER0) assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit CLRWDT ;Clear WDT and must be cleared to a ‘0’. ;prescaler There are 8 prescaler options for the Timer0 module BANKSEL OPTION_REG ; MOVLW b’11110000’ ;Mask TMR0 select and ranging from 1:2 to 1:256. The prescale values are ANDWF OPTION_REG,W ;prescaler bits selectable via the PS<2:0> bits of the OPTION register. IORLW b’00000011’ ;Set prescale to 1:16 In order to have a 1:1 prescaler value for the Timer0 MOVWF OPTION_REG ; module, the prescaler must be assigned to the WDT module. 5.1.4 TIMER0 INTERRUPT The prescaler is not readable or writable. When Timer0 will generate an interrupt when the TMR0 assigned to the Timer0 module, all instructions writing to register overflows from FFh to 00h. The T0IF interrupt the TMR0 register will clear the prescaler. flag bit of the INTCON register is set every time the When the prescaler is assigned to WDT, a CLRWDT TMR0 register overflows, regardless of whether or not instruction will clear the prescaler along with the WDT. the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the 5.1.3.1 Switching Prescaler Between T0IE bit of the INTCON register. Timer0 and WDT Modules Note: The Timer0 interrupt cannot wake the As a result of having the prescaler assigned to either processor from Sleep since the timer is Timer0 or the WDT, it is possible to generate an frozen during Sleep. unintended device Reset when switching prescaler values. When changing the prescaler assignment from 5.1.5 USING TIMER0 WITH AN Timer0 to the WDT module, the instruction sequence EXTERNAL CLOCK shown in Example5-1 must be executed. When Timer0 is in Counter mode, the synchronization EXAMPLE 5-1: CHANGING PRESCALER of the T0CKI input and the Timer0 register is (TIMER0→WDT) accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. BANKSEL TMR0 ; Therefore, the high and low periods of the external CLRWDT ;Clear WDT clock source must meet the timing requirements as CLRF TMR0 ;Clear TMR0 and shown in Section15.0 “Electrical Specifications”. ;prescaler BANKSEL OPTION_REG ; BSF OPTION_REG,PSA ;Select WDT CLRWDT ; ; MOVLW b’11111000’ ;Mask prescaler ANDWF OPTION_REG,W ;bits IORLW b’00000101’ ;Set WDT prescaler MOVWF OPTION_REG ;to 1:32 DS41288F-page 46 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits BIT VALUE TMR0 RATE WDT RATE 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TMR0 Timer0 Modules Register xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module. © 2009 Microchip Technology Inc. DS41288F-page 47

PIC16F610/616/16HV610/616 NOTES: DS41288F-page 48 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 6.0 TIMER1 MODULE WITH GATE 6.1 Timer1 Operation CONTROL The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register The Timer1 module is a 16-bit timer/counter with the pair. Writes to TMR1H or TMR1L directly update the following features: counter. • 16-bit timer/counter register pair (TMR1H:TMR1L) When used with an internal clock source, the module is • Programmable internal or external clock source a timer. When used with an external clock source, the • 3-bit prescaler module can be used as either a timer or counter. • Optional LP oscillator • Synchronous or asynchronous operation 6.2 Clock Source Selection • Timer1 gate (count enable) via comparator or The TMR1CS bit of the T1CON register is used to select T1G pin the clock source. When TMR1CS = 0, the clock source • Interrupt on overflow is FOSC/4. When TMR1CS = 1, the clock source is • Wake-up on overflow (external clock, supplied externally. Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with ECCP) Clock Source TMR1CS T1ACS • Comparator output synchronization to Timer1 FOSC/4 0 0 clock FOSC 0 1 Figure6-1 is a block diagram of the Timer1 module. T1CKI pin 1 x FIGURE 6-1: TIMER1 BLOCK DIAGRAM TMR1GE T1GINV TMR1ON Set flag bit TMR1IF on To C2 Comparator Module Overflow TMR1(2) Timer1 Clock Synchronized EN 0 clock input TMR1H TMR1L 1 Oscillator (1) T1SYNC OSC1/T1CKI 1 Prescaler Synchronize(3) 1, 2, 4, 8 det 0 OSC2/T1G 2 T1CKPS<1:0> TMR1CS 1 INTOSC Without CLKOUT FOSC 1 C2OUT 0 T1OSCEN FOSC/4 Internal 0 T1GSS Clock T1ACS Note 1: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2009 Microchip Technology Inc. DS41288F-page 49

PIC16F610/616/16HV610/616 6.2.1 INTERNAL CLOCK SOURCE 6.5 Timer1 Operation in Asynchronous Counter Mode When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples If control bit T1SYNC of the T1CON register is set, the of TCY as determined by the Timer1 prescaler. external clock input is not synchronized. The timer continues to increment asynchronous to the internal 6.2.2 EXTERNAL CLOCK SOURCE phase clocks. The timer will continue to run during When the external clock source is selected, the Timer1 Sleep and can generate an interrupt on overflow, module may work as a timer or a counter. which will wake-up the processor. However, special When counting, Timer1 is incremented on the rising precautions in software are needed to read/write the edge of the external clock input T1CKI. In addition, the timer (see Section6.5.1 “Reading and Writing Counter mode clock can be synchronized to the Timer1 in Asynchronous Counter Mode”). microcontroller system clock or run asynchronously. Note: When switching from synchronous to If an external clock oscillator is needed (and the asynchronous operation, it is possible to microcontroller is using the INTOSC without CLKOUT), skip an increment. When switching from Timer1 can use the LP oscillator as a clock source. asynchronous to synchronous operation, it is possible to produce an additional Note: In Counter mode, a falling edge must be increment. registered by the counter prior to the first incrementing rising edge. Note: In asynchronous counter mode or when using the internal oscillator and T1ACS=1, 6.3 Timer1 Prescaler Timer1 can not be used as a time base for Timer1 has four prescaler options allowing 1, 2, 4 or 8 the capture or compare modes of the divisions of the clock input. The T1CKPS bits of the ECCP module (for PIC16F616/HV616 T1CON register control the prescale counter. The only). prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to 6.5.1 READING AND WRITING TIMER1 IN TMR1H or TMR1L. ASYNCHRONOUS COUNTER MODE 6.4 Timer1 Oscillator Reading TMR1H or TMR1L while the timer is running A low-power 32.768 kHz crystal oscillator is built-in from an external asynchronous clock will ensure a valid between pins OSC1 (input) and OSC2 (output). The read (taken care of in hardware). However, the user oscillator is enabled by setting the T1OSCEN control should keep in mind that reading the 16-bit timer in two bit of the T1CON register. The oscillator will continue to 8-bit values itself, poses certain problems, since the run during Sleep. timer may overflow between the reads. The Timer1 oscillator is shared with the system LP For writes, it is recommended that the user simply stop oscillator. Thus, Timer1 can use this mode only when the timer and write the desired values. A write the primary system clock is derived from the internal contention may occur by writing to the timer registers, oscillator or when the oscillator is in the LP Oscillator while the register is incrementing. This may produce an mode. The user must provide a software time delay to unpredictable value in the TMR1H:TMR1L register ensure proper oscillator start-up. pair. TRISA5 and TRISA4 bits are set when the Timer1 6.6 Timer1 Gate oscillator is enabled. RA5 and RA4 bits read as ‘0’ and TRISA5 and TRISA4 bits read as ‘1’. Timer1 gate source is software configurable to be the Note: The oscillator requires a start-up and T1G pin or the output of Comparator C2. This allows the stabilization time before use. Thus, device to directly time external events using T1G or T1OSCEN should be set and a suitable analog events using Comparator C2. See the delay observed prior to enabling Timer1. CM2CON1 register (Register8-3) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many DS41288F-page 50 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 other applications. For more information on Delta-Sigma In Capture mode, the value in the TMR1H:TMR1L A/D converters, see the Microchip web site register pair is copied into the CCPR1H:CCPR1L (www.microchip.com). register pair on a configured event. Note: TMR1GE bit of the T1CON register must In Compare mode, an event is triggered when the value be set to use either T1G or C2OUT as the CCPR1H:CCPR1L register pair matches the value in Timer1 gate source. See the CM2CON1 the TMR1H:TMR1L register pair. This event can be a register (Register8-3) for more informa- Special Event Trigger. tion on selecting the Timer1 gate source. For more information, see Section10.0 “Enhanced Timer1 gate can be inverted using the T1GINV bit of Capture/Compare/PWM (With Auto-Shutdown and the T1CON register, whether it originates from the T1G Dead Band) Module (PIC16F616/16HV616 Only)”. pin or Comparator C2 output. This configures Timer1 to measure either the active-high or active-low time 6.10 ECCP Special Event Trigger between events. (PIC16F616/16HV616 Only) When the ECCP is configured to trigger a special 6.7 Timer1 Interrupt event, the trigger will clear the TMR1H:TMR1L register The Timer1 register pair (TMR1H:TMR1L) increments pair. This special event does not cause a Timer1 inter- to FFFFh and rolls over to 0000h. When Timer1 rolls rupt. The ECCP module may still be configured to gen- over, the Timer1 interrupt flag bit of the PIR1 register is erate a ECCP interrupt. set. To enable the interrupt on rollover, you must set In this mode of operation, the CCPR1H:CCPR1L register these bits: pair effectively becomes the period register for Timer1. • TMR1IE bit of the PIE1 register Timer1 should be synchronized to the FOSC to utilize the • PEIE bit of the INTCON register Special Event Trigger. Asynchronous operation of • GIE bit of the INTCON register Timer1 can cause a Special Event Trigger to be missed. • T1SYNC bit of the T1CON register In the event that a write to TMR1H or TMR1L coincides • TMR1CS bit of the T1CON register with a Special Event Trigger from the ECCP, the write • T1OSCEN bit of the T1CON register (can be set) will take precedence. The interrupt is cleared by clearing the TMR1IF bit in For more information, see Section10.2.4 “Special the Interrupt Service Routine. Event Trigger”. Note: The TMR1H:TTMR1L register pair and the 6.11 Comparator Synchronization TMR1IF bit should be cleared before enabling interrupts. The same clock used to increment Timer1 can also be used to synchronize the comparator output. This 6.8 Timer1 Operation During Sleep feature is enabled in the Comparator module. When using the comparator for Timer1 gate, the Timer1 can only operate during Sleep when setup in comparator output should be synchronized to Timer1. Asynchronous Counter mode. In this mode, an external This ensures Timer1 does not miss an increment if the crystal or clock source can be used to increment the comparator changes. counter. To set up the timer to wake the device: For more information, see Section8.8.2 • TMR1ON bit of the T1CON register must be set “Synchronizing Comparator C2 Output to Timer1”. • TMR1IE bit of the PIE1 register must be set • PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). 6.9 ECCP Capture/Compare Time Base (PIC16F616/16HV616 Only) The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. © 2009 Microchip Technology Inc. DS41288F-page 51

PIC16F610/616/16HV610/616 FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 6.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register6-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 6 TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 Gate function 0 = Timer1 is always counting bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value bit 3 T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored DS41288F-page 52 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (CONTINUED) bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock If TMR1ACS = 0: FOSC/4 If TMR1ACS = 1: FOSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register, as a Timer1 gate source. © 2009 Microchip Technology Inc. DS41288F-page 53

PIC16F610/616/16HV610/616 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 CM2CON1 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 00-0 0010 INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: PIC16F616/16HV616 only. DS41288F-page 54 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 7.0 TIMER2 MODULE The TMR2 and PR2 registers are both fully readable (PIC16F616/16HV616 ONLY) and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. The Timer2 module is an 8-bit timer with the following Timer2 is turned on by setting the TMR2ON bit in the features: T2CON register to a ‘1’. Timer2 is turned off by setting • 8-bit timer register (TMR2) the TMR2ON bit to a ‘0’. • 8-bit period register (PR2) The Timer2 prescaler is controlled by the T2CKPS bits • Interrupt on TMR2 match with PR2 in the T2CON register. The Timer2 postscaler is • Software programmable prescaler (1:1, 1:4, 1:16) controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared • Software programmable postscaler (1:1 to 1:16) when: See Figure7-1 for a block diagram of Timer2. • A write to TMR2 occurs. • A write to T2CON occurs. 7.1 Timer2 Operation • Any device Reset occurs (Power-on Reset, MCLR The clock input to the Timer2 module is the system Reset, Watchdog Timer Reset, or Brown-out instruction clock (FOSC/4). The clock is fed into the Reset). Timer2 prescaler, which has prescale options of 1:1, Note: TMR2 is not cleared when T2CON is 1:4 or 1:16. The output of the prescaler is then used to written. increment the TMR2 register. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: • TMR2 is reset to 00h on the next increment cycle. • The Timer2 postscaler is incremented The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. FIGURE 7-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 bit TMR2IF Output Prescaler Reset FOSC/4 TMR2 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T2CKPS<1:0> PR2 4 TOUTPS<3:0> © 2009 Microchip Technology Inc. DS41288F-page 55

PIC16F610/616/16HV610/616 REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 TABLE 7-1: SUMMARY OF ASSOCIATED TIMER2 REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00 PR2(1) Timer2 Module Period Register 1111 1111 1111 1111 TMR2(1) Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000 T2CON(1) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. Note 1: PIC16F616/16HV616 only. DS41288F-page 56 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 8.0 COMPARATOR MODULE FIGURE 8-1: SINGLE COMPARATOR Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and VIN+ + providing a digital indication of their relative magnitudes. Output The comparators are very useful mixed signal building VIN- – blocks because they provide analog functionality independent of the device. The Analog Comparator module includes the following features: • Independent comparator control VIN- • Programmable input selection VIN+ • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change Output • Wake-up from Sleep • PWM shutdown • Timer1 gate (count enable) Note: The black areas of the output of the • Output synchronization to Timer1 clock input comparator represents the uncertainty • SR Latch due to input offsets and response time. • Programmable and fixed voltage reference • User-enable Comparator Hysteresis Note: Only Comparator C2 can be linked to Timer1. 8.1 Comparator Overview A single comparator is shown in Figure8-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. © 2009 Microchip Technology Inc. DS41288F-page 57

PIC16F610/616/16HV610/616 FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> 2 C1POL To D Q Data Bus Q1 C12IN0- 0 EN RD_CM1CON0 C12IN1- 1 MUX Set C1IF D Q C12IN2- 2 Q3*RD_CM1CON0 EN C12IN3- 3 CL To PWM Logic Reset C1ON(1) C1R C1OE C1VIN- - C1IN+ 0 C1 C1OUT MUX C1VIN+ + C1VREF 1 C1OUT pin(2) C1POL Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. 2: Output shown for reference only. See I/O port pin block diagram for more detail. FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM C2POL To D Q Data Bus Q1 EN RD_CM2CON0 C2CH<1:0> Set C2IF 2 D Q Q3*RD_CM2CON0 C12IN0- 0 C2ON(1) ENCL Reset C12IN1- 1 MUX C2VIN- C2IN2- 2 C2VIN+ C2 C2OUT To other peripherals C2IN3- 3 C2SYNC C2OE C2POL C2R 0 MUX D Q 1 C2OUT pin(2) C2IN+ 0 MUX From Timer1 Clock SYNCC2OUT C2VREF 1 To Timer1 Gate To SR Latch Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate. 2: Output shown for reference only. See I/O port pin block diagram for more detail. DS41288F-page 58 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 8.2 Comparator Control 8.2.4 COMPARATOR OUTPUT SELECTION Each comparator has a separate control and The output of the comparator can be monitored by Configuration register: CM1CON0 for Comparator C1 reading either the CxOUT bit of the CMxCON0 register and CM2CON0 for Comparator C2. In addition, or the MCxOUT bit of the CM2CON1 register. In order Comparator C2 has a second control register, to make the output available for an external connection, CM2CON1, for controlling the interaction with Timer1 and the following conditions must be true: simultaneous reading of both comparator outputs. • CxOE bit of the CMxCON0 register must be set The CM1CON0 and CM2CON0 registers (see Registers • Corresponding TRIS bit must be cleared 8-1 and 8-2, respectively) contain the control and Status • CxON bit of the CMxCON0 register must be set. bits for the following: Note1: The CxOE bit overrides the PORT data • Enable latch. Setting the CxON has no impact on • Input selection the port override. • Reference selection 2: The internal output of the comparator is • Output selection latched with each instruction cycle. Unless otherwise specified, external • Output polarity outputs are not latched. 8.2.1 COMPARATOR ENABLE 8.2.5 COMPARATOR OUTPUT POLARITY Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit Inverting the output of the comparator is functionally disables the comparator for minimum current equivalent to swapping the comparator inputs. The consumption. polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. 8.2.2 COMPARATOR INPUT SELECTION Clearing the CxPOL bit results in a non-inverted output. The CxCH<1:0> bits of the CMxCON0 register direct Table8-1 shows the output state versus input one of four analog input pins to the comparator conditions, including polarity control. inverting input. TABLE 8-1: COMPARATOR OUTPUT STATE VS. INPUT Note: To use CxIN+ and CxIN- pins as analog CONDITIONS inputs, the appropriate bits must be set in the ANSEL register and the corresponding Input Condition CxPOL CxOUT TRIS bits must also be set to disable the output drivers. CxVIN- > CxVIN+ 0 0 CxVIN- < CxVIN+ 0 1 8.2.3 COMPARATOR REFERENCE CxVIN- > CxVIN+ 1 1 SELECTION CxVIN- < CxVIN+ 1 0 Setting the CxR bit of the CMxCON0 register directs an internal voltage reference or an analog input pin to the 8.3 Comparator Response Time non-inverting input of the comparator. See Section8.11 “Comparator Voltage Reference” for more information The comparator output is indeterminate for a period of on the internal voltage reference module. time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section15.0 “Electrical Specifications” for more details. © 2009 Microchip Technology Inc. DS41288F-page 59

PIC16F610/616/16HV610/616 8.4 Comparator Interrupt Operation FIGURE 8-4: COMPARATOR INTERRUPT TIMING W/O The comparator interrupt flag can be set whenever CMxCON0 READ there is a change in the output value of the comparator. Changes are recognized by means of a mismatch Q1 circuit which consists of two latches and an Q3 exclusive-or gate (see Figure8-2 and Figure8-3). One latch is updated with the comparator output level when CxIN+ TRT the CMxCON0 register is read. This latch retains the CxOUT value until the next read of the CMxCON0 register or Set CxIF (edge) the occurrence of a Reset. The other latch of the CxIF mismatch circuit is updated on every Q1 system clock. reset by software A mismatch condition will occur when a comparator output change is clocked through the second latch on FIGURE 8-5: COMPARATOR the Q1 clock cycle. At this point the two mismatch INTERRUPT TIMING WITH latches have opposite output levels which is detected CMxCON0 READ by the exclusive-or gate and fed to the interrupt circuitry. The mismatch condition persists until either Q1 the CMxCON0 register is read or the comparator output returns to the previous state. Q3 CxIN+ TRT Note 1: A write operation to the CMxCON0 CxOUT register will also clear the mismatch condition because all writes include a read Set CxIF (edge) operation at the beginning of the write CxIF cycle. cleared by CMxCON0 read reset by software 2: Comparator interrupts will operate correctly regardless of the state of CxOE. The comparator interrupt is set by the mismatch edge Note1: If a change in the CMxCON0 register and not the mismatch level. This means that the inter- (CxOUT) should occur when a read oper- rupt flag can be reset without the additional step of ation is being executed (start of the Q2 reading or writing the CMxCON0 register to clear the cycle), then the CxIF of the PIR1 register mismatch registers. When the mismatch registers are interrupt flag may not get set. cleared, an interrupt will occur upon the comparator’s 2: When either comparator is first enabled, return to the previous state, otherwise no interrupt will bias circuitry in the comparator module be generated. may cause an invalid output from the Software will need to maintain information about the comparator until the bias circuitry is stable. status of the comparator output, as read from the Allow about 1 μs for bias settling then clear CMxCON0 register, or CM2CON1 register, to determine the mismatch condition and interrupt flags the actual change that has occurred. before enabling comparator interrupts. The CxIF bit of the PIR1 register is the comparator interrupt flag. This bit must be reset in software by clearing it to ‘0’. Since it is also possible to write a ‘1’ to this register, an interrupt can be generated. The CxIE bit of the PIE1 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CxIF bit of the PIR1 register will still be set if an interrupt condition occurs. DS41288F-page 60 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 8.5 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section15.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CxIE bit of the PIE1 register and the PEIE bit of the INTCON register must be set. The instruction following the Sleep instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the interrupt service routine. 8.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their OFF states. © 2009 Microchip Technology Inc. DS41288F-page 61

PIC16F610/616/16HV610/616 REGISTER 8-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT = 0 when C1VIN+ > C1VIN- C1OUT = 1 when C1VIN+ < C1VIN- If C1POL = 0 (non-inverted polarity): C1OUT = 1 when C1VIN+ > C1VIN- C1OUT = 0 when C1VIN+ < C1VIN- bit 5 C1OE: Comparator C1 Output Enable bit 1 = C1OUT is present on the C1OUT pin(1) 0 = C1OUT is internal only bit 4 C1POL: Comparator C1 Output Polarity Select bit 1 = C1OUT logic is inverted 0 = C1OUT logic is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 C1R: Comparator C1 Reference Select bit (non-inverting input) 1 = C1VIN+ connects to C1VREF output 0 = C1VIN+ connects to C1IN+ pin bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit 00 = C12IN0- pin of C1 connects to C1VIN- 01 = C12IN1- pin of C1 connects to C1VIN- 10 = C12IN2- pin of C1 connects to C1VIN- 11 = C12IN3- pin of C1 connects to C1VIN- Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port TRIS bit = 0. DS41288F-page 62 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 REGISTER 8-2: CM2CON0: COMPARATOR 2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT = 0 when C2VIN+ > C2VIN- C2OUT = 1 when C2VIN+ < C2VIN- If C2POL = 0 (non-inverted polarity): C2OUT = 1 when C2VIN+ > C2VIN- C2OUT = 0 when C2VIN+ < C2VIN- bit 5 C2OE: Comparator C2 Output Enable bit 1 = C2OUT is present on C2OUT pin(1) 0 = C2OUT is internal only bit 4 C2POL: Comparator C2 Output Polarity Select bit 1 = C2OUT logic is inverted 0 = C2OUT logic is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input) 1 = C2VIN+ connects to C2VREF 0 = C2VIN+ connects to C2IN+ pin bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits 00 = C2VIN- pin of C2 connects to C12IN0- 01 = C2VIN- pin of C2 connects to C12IN1- 10 = C2VIN- pin of C2 connects to C12IN2- 11 = C2VIN- pin of C2 connects to C12IN3- Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port TRIS bit = 0. © 2009 Microchip Technology Inc. DS41288F-page 63

PIC16F610/616/16HV610/616 8.7 Comparator Analog Input Connection Considerations Note1: When reading a PORT register, all pins configured as analog inputs will read as a A simplified circuit for an analog input is shown in ‘0’. Pins configured as digital inputs will Figure8-6. Since the analog input pins share their convert as an analog input, according to connection with a digital input, they have reverse the input specification. biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. 2: Analog levels on any pin defined as a If the input voltage deviates from this range by more digital input, may cause the input buffer to than 0.6V in either direction, one of the diodes is consume more current than is specified. forward biased and a latch-up may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. FIGURE 8-6: ANALOG INPUT MODEL VDD Rs < 10K VT ≈ 0.6V RIC To ADC Input AIN VA C5 PpIFN VT ≈ 0.6V I±L5E0A0K AnGAE Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage DS41288F-page 64 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 8.8 Additional Comparator Features 8.8.2 SYNCHRONIZING COMPARATOR C2 OUTPUT TO TIMER1 There are three additional comparator features: The Comparator C2 output can be synchronized with • Timer1 count enable (gate) Timer1 by setting the C2SYNC bit of the CM2CON1 • Synchronizing output with Timer1 register. When enabled, the C2 output is latched on the • Simultaneous read of comparator outputs falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after 8.8.1 COMPARATOR C2 GATING TIMER1 the prescaling function. To prevent a race condition, the This feature can be used to time the duration or interval comparator output is latched on the falling edge of the of analog events. Clearing the T1GSS bit of the Timer1 clock source and Timer1 increments on the CM2CON1 register will enable Timer1 to increment rising edge of its clock source. See the Comparator based on the output of Comparator C2. This requires Block Diagram (Figure8-3) and the Timer1 Block that Timer1 is on and gating is enabled. See Diagram (Figure6-1) for more information. Section6.0 “Timer1 Module with Gate Control” for 8.8.3 SIMULTANEOUS COMPARATOR details. OUTPUT READ It is recommended to synchronize the comparator with Timer1 by setting the C2SYNC bit when the comparator The MC1OUT and MC2OUT bits of the CM2CON1 is used as the Timer1 gate source. This ensures Timer1 register are mirror copies of both comparator outputs. does not miss an increment if the comparator changes The ability to read both outputs simultaneously from a during an increment. single register eliminates the timing skew of reading separate registers. Note1: Obtaining the status of C1OUT or C2OUT by reading CM2CON1 does not affect the comparator interrupt mismatch registers. REGISTER 8-3: CM2CON1: COMPARATOR 2 CONTROL REGISTER 1 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 Unimplemented: Read as ‘0’ bit 4 T1ACS: Timer1 Alternate Clock Select bit 1 = Timer1 clock source is the system clock (FOSC) 0 = Timer1 clock source is the internal clock FOSC/4) bit 3 C1HYS: Comparator C1 Hysteresis Enable bit 1 = Comparator C1 Hysteresis enabled 0 = Comparator C1 Hysteresis disabled bit 2 C2HYS: Comparator C2 Hysteresis Enable bit 1 = Comparator C2 Hysteresis enabled 0 = Comparator C2 Hysteresis disabled bit 1 T1GSS: Timer1 Gate Source Select bit 1 = Timer1 gate source is T1G 0 = Timer1 gate source is SYNCC2OUT. bit 0 C2SYNC: Comparator C2 Output Synchronization bit 1 = C2 Output is synchronous to falling edge of Timer1 clock 0 = C2 Output is asynchronous © 2009 Microchip Technology Inc. DS41288F-page 65

PIC16F610/616/16HV610/616 8.9 Comparator Hysteresis Figure8-9 shows the relationship between the analog input levels and digital output of a comparator with and Each comparator has built-in hysteresis that is user without hysteresis. The output of the comparator enabled by setting the C1HYS or C2HYS bits of the changes from a low state to a high state only when the CM2CON1 register. The hysteresis feature can help analog voltage at VIN+ rises above the upper filter noise and reduce multiple comparator output hysteresis threshold (VH+). The output of the transitions when the output is changing state. comparator changes from a high state to a low state only when the analog voltage at VIN+ falls below the lower hysteresis threshold (VH-). FIGURE 8-7: COMPARATOR HYSTERESIS VIN+ + Output VIN- – V+ VH+ VIN- VH- VIN+ Output (Without Hysteresis) Output (With Hysteresis) Note: The black areas of the comparator output represents the uncertainty due to input offsets and response time. DS41288F-page 66 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets ANSEL ANS7 ANS6 ANS5 ANS4 ANS3(1) ANS2(1) ANS1 ANS0 1111 1111 1111 1111 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 0000 0000 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 0000 0000 CM2CON1 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 00-0 0010 INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 --x0 x000 PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx --uu 00uu SRCON0 SR1 SR0 C1SEN C2REN PULSS PULSR — SRCLKEN 0000 00-0 0000 00-0 SRCON1 SRCS1 SRCS0 — — — — — — 00-- ---- 00-- ---- TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISC TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 VRCON C1VREN C2VREN VRR FVREN VR3 VR2 VR1 VR0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. DS41288F-page 67

PIC16F610/616/16HV610/616 8.10 Comparator SR Latch inputs are high the latch will go to the Reset state. Both the PULSS and PULSR bits are self resetting which The SR latch module provides additional control of the means that a single write to either of the bits is all that is comparator outputs. The module consists of a single necessary to complete a latch Set or Reset operation. SR latch and output multiplexers. The SR latch can be set, reset or toggled by the comparator outputs. The SR 8.10.2 LATCH OUTPUT latch may also be set or reset, independent of The SR<1:0> bits of the SRCON0 register control the comparator output, by control bits in the SRCON0 latch output multiplexers and determine four possible control register. The SR latch output multiplexers select output configurations. In these four configurations, the whether the latch outputs or the comparator outputs are CxOUT I/O port logic is connected to: directed to the I/O port logic for eventual output to a pin. • C1OUT and C2OUT The SR latch also has a variable clock, which is • C1OUT and SR latch Q connected to the set input of the latch. The SRCLKEN bit of SRCON0 enables the SR latch set clock. The • C2OUT and SR latch Q clock will periodically pulse the set input of the latch. • SR latch Q and Q Control over the frequency of the SR latch set clock is After any Reset, the default output configuration is the provided by the SRCS<1:0> bits of SRCON1 register. unlatched C1OUT and C2OUT mode. This maintains compatibility with devices that do not have the SR latch 8.10.1 LATCH OPERATION feature. The latch is a Set-Reset latch that does not depend on a The applicable TRIS bits of the corresponding ports clock source. Each of the Set and Reset inputs are must be cleared to enable the port pin output drivers. active-high. Each latch input is connected to a Additionally, the CxOE comparator output enable bits of comparator output and a software controlled pulse the CMxCON0 registers must be set in order to make the generator. The latch can be set by C1OUT or the PULSS comparator or latch outputs available on the output pins. bit of the SRCON0 register. The latch can be reset by The latch configuration enable states are completely C2OUT or the PULSR bit of the SRCON0 register. The independent of the enable states for the comparators. latch is reset-dominant, therefore, if both Set and Reset FIGURE 8-8: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRCLKEN SRCLK SR0 C1OE PULSS Pulse Gen(2) 0 C1OUT (from comparator) MUX S Q 1 C1OUT pin(3) C1SEN SR Latch(1) C2OE SYNCC2OUT (from comparator) R Q 1 C2REN MUX 0 C2OUT pin(3) PULSR Pulse SR1 Gen(2) Note 1: If R=1 and S=1 simultaneously, Q=0, Q=1 2: Pulse generator causes a 1 TOSC pulse width. 3: Output shown for reference only. See I/O port pin block diagram for more detail. DS41288F-page 68 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 REGISTER 8-4: SRCON0: SR LATCH CONTROL 0 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 R/W-0 SR1(2) SR0(2) C1SEN C2REN PULSS PULSR — SRCLKEN bit 7 bit 0 Legend: S = Bit is set only - R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SR1: SR Latch Configuration bit(2) 1 = C2OUT pin is the latch Q output 0 = C2OUT pin is the C2 comparator output bit 6 SR0: SR Latch Configuration bits(2) 1 = C1OUT pin is the latch Q output 0 = C1OUT pin is the C1 Comparator output bit 5 C1SEN: C1 Set Enable bit 1 = C1 comparator output sets SR latch 0 = C1 comparator output has no effect on SR latch bit 4 C2REN: C2 Reset Enable bit 1 = C2 comparator output resets SR latch 0 = C2 comparator output has no effect on SR latch bit 3 PULSS: Pulse the SET Input of the SR Latch bit 1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware. 0 = Does not trigger pulse generator bit 2 PULSR: Pulse the Reset Input of the SR Latch bit 1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware. 0 = Does not trigger pulse generator bit 1 Unimplemented: Read as ‘0’ bit 0 SRCLKEN: SR Latch Set Clock Enable bit 1 = Set input of SR latch is pulsed with SRCLK 0 = Set input of SR latch is not pulsed with the SRCLK Note 1: The C1OUT and C2OUT bits in the CMxCON0 register will always reflect the actual comparator output (not the level on the pin), regardless of the SR latch operation. 2: To enable an SR Latch output to the pin, the appropriate CxOE, and TRIS bits must be properly configured. REGISTER 8-5: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 SRCS1 SRCS0 — — — — — — bit 7 bit 0 Legend: S = Bit is set only - R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 SRCS<1:0>: SR Latch Clock Prescale bits 00 = FOSC/16 01 = FOSC/32 10 = FOSC/64 11 = FOSC/128 bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS41288F-page 69

PIC16F610/616/16HV610/616 8.11 Comparator Voltage Reference 8.11.3 OUTPUT CLAMPED TO VSS The comparator voltage reference module provides an The fixed voltage reference output voltage can be set internally generated voltage reference for the to Vss with no power consumption by clearing the comparators. The following features are available: FVREN bit of the VRCON register (FVREN=0). This allows the comparator to detect a zero-crossing while • Independent from Comparator operation not consuming additional module current. • Two 16-level voltage ranges • Output clamped to VSS 8.11.4 OUTPUT RATIOMETRIC TO VDD • Ratiometric with VDD The comparator voltage reference is VDD derived and • Fixed Reference (0.6V) therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator The VRCON register (Register8-6) controls the Voltage Reference can be found in Section15.0 voltage reference module shown in Figure8-9. “Electrical Specifications”. 8.11.1 INDEPENDENT OPERATION The comparator voltage reference is independent of the comparator configuration. Setting the FVREN bit of the VRCON register will enable the voltage reference. 8.11.2 OUTPUT VOLTAGE SELECTION The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON register. The CVREF output voltage is determined by the following equations: EQUATION 8-1: CVREF OUTPUT VOLTAGE VRR = 1 (low range): CVREF = (VR<3:0>/24)×VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR<3:0>×VDD/32) The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure8-9. DS41288F-page 70 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 8.11.5 FIXED VOLTAGE REFERENCE 8.11.7 VOLTAGE REFERENCE SELECTION The fixed voltage reference is independent of VDD, with a nominal output voltage of 0.6V. This reference can be Multiplexers on the output of the voltage reference enabled by setting the FVREN bit of the VRCON module enable selection of either the CVREF or fixed register to ‘1’. This reference is always enabled when voltage reference for use by the comparators. the HFINTOSC oscillator is active. Setting the C1VREN bit of the VRCON register enables 8.11.6 FIXED VOLTAGE REFERENCE current to flow in the CVREF voltage divider and selects the CVREF voltage for use by C1. Clearing the STABILIZATION PERIOD C1VREN bit selects the fixed voltage for use by C1. When the fixed voltage reference module is enabled, it Setting the C2VREN bit of the VRCON register enables will require some time for the reference and its amplifier current to flow in the CVREF voltage divider and selects circuits to stabilize. The user program must include a the CVREF voltage for use by C2. Clearing the small delay routine to allow the module to settle. See C2VREN bit selects the fixed voltage for use by C2. the electrical specifications section for the minimum delay requirement. When both the C1VREN and C2VREN bits are cleared, current flow in the CVREF voltage divider is disabled minimizing the power drain of the voltage reference peripheral. FIGURE 8-9: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR Analog MUX 15 CVREF To Comparators and ADC Module 0 VR<3:0>(1) C1VREN 4 C2VREN To ADC Module 1.2V FVREN EN Fixed Ref 0.6V Fixed Voltage To Comparators Reference and ADC Module Note 1: Care should be taken to ensure VREF remains within the comparator common mode input range. See Section15.0 “Electrical Specifications” for more detail. © 2009 Microchip Technology Inc. DS41288F-page 71

PIC16F610/616/16HV610/616 REGISTER 8-6: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1VREN C2VREN VRR FVREN VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1VREN: Comparator 1 Voltage Reference Enable bit 1 = CVREF circuit powered on and routed to C1VREF input of Comparator C1 0 = 0.6 Volt constant reference routed to C1VREF input of Comparator C1 bit 6 C2VREN: Comparator 2 Voltage Reference Enable bit 1 = CVREF circuit powered on and routed to C2VREF input of Comparator C2 0 = 0.6 Volt constant reference routed to C2VREF input of Comparator C2 bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 FVREN: Fixed Voltage Reference (0.6V) Enable bit 1 = Enabled 0 = Disabled bit 3-0 VR<3:0>: Comparator Voltage Reference CVREF Value Selection bits (0 ≤ VR<3:0> ≤ 15) When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD DS41288F-page 72 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 9.0 ANALOG-TO-DIGITAL Note: The ADRESL and ADRESH registers are CONVERTER (ADC) MODULE read-only. (PIC16F616/16HV616 ONLY) The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. Figure9-1 shows the block diagram of the ADC. FIGURE 9-1: ADC BLOCK DIAGRAM VDD VCFG = 0 VREF VCFG = 1 RA0/AN0 RA1/AN1/VREF RA2/AN2 RA4/AN3 RC0/AN4 RC1/AN5 RC2/AN6 ADC RC3/AN7 CVREF GO/DONE 10 0.6V Reference 0 = Left Justify ADFM 1.2V Reference 1 = Right Justify 4 ADON 10 CHS <3:0> VSS ADRESH ADRESL © 2009 Microchip Technology Inc. DS41288F-page 73

PIC16F610/616/16HV610/616 9.1 ADC Configuration 9.1.4 CONVERSION CLOCK When configuring and using the ADC, the following The source of the conversion clock is software functions must be considered: selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: • Port configuration • FOSC/2 • Channel selection • FOSC/4 • ADC voltage reference selection • FOSC/8 • ADC conversion clock source • FOSC/16 • Interrupt control • FOSC/32 • Results formatting • FOSC/64 9.1.1 PORT CONFIGURATION • FRC (dedicated internal oscillator) The ADC can be used to convert both analog and digital The time to complete one bit conversion is defined as signals. When converting analog signals, the I/O pin TAD. One full 10-bit conversion requires 11 TAD periods should be configured for analog by setting the associated as shown in Figure9-3. TRIS and ANSEL bits. See the corresponding Port For correct conversion, the appropriate TAD specification section for more information. must be met. See A/D conversion requirements in Note: Analog voltages on any pin that is defined Section15.0 “Electrical Specifications” for more as a digital input may cause the input buf- information. Table9-1 gives examples of appropriate fer to conduct excess current. ADC clock selections. Note: Unless using the FRC, any changes in the 9.1.2 CHANNEL SELECTION system clock frequency will change the The CHS bits of the ADCON0 register determine which ADC clock frequency, which may channel is connected to the sample and hold circuit. adversely affect the ADC result. When changing channels, a delay is required before starting the next conversion. Refer to Section9.2 “ADC Operation” for more information. 9.1.3 ADC VOLTAGE REFERENCE The VCFG bit of the ADCON0 register provides control of the positive voltage reference. The positive voltage reference can be either VDD or an external voltage source. The negative voltage reference is always connected to the ground reference. TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 100 ns(2) 250 ns(2) 500 ns(2) 2.0 μs FOSC/4 100 200 ns(2) 500 ns(2) 1.0 μs(2) 4.0 μs FOSC/8 001 400 ns(2) 1.0 μs(2) 2.0 μs 8.0 μs(3) FOSC/16 101 800 ns(2) 2.0 μs 4.0 μs 16.0 μs(3) FOSC/32 010 1.6 μs 4.0 μs 8.0 μs(3) 32.0 μs(3) FOSC/64 110 3.2 μs 8.0 μs(3) 16.0 μs(3) 64.0 μs(3) FRC x11 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 4 μs for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. DS41288F-page 74 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY to TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input 9.1.5 INTERRUPTS 9.1.6 RESULT FORMATTING The ADC module allows for the ability to generate an The 10-bit A/D conversion result can be supplied in two interrupt upon completion of an analog-to-digital formats, left justified or right justified. The ADFM bit of conversion. The ADC interrupt flag is the ADIF bit in the the ADCON0 register controls the output format. PIR1 register. The ADC interrupt enable is the ADIE bit Figure9-4 shows the two output formats. in the PIE1 register. The ADIF bit must be cleared in software. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the interrupt service routine. Please see Section9.1.5 “Interrupts” for more information. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result © 2009 Microchip Technology Inc. DS41288F-page 75

PIC16F610/616/16HV610/616 9.2 ADC Operation 9.2.5 SPECIAL EVENT TRIGGER The ECCP Special Event Trigger allows periodic ADC 9.2.1 STARTING A CONVERSION measurements without software intervention. When To enable the ADC module, the ADON bit of the this trigger occurs, the GO/DONE bit is set by hardware ADCON0 register must be set to a ‘1’. Setting the GO/ and the Timer1 counter resets to zero. DONE bit of the ADCON0 register to a ‘1’ will start the Using the Special Event Trigger does not ensure analog-to-digital conversion. proper ADC timing. It is the user’s responsibility to Note: The GO/DONE bit should not be set in the ensure that the ADC timing requirements are met. same instruction that turns on the ADC. See Section10.0 “Enhanced Capture/Compare/ Refer to Section9.2.6 “A/D Conversion PWM (With Auto-Shutdown and Dead Band) Procedure”. Module (PIC16F616/16HV616 Only)” for more information. 9.2.2 COMPLETION OF A CONVERSION 9.2.6 A/D CONVERSION PROCEDURE When the conversion is complete, the ADC module will: • Clear the GO/DONE bit This is an example procedure for using the ADC to perform an analog-to-digital conversion: • Set the ADIF flag bit • Update the ADRESH:ADRESL registers with new 1. Configure Port: conversion result • Disable pin output driver (See TRIS register) • Configure pin as analog 9.2.3 TERMINATING A CONVERSION 2. Configure the ADC module: If a conversion must be terminated before completion, • Select ADC conversion clock the GO/DONE bit can be cleared in software. The • Configure voltage reference ADRESH:ADRESL registers will not be updated with • Select ADC input channel the partially complete analog-to-digital conversion • Select result format sample. Instead, the ADRESH:ADRESL register pair will retain the value of the previous conversion. Addi- • Turn on ADC module tionally, a 2TAD delay is required before another acqui- 3. Configure ADC interrupt (optional): sition can be initiated. Following this delay, an input • Clear ADC interrupt flag acquisition is automatically started on the selected • Enable ADC interrupt channel. • Enable peripheral interrupt Note: A device Reset forces all registers to their • Enable global interrupt(1) Reset state. Thus, the ADC module is 4. Wait the required acquisition time(2). turned off and any pending conversion is 5. Start conversion by setting the GO/DONE bit. terminated. 6. Wait for ADC conversion to complete by one of 9.2.4 ADC OPERATION DURING SLEEP the following: • Polling the GO/DONE bit The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC • Waiting for the ADC interrupt (interrupts option. When the FRC clock source is selected, the enabled) ADC waits one additional instruction before starting the 7. Read ADC Result conversion. This allows the SLEEP instruction to be 8. Clear the ADC interrupt flag (required if interrupt executed, which can reduce system noise during the is enabled). conversion. If the ADC interrupt is enabled, the device Note1: The global interrupt may be disabled if the will wake-up from Sleep when the conversion user is attempting to wake-up from Sleep completes. If the ADC interrupt is disabled, the ADC and resume in-line code execution. module is turned off after the conversion completes, although the ADON bit remains set. 2: See Section9.3 “A/D Acquisition Requirements”. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. DS41288F-page 76 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 EXAMPLE 9-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B’01110000’ ;ADC Frc clock MOVWF ADCON1 ; BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B’10000001’ ;Right justify, MOVWF ADCON0 ;Vdd Vref, AN0, On CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space © 2009 Microchip Technology Inc. DS41288F-page 77

PIC16F610/616/16HV610/616 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = Channel 00 (AN0) 0001 = Channel 01 (AN1) 0010 = Channel 02 (AN2) 0011 = Channel 03 (AN3) 0100 = Channel 04 (AN4) 0101 = Channel 05 (AN5) 0110 = Channel 06 (AN6) 0111 = Channel 07 (AN7) 1000 = Reserved – do not use 1001 = Reserved – do not use 1010 = Reserved – do not use 1011 = Reserved – do not use 1100 = CVREF 1101 = 0.6V Fixed Voltage Reference(1) 1110 = 1.2V Fixed Voltage Reference(1) 1111 = Reserved – do not use bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: When the CHS<3:0> bits change to select the 1.2V or 0.6V Fixed Voltage Reference, the reference output voltage will have a transient. If the Comparator module uses this VP6 reference voltage, the comparator output may momentarily change state due to the transient. DS41288F-page 78 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCS2 ADCS1 ADCS0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS41288F-page 79

PIC16F610/616/16HV610/616 REGISTER 9-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY) R-x R-x R-x R-x R-x R-x R-x R-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 9-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY) R-x R-x U-0 U-0 U-0 U-0 U-0 U-0 ADRES1 ADRES0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 9-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 (READ-ONLY) U-0 U-0 U-0 U-0 U-0 U-0 R-x R-x — — — — — — ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result REGISTER 9-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 (READ-ONLY) R-x R-x R-x R-x R-x R-x R-x R-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result DS41288F-page 80 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure9-4. The maximum recommended impedance for analog sources is 10 kΩ. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation9-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. EQUATION 9-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10kΩ 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 5µs+TC+[(Temperature - 25°C)(0.05µs/°C)] The value for TC can be approximated with the following equations: ⎛ 1 ⎞ VAPPLIED⎝1– 2---0---4---7---⎠ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb –TC ⎛ ----------⎞ VAPPLIED⎜1–eRC⎟ = VCHOLD ;[2] VCHOLD charge response to VAPPLIED ⎝ ⎠ –Tc ⎛ -R----C----⎞ ⎛ 1 ⎞ VAPPLIED⎜1–e ⎟ = VAPPLIED⎝1– 2---0---4---7---⎠ ;combining [1] and [2] ⎝ ⎠ Solving for TC: TC = –CHOLD(RIC+RSS+RS) ln(1/2047) = –10pF(1kΩ+7kΩ+10kΩ) ln(0.0004885) = 1.37µs Therefore: TACQ = 5µs+1.37µs+[(50°C- 25°C)(0.05µs/°C)] = 7.67µs Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10kΩ. This is required to meet the pin leakage specification. © 2009 Microchip Technology Inc. DS41288F-page 81

PIC16F610/616/16HV610/616 FIGURE 9-4: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC ≤ 1k SS Rss VA C5 PpIFN VT = 0.6V I± L5E0A0K AnGAE CHOLD = 10 pF VSS/VREF- 6V 5V RSS Legend: CPIN = Input Capacitance VDD4V VT = Threshold Voltage 3V 2V I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance 5 6 7 891011 SS = Sampling Switch Sampling Switch CHOLD = Sample/Hold Capacitance (kΩ) FIGURE 9-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh de 3FCh 1 LSB ideal o C 3FBh ut p ut Full-Scale O C 004h Transition D A 003h 002h 001h 000h Analog Input Voltage 1 LSB ideal VSS/VREF- Zero-Scale VDD/VREF+ Transition DS41288F-page 82 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets ADCON0(1) ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 ADCON1(1) — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ---- ANSEL ANS ANS6 ANS5 ANS4 ANS3(1) ANS2(1) ANS1 ANS0 1111 1111 1111 1111 ADRESH(1,2) A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL(1,2) A/D Result Register Low Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 --u0 u000 PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx --uu 00uu TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Note 1: PIC16F616/16HV616 only. 2: Read-only Register. © 2009 Microchip Technology Inc. DS41288F-page 83

PIC16F610/616/16HV610/616 NOTES: DS41288F-page 84 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 10.0 ENHANCED CAPTURE/ event when a predetermined amount of time has COMPARE/PWM (WITH AUTO- expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. SHUTDOWN AND DEAD BAND) Table10-1 shows the timer resources required by the MODULE ECCP module. (PIC16F616/16HV616 ONLY) TABLE 10-1: ECCP MODE – TIMER The Enhanced Capture/Compare/PWM module is a RESOURCES REQUIRED peripheral which allows the user to time and control different events. In Capture mode, the peripheral ECCP Mode Timer Resource allows the timing of the duration of an event. The Capture Timer1 Compare mode allows the user to trigger an external Compare Timer1 PWM Timer2 REGISTER 10-1: CCP1CON: ENHANCED CCP1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 P1M<1:0>: PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-Bridge output; P1A, P1B modulated with dead-time control; P1C, P1D assigned as port pins 11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: ECCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D conversion, if the ADC module is enabled) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2009 Microchip Technology Inc. DS41288F-page 85

PIC16F610/616/16HV610/616 10.1 Capture Mode 10.1.2 TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode or Synchronized 16-bit value of the TMR1 register when an event occurs Counter mode for the CCP module to use the capture on pin CCP1. An event is defined as one of the feature. In Asynchronous Counter mode, the capture following and is configured by the CCP1M<3:0> bits of operation may not work. the CCP1CON register: 10.1.3 SOFTWARE INTERRUPT • Every falling edge When the Capture mode is changed, a false capture • Every rising edge interrupt may be generated. The user should keep the • Every 4th rising edge CCP1IE interrupt enable bit of the PIE1 register clear to • Every 16th rising edge avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag following any change in operating mode. must be cleared in software. If another capture occurs 10.1.4 CCP PRESCALER before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new There are four prescaler settings specified by the captured value (see Figure10-1). CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP 10.1.1 CCP1 PIN CONFIGURATION module is not in Capture mode, the prescaler counter In Capture mode, the CCP1 pin should be configured is cleared. Any Reset will clear the prescaler counter. as an input by setting the associated TRIS control bit. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To Note: If the CCP1 pin is configured as an output, avoid this unexpected operation, turn the module off by a write to the port can cause a capture clearing the CCP1CON register before changing the condition. prescaler (see Example10-1). FIGURE 10-1: CAPTURE MODE EXAMPLE 10-1: CHANGING BETWEEN OPERATION BLOCK CAPTURE PRESCALERS DIAGRAM BANKSELCCP1CON ;Set Bank bits to point Set Flag bit CCP1IF ;to CCP1CON (PIR1 register) Prescaler CLRF CCP1CON ;Turn CCP module off ÷ 1, 4, 16 MOVLW NEW_CAPT_PS;Load the W reg with CCP1 CCPR1H CCPR1L ; the new prescaler pin ; move value and CCP ON and Capture MOVWF CCP1CON ;Load CCP1CON with this Edge Detect Enable ; value TMR1H TMR1L CCP1CON<3:0> System Clock (FOSC) DS41288F-page 86 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets CCP1CON(1) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CCPR1L(1) Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H(1) Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 0000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 0000 0-00 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. DS41288F-page 87

PIC16F610/616/16HV610/616 10.2 Compare Mode 10.2.2 TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is In Compare mode, Timer1 must be running in either constantly compared against the TMR1 register pair Timer mode or Synchronized Counter mode. The value. When a match occurs, the CCP1 module may: compare operation may not work in Asynchronous Counter mode. • Toggle the CCP1 output • Set the CCP1 output 10.2.3 SOFTWARE INTERRUPT MODE • Clear the CCP1 output When Generate Software Interrupt mode is chosen • Generate a Special Event Trigger (CCP1M<3:0>=1010), the CCP1 module does not • Generate a Software Interrupt assert control of the CCP1 pin (see the CCP1CON register). The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. 10.2.4 SPECIAL EVENT TRIGGER All Compare modes can generate an interrupt. When Special Event Trigger mode is chosen (CCP1M<3:0>=1011), the CCP1 module does the FIGURE 10-2: COMPARE MODE following: OPERATION BLOCK • Resets Timer1 DIAGRAM • Starts an ADC conversion if ADC is enabled CCP1CON<3:0> Mode Select The CCP1 module does not assert control of the CCP1 pin in this mode (see the CCP1CON register). Set CCP1IF Interrupt Flag The Special Event Trigger output of the CCP occurs (PIR1) CCP1 4 immediately upon a match between the TMR1H, Pin CCPR1H CCPR1L TMR1L register pair and the CCPR1H, CCPR1L Q S register pair. The TMR1H, TMR1L register pair is not Output Comparator R Logic Match reset until the next rising edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to TMR1H TMR1L TRIS effectively provide a 16-bit programmable period Output Enable register for Timer1. Special Event Trigger Note1: The Special Event Trigger from the CCP Special Event Trigger will: module does not set interrupt flag bit • Clear TMR1H and TMR1L registers. TMR1IF of the PIR1 register. • NOT set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by • Set the GO/DONE bit to start the ADC conversion. changing the contents of the CCPR1H and CCPR1L register pair, between the 10.2.1 CCP1 PIN CONFIGURATION clock edge that generates the Special Event Trigger and the clock edge that The user must configure the CCP1 pin as an output by generates the Timer1 Reset, will preclude clearing the associated TRIS bit. the Reset from occurring. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch. DS41288F-page 88 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets CCP1CON(1) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CCPR1L(1) Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H(1) Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 0000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 0000 0-00 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. DS41288F-page 89

PIC16F610/616/16HV610/616 10.3 PWM Mode The PWM output (Figure10-4) has a time base (period) and a time that the output stays high (duty The PWM mode generates a Pulse-Width Modulated cycle). signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: FIGURE 10-4: CCP PWM OUTPUT • PR2 • T2CON Period • CCPR1L Pulse Width • CCP1CON TMR2 = PR2 In Pulse-Width Modulation (PWM) mode, the CCP TMR2 = CCPR1L:CCP1CON<5:4> module produces up to a 10-bit resolution PWM output TMR2 = 0 on the CCP1 pin. Since the CCP1 pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will relinquish CCP1 control of the CCP1 pin. Figure10-3 shows a simplified block diagram of PWM operation. Figure10-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section10.3.7 “Setup for PWM Operation”. FIGURE 10-3: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty Cycle Registers CCPR1L CCPR1H(2) (Slave) CCP1 Comparator R Q S TMR2 (1) TRIS Comparator Clear Timer2, toggle CCP1 pin and latch duty cycle PR2 Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. 2: In PWM mode, CCPR1H is a read-only register. DS41288F-page 90 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 10.3.1 PWM PERIOD EQUATION 10-2: PULSE WIDTH The PWM period is specified by writing to the PR2 register of Timer2. The PWM period can be calculated Pulse Width = (CCPR1L:CCP1CON<5:4>) • using the formula of Equation10-1. TOSC • (TMR2 Prescale Value) EQUATION 10-1: PWM PERIOD EQUATION 10-3: DUTY CYCLE RATIO PWM Period = [(PR2)+1]•4•TOSC• (TMR2 Prescale Value) (CCPR1L:CCP1CON<5:4>) Duty Cycle Ratio = ----------------------------------------------------------------------- 4(PR2+1) When TMR2 is equal to PR2, the following three events occur on the next increment cycle: The CCPR1H register and a 2-bit internal latch are • TMR2 is cleared used to double buffer the PWM duty cycle. This double • The CCP1 pin is set. (Exception: If the PWM duty buffering is essential for glitchless PWM operation. cycle=0%, the pin will not be set.) The 8-bit timer TMR2 register is concatenated with • The PWM duty cycle is latched from CCPR1L into either the 2-bit internal system clock (FOSC), or 2 bits of CCPR1H. the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. Note: The Timer2 postscaler (see Section7.1 When the 10-bit time base matches the CCPR1H and “Timer2 Operation”) is not used in the 2-bit latch, then the CCP1 pin is cleared (see determination of the PWM frequency. Figure10-3). 10.3.2 PWM DUTY CYCLE 10.3.3 PWM RESOLUTION The PWM duty cycle is specified by writing a 10-bit The resolution determines the number of available duty value to multiple registers: CCPR1L register and cycles for a given period. For example, a 10-bit resolution CCP1<1:0> bits of the CCP1CON register. The will result in 1024 discrete duty cycles, whereas an 8-bit CCPR1L contains the eight MSbs and the CCP1<1:0> resolution will result in 256 discrete duty cycles. bits of the CCP1CON register contain the two LSbs. The maximum PWM resolution is 10 bits when PR2 is CCPR1L and CCP1<1:0> bits of the CCP1CON 255. The resolution is a function of the PR2 register register can be written to at any time. The duty cycle value as shown by Equation10-4. value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H EQUATION 10-4: PWM RESOLUTION register is read-only. Equation10-2 is used to calculate the PWM pulse Resolution = l--o---g----[--4----(--P----R----2-----+-----1----)--]- bits width. log(2) Equation10-3 is used to calculate the PWM duty cycle ratio. Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. TABLE 10-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 10-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 © 2009 Microchip Technology Inc. DS41288F-page 91

PIC16F610/616/16HV610/616 10.3.4 OPERATION IN SLEEP MODE 10.3.7 SETUP FOR PWM OPERATION In Sleep mode, the TMR2register will not increment The following steps should be taken when configuring and the state of the module will not change. If the CCP1 the CCP module for PWM operation: pin is driving a value, it will continue to drive that value. 1. Configure the PWM pin (CCP1) as an input by When the device wakes up, TMR2 will continue from its setting the associated TRIS bit. previous state. 2. Set the PWM period by loading the PR2 register. 10.3.5 CHANGES IN SYSTEM CLOCK 3. Configure the CCP module for the PWM mode FREQUENCY by loading the CCP1CON register with the appropriate values. The PWM frequency is derived from the system clock 4. Set the PWM duty cycle by loading the CCPR1L frequency. Any changes in the system clock frequency register and CCP1 bits of the CCP1CON register. will result in changes to the PWM frequency. See Section3.0 “Oscillator Module” for additional 5. Configure and start Timer2: details. • Clear the TMR2IF interrupt flag bit of the PIR1 register. 10.3.6 EFFECTS OF RESET • Set the Timer2 prescale value by loading the Any Reset will force all ports to Input mode and the T2CKPS bits of the T2CON register. CCP registers to their Reset states. • Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCP1 pin output by clearing the associated TRIS bit. DS41288F-page 92 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 10.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the The Enhanced PWM Mode can generate a PWM signal PWM pins is configurable and is selected by setting the on up to four different output pins with up to 10-bits of CCP1M bits in the CCP1CON register appropriately. resolution. It can do this through four different PWM Table10-6 shows the pin assignments for each Output modes: Enhanced PWM mode. • Single PWM Figure10-5 shows an example of a simplified block • Half-Bridge PWM diagram of the Enhanced PWM module. • Full-Bridge PWM, Forward mode Note: To prevent the generation of an • Full-Bridge PWM, Reverse mode incomplete waveform when the PWM is To select an Enhanced PWM mode, the P1M bits of the first enabled, the ECCP module waits until CCP1CON register must be set appropriately. the start of a new PWM period before generating a PWM signal. FIGURE 10-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE CCP1<1:0> P1M<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L CCP1/P1A CCP1/P1A TRISC<5> CCPR1H (Slave) P1B P1B Output TRISC<4> Comparator R Q Controller P1C P1C TMR2 (1) S TRISC<3> P1D P1D Comparator Clear Timer2, TRISC<2> toggle PWM pin and latch duty cycle PR2 PWM1CON Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. Note1: The TRIS register value for each PWM output must be configured appropriately. 2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins. 3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions TABLE 10-6: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode P1M CCP1/P1A P1B P1C P1D Single 00 Yes No No No Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes © 2009 Microchip Technology Inc. DS41288F-page 93

PIC16F610/616/16HV610/616 FIGURE 10-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse PR2+1 P1M<1:0> Signal 0 Width Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section10.4.6 “Programmable Dead-Band Delay mode”). DS41288F-page 94 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 10-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) P1M<1:0> Signal 0 Pulse PR2+1 Width Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section10.4.6 “Programmable Dead-Band Delay mode”). © 2009 Microchip Technology Inc. DS41288F-page 95

PIC16F610/616/16HV610/616 10.4.1 HALF-BRIDGE MODE Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must In Half-Bridge mode, two pins are used as outputs to be cleared to configure P1A and P1B as outputs. drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM FIGURE 10-8: EXAMPLE OF HALF- output signal is output on the P1B pin (see Figure10-8). BRIDGE PWM OUTPUT This mode can be used for half-bridge applications, as shown in Figure10-9, or for full-bridge applications, Period Period where four power switches are being modulated with two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay P1A(2) can be used to prevent shoot-through current in half- td bridge power devices. The value of the PDC<6:0> bits of td the PWM1CON register sets the number of instruction P1B(2) cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output (1) (1) (1) remains inactive during the entire cycle. See 10.4.6 “Programmable Dead-Band Delay mode” for more td = Dead-Band Delay details of the dead-band delay operations. Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FIGURE 10-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A - Load FET Driver + P1B - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver P1A Load FET FET Driver Driver P1B DS41288F-page 96 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 10.4.2 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must In Full-Bridge mode, all four pins are used as outputs. be cleared to configure the P1A, P1B, P1C and P1D An example of full-bridge application is shown in pins as outputs. Figure10-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure10- 11. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure10-11. FIGURE 10-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D © 2009 Microchip Technology Inc. DS41288F-page 97

PIC16F610/616/16HV610/616 FIGURE 10-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS41288F-page 98 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 10.4.2.1 Direction Change in Full-Bridge The Full-Bridge mode does not provide dead-band Mode delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation In the Full-Bridge mode, the P1M1 bit in the CCP1CON where dead-band delay is required. This situation register allows users to control the forward/reverse occurs when both of the following conditions are true: direction. When the application firmware changes this direction control bit, the module will change to the new 1. The direction of the PWM output changes when direction on the next PWM cycle. the duty cycle of the output is at or near 100%. 2. The turn off time of the power switch, including A direction change is initiated in software by changing the power device and driver circuit, is greater the P1M1 bit of the CCP1CON register. The following than the turn on time. sequence occurs four Timer2 cycles prior to the end of the current PWM period: Figure10-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty • The modulated outputs (P1B and P1D) are placed cycle. In this example, at time t1, the output P1A and in their inactive state. P1D become inactive, while output P1C becomes • The associated unmodulated outputs (P1A and active. Since the turn off time of the power devices is P1C) are switched to drive in the opposite longer than the turn on time, a shoot-through current direction. will flow through power devices QC and QD (see • PWM modulation resumes at the beginning of the Figure10-10) for the duration of ‘t’. The same next period. phenomenon will occur to power devices QA and QB See Figure10-12 for an illustration of this sequence. for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 10-12: EXAMPLE OF PWM DIRECTION CHANGE Signal Period(1) Period P1A (Active-High) P1B (Active-High) Pulse Width P1C (Active-High) (2) P1D (Active-High) Pulse Width Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer2 counts. © 2009 Microchip Technology Inc. DS41288F-page 99

PIC16F610/616/16HV610/616 FIGURE 10-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B DC P1C P1D PW TON External Switch C TOFF External Switch D Potential T = TOFF – TON Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver. DS41288F-page 100 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 10.4.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high- impedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). The CCP1M<1:0> bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. © 2009 Microchip Technology Inc. DS41288F-page 101

PIC16F610/616/16HV610/616 10.4.4 ENHANCED PWM AUTO- A shutdown condition is indicated by the ECCPASE SHUTDOWN MODE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating The PWM mode supports an Auto-Shutdown mode that normally. If the bit is a ‘1’, the PWM outputs are in the will disable the PWM outputs when an external shutdown state. shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This When a shutdown event occurs, two things happen: mode is used to help prevent the PWM from damaging The ECCPASE bit is set to ‘1’. The ECCPASE will the application. remain set until cleared in firmware or an auto-restart The auto-shutdown sources are selected using the occurs (see Section10.4.5 “Auto-Restart Mode”). ECCPASx bits of the ECCPAS register. A shutdown The enabled PWM pins are asynchronously placed in event may be generated by: their shutdown states. The PWM output pins are • A logic ‘0’ on the INT pin grouped into pairs [P1A/P1C] and [P1B/P1D]. The state of each pin pair is determined by the PSSAC and • Comparator C1 PSSBD bits of the ECCPAS register. Each pin pair may • Comparator C2 be placed into one of three states: • Setting the ECCPASE bit in firmware • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) REGISTER 10-2: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits 000 =Auto-Shutdown is disabled 001 =Comparator C1 output high 010 =Comparator C2 output high(1) 011 =Either Comparators output is high 100 =VIL on INT pin 101 =VIL on INT pin or Comparator C1 output high 110 =VIL on INT pin or Comparator C2 output high 111 =VIL on INT pin or either Comparators output is high bit 3-2 PSSACn: Pins P1A and P1C Shutdown State Control bits 00 = Drive pins P1A and P1C to ‘0’ 01 = Drive pins P1A and P1C to ‘1’ 1x = Pins P1A and P1C tri-state bit 1-0 PSSBDn: Pins P1B and P1D Shutdown State Control bits 00 = Drive pins P1B and P1D to ‘0’ 01 = Drive pins P1B and P1D to ‘1’ 1x = Pins P1B and P1D tri-state DS41288F-page 102 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 Note1: The auto-shutdown condition is a level- based signal, not an edge-based signal. As long as the level is present, the auto- shutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period. FIGURE 10-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0) PWM Period ShutdownEvent ECCPASE bit PWM Activity Normal PWM ECCPASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes 10.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automati- cally restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register. If auto-restart is enabled, the ECCPASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPASE bit will be cleared via hardware and normal operation will resume. FIGURE 10-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) PWM Period ShutdownEvent ECCPASE bit PWM Activity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes © 2009 Microchip Technology Inc. DS41288F-page 103

PIC16F610/616/16HV610/616 10.4.6 PROGRAMMABLE DEAD-BAND FIGURE 10-16: EXAMPLE OF HALF- DELAY MODE BRIDGE PWM OUTPUT In half-bridge applications where all power switches are Period Period modulated at the PWM frequency, the power switches Pulse Width normally require more time to turn off than to turn on. If both the upper and lower power switches are switched P1A(2) at the same time (one turned on, and the other turned td off), both switches may be on for a short period of time td until one switch completely turns off. During this brief P1B(2) interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge (1) (1) (1) supply. To avoid this potentially destructive shoot- through current from flowing during switching, turning td = Dead-Band Delay on either of the power switches is normally delayed to allow the other switch to completely turn off. Note 1: At this time, the TMR2 register is equal to the PR2 register. In Half-Bridge mode, a digitally programmable dead- band delay is available to avoid shoot-through current 2: Output signals are shown as active-high. from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure10-16 for illustration. The lower seven bits of the associated PWM1CON register (Register10-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 10-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A V - Load FET Driver + P1B V - V- DS41288F-page 104 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 REGISTER 10-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits PDCn = Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active TABLE 10-7: SUMMARY OF REGISTERS ASSOCIATED WITH PWM Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets CCP1CON(1) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CCPR1L(1) Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCPR1H(1) Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 CM2CON1 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 00-0 0010 ECCPAS(1) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000 INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 0000 0-00 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 0000 0-00 PWM1CON(1) PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 0000 0000 T2CON(1) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 TMR2(1) Timer2 Module Register 0000 0000 0000 0000 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. DS41288F-page 105

PIC16F610/616/16HV610/616 NOTES: DS41288F-page 106 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 11.0 VOLTAGE REGULATOR An external current limiting resistor, RSER, located between the unregulated supply, VUNREG, and the VDD The PIC16HV610/16HV616 include a permanent pin, drops the difference in voltage between VUNREG internal 5 volt (nominal) shunt regulator in parallel with and VDD. RSER must be between RMAX and RMIN as the VDD pin. This eliminates the need for an external defined by Equation11-1. voltage regulator in systems sourced by an unregulated supply. All external devices connected EQUATION 11-1: RSER LIMITING RESISTOR directly to the VDD pin will share the regulated supply voltage and contribute to the total VDD supply current (ILOAD). RMAX = (VUMIN - 5V) 1.05 • (4MA + ILOAD) 11.1 Regulator Operation A shunt regulator generates a specific supply voltage RMIN = (VUMAX - 5V) by creating a voltage drop across a pass resistor RSER. 0.95 • (50MA) The voltage at the VDD pin of the microcontroller is monitored and compared to an internal voltage refer- Where: ence. The current through the resistor is then adjusted, RMAX = maximum value of RSER (ohms) based on the result of the comparison, to produce a voltage drop equal to the difference between the supply RMIN = minimum value of RSER (ohms) voltage VUNREG and the VDD of the microcontroller. VUMIN = minimum value of VUNREG See Figure11-1 for voltage regulator schematic. VUMAX= maximum value of VUNREG FIGURE 11-1: VOLTAGE REGULATOR VDD = regulated voltage (5V nominal) ILOAD = maximum expected load current in mA VUNREG including I/O pin currents and external circuits connected to VDD. ILOAD ISUPPLY RSER 1.05 = compensation for +5% tolerance of RSER VDD 0.95 = compensation for -5% tolerance of RSER CBYPASS ISHUNT Feedback 11.2 Regulator Considerations VSS The supply voltage VUNREG and load current are not constant. Therefore, the current range of the regulator is limited. Selecting a value for RSER must take these three factors into consideration. Since the regulator uses the band gap voltage as the regulated voltage reference, this voltage reference is permanently enabled in the PIC16HV610/16HV616 devices. © 2009 Microchip Technology Inc. DS41288F-page 107

PIC16F610/616/16HV610/616 NOTES: DS41288F-page 108 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 12.0 SPECIAL FEATURES OF THE 12.1 Configuration Bits CPU The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various The PIC16F610/616/16HV610/616 has a host of device configurations as shown in Register12-1. features intended to maximize system reliability, These bits are mapped in program memory location minimize cost through elimination of external 2007h. components, provide power-saving features and offer code protection. Note: Address 2007h is beyond the user program These features are: memory space. It belongs to the special • Reset configuration memory space (2000h- - Power-on Reset (POR) 3FFFh), which can be accessed only during - Power-up Timer (PWRT) programming. See the Memory Program- ming Specification (DS41284) for more - Oscillator Start-up Timer (OST) information. - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Oscillator selection • Sleep • Code protection • ID Locations • In-Circuit Serial Programming™ The PIC16F610/616/16HV610/616 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power- up Timer to provide at least a 64ms Reset. With these three functions-on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through: • External Reset • Watchdog Timer Wake-up • An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register12-1). © 2009 Microchip Technology Inc. DS41288F-page 109

PIC16F610/616/16HV610/616 REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER — — — — — — BOREN1(1) BOREN0(1) bit 15 bit 8 IOSCFS CP(2) MCLRE(3) PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘1’ bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 0x = BOR disabled bit 7 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8MHz 0 = 4MHz bit 6 CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 5 MCLRE: MCLR Pin Function Select bit(3) 1 = MCLR pin function is MCLR 0 = MCLR pin function is digital input, MCLR internally tied to VDD bit 4 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 110 = RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire program memory will be erased when the code protection is turned off. 3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. DS41288F-page 110 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 12.2 Calibration Bits • Power-on Reset • MCLR Reset The 8MHz internal oscillator is factory calibrated. • MCLR Reset during Sleep These calibration values are stored in fuses located in the Calibration Word (2008h). The Calibration Word is • WDT Reset not erased when using the specified bulk erase • Brown-out Reset (BOR) sequence in the Memory Programming Specification WDT wake-up does not cause register resets in the (DS41284) and thus, does not require reprogramming. same manner as a WDT Reset since wake-up is viewed as the resumption of normal operation. TO and 12.3 Reset PD bits are set or cleared differently in different Reset situations, as indicated in Table12-2. Software can use The PIC16F610/616/16HV610/616 differentiates these bits to determine the nature of the Reset. See between various kinds of Reset: Table12-4 for a full description of Reset states of all a) Power-on Reset (POR) registers. b) WDT Reset during normal operation A simplified block diagram of the On-Chip Reset Circuit c) WDT Reset during Sleep is shown in Figure12-1. d) MCLR Reset during normal operation The MCLR Reset path has a noise filter to detect and e) MCLR Reset during Sleep ignore small pulses. See Section15.0 “Electrical f) Brown-out Reset (BOR) Specifications” for pulse-width specifications. Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on: FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/VPP pin Sleep WDT WDT Module Time-out Reset POR Detect Power-on Reset VDD Brown-out(1) Reset BOREN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1/ CLKI pin PWRT On-Chip 11-bit Ripple Counter RC OSC Enable PWRT Enable OST Note 1: Refer to the Configuration Word register (Register12-1). © 2009 Microchip Technology Inc. DS41288F-page 111

PIC16F610/616/16HV610/616 12.3.1 POWER-ON RESET (POR) FIGURE 12-2: RECOMMENDED MCLR CIRCUIT The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper VDD operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This PIC® MCU will eliminate external RC components usually needed R1 to create Power-on Reset. A maximum rise time for 1kΩ (or greater) VDD is required. See Section15.0 “Electrical Specifications” for details. If the BOR is enabled, the R2 maximum rise time specification does not apply. The MCLR BOR circuitry will keep the device in Reset until VDD 100 Ω SW1 (needed with capacitor) reaches VBOR (see Section12.3.4 “Brown-out Reset (optional) (BOR)”). C1 Note: The POR circuit does not produce an 0.1 μF (optional, not critical) internal Reset when VDD declines. To re- enable the POR, VDD must reach Vss for a minimum of 100μs. When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., 12.3.3 POWER-UP TIMER (PWRT) voltage, frequency, temperature, etc.) must be met to The Power-up Timer provides a fixed 64ms (nominal) ensure proper operation. If these conditions are not time-out on power-up only, from POR or Brown-out met, the device must be held in Reset until the Reset. The Power-up Timer operates from an internal operating conditions are met. RC oscillator. For more information, see Section3.4 For additional information, refer to Application Note “Internal Clock Modes”. The chip is kept in Reset as AN607, “Power-up Trouble Shooting” (DS00607). long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, 12.3.2 MCLR PWRTE, can disable (if set) or enable (if cleared or PIC16F610/616/16HV610/616 has a noise filter in the programmed) the Power-up Timer. The Power-up MCLR Reset path. The filter will detect and ignore Timer should be enabled when Brown-out Reset is small pulses. enabled, although it is not required. It should be noted that a WDT Reset does not drive The Power-up Timer delay will vary from chip-to-chip MCLR pin low. due to: Voltages applied to the MCLR pin that exceed its • VDD variation specification can result in both MCLR Resets and • Temperature variation excessive current beyond the device specification • Process variation during the ESD event. For this reason, Microchip See DC parameters for details (Section15.0 recommends that the MCLR pin no longer be tied “Electrical Specifications”). directly to VDD. The use of an RC network, as shown in Figure12-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, MCLRE = 0, the Reset signal to the chip is generated may cause latch-up. Thus, a series resis- internally. When the MCLRE = 1, the RA3/MCLR pin becomes an external Reset input. In this mode, the tor of 50-100 Ω should be used when applying a “low” level to the MCLR pin, RA3/MCLR pin has a weak pull-up to VDD. rather than pulling this pin directly to VSS. DS41288F-page 112 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 12.3.4 BROWN-OUT RESET (BOR) On any Reset (Power-on, Brown-out Reset, Watchdog timer, etc.), the chip will remain in Reset until VDD rises The BOREN0 and BOREN1 bits in the Configuration above VBOR (see Figure12-3). If enabled, the Power- Word register select one of three BOR modes. up Timer will be invoked by the Reset and keep the chip Selecting BOREN<1:0> = 10, the BOR is automatically in Reset an additional 64ms. disabled in Sleep to conserve power and enabled on wake-up. See Register12-1 for the Configuration Word Note: The Power-up Timer is enabled by the definition. PWRTE bit in the Configuration Word A brown-out occurs when VDD falls below VBOR for register. greater than parameter TBOR (see Section15.0 If VDD drops below VBOR while the Power-up Timer is “Electrical Specifications”). The brown-out condition running, the chip will go back into a Brown-out Reset will reset the device. This will occur regardless of VDD and the Power-up Timer will be re-initialized. Once VDD slew rate. A Brown-out Reset may not occur if VDD falls rises above VBOR, the Power-up Timer will execute a below VBOR for less than parameter TBOR. 64ms Reset. FIGURE 12-3: BROWN-OUT SITUATIONS VDD VBOR Internal Reset 64 ms(1) VDD VBOR Internal < 64 ms Reset 64 ms(1) VDD VBOR Internal Reset 64 ms(1) Note 1: 64ms delay only if PWRTE bit is programmed to ‘0’. © 2009 Microchip Technology Inc. DS41288F-page 113

PIC16F610/616/16HV610/616 12.3.5 TIME-OUT SEQUENCE 12.3.6 POWER CONTROL (PCON) REGISTER On power-up, the time-out sequence is as follows: • PWRT time-out is invoked after POR has expired. The Power Control register PCON (address 8Eh) has two Status bits to indicate what type of Reset occurred • OST is activated after the PWRT time-out has last. expired. Bit0 is BOR (Brown-out). BOR is unknown on Power- The total time-out will vary based on oscillator on Reset. It must then be set by the user and checked configuration and PWRTE bit status. For example, in EC on subsequent Resets to see if BOR = 0, indicating that mode with PWRTE bit erased (PWRT disabled), there a Brown-out has occurred. The BOR Status bit is a will be no time-out at all. Figure12-4, Figure12-5 and “don’t care” and is not necessarily predictable if the Figure12-6 depict time-out sequences. brown-out circuit is disabled (BOREN<1:0> = 00 in the Since the time-outs occur from the POR pulse, if MCLR Configuration Word register). is kept low long enough, the time-outs will expire. Then, Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on bringing MCLR high will begin execution immediately Reset and unaffected otherwise. The user must write a (see Figure12-5). This is useful for testing purposes or ‘1’ to this bit following a Power-on Reset. On a subse- to synchronize more than one PIC16F610/616/ quent Reset, if POR is ‘0’, it will indicate that a Power- 16HV610/616 device operating in parallel. on Reset has occurred (i.e., VDD may have gone too Table12-5 shows the Reset conditions for some low). special registers, while Table12-4 shows the Reset For more information, see Section12.3.4 “Brown-out conditions for all the registers. Reset (BOR)”. TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS Power-up Brown-out Reset Wake-up from Oscillator Configuration Sleep PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 XT, HS, LP TPWRT + 1024 • 1024 • TOSC TPWRT + 1024 • 1024 • TOSC 1024 • TOSC TOSC TOSC RC, EC, INTOSC TPWRT — TPWRT — — TABLE 12-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 x 1 1 Power-on Reset u 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets(1) PCON — — — — — — POR BOR ---- --qq ---- --uu STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS41288F-page 114 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset © 2009 Microchip Technology Inc. DS41288F-page 115

PIC16F610/616/16HV610/616 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS Wake-up from Sleep through MCLR Reset Power-on Interrupt Register Address WDT Reset Reset Wake-up from Sleep through Brown-out Reset(1) WDT Time-out W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu PORTA 05h --x0 x000 --u0 u000 --uu uuuu PORTC 07h --xx xx00 --uu 00uu --uu uuuu PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh/8Bh 0000 0000 0000 0000 uuuu uuuu(2) PIR1 0Ch -000 0-00 -000 0-00 -uuu u-uu(2) TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu TMR2(6) 11h 0000 0000 0000 0000 uuuu uuuu T2CON(6) 12h -000 0000 -000 0000 -uuu uuuu CCPR1L(6) 13h xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H(6) 14h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON(6) 15h 0000 0000 0000 0000 uuuu uuuu PWM1CON(6) 16h 0000 0000 0000 0000 uuuu uuuu ECCPAS(6) 17h 0000 0000 0000 0000 uuuu uuuu VRCON 19h 0000 0000 0000 0000 uuuu uuuu CM1CON0 1Ah 0000 -000 0000 -000 uuuu -uuu CM2CON0 1Bh 0000 -000 0000 -000 uuuu -uuu CM2CON1 1Ch 00-0 0000 00-0 0000 uu-u uuuu ADRESH(6) 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0(6) 1Fh 0000 0000 0000 0000 uuuu uuuu OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu TRISA 85h --11 1111 --11 1111 --uu uuuu TRISC 87h --11 1111 --11 1111 --uu uuuu PIE1 8Ch -000 0-00 -000 0-00 -uuu u-uu PCON 8Eh ---- --0x ---- --uu(1, 5) ---- --uu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table12-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. 6: PIC16F616/16HV616 only. 7: ANSEL <3:2> For PIC16F616/HV616 only. DS41288F-page 116 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Wake-up from Sleep through MCLR Reset Power-on Interrupt Register Address WDT Reset (Continued) Reset Wake-up from Sleep through Brown-out Reset(1) WDT Time-out (Continued) OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu ANSEL(7) 91h 1111 1111 1111 1111 uuuu uuuu PR2(6) 92h 1111 1111 1111 1111 1111 1111 WPUA 95h --11 -111 --11 -111 --uu -uuu IOCA 96h --00 0000 --00 0000 --uu uuuu SRCON0 99h 0000 00-0 0000 00-0 uuuu uu-u SRCON1 9Ah 00-- ---- 00-- ---- uu-- ---- ADRESL(6) 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON1(6) 9Fh -000 ---- -000 ---- -uuu ---- Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table12-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. 6: PIC16F616/16HV616 only. 7: ANSEL <3:2> For PIC16F616/HV616 only. TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Status PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 uuuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --10 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. © 2009 Microchip Technology Inc. DS41288F-page 117

PIC16F610/616/16HV610/616 12.4 Interrupts For external interrupt events, such as the INT pin or PORTA change interrupt, the interrupt latency will be The PIC16F610/616/16HV610/616 has multiple three or four instruction cycles. The exact latency sources of interrupt: depends upon when the interrupt event occurs (see • External Interrupt RA2/INT Figure12-8). The latency is the same for one or two- • Timer0 Overflow Interrupt cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be • PORTA Change Interrupts determined by polling the interrupt flag bits. The • 2 Comparator Interrupts interrupt flag bit(s) must be cleared in software before • A/D Interrupt (PIC16F616/16HV616 only) re-enabling interrupts to avoid multiple interrupt • Timer1 Overflow Interrupt requests. • Timer2 Match Interrupt (PIC16F616/16HV616 only) Note1: Individual interrupt flag bits are set, • Enhanced CCP Interrupt (PIC16F616/16HV616 regardless of the status of their only) corresponding mask bit or the GIE bit. The Interrupt Control register (INTCON) and Peripheral 2: When an instruction that clears the GIE Interrupt Request Register 1 (PIR1) record individual bit is executed, any interrupts that were interrupt requests in flag bits. The INTCON register pending for execution in the next cycle also has individual and global interrupt enable bits. are ignored. The interrupts, which were The Global Interrupt Enable bit, GIE of the INTCON ignored, are still pending to be serviced register, enables (if set) all unmasked interrupts, or when the GIE bit is set again. disables (if cleared) all interrupts. Individual interrupts For additional information on Timer1, Timer2, can be disabled through their corresponding enable comparators, ADC, Enhanced CCP modules, refer to bits in the INTCON register and PIE1 register. GIE is the respective peripheral section. cleared on Reset. 12.4.1 RA2/INT INTERRUPT When an interrupt is serviced, the following actions occur automatically: The external interrupt on the RA2/INT pin is edge- • The GIE is cleared to disable any further interrupt. triggered; either on the rising edge if the INTEDG bit of the OPTION register is set, or the falling edge, if the • The return address is pushed onto the stack. INTEDG bit is clear. When a valid edge appears on the • The PC is loaded with 0004h. RA2/INT pin, the INTF bit of the INTCON register is set. The Return from Interrupt instruction, RETFIE, exits This interrupt can be disabled by clearing the INTE the interrupt routine, as well as sets the GIE bit, which control bit of the INTCON register. The INTF bit must re-enables unmasked interrupts. be cleared by software in the Interrupt Service Routine before re-enabling this interrupt. The RA2/INT interrupt The following interrupt flags are contained in the INT- can wake-up the processor from Sleep, if the INTE bit CON register: was set prior to going into Sleep. See Section12.7 • INT Pin Interrupt “Power-Down Mode (Sleep)” for details on Sleep and • PORTA Change Interrupt Figure12-9 for timing of wake-up from Sleep through • Timer0 Overflow Interrupt RA2/INT interrupt. The peripheral interrupt flags are contained in the Note: The ANSEL register must be initialized to special register, PIR1. The corresponding interrupt configure an analog channel as a digital enable bit is contained in special register, PIE1. input. Pins configured as analog inputs will The following interrupt flags are contained in the PIR1 read ‘0’ and cannot generate an interrupt. register: • A/D Interrupt • 2 Comparator Interrupts • Timer1 Overflow Interrupt • Timer2 Match Interrupt • Enhanced CCP Interrupt DS41288F-page 118 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 12.4.2 TIMER0 INTERRUPT 12.4.3 PORTA INTERRUPT-ON-CHANGE An overflow (FFh → 00h) in the TMR0 register will set An input change on PORTA sets the RAIF bit of the the T0IF bit of the INTCON register. The interrupt can INTCON register. The interrupt can be enabled/ be enabled/disabled by setting/clearing T0IE bit of the disabled by setting/clearing the RAIE bit of the INTCON INTCON register. See Section5.0 “Timer0 Module” register. Plus, individual pins can be configured through for operation of the Timer0 module. the IOCA register. Note: If a change on the I/O pin should occur when any PORTA operation is being executed, then the RAIF interrupt flag may not get set. FIGURE 12-7: INTERRUPT LOGIC IOC-RA0 IOCA0 IOC-RA1 IOCA1 IOC-RA2 IOCA2 IOC-RA3 IOCA3 IOC-RA4 IOCA4 IOC-RA5 IOCA5 T0IF T0IE Wake-up (If in Sleep mode)(1) TMR2IF(2) TMR2IE(2) INTF INTE Interrupt to CPU TMR1IF RAIF TMR1IE RAIE C1IF PEIE C1IE C2IF GIE C2IE ADIF(2) ADIE(2) CCP1IF(2) CCP1IE(2) Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section12.7.1 “Wake-up from Sleep”. 2: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. DS41288F-page 119

PIC16F610/616/16HV610/616 FIGURE 12-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) (4) INT pin (1) (1) (2) INTF flag (5) Interrupt Latency (INTCON reg.) GIE bit (INTCON reg.) INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section15.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 PIR1 — ADIF(1) CCP1IF(1) C2IF C1IF — TMR2IF(1) TMR1IF -000 0-00 -000 0-00 PIE1 — ADIE(1) CCP1IE(1) C2IE C1IE — TMR2IE(1) TMR1IE -000 0-00 -000 0-00 Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the interrupt module. Note 1: PIC16F616/16HV616 only. DS41288F-page 120 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 12.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR (see Figure2-4). These 16 locations are common to all banks and do not require banking. This makes context save and restore operations simpler. The code shown in Example12-1 can be used to: • Store the W register • Store the STATUS register • Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register Note: The PIC16F610/616/16HV610/616 does not require saving the PCLATH. However, if computed GOTO’s are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR. EXAMPLE 12-1: SAVING STATUS AND W REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W ;Swaps are used because they do not affect the status bits MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W © 2009 Microchip Technology Inc. DS41288F-page 121

PIC16F610/616/16HV610/616 12.6 Watchdog Timer (WDT) 12.6.1 WDT PERIOD The Watchdog Timer is a free running, on-chip RC The WDT has a nominal time-out period of 18 ms (with oscillator, which requires no external components. This no prescaler). The time-out periods vary with RC oscillator is separate from the external RC oscillator temperature, VDD and process variations from part to of the CLKIN pin and INTOSC. That means that the part (see Table15-4, Parameter 31). If longer time-out WDT will run, even if the clock on the OSC1 and OSC2 periods are desired, a prescaler with a division ratio of pins of the device has been stopped (for example, by up to 1:128 can be assigned to the WDT under execution of a SLEEP instruction). During normal oper- software control by writing to the OPTION register. ation, a WDT Time-out generates a device Reset. If the Thus, time-out periods up to 2.3 seconds can be device is in Sleep mode, a WDT Time-out causes the realized. device to wake-up and continue with normal operation. The CLRWDT and SLEEP instructions clear the WDT The WDT can be permanently disabled by program- and the prescaler, if assigned to the WDT, and prevent ming the Configuration bit, WDTE, as clear it from timing out and generating a device Reset. (Section12.1 “Configuration Bits”). The TO bit in the STATUS register will be cleared upon a Watchdog Timer Time-out. 12.6.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worst- case conditions (i.e., VDD = Min., Temperature = Max., Max. WDT prescaler) it may take several seconds before a WDT Time-out occurs. FIGURE 12-2: WATCHDOG TIMER BLOCK DIAGRAM CLKOUT (= FOSC/4) Data Bus 0 8 1 SYNC 2 1 TMR0 Cycles T0CKI 0 pin 0 T0SE T0CS 8-bit Set Flag bit T0IF on Overflow Prescaler PSA 1 8 PSA 3 PS<2:0> 1 WDT Time-Out Watchdog 0 Timer PSA WDTE Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. TABLE 12-7: WDT STATUS Conditions WDT WDTE = 0 CLRWDT Command Cleared Exit Sleep + System Clock = EXTRC, INTRC, EC Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST DS41288F-page 122 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 CONFIG(1) IOSCFS CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register12-1 for operation of all Configuration Word register bits. © 2009 Microchip Technology Inc. DS41288F-page 123

PIC16F610/616/16HV610/616 12.7 Power-Down Mode (Sleep) When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to The Power-Down mode is entered by executing a wake-up through an interrupt event, the corresponding SLEEP instruction. interrupt enable bit must be set (enabled). Wake-up is If the Watchdog Timer is enabled: regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the • WDT will be cleared but keeps running. instruction after the SLEEP instruction. If the GIE bit is • PD bit in the STATUS register is cleared. set (enabled), the device executes the instruction after • TO bit is set. the SLEEP instruction, then branches to the interrupt • Oscillator driver is turned off. address (0004h). In cases where the execution of the • I/O ports maintain the status they had before SLEEP instruction following SLEEP is not desirable, the user was executed (driving high, low or high-impedance). should have a NOP after the SLEEP instruction. For lowest current consumption in this mode, all I/O pins Note: If the global interrupts are disabled (GIE is should be either at VDD or VSS, with no external circuitry cleared) and any interrupt source has both drawing current from the I/O pin and the comparators its interrupt enable bit and the correspond- and CVREF should be disabled. I/O pins that are high- ing interrupt flag bits set, the device will impedance inputs should be pulled high or low externally immediately wake-up from Sleep. to avoid switching currents caused by floating inputs. The WDT is cleared when the device wakes up from The T0CKI input should also be at VDD or VSS for lowest Sleep, regardless of the source of wake-up. current consumption. The contribution from on-chip pull- ups on PORTA should be considered. 12.7.2 WAKE-UP USING INTERRUPTS The MCLR pin must be at a logic high level. When global interrupts are disabled (GIE cleared) and Note: It should be noted that a Reset generated any interrupt source has both its interrupt enable bit by a WDT time-out does not drive MCLR and interrupt flag bit set, one of the following will occur: pin low. • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will 12.7.1 WAKE-UP FROM SLEEP complete as a NOP. Therefore, the WDT and WDT The device can wake-up from Sleep through one of the prescaler and postscaler (if enabled) will not be following events: cleared, the TO bit will not be set and the PD bit will not be cleared. 1. External Reset input on MCLR pin. • If the interrupt occurs during or after the 2. Watchdog Timer wake-up (if WDT was execution of a SLEEP instruction, the device will enabled). Immediately wake-up from Sleep. The SLEEP 3. Interrupt from RA2/INT pin, PORTA change or a instruction is executed. Therefore, the WDT and peripheral interrupt. WDT prescaler and postscaler (if enabled) will be The first event will cause a device Reset. The two latter cleared, the TO bit will be set and the PD bit will events are considered a continuation of program be cleared. execution. The TO and PD bits in the STATUS register Even if the flag bits were checked before executing a can be used to determine the cause of device Reset. SLEEP instruction, it may be possible for flag bits to The PD bit, which is set on power-up, is cleared when become set before the SLEEP instruction completes. Sleep is invoked. TO bit is cleared if WDT wake-up To determine whether a SLEEP instruction executed, occurred. test the PD bit. If the PD bit is set, the SLEEP instruction The following peripheral interrupts can wake the device was executed as a NOP. from Sleep: To ensure that the WDT is cleared, a CLRWDT instruction 1. Timer1 interrupt. Timer1 must be operating as should be executed before a SLEEP instruction. See an asynchronous counter. Figure12-9 for more details. 2. ECCP Capture mode interrupt. 3. A/D conversion (when A/D clock source is RC). 4. Comparator output changes state. 5. Interrupt-on-change. 6. External Interrupt from INT pin. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. DS41288F-page 124 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 12-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF flag (INTCON reg.) Interrupt Latency(3) GIE bit Processor in (INTCON reg.) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC – 1) Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC, INTOSC and RC Oscillator modes. 3: GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line. 4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference. 12.8 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP™ for verification purposes. Note: The entire Flash program memory will be erased when the code protection is turned off. See the Memory Programming Specification (DS41284) for more information. 12.9 ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. © 2009 Microchip Technology Inc. DS41288F-page 125

PIC16F610/616/16HV610/616 12.10 In-Circuit Serial Programming™ The PIC16F610/616/16HV610/616 microcontrollers Note: To erase the device VDD must be above can be serially programmed while in the end the Bulk Erase VDD minimum given in the application circuit. This is simply done with five Memory Programming Specification connections for: (DS41284) • clock 12.11 In-Circuit Debugger • data • power Since in-circuit debugging requires access to three pins, • ground MPLAB® ICD 2 development with an 14-pin device is not practical. A special 28-pin PIC16F610/616/ • programming voltage 16HV610/616 ICD device is used with MPLAB ICD 2 to This allows customers to manufacture boards with provide separate clock, data and MCLR pins and frees unprogrammed devices and then program the all normally available pins to the user. microcontroller just before shipping the product. This A special debugging adapter allows the ICD device to also allows the most recent firmware or a custom be used in place of a PIC16F610/616/16HV610/616 firmware to be programmed. device. The debugging adapter is the only source of the The device is placed into a Program/Verify mode by ICD device. holding the RA0 and RA1 pins low, while raising the When the ICD pin on the PIC16F610/616/16HV610/ MCLR (VPP) pin from VIL to VIHH. See the Memory 616 ICD device is held low, the In-Circuit Debugger Programming Specification (DS41284) for more functionality is enabled. This function allows simple information. RA0 becomes the programming data and debugging functions when used with MPLAB ICD 2. RA1 becomes the programming clock. Both RA0 and When the microcontroller has this feature enabled, RA1 are Schmitt Trigger inputs in Program/Verify some of the resources are not available for general mode. use. Table12-9 shows which features are consumed A typical In-Circuit Serial Programming connection is by the background debugger. shown in Figure12-10. TABLE 12-9: DEBUGGER RESOURCES FIGURE 12-10: TYPICAL IN-CIRCUIT SERIAL Resource Description PROGRAMMING™ I/O pins ICDCLK, ICDDATA CONNECTION Stack 1 level To Normal Program Memory Address 0h must be NOP Connections 700h-7FFh External CSiognnnaelsctor * PIC12F615/12HV615 For more information, see “MPLAB® ICD 2 In-Circuit PIC12F609/12HV609 Debugger User’s Guide” (DS51331), available on +5V VDD Microchip’s web site (www.microchip.com). 0V VSS VPP MCLR/VPP/GP3/RA3 CLK GP1 Data I/O GP0 * * * To Normal Connections * Isolation devices (as required) DS41288F-page 126 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 12-11: 28 PIN ICD PINOUT 28-Pin PDIP In-Circuit Debug Device VDD 1 28 GND CS0 2 27 RA0 CS1 3 26 RA1 CS2 4 25 SHUNTEN RA5 5 D 24 RA2 C RA4 6 -I 23 RC0 6 RA3 7 1 22 RC1 6 RC5 8 F 21 RC2 6 RC4 9 1 20 NC C RC3 10 PI 19 NC NC 11 18 NC ICDCLK 12 17 NC ICDMCLR 13 16 NC ICDDATA 14 15 ICD © 2009 Microchip Technology Inc. DS41288F-page 127

PIC16F610/616/16HV610/616 NOTES: DS41288F-page 128 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 13.0 INSTRUCTION SET SUMMARY TABLE 13-1: OPCODE FIELD DESCRIPTIONS The PIC16F610/616/16HV610/616 instruction set is highly orthogonal and is comprised of three basic Field Description categories: f Register file address (0x00 to 0x7F) • Byte-oriented operations W Working register (accumulator) • Bit-oriented operations b Bit address within an 8-bit file register • Literal and control operations k Literal field, constant data or label Each PIC16 instruction is a 14-bit word divided into an x Don’t care location (= 0 or 1). opcode, which specifies the instruction type and one or The assembler will generate code with x = 0. more operands, which further specify the operation of It is the recommended form of use for the instruction. The formats for each of the categories compatibility with all Microchip software tools. is presented in Figure13-1, while the various opcode d Destination select; d = 0: store result in W, fields are summarized in Table13-1. d = 1: store result in file register f. Table13-2 lists the instructions recognized by the Default is d = 1. MPASMTM assembler. PC Program Counter For byte-oriented instructions, ‘f’ represents a file TO Time-out bit register designator and ‘d’ represents a destination C Carry bit designator. The file register designator specifies which file register is to be used by the instruction. DC Digit carry bit The destination designator specifies where the result of Z Zero bit the operation is to be placed. If ‘d’ is zero, the result is PD Power-down bit placed in the W register. If ‘d’ is one, the result is placed in the file register specified in the instruction. FIGURE 13-1: GENERAL FORMAT FOR For bit-oriented instructions, ‘b’ represents a bit field INSTRUCTIONS designator, which selects the bit affected by the operation, while ‘f’ represents the address of the file in Byte-oriented file register operations which the bit is located. 13 8 7 6 0 OPCODE d f (FILE #) For literal and control operations, ‘k’ represents an 8-bit or 11-bit constant, or literal value. d = 0 for destination W d = 1 for destination f One instruction cycle consists of four oscillator periods; f = 7-bit file register address for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1μs. All instructions are Bit-oriented file register operations executed within a single instruction cycle, unless a 13 10 9 7 6 0 conditional test is true, or the program counter is OPCODE b (BIT #) f (FILE #) changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the b = 3-bit address second cycle executed as a NOP. f = 7-bit file register address All instruction examples use the format ‘0xhh’ to Literal and control operations represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. General 13 8 7 0 13.1 Read-Modify-Write Operations OPCODE k (literal) Any instruction that specifies a file register as part of k = 8-bit immediate value the instruction performs a Read-Modify-Write (RMW) operation. The register is read, the data is modified, CALL and GOTO instructions only and the result is stored according to either the instruc- 13 11 10 0 tion or the destination designator ‘d’. A read operation OPCODE k (literal) is performed on a register even if the instruction writes to that register. k = 11-bit immediate value For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unin- tended consequence of clearing the condition that set the RAIF flag. © 2009 Microchip Technology Inc. DS41288F-page 129

PIC16F610/616/16HV610/616 TABLE 13-2: PIC16F610/616/16HV610/616 INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP – No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call Subroutine 2 10 0kkk kkkk kkkk CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE – Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS41288F-page 130 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 13.2 Instruction Descriptions ADDLW Add literal and W BCF Bit Clear f Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 Operation: (W) + k → (W) Operation: 0 → (f<b>) Status Affected: C, DC, Z Status Affected: None Description: The contents of the W register are added to the eight-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared. and the result is placed in the W register. ADDWF Add W and f BSF Bit Set f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + (f) → (destination) Operation: 1 → (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set. with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSC f,b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 Operation: (W) .AND. (k) → (W) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: The contents of W register are AND’ed with the eight-bit literal Description: If bit ‘b’ in register ‘f’ is ‘1’, the next ‘k’. The result is placed in the W instruction is executed. register. If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction. ANDWF AND W with f Syntax: [ label ] ANDWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .AND. (f) → (destination) Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2009 Microchip Technology Inc. DS41288F-page 131

PIC16F610/616/16HV610/616 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 127 Operands: None 0 ≤ b < 7 Operation: 00h → WDT Operation: skip if (f<b>) = 1 0 → WDT prescaler, 1 → TO Status Affected: None 1 → PD Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Status Affected: TO, PD instruction is executed. If bit ‘b’ is ‘1’, then the next Description: CLRWDT instruction resets the instruction is discarded and a NOP Watchdog Timer. It also resets the is executed instead, making this a prescaler of the WDT. two-cycle instruction. Status bits TO and PD are set. CALL Call Subroutine COMF Complement f Syntax: [ label ] CALL k Syntax: [ label ] COMF f,d Operands: 0 ≤ k ≤ 2047 Operands: 0 ≤ f ≤ 127 Operation: (PC)+ 1→ TOS, d ∈ [0,1] k → PC<10:0>, Operation: (f) → (destination) (PCLATH<4:3>) → PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are Description: Call Subroutine. First, return complemented. If ‘d’ is ‘0’, the address (PC + 1) is pushed onto result is stored in W. If ‘d’ is ‘1’, the stack. The eleven-bit the result is stored back in immediate address is loaded into register ‘f’. PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: 00h → (f) 1 → Z Operation: (f) - 1 → (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Decrement register ‘f’. If ‘d’ is ‘0’, cleared and the Z bit is set. the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h → (W) 1 → Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS41288F-page 132 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f) - 1 → (destination); Operation: (f) + 1 → (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. If the result is ‘1’, the next If the result is ‘1’, the next instruction is executed. If the instruction is executed. If the result is ‘0’, then a NOP is result is ‘0’, a NOP is executed executed instead, making it a instead, making it a two-cycle two-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0 ≤ k ≤ 2047 Operands: 0 ≤ k ≤ 255 Operation: k → PC<10:0> Operation: (W) .OR. k → (W) PCLATH<4:3> → PC<12:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the eight-bit literal ‘k’. The eleven-bit immediate value is The result is placed in the loaded into PC bits <10:0>. The W register. upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f) + 1 → (destination) Operation: (W) .OR. (f) → (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Inclusive OR the W register with incremented. If ‘d’ is ‘0’, the result register ‘f’. If ‘d’ is ‘0’, the result is is placed in the W register. If ‘d’ is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. © 2009 Microchip Technology Inc. DS41288F-page 133

PIC16F610/616/16HV610/616 MOVF Move f MOVWF Move W to f Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) → (f) Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: Move data from W register to Description: The contents of register ‘f’ is register ‘f’. moved to a destination dependent Words: 1 upon the status of ‘d’. If d = 0, Cycles: 1 destination is W register. If d = 1, the destination is file register ‘f’ Example: MOVW OPTION itself. d = 1 is useful to test a file F register since status flag Z is Before Instruction affected. OPTION= 0xFF Words: 1 W = 0x4F After Instruction Cycles: 1 OPTION= 0x4F Example: MOVF FSR, 0 W = 0x4F After Instruction W = value in FSR register Z = 1 MOVLW Move literal to W NOP No Operation Syntax: [ label ] MOVLW k Syntax: [ label ] NOP Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W) Operation: No operation Status Affected: None Status Affected: None Description: The eight-bit literal ‘k’ is loaded into Description: No operation. W register. The “don’t cares” will Words: 1 assemble as ‘0’s. Cycles: 1 Words: 1 Example: NOP Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A DS41288F-page 134 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, Operation: k → (W); 1 → GIE TOS → PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is Description: The W register is loaded with the POPed and Top-of-Stack (TOS) is eight-bit literal ‘k’. The program loaded in the PC. Interrupts are counter is loaded from the top of enabled by setting Global the stack (the return address). Interrupt Enable bit, GIE This is a two-cycle instruction. (INTCON<7>). This is a two-cycle Words: 1 instruction. Cycles: 2 Words: 1 Example: CALL TABLE;W contains Cycles: 2 ;table offset Example: RETFIE ;value GOTO DONE After Interrupt TABLE • PC = TOS • GIE= 1 ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ;End of table DONE Before Instruction W = 0x07 After Instruction W = value of k8 RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS → PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. © 2009 Microchip Technology Inc. DS41288F-page 135

PIC16F610/616/16HV610/616 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 Operands: None d ∈ [0,1] Operation: 00h → WDT, Operation: See description below 0 → WDT prescaler, 1 → TO, Status Affected: C 0 → PD Description: The contents of register ‘f’ are Status Affected: TO, PD rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is result is placed in the W register. cleared. Time-out Status bit, TO If ‘d’ is ‘1’, the result is stored is set. Watchdog Timer and its back in register ‘f’. prescaler are cleared. The processor is put into Sleep C Register f mode with the oscillator stopped. Words: 1 Cycles: 1 Example: RLF REG1,0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 1100 1100 C = 1 RRF Rotate Right f through Carry SUBLW Subtract W from literal Syntax: [ label ] RRF f,d Syntax: [ label ] SUBLW k Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: k - (W) → (W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s Description: The contents of register ‘f’ are complement method) from the rotated one bit to the right through eight-bit literal ‘k’. The result is the Carry flag. If ‘d’ is ‘0’, the placed in the W register. result is placed in the W register. If ‘d’ is ‘1’, the result is placed Result Condition back in register ‘f’. C = 0 W > k C Register f C = 1 W ≤ k DC = 0 W<3:0> > k<3:0> DC = 1 W<3:0> ≤ k<3:0> DS41288F-page 136 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 SUBWF Subtract W from f XORWF Exclusive OR W with f Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f) - (W) → (destination) Operation: (W) .XOR. (F.) → (destination) Status Affected: C, DC, Z Status Affected: Z Description: Subtract (2’s complement method) Description: Exclusive OR the contents of the W register from register ‘f’. If ‘d’ is W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. stored back in register ‘f’. C = 0 W > f C = 1 W ≤ f DC = 0 W<3:0> > f<3:0> DC = 1 W<3:0> ≤ f<3:0> SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2009 Microchip Technology Inc. DS41288F-page 137

PIC16F610/616/16HV610/616 NOTES: DS41288F-page 138 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 14.0 DEVELOPMENT SUPPORT 14.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2009 Microchip Technology Inc. DS41288F-page 139

PIC16F610/616/16HV610/616 14.2 MPLAB C Compilers for Various 14.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 14.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 14.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 14.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS41288F-page 140 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 14.7 MPLAB SIM Software Simulator 14.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 14.10 PICkit 3 In-Circuit Debugger/ Programmer and 14.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers signifi- cant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a rugge- dized probe interface and long (up to three meters) inter- connection cables. © 2009 Microchip Technology Inc. DS41288F-page 141

PIC16F610/616/16HV610/616 14.11 PICkit 2 Development 14.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 14.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS41288F-page 142 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 15.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ...............................................................................................-0.3V to +13.5V Voltage on all other pins with respect to VSS ...........................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)...............................................................................................................................800 mW Maximum current out of VSS pin...................................................................................................................... 95 mA Maximum current into VDD pin......................................................................................................................... 95 mA Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................................................................± 20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD).........................................................................................................± 20 mA Maximum output current sunk by any I/O pin....................................................................................................25 mA Maximum output current sourced by any I/O pin..............................................................................................25 mA Maximum current sunk by PORTA and PORTC (combined)........................................................................... 90 mA Maximum current sourced PORTA and PORTC (combined)........................................................................... 90 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS41288F-page 143

PIC16F610/616/16HV610/616 FIGURE 15-1: PIC16F610/616 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 4.5 V) 4.0 ( D D V 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: PIC16HV610/616 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.0 4.5 V) 4.0 (D D V 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note1: The shaded region indicates the permissible combinations of voltage and frequency. DS41288F-page 144 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 15-3: PIC16F610/616 FREQUENCY TOLERANCE GRAPH, -40°C ≤ TA ≤ +125°C 125 ± 5% 85 C) ± 2% ° 60 ( e r u t a r e p 25 ± 1% m e T 0 -40 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-4: PIC16HV610/616 FREQUENCY TOLERANCE GRAPH, -40°C ≤ TA ≤ +125°C 125 ± 5% 85 C) ± 2% ° 60 ( e r u at r e p 25 ± 1% m e T 0 -40 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (V) © 2009 Microchip Technology Inc. DS41288F-page 145

PIC16F610/616/16HV610/616 15.1 DC Characteristics: PIC16F610/616/16HV610/616-I (Industrial) PIC16F610/616/16HV610/616-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. VDD Supply Voltage D001 PIC16F610/616 2.0 — 5.5 V FOSC < = 4 MHz D001 PIC16HV610/616 2.0 — —(2) V FOSC < = 4 MHz D001B PIC16F610/616 2.0 — 5.5 V FOSC < = 8 MHz D001B PIC16HV610/616 2.0 — —(2) V FOSC < = 8 MHz D001C PIC16F610/616 3.0 — 5.5 V FOSC < = 10 MHz D001C PIC16HV610/616 3.0 — —(2) V FOSC < = 10 MHz D001D PIC16F610/616 4.5 — 5.5 V FOSC < = 20 MHz D001D PIC16HV610/616 4.5 — —(2) V FOSC < = 20 MHz D002* VDR RAM Data Retention 1.5 — — V Device in Sleep mode Voltage(1) D003 VPOR VDD Start Voltage to — VSS — V See Section12.3.1 “Power-on Reset ensure internal Power-on (POR)” for details. Reset signal D004* SVDD VDD Rise Rate to ensure 0.05 — — V/ms See Section12.3.1 “Power-on Reset internal Power-on Reset (POR)” for details. signal * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: User defined. Voltage across the shunt regulator should not exceed 5V. DS41288F-page 146 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 15.2 DC Characteristics: PIC16F610/616-I (Industrial) PIC16F610/616-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D010 Supply Current (IDD)(1, 2) — 13 25 μA 2.0 FOSC = 32kHz PIC16F610/616 — 19 29 μA 3.0 LP Oscillator mode — 32 51 μA 5.0 D011* — 135 225 μA 2.0 FOSC = 1MHz XT Oscillator mode — 185 285 μA 3.0 — 300 405 μA 5.0 D012 — 240 360 μA 2.0 FOSC = 4MHz — 360 505 μA 3.0 XT Oscillator mode — 0.66 1.0 mA 5.0 D013* — 75 110 μA 2.0 FOSC = 1MHz — 155 255 μA 3.0 EC Oscillator mode — 345 530 μA 5.0 D014 — 185 255 μA 2.0 FOSC = 4MHz — 325 475 μA 3.0 EC Oscillator mode — 0.665 1.0 mA 5.0 D016* — 245 340 μA 2.0 FOSC = 4MHz — 360 485 μA 3.0 INTOSC mode — 0.620 0.845 mA 5.0 D017 — 395 550 μA 2.0 FOSC = 8MHz — 0.620 0.850 mA 3.0 INTOSC mode — 1.2 1.6 mA 5.0 D018 — 175 235 μA 2.0 FOSC = 4MHz — 285 390 μA 3.0 EXTRC mode(3) — 530 750 μA 5.0 D019 — 2.2 3.1 mA 4.5 FOSC = 20MHz — 2.8 3.35 mA 5.0 HS Oscillator mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ. © 2009 Microchip Technology Inc. DS41288F-page 147

PIC16F610/616/16HV610/616 15.3 DC Characteristics: PIC16HV610/616-I (Industrial) PIC16HV610/616-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D010 Supply Current (IDD)(1, 2) — 160 230 μA 2.0 FOSC = 32kHz PIC16HV610/616 — 240 310 μA 3.0 LP Oscillator mode — 280 400 μA 4.5 D011* — 270 380 μA 2.0 FOSC = 1MHz XT Oscillator mode — 400 560 μA 3.0 — 520 780 μA 4.5 D012 — 380 540 μA 2.0 FOSC = 4MHz — 575 810 μA 3.0 XT Oscillator mode — 0.875 1.3 mA 4.5 D013* — 215 310 μA 2.0 FOSC = 1MHz — 375 565 μA 3.0 EC Oscillator mode — 570 870 μA 4.5 D014 — 330 475 μA 2.0 FOSC = 4MHz — 550 800 μA 3.0 EC Oscillator mode — 0.85 1.2 mA 4.5 D016* — 310 435 μA 2.0 FOSC = 4MHz — 500 700 μA 3.0 INTOSC mode — 0.74 1.1 mA 4.5 D017 — 460 650 μA 2.0 FOSC = 8MHz — 0.75 1.1 mA 3.0 INTOSC mode — 1.2 1.6 mA 4.5 D018 — 320 465 μA 2.0 FOSC = 4MHz — 510 750 μA 3.0 EXTRC mode(3) — 0.770 1.0 mA 4.5 D019 — 2.5 3.4 mA 4.5 FOSC = 20MHz HS Oscillator mode * These parameters are characterized but not tested. † Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ. DS41288F-page 148 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 15.4 DC Characteristics: PIC16F610/616- I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D020 Power-down Base — 0.05 0.9 μA 2.0 WDT, BOR, Comparators, VREF and Current(IPD)(2) T1OSC disabled — 0.15 1.2 μA 3.0 PIC16F610/616 — 0.35 1.5 μA 5.0 — 150 500 nA 3.0 -40°C ≤ TA ≤ +25°C for industrial D021 — 0.5 1.5 μA 2.0 WDT Current(1) — 2.5 4.0 μA 3.0 — 9.5 17 μA 5.0 D022 — 5.0 9 μA 3.0 BOR Current(1) — 6.0 12 μA 5.0 D023 — 105 115 μA 2.0 Comparator Current(1), both — 110 125 μA 3.0 comparators enabled — 116 140 μA 5.0 D024 — 50 60 μA 2.0 Comparator Current(1), single — 55 65 μA 3.0 comparator enabled — 60 75 μA 5.0 D025 — 30 40 μA 2.0 CVREF Current(1) (high range) — 45 60 μA 3.0 — 75 105 μA 5.0 D026* — 39 50 μA 2.0 CVREF Current(1) (low range) — 59 80 μA 3.0 — 98 130 μA 5.0 D027 — 5.5 10 μA 2.0 T1OSC Current(1), 32.768kHz — 7.0 12 μA 3.0 — 8.5 14 μA 5.0 D028 — 0.2 1.6 μA 3.0 A/D Current(1), no conversion in — 0.36 1.9 μA 5.0 progress. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. © 2009 Microchip Technology Inc. DS41288F-page 149

PIC16F610/616/16HV610/616 15.5 DC Characteristics: PIC16F610/616-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D020E Power-down Base — 0.05 4.0 μA 2.0 WDT, BOR, Comparators, VREF and Current (IPD)(2) — 0.15 5.0 μA 3.0 T1OSC disabled PIC16F610/616 — 0.35 8.5 μA 5.0 D021E — 0.5 5.0 μA 2.0 WDT Current(1) — 2.5 8.0 μA 3.0 — 9.5 19 μA 5.0 D022E — 5.0 15 μA 3.0 BOR Current(1) — 6.0 19 μA 5.0 D023E — 105 130 μA 2.0 Comparator Current(1), both — 110 140 μA 3.0 comparators enabled — 116 150 μA 5.0 D024E — 50 70 μA 2.0 Comparator Current(1), single — 55 75 μA 3.0 comparator enabled — 60 80 μA 5.0 D025E — 30 40 μA 2.0 CVREF Current(1) (high range) — 45 60 μA 3.0 — 75 105 μA 5.0 D026E* — 39 50 μA 2.0 CVREF Current(1) (low range) — 59 80 μA 3.0 — 98 130 μA 5.0 D027E — 5.5 16 μA 2.0 T1OSC Current(1), 32.768kHz — 7.0 18 μA 3.0 — 8.5 22 μA 5.0 D028E — 0.2 6.5 μA 3.0 A/D Current(1), no conversion in — 0.36 10 μA 5.0 progress * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. DS41288F-page 150 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 15.6 DC Characteristics: PIC16HV610/616- I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D020 Power-down Base — 135 200 μA 2.0 WDT, BOR, Comparators, VREF and Current(IPD)(2,3) T1OSC disabled — 210 280 μA 3.0 PIC16HV610/616 — 260 350 μA 4.5 D021 — 135 200 μA 2.0 WDT Current(1) — 210 285 μA 3.0 — 265 360 μA 4.5 D022 — 215 285 μA 3.0 BOR Current(1) — 265 360 μA 4.5 D023 — 240 340 μA 2.0 Comparator Current(1), both — 320 420 μA 3.0 comparators enabled — 370 500 μA 4.5 D024 — 185 270 μA 2.0 Comparator Current(1), single — 265 350 μA 3.0 comparator enabled — 320 430 μA 4.5 D025 — 165 235 μA 2.0 CVREF Current(1) (high range) — 255 330 μA 3.0 — 330 430 μA 4.5 D026* — 175 245 μA 2.0 CVREF Current(1) (low range) — 275 350 μA 3.0 — 355 450 μA 4.5 D027 — 140 205 μA 2.0 T1OSC Current(1), 32.768kHz — 220 290 μA 3.0 — 270 360 μA 4.5 D028 — 210 280 μA 3.0 A/D Current(1), no conversion in — 260 350 μA 4.5 progress * These parameters are characterized but not tested. † Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: Shunt regulator is always enabled and always draws operating current. © 2009 Microchip Technology Inc. DS41288F-page 151

PIC16F610/616/16HV610/616 15.7 DC Characteristics: PIC16HV610/616-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D020E Power-down Base — 135 200 μA 2.0 WDT, BOR, Comparators, VREF and Current (IPD)(2, 3) — 210 280 μA 3.0 T1OSC disabled PIC16HV610/616 — 260 350 μA 4.5 D021E — 135 200 μA 2.0 WDT Current(1) — 210 285 μA 3.0 — 265 360 μA 4.5 D022E — 215 285 μA 3.0 BOR Current(1) — 265 360 μA 4.5 D023E — 240 360 μA 2.0 Comparator Current(1), both — 320 440 μA 3.0 comparators enabled — 370 500 μA 4.5 D024E — 185 280 μA 2.0 Comparator Current(1), single — 265 360 μA 3.0 comparator enabled — 320 430 μA 4.5 D025E — 165 235 μA 2.0 CVREF Current(1) (high range) — 255 330 μA 3.0 — 330 430 μA 4.5 D026E* — 175 245 μA 2.0 CVREF Current(1) (low range) — 275 350 μA 3.0 — 355 450 μA 4.5 D027E — 140 205 μA 2.0 T1OSC Current(1), 32.768kHz — 220 290 μA 3.0 — 270 360 μA 4.5 D028E — 210 280 μA 3.0 A/D Current(1), no conversion in — 260 350 μA 4.5 progress * These parameters are characterized but not tested. † Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: Shunt regulator is always enabled and always draws operating current. DS41288F-page 152 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 15.8 DC Characteristics: PIC16F610/616/16HV610/616- I (Industrial) PIC16F610/616/16HV610/616 - E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O port: D030 with TTL buffer Vss — 0.8 V 4.5V ≤ VDD ≤ 5.5V D030A Vss — 0.15 VDD V 2.0V ≤ VDD ≤ 4.5V D031 with Schmitt Trigger buffer Vss — 0.2 VDD V 2.0V ≤ VDD ≤ 5.5V D032 MCLR, OSC1 (RC mode) VSS — 0.2 VDD V D033 OSC1 (XT and LP modes) VSS — 0.3 V D033A OSC1 (HS mode) VSS — 0.3 VDD V VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V 4.5V ≤ VDD ≤ 5.5V D040A 0.25 VDD + 0.8 — VDD V 2.0V ≤ VDD ≤ 4.5V D041 with Schmitt Trigger buffer 0.8 VDD — VDD V 2.0V ≤ VDD ≤ 5.5V D042 MCLR 0.8 VDD — VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V D043A OSC1 (HS mode) 0.7 VDD — VDD V D043B OSC1 (RC mode) 0.9 VDD — VDD V (Note 1) IIL Input Leakage Current(2,3) D060 I/O ports — ± 0.1 ± 1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 RA3/MCLR(3,4) — ± 0.7 ± 5 μA VSS ≤ VPIN ≤ VDD D063 OSC1 — ± 0.1 ± 5 μA VSS ≤ VPIN ≤ VDD, XT, HS and LP oscillator configuration D070* IPUR PORTA Weak Pull-up Current(5) 50 250 400 μA VDD = 5.0V, VPIN = VSS VOL Output Low Voltage — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C VOH Output High Voltage VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C D090 I/O ports(2) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: This specification applies to RA3/MCLR configured as RA3 input with internal pull-up disabled. 5: This specification applies to all weak pull-up pins, including the weak pull-up on RA3/MCLR. When RA3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. © 2009 Microchip Technology Inc. DS41288F-page 153

PIC16F610/616/16HV610/616 15.9 DC Characteristics: PIC16F610/616/16HV610/616- I (Industrial) PIC16F610/616/16HV610/616 - E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Capacitive Loading Specs on D101* COSC2 Output Pins — — 15 pF In XT, HS and LP modes when OSC2 pin external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C D130A ED Cell Endurance 1K 10K — E/W +85°C ≤ TA ≤ +125°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VPEW VDD for Erase/Write 4.5 — 5.5 V D133 TPEW Erase/Write cycle time — 2 2.5 ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. DS41288F-page 154 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 15.10 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Typ Units Conditions No. TH01 θJA Thermal Resistance 70* C/W 14-pin PDIP package Junction to Ambient 85.0* C/W 14-pin SOIC package 100* C/W 14-pin TSSOP package 37* C/W 16-pin QFN 4x4mm package TH02 θJC Thermal Resistance 32.5* C/W 14-pin PDIP package Junction to Case 31.0* C/W 14-pin SOIC package 31.7* C/W 14-pin TSSOP package 2.6* C/W 16-pin QFN 4x4mm package TH03 TDIE Die Temperature 150* C TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD (NOTE 1) TH06 PI/O I/O Power Dissipation — W PI/O = Σ (IOL * VOL) + Σ (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TDIE - TA)/θJA (NOTE 2) * These parameters are characterized but not tested. Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature. © 2009 Microchip Technology Inc. DS41288F-page 155

PIC16F610/616/16HV610/616 15.11 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O Port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 15-5: LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins 15 pF for OSC2 output DS41288F-page 156 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 15.12 AC Characteristics: PIC16F610/616/16HV610/616 (Industrial, Extended) FIGURE 15-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode DC — 4 MHz XT Oscillator mode DC — 20 MHz HS Oscillator mode DC — 20 MHz EC Oscillator mode Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 20 MHz HS Oscillator mode DC — 4 MHz RC Oscillator mode OS02 TOSC External CLKIN Period(1) 27 — ∞ μs LP Oscillator mode 250 — ∞ ns XT Oscillator mode 50 — ∞ ns HS Oscillator mode 50 — ∞ ns EC Oscillator mode Oscillator Period(1) — 30.5 — μs LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC OS04* TOSH, External CLKIN High, 2 — — μs LP oscillator TOSL External CLKIN Low 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TOSR, External CLKIN Rise, 0 — ∞ ns LP oscillator TOSF External CLKIN Fall 0 — ∞ ns XT oscillator 0 — ∞ ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. © 2009 Microchip Technology Inc. DS41288F-page 157

PIC16F610/616/16HV610/616 TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Freq. Sym Characteristic Min Typ† Max Units Conditions No. Tolerance OS06 TWARM Internal Oscillator Switch — — — 2 TOSC Slowest clock when running(3) OS07 INTOSC Internal Calibrated ±1% 3.96 4.0 4.04 MHz VDD = 3.5V, TA = 25°C INTOSC Frequency(2) ±2% 3.92 4.0 4.08 MHz 2.5V ≤ VDD ≤ 5.5V, (4MHz) 0°C ≤ TA ≤ +85°C ±5% 3.80 4.0 4.2 MHz 2.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ +85°C (Ind.), -40°C ≤ TA ≤ +125°C (Ext.) OS08 INTOSC Internal Calibrated ±1% 7.92 8.0 8.08 MHz VDD = 3.5V, TA = 25°C INTOSC Frequency(2) ±2% 7.84 8.0 8.16 MHz 2.5V ≤ VDD ≤ 5.5V, (8MHz) 0°C ≤ TA ≤ +85°C ±5% 7.60 8.0 8.40 MHz 2.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ +85°C (Ind.), -40°C ≤ TA ≤ +125°C (Ext.) OS10* TIOSC ST INTOSC Oscillator Wake- — 5.5 12 24 μs VDD = 2.0V, -40°C to +85°C up from Sleep — 3.5 7 14 μs VDD = 3.0V, -40°C to +85°C Start-up Time — 3 6 11 μs VDD = 5.0V, -40°C to +85°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1μF and 0.01μF values in parallel are recommended. 3: By design. DS41288F-page 158 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 15-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19 TABLE 15-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. OS11 TOSH2CKL FOSC↑ to CLKOUT↓ (1) — — 70 ns VDD = 5.0V OS12 TOSH2CKH FOSC↑ to CLKOUT↑ (1) — — 72 ns VDD = 5.0V OS13 TCKL2IOV CLKOUT↓ to Port out valid(1) — — 20 ns OS14 TIOV2CKH Port input valid before CLKOUT↑(1) TOSC + 200 ns — — ns OS15 TOSH2IOV FOSC↑ (Q1 cycle) to Port out valid — 50 70* ns VDD = 5.0V OS16 TOSH2IOI FOSC↑ (Q2 cycle) to Port input invalid 50 — — ns VDD = 5.0V (I/O in hold time) OS17 TIOV2OSH Port input valid to FOSC↑ (Q2 cycle) 20 — — ns (I/O in setup time) OS18 TIOR Port output rise time(2) — 15 72 ns VDD = 2.0V — 40 32 VDD = 5.0V OS19 TIOF Port output fall time(2) — 28 55 ns VDD = 2.0V — 15 30 VDD = 5.0V OS20* TINP INT pin input high or low time 25 — — ns OS21* TRAP PORTA interrupt-on-change new input TCY — — ns level time * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode. © 2009 Microchip Technology Inc. DS41288F-page 159

PIC16F610/616/16HV610/616 FIGURE 15-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 15-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33* (due to BOR) * 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. DS41288F-page 160 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — μs VDD = 5V, -40°C to +85°C 5 — — μs VDD = 5V, -40°C to +125°C 31* TWDT Watchdog Timer Time-out 10 20 30 ms VDD = 5V, -40°C to +85°C Period (No Prescaler) 10 20 35 ms VDD = 5V, -40°C to +125°C 32 TOST Oscillation Start-up Timer — 1024 — TOSC (NOTE 3) Period(1, 2) 33* TPWRT Power-up Timer Period 40 65 140 ms 34* TIOZ I/O High-impedance from — — 2.0 μs MCLR Low or Watchdog Timer Reset 35* VBOR Brown-out Reset Voltage 2.0 2.15 2.3 V (NOTE 4) 36* VHYST Brown-out Reset Hysteresis — 100 — mV 37* TBOR Brown-out Reset Minimum 100 — — μs VDD ≤ VBOR Detection Period Legend: TBD = To Be Determined * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper- ation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitivey decoupled as close to the device as possible. 0.1μF and 0.01μF values in parallel are recommended. © 2009 Microchip Technology Inc. DS41288F-page 161

PIC16F610/616/16HV610/616 FIGURE 15-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value Period 30 or TCY + 40 (1, 2, 4, 8) N Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range — 32.768 — kHz (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync Increment mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41288F-page 162 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 15-11: CAPTURE/COMPARE/PWM TIMINGS (ECCP) CCP1 (Capture mode) CC01 CC02 CC03 Note: Refer to Figure15-5 for load conditions. TABLE 15-6: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCP1 Input Period 3TCY + 40 — — ns N = prescale N value (1, 4 or 16) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. DS41288F-page 163

PIC16F610/616/16HV610/616 TABLE 15-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristics Min Typ† Max Units Comments No. CM01 VOS Input Offset Voltage(2) — ± 5.0 ± 10 mV CM02 VCM Input Common Mode Voltage 0 — VDD – 1.5 V CM03* CMRR Common Mode Rejection Ratio +55 — — dB CM04* TRT Response Time(1) Falling — 150 600 ns Rising — 200 1000 ns CM05* TMC2COV Comparator Mode Change to Output Valid — — 10 μs CM06* VHYS Input Hysteresis Voltage — 45 60 mV * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD-1.5)/2-100mV to (VDD-1.5)/2+20mV. The other input is at (VDD -1.5)/2. 2: Input offset voltage is measured with one comparator input at (VDD-1.5V)/2. TABLE 15-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristics Min Typ† Max Units Comments No. CV01 CLSB Step Size(2) — VDD/24 — V Low Range (VRR = 1) — VDD/32 — V High Range (VRR = 0) CV02 CACC Absolute Accuracy(3) — — ± 1/2 LSb Low Range (VRR = 1) — — ± 1/2 LSb High Range (VRR = 0) CV03 CR Unit Resistor Value (R) — 2k — Ω CV04 CST Settling Time(1) — — 10 μs † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. 2: See Section8.11 “Comparator Voltage Reference” for more information. 3: Absolute Accuracy when CVREF output is ≤ (VDD-1.5). TABLE 15-9: VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VR Voltage Reference Specifications Operating temperature -40°C ≤ TA ≤ +125°C Param Symbol Characteristics Min Typ Max Units Comments No. VR01 VP6OUT VP6 voltage output 0.50 0.6 0.7 V VR02 V1P2OUT V1P2 voltage output 1.05 1.20 1.35 V VR03* TSTABLE Settling Time — 10 — μs * These parameters are characterized but not tested. DS41288F-page 164 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 15-10: SHUNT REGULATOR SPECIFICATIONS (PIC16HV610/616 only) Standard Operating Conditions (unless otherwise stated) SHUNT REGULATOR CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +125°C Param Symbol Characteristics Min Typ Max Units Comments No. SR01 VSHUNT Shunt Voltage 4.75 5 5.4 V SR02 ISHUNT Shunt Current 4 — 50 mA SR03* TSETTLE Settling Time — — 150 ns To 1% of final value SR04 CLOAD Load Capacitance 0.01 — 10 μF Bypass capacitor on VDD pin SR05 ΔISNT Regulator operating current — 180 — μA Includes band gap reference current * These parameters are characterized but not tested. TABLE 15-11: PIC16F616/16HV616 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. AD01 NR Resolution — — 10 bits bit AD02 EIL Integral Error — — ±1 LSb VREF = 5.12V(5) AD03 EDL Differential Error — — ±1 LSb No missing codes to 10 bits VREF = 5.12V(5) AD04 EOFF Offset Error — +1.5 + 2.0 LSb VREF = 5.12V(5) AD07 EGN Gain Error — — ±1 LSb VREF = 5.12V(5) AD06 VREF Reference Voltage(3) 2.2 — — V AD06A 2.5 VDD Absolute minimum to ensure 1LSb accuracy AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended — — 10 kΩ Impedance of Analog Voltage Source AD09* IREF VREF Input Current(3) 10 — 1000 μA During VAIN acquisition. Based on differential of VHOLD to VAIN. — — 50 μA During A/D conversion cycle. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input. 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. 5: VREF = 5V for PIC16HV616. © 2009 Microchip Technology Inc. DS41288F-page 165

PIC16F610/616/16HV610/616 TABLE 15-12: PIC16F616/16HV616 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. AD130* TAD A/D Clock Period 1.6 — 9.0 μs TOSC-based, VREF ≥ 3.0V 3.0 — 9.0 μs TOSC-based, VREF full range A/D Internal RC ADCS<1:0> = 11 (ADRC mode) Oscillator Period 3.0 6.0 9.0 μs At VDD = 2.5V 1.6 4.0 6.0 μs At VDD = 5.0V AD131 TCNV Conversion Time — 11 — TAD Set GO/DONE bit to new data in A/D (not including Result register Acquisition Time)(1) AD132* TACQ Acquisition Time 11.5 — μs AD133* TAMP Amplifier Settling Time — — 5 μs AD134 TGO Q4 to A/D Clock Start — TOSC/2 — — — TOSC/2 + TCY — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Section9.3 “A/D Acquisition Requirements” for minimum conditions. DS41288F-page 166 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 15-12: PIC16F616/16HV616 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 (TOSC/2(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. FIGURE 15-13: PIC16F616/16HV616 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. © 2009 Microchip Technology Inc. DS41288F-page 167

PIC16F610/616/16HV610/616 15.13 High Temperature Operation This section outlines the specifications for the PIC16F616 device operating in a temperature range between -40°C and 150°C.(4) The specifications between -40°C and 150°C(4) are identical to those shown in DS41302 and DS80329. Note1: Writes are not allowed for Flash Program Memory above 125°C. 2: All AC timing specifications are increased by 30%. This derating factor will include parameters such as TPWRT. 3: The temperature range indicator in the part number is “H” for -40°C to 150°C.(4) Example: PIC16F616T-H/ST indicates the device is shipped in a tAPE and reel config- uration, in the TSSOP package, and is rated for operation from -40°C to 150°C.(4) 4: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which the total oper- ating time from 125°C to 150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. TABLE 15-13: ABSOLUTE MAXIMUM RATINGS Parameter Source/Sink Value Units Max. Current: VDD Source 20 mA Max. Current: VSS Sink 50 mA Max. Current: PIN Source 5 mA Max. Current: PIN Sink 10 mA Pin Current: at VOH Source 3 mA Pin Current: at VOL Sink 8.5 mA Port Current: A and C Source 20 mA Port Current: A and C Sink 50 mA Maximum Junction Temperature 155 °C Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS41288F-page 168 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 15-14: DC CHARACTERISTICS FOR IDD SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Condition Param Device Units Min Typ Max No. Characteristics VDD Note D010 — 13 58 2.0 Supply Current (IDD) μA — 19 67 3.0 IDD LP OSC (32 kHz) — 32 92 5.0 D011 — 135 316 2.0 μA — 185 400 3.0 IDD XT OSC (1 MHz) — 300 537 5.0 D012 — 240 495 2.0 μA — 360 680 3.0 IDD XT OSC (4 MHz) mA — 0.660 1.20 5.0 D013 — 75 158 2.0 μA — 155 338 3.0 IDD EC OSC (1 MHz) — 345 792 5.0 D014 — 185 357 2.0 μA — 325 625 3.0 IDD EC OSC (4 MHz) mA — 0.665 1.30 5.0 D016 — 245 476 2.0 μA — 360 672 3.0 IDD INTOSC (4 MHz) — 620 1.10 5.0 D017 μA — 395 757 2.0 — 0.620 1.20 3.0 IDD INTOSC (8 MHz) mA — 1.20 2.20 5.0 D018 — 175 332 2.0 μA — 285 518 3.0 IDD EXTRC (4 MHz) — 530 972 5.0 D019 — 2.20 4.10 4.5 mA IDD HS OSC (20 MHz) — 2.80 4.80 5.0 © 2009 Microchip Technology Inc. DS41288F-page 169

PIC16F610/616/16HV610/616 TABLE 15-15: DC CHARACTERISTICS FOR IPD SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Condition Param Device Units Min Typ Max No. Characteristics VDD Note D020E — 0.05 12 2.0 Power Down IPD μA — 0.15 13 3.0 IPD Base — 0.35 14 5.0 D021E — 0.5 20 2.0 μA — 2.5 25 3.0 WDT Current — 9.5 36 5.0 D022E — 5.0 28 3.0 μA BOR Current — 6.0 36 5.0 D023E — 105 195 2.0 IPD Current (Both μA — 110 210 3.0 Comparators Enabled) — 116 220 5.0 — 50 105 2.0 μA IPD Current (One Comparator — 55 110 3.0 Enabled) — 60 125 5.0 D024E — 30 58 2.0 μA — 45 85 3.0 IPD (CVREF, High Range) — 75 142 5.0 D025E — 39 76 2.0 μA — 59 114 3.0 IPD (CVREF, Low Range) — 98 190 5.0 D026E — 5.5 30 2.0 μA — 7.0 35 3.0 IPD (T1 OSC, 32 kHz) — 8.5 45 5.0 D027E — 0.2 12 3.0 μA IPD (A2D on, not converting) — 0.3 15 5.0 TABLE 15-16: WATCHDOG TIMER SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Param Sym Characteristic Units Min Typ Max Conditions No. 31 TWDT Watchdog Timer Time-out Period ms 6 20 70 150°C Temperature (No Prescaler) TABLE 15-17: LEAKAGE CURRENT SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Param Sym Characteristic Units Min Typ Max Conditions No. D061 IIL Input Leakage Current(1) µA — ±0.5 ±5.0 VSS ≤ VPIN ≤ VDD (GP3/RA3/MCLR) D062 IIL Input Leakage Current(2) µA 50 250 400 VDD = 5.0V (GP3/RA3/MCLR) Note 1: This specification applies when GP3/RA3/MCLR is configured as an input with the pull-up disabled. The leakage current for the GP3/RA3/MCLR pin is higher than for the standard I/O port pins. 2: This specification applies when GP3/RA3/MCLR is configured as the MCLR Reset pin function with the weak pull-up enabled. DS41288F-page 170 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 TABLE 15-18: OSCILLATOR PARAMETERS FOR PIC16F616 – H (High Temp.) Param Frequency Sym Characteristic Units Min Typ Max Conditions No. Tolerance OS08 INTOSC Int. Calibrated INTOSC ±10% MHz 7.2 8.0 8.8 2.0V ≤ VDD ≤ 5.5V Freq.(1) -40°C ≤ TA ≤ 150°C Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended. TABLE 15-19: COMPARATOR SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Param Sym Characteristic Units Min Typ Max Conditions No. CM01 VOS Input Offset Voltage mV — ±5 ±20 (VDD - 1.5)/2 © 2009 Microchip Technology Inc. DS41288F-page 171

PIC16F610/616/16HV610/616 NOTES: DS41288F-page 172 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean+3σ) or (mean- 3σ) respectively, where s is a standard deviation, over each temperature range. FIGURE 16-1: PIC16F610/616 IDD LP (32 kHz) vs. VDD 60 Typical: Statistical Mean @25°C Maximum 50 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 40 A) Typical µ 30 P ( L D D 20 I 10 0 1 2 3 4 5 6 VDD (V) FIGURE 16-2: PIC16F610/616 IDD EC (1 MHz) vs. VDD 600 Maximum Typical: Statistical Mean @25°C 500 Maximum: Mean (Worst-Case Temp) + 3σ A) 400 (-40°C to 125°C) C (µ Typical E 300 D D I 200 100 0 1 2 3 4 5 6 VDD (V) © 2009 Microchip Technology Inc. DS41288F-page 173

PIC16F610/616/16HV610/616 FIGURE 16-3: PIC16F610/616 IDD EC (4 MHz) vs. VDD 1200 Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3σ 1000 (-40°C to 125°C) 800 A) Typical µ C ( 600 E D D I 400 200 0 1 2 3 4 5 6 VDD (V) FIGURE 16-4: PIC16F610/616 IDD XT (1 MHz) vs. VDD 1200 Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 800 A) T (µ 600 X Maximum D D 400 I Typical 200 0 1 2 3 4 5 6 VDD (V) FIGURE 16-5: PIC16F610/616 IDD XT (4 MHz) vs. VDD 1200 Maximum Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 800 A) Typical µ T ( 600 X DD 400 I 200 0 1 2 3 4 5 6 VDD (V) DS41288F-page 174 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 16-6: PIC16F610/616 IDD INTOSC (4 MHz) vs. VDD 900 Maximum 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 700 (-40°C to 125°C) Typical 600 A) µ C ( 500 S O T 400 N ID 300 D I 200 100 0 1 2 3 4 5 6 VDD (V) FIGURE 16-7: PIC16F610/616 IDD INTOSC (8 MHz) vs. VDD 1800 Maximum 1600 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 1400 (-40°C to 125°C) Typical 1200 A) µ C ( 1000 S O T 800 N ID D 600 I 400 200 0 1 2 3 4 5 6 VDD (V) © 2009 Microchip Technology Inc. DS41288F-page 175

PIC16F610/616/16HV610/616 FIGURE 16-8: PIC16F610/616 IDD EXTRC (4 MHz) vs. VDD 800 Maximum Typical: Statistical Mean @25°C 700 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 600 Typical A) 500 µ C ( 400 R T X ED 300 D I 200 100 0 1 2 3 4 5 6 VDD (V) FIGURE 16-9: PIC16F610/616 IDD HS (20 MHz) vs. VDD 4 Maximum 3 Typical Typical: Statistical Mean @25°C A) Maximum: Mean (Worst-Case Temp) + 3σ µ (-40°C to 125°C) S ( 2 H D D I 1 0 4 5 6 VDD (V) DS41288F-page 176 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 16-10: PIC16F610/616 IPD BASE vs. VDD 9 Extended Typical: Statistical Mean @25°C 8 Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ 7 (-40°C to 125°C) 6 A) µ E ( 5 S A B D P 4 I 3 2 Industrial 1 Typical 0 1 2 3 4 5 6 VDD (V) FIGURE 16-11: PIC16F610/616 IPD COMPARATOR (SINGLE ON) vs. VDD 90 Extended 80 Industrial 70 A) µ P ( M C Typical D 60 P I 50 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ 40 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 30 1 2 3 4 5 6 VDD (V) © 2009 Microchip Technology Inc. DS41288F-page 177

PIC16F610/616/16HV610/616 FIGURE 16-12: PIC16F610/616 IPD COMPARATOR (BOTH ON) vs. VDD 160 Extended 150 Industrial 140 130 A) µ 120 P ( Typical M C D 110 P I 100 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) 90 Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 80 1 2 3 4 5 6 VDD (V) FIGURE 16-13: PIC16F610/616 IPD WDT vs. VDD 20 Extended 18 Typical: Statistical Mean @25°C Industrial 16 Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) 14 A) Extended: Mean (Worst-Case Temp) + 3σ µ 12 (-40°C to 125°C) T ( D 10 W Typical PD 8 I 6 4 2 0 1 2 3 4 5 6 VDD (V) DS41288F-page 178 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 16-14: PIC16F610/616 IPD BOR vs. VDD 20 Typical: Statistical Mean @25°C Extended Industrial: Mean (Worst-Case Temp) + 3σ 18 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ 16 (-40°C to 125°C) 14 Industrial A) µ 12 R ( O B 10 D P I 8 Typical 6 4 2 0 1 2 3 4 5 6 VDD (V) FIGURE 16-15: PIC16F610/616 IPD CVREF (LOW RANGE) vs. VDD 140 Typical: Statistical Mean @25°C Maximum Industrial: Mean (Worst-Case Temp) + 3σ 120 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Typical 100 80 A) µ (F E VR 60 C D P I 40 20 0 1 2 3 4 5 6 VDD (V) © 2009 Microchip Technology Inc. DS41288F-page 179

PIC16F610/616/16HV610/616 FIGURE 16-16: PIC16F610/616 IPD CVREF (HI RANGE) vs. VDD 120 Typical: Statistical Mean @25°C Maximum Industrial: Mean (Worst-Case Temp) + 3σ 100 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ 80 (-40°C to 125°C) A) Typical µ F ( 60 E R V C 40 D P I 20 0 1 2 3 4 5 6 VDD (V) FIGURE 16-17: PIC16F610/616 IPD T1OSC vs. VDD 25 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended Extended: Mean (Worst-Case Temp) + 3σ 20 (-40°C to 125°C) A) µ C ( 15 S Industrial O 1 T D P I 10 Typical 5 0 1 2 3 4 5 6 VDD (V) DS41288F-page 180 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 16-18: PIC16F616 IPD A/D vs. VDD 14 Typical: Statistical Mean @25°C Extended Industrial: Mean (Worst-Case Temp) + 3σ 12 (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ 10 (-40°C to 125°C) A) µ 8 D ( 2 A D 6 P I 4 Industrial 2 Typical 0 1 2 3 4 5 6 VDD (V) FIGURE 16-19: PIC16HV610/616 IDD LP (32 kHz) vs. VDD 450 Maximum 400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 350 (-40°C to 125°C) 300 Typical A) µ 250 P ( L 200 D D I 150 100 50 0 1 2 3 4 5 VDD (V) © 2009 Microchip Technology Inc. DS41288F-page 181

PIC16F610/616/16HV610/616 FIGURE 16-20: PIC16HV610/616 IDD EC (1 MHz) vs. VDD 1000 900 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ Maximum 800 (-40°C to 125°C) 700 A) µ C ( 600 E Typical D 500 D I 400 300 200 100 1 2 3 4 5 VDD (V) FIGURE 16-21: PIC16HV610/616 IDD EC (4 MHz) vs. VDD 1400 Maximum Typical: Statistical Mean @25°C 1200 Maximum: Mean (Worst-Case Temp) + 3σ A) 1000 (-40°C to 125°C) C (µ 800 Typical E D D 600 I 400 200 0 1 2 3 4 5 VDD (V) FIGURE 16-22: PIC16HV610/616 IDD XT (1 MHz) vs. VDD 900 800 Typical: Statistical Mean @25°C Maximum 700 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 600 A) Typical µ T ( 500 X D 400 D I 300 200 100 0 1 2 3 4 5 VDD (V) DS41288F-page 182 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 16-23: PIC16HV610/616 IDD XT (4 MHz) vs. VDD 1400 Maximum Typical: Statistical Mean @25°C 1200 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 1000 Typical A) µ 800 T ( X D 600 D I 400 200 0 1 2 3 4 5 VDD (V) FIGURE 16-24: PIC16HV610/616 IDD INTOSC (4 MHz) vs. VDD 1200 Maximum Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3σ A) (-40°C to 125°C) C (µ 800 Typical S O T 600 N ID D 400 I 200 0 1 2 3 4 5 VDD (V) FIGURE 16-25: PIC16HV610/616 IDD INTOSC (8 MHz) vs. VDD 2000 Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3σ A) 1500 (-40°C to 125°C) µ C ( Typical S O 1000 T N ID D I 500 0 1 2 3 4 5 VDD (V) © 2009 Microchip Technology Inc. DS41288F-page 183

PIC16F610/616/16HV610/616 FIGURE 16-26: PIC16HV610/616 IDD EXTRC (4 MHz) vs. VDD 1200 Maximum Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3σ A) (-40°C to 125°C) µ 800 Typical C ( R XT 600 E D D 400 I 200 0 1 2 3 4 5 VDD (V) FIGURE 16-27: PIC16HV610/616 IPD BASE vs. VDD 400 Maximum Typical: Statistical Mean @25°C 350 Maximum: Mean (Worst-Case Temp) + 3σ A) 300 (-40°C to 125°C) µ E ( Typical S 250 A B D 200 P I 150 100 50 0 1 2 3 4 5 VDD (V) FIGURE 16-28: PIC16HV610/616 IPD COMPARATOR (SINGLE ON) vs. VDD Typical: Statistical Mean @25°C 500 Maximum: Mean (Worst-Case Temp) + 3σ Maximum (-40°C to 125°C) 400 Typical A) 300 µ P ( M C 200 D P I 100 0 1 2 3 4 5 VDD (V) DS41288F-page 184 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 16-29: PIC16HV610/616 IPD COMPARATOR (BOTH ON) vs. VDD 600 Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3σ 500 (-40°C to 125°C) 400 A) Typical µ P ( 300 M C D P 200 I 100 0 1 2 3 4 5 VDD (V) FIGURE 16-30: PIC16HV610/616 IPD WDT vs. VDD 400 Typical: Statistical Mean @25°C Maximum 350 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) A) 300 µ Typical T ( 250 D W D 200 P I 150 100 50 0 1 2 3 4 5 VDD (V) FIGURE 16-31: PIC16HV610/616 IPD BOR vs. VDD 400 Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3σ 350 (-40°C to 125°C) A) 300 µ R ( Typical O 250 B D P I 200 150 100 2 3 4 5 VDD (V) © 2009 Microchip Technology Inc. DS41288F-page 185

PIC16F610/616/16HV610/616 FIGURE 16-32: PIC16HV610/616 IPD CVREF (LOW RANGE) vs. VDD 500 Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3σ 400 A) (-40°C to 125°C) Typical µ F ( 300 E R V CD 200 P I 100 0 1 2 3 4 5 VDD (V) FIGURE 16-33: PIC16HV610/616 IPD CVREF (HI RANGE) vs. VDD 500 Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3σ 400 (-40°C to 125°C) A) Typical F (µ 300 E R V 200 C D P I 100 0 1 2 3 4 5 VDD (V) FIGURE 16-34: PIC16HV610/616 IPD T1OSC vs. VDD Typical: Statistical Mean @25°C 400 Maximum: Mean (Worst-Case Temp) + 3σ Maximum (-40°C to 125°C) 350 300 A) Typical µ 250 C ( S 200 O 1 T 150 D P I 100 50 0 1 2 3 4 5 VDD (V) DS41288F-page 186 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 16-35: PIC16HV616 IPD A/D vs. VDD Typical: Statistical Mean @25°C 400 Maximum: Mean (Worst-Case Temp) + 3σ Maximum (-40°C to 125°C) 350 300 Typical A) 250 µ D ( 200 2 A D 150 P I 100 50 0 2 3 VDD (V) 4 5 FIGURE 16-36: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-Case Temp) + 3σ Max. 125°C (-40°C to 125°C) 0.6 0.5 Max. 85°C V) (L 0.4 O V Typical 25°C 0.3 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) © 2009 Microchip Technology Inc. DS41288F-page 187

PIC16F610/616/16HV610/616 FIGURE 16-37: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. 125°C 0.35 Max. 85°C 0.30 0.25 V) (L Typ. 25°C O V 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 16-38: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C 2.0 V) (H O V 1.5 Typical: Statistical Mean @25°C 1.0 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) DS41288F-page 188 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 16-39: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) 5.5 5.0 Max. -40°C Typ. 25°C 4.5 V) Min. 125°C (H O V 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) FIGURE 16-40: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. -40°C 1.3 Typ. 25°C V) (N 1.1 VI Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2009 Microchip Technology Inc. DS41288F-page 189

PIC16F610/616/16HV610/616 FIGURE 16-41: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) VIH Min. -40°C 3.0 2.5 V) (N VI 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-42: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 16 Typical: Statistical Mean @25°C 14 Maximum: Mean (Worst-Case Temp) + 3σ 85°C (-40°C to 125°C) 12 25°C 10 s) -40°C µ e ( 8 m Ti 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41288F-page 190 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 16-43: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 25 Typical: Statistical Mean @25°C 20 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 15 s) 85°C µ e ( m Ti 25°C 10 -40°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-44: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 10 9 Typical: Statistical Mean @25°C 8 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 7 85°C 6 s) 25°C μ e ( 5 m Ti -40°C 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2009 Microchip Technology Inc. DS41288F-page 191

PIC16F610/616/16HV610/616 FIGURE 16-45: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 3 2 %) n ( 1 o ati br 0 ali m C -1 o e fr -2 g n a -3 h C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-46: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (85°C) 5 4 3 %) n ( 2 o ati 1 r b Cali 0 m o -1 r e f ng -2 a h C -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41288F-page 192 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 16-47: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 3 %) 2 n ( o 1 ati r alib 0 C m -1 o r e f -2 g n ha -3 C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD ( V) FIGURE 16-48: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 3 %) 2 n ( o 1 ati r b 0 ali C m -1 o r e f -2 g n ha -3 C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD ( V) © 2009 Microchip Technology Inc. DS41288F-page 193

PIC16F610/616/16HV610/616 FIGURE 16-49: 0.6V REFERENCE VOLTAGE vs. TEMP (TYPICAL) 0.61 2.5V 0.6 3V V) e ( 4V g 0.59 a olt ce V 0.58 5V n 5.5V e r e Ref 0.57 0.56 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) FIGURE 16-50: 1.2V REFERENCE VOLTAGE vs. TEMP (TYPICAL) 1.26 2.5V 1.25 3V V) e ( 1.24 4V g olta 1.23 5V V 5.5V e c n e 1.22 r e ef R 1.21 1.2 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) FIGURE 16-51: SHUNT REGULATOR VOLTAGE vs. INPUT CURRENT (TYPICAL) 5.16 5.14 -40°C 25°C V) 5.12 85°C e ( 5.1 g 125°C a olt 5.08 V r 5.06 o at 5.04 ul eg 5.02 R nt 5 u h 4.98 S 4.96 0 10 20 30 40 50 60 Input Current (mA) DS41288F-page 194 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 FIGURE 16-52: SHUNT REGULATOR VOLTAGE vs. TEMP (TYPICAL) 5.16 5.14 V) e ( 5.12 g 5.1 olta 5.08 50 mA or V 5.06 40 mA at ul 5.04 g 20 mA Re 5.02 nt 5 15 mA hu 10 mA S 4.98 4 mA 4.96 -60 -40 -20 0 20 40 60 80 100 120 140 Temp (C) FIGURE 16-53: COMPARATOR RESPONSE TIME (RISING EDGE) 1000 900 800 Max. 125°C 700 S) n e ( 600 Note: V c m = (VDD - 1.5V)/2 m Ti V+ input = Vcm Max. 85°C e 500 V- input = Transition from Vcm + 100mV to Vcm - 20mV s n o p 400 s e R 300 200 Typ. 25°C Min. -40°C 100 0 2.0 2.5 4.0 5.5 VDD (V) © 2009 Microchip Technology Inc. DS41288F-page 195

PIC16F610/616/16HV610/616 FIGURE 16-54: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 800 Max. 125°C 700 S) n 600 Note: V C M = (VDD - 1.5V)/2 me ( V+ input = VCM Max. 85°C Ti 500 V- input = Transition from VCM - 100MV to VCM + 20MV e s n 400 o p s Re 300 Typ. 25°C 200 Min. -40°C 100 0 2.0 2.5 4.0 5.5 VDD (V) FIGURE 16-55: WDT TIME-OUT PERIOD vs. VDD OVER TEMPERATURE 55 50 45 40 35 s) m 30 me ( 125°C Ti 25 85°C 20 25°C 15 -40°C 10 5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) DS41288F-page 196 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 14-Lead PDIP Example XXXXXXXXXXXXXX PIC16F616 XXXXXXXXXXXXXX -I/P e3 YYWWNNN 0610017 14-Lead SOIC (.150”) Example XXXXXXXXXXX PIC16F616-E XXXXXXXXXXX YYWWNNN 0610017 14-Lead TSSOP Example XXXXXXXX XXXX/ST YYWW 0610 NNN 017 16-Lead QFN Example XXXXXXX 16F616 XXXXXXX -I/ML YYWWNNN 0610017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability code. For PIC® device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2009 Microchip Technology Inc. DS41288F-page 197

PIC16F610/616/16HV610/616 17.2 Package Details The following sections give the technical details of the packages. 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(cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:20)(cid:4)(cid:29)(cid:4).(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2(cid:2)1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)(cid:4)01 DS41288F-page 198 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)!(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)"(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)!(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)(cid:31)(cid:7)##(cid:27)$%(cid:9)(cid:23)&’(cid:24)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)!"(cid:18)((cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 3 e h b α h c φ A A2 A1 L L1 β 6(cid:15)(cid:7)% (cid:6)(cid:19)99(cid:19)(cid:6)-(cid:13)-(cid:26)(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:29)(cid:23) (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:29)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)% (cid:25) < < (cid:29)(cid:20)(cid:5)0 (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:29)(cid:20)(cid:3)0 < < (cid:22)%(cid:28)(cid:15)"(cid:10)$$(cid:2)(cid:2)* (cid:25)(cid:29) (cid:4)(cid:20)(cid:29)(cid:4) < (cid:4)(cid:20)(cid:3)0 :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)"%(cid:11) - ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22)+ (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) ,(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) >(cid:20)?0(cid:2)1(cid:22)+ +(cid:11)(cid:28)&$(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)%(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)0 < (cid:4)(cid:20)0(cid:4) 3(cid:10)(cid:10)%(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) < (cid:29)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)%(cid:12)(cid:9)(cid:7)(cid:15)% 9(cid:29) (cid:29)(cid:20)(cid:4)(cid:23)(cid:2)(cid:26)-3 3(cid:10)(cid:10)%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B < >B 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:29)(cid:5) < (cid:4)(cid:20)(cid:3)0 9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:4)(cid:20),(cid:29) < (cid:4)(cid:20)0(cid:29) (cid:6)(cid:10)(cid:16)"(cid:2)(cid:21)(cid:9)(cid:28)$%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) 0B < (cid:29)0B (cid:6)(cid:10)(cid:16)"(cid:2)(cid:21)(cid:9)(cid:28)$%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)%%(cid:10)& (cid:5) 0B < (cid:29)0B (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) *(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)$(cid:7)(cid:8)(cid:28)(cid:15)%(cid:2)+(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)%(cid:14)(cid:9)(cid:7) %(cid:7)(cid:8)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:4)(cid:20)(cid:29)0(cid:2)&&(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2 1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)-32 (cid:26)(cid:14)$(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)’(cid:2)! !(cid:28)(cid:16)(cid:16)(cid:18)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2)$(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)$(cid:10)(cid:9)&(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)!(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)?01 © 2009 Microchip Technology Inc. DS41288F-page 199

PIC16F610/616/16HV610/616 (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS41288F-page 200 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9))*(cid:14)(cid:19)(cid:9)!*#(cid:14)(cid:19)+(cid:9)!(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)"(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)!)(cid:21)(cid:9)(cid:22)(cid:9)(cid:3)&(cid:3)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29))!!"(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 e b c φ A A2 A1 L1 L 6(cid:15)(cid:7)% (cid:6)(cid:19)99(cid:19)(cid:6)-(cid:13)-(cid:26)(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:29)(cid:23) (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?0(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)% (cid:25) < < (cid:29)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20)>(cid:4) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)(cid:4)0 (cid:22)%(cid:28)(cid:15)"(cid:10)$$(cid:2) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)0 < (cid:4)(cid:20)(cid:29)0 :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)"%(cid:11) - ?(cid:20)(cid:23)(cid:4)(cid:2)1(cid:22)+ (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) (cid:23)(cid:20),(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)0(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) (cid:23)(cid:20)(cid:24)(cid:4) 0(cid:20)(cid:4)(cid:4) 0(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)%(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) 9 (cid:4)(cid:20)(cid:23)0 (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)0 3(cid:10)(cid:10)%(cid:12)(cid:9)(cid:7)(cid:15)% 9(cid:29) (cid:29)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26)-3 3(cid:10)(cid:10)%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B < >B 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) < (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:4)(cid:20)(cid:29)(cid:24) < (cid:4)(cid:20),(cid:4) (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:4)(cid:20)(cid:29)0(cid:2)&&(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2 1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)-32 (cid:26)(cid:14)$(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)’(cid:2)! !(cid:28)(cid:16)(cid:16)(cid:18)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2)$(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)$(cid:10)(cid:9)&(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)!(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)>(cid:5)1 © 2009 Microchip Technology Inc. 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PIC16F610/616/16HV610/616 (cid:2),(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)-(cid:17)(cid:7)(cid:8)(cid:9).(cid:11)(cid:7)(cid:13)%(cid:9)(cid:31)(cid:27)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)+(cid:7)/(cid:6)(cid:9)(cid:20)0(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)(cid:3)1(cid:3)1(cid:24)&’(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)-.(cid:31)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E E2 2 2 b 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A3 A A1 6(cid:15)(cid:7)% (cid:6)(cid:19)99(cid:19)(cid:6)-(cid:13)-(cid:26)(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:29)? 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PIC16F610/616/16HV610/616 (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2009 Microchip Technology Inc. DS41288F-page 203

PIC16F610/616/16HV610/616 NOTES: DS41288F-page 204 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 APPENDIX A: DATA SHEET REVISION HISTORY Revision A This is a new data sheet. Revision B (12/06) Added PIC16F610/16HV610 parts. Replaced Package Drawings. Revision C (03/2007) Replaced Package Drawings (Rev. AM); Replaced Development Support Section; Revised Product ID System. Revision D (06/2008) Added Graphs; Revised 28-Pin ICD Pinout, Electrical Specifications Section; Package Details. Revision E (09/2009) Added section 15.13 (High Temperature Operation) to the Electrical Specifications Chapter; Other minor corrections. Revision F (11/2009) Updated Figure 16-52. © 2009 Microchip Technology Inc. DS41288F-page 205

PIC16F610/616/16HV610/616 APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This discusses some of the issues in migrating from other PIC® devices to the PIC16F6XX Family of devices. B.1 PIC16F676 to PIC16F610/616/16HV610/616 TABLE B-1: FEATURE COMPARISON Feature PIC16F676 PIC16F610/16HV610 PIC16F616/16HV616 Max Operating Speed 20MHz 20MHz 20MHz Max Program Memory (Words) 1024 1024 2048 SRAM (bytes) 64 64 128 A/D Resolution 10-bit None 10-bit Timers (8/16-bit) 1/1 1/1 2/1 Oscillator Modes 8 8 8 Brown-out Reset Y Y Y Internal Pull-ups RA0/1/2/4/5 RA0/1/2/4/5, MCLR RA0/1/2/4/5, MCLR Interrupt-on-change RA0/1/2/3/4/5 RA0/1/2/3/4/5 RA0/1/2/3/4/5 Comparator 1 2 2 ECCP N N Y INTOSC Frequencies 4MHz 4/8MHz 4/8MHz Internal Shunt Regulator N Y (PIC16HV610) Y (PIC16HV616) Note: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. DS41288F-page 206 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 INDEX A RC2 and RC3 Pins.....................................................43 RC4 Pin......................................................................44 A/D RC5 Pin......................................................................44 Specifications....................................................165, 166 Resonator Operation..................................................29 Absolute Maximum Ratings..............................................143 Timer1........................................................................49 AC Characteristics Timer2........................................................................55 Industrial and Extended............................................157 TMR0/WDT Prescaler................................................45 Load Conditions........................................................156 Watchdog Timer.......................................................122 ADC....................................................................................73 Brown-out Reset (BOR)....................................................113 Acquisition Requirements...........................................81 Associated Registers................................................114 Associated registers....................................................83 Specifications...........................................................161 Block Diagram.............................................................73 Timing and Characteristics.......................................160 Calculating Acquisition Time.......................................81 Channel Selection.......................................................74 C Configuration...............................................................74 C Compilers Configuring Interrupt...................................................76 MPLAB C18..............................................................140 Conversion Clock........................................................74 Calibration Bits..................................................................111 Conversion Procedure................................................76 Capture Module. See Enhanced Capture/Compare/PWM Internal Sampling Switch (RSS) Impedance................81 (ECCP) Interrupts.....................................................................75 Capture/Compare/PWM (CCP) Operation....................................................................76 Associated registers w/ Capture/Compare/PWM 87, 89, Operation During Sleep..............................................76 105 Port Configuration.......................................................74 Capture Mode.............................................................86 Reference Voltage (VREF)...........................................74 CCP1 Pin Configuration.............................................86 Result Formatting........................................................75 Compare Mode...........................................................88 Source Impedance......................................................81 CCP1 Pin Configuration.....................................88 Special Event Trigger..................................................76 Software Interrupt Mode...............................86, 88 Starting an A/D Conversion........................................75 Special Event Trigger.........................................88 ADCON0 Register...............................................................78 Timer1 Mode Selection.................................86, 88 ADCON1 Register...............................................................79 Prescaler....................................................................86 ADRESH Register (ADFM = 0)...........................................80 PWM Mode.................................................................90 ADRESH Register (ADFM = 1)...........................................80 Duty Cycle..........................................................91 ADRESL Register (ADFM = 0)............................................80 Effects of Reset..................................................92 ADRESL Register (ADFM = 1)............................................80 Example PWM Frequencies and Resolutions, 20 Analog-to-Digital Converter. See ADC MHz............................................................91 ANSEL Register..................................................................34 Example PWM Frequencies and Resolutions, 8 Assembler MHz............................................................91 MPASM Assembler...................................................140 Operation in Sleep Mode....................................92 B Setup for Operation............................................92 System Clock Frequency Changes....................92 Block Diagrams PWM Period...............................................................91 (CCP) Capture Mode Operation.................................86 Setup for PWM Operation..........................................92 ADC............................................................................73 CCP1CON (Enhanced) Register........................................85 ADC Transfer Function...............................................82 Clock Sources Analog Input Model...............................................64, 82 External Modes...........................................................28 CCP PWM...................................................................90 EC......................................................................28 Clock Source...............................................................27 HS......................................................................29 Comparator C1...........................................................58 LP.......................................................................29 Comparator C2...........................................................58 OST....................................................................28 Compare Mode Operation..........................................88 RC......................................................................30 Crystal Operation........................................................29 XT.......................................................................29 External RC Mode.......................................................30 Internal Modes............................................................30 In-Circuit Serial Programming Connections..............126 INTOSC..............................................................30 Interrupt Logic...........................................................119 INTOSCIO..........................................................30 MCLR Circuit.............................................................112 CM1CON0 Register............................................................62 On-Chip Reset Circuit...............................................111 CM2CON0 Register............................................................63 PIC16F610/16HV610....................................................9 CM2CON1 Register............................................................65 PIC16F616/16HV616..................................................10 Code Examples PWM (Enhanced)........................................................93 A/D Conversion..........................................................77 RA0 and RA1 Pins......................................................36 Assigning Prescaler to Timer0....................................46 RA2 Pins.....................................................................37 Assigning Prescaler to WDT.......................................46 RA3 Pin.......................................................................38 Changing Between Capture Prescalers.....................86 RA4 Pin.......................................................................39 Indirect Addressing.....................................................24 RA5 Pin.......................................................................40 Initializing PORTA......................................................33 RC0 and RC1 Pins......................................................43 © 2009 Microchip Technology Inc. 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PIC16F610/616/16HV610/616 Initializing PORTC.......................................................42 Specifications...........................................................163 Saving Status and W Registers in RAM...................121 Timer Resources........................................................85 Code Protection................................................................125 Errata....................................................................................8 Comparator F C2OUT as T1 Gate.....................................................65 Operation....................................................................57 Firmware Instructions.......................................................129 Operation During Sleep..............................................61 Fuses. See Configuration Bits Response Time...........................................................59 G Synchronizing COUT w/Timer1..................................65 Comparator Analog Input Connection Considerations........64 General Purpose Register File...........................................14 Comparator Hysteresis.......................................................66 H Comparator Module............................................................57 High Temperature Operation............................................168 Associated registers....................................................67 C1 Output State Versus Input Conditions...................59 I Comparator Voltage Reference (CVREF)............................70 ID Locations......................................................................125 Effects of a Reset........................................................61 In-Circuit Debugger...........................................................126 Comparator Voltage Reference (CVREF) In-Circuit Serial Programming (ICSP)...............................126 Response Time...........................................................59 Indirect Addressing, INDF and FSR registers.....................24 Comparator Voltage Reference (CVREF) Instruction Format.............................................................129 Specifications............................................................164 Instruction Set...................................................................129 Comparators ADDLW.....................................................................131 C2OUT as T1 Gate.....................................................50 ADDWF.....................................................................131 Effects of a Reset........................................................61 ANDLW.....................................................................131 Specifications............................................................164 ANDWF.....................................................................131 Compare Module. See Enhanced Capture/Compare/PWM MOVF.......................................................................134 (ECCP) BCF..........................................................................131 CONFIG Register..............................................................110 BSF...........................................................................131 Configuration Bits..............................................................109 BTFSC......................................................................131 CPU Features...................................................................109 BTFSS......................................................................132 Customer Change Notification Service.............................211 CALL.........................................................................132 Customer Notification Service...........................................211 CLRF........................................................................132 Customer Support.............................................................211 CLRW.......................................................................132 D CLRWDT..................................................................132 Data Memory.......................................................................14 COMF.......................................................................132 DC and AC Characteristics DECF........................................................................132 Graphs and Tables...................................................173 DECFSZ...................................................................133 DC Characteristics GOTO.......................................................................133 Extended and Industrial....................................153, 154 INCF.........................................................................133 Industrial and Extended............................................146 INCFSZ.....................................................................133 Development Support.......................................................139 IORLW......................................................................133 Device Overview...................................................................9 IORWF......................................................................133 MOVLW....................................................................134 E MOVWF....................................................................134 ECCP. See Enhanced Capture/Compare/PWM NOP..........................................................................134 ECCPAS Register.............................................................102 RETFIE.....................................................................135 Effects of Reset RETLW.....................................................................135 PWM mode.................................................................92 RETURN...................................................................135 Electrical Specifications....................................................143 RLF...........................................................................136 Enhanced Capture/Compare/PWM.....................................85 RRF..........................................................................136 Enhanced Capture/Compare/PWM (ECCP) SLEEP......................................................................136 Enhanced PWM Mode................................................93 SUBLW.....................................................................136 Auto-Restart......................................................103 SUBWF.....................................................................137 Auto-shutdown..................................................102 SWAPF.....................................................................137 Direction Change in Full-Bridge Output Mode....99 XORLW....................................................................137 Full-Bridge Application........................................97 XORWF....................................................................137 Full-Bridge Mode.................................................97 Summary Table........................................................130 Half-Bridge Application.......................................96 INTCON Register................................................................20 Half-Bridge Application Examples.....................104 Internal Oscillator Block Half-Bridge Mode................................................96 INTOSC Output Relationships (Active-High and Active-Low) Specifications...........................................158, 159 94 Internal Sampling Switch (RSS) Impedance........................81 Output Relationships Diagram............................95 Internet Address...............................................................211 Programmable Dead Band Delay.....................104 Interrupts...........................................................................118 Shoot-through Current......................................104 ADC............................................................................76 Start-up Considerations....................................101 Associated Registers................................................120 DS41288F-page 208 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 Context Saving..........................................................121 Additional Pin Functions.............................................34 Interrupt-on-Change....................................................34 ANSEL Register.................................................34 PORTA Interrupt-on-Change....................................119 Interrupt-on-Change...........................................34 RA2/INT....................................................................118 Weak Pull-Ups....................................................34 Timer0.......................................................................119 Associated registers...................................................41 TMR1..........................................................................51 Pin Descriptions and Diagrams..................................36 INTOSC Specifications.............................................158, 159 RA0.............................................................................36 IOCA Register.....................................................................35 RA1.............................................................................36 RA2.............................................................................37 L RA3.............................................................................38 Load Conditions................................................................156 RA4.............................................................................39 RA5.............................................................................40 M Specifications...........................................................159 MCLR................................................................................112 PORTA Register.................................................................33 Internal......................................................................112 PORTC...............................................................................42 Memory Organization..........................................................13 Associated registers...................................................44 Data............................................................................14 P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/ Program......................................................................13 PWM (ECCP).....................................................42 Microchip Internet Web Site..............................................211 Specifications...........................................................159 Migrating from other PIC Devices.....................................206 PORTC Register.................................................................42 MPLAB ASM30 Assembler, Linker, Librarian...................140 Power-Down Mode (Sleep)...............................................124 MPLAB Integrated Development Environment Software..139 Power-on Reset (POR).....................................................112 MPLAB PM3 Device Programmer....................................142 Power-up Timer (PWRT)..................................................112 MPLAB REAL ICE In-Circuit Emulator System.................141 Specifications...........................................................161 MPLINK Object Linker/MPLIB Object Librarian................140 Precision Internal Oscillator Parameters..........................159 O Prescaler Shared WDT/Timer0...................................................46 OPCODE Field Descriptions.............................................129 Switching Prescaler Assignment................................46 Operational Amplifier (OPA) Module Program Memory................................................................13 AC Specifications......................................................165 Map and Stack (PIC16F610/16HV610)......................13 OPTION Register..........................................................19, 47 Map and Stack (PIC16F616/16HV616)......................13 Oscillator Programming, Device Instructions....................................129 Associated registers..............................................31, 54 PWM Mode. See Enhanced Capture/Compare/PWM........93 Oscillator Module................................................................27 PWM1CON Register.........................................................105 EC...............................................................................27 HS...............................................................................27 R INTOSC......................................................................27 Reader Response.............................................................212 INTOSCIO...................................................................27 Read-Modify-Write Operations.........................................129 LP................................................................................27 Registers RC...............................................................................27 ADCON0 (ADC Control 0)..........................................78 RCIO...........................................................................27 ADCON1 (ADC Control 1)..........................................79 XT...............................................................................27 ADRESH (ADC Result High) with ADFM = 0)............80 Oscillator Parameters.......................................................158 ADRESH (ADC Result High) with ADFM = 1)............80 Oscillator Specifications....................................................157 ADRESL (ADC Result Low) with ADFM = 0)..............80 Oscillator Start-up Timer (OST) ADRESL (ADC Result Low) with ADFM = 1)..............80 Specifications............................................................161 ANSEL (Analog Select)..............................................34 OSCTUNE Register............................................................31 CCP1CON (Enhanced CCP1 Control).......................85 P CM1CON0 (C1 Control).............................................62 CM2CON0 (C2 Control).............................................63 P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/PWM CM2CON1 (C2 Control).............................................65 (ECCP)........................................................................93 CONFIG (Configuration Word).................................110 Packaging.........................................................................197 Data Memory Map (PIC16F610/16HV610)................15 Marking.....................................................................197 Data Memory Map (PIC16F616/16HV616)................15 PDIP Details..............................................................198 ECCPAS (Enhanced CCP Auto-shutdown Control).102 PCL and PCLATH...............................................................24 INTCON (Interrupt Control)........................................20 Stack...........................................................................24 IOCA (Interrupt-on-Change PORTA)..........................35 PCON Register...........................................................23, 114 OPTION_REG (OPTION).....................................19, 47 PIE1 Register......................................................................21 OSCTUNE (Oscillator Tuning)....................................31 Pin Diagram PCON (Power Control Register).................................23 PDIP, SOIC, TSSOP.................................................4, 5 PCON (Power Control).............................................114 QFN..........................................................................6, 7 PIE1 (Peripheral Interrupt Enable 1)..........................21 Pinout Descriptions PIR1 (Peripheral Interrupt Register 1)........................22 PIC16F610/16HV610..................................................11 PORTA.......................................................................33 PIC16F616/16HV616..................................................12 PORTC.......................................................................42 PIR1 Register......................................................................22 PWM1CON (Enhanced PWM Control).....................105 PORTA................................................................................33 Reset Values............................................................116 © 2009 Microchip Technology Inc. DS41288F-page 209

PIC16F610/616/16HV610/616 Reset Values (special registers)...............................117 A/D Conversion.........................................................167 Special Function Registers.........................................14 A/D Conversion (Sleep Mode)..................................167 Special Register Summary.........................................17 Brown-out Reset (BOR)............................................160 SRCON0 (SR Latch Control 0)...................................69 Brown-out Reset Situations......................................113 SRCON1 (SR Latch Control 1)...................................69 CLKOUT and I/O......................................................159 STATUS......................................................................18 Clock Timing.............................................................157 T1CON........................................................................52 Comparator Output.....................................................57 T2CON........................................................................56 Enhanced Capture/Compare/PWM (ECCP).............163 TRISA (Tri-State PORTA)...........................................33 Full-Bridge PWM Output.............................................98 TRISC (Tri-State PORTC)..........................................42 Half-Bridge PWM Output....................................96, 104 VRCON (Voltage Reference Control).........................72 INT Pin Interrupt.......................................................120 WPUA (Weak Pull Up PORTA)...................................35 PWM Auto-shutdown Reset.................................................................................111 Auto-restart Enabled.........................................103 Revision History................................................................205 Firmware Restart..............................................103 PWM Direction Change..............................................99 S PWM Direction Change at Near 100% Duty Cycle...100 Shoot-through Current......................................................104 PWM Output (Active-High).........................................94 Sleep PWM Output (Active-Low)..........................................95 Power-Down Mode...................................................124 Reset, WDT, OST and Power-up Timer...................160 Wake-up....................................................................124 Time-out Sequence Wake-up using Interrupts..........................................124 Case 1..............................................................115 Software Simulator (MPLAB SIM).....................................141 Case 2..............................................................115 Special Event Trigger..........................................................76 Case 3..............................................................115 Special Function Registers.................................................14 Timer0 and Timer1 External Clock...........................162 SRCON0 Register...............................................................69 Timer1 Incrementing Edge.........................................52 SRCON1 Register...............................................................69 Wake-up from Interrupt.............................................125 STATUS Register................................................................18 Timing Parameter Symbology..........................................156 TRISA.................................................................................33 T TRISA Register...................................................................33 T1CON Register..................................................................52 TRISC.................................................................................42 T2CON Register..................................................................56 TRISC Register...................................................................42 Thermal Considerations....................................................155 V Time-out Sequence...........................................................114 Timer0.................................................................................45 Voltage Reference (VR) Associated Registers..................................................47 Specifications...........................................................164 External Clock.............................................................46 Voltage Reference. See Comparator Voltage Reference Interrupt.......................................................................47 (CVREF) Operation....................................................................45 Voltage References Specifications............................................................162 Associated registers...................................................67 T0CKI..........................................................................46 VP6 Stabilization........................................................71 Timer1.................................................................................49 VREF. SEE ADC Reference Voltage Associated registers....................................................54 W Asynchronous Counter Mode.....................................50 Reading and Writing...........................................50 Wake-up Using Interrupts.................................................124 Interrupt.......................................................................51 Watchdog Timer (WDT)....................................................122 Modes of Operation....................................................49 Associated registers.................................................123 Operation....................................................................49 Specifications...........................................................161 Operation During Sleep..............................................51 WPUA Register...................................................................35 Oscillator.....................................................................50 WWW Address.................................................................211 Prescaler.....................................................................50 WWW, On-Line Support.......................................................8 Specifications............................................................162 Timer1 Gate Inverting Gate.....................................................51 Selecting Source...........................................50, 65 SR Latch.............................................................68 Synchronizing COUT w/Timer1..........................65 TMR1H Register.........................................................49 TMR1L Register..........................................................49 Timer2 Associated registers....................................................56 Timers Timer1 T1CON................................................................52 Timer2 T2CON................................................................56 Timing Diagrams DS41288F-page 210 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS41288F-page 211

PIC16F610/616/16HV610/616 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16F610/616/16HV610/616 Literature Number: DS41288F Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41288F-page 212 © 2009 Microchip Technology Inc.

PIC16F610/616/16HV610/616 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F610-E/P 301 = Extended Temp., PDIP Range package, 20 MHz, QTP pattern #301 b) PIC16F616-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 c) PIC16HV610-E/P 301 = Extended Temp., Device: PIC16F610/616/16HV610/616, PIC16F610/616/16HV610/ 616T(1) PDIP package, 20 MHz, QTP pattern #301 d) PIC16HV616-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 e) PIC16F610-I/SL = Industrial Temp., SOIC Temperature I = -40°C to +85°C (Industrial) package, 20 MHz Range: E = -40°C to +125°C (Extended) f) PIC16F616-I/SL = Industrial Temp., SOIC H = -40°C to +150°C (High Temp.)(2) package, 20 MHz g) PIC16HV610-I/SL = Industrial Temp., SOIC package, 20 MHz Package: ML = Quad Flat No Leads (QFN) h) PIC16HV616-I/SL = Industrial Temp., SOIC P = Plastic DIP (PDIP) package, 20 MHz SL = 14-lead Small Outline (3.90 mm) (SOIC) i) PIC16F610T-E/ST Tape and Reel, Extended ST = Thin Shrink Small Outline (4.4 mm) (TSSOP) Temp., TSSOP package, 20 MHz j) PIC16F616T-E/ST Tape and Reel, Extended Temp., TSSOP package, 20 MHz Pattern: QTP, SQTP or ROM Code; Special Requirements k) PIC16HV610T-E/ST Tape and Reel, Extended (blank otherwise) Temp., TSSOP package, 20 MHz l) PIC16HV616T-E/ST Tape and Reel, Extended Temp., TSSOP package, 20 MHz m) PIC16F616 - H/SL = High Temp., SOIC pack- age, 20 MHz. Note1: T = in tape and reel for TSSOP, SOIC and QFN packages only. 2: High Temp. available for PIC16F616 only. © 2009 Microchip Technology Inc. DS41288F-page 213

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16F610-E/ML PIC16F610-E/P PIC16F610-E/SL PIC16F610-E/ST PIC16F610-I/ML PIC16F610-I/P PIC16F610- I/SL PIC16F610-I/ST PIC16F610T-I/ML PIC16F610T-I/SL PIC16F610T-I/ST PIC16F616-E/ML PIC16F616-E/P PIC16F616-E/SL PIC16F616-E/ST PIC16F616-I/ML PIC16F616-I/P PIC16F616-I/SL PIC16F616-I/ST PIC16F616T- I/ML PIC16F616T-I/SL PIC16F616T-I/ST PIC16HV610-E/ML PIC16HV610-E/P PIC16HV610-E/SL PIC16HV610- E/ST PIC16HV610-I/ML PIC16HV610-I/P PIC16HV610-I/SL PIC16HV610-I/ST PIC16HV610T-I/ML PIC16HV610T- I/SL PIC16HV610T-I/ST PIC16HV616-E/ML PIC16HV616-E/P PIC16HV616-E/SL PIC16HV616-E/ST PIC16HV616- I/ML PIC16HV616-I/P PIC16HV616-I/SL PIC16HV616-I/ST PIC16HV616T-I/ML PIC16HV616T-I/SL PIC16HV616T- I/ST PIC16F616-H/ML PIC16F616-H/SL PIC16F616-H/ST