PIC16F5X Data Sheet Flash-Based, 8-Bit CMOS Microcontroller Series © 2007 Microchip Technology Inc. DS41213D

Note the following details of the code protection feature on Microchip devices: (cid:129) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:129) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:129) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:129) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:129) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, ensure that your application meets with your specifications. PICmicro, PICSTART, PROMATE, PowerSmart, rfPIC, and MICROCHIP MAKES NO REPRESENTATIONS OR SmartShunt are registered trademarks of Microchip WARRANTIES OF ANY KIND WHETHER EXPRESS OR Technology Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor QUALITY, PERFORMANCE, MERCHANTABILITY OR and The Embedded Control Solutions Company are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41213D-page ii © 2007 Microchip Technology Inc.

PIC16F5X Flash-Based, 8-Bit CMOS Microcontroller Series High-Performance RISC CPU: Low-Power Features: (cid:129) Only 33 single-word instructions to learn (cid:129) Operating Current: (cid:129) All instructions are single cycle except for - 170μA @ 2V, 4MHz, typical program branches which are two-cycle - 15μA @ 2V, 32kHz, typical (cid:129) Two-level deep hardware stack (cid:129) Standby Current: (cid:129) Direct, Indirect and Relative Addressing modes - 500nA @ 2V, typical for data and instructions (cid:129) Operating speed: Peripheral Features: - DC – 20MHz clock speed - DC – 200ns instruction cycle time (cid:129) 12/20/32 I/O pins: (cid:129) On-chip Flash program memory: - Individual direction control - 512 x 12 on PIC16F54 - High current source/sink - 2048 x 12 on PIC16F57 (cid:129) 8-bit real-time clock/counter (TMR0) with 8-bit - 2048 x 12 on PIC16F59 programmable prescaler (cid:129) General Purpose Registers (SRAM): CMOS Technology: - 25 x 8 on PIC16F54 - 72 x 8 on PIC16F57 (cid:129) Wide operating voltage range: - 134 x 8 on PIC16F59 - Industrial: 2.0V to 5.5V - Extended: 2.0V to 5.5V Special Microcontroller Features: (cid:129) Wide temperature range: (cid:129) Power-on Reset (POR) - Industrial: -40°C to 85°C (cid:129) Device Reset Timer (DRT) - Extended: -40°C to 125°C (cid:129) Watchdog Timer (WDT) with its own on-chip (cid:129) High-endurance Flash: RC oscillator for reliable operation - 100K write/erase cycles (cid:129) Programmable Code Protection - > 40-year retention (cid:129) Power-Saving Sleep mode (cid:129) In-Circuit Serial Programming™ (ICSP™) (cid:129) Selectable oscillator options: - RC: Low-cost RC oscillator - XT: Standard crystal/resonator - HS: High-speed crystal/resonator - LP: Power-saving, low-frequency crystal (cid:129) Packages: - 18-pin PDIP and SOIC for PIC16F54 - 20-pin SSOP for PIC16F54 - 28-pin PDIP, SOIC and SSOP for PIC16F57 - 40-pin PDIP for PIC16F59 - 44-pin TQFP for PIC16F59 Program Memory Data Memory Timers Device I/O 8-bit Flash (words) SRAM (bytes) PIC16F54 512 25 12 1 PIC16F57 2048 72 20 1 PIC16F59 2048 134 32 1 © 2007 Microchip Technology Inc. DS41213D-page 1

PIC16F5X Pin Diagrams PDIP, SOIC PDIP, SOIC RA2 •1 18 RA1 T0CKI (cid:129)1 28 MCLR/VPP RA3 2 17 RA0 VDD 2 27 OSC1/CLKIN T0CKI 3 16 OSC1/CLKIN MCLR/VVPSPS 45 6F54 1154 OVDSDC2/CLKOUT VNS/CS 34 2265 ORCS7C2/CLKOUT RB0 6 C1 13 RB7/ICSPDAT N/C 5 24 RC6 RB1 7 PI 12 RB6/ICSPCLK RA0 6 7 23 RC5 RB2 8 11 RB5 RA1 7 F5 22 RC4 RB3 9 10 RB4 6 RA2 8 C1 21 RC3 RA3 9 PI 20 RC2 RB0 10 19 RC1 RB1 11 18 RC0 RB2 12 17 RB7/ICSPDAT RB3 13 16 RB6/ICSPCLK RB4 14 15 RB5 SSOP SSOP RA2 •1 20 RA1 VSS •1 28 MCLR/VPP RA3 2 19 RA0 T0CKI 2 27 OSC1/CLKIN T0CKI 3 18 OSC1/CLKIN VVDDDD 34 2265 ORCS7C2/CLKOUT MCLR/VPP 4 54 17 OSC2/CLKOUT RA0 5 24 RC6 VSS 5 F 16 VDD RA1 6 23 RC5 VSS 6 16 15 VDD RA2 7 PIC16F57 22 RC4 RB0 7 PIC 14 RB7/ICSPDAT RRAB30 89 2210 RRCC32 RB1 8 13 RB6/ICSPCLK RB1 10 19 RC1 RB2 9 12 RB5 RB2 11 18 RC0 RB3 10 11 RB4 RB3 12 17 RB7/ICSPDAT RB4 13 16 RB6/ICSPCLK VSS 14 15 RB5 PDIP, 0.600" TQFP KI RA0 (cid:129)1 40 T0CKI A3A2A1A00CE7E6E5E4DDDD RRRRTRRRRVV RA1 2 39 RE7 RA2 3 38 RE6 RA3 4 37 RE5 GND 5 36 RE4 43210987654 RB0 6 35 VDD GND 1 4444433333333 OSC1/CLKIN RB1 7 34 OSC1/CLKIN GND 2 32 OSC2/CLKOUT RB0 3 31 RD7 RB2 8 33 OSC2/CLKOUT RB1 4 30 RD6 RB3 9 32 RD7 RB2 5 PIC16F59 29 RD5 RB4 10 59 31 RD6 RB3 6 28 RD4 F RB4 7 27 RD3 RB5 11 16 30 RD5 RB5 8 26 RD2 RRBB67//IICCSSPPCDLAKT 1123 PIC 2298 RRDD43 RRBB67M//IICCCLSSRPP/CDVLAPKTP 11910 222345 RGGDNN1DD MCLR/VPP 14 27 RD2 1213141516171819202122 VDD 15 26 RD1 RC0 16 25 GND RC1 17 24 RD0 RC2 18 23 RC7 DDDDC0C1C2C3C4C5C6C7D0 RC3 19 22 RC6 VVRRRRRRRRR RC4 20 21 RC5 DS41213D-page 2 © 2007 Microchip Technology Inc.

PIC16F5X Table of Contents 1.0 General Description......................................................................................................................................................................5 2.0 Architectural Overview.................................................................................................................................................................7 3.0 Memory Organization.................................................................................................................................................................13 4.0 Oscillator Configurations............................................................................................................................................................21 5.0 Reset..........................................................................................................................................................................................23 6.0 I/O Ports.....................................................................................................................................................................................29 7.0 Timer0 Module and TMR0 Register...........................................................................................................................................33 8.0 Special Features of the CPU......................................................................................................................................................37 9.0 Instruction Set Summary............................................................................................................................................................41 10.0 Development Support.................................................................................................................................................................53 11.0 Electrical Specifications for PIC16F54/57..................................................................................................................................57 11.0 Electrical Specifications for PIC16F59 (continued)....................................................................................................................58 12.0 Packaging Information................................................................................................................................................................69 The Microchip Web Site.......................................................................................................................................................................83 Customer Change Notification Service................................................................................................................................................83 Customer Support................................................................................................................................................................................83 Reader Response................................................................................................................................................................................84 Product Identification System..............................................................................................................................................................85 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: (cid:129) Microchip’s Worldwide Web site; http://www.microchip.com (cid:129) Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. DS41213D-page 3

PIC16F5X NOTES: DS41213D-page 4 © 2007 Microchip Technology Inc.

PIC16F5X 1.0 GENERAL DESCRIPTION 1.1 Applications The PIC16F5X from Microchip Technology is a family The PIC16F5X series fits perfectly in applications rang- of low-cost, high-performance, 8-bit, fully static, Flash- ing from high-speed automotive and appliance motor based CMOS microcontrollers. It employs a RISC control to low-power remote transmitters/receivers, architecture with only 33 single-word/single-cycle pointing devices and telecom processors. The Flash instructions. All instructions are single cycle except for technology makes customizing application programs program branches which take two cycles. The (transmitter codes, motor speeds, receiver PIC16F5X delivers performance an order of magnitude frequencies, etc.) extremely fast and convenient. The higher than its competitors in the same price category. small footprint packages, for through hole or surface The 12-bit wide instructions are highly symmetrical mounting, make this microcontroller series perfect for resulting in 2:1 code compression over other 8-bit applications with space limitations. Low-cost, low- microcontrollers in its class. The easy-to-use and easy- power, high performance, ease of use and I/O flexibility to-remember instruction set reduces development time make the PIC16F5X series very versatile, even in significantly. areas where no microcontroller use has been considered before (e.g., timer functions, replacement The PIC16F5X products are equipped with special of “glue” logic in larger systems, co-processor features that reduce system cost and power require- applications). ments. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. There are four oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator. Power- saving Sleep mode, Watchdog Timer and code protec- tion features improve system cost, power and reliability. The PIC16F5X products are supported by a full-featured macro assembler, a software simulator, a low-cost devel- opment programmer and a full featured programmer. All ® the tools are supported on IBM PC and compatible machines. TABLE 1-1: PIC16F5X FAMILY OF DEVICES Features PIC16F54 PIC16F57 PIC16F59 Maximum Operation Frequency 20MHz 20MHz 20MHz Flash Program Memory (x12 words) 512 2K 2K RAM Data Memory (bytes) 25 72 134 Timer Module(s) TMR0 TMR0 TMR0 I/O Pins 12 20 32 Number of Instructions 33 33 33 Packages 18-pin DIP, SOIC; 28-pin DIP, SOIC; 40-pin DIP, 44-pin TQFP 20-pin SSOP 28-pin SSOP Note: All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect and high I/O current capability. © 2007 Microchip Technology Inc. DS41213D-page 5

PIC16F5X NOTES: DS41213D-page 6 © 2007 Microchip Technology Inc.

PIC16F5X 2.0 ARCHITECTURAL OVERVIEW The PIC16F5X device contains an 8-bit ALU and work- ing register. The ALU is a general purpose arithmetic The high performance of the PIC16F5X family can be unit. It performs arithmetic and Boolean functions attributed to a number of architectural features between data in the working register and any register commonly found in RISC microprocessors. To begin file. with, the PIC16F5X uses a Harvard architecture in The ALU is 8-bits wide and capable of addition, which program and data are accessed on separate subtraction, shift and logical operations. Unless other- buses. This improves bandwidth over traditional von wise mentioned, arithmetic operations are two's Neumann architecture where program and data are complement in nature. In two-operand instructions, fetched on the same bus. Separating program and data typically one operand is the W (working) register. The memory further allows instructions to be sized differ- other operand is either a file register or an immediate ently than the 8-bit wide data word. Instruction opcodes constant. In single operand instructions, the operand is are 12-bits wide, making it possible to have all single- either the W register or a file register. word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. The W register is an 8-bit working register used for ALU A two-stage pipeline overlaps fetch and execution of operations. It is not an addressable register. instructions. Consequently, all instructions (33) execute Depending on the instruction executed, the ALU may in a single cycle except for program branches. affect the values of the Carry (C), Digit Carry (DC) and The PIC16F54 addresses 512x12 of program Zero (Z) bits in the STATUS Register. The C and DC memory, the PIC16F57 and PIC16F59 addresses bits operate as a borrow and digit borrow out bit, 2048x12 of program memory. All program memory is respectively, in subtraction. See the SUBWF and ADDWF internal. instructions for examples. The PIC16F5X can directly or indirectly address its A simplified block diagram is shown in Figure2-1 with register files and data memory. All Special Function the corresponding device pins described in Table2-1 Registers (SFR), including the program counter, are (for PIC16F54), Table2-2 (for PIC16F57) and mapped in the data memory. The PIC16F5X has a Table2-3 (for PIC16F59). highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any reg- ister using any Addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make pro- gramming with the PIC16F5X simple, yet efficient. In addition, the learning curve is reduced significantly. © 2007 Microchip Technology Inc. DS41213D-page 7

PIC16F5X FIGURE 2-1: PIC16F5X SERIES BLOCK DIAGRAM 512 XF l1a2sh (F54) 9-11 9-11 Stack 1 T0PCinKI Configuration Word OSC1 OSC2 MCLR 2048 X 12(F57) Stack 2 “Disable” “Osc 2048 x 12(F59) PC Select” 12 Watchdog 2 Timer “Code- Protect” Oscillator/ Instruction Timing & Register Control 9 WDT WDT/TMR0 CLKOUT 12 Time-out Prescaler 8 “Sleep” Instruction 6 Decoder Option Reg. “Option” Direct Address Direct RAM From W General Address Purpose 5 Register File 8 5-7 (SRAM) 25, 72 or 134 s STATUS Bytes al er TMR0 SFR Lit 8 Data Bus W ALU 8 From W From W From W 4 8 8 4 8 8 TRISA PORTA TRISB PORTB TRISC PORTC 4 8 8 “TRIS 5” “TRIS 6” “TRIS 7” RA<3:0> RB<7:0> RC<7:0> PIC16F57/59 only From W From W 8 8 4 8 TRISE PORTE TRISD PORTD 4 8 “TRIS 9” “TRIS 8” RE<7:4> RD<7:0> PIC16F59 PIC16F59 only only DS41213D-page 8 © 2007 Microchip Technology Inc.

PIC16F5X TABLE 2-1: PIC16F54 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0 RA0 TTL CMOS Bidirectional I/O pin RA1 RA1 TTL CMOS Bidirectional I/O pin RA2 RA2 TTL CMOS Bidirectional I/O pin RA3 RA3 TTL CMOS Bidirectional I/O pin RB0 RB0 TTL CMOS Bidirectional I/O pin RB1 RB1 TTL CMOS Bidirectional I/O pin RB2 RB2 TTL CMOS Bidirectional I/O pin RB3 RB3 TTL CMOS Bidirectional I/O pin RB4 RB4 TTL CMOS Bidirectional I/O pin RB5 RB5 TTL CMOS Bidirectional I/O pin RB6/ICSPCLK RB6 TTL CMOS Bidirectional I/O pin ICSPCLK ST — Serial Programming Clock RB7/ICSPDAT RB7 TTL CMOS Bidirectional I/O pin ICSPDAT ST CMOS Serial Programming I/O T0CKI T0CKI ST — Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. MCLR/VPP MCLR ST — Active-low Reset to device. Voltage on the MCLR/VPP pin must not exceed VDD to avoid unintended entering of Programming mode. VPP HV — Programming voltage input OSC1/CLKIN OSC1 XTAL — Oscillator crystal input CLKIN ST — External clock source input OSC2/CLKOUT OSC2 — XTAL Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKOUT — CMOS In RC mode, OSC2 pin can output CLKOUT, which has 1/4 the frequency of OSC1. VDD VDD Power — Positive supply for logic and I/O pins VSS VSS Power — Ground reference for logic and I/O pins Legend: I = input I/O = input/output CMOS = CMOS output O = output — = Not Used XTAL = Crystal input/output ST = Schmitt Trigger input TTL = TTL input HV = High Voltage © 2007 Microchip Technology Inc. DS41213D-page 9

PIC16F5X TABLE 2-2: PIC16F57 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0 RA0 TTL CMOS Bidirectional I/O pin RA1 RA1 TTL CMOS Bidirectional I/O pin RA2 RA2 TTL CMOS Bidirectional I/O pin RA3 RA3 TTL CMOS Bidirectional I/O pin RB0 RB0 TTL CMOS Bidirectional I/O pin RB1 RB1 TTL CMOS Bidirectional I/O pin RB2 RB2 TTL CMOS Bidirectional I/O pin RB3 RB3 TTL CMOS Bidirectional I/O pin RB4 RB4 TTL CMOS Bidirectional I/O pin RB5 RB5 TTL CMOS Bidirectional I/O pin RB6/ICSPCLK RB6 TTL CMOS Bidirectional I/O pin ICSPCLK ST — Serial programming clock RB7/ICSPDAT RB7 TTL CMOS Bidirectional I/O pin ICSPDAT ST CMOS Serial programming I/O RC0 RC0 TTL CMOS Bidirectional I/O pin RC1 RC1 TTL CMOS Bidirectional I/O pin RC2 RC2 TTL CMOS Bidirectional I/O pin RC3 RC3 TTL CMOS Bidirectional I/O pin RC4 RC4 TTL CMOS Bidirectional I/O pin RC5 RC5 TTL CMOS Bidirectional I/O pin RC6 RC6 TTL CMOS Bidirectional I/O pin RC7 RC7 TTL CMOS Bidirectional I/O pin T0CKI T0CKI ST — Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. MCLR/VPP MCLR ST — Active-low Reset to device. Voltage on the MCLR/VPP pin must not exceed VDD to avoid unintended entering of Programming mode. VPP HV — Programming voltage input OSC1/CLKIN OSC1 XTAL — Oscillator crystal input CLKIN ST — External clock source input OSC2/CLKOUT OSC2 — XTAL Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKOUT — CMOS In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1. VDD VDD Power — Positive supply for logic and I/O pins VSS VSS Power — Ground reference for logic and I/O pins N/C N/C — — Unused, do not connect Legend: I = input I/O = input/output CMOS = CMOS output O = output — = Not Used XTAL = Crystal input/output ST= Schmitt Trigger input TTL = TTL input HV = High Voltage DS41213D-page 10 © 2007 Microchip Technology Inc.

PIC16F5X TABLE 2-3: PIC16F59 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0 RA0 TTL CMOS Bidirectional I/O pin RA1 RA1 TTL CMOS Bidirectional I/O pin RA2 RA2 TTL CMOS Bidirectional I/O pin RA3 RA3 TTL CMOS Bidirectional I/O pin RB0 RB0 TTL CMOS Bidirectional I/O pin RB1 RB1 TTL CMOS Bidirectional I/O pin RB2 RB2 TTL CMOS Bidirectional I/O pin RB3 RB3 TTL CMOS Bidirectional I/O pin RB4 RB4 TTL CMOS Bidirectional I/O pin RB5 RB5 TTL CMOS Bidirectional I/O pin RB6/ICSPCLK RB6 TTL CMOS Bidirectional I/O pin ICSPCLK ST — Serial programming clock RB7/ICSPDAT RB7 TTL CMOS Bidirectional I/O pin ICSPDAT ST CMOS Serial programming I/O RC0 RC0 TTL CMOS Bidirectional I/O pin RC1 RC1 TTL CMOS Bidirectional I/O pin RC2 RC2 TTL CMOS Bidirectional I/O pin RC3 RC3 TTL CMOS Bidirectional I/O pin RC4 RC4 TTL CMOS Bidirectional I/O pin RC5 RC5 TTL CMOS Bidirectional I/O pin RC6 RC6 TTL CMOS Bidirectional I/O pin RC7 RC7 TTL CMOS Bidirectional I/O pin RD0 RD0 TTL CMOS Bidirectional I/O pin RD1 RD1 TTL CMOS Bidirectional I/O pin RD2 RD2 TTL CMOS Bidirectional I/O pin RD3 RD3 TTL CMOS Bidirectional I/O pin RD4 RD4 TTL CMOS Bidirectional I/O pin RD5 RD5 TTL CMOS Bidirectional I/O pin RD6 RD6 TTL CMOS Bidirectional I/O pin RD7 RD7 TTL CMOS Bidirectional I/O pin RE4 RE4 TTL CMOS Bidirectional I/O pin RE5 RE5 TTL CMOS Bidirectional I/O pin RE6 RE6 TTL CMOS Bidirectional I/O pin RE7 RE7 TTL CMOS Bidirectional I/O pin T0CKI T0CKI ST — Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. MCLR/VPP MCLR ST — Active-low Reset to device. Voltage on the MCLR/VPP pin must not exceed VDD to avoid unintended entering of Programming mode. VPP HV — Programming voltage input OSC1/CLKIN OSC1 XTAL — Oscillator crystal input CLKIN ST — External clock source input OSC2/CLKOUT OSC2 — XTAL Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKOUT — CMOS In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1. VDD VDD Power — Positive supply for logic and I/O pins VSS VSS Power — Ground reference for logic and I/O pins Legend: I = input I/O = input/output CMOS = CMOS output O = output — = Not Used XTAL = Crystal input/output ST= Schmitt Trigger input TTL = TTL input HV = High Voltage © 2007 Microchip Technology Inc. DS41213D-page 11

PIC16F5X 2.1 Clocking Scheme/Instruction 2.2 Instruction Flow/Pipelining Cycle An instruction cycle consists of four Q cycles (Q1, Q2, The clock input (OSC1/CLKIN pin) is internally divided Q3 and Q4). The instruction fetch and execute are by four to generate four non-overlapping quadrature pipelined such that fetch takes one instruction cycle, clocks, namely Q1, Q2, Q3 and Q4. Internally, the while decode and execute takes another instruction Program Counter (PC) is incremented every Q1 and cycle. However, due to the pipelining, each instruction the instruction is fetched from program memory and effectively executes in one cycle. If an instruction latched into the instruction register in Q4. It is decoded causes the Program Counter to change (e.g., GOTO), and executed during the following Q1 through Q4. The then two cycles are required to complete the instruction clocks and instruction execution flow are shown in (Example2-1). Figure2-2 and Example2-1. A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the instruction register in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 2-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC + 1 PC + 2 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC - 1) Fetch INST (PC + 1) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 1) EXAMPLE 2-1: INSTRUCTION PIPELINE FLOW 1. MOVLW H'55' Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. DS41213D-page 12 © 2007 Microchip Technology Inc.

PIC16F5X 3.0 MEMORY ORGANIZATION FIGURE 3-2: PIC16F57/PIC16F59 PROGRAM MEMORY MAP PIC16F5X memory is organized into program memory AND STACK and data memory. For the PIC16F57 and PIC16F59, which have more than 512 words of program memory, PC<10:0> a paging scheme is used. Program memory pages are 11 accessed using one or two STATUS register bits. For CALL, RETLW the PIC16F57 and PIC16F59, which have a data mem- Stack Level 1 ory register file of more than 32 registers, a banking Stack Level 2 scheme is used. Data memory banks are accessed using the File Selection Register (FSR). 000h On-chip Program 0FFh Memory (Page 0) 3.1 Program Memory Organization 100h 1FFh The PIC16F54 has a 9-bit Program Counter (PC) 200h capable of addressing a 512 x 12 program memory On-chip Program sapna 1c1e- b(Fiti gPuroregr3a-m1) .C Tohuen PteIrC c1a6pFa5b7le a onfd a PdIdCr1e6ssFi5n9g haa 2vKe emoryce Memory (Page 1) 23F00Fhh x 12 program memory space (Figure3-2). Accessing a Mpa 3FFh location above the physically implemented address will ser S 400h U On-chip Program cause a wraparound. 4FFh Memory (Page 2) 500h A NOP at the Reset vector location will cause a restart at location 000h. The Reset vector for the PIC16F54 is 5FFh 600h at 1FFh. The Reset vector for the PIC16F57 and On-chip Program PIC16F59 is at 7FFh. See Section3.5 “Program 6FFh Memory (Page 3) Counter” for additional information using CALL and 700h GOTO instructions. Reset Vector 7FFh FIGURE 3-1: PIC16F54 PROGRAM MEMORY MAP AND STACK PC<8:0> 9 CALL, RETLW Stack Level 1 Stack Level 2 000h y or On-chip emce Program 0FFh er MSpa Memory 100h s U Reset Vector 1FFh © 2007 Microchip Technology Inc. DS41213D-page 13

PIC16F5X 3.2 Data Memory Organization 3.2.1 GENERAL PURPOSE REGISTER FILE Data memory is composed of registers or bytes of RAM. Therefore, data memory for a device is specified The register file is accessed either directly or indirectly by its register file. The register file is divided into two through the File Select Register (FSR). The FSR functional groups: Special Function Registers (SFR) register is described in Section3.7 “Indirect Data and General Purpose Registers (GPR). Addressing; INDF and FSR Registers”. The Special Function Registers include the TMR0 FIGURE 3-3: PIC16F54 REGISTER FILE register, the Program Counter (PC), the STATUS regis- MAP ter, the I/O registers (ports) and the File Select Register (FSR). In addition, Special Purpose Registers are used File Address to control the I/O port configuration and prescaler 00h INDF(1) options. 01h TMR0 The General Purpose Registers are used for data and 02h PCL control information under command of the instructions. 03h STATUS For the PIC16F54, the register file is composed of 7 Special Function Registers and 25 General Purpose 04h FSR Registers (Figure3-3). 05h PORTA For the PIC16F57, the register file is composed of 8 06h PORTB Special Function Registers, 8 General Purpose 07h Registers and 64 additional General Purpose Registers that may be addressed using a banking scheme (Figure3-4). General Purpose For the PIC16F59, the register file is composed of 10 Registers Special Function Registers, 6 General Purpose Registers and 128 additional General Purpose Registers that may be addressed using a banking 1Fh scheme (Figure3-5). Note 1: Not a physical register. See Section3.7 “Indirect Data Addressing; INDF and FSR Registers”. FIGURE 3-4: PIC16F57 REGISTER FILE MAP FSR<6:5> 00 01 10 11 File Address 00h INDF(1) 20h 40h 60h 01h TMR0 02h PCL 03h STATUS 04h FSR Addresses map back to 05h PORTA addresses in Bank 0. 06h PORTB 07h POR TC 08h General Purpose 0Fh Registers 2Fh 4Fh 6Fh 10h 30h 50h 70h General General General General Purpose Purpose Purpose Purpose Registers Registers Registers Registers 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: Not a physical register. See Section3.7 “Indirect Data Addressing; INDF and FSR Registers”. DS41213D-page 14 © 2007 Microchip Technology Inc.

PIC16F5X FIGURE 3-5: PIC16F59 REGISTER FILE MAP FSR<7:5> 000 001 010 011 100 101 110 111 File Address 00h INDF(1) 20h 40h 60h 80h A0h C0h E0h 01h TMR0 02h PCL 03h STATUS 04h FSR Addresses map back to addresses in Bank 0. 05h PORTA 06h PORTB 07h PORTC 08h PORTD 09h PORTE 0Ah General Purpose Registers 0Fh 2Fh 4Fh 6Fh 8Fh AFh CFh EFh 10h 30h 50h 70h 90h B0h D0h F0h General General General General General General General General Purpose Purpose Purpose Purpose Purpose Purpose Purpose Purpose Registers Registers Registers Registers Registers Registers Registers Registers 1Fh 3Fh 5Fh 7Fh 9Fh BFh DFh FFh Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Note 1: Not a physical register. © 2007 Microchip Technology Inc. DS41213D-page 15

PIC16F5X 3.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFR) are registers used by the CPU and peripheral functions to control the operation of the device (Table3-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 3-1: SPECIAL FUNCTION REGISTER SUMMARY Value on Details Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on on Page Reset N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC, TRISD, TRISE) 1111 1111 29 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT --11 1111 18 prescaler 00h INDF Uses contents of FSR to address data memory (not a physical xxxx xxxx 20 register) 01h TMR0 Timer0 Module Register xxxx xxxx 34 02h PCL(1) Low order 8 bits of PC 1111 1111 19 03h STATUS PA2 PA1 PA0 TO PD Z DC C 0001 1xxx 17 04h FSR(3) Indirect data memory Address Pointer 111x xxxx 20 04h FSR(4) Indirect data memory Address Pointer 1xxx xxxx 20 04h FSR(5) Indirect data memory Address Pointer xxxx xxxx 20 05h PORTA(6) — — — — RA3 RA2 RA1 RA0 ---- xxxx 29 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 29 07h PORTC(2) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 29 08h PORTD(7) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 29 09h PORTE(6), (7) RE7 RE6 RE5 RE4 — — — — xxxx ---- 29 Legend: Shaded cells = unimplemented or unused, – = unimplemented, read as ‘0’ (if applicable), x = unknown, u = unchanged Note 1: The upper byte of the Program Counter is not directly accessible. See Section3.5 “Program Counter” for an explanation of how to access these bits. 2: File address 07h is a General Purpose Register on the PIC16F54. 3: PIC16F54 only. 4: PIC16F57 only. 5: PIC16F59 only. 6: Unimplemented bits are read as ‘0’s. 7: File address 08h and 09h are General Purpose Registers on the PIC16F54 and PIC16F57. DS41213D-page 16 © 2007 Microchip Technology Inc.

PIC16F5X 3.3 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register This register contains the arithmetic status of the ALU, as 000u u1uu (where u = unchanged). the Reset status and the page preselect bits for Therefore, it is recommended that only BCF, BSF, program memories larger than 512 words. MOVWF and SWAPF instructions be used to alter the The STATUS register can be the destination for any STATUS register because these instructions do not instruction, as with any other register. If the STATUS affect the Z, DC or C bits from the STATUS register. For register is the destination for an instruction that affects other instructions which do affect Status bits, see the Z, DC or C bits, then the write to these three bits is Section9.0 “Instruction Set Summary”. disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 3-1: STATUS REGISTER (ADDRESS: 03h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x PA2 PA1 PA0 TO PD Z DC C bit 7 bit 0 bit 7 PA2: Reserved, do not use Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. bit 6-5 PA<1:0>: Program Page Preselect bits (PIC16F57/PIC16F59) 00 = Page 0 (000h-1FFh) 01 = Page 1 (200h-3FFh) 10 = Page 2 (400h-5FFh) 11 = Page 3 (600h-7FFh) Each page is 512 words. Using the PA<1:0> bits as general purpose read/write bits in devices which do not use them for program page preselect is not recommended. This may affect upward compatibility with future products. bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry to the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow to the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF RRF or RLF 1 = A carry occurred 1 = A borrow did not occur Loaded with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2007 Microchip Technology Inc. DS41213D-page 17

PIC16F5X 3.4 Option Register The Option register is a 6-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the Option register. A Reset sets the Option<5:0> bits. REGISTER 3-2: OPTION REGISTER U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1 — — T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0 PS<2:0>: Prescaler rate select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41213D-page 18 © 2007 Microchip Technology Inc.

PIC16F5X 3.5 Program Counter FIGURE 3-7: LOADING OF PC BRANCH INSTRUCTIONS – PIC16F57 As a program instruction is executed, the Program AND PIC16F59 Counter (PC) will contain the address of the next program instruction to be executed. The PC value is GOTO Instruction increased by one, every instruction cycle, unless an 10 9 8 7 0 instruction changes the PC. PC PCL For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is Instruction Word mapped to PC<7:0> (Figure3-6 and Figure3-7). 2 PA<1:0> For the PIC16F57 and PIC16F59, a page number must 7 0 be supplied as well. Bit 5 and bit 6 of the STATUS reg- ister provide page information to bit 9 and bit 10 of the Status PC (Figure3-6 and Figure3-7). For a CALL instruction, or any instruction where the CALL or Modify PCL Instruction PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> 10 9 8 7 0 does not come from the instruction word, but is always PC PCL cleared (Figure3-6 and Figure3-7). Instructions where the PCL is the destination or modify PCL instructions, include MOVWF PCL, ADDWF PCL, Instruction Word and BSF PCL,5. Reset to ‘0’ For the PIC16F57 and PIC16F59, a page number 2 PA<1:0> 7 0 again must be supplied. Bit 5 and bit 6 of the STATUS register provide page information to bit 9 and bit 10 of the PC (Figure3-6 and Figure3-7). Status Note: Because PC<8> is cleared in the CALL instruction or any modified PCL instruc- 3.5.1 PAGING CONSIDERATIONS tion, all subroutine calls or computed PIC16F57 AND PIC16F59 jumps are limited to the first 256 locations If the PC is pointing to the last address of a selected of any program memory page (512 words memory page, when it increments, it will cause the pro- long). gram to continue in the next higher page. However, the page preselect bits in the STATUS register will not be FIGURE 3-6: LOADING OF PC BRANCH updated. Therefore, the next GOTO, CALL or MODIFY INSTRUCTIONS – PIC16F54 PCL instruction will send the program to the page specified by the page preselect bits (PA0 or PA<1:0>). GOTO Instruction For example, a NOP at location 1FFh (page 0) 8 7 0 increments the PC to 200h (page 1). A GOTO xxx at PC PCL 200h will return the program to address xxh on page 0 (assuming that PA<1:0> are clear). Instruction Word To prevent this, the page preselect bits must be updated under program control. CALL or Modify PCL Instruction 3.5.2 EFFECTS OF RESET 8 7 0 The PC is set upon a Reset, which means that the PC PC PCL addresses the last location in the last page (i.e., the Reset vector). Reset to '0' Instruction Word The STATUS register page preselect bits are cleared upon a Reset, which means that page 0 is preselected. Therefore, upon a Reset, a GOTO instruction at the Reset vector location will automatically cause the program to jump to page0. © 2007 Microchip Technology Inc. DS41213D-page 19

PIC16F5X 3.6 Stack EXAMPLE 3-1: INDIRECT ADDRESSING The PIC16F54 device has a 9-bit wide, two-level hard- (cid:129) Register file 08 contains the value 10h ware PUSH/POP stack. The PIC16F57 and PIC16F59 (cid:129) Register file 09 contains the value 0Ah devices have an 11-bit wide, two-level hardware (cid:129) Load the value 08 into the FSR register PUSH/POP stack. (cid:129) A read of the INDF register will return the value A CALL instruction will PUSH the current value of stack 1 of10h into stack 2 and then PUSH the current program counter (cid:129) Increment the value of the FSR register by one value, incremented by one, into stack level 1. If more than (FSR = 09h) two sequential CALL’s are executed, only the most recent (cid:129) A read of the INDF register now will return the two return addresses are stored. value of 0Ah. A RETLW instruction will POP the contents of stack level Reading INDF itself indirectly (FSR = 0) will produce 1 into the program counter and then copy stack level 2 00h. Writing to the INDF register indirectly results in a contents into level 1. If more than two sequential no-operation (although Status bits may be affected). RETLW’s are executed, the stack will be filled with the address previously stored in level 2. A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example3-2. Note: The Wregister will be loaded with the EXAMPLE 3-2: HOW TO CLEAR RAM literal value specified in the instruction. USING INDIRECT This is particularly useful for the ADDRESSING implementation of data look-up tables MOVLW H'10' ;initialize pointer within the program memory. MOVWF FSR ;to RAM For the RETLW instruction, the PC is loaded with the NEXT CLRF INDF ;clear INDF Register Top-of-Stack (TOS) contents. All of the devices cov- INCF FSR,F ;inc pointer BTFSC FSR,4 ;all done? ered in this data sheet have a two-level stack. The GOTO NEXT ;NO, clear next stack has the same bit width as the device PC, there- CONTINUE fore, paging is not an issue when returning from a sub- : ;YES, continue routine. The FSR is either a 5-bit (PIC16F54), 7-bit (PIC16F57) 3.7 Indirect Data Addressing; INDF or 8-bit (PIC16F59) wide register. It is used in conjunc- and FSR Registers tion with the INDF register to indirectly address the data memory area. The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is The FSR<4:0> bits are used to select data memory contained in the FSR Register (FSR is a pointer). This addresses 00h to 1Fh. is indirect addressing. PIC16F54: This does not use banking. FSR<7:5> bits are unimplemented and read as‘1’s. PIC16F57: FSR<7> bit is unimplemented and read as ‘1’. FSR<6:5> are the bank select bits and are used to select the bank to be addressed (00 = Bank 0, 01 = Bank 1, 10 = Bank 2, 11 = Bank 3). PIC16F59: FSR<7:5> are the bank select bits and are used to select the bank to be addressed (000 = Bank0, 001 = Bank 1, 010 = Bank 2, 011 = Bank 3, 100 = Bank4, 101 = Bank 5, 110 = Bank 6, 111 = Bank 7). Note: A CLRF FSR instruction may not result in an FSR value of 00h if there are unimplemented bits present in the FSR. DS41213D-page 20 © 2007 Microchip Technology Inc.

PIC16F5X 4.0 OSCILLATOR TABLE 4-1: CAPACITOR SELECTION FOR CONFIGURATIONS CERAMIC RESONATORS Osc Resonator Cap. Range Cap. Range 4.1 Oscillator Types Type Freq. C1 C2 XT 455kHz 68-100pF 68-100pF The PIC16F5X devices can be operated in four differ- 2.0MHz 15-33pF 15-33pF ent oscillator modes. The user can program two Con- 4.0MHz 10-22pF 10-22pF figuration bits (FOSC1:FOSC0) to select one of these four modes: HS 8.0MHz 10-22pF 10-22pF 16.0MHz 10pF 10pF (cid:129) LP: Low-power Crystal These values are for design guidance only. Since (cid:129) XT: Crystal/Resonator each resonator has its own characteristics, the user (cid:129) HS: High-speed Crystal/Resonator should consult the resonator manufacturer for (cid:129) RC: Resistor/Capacitor appropriate values of external components. 4.2 Crystal Oscillator/Ceramic TABLE 4-2: CAPACITOR SELECTION FOR Resonators CRYSTAL OSCILLATOR In XT, LP or HS modes, a crystal or ceramic resonator Osc Crystal Cap.Range Cap. Range is connected to the OSC1/CLKIN and OSC2/CLKOUT Type Freq. C1 C2 pins to establish oscillation (Figure4-1). The LP 32kHz(1) 15pF 15pF PIC16F5X oscillator design requires the use of a XT 100kHz 15-30pF 200-300pF parallel cut crystal. Use of a series cut crystal may give 200kHz 15-30pF 100-200pF a frequency outside of the crystal manufacturers 455kHz 15-30pF 15-100pF specifications. When in XT, LP or HS modes, the 1MHz 15-30pF 15-30pF device can have an external clock source drive the 2MHz 15pF 15pF OSC1/CLKIN pin (Figure4-2). 4MHz 15pF 15pF FIGURE 4-1: CRYSTAL/CERAMIC HS 4MHz 15pF 15pF RESONATOR OPERATION 8MHz 15pF 15pF 20MHz 15pF 15pF (HS, XT OR LP OSC CONFIGURATION) Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended. C1(1) OSC1 PIC16F5X These values are for design guidance only. Rs may be required in HS mode, as well as XT mode, to Sleep avoid overdriving crystals with low drive level specifi- XTAL RF(3) cations. Since each crystal has its own characteris- To internal tics, the user should consult the crystal manufacturer OSC2 logic for appropriate values of external components. RS(2) C2(1) Note 1: See Capacitor Selection tables for Note1: This device has been designed to perform recommended values of C1 and C2. to the parameters of its data sheet. It has 2: A series resistor (RS) may be required. been tested to an electrical specification 3: RF varies with the Oscillator mode chosen designed to determine its conformance (approx. value = 10MΩ). with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its FIGURE 4-2: EXTERNAL CLOCK INPUT earlier version. These differences may OPERATION (HS, XT OR LP cause this device to perform differently in OSC CONFIGURATION) your application than the earlier version of this device. Clock from OSC1 ext. system 2: The user should verify that the device PIC16F5X oscillator starts and performs as Open OSC2 expected. Adjusting the loading capacitor values and/or the Oscillator mode may be required. © 2007 Microchip Technology Inc. DS41213D-page 21

PIC16F5X 4.3 External Crystal Oscillator Circuit FIGURE 4-4: EXTERNAL SERIES RESONANT CRYSTAL Either a pre-packaged oscillator or a simple oscillator OSCILLATOR CIRCUIT circuit with TTL gates can be used as an external (USING XT, HS OR LP crystal oscillator circuit. Pre-packaged oscillators OSCILLATOR MODE) provide a wide operating range and better stability. A well designed crystal oscillator will provide good perfor- To Other mance with TTL gates. Two types of crystal oscillator 330K 330K Devices circuits can be used: one with parallel resonance or one 74AS04 74AS04 74AS04 PIC16F5X with series resonance. CLKIN Figure4-3 shows an implementation example of a 0.1 μF parallel resonant oscillator circuit. The circuit is XTAL Open OSC2 designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180° phase shift that a parallel oscillator requires. The 4.7kΩ resistor provides the negative feedback for stability. 4.4 RC Oscillator The 10kΩ potentiometers bias the 74AS04 in the linear region. This circuit could be used for external For applications where precise timing is not a require- oscillator designs. ment, the RC oscillator option is available. The operation and functionality of the RC oscillator is FIGURE 4-3: EXTERNAL PARALLEL dependent upon a number of variables. The RC oscillator frequency is a function of: RESONANT CRYSTAL OSCILLATOR CIRCUIT (cid:129) Supply voltage (USING XT, HS OR LP (cid:129) Resistor (R EXT) and capacitor (CEXT) values OSCILLATOR MODE) (cid:129) Operating temperature. +5V The oscillator frequency will vary from unit to unit due To Other Devices to normal process parameter variation. The difference 10k in lead frame capacitance between package types will 4.7k 74AS04 PIC16F5X also affect the oscillation frequency, especially for low 74AS04 CLKIN CEXT values. The user also needs to account for the tolerance of the external R and C components. Open OSC2 Figure4-5 shows how the R/C combination is 10k connected. XTAL The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin and can be used for test 10k purposes or to synchronize other logic. 20 pF 20 pF FIGURE 4-5: RC OSCILLATOR MODE VDD Figure4-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverters perform a 360° REXT Internal OSC1 clock phase shift in a series resonant oscillator circuit. The 330kΩ resistors provide the negative feedback to bias the inverters in their linear region. N CEXT PIC16F5X VSS OSC2/CLKOUT FOSC/4 DS41213D-page 22 © 2007 Microchip Technology Inc.

PIC16F5X 5.0 RESET The TO and PD bits (STATUS <4:3>) are set or cleared depending on the different Reset conditions (Table5-1). The PIC16F5X devices may be reset in one of the These bits may be used to determine the nature of the following ways: Reset. (cid:129) Power-on Reset (POR) Table5-3 lists a full description of Reset states of all (cid:129) MCLR Reset (normal operation) registers. Figure5-1 shows a simplified block diagram (cid:129) MCLR Wake-up Reset (from Sleep) of the on-chip Reset circuit. (cid:129) WDT Reset (normal operation) (cid:129) WDT Wake-up Reset (from Sleep) Table5-1 shows these Reset conditions for the PCL and STATUS registers. Some registers are not affected in any Reset condition. Their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on Power-on Reset (POR), MCLR or WDT Reset. A MCLR or WDT wake-up from Sleep also results in a device Reset and not a continuation of operation before Sleep. TABLE 5-1: STATUS BITS AND THEIR SIGNIFICANCE Condition TO PD Power-on Reset 1 1 MCLR Reset (normal operation) u u MCLR Wake-up (from Sleep) 1 0 WDT Reset (normal operation) 0 1 WDT Wake-up (from Sleep) 0 0 Legend: u = unchanged, x = unknown, — = unimplemented read as ‘0’. TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH RESET Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCLR and POR WDT Reset 03h STATUS PA2 PA1 PA0 TO PD Z DC C 0001 1xxx 000q quuu Legend: u = unchanged, x = unknown, q = see Table5-1 for possible values. © 2007 Microchip Technology Inc. DS41213D-page 23

PIC16F5X TABLE 5-3: RESET CONDITIONS FOR ALL REGISTERS Register Address Power-on Reset MCLR or WDT Reset W N/A xxxx xxxx uuuu uuuu TRIS N/A 1111 1111 1111 1111 OPTION N/A --11 1111 --11 1111 INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000q quuu FSR(1) 04h 111x xxxx 111u uuuu FSR(2) 04h 1xxx xxxx 1uuu uuuu FSR(3) 04h xxxx xxxx uuuu uuuu PORTA 05h ---- xxxx ---- uuuu PORTB 06h xxxx xxxx uuuu uuuu PORTC(4) 07h xxxx xxxx uuuu uuuu PORTD(5) 08h xxxx xxxx uuuu uuuu PORTE(5) 09h xxxx ---- uuuu ---- Legend: u = unchanged, x = unknown, – = unimplemented, read as ‘0’, q = see tables in Table5-1 for possible values. Note 1: PIC16F54 only. 2: PIC16F57 only. 3: PIC16F59 only. 4: General purpose register file on PIC16F54. 5: General purpose register file on PIC16F54 and PIC16F57. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD POR MCLR/VPP MCLR S Filter R Q WDT Chip Reset Module DRT Reset DS41213D-page 24 © 2007 Microchip Technology Inc.

PIC16F5X 5.1 Power-on Reset (POR) FIGURE 5-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The PIC16F5X family of devices incorporate on-chip SLOW VDD POWER-UP) Power-on Reset (POR) circuitry which provides an internal chip Reset for most power-up situations. To VDD VDD use this feature, the user merely ties the MCLR/VPP pin to VDD. A simplified block diagram of the on-chip D R Power-on Reset circuit is shown in Figure5-1. R1 The Power-on Reset circuit and the Device Reset MCLR Timer (Section5.2) circuit are closely related. On C PIC16F5X power-up, the Reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically (cid:129) External Power-on Reset circuit is required 18ms, it will reset the Reset latch and thus end the on- only if VDD power-up is too slow. The diode D chip Reset signal. helps discharge the capacitor quickly when A power-up example where MCLR is not tied to VDD is VDD powers down. shown in Figure5-3. VDD is allowed to rise and stabilize (cid:129) R < 40k Ω is recommended to make sure that before bringing MCLR high. The chip will actually come voltage drop across R does not violate the out of Reset TDRT msec after MCLR goes high. device electrical specification. In Figure5-4, the on-chip Power-on Reset feature is (cid:129) R1 = 100 Ω to 1kΩ will limit any current being used (MCLR and VDD are tied together). The VDD flowing into MCLR from external capacitor C is stable before the start-up timer times out and there is in the event of MCLR pin breakdown due to no problem in getting a proper Reset. However, Electrostatic Discharge (ESD) or Electrical Figure5-5 depicts a problem situation where VDD rises Overstress (EOS). too slowly. The time between when the DRT senses a high on the MCLR/VPP pin and the MCLR/VPP pin (and VDD) actually reach their full value is too long. In this sit- uation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not ensured to function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure5-2). Note1: When the device starts normal operation (exits the Reset condition), device operating parameters (voltage, fre- quency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. 2: The POR is disabled when the device is in Sleep. For more information on the PIC16F5X POR, see Application Note AN522, “Power-Up Considerations” at www.microchip.com. © 2007 Microchip Technology Inc. DS41213D-page 25

PIC16F5X FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD) VDD MCLR Internal POR TDRT DRT Time-out Internal Reset FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR Internal POR TDRT DRT Time-out Internal Reset FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note : When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min. DS41213D-page 26 © 2007 Microchip Technology Inc.

PIC16F5X 5.2 Device Reset Timer (DRT) FIGURE 5-7: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 The Device Reset Timer (DRT) provides an 18ms nominal time-out on Reset regardless of the oscillator VDD mode used. The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the VDD DRT is active. The DRT delay allows VDD to rise above R1 VDD min. and for the chosen oscillator to stabilize. Q1 Oscillator circuits, based on crystals or ceramic resona- MCLR tors, require a certain time after power-up to establish R2 40k a stable oscillation. The on-chip DRT keeps the device PIC16F5X in a Reset condition for approximately 18ms after the voltage on the MCLR/VPP pin has reached a logic high (VIH) level. Thus, external RC networks connected to the MCLR input are not required in most cases, allowing for savings in cost-sensitive and/or space This brown-out circuit is less expensive, although restricted applications. less accurate. Transistor Q1 turns off when VDD is The device Reset time delay will vary from chip-to-chip below a certain level such that: due to VDD, temperature and process variation. See R1 AC parameters for details. VDD (cid:129) = 0.7V R1 + R2 The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake the PIC16F5X from Sleep mode automatically. FIGURE 5-8: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3 5.3 Reset on Brown-Out VDD A Brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then VDD recovers. The device should be reset in the event of a VDD Bypass Capacitor Brown-out. MCP809 To reset PIC16F5X devices when a Brown-out occurs, external Brown-out protection circuits may be built, as RST shown in Figure5-6, Figure5-7 and Figure5-8. VSS MCLR PIC16F5X FIGURE 5-6: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 This brown-out protection circuit employs Microchip Technology’s MCP809 microcontroller supervisor. The MCP8XX and MCP1XX families VDD of supervisors provide push-pull and open collec- tor outputs with both “active-high and active-low” VDD Reset pins. There are 7 different trip point 33k selections to accommodate 5V and 3V systems. Q1 10k MCLR 40k PIC16F5X This circuit will activate Reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). © 2007 Microchip Technology Inc. DS41213D-page 27

PIC16F5X NOTES: DS41213D-page 28 © 2007 Microchip Technology Inc.

PIC16F5X 6.0 I/O PORTS 6.6 TRIS Registers As with any other register, the I/O registers can be writ- The output driver control registers are loaded with the ten and read under program control. However, read contents of the W register by executing the TRIS f instructions (e.g., MOVF PORTB, W) always read the I/O instruction. A ‘1’ from a TRIS register bit puts the corre- pins independent of the pin’s Input/Output modes. On sponding output driver in a High-Impedance (Input) Reset, all I/O ports are defined as input (inputs are at mode. A ‘0’ puts the contents of the output data latch high-impedance), since the I/O control registers on the selected pins, enabling the output buffer. (TRISA, TRISB, TRISC, TRISD and TRISE) are all set. Note: A read of the ports reads the pins, not the output data latches. That is, if an output 6.1 PORTA driver on a pin is enabled and driven high, but the external system is holding it low, a PORTA is a 4-bit I/O register. Only the low order 4 bits read of the port will indicate that the pin is are used (PORTA<3:0>). The high order 4 bits low. (PORTA<7:4>) are unimplemented and read as ‘0’s. The TRIS registers are “write-only” and are set (output 6.2 PORTB drivers disabled) upon Reset. PORTB is an 8-bit I/O register (PORTB<7:0>). 6.7 I/O Interfacing 6.3 PORTC The equivalent circuit for an I/O port pin is shown in Figure6-1. All ports may be used for both input and PORTC is an 8-bit I/O register (PORTC<7:0>) for the output operation. For input operations, these ports are PIC16F57 and PIC16F59. non-latching. Any input must be present until read by PORTC is a General Purpose Register for the an input instruction (e.g., MOVF PORTB, W). The out- PIC16F54. puts are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the 6.4 PORTD corresponding direction control bit (in TRISA, TRISB, TRISC, TRISD and TRISE) must be cleared (= 0). For PORTD is an 8-bit I/O register (PORTD<7:0>) for the use as an input, the corresponding TRIS bit must be PIC16F59. set. Any I/O pin can be programmed individually as input or output. PORTD is a General Purpose Register for the PIC16F54 and PIC16F57. FIGURE 6-1: EQUIVALENT CIRCUIT 6.5 PORTE FOR A SINGLE I/O PIN Data PORTE is an 4-bit I/O register for the PIC16F59. Only Bus D Q the high order 4 bits are used (PORTE<7:4>). The low Data order 4 bits (PORTE<3:0>) are unimplemented and VDD read as ‘0’s. WPoRrt Latch VDD CK Q P PORTE is a General Purpose Register for the PIC16F54 and PIC16F57. I/O W N pin Reg D Q TRIS VSS VSS Latch TRIS ‘f’ CK Q Reset Q D E RD Port © 2007 Microchip Technology Inc. DS41213D-page 29

PIC16F5X TABLE 6-1: SUMMARY OF PORT REGISTERS Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on MCLR and Reset WDT Reset N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC, TRISD and TRISE) 1111 1111 1111 1111 05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 07h PORTC(1) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 08h PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 09h PORTE(2) RE7 RE6 RE5 RE4 — — — — xxxx ---- uuuu ---- Legend: Shaded cells = unimplemented, read as ‘0’, – = unimplemented, read as ‘0’, x = unknown, u = unchanged Note 1: File address 07h is a General Purpose Register on the PIC16F54. 2: File address 08h and 09h are General Purpose Registers on the PIC16F54 and PIC16F57. DS41213D-page 30 © 2007 Microchip Technology Inc.

PIC16F5X 6.8 I/O Programming Considerations EXAMPLE 6-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O 6.8.1 BIDIRECTIONAL I/O PORTS PORT Some instructions operate internally as read followed ;Initial PORT Settings by write operations. The BCF and BSF instructions, for ;PORTB<7:4> Inputs example, read the entire port into the CPU, execute the ;PORTB<3:0> Outputs bit operation and re-write the result. Caution must be ;PORTB<7:6> have external pull-ups and are used when these instructions are applied to a port ;not connected to other circuitry ; where one or more pins are used as input/outputs. For ; PORT latch PORT pins example, a BSF operation on bit 5 of PORTB will cause ; --------------------- all eight bits of PORTB to be read into the CPU, bit 5 to BCF PORTB, 7 ;01pp pppp 11pp pppp be set and the PORTB value to be written to the output BCF PORTB, 6 ;10pp pppp 11pp pppp latches. If another bit of PORTB is used as a MOVLW H'3F' ; bidirectional I/O pin (say bit ‘0’), and it is defined as an TRIS PORTB ;10pp pppp 10pp pppp input at this time, the input signal present on the pin ; itself would be read into the CPU and rewritten to the ;Note that the user may have expected the data latch of this particular pin, overwriting the previous pin content. As long as the pin stays in the Input mode, no ;values to be 00pp pppp. The 2nd BCF caused ;RB7 to be latched as the pin value (High). problem occurs. However, if bit ‘0’ is switched into Output mode later on, the content of the data latch may now be unknown. 6.8.2 SUCCESSIVE OPERATIONS ON I/O PORTS Example6-1 shows the effect of two sequential read- modify-write instructions (e.g., BCF, BSF, etc.) on an The actual write to an I/O port happens at the end of an I/O port. instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (see A pin actively outputting a high or a low should not be Figure6-2). Therefore, care must be exercised if a write driven from external devices at the same time in order followed by a read operation is carried out on the same to change the level on this pin (“wired-or”, “wired-and”). I/O port. The sequence of instructions should allow the pin The resulting high output currents may damage the voltage to stabilize (load dependent) before the next chip. instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 6-2: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 PC + 2 PC + 3 Instruction fetched MOVWF PORTB MOVF PORTB,W NOP NOP This example shows a write RB<7:0> to PORTB followed by a read from PORTB. Port pin Port pin written here sampled here MOVWF PORTB MOVF PORTB,W NOP Instruction (Write to (Read executed PORTB) PORTB) Fetch INST (PC) Execute INST (PC - 1) Fetch INST (PC + 1) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 1) Fetch INST (PC + 3) Execute INST (PC + 2) © 2007 Microchip Technology Inc. DS41213D-page 31

PIC16F5X NOTES: DS41213D-page 32 © 2007 Microchip Technology Inc.

PIC16F5X 7.0 TIMER0 MODULE AND TMR0 Counter mode is selected by setting the T0CS bit REGISTER (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The The Timer0 module has the following features: incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit (cid:129) 8-bit Timer/Counter register, TMR0 selects the rising edge. Restrictions on the external - Readable and writable clock input are discussed in detail in Section7.1 (cid:129) 8-bit software programmable prescaler “Using Timer0 with an External Clock”. (cid:129) Internal or external clock select Note: The prescaler may be used by either the - Edge select for external clock Timer0 module or the Watchdog Timer, but Figure7-1 is a simplified block diagram of the Timer0 not both. module. The prescaler assignment is controlled in software by Timer mode is selected by clearing the T0CS bit the control bit PSA (OPTION<3>). Clearing the PSA bit (OPTION<5>). In Timer mode, the Timer0 module will will assign the prescaler to Timer0. The prescaler is not increment every instruction cycle (without prescaler). If readable or writable. When the prescaler is assigned to TMR0 register is written, the increment is inhibited for the Timer0 module, prescale values of 1:2, 1:4,..., the following two cycles (Figure7-2 and Figure7-3). 1:256 are selectable. Section7.2 “Prescaler” details The user can work around this by writing an adjusted the operation of the prescaler. value to the TMR0 register. A summary of registers associated with the Timer0 module is found in Table7-1. FIGURE 7-1: TIMER0 BLOCK DIAGRAM Data Bus FOSC/4 0 PSout 8 1 Sync with 1 Internal TMR0 Reg Clocks T0CKI Programmable 0 PSout pin Prescaler(2) Sync T0SE(1) (2 cycle delay) 3 PS2, PS1, PS0(1) PSA(1) T0CS(1) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in Section3.4 “Option Register”. 2: The prescaler is shared with the Watchdog Timer (Figure7-5). FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC - 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W Fetch Timer0 T0 T0 + 1 T0 + 2 NT0 NT0 NT0 NT0 + 1 NT0 + 2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 © 2007 Microchip Technology Inc. DS41213D-page 33

PIC16F5X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2 PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC - 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,WMOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 NT0 NT0 + 1 Instruction Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on MCLR and Reset WDT Reset 01h TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu N/A OPTION — — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111 Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged. DS41213D-page 34 © 2007 Microchip Technology Inc.

PIC16F5X 7.1 Using Timer0 with an External When a prescaler is used, the external clock input is Clock divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. When an external clock input is used for Timer0, it must For the external clock to meet the sampling require- meet certain requirements. The external clock ment, the ripple counter must be taken into account. requirement is due to internal phase clock (TOSC) Therefore, it is necessary for T0CKI to have a period of synchronization. Also, there is a delay in the actual at least 4TOSC (and a small RC delay of 40ns) divided incrementing of Timer0 after synchronization. by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the 7.1.1 EXTERNAL CLOCK minimum pulse width requirement of 10 ns. Refer to SYNCHRONIZATION parameters 40, 41 and 42 in the electrical specification When no prescaler is used, the external clock is the of the desired device. Timer0 input. The synchronization of T0CKI with the 7.1.2 TIMER0 INCREMENT DELAY internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the inter- Since the prescaler output is synchronized with the nal phase clocks (Figure7-4). Therefore, it is neces- internal clocks, there is a small delay from the time the sary for T0CKI to be high for at least 2TOSC (and a small external clock edge occurs to the time the Timer0 RC delay of 20ns) and low for at least 2TOSC (and a module is actually incremented. Figure7-4 shows the small RC delay of 20ns). Refer to the electrical delay from the external clock edge to the timer specification of the desired device. incrementing. FIGURE 7-4: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Small pulse Prescaler Output(1) misses sampling (3) External Clock/Prescaler (2) Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: External clock if no prescaler selected; prescaler output otherwise. 2: The arrows indicate the points in time where sampling occurs. 3: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC (duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4TOSC max. 7.2 Prescaler The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. An 8-bit counter is available as a prescaler for the When assigned to the Timer0 module, all instructions Timer0 module, or as a postscaler for the Watchdog writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, Timer (WDT), respectively (Section8.2.1 “WDT BSF 1, x, etc.) will clear the prescaler. When assigned Period”). For simplicity, this counter is being referred to WDT, a CLRWDT instruction will clear the prescaler to as “prescaler” throughout this data sheet. Note that along with the WDT. The prescaler is neither readable the prescaler may be used by either the Timer0 module nor writable. On a Reset, the prescaler contains all ‘0’s. or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. © 2007 Microchip Technology Inc. DS41213D-page 35

PIC16F5X 7.2.1 SWITCHING PRESCALER To change prescaler from the WDT to the Timer0 ASSIGNMENT module, use the sequence shown in Example7-2. This sequence must be used even if the WDT is disabled. A The prescaler assignment is fully under software control CLRWDT instruction should be executed before (i.e., it can be changed “on-the-fly” during program switching the prescaler. execution). To avoid an unintended device Reset, the following instruction sequence (Example7-1) must be EXAMPLE 7-2: CHANGING PRESCALER executed when changing the prescaler assignment (WDT→TIMER0) from Timer0 to the WDT. CLRWDT ;Clear WDT and EXAMPLE 7-1: CHANGING PRESCALER ;prescaler (TIMER0→WDT) MOVLW B'xxxx0xxx' ;Select TMR0, new ;prescale value and CLRWDT ;Clear WDT ;clock source CLRF TMR0 ;Clear TMR0 & ;Prescaler OPTION MOVLW B'00xx1111’ ;Last 3 instructions ;in this example OPTION ;are required only if ;desired CLRWDT ;PS<2:0> are 000 or 001 MOVLW B'00xx1xxx’ ;Set Prescaler to OPTION ;desired WDT rate FIGURE 7-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY ( = FOSC/4) Data Bus 0 8 M 1 U T0CKI 1 X M Sync pin U 2 TMR0 reg 0 X Cycles T0SE(1) T0CS(1) PSA(1) 0 8-bit Prescaler M U 1 X Watchdog 8 Timer 8-to-1 MUX PS<2:0>(1) PSA(1) 0 1 WDT Enable bit MUX PSA(1) WDT Time-Out Note 1: T0CS, T0SE, PSA PS<2:0> are bits in the Option register. DS41213D-page 36 © 2007 Microchip Technology Inc.

PIC16F5X 8.0 SPECIAL FEATURES OF THE The Sleep mode is designed to offer a very low-current CPU Power-down mode. The user can wake-up from Sleep through external Reset or through a Watchdog Timer What sets a microcontroller apart from other proces- time-out. Several oscillator options are also made sors are special circuits that deal with the needs of real- available to allow the part to fit the application. The RC time applications. The PIC16F5X family of microcon- oscillator option saves system cost, while the LP crystal trollers have a host of such features intended to option saves power. A set of Configuration bits are maximize system reliability, minimize cost through used to select various options. elimination of external components, provide power- saving operating modes and offer code protection. 8.1 Configuration Bits These features are: Configuration bits can be programmed to select various (cid:129) Oscillator Selection device configurations. Two bits are for the selection of (cid:129) Reset the oscillator type; one bit is the Watchdog Timer (cid:129) Power-on Reset enable bit; one bit is for code protection for the (cid:129) Device Reset Timer PIC16F5X devices (Register8-1). (cid:129) Watchdog Timer (WDT) (cid:129) Sleep (cid:129) Code protection (cid:129) User ID locations (cid:129) In-Circuit Serial Programming™ (ICSP™) The PIC16F5X family has a Watchdog Timer which can be shut off only through Configuration bit WDTE. It runs off of its own RC oscillator for added reliability. There is an 18ms delay provided by the Device Reset Timer (DRT), intended to keep the chip in Reset until the crystal oscillator is stable. With this timer on-chip, most applications need no external Reset circuitry. REGISTER 8-1: CONFIGURATION WORD FOR PIC16F5X — — — — — — — — CP WDTE FOSC1 FOSC0 bit 11 bit 0 bit 11-4: Unimplemented: Read as ‘1’ bit 3: CP: Code Protection bit. 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 00 = LP oscillator 01 = XT oscillator 10 = HS oscillator 11 = RC oscillator Note1: Refer to the PIC16F54, PIC16F57 and PIC16F59 Programming Specifications to determine how to access the Configuration Word. These documents can be found on the Microchip web site at www.microchip.com. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown © 2007 Microchip Technology Inc. DS41213D-page 37

PIC16F5X 8.2 Watchdog Timer (WDT) 8.2.2 WDT PROGRAMMING CONSIDERATIONS The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external The CLRWDT instruction clears the WDT and the components. This RC oscillator is separate from the prescaler, if assigned to the WDT, and prevents it from RC oscillator of the OSC1/CLKIN pin. That means that timing out and generating a device Reset. the WDT will run even if the clock on the OSC1/CLKIN The SLEEP instruction resets the WDT and the and OSC2/CLKOUT pins have been stopped, for prescaler, if assigned to the WDT. This gives the example, by execution of a SLEEP instruction. During maximum Sleep time before a WDT Wake-up Reset. normal operation or Sleep, a WDT Reset or Wake-up Reset generates a device Reset. FIGURE 8-1: WATCHDOG TIMER The TO bit (STATUS<4>) will be cleared upon a BLOCK DIAGRAM Watchdog Timer Reset (Section3.3 “STATUS From TMR0 Clock Source Register”). The WDT can be permanently disabled by program- 0 M ming the Configuration bit WDTE as a ‘0’ (Section8.1 “Configuration Bits”). Refer to the PIC16F54 and Watchdog 1 U Prescaler Timer X PIC16F57 Programming Specifications to determine how to access the Configuration Word. These documents can be found on the Microchip web site at PSA(1) 8-to-1 PS<2:0>(1) www.microchip.com. WDTE MUX 8.2.1 WDT PERIOD To TMR0 An 8-bit counter is available as a prescaler for the 0 1 Timer0 module (Section7.2 “Prescaler”), or as a MUX PSA(1) postscaler for the Watchdog Timer (WDT), respec- tively. For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. WDT Time-out Note: The prescaler may be used by either the Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the Timer0 module or the WDT, but not both. Option register. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio (Section3.4 “Option Register”). The WDT has a nominal time-out period of 18ms (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writ- ing to the Option register. Thus time-out, a period of a nominal 2.3 seconds, can be realized. These periods vary with temperature, VDD and part-to-part process variations (see Device Characterization). Under worst case conditions (VDD = Min., Temperature = Max., WDT prescaler = 1:128), it may take several seconds before a WDT time-out occurs. TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on MCLR and Reset WDT Reset N/A OPTION — — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111 Legend: Shaded cells not used by Watchdog Timer, - = unimplemented, read as ‘0’, u = unchanged DS41213D-page 38 © 2007 Microchip Technology Inc.

PIC16F5X 8.3 Power-Down Mode (Sleep) 8.5 User ID Locations A device may be powered down (Sleep) and later Four memory locations are designated as user ID loca- powered up (wake-up from Sleep). tions where the user can store checksum or other code-identification numbers. These locations are not 8.3.1 SLEEP accessible during normal execution, but are readable The Power-down mode is entered by executing a and writable during Program/Verify. SLEEP instruction. Use only the lower 4 bits of the user ID locations and If enabled, the Watchdog Timer will be cleared but always program the upper 8 bits as ‘1’s. keeps running, the TO bit (STATUS<4>) is set, the PD Note: Microchip will assign a unique pattern bit (STATUS<3>) is cleared and the oscillator driver is number for QTP and SQTP requests. This turned off. The I/O ports maintain the status they had pattern number will be unique and trace- before the SLEEP instruction was executed (driving able to the submitted code. high, driving low or high-impedance). It should be noted that a Reset generated by a WDT 8.6 In-Circuit Serial Programming™ time-out does not drive the MCLR/VPP pin low. (ICSP™) For lowest current consumption while powered down, The PIC16F5X microcontrollers can be serially the T0CKI input should be at VDD or VSS and the programmed while in the end application circuit. This is MCLR/VPP pin must be at a logic high level simply done with two lines for clock and data, and three (MCLR = VIH). other lines for power, ground and programming 8.3.2 WAKE-UP FROM SLEEP voltage. This allows customers to manufacture boards with unprogrammed devices and then program the The device can wake-up from Sleep through one of the microcontroller just before shipping the product. Thus, following events: the most recent firmware or custom firmware can be 1. An external Reset input on MCLR/VPP pin. programmed. 2. A Watchdog Timer time-out Reset (if WDT was The device is placed into a Program/Verify mode by enabled). holding the RB6 and RB7 pins low while raising the Both of these events cause a device Reset. The TO MCLR (VPP) pin from VIL to VIHH (see programming and PD bits can be used to determine the cause of specification). RB6 becomes the programming clock device Reset. The TO bit is cleared if a WDT time-out and RB7 becomes the programming data. Both RB6 occurred (and caused wake-up). The PD bit, which is and RB7 are Schmitt Trigger inputs in this mode. set on power-up, is cleared when SLEEP is invoked. A 6-bit command is then supplied to the device. The WDT is cleared when the device wakes from Depending on the command, 14 bits of program data Sleep, regardless of the wake-up source. are then supplied to or from the device, depending if the command was a Load or a Read. For complete details of serial programming, please refer to the 8.4 Program Verification/Code respective Programming Specifications: “PIC16F54 Protection Memory Programming Specification” (DS41207), If the code protection bit has not been programmed, the “PIC16F57 Memory Programming Specification” on-chip program memory can be read out for (DS41208), and “PIC16F59 Memory Programming verification purposes. Specification” (DS41243). Once code protection is enabled, all program memory A typical In-Circuit Serial Programming connection is locations above 0x3F read all ‘0’s. Program memory shown in Figure8-1. locations 0x00-0x3F are always unprotected. The user ID locations and the Configuration Word read out in an unprotected fashion. It is possible to program the user ID locations and the Configuration Word after code protect is enabled. © 2007 Microchip Technology Inc. DS41213D-page 39

PIC16F5X FIGURE 8-1: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING™ CONNECTION To Normal External Connections Connector Signals PIC16F5X +5V VDD 0V VSS VPP MCLR/VPP CLK RB6/ICSPCLK Data I/O RB7/ICSPDAT VDD To Normal Connections DS41213D-page 40 © 2007 Microchip Technology Inc.

PIC16F5X 9.0 INSTRUCTION SET SUMMARY All instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the Each PIC16F5X instruction is a 12-bit word divided into program counter is changed as a result of an instruc- an opcode, which specifies the instruction type, and tion. In this case, the execution takes two instruction one or more operands which further specify the opera- cycles. One instruction cycle consists of four oscillator tion of the instruction. The PIC16F5X instruction set periods. Thus, for an oscillator frequency of 4MHz, the summary in Table9-2 groups the instructions into byte- normal instruction execution time would be 1μs. If a oriented, bit-oriented, and literal and control opera- conditional test is true or the program counter is tions. Table9-1 shows the opcode field descriptions. changed as a result of an instruction, the instruction For byte-oriented instructions, ‘f’ represents a file execution time would be 2μs. register designator and ‘d’ represents a destination Figure9-1 shows the three general formats that the designator. The file register designator is used to instructions can have. All examples in the figure use specify which one of the 32 file registers in that bank is the following format to represent a hexadecimal to be used by the instruction. number: The destination designator specifies where the result of 0xhhh the operation is to be placed. If ‘d’ is ‘0’, the result is where ‘h’ signifies a hexadecimal digit. placed in the W register. If ‘d’ is ‘1’, the result is placed in the file register specified in the instruction. FIGURE 9-1: GENERAL FORMAT FOR For bit-oriented instructions, ‘b’ represents a bit field INSTRUCTIONS designator which selects the number of the bit affected by the operation, while ‘f’ represents the number of the Byte-oriented file register operations file in which the bit is located. 11 6 5 4 0 For literal and control operations, ‘k’ represents an OPCODE d f (FILE #) 8-or 9-bit constant or literal value. d = 0 for destination W d = 1 for destination f TABLE 9-1: OPCODE FIELD f = 5-bit file register address DESCRIPTIONS Bit-oriented file register operations Field Description 11 8 7 5 4 0 OPCODE b (BIT #) f (FILE #) f Register file address (0x00 to 0x1F) W Working register (accumulator) b = 3-bit bit address b Bit address within an 8-bit file register f = 5-bit file register address k Literal field, constant data or label Literal and control operations (except GOTO) x Don't care location (= 0 or 1) 11 8 7 0 The assembler will generate code with x = 0. It is the recommended form of use OPCODE k (literal) for compatibility with all Microchip k = 8-bit immediate value software tools. d Destination select; Literal and control operations - GOTO instruction d = 0 (store result in W) 11 9 8 0 d = 1 (store result in file register ‘f’) OPCODE k (literal) Default is d = 1 k = 9-bit immediate value label Label name TOS Top-of-Stack PC Program Counter WDT Watchdog Timer Counter TO Time-out bit PD Power-down bit dest Destination, either the W register or the specified register file location [ ] Options ( ) Contents → Assigned to < > Register bit field ∈ In the set of italics User defined term © 2007 Microchip Technology Inc. DS41213D-page 41

PIC16F5X TABLE 9-2: INSTRUCTION SET SUMMARY Mnemonic, 12-Bit Opcode Status Description Cycles Notes Operands Affected MSb LSb ADDWF f, d Add W and f 1 0001 11df ffff C,DC,Z 1, 2, 4 ANDWF f, d AND W with f 1 0001 01df ffff Z 2, 4 CLRF f Clear f 1 0000 011f ffff Z 4 CLRW — Clear W 1 0000 0100 0000 Z COMF f, d Complement f 1 0010 01df ffff Z DECF f, d Decrement f 1 0000 11df ffff Z 2, 4 DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2, 4 INCF f, d Increment f 1 0010 10df ffff Z 2, 4 INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2, 4 IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2, 4 MOVF f, d Move f 1 0010 00df ffff Z 2, 4 MOVWF f Move W to f 1 0000 001f ffff None 1, 4 NOP — No Operation 1 0000 0000 0000 None RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2, 4 RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2,4 SUBWF f, d Subtract W from f 1 0000 10df ffff C,DC,Z 1, 2, 4 SWAPF f, d Swap f 1 0011 10df ffff None 2, 4 XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2, 4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 0100 bbbf ffff None 2, 4 BSF f, b Bit Set f 1 0101 bbbf ffff None 2, 4 BTFSC f, b Bit Test f, Skip if Clear 1(2) 0110 bbbf ffff None BTFSS f, b Bit Test f, Skip if Set 1(2) 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Subroutine Call 2 1001 kkkk kkkk None 1 CLRWDT — Clear Watchdog Timer 1 0000 0000 0100 TO, PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR Literal with W 1 1101 kkkk kkkk Z MOVLW k Move Literal to W 1 1100 kkkk kkkk None OPTION — Load OPTION register 1 0000 0000 0010 None RETLW k Return, place Literal in W 2 1000 kkkk kkkk None SLEEP — Go into Standby mode 1 0000 0000 0011 TO, PD TRIS f Load TRIS register 1 0000 0000 0fff None 3 XORLW k Exclusive OR Literal to W 1 1111 kkkk kkkk Z Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for GOTO (see Section3.5 “Program Counter” for more on program counter). 2: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 3: The instruction TRIS f, where f = 5, 6 or 7 causes the contents of the W register to be written to the tri-state latches of PORTA, B or C, respectively. A ‘1’ forces the pin to a high-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS41213D-page 42 © 2007 Microchip Technology Inc.

PIC16F5X ADDWF Add W and f ANDWF AND W with f Syntax: [ label ] ADDWF f, d Syntax: [ label ] ANDWF f, d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: (W) + (f) → (dest) Operation: (W) .AND. (f) → (dest) Status Affected: C, DC, Z Status Affected: Z Encoding: 0001 11df ffff Encoding: 0001 01df ffff Description: Add the contents of the W register Description: The contents of the W register are and register ‘f’. If ‘d’ is ‘0’, the AND’ed with register ‘f’. If ‘d’ is ‘0’, result is stored in the W register. If the result is stored in the W ‘d’ is ‘1’, the result is stored back in register. If ‘d’ is ‘1’, the result is register 'f'. stored back in register ‘f’. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: ADDWF TEMP_REG, 0 Example: ANDWF TEMP_REG, 1 Before Instruction Before Instruction W = 0x17 W = 0x17 TEMP_REG = 0xC2 TEMP_REG = 0xC2 After Instruction After Instruction W = 0xD9 W = 0x17 TEMP_REG = 0xC2 TEMP_REG = 0x02 ANDLW AND literal with W BCF Bit Clear f Syntax: [ label ] ANDLW k Syntax: [ label ] BCF f, b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 31 Operation: (W).AND. (k) → (W) 0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: Z Status Affected: None Encoding: 1110 kkkk kkkk Encoding: 0100 bbbf ffff Description: The contents of the W register are AND’ed with the eight-bit literal ‘k’. Description: Bit ‘b’ in register ‘f’ is cleared. The result is placed in the W Words: 1 register. Cycles: 1 Words: 1 Example: BCF FLAG_REG, 7 Cycles: 1 Before Instruction Example: ANDLW H'5F' FLAG_REG = 0xC7 Before Instruction After Instruction W = 0xA3 FLAG_REG = 0x47 After Instruction W = 0x03 © 2007 Microchip Technology Inc. DS41213D-page 43

PIC16F5X BSF Bit Set f BTFSS Bit Test f, Skip if Set Syntax: [ label ] BSF f, b Syntax: [ label ] BTFSS f, b Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 0 ≤ b ≤ 7 0 ≤ b < 7 Operation: 1 → (f<b>) Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 0101 bbbf ffff Encoding: 0111 bbbf ffff Description: Bit ‘b’ in register ‘f’ is set. Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. Words: 1 If bit ‘b’ is ‘1’, then the next instruc- Cycles: 1 tion fetched during the current Example: BSF FLAG_REG, 7 instruction execution is discarded and a NOP is executed instead, Before Instruction making this a two-cycle instruction. FLAG_REG = 0x0A After Instruction Words: 1 FLAG_REG = 0x8A Cycles: 1(2) Example: HERE BTFSS FLAG,1 FALSE GOTO PROCESS_CODE BTFSC Bit Test f, Skip if Clear TRUE • • Syntax: [ label ] BTFSC f, b • Operands: 0 ≤ f ≤ 31 0 ≤ b ≤ 7 Before Instruction PC = address (HERE) Operation: skip if (f<b>) = 0 After Instruction Status Affected: None If FLAG<1> = 0, PC = address (FALSE); Encoding: 0110 bbbf ffff if FLAG<1> = 1, Description: If bit ‘b’ in register ‘f’ is ‘0’, then the PC = address (TRUE) next instruction is skipped. If bit ‘b’ is ‘0’, then the next instruc- tion fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. Words: 1 Cycles: 1(2) Example: HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE (cid:129) (cid:129) (cid:129) Before Instruction PC = address (HERE) After Instruction if FLAG<1> = 0, PC = address (TRUE); if FLAG<1> = 1, PC = address(FALSE) DS41213D-page 44 © 2007 Microchip Technology Inc.

PIC16F5X CALL Subroutine Call CLRW Clear W Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0 ≤ k ≤ 255 Operands: None Operation: (PC) + 1→ TOS; Operation: 00h → (W); k → PC<7:0>; 1 → Z (Status<6:5>) → PC<10:9>; Status Affected: Z 0 → PC<8> Encoding: 0000 0100 0000 Status Affected: None Description: The W register is cleared. Zero bit Encoding: 1001 kkkk kkkk (Z) is set. Description: Subroutine call. First, return Words: 1 address (PC + 1) is pushed onto the stack. The eight-bit immediate Cycles: 1 address is loaded into PC bits Example: CLRW <7:0>. The upper bits PC<10:9> Before Instruction are loaded from STATUS<6:5>, W = 0x5A PC<8> is cleared. CALL is a After Instruction two-cycle instruction. W = 0x00 Words: 1 Z = 1 Cycles: 2 Example: HERE CALL THERE Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 1) CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRF f Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 31 Operands: None Operation: 00h → (f); Operation: 00h → WDT; 1 → Z 0 → WDT prescaler (if assigned); Status Affected: Z 1 → TO; 1 → PD Encoding: 0000 011f ffff Status Affected: TO, PD Description: The contents of register ‘f’ are Encoding: 0000 0000 0100 cleared and the Z bit is set. Description: The CLRWDT instruction resets the Words: 1 WDT. It also resets the prescaler if Cycles: 1 the prescaler is assigned to the Example: CLRF FLAG_REG WDT and not Timer0. Status bits TO and PD are set. Before Instruction FLAG_REG = 0x5A Words: 1 After Instruction Cycles: 1 FLAG_REG = 0x00 Z = 1 Example: CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = 0x00 WDT prescaler = 0 TO = 1 PD = 1 © 2007 Microchip Technology Inc. DS41213D-page 45

PIC16F5X COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF f, d Syntax: [ label ] DECFSZ f, d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: (f) → (dest) Operation: (f) – 1 → d; skip if result = 0 Status Affected: Z Status Affected: None Encoding: 0010 01df ffff Encoding: 0010 11df ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the decremented. If ‘d’ is ‘0’, the result result is stored in the W register. If is placed in the W register. If ‘d’ is ‘d’ is ‘1’, the result is stored back in ‘1’. the result is placed back in register ‘f’. register ‘f’. If the result is ‘0’, the next instruction, which is already Words: 1 fetched, is discarded and a NOP is Cycles: 1 executed instead making it a Example: COMF REG1,0 two-cycle instruction. Before Instruction Words: 1 REG1 = 0x13 Cycles: 1(2) After Instruction Example: HERE DECFSZ CNT, 1 REG1 = 0x13 GOTO LOOP W = 0xEC CONTINUE (cid:129) (cid:129) (cid:129) DECF Decrement f Before Instruction Syntax: [ label ] DECF f, d PC = address(HERE) Operands: 0 ≤ f ≤ 31 After Instruction d ∈ [0,1] CNT = CNT - 1; if CNT = 0, Operation: (f) – 1 → (dest) PC = address (CONTINUE); Status Affected: Z if CNT ≠ 0, PC = address (HERE+1) Encoding: 0000 11df ffff Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Words: 1 Cycles: 1 Example: DECF CNT, 1 Before Instruction CNT = 0x01 Z = 0 After Instruction CNT = 0x00 Z = 1 DS41213D-page 46 © 2007 Microchip Technology Inc.

PIC16F5X GOTO Unconditional Branch INCFSZ Increment f, Skip if 0 Syntax: [ label ] GOTO k Syntax: [ label ] INCFSZ f, d Operands: 0 ≤ k ≤ 511 Operands: 0 ≤ f ≤ 31 Operation: k → PC<8:0>; d ∈ [0,1] STATUS<6:5> → PC<10:9> Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Status Affected: None Encoding: 101k kkkk kkkk Encoding: 0011 11df ffff Description: GOTO is an unconditional branch. Description: The contents of register ‘f’ are The 9-bit immediate value is incremented. If ‘d’ is ‘0’, the result loaded into PC bits <8:0>. The is placed in the W register. If ‘d’ is upper bits of PC are loaded from ‘1’, the result is placed back in STATUS<6:5>. GOTO is a two- register ‘f’. If the result is ‘0’, then cycle instruction. the next instruction, which is already fetched, is discarded and Words: 1 a NOP is executed instead making Cycles: 2 it a two-cycle instruction. Example: GOTO THERE Words: 1 After Instruction Cycles: 1(2) PC = address (THERE) Example: HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE (cid:129) INCF Increment f (cid:129) (cid:129) Syntax: [ label ] INCF f, d Operands: 0 ≤ f ≤ 31 Before Instruction d ∈ [0,1] PC = address (HERE) After Instruction Operation: (f) + 1 → (dest) CNT = CNT + 1; Status Affected: Z if CNT = 0, PC = address (CONTINUE); Encoding: 0010 10df ffff if CNT ≠ 0, Description: The contents of register ‘f’ are PC = address (HERE +1) incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Words: 1 Cycles: 1 Example: INCF CNT, 1 Before Instruction CNT = 0xFF Z = 0 After Instruction CNT = 0x00 Z = 1 © 2007 Microchip Technology Inc. DS41213D-page 47

PIC16F5X IORLW Inclusive OR literal with W MOVF Move f Syntax: [ label ] IORLW k Syntax: [ label ] MOVF f, d Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 31 Operation: (W) .OR. (k) → (W) d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Status Affected: Z Encoding: 1101 kkkk kkkk Encoding: 0010 00df ffff Description: The contents of the W register are OR’ed with the eight-bit literal ‘k’. Description: The contents of register ‘f’ is The result is placed in the W moved to destination ‘d’. If ‘d’ is ‘0’, register. destination is the W register. If ‘d’ is ‘1’, the destination is file Words: 1 register ‘f’. ‘d’ is ‘1’ is useful to test Cycles: 1 a file register since Status flag Z is Example: IORLW 0x35 affected. Before Instruction Words: 1 W = 0x9A Cycles: 1 After Instruction Example: MOVF FSR, 0 W = 0xBF Z = 0 After Instruction W = value in FSR register IORWF Inclusive OR W with f MOVLW Move Literal to W Syntax: [ label ] IORWF f, d Syntax: [ label ] MOVLW k Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: k → (W) Operation: (W).OR. (f) → (dest) Status Affected: None Status Affected: Z Encoding: 1100 kkkk kkkk Encoding: 0001 00df ffff Description: The eight-bit literal ‘k’ is loaded Description: Inclusive OR the W register with into the W register. register ‘f’. If ‘d’ is ‘0’, the result is Words: 1 placed in the W register. If ‘d’ is ‘1’, the result is placed back in Cycles: 1 register ‘f’. Example: MOVLW 0x5A Words: 1 After Instruction W = 0x5A Cycles: 1 Example: IORWF RESULT, 0 Before Instruction RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93 Z = 0 DS41213D-page 48 © 2007 Microchip Technology Inc.

PIC16F5X MOVWF Move W to f OPTION Load OPTION Register Syntax: [ label ] MOVWF f Syntax: [ label ] OPTION Operands: 0 ≤ f ≤ 31 Operands: None Operation: (W) → (f) Operation: (W) → OPTION Status Affected: None Status Affected: None Encoding: 0000 0000 0010 Encoding: 0000 001f ffff Description: The content of the W register is Description: Move data from the W register to loaded into the Option register. register ‘f’. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: OPTION Example: MOVWF TEMP_REG Before Instruction Before Instruction W = 0x07 TEMP_REG = 0xFF After Instruction W = 0x4F OPTION = 0x07 After Instruction TEMP_REG = 0x4F W = 0x4F NOP No Operation RETLW Return with Literal in W Syntax: [ label ] NOP Syntax: [ label ] RETLW k Operands: None Operands: 0 ≤ k ≤ 255 Operation: No operation Operation: k → (W); TOS → PC Status Affected: None Status Affected: None Encoding: 0000 0000 0000 Encoding: 1000 kkkk kkkk Description: No operation. Description: The W register is loaded with the Words: 1 eight-bit literal ‘k’. The program Cycles: 1 counter is loaded from the top of Example: NOP the stack (the return address). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: CALL TABLE;W contains ;table offset ;value. (cid:129) ;W now has table (cid:129) ;value. TABLE (cid:129) ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; (cid:129) (cid:129) (cid:129) RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 © 2007 Microchip Technology Inc. DS41213D-page 49

PIC16F5X RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] RLF f, d Syntax: [ label ] RRF f, d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: 0011 01df ffff Encoding: 0011 00df ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are rotated one bit to the left through rotated one bit to the right through the Carry Flag (STATUS<0>). If ‘d’ the Carry Flag (STATUS<0>). If ‘d’ is ‘0’, the result is placed in the W is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. placed back in register ‘f’. C register 'f' C register 'f' Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: RLF REG1,0 Example: RRF REG1,0 Before Instruction Before Instruction REG1 = 1110 0110 REG1 = 1110 0110 C = 0 C = 0 After Instruction After Instruction REG1 = 1110 0110 REG1 = 1110 0110 W = 1100 1100 W = 0111 0011 C = 1 C = 0 Sleep Go into Standby Mode Syntax: [ label ] Sleep Operands: None Operation: 00h → WDT; 0 → WDT prescaler; if assigned 1 → TO; 0 → PD Status Affected: TO, PD Encoding: 0000 0000 0011 Description: Time-out Status bit (TO) is set. The power-down Status bit (PD) is cleared. The WDT and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. See section on Sleep for more details. Words: 1 Cycles: 1 Example: SLEEP DS41213D-page 50 © 2007 Microchip Technology Inc.

PIC16F5X SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] SUBWF f, d Syntax: [ label ] SWAPF f, d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: (f) – (W) → (dest) Operation: (f<3:0>) → (dest<7:4>); (f<7:4>) → (dest<3:0>) Status Affected: C, DC, Z Status Affected: None Encoding: 0000 10df ffff Encoding: 0011 10df ffff Description: Subtract (2’s complement method) the W register from register ‘f’. If ‘d’ Description: The upper and lower nibbles of is ‘0’, the result is stored in the W register ‘f’ are exchanged. If ‘d’ is register. If ‘d’ is ‘1’, the result is ‘0’, the result is placed in W stored back in register ‘f’. register. If ‘d’ is ‘1’, the result is placed in register ‘f’. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example 1: SUBWF REG1, 1 Example: SWAPF REG1, 0 Before Instruction REG1 = 3 Before Instruction W = 2 REG1 = 0xA5 C = ? After Instruction After Instruction REG1 = 0xA5 REG1 = 1 W = 0x5A W = 2 C = 1 ; result is positive Example 2: TRIS Load TRIS Register Before Instruction REG1 = 2 Syntax: [ label ] TRIS f W = 2 Operands: f = 5, 6, 7, 8 or 9 C = ? Operation: (W) → TRIS register f After Instruction Status Affected: None REG1 = 0 W = 2 Encoding: 0000 0000 0fff C = 1 ; result is zero Description: TRIS register ‘f’ (f = 5, 6 or 7) is Example 3: loaded with the contents of the W Before Instruction register. REG1 = 1 Words: 1 W = 2 C = ? Cycles: 1 After Instruction Example: TRIS PORTB REG1 = 0xFF Before Instruction W = 2 W = 0xA5 C = 0 ; result is negative After Instruction TRISB = 0xA5 © 2007 Microchip Technology Inc. DS41213D-page 51

PIC16F5X XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Encoding: 1111 kkkk kkkk Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. Words: 1 Cycles: 1 Example: XORLW 0xAF Before Instruction W = 0xB5 After Instruction W = 0x1A XORWF Exclusive OR W with f Syntax: [ label ] XORWF f, d Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding: 0001 10df ffff Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Words: 1 Cycles: 1 Example: XORWF REG,1 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 DS41213D-page 52 © 2007 Microchip Technology Inc.

PIC16F5X 10.0 DEVELOPMENT SUPPORT 10.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- (cid:129) Integrated Development Environment controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software operating system-based application that contains: (cid:129) Assemblers/Compilers/Linkers (cid:129) A single graphical interface to all debugging tools - MPASMTM Assembler - Simulator - MPLAB C18 and MPLAB C30 C Compilers - Programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) (cid:129) Simulators (cid:129) A full-featured editor with color-coded context - MPLAB SIM Software Simulator (cid:129) A multiple project manager (cid:129) Emulators (cid:129) Customizable data windows with direct edit of contents - MPLAB ICE 2000 In-Circuit Emulator (cid:129) High-level source code debugging - MPLAB REAL ICE™ In-Circuit Emulator (cid:129) Visual device initializer for easy register (cid:129) In-Circuit Debugger initialization - MPLAB ICD 2 (cid:129) Mouse over variable inspection (cid:129) Device Programmers (cid:129) Drag and drop variables from source to watch - PICSTART® Plus Development Programmer windows - MPLAB PM3 Device Programmer (cid:129) Extensive on-line help - PICkit™ 2 Development Programmer (cid:129) Integration of select third party tools, such as (cid:129) Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR Boards and Evaluation Kits C Compilers The MPLAB IDE allows you to: (cid:129) Edit your source files (either assembly or C) (cid:129) One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) (cid:129) Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2007 Microchip Technology Inc. DS41213D-page 53

PIC16F5X 10.2 MPASM Assembler 10.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: (cid:129) Support for the entire dsPIC30F instruction set (cid:129) Integration into MPLAB IDE projects (cid:129) Support for fixed-point and floating-point data (cid:129) User-defined macros to streamline (cid:129) Command line interface assembly code (cid:129) Rich directive set (cid:129) Conditional assembly for multi-purpose source files (cid:129) Flexible macro language (cid:129) Directives that allow complete control over the (cid:129) MPLAB IDE compatibility assembly process 10.6 MPLAB SIM Software Simulator 10.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulat- ing the PIC MCUs and dsPIC® DSCs on an instruction The MPLAB C18 and MPLAB C30 Code Development level. On any given instruction, the data areas can be Systems are complete ANSI C compilers for examined or modified and stimuli can be applied from Microchip’s PIC18 and PIC24 families of microcontrol- a comprehensive stimulus controller. Registers can be lers and the dsPIC30 and dsPIC33 family of digital sig- logged to files for further run-time analysis. The trace nal controllers. These compilers provide powerful buffer and logic analyzer display extend the power of integration capabilities, superior code optimization and the simulator to record and track program execution, ease of use not found with other compilers. actions on I/O, most peripherals and internal registers. For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and debugger. MPLAB C30 CCompilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator 10.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside MPLIB Object Librarian of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: (cid:129) Efficient linking of single libraries instead of many smaller files (cid:129) Enhanced code maintainability by grouping related modules together (cid:129) Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS41213D-page 54 © 2007 Microchip Technology Inc.

PIC16F5X 10.7 MPLAB ICE 2000 10.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes microcontrollers. Software control of the MPLAB ICE the in-circuit debugging capability built into theFlash 2000 In-Circuit Emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers cost- editing, building, downloading and source debugging effective, in-circuit Flash debugging from the graphical from a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step- ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB ICE 2000 In-Circuit Emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 10.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for simple, unified application. maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various 10.8 MPLAB REAL ICE In-Circuit package types. The ICSP™ cable assembly is included Emulator System as a standard item. In Stand-Alone mode, the MPLAB MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set Microchip Flash DSC® and MCU devices. It debugs and code protection in this mode. The MPLAB PM3 programs PIC® and dsPIC® Flash microcontrollers with connects to the host PC via an RS-232 or USB cable. the easy-to-use, powerful graphical user interface of the The MPLAB PM3 has high-speed communications and MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large included with each kit. memory devices and incorporates an SD/MMC card for file storage and secure data applications. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, low- voltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2007 Microchip Technology Inc. DS41213D-page 55

PIC16F5X 10.11 PICSTART Plus Development 10.13 Demonstration, Development and Programmer Evaluation Boards The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func- Integrated Development Environment software makes tional systems. Most boards include prototyping areas for using the programmer simple and efficient. The adding custom circuitry and provide application firmware PICSTART Plus Development Programmer supports and source code for examination and modification. most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs, Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232 PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional The PICSTART Plus Development Programmer is CE EEPROM memory. compliant. The demonstration and development boards can be used in teaching environments, for prototyping custom 10.12 PICkit 2 Development Programmer circuits and for learning about various microcontroller The PICkit™ 2 Development Programmer is a low-cost applications. programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ demon- an easy-to-use interface for programming many of stration/development board series of circuits, Microchip Microchip’s baseline, mid-range and PIC18F families of has a line of evaluation kits and demonstration software Flash memory microcontrollers. The PICkit 2 Starter Kit for analog filter design, KEELOQ® security ICs, CAN, includes a prototyping development board, twelve IrDA®, PowerSmart® battery management, SEEVAL® sequential lessons, software and HI-TECH’s PICC™ evaluation system, Sigma-Delta ADC, flow rate Lite C compiler, and is designed to help get up to speed sensing, plus many more. quickly using PIC® microcontrollers. The kit provides Check the Microchip web page (www.microchip.com) everything needed to program, evaluate and develop and the latest “Product Selector Guide” (DS00148) for applications using Microchip’s powerful, mid-range the complete list of demonstration, development and Flash memory family of microcontrollers. evaluation kits. DS41213D-page 56 © 2007 Microchip Technology Inc.

PIC16F5X 11.0 ELECTRICAL SPECIFICATIONS FOR PIC16F54/57 Absolute Maximum Ratings(†) Ambient Temperature under bias.........................................................................................................-40°C to +125°C Storage Temperature...........................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS............................................................................................................0V to +6.5V Voltage on MCLR with respect to VSS(1)...................................................................................................0V to +13.5V Voltage on all other pins with respect to VSS...............................................................................-0.6V to (VDD + 0.6V) Total power dissipation(2)..................................................................................................................................800mW Max. current out of VSS pin................................................................................................................................150mA Max. current into VDD pin...................................................................................................................................100mA Max. current into an input pin (T0CKI only).......................................................................................................±500μA Input clamp current, IIK (VI < 0 or VI > VDD).......................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)................................................................................................±20mA Max. output current sunk by any I/O pin..............................................................................................................25mA Max. output current sourced by any I/O pin.........................................................................................................25mA Max. output current sourced by a single I/O port (PORTA, B or C).....................................................................50mA Max. output current sunk by a single I/O port (PORTA, B or C)...........................................................................50mA Note1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80mA, may cause latch-up. Thus, a series resistor of 50 to 100Ω should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. 2: Power Dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2007 Microchip Technology Inc. DS41213D-page 57

PIC16F5X 11.0 ELECTRICAL SPECIFICATIONS FOR PIC16F59 (continued) Absolute Maximum Ratings(†) Ambient Temperature under bias.........................................................................................................-40°C to +125°C Storage Temperature............................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS............................................................................................................0V to +6.5V Voltage on MCLR with respect to VSS(1)...................................................................................................0V to +13.5V Voltage on all other pins with respect to VSS................................................................................-0.6V to (VDD + 0.6V) Total power dissipation(2)..................................................................................................................................900mW Max. current out of VSS pins...............................................................................................................................250mA Max. current into VDD pins.................................................................................................................................200mA Max. current into an input pin (T0CKI only).......................................................................................................±500μA Input clamp current, IIK (VI < 0 or VI > VDD).......................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)................................................................................................±20mA Max. output current sunk by any I/O pin...............................................................................................................25mA Max. output current sourced by any I/O pin.........................................................................................................25mA Max. output current sourced by a single I/O port (PORTA, B, C, D or E)...........................................................100mA Max. output current sunk by a single I/O port (PORTA, B, C, D or E)................................................................100mA Note1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80mA, may cause latch-up. Thus, a series resistor of 50 to 100Ω should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. 2: Power Dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DS41213D-page 58 © 2007 Microchip Technology Inc.

PIC16F5X FIGURE 11-1: PIC16F5X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 4.5 4.0 VDD (Volts) 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. © 2007 Microchip Technology Inc. DS41213D-page 59

PIC16F5X 11.1 DC Characteristics: PIC16F5X (Industrial) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym. Characteristic/Device Min. Typ† Max. Units Conditions No. D001 VDD Supply Voltage 2.0 — 5.5 V D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure — Vss — V See Section5.1 “Power-on Reset Power-on Reset (POR)” for details on Power-on Reset D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section5.1 “Power-on Reset Power-on Reset (POR)” for details on Power-on Reset D010 IDD Supply Current(2) — 170 350 μA FOSC = 4 MHz, VDD = 2.0V, XT or RC mode(3) — 0.4 1.0 mA FOSC = 10 MHz, VDD = 3.0V, HS mode — 1.7 5.0 mA FOSC = 20 MHz, VDD = 5.0V, HS mode — 15 22.5 μA FOSC = 32 kHz, VDD = 2.0V, LP mode, WDT disabled D020 IPD Power-down Current(2) — 1.0 6.0 μA VDD = 2.0V, WDT enabled — 0.5 2.5 μA VDD = 2.0V, WDT disabled * These parameters are characterized but not tested. † Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature, also have an impact on the current consumption. a) The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode. The Power-down Current in Sleep mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR=VDD/2REXT(mA) with REXT in kΩ. DS41213D-page 60 © 2007 Microchip Technology Inc.

PIC16F5X 11.2 DC Characteristics: PIC16F5X (Extended) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +125°C for extended Param Sym. Characteristic/Device Min. Typ† Max. Units Conditions No. D001 VDD Supply Voltage 2.0 — 5.5 V D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure — VSS — V See Section5.1 “Power-on Reset Power-on Reset (POR)” for details on Power-on Reset D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section5.1 “Power-on Reset Power-on Reset (POR)” for details on Power-on Reset D010 IDD Supply Current(2) — 170 450 μA FOSC = 4 MHz, VDD = 2.0V, XT or RC mode(3) — 0.4 2.0 mA FOSC = 10 MHz, VDD = 3.0V, HS mode — 1.7 7.0 mA FOSC = 20 MHz, VDD = 5.0V, HS mode — 15 40 μA FOSC = 32 kHz, VDD = 2.0V, LP mode, WDT disabled D020 IPD Power-down Current(2) — 1.0 15.0 μA VDD = 2.0V, WDT enabled — 0.5 8.0 μA VDD = 2.0V, WDT disabled * These parameters are characterized but not tested. † Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature, also have an impact on the current consumption. a) The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode. The Power-down Current in Sleep mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR=VDD/2REXT(mA) with REXT in kΩ. © 2007 Microchip Technology Inc. DS41213D-page 61

PIC16F5X 11.3 DC Characteristics PIC16F5X Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage D030 I/O Ports VSS — 0.8V V 4.5V <VDD ≤ 5.5V I/O Ports VSS — 0.15VDD V VDD ≤ 4.5V MCLR (Schmitt Trigger) VSS — 0.15VDD V T0CKI (Schmitt Trigger) VSS — 0.15VDD V OSC1 (Schmitt Trigger) VSS — 0.15VDD V RC mode(3) OSC1 VSS — 0.3VDD V HS mode VSS — 0.3 V XT mode VSS — 0.3 V LP mode VIH Input High Voltage D040 I/O ports 2.0 — VDD V 4.5V < VDD ≤ 5.5V I/O ports 0.25VDD + 0.8 — VDD V VDD ≤ 4.5V MCLR (Schmitt Trigger) 0.85VDD — VDD V T0CKI (Schmitt Trigger) 0.85VDD — VDD V OSC1 (Schmitt Trigger) 0.85VDD — VDD V RC mode(3) OSC1 0.7VDD — VDD V HS mode 1.6 — VDD V XT mode 1.6 — VDD V LP mode IIL Input Leakage Current(1, 2) D060 I/O ports — — ±1.0 μA VSS ≤ VPIN ≤ VDD, pin at high-impedance MCLR — — ±5.0 μA VSS ≤ VPIN ≤ VDD T0CKI — — ±5.0 μA VSS ≤ VPIN ≤ VDD OSC1 — — ±5.0 μA VSS ≤ VPIN ≤ VDD, XT, HS and LP modes VOL Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5mA, VDD = 4.5V D083 OSC2/CLKOUT — — 0.6 V IOL = 1.6mA, VDD = 4.5V (RC mode) VOH Output High Voltage(2) D090 I/O ports(2) VDD – 0.7 — — V IOH = -3.0mA, VDD = 4.5V D092 OSC2/CLKOUT VDD – 0.7 — — V IOH = -1.3mA, VDD = 4.5V (RC mode) * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F5X be driven with external clock in RC mode. DS41213D-page 62 © 2007 Microchip Technology Inc.

PIC16F5X 11.4 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 11-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS – PIC16F5X Pin Legend: CL CL = 50 pF for all pins and OSC2 for RC mode 0-15 pF for OSC2 in XT, HS or LP modes when VSS external clock is used to drive OSC1 11.5 Timing Diagrams and Specifications FIGURE 11-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT © 2007 Microchip Technology Inc. DS41213D-page 63

PIC16F5X TABLE 11-1: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Parameter Sym. Characteristic Min. Typ† Max. Units Conditions No. FOSC External CLKIN Frequency(1) DC — 4.0 MHz XT Osc mode DC — 20 MHz HS Osc mode DC — 200 kHz LP Osc mode Oscillator Frequency(1) DC — 4.0 MHz RC Osc mode 0.1 — 4.0 MHz XT Osc mode 4.0 — 20 MHz HS Osc mode 5.0 — 200 kHz LP Osc mode 1 TOSC External CLKIN Period(1) 250 — — ns XT Osc mode 50 — — ns HS Osc mode 5.0 — — μs LP Osc mode Oscillator Period(1) 250 — — ns RC Osc mode 250 — 10,000 ns XT Osc mode 50 — 250 ns HS Osc mode 5.0 — — μs LP Osc mode 2 TCY Instruction Cycle Time(2) — 4/FOSC — — 3 TosL, TosH Clock in (OSC1) Low or High 50* — — ns XT oscillator Time 20* — — ns HS oscillator 2.0* — — μs LP oscillator 4 TosR, TosF Clock in (OSC1) Rise or Fall — — 25* ns XT oscillator Time — — 5* ns HS oscillator — — 50* ns LP oscillator * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS41213D-page 64 © 2007 Microchip Technology Inc.

PIC16F5X FIGURE 11-4: CLKOUT AND I/O TIMING – PIC16F5X Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 18 14 19 16 I/O Pin (input) 17 15 I/O Pin Old Value New Value (output) 20, 21 Note: Please refer to Figure11-2 for load conditions. TABLE 11-2: CLKOUT AND I/O TIMING REQUIREMENTS – PIC16F5X Param Sym. Characteristic Min. Typ† Max. Units No. 10 TosH2CKL OSC1↑ to CLKOUT↓(1) — 15 30** ns 11 TosH2CKH OSC1↑ to CLKOUT↑(1) — 15 30** ns 12 TCKR CLKOUT rise time(1) — 5.0 15** ns 13 TCKF CLKOUT fall time(1) — 5.0 15** ns 14 TCKL2IOV CLKOUT↓ to Port out valid(1) — — 40** ns 15 TIOV2CKH Port in valid before CLKOUT↑(1) 0.25 TCY+30* — — ns 16 TCKH2IOI Port in hold after CLKOUT↑(1) 0* — — ns 17 TOSH2IOV OSC1↑ (Q1 cycle) to Port out valid(2) — — 100* ns 18 TOSH2IOI OSC1↑ (Q2 cycle) to Port input invalid TBD — — ns (I/O in hold time) 19 TIOV2OSH Port input valid to OSC1↑ TBD — — ns (I/O in setup time) 20 TIOR Port output rise time(2, 3) — 10 25** ns 20 TIOR Port output rise time(2, 4) — 10 50** ns 21 TIOF Port output fall time(2, 3) — 10 25** ns 21 TIOF Port output fall time(2, 4) — 10 50** ns Legend: TBD = To Be Determined. * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. † Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Please refer to Figure11-2 for load conditions. 3: PIC16F54/57 only. 4: PIC16F59 only. © 2007 Microchip Technology Inc. DS41213D-page 65

PIC16F5X FIGURE 11-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -– PIC16F5X VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O pin(1) Note 1: Please refer to Figure11-2 for load conditions. TABLE 11-3: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC16F5X Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2000* — — ns VDD = 5.0V 31 TWDT Watchdog Timer Time-out Period 9.0* 18* 30* ms VDD = 5.0V (industrial) (No Prescaler) 9.0* 18* 40* VDD = 5.0V (extended) 32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (industrial) 9.0* 18* 40* VDD = 5.0V (extended) 34 TIOZ I/O high-impedance from MCLR 100* 300* 2000* ns Low * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41213D-page 66 © 2007 Microchip Technology Inc.

PIC16F5X FIGURE 11-6: TIMER0 CLOCK TIMINGS – PIC16F5X T0CKI 40 41 42 Note: Please refer to Figure11-2 for load conditions. TABLE 11-4: TIMER0 CLOCK REQUIREMENTS – PIC16F5X Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 40 Tt0H T0CKI High Pulse Width: No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width: No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* — — ns Whichever is greater. N N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. DS41213D-page 67

PIC16F5X NOTES: DS41213D-page 68 © 2007 Microchip Technology Inc.

PIC16F5X 12.0 PACKAGING INFORMATION 12.1 Package Marketing Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX PIC16F54 XXXXXXXXXXXXXXXXX -I/P e3 YYWWNNN 0723CBA 18-Lead SOIC Example XXXXXXXXXXXX PIC16F54 XXXXXXXXXXXX XXXXXXXXXXXX -E/SO e3 YYWWNNN 0718CDK 20-Lead SSOP Example XXXXXXXXXXX PIC16F54 XXXXXXXXXXX -E/SS e3 YYWWNNN 0720CBP 28-Lead PDIP Example XXXXXXXXXXXXXXX PIC16F57 XXXXXXXXXXXXXXX -I/P e3 XXXXXXXXXXXXXXX YYWWNNN 0723CBA >h >h Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2007 Microchip Technology Inc. DS41213D-page 69

PIC16F5X Package Marking Information (Continued) 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC16F57 XXXXXXXXXXXXXXXXXXXX -E/SO e3 XXXXXXXXXXXXXXXXXXXX YYWWNNN 0718CDK 28-Lead SSOP Example XXXXXXXXXXXX PIC16F57 XXXXXXXXXXXX -E/SS e3 YYWWNNN 0725CBK 28-Lead SPDIP (.300") Example XXXXXXXXXXXXXXXXX PIC16F57 XXXXXXXXXXXXXXXXX -I/P e3 YYWWNNN 0717HAT >h >h 40-Lead PDIP (.600") XXXXXXXXXXXXXXXXXX PIC16F59 XXXXXXXXXXXXXXXXXX -I/P e3 XXXXXXXXXXXXXXXXXX YYWWNNN 0712SAA >h >h 44-Lead TQFP M M XXXXXXXXXX XXXXXXXXXX PIC16F59 XXXXXXXXXX -04/PT e3 YYWWNNN 0711HAT DS41213D-page 70 © 2007 Microchip Technology Inc.

PIC16F5X 18-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L c A1 b1 b e eB Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 18 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .300 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .880 .900 .920 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .014 Upper Lead Width b1 .045 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-007B © 2007 Microchip Technology Inc. DS41213D-page 71

PIC16F5X 18-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e b α h h c φ A A2 β A1 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 18 Pitch e 1.27 BSC Overall Height A – – 2.65 Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E 10.30 BSC Molded Package Width E1 7.50 BSC Overall Length D 11.55 BSC Chamfer (optional) h 0.25 – 0.75 Foot Length L 0.40 – 1.27 Footprint L1 1.40 REF Foot Angle φ 0° – 8° Lead Thickness c 0.20 – 0.33 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-051B DS41213D-page 72 © 2007 Microchip Technology Inc.

PIC16F5X 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b c A A2 φ A1 L1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 20 Pitch e 0.65 BSC Overall Height A – – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.20 Molded Package Width E1 5.00 5.30 5.60 Overall Length D 6.90 7.20 7.50 Foot Length L 0.55 0.75 0.95 Footprint L1 1.25 REF Lead Thickness c 0.09 – 0.25 Foot Angle φ 0° 4° 8° Lead Width b 0.22 – 0.38 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-072B © 2007 Microchip Technology Inc. DS41213D-page 73

PIC16F5X 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L c A1 b1 b e eB Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e .100 BSC Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .050 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-070B DS41213D-page 74 © 2007 Microchip Technology Inc.

PIC16F5X 28-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L c b1 A1 b e eB Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e .100 BSC Top to Seating Plane A – – .250 Molded Package Thickness A2 .125 – .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .590 – .625 Molded Package Width E1 .485 – .580 Overall Length D 1.380 – 1.565 Tip to Seating Plane L .115 – .200 Lead Thickness c .008 – .015 Upper Lead Width b1 .030 – .070 Lower Lead Width b .014 – .022 Overall Row Spacing § eB – – .700 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-079B © 2007 Microchip Technology Inc. DS41213D-page 75

PIC16F5X 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e b h α h φ c A A2 L A1 L1 β Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 1.27 BSC Overall Height A – – 2.65 Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E 10.30 BSC Molded Package Width E1 7.50 BSC Overall Length D 17.90 BSC Chamfer (optional) h 0.25 – 0.75 Foot Length L 0.40 – 1.27 Footprint L1 1.40 REF Foot Angle Top φ 0° – 8° Lead Thickness c 0.18 – 0.33 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-052B DS41213D-page 76 © 2007 Microchip Technology Inc.

PIC16F5X 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 1 2 b NOTE 1 e c A A2 φ A1 L1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 0.65 BSC Overall Height A – – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.20 Molded Package Width E1 5.00 5.30 5.60 Overall Length D 9.90 10.20 10.50 Foot Length L 0.55 0.75 0.95 Footprint L1 1.25 REF Lead Thickness c 0.09 – 0.25 Foot Angle φ 0° 4° 8° Lead Width b 0.22 – 0.38 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-073B © 2007 Microchip Technology Inc. DS41213D-page 77

PIC16F5X 40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L c b1 A1 b e eB Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 40 Pitch e .100 BSC Top to Seating Plane A – – .250 Molded Package Thickness A2 .125 – .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .590 – .625 Molded Package Width E1 .485 – .580 Overall Length D 1.980 – 2.095 Tip to Seating Plane L .115 – .200 Lead Thickness c .008 – .015 Upper Lead Width b1 .030 – .070 Lower Lead Width b .014 – .023 Overall Row Spacing § eB – – .700 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-016B DS41213D-page 78 © 2007 Microchip Technology Inc.

PIC16F5X 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 A α c φ β A1 A2 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 44 Lead Pitch e 0.80 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.30 0.37 0.45 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-076B © 2007 Microchip Technology Inc. DS41213D-page 79

PIC16F5X APPENDIX A: DATA SHEET REVISION HISTORY Revision D (04/2007) Changed PICmicro to PIC; Replaced Dev. Tool Section; Updated Package Marking Information and replaced Package Drawings (Rev. AP) DS41213D-page 80 © 2007 Microchip Technology Inc.

PIC16F5X A G Absolute Maximum Ratings GOTO...........................................................................19, 47 PIC1654/57.................................................................57 H PIC1659......................................................................58 ADDWF...............................................................................43 High-Performance RISC CPU..............................................1 ALU.......................................................................................7 I ANDLW...............................................................................43 ANDWF...............................................................................43 I/O Interfacing.....................................................................29 Applications...........................................................................5 I/O Ports.............................................................................29 Architectural Overview..........................................................7 I/O Programming Considerations.......................................31 Assembler ID Locations..................................................................37, 39 MPASM Assembler.....................................................54 INCF...................................................................................47 INCFSZ...............................................................................47 B INDF Register.....................................................................20 Block Diagram Value on Reset...........................................................24 On-Chip Reset Circuit.................................................24 Indirect Data Addressing....................................................20 PIC16F5X Series..........................................................8 Instruction Cycle.................................................................12 Timer0.........................................................................33 Instruction Flow/Pipelining..................................................12 TMR0/WDT Prescaler.................................................36 Instruction Set Summary....................................................41 Watchdog Timer..........................................................38 Internet Address.................................................................83 Brown-Out Protection Circuit..............................................27 IORLW................................................................................48 BSF.....................................................................................44 IORWF................................................................................48 BTFSC................................................................................44 L BTFSS................................................................................44 Loading of PC.....................................................................19 C M C Compilers MPLAB C18................................................................54 MCLR Reset MPLAB C30................................................................54 Register values on......................................................24 CALL.............................................................................19, 45 Memory Map Carry (C) bit....................................................................7, 17 PIC16F54...................................................................13 Clocking Scheme................................................................12 PIC16F57/59..............................................................13 CLRF...................................................................................45 Memory Organization.........................................................13 CLRW.................................................................................45 Microchip Internet Web Site................................................83 CLRWDT.............................................................................45 MOVF.................................................................................48 Code Protection............................................................37, 39 MOVLW..............................................................................48 COMF.................................................................................46 MOVWF..............................................................................49 Configuration Bits................................................................37 MPLAB ASM30 Assembler, Linker, Librarian.....................54 Customer Change Notification Service...............................83 MPLAB ICD 2 In-Circuit Debugger.....................................55 Customer Notification Service.............................................83 MPLAB ICE 2000 High-Performance Universal Customer Support...............................................................83 In-Circuit Emulator......................................................55 MPLAB Integrated Development Environment Software....53 D MPLAB PM3 Device Programmer......................................55 DC Characteristics MPLAB REAL ICE In-Circuit Emulator System..................55 Commercial.................................................................62 MPLINK Object Linker/MPLIB Object Librarian..................54 Extended.....................................................................61 N Industrial...............................................................60, 62 DECF..................................................................................46 NOP....................................................................................49 DECFSZ..............................................................................46 O Development Support.........................................................53 Option.................................................................................49 Device Reset Timer (DRT)..................................................27 Digit Carry (DC) bit..........................................................7, 17 Option Register...................................................................18 Value on Reset...........................................................24 DRT.....................................................................................27 Oscillator Configurations.....................................................21 E Oscillator Types Electrical Specifications HS...............................................................................21 PIC16F54/57...............................................................57 LP...............................................................................21 PIC16F59....................................................................58 RC..............................................................................21 Errata....................................................................................3 XT...............................................................................21 External Power-On Reset Circuit........................................25 P F PA0 bit................................................................................17 FSR Register......................................................................20 PA1 bit................................................................................17 Value on Reset (PIC16F54)........................................24 Paging................................................................................19 Value on Reset (PIC16F57)........................................24 PC.......................................................................................19 Value on Reset (PIC16F59)........................................24 Value on Reset...........................................................24 © 2007 Microchip Technology Inc. DS41213D-page 81

PIC16F5X PD bit............................................................................17, 23 T PICSTART Plus Development Programmer.......................56 Timer0 Pinout Description - PIC16F54..............................................9 Switching Prescaler Assignment................................36 Pinout Description - PIC16F57............................................10 Timer0 (TMR0) Module...............................................33 Pinout Description - PIC16F59............................................11 TMR0 register - Value on Reset.................................24 PORTA................................................................................29 TMR0 with External Clock..........................................35 Value on Reset...........................................................24 Timing Diagrams and Specifications PORTB................................................................................29 ....................................................................................63 Value on Reset...........................................................24 Timing Parameter Symbology and Load Conditions PORTC................................................................................29 ....................................................................................63 Value on Reset...........................................................24 TO bit............................................................................17, 23 PORTD TRIS....................................................................................51 Value on Reset...........................................................24 TRIS Registers...................................................................29 PORTE Value on Reset...........................................................24 Value on Reset...........................................................24 Power-down Mode..............................................................39 W Power-on Reset (POR).......................................................25 W Register Register values on......................................................24 Value on Reset...........................................................24 Prescaler.............................................................................35 Wake-up from Sleep.....................................................23, 39 Program Counter.................................................................19 Watchdog Timer (WDT)................................................37, 38 Program Memory Organization...........................................13 Period.........................................................................38 Program Verification/Code Protection.................................39 Programming Considerations.....................................38 Q Register Values on Reset...........................................24 WWW Address...................................................................83 Q cycles..............................................................................12 WWW, On-Line Support.......................................................3 R X RC Oscillator.......................................................................22 XORLW...............................................................................52 Reader Response...............................................................84 XORWF..............................................................................52 Read-Modify-Write..............................................................31 Register File Map Z PIC16F54....................................................................14 Zero (Z) bit......................................................................7, 17 PIC16F57....................................................................14 PIC16F59....................................................................15 Registers Special Function.........................................................16 Value on Reset...........................................................24 Reset...................................................................................23 Reset on Brown-out............................................................27 RETLW................................................................................49 RLF.....................................................................................50 RRF.....................................................................................50 S Sleep.......................................................................37, 39, 50 Software Simulator (MPLAB SIM).......................................54 Special Features of the CPU...............................................37 Special Function Registers.................................................16 Stack...................................................................................20 STATUS Register............................................................7, 17 Value on Reset...........................................................24 SUBWF...............................................................................51 SWAPF...............................................................................51 DS41213D-page 82 © 2007 Microchip Technology Inc.

PIC16F5X THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to (cid:129) Distributor or Representative customers. Accessible by using your favorite Internet (cid:129) Local Sales Office browser, the web site contains the following (cid:129) Field Application Engineer (FAE) information: (cid:129) Technical Support (cid:129) Product Support – Data sheets and errata, (cid:129) Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help (cid:129) General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com (cid:129) Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. DS41213D-page 83

PIC16F5X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16F5X Literature Number: DS41213D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41213D-page 84 © 2007 Microchip Technology Inc.

PIC16F5X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F54–I/P = Industrial temp, PDIP package Range b) PIC16F54T–I/SSG = Industrial temp, SSOP package (Pb -free), tape and reel c) PIC16F57–E/SP6 = Extended temp, Skinny Plastic DIP package (Pb-free) Device PIC16F54 – VDD range 2.0V to 5.5V PIC16F54T(1)– VDD range 2.0V to 5.5V d) PIC16F57T–E/SS = Extended temp, SSOP package, tape and reel PIC16F57 – VDD range 2.0V to 5.5V PIC16F57T(1)– VDD range 2.0V to 5.5V e) PIC16F54–I/SOG = Industrial temp, SOIC package (Pb-free) Temperature Range I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package SO = SOIC SS = SSOP P = PDIP SP = Skinny Plastic DIP (SPDIP)(2) Note 1: T = in tape and reel SOIC and SSOP SOG = SOIC (Pb-free) packages only. SSG = SOIC (Pb-free) PG = SOIC (Pb-free) 2: PIC16F57 only SPG = SOIC (Pb-free) Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F59–I/P = Industrial temp, PDIP package Range (Pb-free). b) PIC16F59T–I/PT = Industrial temp, TQFP package (Pb-free), tape and reel. Device PIC16F59 – VDD range 2.0V to 5.5V PIC16F59T(1)– VDD range 2.0V to 5.5V Temperature Range I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package P = PDIP PT = TQFP Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) Note 1: T = in tape and reel TQFP packages only. © 2007 Microchip Technology Inc. DS41213D-page 85

WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-4182-8400 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-4182-8422 Fax: 43-7242-2244-393 Tel: 480-792-7200 Habour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://support.microchip.com Web Address: Fax: 852-2401-3431 India - Pune France - Paris www.microchip.com Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 ADtullaunthta, GA Fax: 61-2-9868-6755 Japan - Yokohama Germany - Munich Tel: 678-957-9614 China - Beijing Tel: 81-45-471- 6166 Tel: 49-89-627-144-0 Tel: 86-10-8528-2100 Fax: 49-89-627-144-44 Fax: 678-957-1455 Fax: 81-45-471-6122 Fax: 86-10-8528-2104 Italy - Milan Boston Korea - Gumi China - Chengdu Tel: 39-0331-742611 Westborough, MA Tel: 82-54-473-4301 Tel: 774-760-0087 Tel: 86-28-8665-5511 Fax: 82-54-473-4302 Fax: 39-0331-466781 Fax: 774-760-0088 Fax: 86-28-8665-7889 Korea - Seoul Netherlands - Drunen Chicago China - Fuzhou Tel: 82-2-554-7200 Tel: 31-416-690399 Itasca, IL Tel: 86-591-8750-3506 Fax: 82-2-558-5932 or Fax: 31-416-690340 Tel: 630-285-0071 Fax: 86-591-8750-3521 82-2-558-5934 Spain - Madrid Fax: 630-285-0075 China - Hong Kong SAR Malaysia - Penang Tel: 34-91-708-08-90 Dallas Tel: 852-2401-1200 Tel: 60-4-646-8870 Fax: 34-91-708-08-91 Addison, TX Fax: 852-2401-3431 Fax: 60-4-646-5086 UK - Wokingham Tel: 972-818-7423 China - Qingdao Philippines - Manila Tel: 44-118-921-5869 Fax: 972-818-2924 Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Fax: 44-118-921-5820 Detroit Fax: 86-532-8502-7205 Fax: 63-2-634-9069 Farmington Hills, MI China - Shanghai Singapore Tel: 248-538-2250 Tel: 86-21-5407-5533 Tel: 65-6334-8870 Fax: 248-538-2260 Fax: 86-21-5407-5066 Fax: 65-6334-8850 Kokomo China - Shenyang Taiwan - Hsin Chu Kokomo, IN Tel: 86-24-2334-2829 Tel: 886-3-572-9526 Tel: 765-864-8360 Fax: 86-24-2334-2393 Fax: 886-3-572-6459 Fax: 765-864-8387 China - Shenzhen Taiwan - Kaohsiung Los Angeles Tel: 86-755-8203-2660 Tel: 886-7-536-4818 Mission Viejo, CA Fax: 86-755-8203-1760 Fax: 886-7-536-4803 Tel: 949-462-9523 China - Shunde Taiwan - Taipei Fax: 949-462-9608 Tel: 86-757-2839-5507 Tel: 886-2-2500-6610 Santa Clara Fax: 86-757-2839-5571 Fax: 886-2-2508-0102 Santa Clara, CA China - Wuhan Thailand - Bangkok Tel: 408-961-6444 Tel: 86-27-5980-5300 Tel: 66-2-694-1351 Fax: 408-961-6445 Fax: 86-27-5980-5118 Fax: 66-2-694-1350 Toronto China - Xian Mississauga, Ontario, Tel: 86-29-8833-7250 Canada Fax: 86-29-8833-7256 Tel: 905-673-0699 Fax: 905-673-6509 12/08/06 DS41213D-page 86 © 2007 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16F59-I/PT PIC16F59-E/PT PIC16F57-E/SP PIC16F59T-I/PT PIC16F57-E/SS PIC16F57-E/SO PIC16F54T- I/SO PIC16F57T-I/SS PIC16F54T-I/SS PIC16F57T-I/SO PIC16F57-I/P PIC16F54-E/P PIC16F54-E/SS PIC16F57- E/P PIC16F54-I/P PIC16F57-I/SO PIC16F57-I/SS PIC16F57-I/PG PIC16F57-I/SP PIC16F57T-E/SO PIC16F57T- E/SS PIC16F54T-E/SS PIC16F54T-E/SO PIC16F57-I/SOG PIC16F57-I/SSG PIC16F54-I/SSG PIC16F54-I/SOG PIC16F59-I/P PIC16F54-E/SO PIC16F59-E/P PIC16F54-I/SS PIC16F54-I/SO PIC16F54-I/PG