PIC16F526 Data Sheet 14-Pin, 8-Bit Flash Microcontroller  2010 Microchip Technology Inc. DS41326E

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-355-4 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41326E-page 2  2010 Microchip Technology Inc.

PIC16F526 14-Pin, 8-Bit Flash Microcontroller High-Performance RISC CPU: Low-Power Features/CMOS Technology: • Only 33 Single-Word Instructions • Standby current: • All Single-Cycle Instructions except for Program - 100nA @ 2.0V, typical Branches which are Two-Cycle • Operating current: - 11A @ 32kHz, 2.0V, typical • Two-Level Deep Hardware Stack - 175A @ 4MHz, 2.0V, typical • Direct, Indirect and Relative Addressing modes • Watchdog Timer current: for Data and Instructions - 1A @ 2.0V, typical • Operating Speed: - 7A @ 5.0V, typical - DC – 20MHz crystal oscillator • High Endurance Program and Flash Data Memory - DC – 200ns instruction cycle cells: • On-chip Flash Program Memory: - 100,000 write Program Memory endurance - 1024 x 12 - 1,000,000 write Flash Data Memory endurance • General Purpose Registers (SRAM): - Program and Flash Data retention: >40 years - 67 x 8 • Fully Static Design • Flash Data Memory: • Wide Operating Voltage Range: 2.0V to 5.5V: - 64 x 8 - Wide temperature range - Industrial: -40C to +85C Special Microcontroller Features: - Extended: -40C to +125C • 8MHz Precision Internal Oscillator: Peripheral Features: - Factory calibrated to ±1% • In-Circuit Serial Programming™ (ICSP™) • 12 I/O Pins: • In-Circuit Debugging (ICD) Support - 11 I/O pins with individual direction control - 1 input-only pin • Power-On Reset (POR) - High current sink/source for direct LED drive • Device Reset Timer (DRT) - Wake-up on change • Watchdog Timer (WDT) with Dedicated On-Chip - Weak pull-ups RC Oscillator for Reliable Operation • 8-bit Real-time Clock/Counter (TMR0) with 8-bit • Programmable Code Protection Programmable Prescaler • Multiplexed MCLR Input Pin • Two Analog Comparators: • Internal Weak Pull-ups on I/O Pins - Comparator inputs and output accessible externally • Power-Saving Sleep mode - One comparator with 0.6V fixed on-chip • Wake-Up from Sleep on Pin Change absolute voltage reference (VREF) • Selectable Oscillator Options: - One comparator with programmable on-chip - INTRC: 4 MHz or 8MHz precision Internal voltage reference (VREF) RC oscillator • Analog-to-Digital (A/D) Converter: - EXTRC: External low-cost RC oscillator - 8-bit resolution - XT: Standard crystal/resonator - 3-channel external programmable inputs - HS: High-speed crystal/resonator - 1-channel internal input to internal absolute - LP: Power-saving, low-frequency crystal 0.6 voltage reference - EC: High-speed external clock input Program Data Memory Memory 8-bit A/D Device I/O Comparators Timers 8-bit Channels Flash Flash (words) SRAM (bytes) (bytes) PIC16F526 1024 67 64 12 2 1 3  2010 Microchip Technology Inc. DS41326E-page 3

PIC16F526 FIGURE 1-1: 14-PIN PDIP, SOIC, TSSOP DIAGRAM VDD 1 14 VSS RB5/OSC1/CLKIN 2 13 RB0/C1IN+/AN0/ICSPDAT RB4/OSC2/CLKOUT 3 6 12 RB1/C1IN-/AN1/ICSPCLK 2 RB3/MCLR/VPP 4 F5 11 RB2/C1OUT/AN2 6 RC5/T0CKI 5 1 10 RC0/C2IN+ C RC4/C2OUT 6 PI 9 RC1/C2IN- RC3 7 8 RC2/CVREF FIGURE 1-2: 16-PIN QFN DIAGRAM DD C C ND V N N G 16 15 14 13 RB5/OSC1/CLKIN 1 12 RB0/C1IN+/AN0/ICSPDAT 6 RB4/OSC2/CLKOUT 2 52 11 RB1/C1IN-/AN1/ICSPCLK F RB3/MCLR/VPP 3 16 10 RB2/C1OUT/AN2 C RC5/T0CKI 4 PI 9 RC0/C2IN+ 5 6 7 8 RC4/C2OUT RC3 RC2/CVREF RC1/C2IN- DS41326E-page 4  2010 Microchip Technology Inc.

PIC16F526 Table of Contents 1.0 General Description..................................................................................................................................................................... 7 2.0 PIC16F526 Device Varieties...................................................................................................................................................... 9 3.0 Architectural Overview.............................................................................................................................................................. 11 4.0 Memory Organization................................................................................................................................................................ 15 5.0 Flash Data Memory Control...................................................................................................................................................... 23 6.0 I/O Port...................................................................................................................................................................................... 27 7.0 Timer0 Module and TMR0 Register.......................................................................................................................................... 37 8.0 Special Features of the CPU..................................................................................................................................................... 43 9.0 Analog-to-Digital (A/D) Converter.............................................................................................................................................. 59 10.0 Comparator(s)........................................................................................................................................................................... 63 11.0 Comparator Voltage Reference Module.................................................................................................................................... 69 12.0 Instruction Set Summary........................................................................................................................................................... 71 13.0 Development Support................................................................................................................................................................ 79 14.0 Electrical Characteristics........................................................................................................................................................... 83 15.0 DC and AC Characteristics Graphs and Charts........................................................................................................................ 97 16.0 Packaging Information............................................................................................................................................................. 107 The Microchip Web Site.................................................................................................................................................................... 115 Customer Change Notification Service............................................................................................................................................. 115 Customer Support............................................................................................................................................................................. 115 Reader Response............................................................................................................................................................................. 116 Index..................................................................................................................................................................................................117 Product Identification System........................................................................................................................................................... 119 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Micro- chip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit- erature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.  2010 Microchip Technology Inc. DS41326E-page 5

PIC16F526 NOTES: DS41326E-page 6  2010 Microchip Technology Inc.

PIC16F526 1.0 GENERAL DESCRIPTION 1.1 Applications The PIC16F526 device from Microchip Technology is The PIC16F526 device fits in applications ranging from low-cost, high-performance, 8-bit, fully-static, Flash- personal care appliances and security systems to low- based CMOS microcontrollers. It employs a RISC power remote transmitters/receivers. The Flash architecture with only 33 single-word/single-cycle technology makes customizing application programs instructions. All instructions are single cycle (200s) (transmitter codes, appliance settings, receiver except for program branches, which take two cycles. frequencies, etc.) extremely fast and convenient. The The PIC16F526 device delivers performance an order small footprint packages, for through hole or surface of magnitude higher than their competitors in the same mounting, make these microcontrollers perfect for price category. The 12-bit wide instructions are highly applications with space limitations. Low cost, low symmetrical, resulting in a typical 2:1 code power, high performance, ease of use and I/O flexibility compression over other 8-bit microcontrollers in its make the PIC16F526 device very versatile even in class. The easy-to-use and easy to remember areas where no microcontroller use has been instruction set reduces development time significantly. considered before (e.g., timer functions, logic and PLDs in larger systems and coprocessor applications). The PIC16F526 product is equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. There are four oscillator configurations to choose from, including INTRC Internal Oscillator mode and the power-saving LP (Low-Power) Oscillator mode. Power-Saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC16F526 device is available in the cost-effective Flash programmable version, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibility. The PIC16F526 product is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM® PC and compatible machines. TABLE 1-1: FEATURES AND MEMORY OF PIC16F526 PIC16F526 Clock Maximum Frequency of Operation (MHz) 20 Memory Flash Program Memory 1024 SRAM Data Memory (bytes) 67 Flash Data Memory (bytes) 64 Peripherals Timer Module(s) TMR0 Wake-up from Sleep on Pin Change Yes Features I/O Pins 11 Input Pins 1 Internal Pull-ups Yes In-Circuit Serial ProgrammingTM Yes Number of Instructions 33 Packages 14-pin PDIP, SOIC, TSSOP, QFN The PIC16F526 device has Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. The PIC16F526 device uses serial programming with data pin RB0 and clock pin RB1.  2010 Microchip Technology Inc. DS41326E-page 7

PIC16F526 NOTES: DS41326E-page 8  2010 Microchip Technology Inc.

PIC16F526 2.0 PIC16F526 DEVICE VARIETIES 2.2 Serialized Quick Turn ProgrammingSM (SQTPSM) Devices A variety of packaging options are available. Depending on application and production Microchip offers a unique programming service, where requirements, the proper device option can be selected a few user-defined locations in each device are using the information in this section. When placing programmed with different serial numbers. The serial orders, please use the PIC16F526 Product numbers may be random, pseudo-random or Identification System at the back of this data sheet to sequential. specify the correct part number. Serial programming allows each device to have a unique number, which can serve as an entry code, 2.1 Quick Turn Programming (QTP) password or ID number. Devices Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.  2010 Microchip Technology Inc. DS41326E-page 9

PIC16F526 NOTES: DS41326E-page 10  2010 Microchip Technology Inc.

PIC16F526 3.0 ARCHITECTURAL OVERVIEW The PIC16F526 device contains an 8-bit ALU and working register. The ALU is a general purpose arith- The high performance of the PIC16F526 device can metic unit. It performs arithmetic and Boolean functions be attributed to a number of architectural features between data in the working register and any register commonly found in RISC microprocessors. To begin file. with, the PIC16F526 device uses a Harvard The ALU is 8 bits wide and capable of addition, subtrac- architecture in which program and data are accessed tion, shift and logical operations. Unless otherwise on separate buses. This improves bandwidth over mentioned, arithmetic operations are two’s comple- traditional von Neumann architectures where program ment in nature. In two-operand instructions, one and data are fetched on the same bus. Separating operand is typically the W (working) register. The other program and data memory further allows instructions operand is either a file register or an immediate to be sized differently than the 8-bit wide data word. constant. In single operand instructions, the operand is Instruction opcodes are 12 bits wide, making it either the W register or a file register. possible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit The W register is an 8-bit working register used for ALU instruction in a single cycle. A two-stage pipeline operations. It is not an addressable register. overlaps fetch and execution of instructions. Depending on the instruction executed, the ALU may Consequently, all instructions (33) execute in a single affect the values of the Carry (C), Digit Carry (DC) and cycle (200ns @ 20MHz, 1s @ 4MHz) except for Zero (Z) bits in the STATUS register. The C and DC bits program branches. operate as a borrow and digit borrow out bit, Table3-1 below lists memory supported by the respectively, in subtraction. See the SUBWF and ADDWF PIC16F526 device. instructions for examples. A simplified block diagram is shown in Figure3-2, with TABLE 3-1: PIC16F526 MEMORY the corresponding device pins described in Table3-2. Program Data Memory Memory Device Flash SRAM Flash (words) (bytes) (bytes) PIC16F526 1024 67 64 The PIC16F526 device can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC16F526 device has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any Addressing mode. This sym- metrical nature and lack of “special optimal situations” make programming with the PIC16F526 device simple, yet efficient. In addition, the learning curve is reduced significantly.  2010 Microchip Technology Inc. DS41326E-page 11

PIC16F526 FIGURE 3-1: PIC16F526 BLOCK DIAGRAM 11 8 Data Bus PORTB Flash Program Program Counter Memory RB0/ICSPDAT 1K x 12 RB1/ICSPCLK Flash Data RAM RB2 Memory STACK1 67 RB3/MCLR/VPP 64x8 STACK2 bytes RB4/OSC2/CLKOUT File RB5/OSC1/CLKIN Registers Program Bus 12 RAM Addr (1) 9 PORTC Addr MUX Instruction Reg RC0 Direct Addr 5 Indirect RC1 5-7 Addr RC2 RC3 FSR Reg RC4 RC5/T0CKI STATUS Reg 8 C1IN+ 3 Co mparator 1 C1IN- Device Reset MUX C1OUT Timer Instruction VREF Power-on Decode and Reset ALU C2IN+ Control Comparator 2 C2IN- Watchdog 8 C2OUT Timer OOSSCC21//CCLLKKOINUT GeTnimeriantgion InteCrlnoaclk RC W Reg CVREF CVREF CVREF Timer0 MCLR AN0 VDD, VSS 8-bit ADC AN1 AN2 VREF DS41326E-page 12  2010 Microchip Technology Inc.

PIC16F526 TABLE 3-2: PIC16F526 PINOUT DESCRIPTION Input Output Name Function Description Type Type RB0//C1IN+/AN0/ RB0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal ICSPDAT weak pull-up and wake-up from Sleep on pin change. C1IN+ AN — Comparator 1 input. AN0 AN — ADC channel input. ICSPDAT ST CMOS ICSP™ mode Schmitt Trigger. RB1/C1IN-/AN1/ RB1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal ICSPCLK weak pull-up and wake-up from Sleep on pin change. C1IN- AN — Comparator 1 input. AN1 AN — ADC channel input. ICSPCLK ST CMOS ICSP mode Schmitt Trigger. RB2/C1OUT/AN2 RB2 TTL CMOS Bidirectional I/O pin. C1OUT — CMOS Comparator 1 output. AN2 AN — ADC channel input. RB3/MCLR/VPP RB3 TTL — Input pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. MCLR ST — Master Clear (Reset). When configured as MCLR, this pin is an active-low Reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation or the device will enter Programming mode. Weak pull-up always on if configured as MCLR. VPP HV — Programming voltage input. RB4/OSC2/CLKOUT RB4 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. OSC2 — XTAL Oscillator crystal output. Connections to crystal or resonator in Crystal Oscillator mode (XT, HS and LP modes only, PORTB in other modes). CLKOUT — CMOS EXTRC/INTRC CLKOUT pin (FOSC/4). RB5/OSC1/CLKIN RB5 TTL CMOS Bidirectional I/O pin. OSC1 XTAL — Oscillator crystal input. CLKIN ST — External clock source input. RC0/C2IN+ RC0 TTL CMOS Bidirectional I/O port. C2IN+ AN — Comparator 2 input. RC1/C2IN- RC1 TTL CMOS Bidirectional I/O port. C2IN- AN — Comparator 2 input. RC2/CVREF RC2 TTL CMOS Bidirectional I/O port. CVREF — AN Programmable Voltage Reference output. RC3 RC3 TTL CMOS Bidirectional I/O port. RC4/C2OUT RC4 TTL CMOS Bidirectional I/O port. C2OUT — CMOS Comparator 2 output. RC5/T0CKI RC5 TTL CMOS Bidirectional I/O port. T0CKI ST — Timer0 Schmitt Trigger input pin. VDD VDD — P Positive supply for logic and I/O pins. VSS VSS — P Ground reference for logic and I/O pins. Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input, ST = Schmitt Trigger input, HV = High Voltage  2010 Microchip Technology Inc. DS41326E-page 13

PIC16F526 3.1 Clocking Scheme/Instruction 3.2 Instruction Flow/Pipelining Cycle An instruction cycle consists of four Q cycles (Q1, Q2, The clock input (OSC1/CLKIN pin) is internally divided Q3 and Q4). The instruction fetch and execute are by four to generate four non-overlapping quadrature pipelined such that fetch takes one instruction cycle, clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC while decode and execute take another instruction is incremented every Q1 and the instruction is fetched cycle. However, due to the pipelining, each instruction from program memory and latched into the instruction effectively executes in one cycle. If an instruction register in Q4. It is decoded and executed during the causes the PC to change (e.g., GOTO), then two cycles following Q1 through Q4. The clocks and instruction are required to complete the instruction (Example3-1). execution flow is shown in Figure3-2 and Example3-1. A fetch cycle begins with the PC incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 1 PC + 2 Fetch INST (PC) Execute INST (PC – 1) Fetch INST (PC + 1) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 03H Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTB, BIT1 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. DS41326E-page 14  2010 Microchip Technology Inc.

PIC16F526 4.0 MEMORY ORGANIZATION FIGURE 4-1: MEMORY MAP The PIC16F526 memories are organized into program memory and data memory (SRAM).The self-writable 000h On-chip User portion of the program memory called Flash data y Program memory is located at addresses at 400h-43Fh. All more Memory (Page 0) PFlraosghr amme mmoordye wcoormk mona ntdhse tFhlaats hw doarkta o mn etmheo rny.o rTmhaisl er MeSpac On-chip User 12F00Fhh includes bulk erase, row/column/cycling toggles, Load s Program U and Read data commands (Refer to Section5.0 Memory (Page 1) 3FEh “Flash Data Memory Control” for more details). For Reset Vector 3FFh devices with more than 512 bytes of program memory, ory 400h a paging scheme is used. Program memory pages are emce accessed using one STATUS register bit. For the Mpa Flash Data Memory a S PIC16F526, with data memory register files of more at 43Fh D 440h than 32 registers, a banking scheme is used. Data User ID Locations 443h memory banks are accessed using the File Select Backup OSCCAL 444h Register (FSR). Locations 447h y 448h 4.1 Program Memory Organization for or m the PIC16F526 Me Reserved The PIC16F526 device has an 11-bit Program Counter ation Space 49Fh (PC) capable of addressing a 2K x 12 program memory ur 4A0h g space. Program memory is partitioned into user memory, nfi Unimplemented data memory and configuration memory spaces. Co 7FEh Configuration Word 7FFh The user memory space is the on-chip user program memory. As shown in Figure4-1, it extends from 0x000 to 0x3FF and partitions into pages, including Reset vector at address 0x3FF. The data memory space is the Flash data memory block and is located at addresses PC=400h-43Fh. All Program mode commands that work on the normal Flash memory work on the Flash data memory block. This includes bulk erase, Load and Read data commands. The configuration memory space extends from 0x440 to 0x7FF. Locations from 0x448 through 0x49F are reserved. The user ID locations extend from 0x440 through 0x443. The Backup OSCCAL locations extend from 0x444 through 0x447. The Configuration Word is physically located at 0x7FF. Refer to “PIC16F526 Memory Programming Specification” (DS41317) for more details.  2010 Microchip Technology Inc. DS41326E-page 15

PIC16F526 4.2 Data Memory (SRAM and FSRs) 4.2.1 GENERAL PURPOSE REGISTER FILE Data memory is composed of registers or bytes of SRAM. Therefore, data memory for a device is The General Purpose Register file is accessed, either specified by its register file. The register file is divided directly or indirectly, through the File Select Register into two functional groups: Special Function Registers (FSR). See Section4.8 “Indirect Data Addressing: (SFR) and General Purpose Registers (GPR). INDF and FSR Registers”. The Special Function Registers are registers used by 4.2.2 SPECIAL FUNCTION REGISTERS the CPU and peripheral functions for controlling The Special Function Registers (SFRs) are registers desired operations of the PIC16F526. See Figure4-1 used by the CPU and peripheral functions to control the for details. operation of the device (Table4-1). The PIC16F526 register file is composed of 16 Special The Special Function Registers can be classified into Function Registers and 67 General Purpose Registers. two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. FIGURE 4-2: REGISTER FILE MAP FSR<6:5> 00 01 10 11 File Address 20h 40h 60h 00h INDF(1) INDF(1) INDF(1) INDF(1) 01h TMR0 EECON TMR0 EECON 02h PCL PCL PCL PCL 03h STATUS STATUS STATUS STATUS 04h FSR FSR FSR FSR 05h OSCCAL EEDATA OSCCAL EEDATA 06h PORTB EEADR PORTB EEADR 07h POR TC POR TC POR TC PO RTC 08h CM1CON0 CM1CON0 CM1CON0 CM1CON0 09h ADCON0 ADCON0 ADCON0 ADCON0 0Ah ADRES ADRES ADRES ADRES 0Bh CM2CON0 CM2CON0 CM2CON0 CM2CON0 0Ch VRCON VRCON VRCON VRCON 0Dh General Addresses map back to Purpose addresses in Bank 0. 0Fh Registers 2Fh 4Fh 6Fh 10h 30h 50h 70h General General General General Purpose Purpose Purpose Purpose Registers Registers Registers Registers 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: Not a physical register. See Section4.8 “Indirect Data Addressing: INDF and FSR Registers”. DS41326E-page 16  2010 Microchip Technology Inc.

PIC16F526 TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on Page # Reset N/A TRIS — — I/O Control Register (PORTB, PORTC) --11 1111 27 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 19 00h INDF Uses contents of FSR to Address Data Memory (not a physical register) xxxx xxxx 22 01h/41h TMR0 Timer0 Module Register xxxx xxxx 37 02h(1) PCL Low order 8 bits of PC 1111 1111 21 03h STATUS RBWUF CWUF PA0 TO PD Z DC C 0001 1xxx 18 04h FSR Indirect Data Memory Address Pointer 100x xxxx 22 05h/45h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 20 06h/46h PORTB — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx 27 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx 28 08h CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU q111 1111 63 09h ADCON0 ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON 1111 1100 61 0Ah ADRES ADC Conversion Result xxxx xxxx 62 0Bh CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU q111 1111 64 0Ch VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 001- 1111 69 21h/61h EECON — — — FREE WRERR WREN WR RD ---0 x000 23 25h/65h EEDATA SELF READ/WRITE DATA xxxx xxxx 23 26h/66h EEADR — — SELF READ/WRITE ADDRESS --xx xxxx 23 Legend: x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable), q = value depends on condition. Shaded cells = unimplemented or unused Note 1: The upper byte of the Program Counter is not directly accessible. See Section4.6 “Program Counter” for an explanation of how to access these bits.  2010 Microchip Technology Inc. DS41326E-page 17

PIC16F526 4.3 STATUS Register For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register This register contains the arithmetic status of the ALU, as 000u u1uu (where u = unchanged). the Reset status and the page preselect bit. Therefore, it is recommended that only BCF, BSF and The STATUS register can be the destination for any MOVWF instructions be used to alter the STATUS instruction, as with any other register. If the STATUS register. These instructions do not affect the Z, DC or C register is the destination for an instruction that affects bits from the STATUS register. For other instructions the Z, DC or C bits, then the write to these three bits is which do affect Status bits, see Section12.0 disabled. These bits are set or cleared according to the “Instruction Set Summary”. device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 4-1: STATUS: STATUS REGISTER R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x RBWUF CWUF PA0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBWUF: Wake-up from Sleep on Pin Change bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 CWUF: Wake-up from Sleep on Comparator Change bit 1 = Reset due to wake-up from Sleep on comparator change 0 = After power-up or other Reset bit 5 PA0: Program Page Preselect bit 1 = Page 1 (000h-1FFh) 0 = Page 0 (200h-3FFh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred bit 0 C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred DS41326E-page 18  2010 Microchip Technology Inc.

PIC16F526 4.4 OPTION Register The OPTION register is a 8-bit wide, write-only register, Note: If TRIS bit is set to ‘0’, the wake-up on which contains various control bits to configure the change and pull-up functions are disabled Timer0/WDT prescaler and Timer0. for that pin (i.e., note that TRIS overrides By executing the OPTION instruction, the contents of Option control of RBPU and RBWU). the W register will be transferred to the OPTION register. A Reset sets the OPTION <7:0> bits. REGISTER 4-2: OPTION: OPTION REGISTER W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 RBWU RBPU T0CS(1) T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBWU: Enable Wake-up On Pin Change bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 6 RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 5 T0CS: Timer0 Clock Source Select bit(1) 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Note 1: If the T0CS bit is set to ‘1’, it will override the TRIS function on the T0CKI pin.  2010 Microchip Technology Inc. DS41326E-page 19

PIC16F526 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the 8MHz internal oscillator macro. It contains 7 bits of calibration that uses a two’s complement scheme for controlling the oscillator speed. See Register4-3 for details. REGISTER 4-3: OSCCAL: OSCILLATOR CALIBRATION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 CAL<6:0>: Oscillator Calibration bits 0111111 = Maximum frequency • • • 0000001 0000000 = Center frequency 1111111 • • • 1000000 = Minimum frequency bit 0 Unimplemented: Read as ‘0’ DS41326E-page 20  2010 Microchip Technology Inc.

PIC16F526 4.6 Program Counter 4.6.1 EFFECTS OF RESET As a program instruction is executed, the Program The PC is set upon a Reset, which means that the PC Counter (PC) will contain the address of the next addresses the last location in the last page (i.e., the program instruction to be executed. The PC value is oscillator calibration instruction). After executing increased by one every instruction cycle, unless an MOVLW XX, the PC will roll over to location 00h and instruction changes the PC. begin executing user code. For a GOTO instruction, bits 8:0 of the PC are provided The STATUS register page preselect bits are cleared by the GOTO instruction word. The Program Counter upon a Reset, which means that page0 is pre-selected. (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS Therefore, upon a Reset, a GOTO instruction will register provides page information to bit 9 of the PC automatically cause the program to jump to page0 until (Figure4-3). the value of the page bits is altered. For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are 4.7 Stack provided by the instruction word. However, PC<8> The PIC16F526 device has a 2-deep, 12-bit wide does not come from the instruction word, but is always hardware PUSH/POP stack. cleared (Figure4-3). A CALL instruction will PUSH the current value of Stack 1 Instructions where the PCL is the destination, or modify into Stack 2 and then PUSH the current PC value, incre- PCL instructions, include MOVWF PCL, ADDWF PCL mented by one, into Stack Level 1. If more than two and BSF PCL,5. sequential CALLs are executed, only the most recent two Note: Because bit 8 of the PC is cleared in the return addresses are stored. CALL instruction or any modify PCL A RETLW instruction will POP the contents of Stack instruction, all subroutine calls or com- Level 1 into the PC and then copy Stack Level 2 puted jumps are limited to the first 256 contents into Stack Level 1. If more than two sequential locations of any program memory page RETLWs are executed, the stack will be filled with the (512 words long). address previously stored in Stack Level 2. Note that the Wregister will be loaded with the literal value FIGURE 4-3: LOADING OF PC specified in the instruction. This is particularly useful for BRANCH INSTRUCTIONS the implementation of data look-up tables within the program memory. GOTO Instruction Note1: There are no Status bits to indicate Stack 10 9 8 7 0 Overflows or Stack Underflow conditions. PC PCL 2: There are no instruction mnemonics called PUSH or POP. These are actions Instruction Word that occur from the execution of the CALL PA0 and RETLW instructions. 7 0 Status CALL or Modify PCL Instruction 10 9 8 7 0 PC PCL Instruction Word Reset to ‘0’ PA0 7 0 Status  2010 Microchip Technology Inc. DS41326E-page 21

PIC16F526 4.8 Indirect Data Addressing: INDF A simple program to clear RAM locations 10h-1Fh and FSR Registers using indirect addressing is shown in Example4-1. The INDF Register is not a physical register. EXAMPLE 4-1: HOW TO CLEAR RAM Addressing INDF actually addresses the register USING INDIRECT whose address is contained in the FSR Register (FSR ADDRESSING is a pointer). This is indirect addressing. MOVLW 0x10 ;initialize pointer Reading INDF itself indirectly (FSR = 0) will produce MOVWF FSR ;to RAM 00h. Writing to the INDF Register indirectly results in a NEXT CLRF INDF ;clear INDF no-operation (although Status bits may be affected). ;register The FSR is an 8-bit wide register. It is used in INCF FSR,F ;inc pointer conjunction with the INDF Register to indirectly BTFSC FSR,4 ;all done? GOTO NEXT ;NO, clear next address the data memory area. CONTINUE The FSR<4:0> bits are used to select data memory : ;YES, continue addresses 00h to 1Fh. : FSR<6:5> are the bank select bits and are used to select the bank to be addressed (00 = Bank 0, 01=Bank 1, 10 = Bank 2, 11 = Bank 3). FSR<7> is unimplemented and read as ‘1’. FIGURE 4-4: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing (FSR) (opcode) (FSR) 6 5 4 3 2 1 0 6 5 4 3 2 1 0 bank select location select bank location select select 00 01 10 11 00h Data 0Ch Memory(1) 0Dh Addresses map back to addresses in Bank 0. 0Fh 2Fh 4Fh 6Fh 10h 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register map detail see Figure4-1. DS41326E-page 22  2010 Microchip Technology Inc.

PIC16F526 5.0 FLASH DATA MEMORY 3. Perform a row erase of the row of interest. CONTROL 4. Write the new byte of data and any saved bytes back to the appropriate addresses in Flash data The Flash data memory is readable and writable during memory. normal operation (full VDD range). This memory is not To prevent accidental corruption of the Flash data directly mapped in the register file space. Instead, it is memory, an unlock sequence is required to initiate a indirectly addressed through the Special Function write or erase cycle. This sequence requires that the bit Registers (SFRs). set instructions used to configure the EECON register happen exactly as shown in Example2 and Example3, 5.1 Reading Flash Data Memory depending on the operation requested. To read a Flash data memory location the user must: 5.2.1 ERASING FLASH DATA MEMORY • Write the EEADR register A row must be manually erased before writing new • Set the RD bit of the EECON register data. The following sequence must be performed for a The value written to the EEADR register determines single row erase. which Flash data memory location is read. Setting the 1. Load EEADR with an address in the row to be RD bit of the EECON register initiates the read. Data erased. from the Flash data memory read is available in the 2. Set the FREE bit to enable the erase. EEDATA register immediately. The EEDATA register 3. Set the WREN bit to enable write access to the will hold this value until another read is initiated or it is array. modified by a write operation. Program execution is suspended while the read cycle is in progress. 4. Set the WR bit to initiate the erase cycle. Execution will continue with the instruction following the If the WREN bit is not set in the instruction cycle after one that sets the WR bit. See Example1 for sample the FREE bit is set, the FREE bit will be cleared in code. hardware. If the WR bit is not set in the instruction cycle after the EXAMPLE 1: READING FROM FLASH WREN bit is set, the WREN bit will be cleared in DATA MEMORY hardware. BANKSEL EEADR ; Sample code that follows this procedure is included in MOVF DATA_EE_ADDR, W ; Example2. MOVWF EEADR ;Data Memory Program execution is suspended while the erase cycle ;Address to read is in progress. Execution will continue with the BANKSEL EECON1 ; instruction following the one that sets the WR bit. BSF EECON, RD ;EE Read EXAMPLE 2: ERASING A FLASH DATA MOVF EEDATA, W ;W = EEDATA MEMORY ROW BANKSEL EEADR Note: Only a BSF command will work to enable the MOVLW EE_ADR_ERASE ; LOAD ADDRESS OF ROW TO Flash data memory read documented in ; ERASE Example1. No other sequence of MOVWF EEADR ; commands will work, no exceptions. BSF EECON,FREE ; SELECT ERASE BSF EECON,WREN ; ENABLE WRITES 5.2 Writing and Erasing Flash Data BSF EECON,WR ; INITITATE ERASE Memory Flash data memory is erased one row at a time and Note1: The FREE bit may be set by any com- written one byte at a time. The 64-byte array is made mand normally used by the core. How- up of eight rows. A row contains eight sequential bytes. ever, the WREN and WR bits can only be Row boundaries exist every eight bytes. set using a series of BSF commands, as Generally, the procedure to write a byte of data to Flash documented in Example1. No other data memory is: sequence of commands will work, no exceptions. 1. Identify the row containing the address where the byte will be written. 2: Bits <5:3> of the EEADR register indicate which row is to be erased. 2. If there is other information in that row that must be saved, copy those bytes from Flash data memory to RAM.  2010 Microchip Technology Inc. DS41326E-page 23

PIC16F526 5.2.2 WRITING TO FLASH DATA MEMORY Note1: Only a series of BSF commands will work Once a cell is erased, new data can be written. to enable the memory write sequence Program execution is suspended during the write cycle. documented in Example2. No other The following sequence must be performed for a single sequence of commands will work, no byte write. exceptions. 1. Load EEADR with the address. 2: For reads, erases and writes to the Flash 2. Load EEDATA with the data to write. data memory, there is no need to insert a NOP into the user code as is done on mid- 3. Set the WREN bit to enable write access to the range devices. The instruction immediately array. following the “BSF EECON,WR/RD” will be 4. Set the WR bit to initiate the erase cycle. fetched and executed properly. If the WR bit is not set in the instruction cycle after the WREN bit is set, the WREN bit will be cleared in 5.3 Write Verify hardware. Depending on the application, good programming Sample code that follows this procedure is included in practice may dictate that data written to the Flash data Example3. memory be verified. Example4 is an example of a write verify. EXAMPLE 3: WRITING A FLASH DATA MEMORY ROW EXAMPLE 4: WRITE VERIFY OF FLASH BANKSEL EEADR DATA MEMORY MOVLW EE_ADR_WRITE ; LOAD ADDRESS MOVWF EEADR ; MOVF EEDATA, W ;EEDATA has not changed MOVLW EE_DATA_TO_WRITE ; LOAD DATA ;from previous write MOVWF EEDATA ; INTO EEDATA REGISTER BSF EECON, RD ;Read the value written BSF EECON,WREN ; ENABLE WRITES XORWF EEDATA, W ; BSF EECON,WR ; INITITATE ERASE BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error ;Yes, continue REGISTER 5-1: EEDATA: FLASH DATA REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EEDATA7 EEDATA6 EEDATA5 EEDATA4 EEDATA3 EEDATA2 EEDATA1 EEDATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EEDATA<7:0>: 8-bits of data to be read from/written to data Flash REGISTER 5-2: EEADR: FLASH ADDRESS REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’. bit 5-0 EEADR<5:0>: 6-bits of data to be read from/written to data Flash DS41326E-page 24  2010 Microchip Technology Inc.

PIC16F526 REGISTER 5-3: EECON: FLASH CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FREE WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’. bit 4 FREE: Flash Data Memory Row Erase Enable Bit 1 = Program memory row being pointed to by EEADR will be erased on the next write cycle. No write will be performed. This bit is cleared at the completion of the erase operation. 0 = Perform write only bit 3 WRERR: Write Error Flag bit 1 = A write operation terminated prematurely (by device Reset) 0 = Write operation completed successfully bit 2 WREN: Write Enable bit 1 = Allows write cycle to Flash data memory 0 = Inhibits write cycle to Flash data memory bit 1 WR: Write Control bit 1 = Initiate a erase or write cycle 0 = Write/Erase cycle is complete bit 0 RD: Read Control bit 1 = Initiate a read of Flash data memory 0 = Do not read Flash data memory 5.4 Code Protection Code protection does not prevent the CPU from performing read or write operations on the Flash data memory. Refer to the code protection chapter for more information.  2010 Microchip Technology Inc. DS41326E-page 25

PIC16F526 NOTES: DS41326E-page 26  2010 Microchip Technology Inc.

PIC16F526 6.0 I/O PORT 6.2 PORTC As with any other register, the I/O register(s) can be PORTC is a 6-bit I/O register. Only the low-order 6 bits written and read under program control. However, read are used (RC<5:0>). Bits 7 and 6 are unimplemented instructions (e.g., MOVF PORTB,W) always read the I/O and read as ‘0’s. pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high- 6.3 TRIS Register impedance) since the I/O control registers are all set. The Output Driver Control register is loaded with the contents of the W register by executing the TRIS f 6.1 PORTB instruction. A ‘1’ from a TRIS register bit puts the PORTB is a 6-bit I/O register. Only the low-order 6 bits corresponding output driver in a High-Impedance are used (RB<5:0>). Bits 7 and 6 are unimplemented mode. A ‘0’ puts the contents of the output data latch and read as ‘0’s. Please note that RB3 is an input-only on the selected pins, enabling the output buffer. The pin. The Configuration Word can set several I/O’s to exceptions are RB3, which is input-only and the T0CKI alternate functions. When acting as alternate functions, pin, which may be controlled by the OPTION register. the pins will read as ‘0’ during a port read. Pins RB0, See Register4-2. RB1, RB3 and RB4 can be configured with weak pull- TRIS registers are “write-only”. Active bits in these ups and also for wake-up on change. The wake-up on registers are set (output drivers disabled) upon Reset. change and weak pull-up functions are not pin selectable. If RB3/MCLR is configured as MCLR, weak pull-up is always on and wake-up on change for this pin is not enabled. TABLE 6-1: WEAK PULL-UP ENABLED PINS Device RB0 Weak Pull-up RB1 Weak Pull-up RB3 Weak Pull-up(1) RB4 Weak Pull-up PIC16F526 Yes Yes Yes Yes Note1: When MCLREN = 1, the weak pull-up on RB3/MCLR is always enabled. REGISTER 6-1: PORTB: PORTB REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RB<5:0>: PORTB I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is <VIL max.  2010 Microchip Technology Inc. DS41326E-page 27

PIC16F526 REGISTER 6-2: PORTC: PORTC REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RC<5:0>: PORTC I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is <VIL max. DS41326E-page 28  2010 Microchip Technology Inc.

PIC16F526 6.4 I/O Interfacing FIGURE 6-1: BLOCK DIAGRAM OF RB0 AND RB1 (with Weak Pull- The equivalent circuit for an I/O port pin is shown in up and Wake-up on Figure6-1. All port pins, except RB3 which is input- Change) only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction RBPU (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O Data pin (except RB3) can be programmed individually as Bus D Q input or output. Data WR Latch I/O Pin(1) Port CK Q W Reg D Q TRIS Latch TRIS ‘f’ CK Q Reset (2) ADC pin Ebl (2) COMP pin Ebl RD Port Q D CK Pin Change ADC COMP Note 1: I/O pins have protection diodes to VDD and VSS. 2: Pin enabled as analog for ADC or comparator.  2010 Microchip Technology Inc. DS41326E-page 29

PIC16F526 FIGURE 6-2: BLOCK DIAGRAM OF RB2 FIGURE 6-3: BLOCK DIAGRAM OF RB3 (with Weak Pull-up and Wake-up on Change) C1OUT 0 I/O Pin(1) Data GPPU Bus D Q 1 RBPU Data WR Latch MCLRE Port CK Q C1OUTEN W Reg Reset D Q TRIS Latch Input Pin TRIS ‘f’ CK Q Reset Data Bus ADC Pin Enable RD Port Q D CK RD Port Pin Change ADC Note 1: I/O pins have protection diodes to VDD and Note 1: RB3/MCLR pin has a protection diode to VSS VSS. only. DS41326E-page 30  2010 Microchip Technology Inc.

PIC16F526 FIGURE 6-4: BLOCK DIAGRAM OF RB4 FIGURE 6-5: BLOCK DIAGRAM OF RB5 (with Weak Pull-up and Wake-up on Change) Data Bus D Q Data I/O RBPU WPoRrt Latch pin(1) CK Q Data W Bus Reg D Q 0 D Q Data TRIS WR Latch Latch Port TRIS ‘f’ CK Q 1 I/O CK Q pin(1) FOSC/4 W Reset Reg (Note 2) D Q TRIS Latch TRIS ‘f’ CK Q RD Port Reset Oscillator INTOSC/RC/EC OSC2 Circuit (Note 3) CLKOUT Enable Note 1: I/O pins have protection diodes to VDD and (Note 2) VSS. 2: Input mode is disabled when pin is used for oscillator. RD Port Oscillator OSC1 Circuit Q D CK Pin Change Note 1: I/O pins have protection diodes to VDD and VSS. 2: Input mode is disabled when pin is used for oscillator. 3: Pin is not used for oscillator.  2010 Microchip Technology Inc. DS41326E-page 31

PIC16F526 FIGURE 6-6: BLOCK DIAGRAM OF FIGURE 6-7: BLOCK DIAGRAM OF RC2 RC0/RC1 VROE Data Bus D Q Data CVREF 1 I/O PIN(1) I/O WR Latch Port pin(1) CK Q Data Bus D Q 0 Data W WR Latch Port Reg CK Q D Q TRIS Latch TRIS ‘f’ CK Q W Reg D Q TRIS Reset Latch TRIS ‘f’ CK Q Comp Pin Enable Reset RD Port COMP2 RD Port Note 1: I/O pins have protection diodes to VDD and Note 1: I/O pins have protection diodes to VDD and VSS. VSS. DS41326E-page 32  2010 Microchip Technology Inc.

PIC16F526 FIGURE 6-8: BLOCK DIAGRAM OF RC3 FIGURE 6-9: BLOCK DIAGRAM OF RC4 Data I/O Pin(1) C2OUT 0 I/O Pin(1) Bus D Q Data Data Bus D Q 1 WR Latch Port Data CK Q WR Latch Port CK Q W C2OUTEN Reg D Q W TRIS Reg D Q Latch TRIS ‘f’ TRIS CK Q Latch TRIS ‘f’ CK Q Reset Reset RD Port RD Port Note 1: I/O pins have protection diodes to VDD and Note 1: I/O pins have protection diodes to VDD and VSS. VSS.  2010 Microchip Technology Inc. DS41326E-page 33

PIC16F526 FIGURE 6-10: BLOCK DIAGRAM OF RC5 Data I/O Pin(1) Bus D Q Data WR Latch Port CK Q W Reg D Q TRIS Latch TRIS ‘f’ CK Q T0CS Reset RD Port T0CKI Note 1: I/O pins have protection diodes to VDD and VSS. DS41326E-page 34  2010 Microchip Technology Inc.

PIC16F526 TABLE 6-2: SUMMARY OF PORT REGISTERS Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets N/A TRIS — — I/O Control Register (PORTB, PORTC) --11 1111 --11 1111 N/A OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 03h STATUS RBWUF CWUF PA0 TO PD Z DC C 0001 1xxx qq0q quuu(1) 06h PORTB — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu Legend: Shaded cells are not used by PORT registers, read as ‘0’. – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = depends on condition. Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. TABLE 6-3: I/O PINS ORDER OF PRECEDENCE Priority RB0 RB1 RB2 RB3 RC0 RC1 RC2 RC4 RC5 1 AN0 AN1 AN2 RB3/MCLR C2IN+ C2IN- CVREF C2OUT T0CKI 2 C1IN+ C1IN- C1OUT — TRISC TRISC TRISC TRISC TRISC 3 TRISB TRISB TRISB — — — — — —  2010 Microchip Technology Inc. DS41326E-page 35

PIC16F526 6.5 I/O Programming Considerations EXAMPLE 6-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN 6.5.1 BIDIRECTIONAL I/O PORTS I/O PORT(e.g. DSTEMP) Some instructions operate internally as read followed ;Initial PORTB Settings by write operations. The BCF and BSF instructions, for ;PORTB<5:3> Inputs example, read the entire port into the CPU, execute the ;PORTB<2:0> Outputs bit operation and rewrite the result. Caution must be ; used when these instructions are applied to a port ; PORTB latch PORTB pins where one or more pins are used as input/outputs. For ; ---------- ---------- BCF PORTB, 5 ;--01 -ppp --11 pppp example, a BSF operation on bit 5 of PORTB will cause BCF PORTB, 4 ;--10 -ppp --11 pppp all eight bits of PORTB to be read into the CPU, bit 5 to MOVLW 007h; be set and the PORTB value to be written to the output TRIS PORTB ;--10 -ppp --11 pppp latches. If another bit of PORTB is used as a bidirec- ; tional I/O pin (say bit 0) and it is defined as an input at Note 1: The user may have expected the pin values to this time, the input signal present on the pin itself would be ‘--00 pppp’. The 2nd BCF caused RB5 to be read into the CPU and rewritten to the data latch of be latched as the pin value (High). this particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem 6.5.2 SUCCESSIVE OPERATIONS ON occurs. However, if bit 0 is switched into Output mode I/O PORTS later on, the content of the data latch may now be unknown. The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be Example6-1 shows the effect of two sequential valid at the beginning of the instruction cycle (Figure6-11). Read-Modify-Write instructions (e.g., BCF, BSF, etc.) Therefore, care must be exercised if a write followed by a on an I/O port. read operation is carried out on the same I/O port. The A pin actively outputting a high or a low should not be sequence of instructions should allow the pin voltage to driven from external devices at the same time in order stabilize (load dependent) before the next instruction to change the level on this pin (“wired OR”, “wired causes that file to be read into the CPU. Otherwise, the AND”). The resulting high output currents may damage previous state of that pin may be read into the CPU rather the chip. than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 6-11: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB Instruction followed by a read from PORTB. Fetched MOVWF PORTB MOVF PORTB, W NOP NOP Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle. RB<5:0> TPD = propagation delay Port pin Port pin Therefore, at higher clock frequencies, a written here sampled here write followed by a read may be problematic. Instruction Executed MOVWF PORTB MOVF PORTB,W NOP (Write to PORTB) (Read PORTB) DS41326E-page 36  2010 Microchip Technology Inc.

PIC16F526 7.0 TIMER0 MODULE AND TMR0 There are two types of Counter mode. The first Counter REGISTER mode uses the T0CKI pin to increment Timer0. It is selected by setting the T0CS bit of the OPTION regis- The Timer0 module has the following features: ter, setting the C1T0CS bit of the CM1CON0 register and setting the C1OUTEN bit of the CM1CON0 regis- • 8-bit timer/counter register, TMR0 ter. In this mode, Timer0 will increment either on every • Readable and writable rising or falling edge of pin T0CKI. The T0SE bit of the • 8-bit software programmable prescaler OPTION register determines the source edge. Clearing • Internal or external clock select: the T0SE bit selects the rising edge. Restrictions on the - Edge select for external clock external clock input are discussed in detail in Section7.1 “Using Timer0 with an External Clock”. Figure7-1 is a simplified block diagram of the Timer0 module. The second Counter mode uses the output of the comparator to increment Timer0. It can be entered in Timer mode is selected by clearing the T0CS bit of the two different ways. The first way is selected by setting OPTION register. In Timer mode, the Timer0 module the T0CS bit of the OPTION register, and clearing the will increment every instruction cycle (without pres- C1T0CS bit of the CM1CON0 register (C1OUTEN caler). If TMR0 register is written, the increment is [CM1CON0<6>] does not affect this mode of inhibited for the following two cycles (Figure7-2 and operation). This enables an internal connection Figure7-3). The user can work around this by writing between the comparator and the Timer0. an adjusted value to the TMR0 register. The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit, PSA of the OPTION register. Clearing the PSA bit will assign the prescaler to Timer0. The pres- caler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section7.2 “Prescaler” details the operation of the prescaler. A summary of registers associated with the Timer0 module is found in Table7-1. FIGURE 7-1: TIMER0 BLOCK DIAGRAM Data Bus Comparator FOSC/4 0 PSOUT 8 Output 0 1 Sync with 1 Internal TMR0 Reg T0CKI 1 T0SE(1) PrPorgersacmalmera(2b)le 0 (2 cCyclolec kdselay)PSSyOnUcT pin T0CS(1) 3 PSA(1) PS2(1), PS1(1), PS0(1) C1T0CS(3) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer. 3: The C1T0CS bit is in the CM1CON0 register.  2010 Microchip Technology Inc. DS41326E-page 37

PIC16F526 FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 (Program Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2Q3 Q4 (Program Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 NT0 NT0 + 1 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets 01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter xxxx xxxx uuuu uuuu 08h CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 uuuu uuuu 0Bh CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 1111 1111 uuuu uuuu N/A OPTION RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A TRIS(1) — — I/O Control Register (PORTB, PORTC) --11 1111 --11 1111 Legend: Shaded cells are not used by Timer0. – = unimplemented, x = unknown, u = unchanged. Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1. DS41326E-page 38  2010 Microchip Technology Inc.

PIC16F526 7.1 Using Timer0 with an External When a prescaler is used, the external clock input is Clock divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. When an external clock input is used for Timer0, it must For the external clock to meet the sampling require- meet certain requirements. The external clock ment, the ripple counter must be taken into account. requirement is due to internal phase clock (TOSC) Therefore, it is necessary for T0CKI to have a period of synchronization. Also, there is a delay in the actual at least 4 TOSC (and a small RC delay of 4 Tt0H) incrementing of Timer0 after synchronization. divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate 7.1.1 EXTERNAL CLOCK the minimum pulse width requirement of Tt0H. Refer to SYNCHRONIZATION parameters 40, 41 and 42 in the electrical specification When no prescaler is used, the external clock input is of the desired device. the same as the prescaler output. The synchronization 7.1.2 TIMER0 INCREMENT DELAY of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and Since the prescaler output is synchronized with the Q4 cycles of the internal phase clocks (Figure7-4). internal clocks, there is a small delay from the time the Therefore, it is necessary for T0CKI to be high for at external clock edge occurs to the time the Timer0 least 2 TOSC (and a small RC delay of 2 Tt0H) and low module is actually incremented. Figure7-4 shows the for at least 2 TOSC (and a small RC delay of 2 Tt0H). delay from the external clock edge to the timer Refer to the electrical specification of the desired incrementing. device. FIGURE 7-4: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Small pulse Prescaler Output (2) misses sampling (1) External Clock/Prescaler (3) Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = ±4 TOSC max. 2: External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.  2010 Microchip Technology Inc. DS41326E-page 39

PIC16F526 7.2 Prescaler EXAMPLE 7-1: CHANGING PRESCALER (TIMER0 WDT) An 8-bit counter is available as a prescaler for the CLRWDT ;Clear WDT Timer0 module or as a postscaler for the Watchdog CLRF TMR0 ;Clear TMR0 & Prescaler Timer (WDT), respectively (see Section8.6 “Watch- MOVLW b'00xx1111' dog Timer (WDT)”). For simplicity, this counter is CLRWDT ;PS<2:0> are 000 or 001 being referred to as “prescaler” throughout this data MOVLW b'00xx1xxx';Set Postscaler to sheet. OPTION ;desired WDT rate Note: The prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the To change the prescaler from the WDT to the Timer0 Timer0 module means that there is no module, use the sequence shown in Example7-2. This prescaler for the WDT and vice versa. sequence must be used even if the WDT is disabled. A The PSA and PS<2:0> bits of the OPTION register CLRWDT instruction should be executed before switching the prescaler. determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions EXAMPLE 7-2: CHANGING PRESCALER writing to the TMR0 register (e.g., CLRF TMR0, (WDT TIMER0) MOVWF TMR0, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the CLRWDT ;Clear WDT and prescaler along with the WDT. The prescaler is neither ;prescaler readable nor writable. On a Reset, the prescaler MOVLW b'xxxx0xxx' ;Select TMR0, new ;prescale value and contains all ‘0’s. ;clock source OPTION 7.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). To avoid an unintended device Reset, the following instruction sequence (Example7- 1) must be executed when changing the prescaler assignment from Timer0 to the WDT. DS41326E-page 40  2010 Microchip Technology Inc.

PIC16F526 FIGURE 7-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY (= FOSC/4) Data Bus 0 8 Comparator M 1 Output 0 U M 1 X U Sy2nc TMR0 Reg 0 X Cycles 1 T0CKI Pin T0SE(1) T0CS(1) PSA(1) C1TOCS 0 8-bit Prescaler M U X Watchdog 1 8 Timer 8-to-1 MUX PS<2:0>(1) PSA(1) 0 1 WDT Enable bit MUX PSA(1) WDT Time-out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.  2010 Microchip Technology Inc. DS41326E-page 41

PIC16F526 NOTES: DS41326E-page 42  2010 Microchip Technology Inc.

PIC16F526 8.0 SPECIAL FEATURES OF THE The PIC16F526 device has a Watchdog Timer, which CPU can be shut off only through Configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If What sets a microcontroller apart from other using HS, XT or LP selectable oscillator options, there processors are special circuits that deal with the needs is always an 18ms (nominal) delay provided by the of real-time applications. The PIC16F526 Device Reset Timer (DRT), intended to keep the chip in microcontrollers have a host of such features intended Reset until the crystal oscillator is stable. If using to maximize system reliability, minimize cost through INTRC or EXTRC, there is a 1ms delay only on VDD elimination of external components, provide power- power-up. With this timer on-chip, most applications saving operating modes and offer code protection. need no external Reset circuitry. These features are: The Sleep mode is designed to offer a very low current • Oscillator Selection Power-Down mode. The user can wake-up from Sleep through a change on input pins or through a Watchdog • Reset: Timer time-out. Several oscillator options are also - Power-on Reset (POR) made available to allow the part to fit the application, - Device Reset Timer (DRT) including an internal 4/8MHz oscillator. The EXTRC - Wake-up from Sleep on Pin Change oscillator option saves system cost while the LP crystal • Watchdog Timer (WDT) option saves power. A set of Configuration bits are • Sleep used to select various options. • Code Protection 8.1 Configuration Bits • ID Locations • In-Circuit Serial Programming™ The PIC16F526 Configuration Words consist of 12 bits. • Clock Out Configuration bits can be programmed to select various device configurations. Three bits are for the selection of the oscillator type; one bit is the Watchdog Timer enable bit, one bit is the MCLR enable bit and one bit is for code protection (Register8-1).  2010 Microchip Technology Inc. DS41326E-page 43

PIC16F526 REGISTER 8-1: CONFIG: CONFIGURATION WORD REGISTER CPDF IOSCFS MCLRE CP WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7 CPDF: Code Protection bit – Flash Data Memory 1 = Code protection off 0 = Code protection on bit 6 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8MHz INTOSC frequency 0 = 4MHz INTOSC frequency bit 5 MCLRE: Master Clear Enable bit 1 = RB3/MCLR pin functions as MCLR 0 = RB3/MCLR pin functions as RB3, MCLR internally tied to VDD bit 4 CP: Code Protection bit – User Program Memory 1 = Code protection off 0 = Code protection on bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 000 = LP oscillator and 18ms DRT 001 = XT oscillator and 18ms DRT 010 = HS oscillator and 18ms DRT 011 = EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1ms DRT(1) 100 = INTRC with RB4 function on RB4/OSC2/CLKOUT and 1ms DRT(1) 101 = INTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1ms DRT(1) 110 = EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1ms DRT(1) 111 = EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1ms DRT(1) Note1: Refer to the “PIC16F526 Memory Programming Specification”, DS41317 to determine how to access the Configuration Word. 2: DRT length (18 ms or 1 ms) is a function of Clock mode selection. It is the responsibility of the application designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in acceptable operation. Refer to Section14.1 “DC Characteristics: PIC16F526 (Industrial)” and Section14.2 “DC Characteristics: PIC16F526 (Extended)” for VDD rise time and stability requirements for this mode of operation. DS41326E-page 44  2010 Microchip Technology Inc.

PIC16F526 8.2 Oscillator Configurations FIGURE 8-1: CRYSTAL OPERATION (OR CERAMIC 8.2.1 OSCILLATOR TYPES RESONATOR) The PIC16F526 device can be operated in up to six (HS, XT OR LP OSC different oscillator modes. The user can program up to CONFIGURATION) three Configuration bits (FOSC<2:0>). To select one of C1(1) these modes: OSC1 PIC16F526 • LP: Low-Power Crystal Sleep • XT: Crystal/Resonator XTAL RF(3) • HS: High-Speed Crystal/Resonator To internal logic • INTRC: Internal 4/8MHz Oscillator OSC2 RS(2) • EXTRC: External Resistor/Capacitor C2(1) • EC: External High-Speed Clock Input Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 8.2.2 CRYSTAL OSCILLATOR/CERAMIC 2: A series resistor (RS) may be required for AT RESONATORS strip cut crystals. In HS, XT or LP modes, a crystal or ceramic resonator 3: RF approx. value = 10M. is connected to the RB5/OSC1/CLKIN and RB4/OSC2/ CLKOUT pins to establish oscillation (Figure8-1). The PIC16F526 oscillator designs require the use of a FIGURE 8-2: EXTERNAL CLOCK INPUT parallel cut crystal. Use of a series cut crystal may give OPERATION (HS, XT, LP a frequency out of the crystal manufacturers OR EC OSC specifications. When in HS, XT or LP modes, the CONFIGURATION) device can have an external clock source drive the RB5/OSC1/CLKIN pin (Figure8-2). In this mode, the EC, HS, XT, LP output drive levels on the OSC2 pin are very weak. If the part is used in this fashion, then this pin should be Clock From RB5/OSC1/CLKIN ext. system left open and unloaded. Also when using this mode, the PIC16F526 external clock should observe the frequency limits for the Clock mode chosen (HS, XT or LP). OSC2/CLKOUT/RB4 OSC2/CLKOUT/RB4(1) Note1: This device has been designed to per- form to the parameters of its data sheet. Note 1: RB4 is available in EC mode only. It has been tested to an electrical specification designed to determine its conformance with these parameters. TABLE 8-1: CAPACITOR SELECTION FOR Due to process differences in the CERAMIC RESONATORS manufacture of this device, this device Osc Resonator Cap. Range Cap. Range may have different performance charac- Type Freq. C1 C2 teristics than its earlier version. These differences may cause this device to XT 4.0 MHz 30 pF 30 pF perform differently in your application HS 16 MHz 10-47 pF 10-47 pF than the earlier version of this device. Note 1: These values are for design guidance 2: The user should verify that the device only. Since each resonator has its own oscillator starts and performs as characteristics, the user should consult expected. Adjusting the loading capacitor the resonator manufacturer for values and/or the Oscillator mode may appropriate values of external be required. components.  2010 Microchip Technology Inc. DS41326E-page 45

PIC16F526 TABLE 8-2: CAPACITOR SELECTION FOR Figure8-4 shows a series resonant oscillator circuit. CRYSTAL OSCILLATOR(2) This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180- Osc Resonator Cap. Range Cap. Range degree phase shift in a series resonant oscillator Type Freq. C1 C2 circuit. The 330 resistors provide the negative LP 32kHz(1) 15pF 15pF feedback to bias the inverters in their linear region. XT 200 kHz 47-68 pF 47-68 pF FIGURE 8-4: EXTERNAL SERIES 1 MHz 15 pF 15 pF RESONANT CRYSTAL 4 MHz 15 pF 15 pF OSCILLATOR CIRCUIT HS 20 MHz 15-47 pF 15-47 pF Note 1: For VDD > 4.5V, C1 = C2  30 pF is To Other recommended. 330 330 Devices 2: These values are for design guidance 74AS04 74AS04 74AS04 only. Rs may be required to avoid over- CLKIN driving crystals with low drive level specifi- 0.1 mF PIC16F526 cation. Since each crystal has its own XTAL characteristics, the user should consult the crystal manufacturer for appropriate values of external components. 8.2.4 EXTERNAL RC OSCILLATOR 8.2.3 EXTERNAL CRYSTAL OSCILLATOR For timing insensitive applications, the RC device CIRCUIT option offers additional cost savings. The RC oscillator Either a prepackaged oscillator or a simple oscillator frequency is a function of the supply voltage, the resis- circuit with TTL gates can be used as an external tor (REXT) and capacitor (CEXT) values, and the operat- crystal oscillator circuit. Prepackaged oscillators ing temperature. In addition to this, the oscillator provide a wide operating range and better stability. A frequency will vary from unit-to-unit due to normal pro- well-designed crystal oscillator will provide good cess parameter variation. Furthermore, the difference performance with TTL gates. Two types of crystal in lead frame capacitance between package types will oscillator circuits can be used: one with parallel also affect the oscillation frequency, especially for low resonance, or one with series resonance. CEXT values. The user also needs to take into account variation due to tolerance of external R and C Figure8-3 shows implementation of a parallel resonant components used. oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 Figure8-5 shows how the R/C combination is con- inverter performs the 180-degree phase shift that a nected to the PIC16F526 device. For REXT values parallel oscillator requires. The 4.7k resistor provides below 3.0k, the oscillator operation may become the negative feedback for stability. The 10k unstable, or stop completely. For very high REXT values potentiometers bias the 74AS04 in the linear region. (e.g.,1M), the oscillator becomes sensitive to noise, This circuit could be used for external oscillator humidity and leakage. Thus, we recommend keeping designs. REXT between 5.0k and 100k. Although the oscillator will operate with no external FIGURE 8-3: EXTERNAL PARALLEL capacitor (CEXT = 0pF), we recommend using values RESONANT CRYSTAL above 20pF for noise and stability reasons. With no or OSCILLATOR CIRCUIT small external capacitance, the oscillation frequency can vary dramatically due to changes in external +5V To Other capacitances, such as PCB trace capacitance or Devices package lead frame capacitance. 10k 4.7k 74AS04 Section14.0 “Electrical Characteristics” shows RC 74AS04 CLKIN frequency variation from part-to-part due to normal process variation. The variation is larger for larger val- PIC16F526 ues of R (since leakage current variation will affect RC 10k frequency more for large R) and for smaller values of C XTAL (since variation of input capacitance will affect RC frequency more). 10k 20 pF 20 pF DS41326E-page 46  2010 Microchip Technology Inc.

PIC16F526 Also, see the Electrical Specifications section for 8.2.5 INTERNAL 4/8MHz RC variation of oscillator frequency due to VDD for given OSCILLATOR REXT/CEXT values, as well as frequency variation due The internal RC oscillator provides a fixed 4/8MHz to operating temperature for given R, C and VDD (nominal) system clock at VDD = 5V and 25°C, (see values. Section14.0 “Electrical Characteristics” for information on variation over voltage and temperature). FIGURE 8-5: EXTERNAL RC OSCILLATOR MODE In addition, a calibration instruction is programmed into the last address of memory, which contains the calibra- VDD tion value for the internal RC oscillator. This location is always non-code protected, regardless of the code- REXT Internal protect settings. This value is programmed as a MOVLW OSC1 clock XX instruction where XX is the calibration value, and is placed at the Reset vector. This will load the W register with the calibration value upon Reset and the PC will N CEXT then roll over to the users program at address 0x000. PIC16F526 The user then has the option of writing the value to the VSS OSCCAL Register (05h) or ignoring it. FOSC/4 OSC2/CLKOUT OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. Note: Erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. For the PIC16F526 device, only bits 7:1 of OSCCAL are used for calibration. See Register4-3 for more information. Note: The bit 0 of the OSCCAL register is unimplemented and should be written as ‘0’ when modifying OSCCAL for compatibility with future devices.  2010 Microchip Technology Inc. DS41326E-page 47

PIC16F526 8.3 Reset Some registers are not reset in any way, they are unknown on POR and unchanged in any other Reset. The device differentiates between various kinds of Most other registers are reset to “Reset state” on Reset: Power-on Reset (POR), MCLR, WDT or Wake-up on • Power-on Reset (POR) pin change Reset during normal operation. They are • MCLR Reset during normal operation not affected by a WDT Reset during Sleep or MCLR Reset during Sleep, since these Resets are viewed as • MCLR Reset during Sleep resumption of normal operation. The exceptions to this • WDT Time-out Reset during normal operation are TO, PD and RBWUF bits. They are set or cleared • WDT Time-out Reset during Sleep differently in different Reset situations. These bits are • Wake-up from Sleep on pin change used in software to determine the nature of Reset. See Table8-3 for a full description of Reset states of all registers. TABLE 8-3: RESET CONDITIONS FOR REGISTERS MCLR Reset, WDT Time-out, Register Address Power-on Reset Wake-up On Pin Change W — qqqq qqq0(1) qqqq qqq0(1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx qq0q quuu(2) FSR 04h 100x xxxx 1uuu uuuu OSCCAL 05h 1111 111- uuuu uuu- PORTB 06h --xx xxxx --uu uuuu PORTC 07h --xx xxxx --uu uuuu CMICON0 08h q111 1111 quuu uuuu ADCON0 09h 1111 1100 1111 1100 ADRES 0Ah xxxx xxxx uuuu uuuu CM2CON0 0Bh q111 1111 quuu uuuu VRCON 0Ch 001-1111 uuu-uuuu OPTION — 1111 1111 1111 1111 TRISB — --11 1111 --11 1111 TRISC — --11 1111 --11 1111 EECON 21h/61h ---0 x000 ---0 q000 EEDATA 25h/65h xxxx xxxx uuuu uuuu EEADR 26h/66h --xx xxxx --uu uuuu Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: Bits <7:1> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. 2: See Table8-4 for Reset value for specific conditions. DS41326E-page 48  2010 Microchip Technology Inc.

PIC16F526 TABLE 8-4: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h Power-on Reset 0001 1xxx MCLR Reset during normal operation 000u uuuu MCLR Reset during Sleep 0001 0uuu WDT Reset during Sleep 0000 0uuu WDT Reset normal operation 0000 uuuu Wake-up from Sleep on pin change 1001 0uuu Wake-up from Sleep on comparator change 0101 0uuu Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’.  2010 Microchip Technology Inc. DS41326E-page 49

PIC16F526 8.3.1 MCLR ENABLE The Power-on Reset circuit and the Device Reset Timer (see Section8.5 “Device Reset Timer (DRT)”) This Configuration bit, when unprogrammed (left in the circuit are closely related. On power-up, the Reset latch ‘1’ state), enables the external MCLR function. When is set and the DRT is reset. The DRT timer begins programmed, the MCLR function is tied to the internal counting once it detects MCLR to be high. After the VDD and the pin is assigned to be a I/O. See Figure8-6. time-out period, which is typically 18ms or 1ms, it will reset the Reset latch and thus end the on-chip Reset FIGURE 8-6: MCLR SELECT signal. A power-up example where MCLR is held low is shown RBWU in Figure8-8. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of Reset TDRT msec after MCLR goes high. RB3/MCLR/VPP In Figure8-9, the on-chip Power-on Reset feature is MCLRE Internal MCLR being used (MCLR and VDD are tied together or the pin is programmed to be RB3. The VDD is stable before the start-up timer times out and there is no problem in get- ting a proper Reset. However, Figure8-10 depicts a problem situation where VDD rises too slowly. The time 8.4 Power-on Reset (POR) between when the DRT senses that MCLR is high and when MCLR and VDD actually reach their full value, is The PIC16F526 device incorporates an on-chip Power- too long. In this situation, when the start-up timer times on Reset (POR) circuitry, which provides an internal out, VDD has not reached the VDD (min) value and the chip Reset for most power-up situations. chip may not function correctly. For such situations, we The on-chip POR circuit holds the chip in Reset until recommend that external RC circuits be used to VDD has reached a high enough level for proper oper- achieve longer POR delay times (Figure8-9). ation. To take advantage of the internal POR, program Note: When the device starts normal operation the RB3/MCLR/VPP pin as MCLR and tie through a (exit the Reset condition), device operat- resistor to VDD, or program the pin as RB3. An internal ing parameters (voltage, frequency, tem- weak pull-up resistor is implemented using a transistor perature, etc.) must be met to ensure (refer to Table14-5 for the pull-up resistor ranges). This operation. If these conditions are not met, will eliminate external RC components usually needed the device must be held in Reset until the to create a Power-on Reset. A maximum rise time for operating conditions are met. VDD is specified. See Section14.0 “Electrical Char- acteristics” for details. For additional information, refer to Application Notes AN522 “Power-Up Considerations” (DS00522) and When the device starts normal operation (exit the AN607 “Power-up Trouble Shooting” (DS00607). Reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating parameters are met. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure8-7. DS41326E-page 50  2010 Microchip Technology Inc.

PIC16F526 FIGURE 8-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) RB3/MCLR/VPP MCLR Reset S Q MCLRE R Q WDT Time-out WDT Reset Start-up Timer CHIP Reset (10 ms, 1.125ms Pin Change or 18 ms) Sleep Wake-up on pin Change Reset Comparator Change Wake-up on Comparator Change FIGURE 8-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) VDD MCLR Internal POR TDRT DRT Time-out Internal Reset FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR Internal POR TDRT DRT Time-out Internal Reset  2010 Microchip Technology Inc. DS41326E-page 51

PIC16F526 FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1  VDD min. DS41326E-page 52  2010 Microchip Technology Inc.

PIC16F526 8.5 Device Reset Timer (DRT) TABLE 8-5: TYPICAL DRT PERIODS On the PIC16F526 device, the DRT runs any time the Oscillator Subsequent POR Reset device is powered up. DRT runs from Reset and varies Configuration Resets based on oscillator selection and Reset type (see HS, XT, LP 18ms 18ms Table8-5). The DRT operates on an internal RC oscillator. The EC 1.125ms 10s processor is kept in Reset as long as the DRT is active. INTOSC, EXTRC 1.125ms 10s The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize. 8.6.1 WDT PERIOD Oscillator circuits based on crystals or ceramic resona- The WDT has a nominal time-out period of 18ms, (with tors require a certain time after power-up to establish a no prescaler). If a longer time-out period is desired, a stable oscillation. The on-chip DRT keeps the device in prescaler with a division ratio of up to 1:128 can be a Reset condition after MCLR has reached a logic high assigned to the WDT (under software control) by (VIH MCLR) level. Programming RB3/MCLR/VPP as writing to the OPTION register. Thus, a time-out period MCLR and using an external RC network connected to of a nominal 2.3 seconds can be realized. These the MCLR input is not required in most cases. This periods vary with temperature, VDD and part-to-part allows savings in cost-sensitive and/or space restricted process variations (see DC specs). applications, as well as allowing the use of the RB3/ MCLR/VPP pin as a general purpose input. Under worst-case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several The Device Reset Time delays will vary from chip-to- seconds before a WDT time-out occurs. chip due to VDD, temperature and process variation. See AC parameters for details. 8.6.2 WDT PROGRAMMING The DRT will also be triggered upon a Watchdog Timer CONSIDERATIONS time-out from Sleep. This is particularly important for The CLRWDT instruction clears the WDT and the applications using the WDT to wake from Sleep mode postscaler, if assigned to the WDT, and prevents it from automatically. timing out and generating a device Reset. Reset sources are POR, MCLR, WDT time-out and The SLEEP instruction resets the WDT and the wake-up on pin or comparator change. See postscaler, if assigned to the WDT. This gives the Section8.9.2 “Wake-up from Sleep”, Notes 1, 2 and maximum Sleep time before a WDT wake-up Reset. 3. 8.6 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the external RC oscillator of the RB5/OSC1/CLKIN pin and the internal 4/8MHz oscillator. This means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or Sleep, a WDT Reset or wake-up Reset, generates a device Reset. The TO bit of the STATUS register will be cleared upon a Watchdog Timer Reset. The WDT can be permanently disabled by programming the configuration WDTE as a ‘0’ (see Section8.1 “Configuration Bits”). Refer to the PIC16F526 Programming Specifications to determine how to access the Configuration Word.  2010 Microchip Technology Inc. DS41326E-page 53

PIC16F526 FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure7-1) 0 M Watchdog 1 U PPoossttssccaalleerr Time X 8-to-1 MUX PS<2:0>(1) PSA WDT Enable Configuration To Timer0 (Figure7-4) Bit 0 1 MUX PSA(1) WDT Time-out Note 1: PSA, PS<2:0> are bits in the OPTION register. TABLE 8-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets N/A OPTION RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: Shaded boxes = Not used by Watchdog Timer. DS41326E-page 54  2010 Microchip Technology Inc.

PIC16F526 8.7 Time-out Sequence, Power-down FIGURE 8-12: BROWN-OUT and Wake-up from Sleep Status PROTECTION CIRCUIT 1 Bits (TO, PD, RBWUF, CWUF) VDD The TO, PD and RBWUF bits in the STATUS register VDD can be tested to determine if a Reset condition has 33k PIC12F510 been caused by a power-up condition, a MCLR or PIC16F506 Watchdog Timer (WDT) Reset. 10k Q1 MCLR(2) TABLE 8-7: TO/PD/RBWUF/CWUF 40k(1) STATUS AFTER RESET CWUF RBWUF TO PD Reset Caused By 0 0 0 0 WDT wake-up from Note 1: This circuit will activate Reset when VDD goes Sleep below Vz + 0.7V (where Vz = Zener voltage). 0 0 0 u WDT time-out (not from 2: Pin must be configured as MCLR. Sleep) 0 0 1 0 MCLR wake-up from FIGURE 8-13: BROWN-OUT Sleep PROTECTION CIRCUIT 2 0 0 1 1 Power-up VDD 0 0 u u MCLR not during Sleep VDD 0 1 1 0 Wake-up from Sleep on pin change R1 PIC12F510 PIC16F506 1 0 1 0 Wake up from Sleep on Q1MCLR(2) comparator change Legend: u = unchanged R2 40k(1) Note1: The TO, PD and RBWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the MCLR input does not Note 1: This brown-out circuit is less expensive, change the TO, PD and RBWUF Status although less accurate. Transistor Q1 turns bits. off when VDD is below a certain level such that: 8.8 Reset on Brown-out R1 VDD • = 0.7V R1 + R2 A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then 2: Pin must be configured as MCLR. recovers. The device should be reset in the event of a brown-out. FIGURE 8-14: BROWN-OUT To reset PIC16F526 devices when a brown-out occurs, PROTECTION CIRCUIT 3 external brown-out protection circuits may be built, as shown in Figure8-12 and Figure8-13. VDD MCP809 Bypass VDD VSS Capacitor VDD RST MCLR PIC12F510 PIC16F506 Note: This brown-out protection circuit employs Microchip Technology’s MCP809 microcon- troller supervisor. There are 7 different trip point selections to accommodate 5V to 3V systems.  2010 Microchip Technology Inc. DS41326E-page 55

PIC16F526 8.9 Power-down Mode (Sleep) 8.9.2 WAKE-UP FROM SLEEP A device may be powered down (Sleep) and later The device can wake-up from Sleep through one of powered up (wake-up from Sleep). the following events: 1. An external Reset input on RB3/MCLR/VPP pin, 8.9.1 SLEEP when configured as MCLR. The Power-Down mode is entered by executing a 2. A Watchdog Timer Time-out Reset (if WDT was SLEEP instruction. enabled). If enabled, the Watchdog Timer will be cleared but 3. A change on input pin RB0, RB1, RB3 or RB4 keeps running, the TO bit of the STATUS register is set, when wake-up on change is enabled. the PD bit of the STATUS register is cleared and the 4. A change in one of the comparator output bits, oscillator driver is turned off. The I/O ports maintain the C1OUT or C2OUT (if comparator wake-up is status they had before the SLEEP instruction was exe- enabled). cuted (driving high, driving low or high-impedance). These events cause a device Reset. The TO, PD and Note: A Reset generated by a WDT time-out CWUF/RBWUF bits can be used to determine the does not drive the MCLR pin low. cause of device Reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, For lowest current consumption while powered down, which is set on power-up, is cleared when SLEEP is the T0CKI input should be at VDD or VSS and the RB3/ invoked. The CWUF bit indicates a change in a com- MCLR/VPP pin must be at a logic high level if MCLR is parator output state while the device was in Sleep. The enabled. RBWUF bit indicates a change in state while in Sleep at pins RB0, RB1, RB3 or RB4 (since the last file or bit operation on RB port). Note: Caution: Right before entering Sleep, read the input pins. When in Sleep, wake-up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before re-entering Sleep, a wake-up will occur immediately even if no pins change while in Sleep mode. The WDT is cleared when the device wakes from Sleep, regardless of the wake-up source. Note: Caution: Right before entering Sleep, read the comparator Configuration register(s) CM1CON0 and CM2CON0. When in Sleep, wake-up occurs when the comparator output bit C1OUT and C2OUT change from the state they were in at the last reading. If a wake-up on comparator change occurs and the pins are not read before re-entering Sleep, a wake-up will occur immediately, even if no pins change while in Sleep mode. DS41326E-page 56  2010 Microchip Technology Inc.

PIC16F526 8.10 Program Verification/Code FIGURE 8-15: TYPICAL IN-CIRCUIT Protection SERIAL PROGRAMMING CONNECTION If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. To Normal Connections The first 64 locations and the last location (OSCCAL) External Connector can be read, regardless of the code protection bit PIC16F526 Signals setting. +5V VDD The last memory location can be read regardless of the 0V VSS code protection bit setting on the PIC16F526 device. VPP MCLR/VPP 8.11 ID Locations CLK RB1 Four memory locations are designated as ID locations Data RB0 where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable VDD and writable during Program/Verify. Use only the lower 4 bits of the ID locations and always To Normal Connections program the upper 8 bits as ‘0’s. 8.12 In-Circuit Serial Programming™ The PIC16F526 microcontroller can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware, or a custom firmware, to be programmed. The devices are placed into a Program/Verify mode by holding the RB1 and RB0 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB1 becomes the programming clock and B0 becomes the programming data. Both RB1 and RB0 are Schmitt Trigger inputs in this mode. After Reset, a 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a Load or a Read. For complete details of serial programming, please refer to the PIC16F526 Programming Specifications. A typical In-Circuit Serial Programming connection is shown in Figure8-15.  2010 Microchip Technology Inc. DS41326E-page 57

PIC16F526 NOTES: DS41326E-page 58  2010 Microchip Technology Inc.

PIC16F526 9.0 ANALOG-TO-DIGITAL (A/D) CONVERTER Note: It is the users responsibility to ensure that use of the ADC and comparator simulta- The A/D Converter allows conversion of an analog signal into an 8-bit digital signal. neously on the same pin, does not adversely affect the signal being monitored or adversely effect device 9.1 Clock Divisors operation. The ADC has 4 clock source settings ADCS<1:0>. When the CHS<1:0> bits are changed during an ADC There are 3 divisor values 16, 8 and 4. The fourth conversion, the new channel will not be selected until setting is INTOSC with a divisor of 4. These settings the current conversion is completed. This allows the will allow a proper conversion when using an external current conversion to complete with valid results. All oscillator at speeds from 20MHz to 350kHz. Using an channel selection information will be lost when the external oscillator at a frequency below 350kHz device enters Sleep. requires the ADC oscillator setting to be INTOSC/4 (ADCS<1:0> = 11) for valid ADC results. TABLE 9-1: CHANNEL SELECT (ADCS) The ADC requires 13 TAD periods to complete a BITS AFTER AN EVENT conversion. The divisor values do not affect the number of TAD periods required to perform a conversion. The Event ADCS<1:0> divisor values determine the length of the TAD period. MCLR 11 When the ADCS<1:0> bits are changed while an ADC Conversion completed CS<1:0> conversion is in process, the new ADC clock source will Conversion terminated CS<1:0> not be selected until the next conversion is started. This clock source selection will be lost when the device Power-on 11 enters Sleep. Wake from Sleep 11 Note: The ADC clock is derived from the instruc- tion clock. The ADCS divisors are then 9.1.4 THE GO/DONE BIT applied to create the ADC clock The GO/DONE bit is used to determine the status of a conversion, to start a conversion and to manually halt 9.1.1 VOLTAGE REFERENCE a conversion in process. Setting the GO/DONE bit There is no external voltage reference for the ADC. The starts a conversion. When the conversion is complete, ADC reference voltage will always be VDD. the ADC module clears the GO/DONE bit. A conversion can be terminated by manually clearing the 9.1.2 ANALOG MODE SELECTION GO/DONE bit while a conversion is in process. Manual The ANS<1:0> bits are used to configure pins for termination of a conversion may result in a partially analog input. Upon any Reset, ANS<1:0> defaults to converted result in ADRES. 11. This configures pins AN0, AN1 and AN2 as analog The GO/DONE bit is cleared when the device enters inputs. The comparator output, C1OUT, will override Sleep, stopping the current conversion. The ADC does AN2 as an input if the comparator output is enabled. not have a dedicated oscillator, it runs off of the Pins configured as analog inputs are not available for instruction clock. Therefore, no conversion can occur in digital output. Users should not change the ANS bits sleep. while a conversion is in process. ANS bits are active The GO/DONE bit cannot be set when ADON is clear. regardless of the condition of ADON. 9.1.3 ADC CHANNEL SELECTION The CHS bits are used to select the analog channel to be sampled by the ADC. The CHS<1:0> bits can be changed at any time without adversely effecting a con- version. To acquire an analog signal the CHS<1:0> selection must match one of the pin(s) selected by the ANS<1:0> bits. When the ADC is on (ADON = 1) and a channel is selected that is also being used by the comparator, then both the comparator and the ADC will see the analog voltage on the pin.  2010 Microchip Technology Inc. DS41326E-page 59

PIC16F526 9.1.5 SLEEP This ADC does not have a dedicated ADC clock, and therefore, no conversion in Sleep is possible. If a conversion is underway and a Sleep command is executed, the GO/DONE and ADON bit will be cleared. This will stop any conversion in process and power- down the ADC module to conserve power. Due to the nature of the conversion process, the ADRES may con- tain a partial conversion. At least 1 bit must have been converted prior to Sleep to have partial conversion data in ADRES. The ADCS and CHS bits are reset to their default condition; ANS<1:0> = 11 and CHS<1:0> = 11. • For accurate conversions, TAD must meet the following: • 500ns < TAD < 50s • TAD = 1/(FOSC/divisor) Shaded areas indicate TAD out of range for accurate conversions. If analog input is desired at these frequencies, use INTOSC/8 for the ADC clock source. TABLE 9-2: TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS ADCS 20 16 500 350 200 100 Source Divisor 8MHz 4MHz 1MHz 32 kHz <1:0> MHz MHz kHz kHz kHz kHz INTOSC 11 4 — — .5s 1s — — — — — — FOSC 10 4 .2s .25s .5s 1s 4s 8s 11s 20s 40s 125s FOSC 01 8 .4s .5s 1s 2s 8s 16s 23s 40s 80s 250s FOSC 00 16 .8s 1s 2s 4s 16s 32s 46s 80s 160s 500s TABLE 9-3: EFFECTS OF SLEEP ON ADCON0 ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON Entering Unchanged Unchanged 1 1 1 1 0 0 Sleep Wake or 1 1 1 1 1 1 0 0 Reset DS41326E-page 60  2010 Microchip Technology Inc.

PIC16F526 9.1.6 ANALOG CONVERSION RESULT right shifts of the ‘leading one’ have taken place, the REGISTER conversion is complete; the ‘leading one’ has been shifted out and the GO/DONE bit is cleared. The ADRES register contains the results of the last conversion. These results are present during the If the GO/DONE bit is cleared in software during a sampling period of the next analog conversion process. conversion, the conversion stops. The data in ADRES After the sampling period is over, ADRES is cleared is the partial conversion result. This data is valid for the (=0). A ‘leading one’ is then right shifted into the bit weights that have been converted. The position of ADRES to serve as an internal conversion complete the ‘leading one’ determines the number of bits that bit. As each bit weight, starting with the MSB, is have been converted. The bits that were not converted converted, the leading one is shifted right and the before the GO/DONE was cleared are unrecoverable. converted bit is stuffed into ADRES. After a total of 9 REGISTER 9-1: ADCON0: A/D CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ANS<1:0>: ADC Analog Input Pin Select bits(1), (2), (5) 00 = No pins configured for analog input 01 = AN2 configured as an analog input 10 = AN2 and AN0 configured as analog inputs 11 = AN2, AN1 and AN0 configured as analog inputs bit 5-4 ADCS<1:0>: ADC Conversion Clock Select bits 00 = FOSC/16 01 = FOSC/8 10 = FOSC/4 11 = INTOSC/4 bit 3-2 CHS<1:0>: ADC Channel Select bits(3, 5) 00 = Channel AN0 01 = Channel AN1 10 = Channel AN2 11 = 0.6V absolute voltage reference bit 1 GO/DONE: ADC Conversion Status bit(4) 1 = ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC is done converting. 0 = ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process termi- nates the current conversion. bit 0 ADON: ADC Enable bit 1 = ADC module is operating 0 = ADC module is shut-off and consumes no power Note 1: When the ANS bits are set, the channels selected will automatically be forced into Analog mode, regardless of the pin function previously defined. The only exception to this is the comparator, where the analog input to the comparator and the ADC will be active at the same time. It is the users responsibility to ensure that the ADC loading on the comparator input does not affect their application. 2: The ANS<1:0> bits are active regardless of the condition of ADON. 3: CHS<1:0> bits default to 11 after any Reset. 4: If the ADON bit is clear, the GO/DONE bit cannot be set. 5: C1OUT, when enabled, overrides AN2.  2010 Microchip Technology Inc. DS41326E-page 61

PIC16F526 REGISTER 9-2: ADRES: A/D CONVERSION RESULTS REGISTER R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown EXAMPLE 9-1: PERFORMING AN EXAMPLE 9-2: CHANNEL SELECTION ANALOG-TO-DIGITAL CHANGE DURING CONVERSION CONVERSION ;Sample code operates out of BANK0 MOVLW 0xF1 ;configure A/D MOVWF ADCON0 MOVLW 0xF1 ;configure A/D BSF ADCON0, 1 ;start conversion MOVWF ADCON0 BSF ADCON0, 2 ;setup for read of BSF ADCON0, 1 ;start conversion ;channel 1 loop0 BTFSC ADCON0, 1;wait for ‘DONE’ loop0 BTFSC ADCON0, 1;wait for ‘DONE’ GOTO loop0 GOTO loop0 MOVF ADRES, W ;read result MOVF ADRES, W ;read result MOVWF result0 ;save result MOVWF result0 ;save result BSF ADCON0, 2 ;setup for read of BSF ADCON0, 1 ;start conversion ;channel 1 BSF ADCON0, 3 ;setup for read of BSF ADCON0, 1 ;start conversion BCF ADCON0, 2 ;channel 2 loop1 BTFSC ADCON0, 1;wait for ‘DONE’ loop1 BTFSC ADCON0, 1;wait for ‘DONE’ GOTO loop1 GOTO loop1 MOVF ADRES, W ;read result MOVF ADRES, W ;read result MOVWF result1 ;save result MOVWF result1 ;save result BSF ADCON0, 3 ;setup for read of BSF ADCON0, 1 ;start conversion BCF ADCON0, 2 ;channel 2 loop2 BTFSC ADCON0, 1;wait for ‘DONE’ BSF ADCON0, 1 ;start conversion GOTO loop2 loop2 BTFSC ADCON0, 1;wait for ‘DONE’ MOVF ADRES, W ;read result GOTO loop2 MOVWF result2 ;save result MOVF ADRES, W ;read result CLRF ADCON0 ;optional: returns MOVWF result2 ;save result ;pins to Digital mode and turns off ;the ADC module DS41326E-page 62  2010 Microchip Technology Inc.

PIC16F526 10.0 COMPARATOR(S) This device contains two comparators and a comparator voltage reference. REGISTER 10-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1OUT: Comparator Output bit 1 = VIN+ > VIN- 0 = VIN+ < VIN- bit 6 C1OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C1OUT pin 0 = Output of comparator is placed in the C1OUT pin bit 5 C1POL: Comparator Output Polarity bit(2) 1 = Output of comparator is not inverted 0 = Output of comparator is inverted bit 4 C1T0CS: Comparator TMR0 Clock Source bit(2) 1 = TMR0 clock source selected by T0CS control bit 0 = Comparator output used as TMR0 clock source bit 3 C1ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off bit 2 C1NREF: Comparator Negative Reference Select bit(2) 1 = C1IN- pin 0 = 0.6V VREF bit 1 C1PREF: Comparator Positive Reference Select bit(2) 1 = C1IN+ pin 0 = C1IN- pin bit 0 C1WU: Comparator Wake-up On Change Enable bit(2) 1 = Wake-up On Comparator Change is disabled 0 = Wake-up On Comparator Change is enabled Note1: Overrides T0CS bit for TRIS control of RB2. 2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have precedence.  2010 Microchip Technology Inc. DS41326E-page 63

PIC16F526 REGISTER 10-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2OUT: Comparator Output bit 1 = VIN+ > VIN- 0 = VIN+ < VIN- bit 6 C2OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C2OUT pin 0 = Output of comparator is placed in the C2OUT pin bit 5 C2POL: Comparator Output Polarity bit(2) 1 = Output of comparator not inverted 0 = Output of comparator inverted bit 4 C2PREF2: Comparator Positive Reference Select bit(2) 1 = C1IN+ pin 0 = C2IN- pin bit 3 C2ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off bit 2 C2NREF: Comparator Negative Reference Select bit(2) 1 = C2IN- pin 0 = CVREF bit 1 C2PREF1: Comparator Positive Reference Select bit(2) 1 = C2IN+ pin 0 = C2PREF2 controls analog input selection bit 0 C2WU: Comparator Wake-up on Change Enable bit(2) 1 = Wake-up on Comparator change is disabled 0 = Wake-up on Comparator change is enabled. Note1: Overrides TOCS bit for TRIS control of RC4. 2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have precedence. DS41326E-page 64  2010 Microchip Technology Inc.

PIC16F526 FIGURE 10-1: COMPARATORS BLOCK DIAGRAM C1PREF RB2/C1OUT C1IN+ 1 C1OUTEN + C1IN- 0 C1OUT (Register) 1 VREF - (0.6V) 0 C1NREF C1POL C1ON T0CKI 0 1 T0CKI Pin C1T0CS Q D S READ CM1CON0 RC4/C2OUT C2PREF1 C2IN+ 1 C2OUTEN + 0 1 C2OUT (Register) 0 - C2PREF2 C2IN- C2POL C2ON 1 CVREF 0 C2NREF Q D C1WU S READ CM2CON0 CWUF C2WU  2010 Microchip Technology Inc. DS41326E-page 65

PIC16F526 10.1 Comparator Operation A single comparator is shown in Figure10-2 along with Note: Analog levels on any pin that is defined as the relationship between the analog input levels and a digital input may cause the input buffer the digital output. When the analog input at VIN+ is less to consume more current than is specified. than the analog input VIN-, the output of the comparator is a digital low level. The shaded area of the output of 10.5 Comparator Wake-up Flag the comparator in Figure10-2 represent the uncertainty due to input offsets and response time. See The Comparator Wake-up Flag is set whenever all of Table14-2 for Common Mode Voltage. the following conditions are met: • C1WU = 0 (CM1CON0<0>) or FIGURE 10-2: SINGLE COMPARATOR C2WU = 0 (CM2CON0<0>) • CM1CON0 or CM2CON0 has been read to latch the last known state of the C1OUT and C2OUT bit (MOVF CM1CON0, W) VIN+ + Result • Device is in Sleep VIN- – • The output of a comparator has changed state The wake-up flag may be cleared in software or by another device Reset. 10.6 Comparator Operation During VIN- Sleep VIN+ When the comparator is enabled it is active. To minimize power consumption while in Sleep mode, turn off the comparator before entering Sleep. Result 10.7 Effects of Reset A Power-on Reset (POR) forces the CM2CON0 register to its Reset state. This forces the Comparator 10.2 Comparator Reference input pins to analog Reset mode. Device current is minimized when analog inputs are present at Reset An internal reference signal may be used depending on time. the comparator operating mode. The analog signal that is present at VIN- is compared to the signal at VIN+, and 10.8 Analog Input Connection the digital output of the comparator is adjusted Considerations accordingly (Figure10-2). Please see Section11.0 “Comparator Voltage Reference Module” for internal A simplified circuit for an analog input is shown in reference specifications. Figure10-3. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD 10.3 Comparator Response Time and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this Response time is the minimum time after selecting a range by more than 0.6V in either direction, one of the new reference voltage or input source before the diodes is forward biased and a latch-up may occur. A comparator output is to have a valid level. If the maximum source impedance of 10k is comparator inputs are changed, a delay must be used recommended for the analog sources. Any external to allow the comparator to settle to its new state. component connected to an analog input pin, such as Please see Table14-3 for comparator response time a capacitor or a Zener diode, should have very little specifications. leakage current. 10.4 Comparator Output The comparator output is read through the CM1CON0 or CM2CON0 register. This bit is read-only. The comparator output may also be used externally, see Figure10-1. DS41326E-page 66  2010 Microchip Technology Inc.

PIC16F526 FIGURE 10-3: ANALOG INPUT MODE VDD RS < 10K VT = 0.6V RIC AIN VA C5PpIFN VT = 0.6V I±L5E0A0KAnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the Pin RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on All Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Other Resets STATUS RBWUF CWUF PA0 TO PD Z DC C 0001 1xxx qq0q quuu CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU q111 1111 quuu uuuu CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU q111 1111 quuu uuuu TRIS — — I/O Control Register (PORTB, PORTC) --11 1111 --11 1111 Legend: x = Unknown, u = Unchanged, – = Unimplemented, read as ‘0’, q = Depends on condition.  2010 Microchip Technology Inc. DS41326E-page 67

PIC16F526 NOTES: DS41326E-page 68  2010 Microchip Technology Inc.

PIC16F526 11.0 COMPARATOR VOLTAGE 11.2 Voltage Reference Accuracy/Error REFERENCE MODULE The full range of VSS to VDD cannot be realized due to construction of the module. The transistors on the top The Comparator Voltage Reference module also and bottom of the resistor ladder network (Figure11-1) allows the selection of an internally generated voltage reference for one of the C2 comparator inputs. The keep CVREF from approaching VSS or VDD. The exception is when the module is disabled by clearing VRCON register (Register11-1) controls the Voltage the VREN bit of the VRCON register. When disabled, Reference module shown in Figure11-1. the reference voltage is VSS when VR<3:0> is ‘0000’ and the VRR bit of the VRCON register is set. This 11.1 Configuring The Voltage allows the comparator to detect a zero-crossing and Reference not consume the CVREF module current. The voltage reference can output 32 voltage levels; 16 The voltage reference is VDD derived and, therefore, in a high range and 16 in a low range. the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the comparator Equation11-1 determines the output voltages: voltage reference can be found in Section14.0 “Elec- trical Characteristics”. EQUATION 11-1: VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR<3:0> x VDD/32) REGISTER 11-1: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN VROE VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VREN: CVREF Enable bit 1 = CVREF is powered on 0 = CVREF is powered down, no current is drawn bit 6 VROE: CVREF Output Enable bit(1) 1 = CVREF output is enabled 0 = CVREF output is disabled bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ bit 3-0 VR<3:0> CVREF Value Selection bit When VRR = 1: CVREF= (VR<3:0>/24)*VDD When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD Note1: When this bit is set, the TRIS for the CVREF pin is overridden and the analog voltage is placed on the CVREF pin.  2010 Microchip Technology Inc. DS41326E-page 69

PIC16F526 FIGURE 11-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR 16-1 Analog MUX VREN CVREF to Comparator 2 Input VR<3:0> RC2/CVREF VREN VROE VR<3:0> = 0000 VRR TABLE 11-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR other Resets VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 001- 1111 uuu- uuuu CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU q111 1111 quuu uuuu CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU q111 1111 quuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’, q = value depends on condition. DS41326E-page 70  2010 Microchip Technology Inc.

PIC16F526 12.0 INSTRUCTION SET SUMMARY All instructions are executed within a single instruction cycle, unless a conditional test is true or the program The PIC16 instruction set is highly orthogonal and is counter is changed as a result of an instruction. In this comprised of three basic categories. case, the execution takes two instruction cycles. One • Byte-oriented operations instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4MHz, the normal • Bit-oriented operations instruction execution time is 1s. If a conditional test is • Literal and control operations true or the program counter is changed as a result of an Each PIC16 instruction is a 12-bit word divided into an instruction, the instruction execution time is 2s. opcode, which specifies the instruction type, and one Figure12-1 shows the three general formats that the or more operands which further specify the operation instructions can have. All examples in the figure use of the instruction. The formats for each of the the following format to represent a hexadecimal categories is presented in Figure12-1, while the number: various opcode fields are summarized in Table12-1. 0xhhh For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination where ‘h’ signifies a hexadecimal digit. designator. The file register designator specifies which file register is to be used by the instruction. FIGURE 12-1: GENERAL FORMAT FOR INSTRUCTIONS The destination designator specifies where the result of the operation is to be placed. If ‘d’ is ‘0’, the result is Byte-oriented file register operations placed in the W register. If ‘d’ is ‘1’, the result is placed 11 6 5 4 0 in the file register specified in the instruction. OPCODE d f (FILE #) For bit-oriented instructions, ‘b’ represents a bit field d = 0 for destination W designator which selects the number of the bit affected d = 1 for destination f by the operation, while ‘f’ represents the number of the f = 5-bit file register address file in which the bit is located. Bit-oriented file register operations For literal and control operations, ‘k’ represents an 11 8 7 5 4 0 8or 9-bit constant or literal value. OPCODE b (BIT #) f (FILE #) TABLE 12-1: OPCODE FIELD b = 3-bit bit address DESCRIPTIONS f = 5-bit file register address Field Description Literal and control operations (except GOTO) f Register file address (0x00 to 0x7F) 11 8 7 0 W Working register (accumulator) OPCODE k (literal) b Bit address within an 8-bit file register k = 8-bit immediate value k Literal field, constant data or label x Don’t care location (= 0 or 1) Literal and control operations – GOTO instruction The assembler will generate code with x = 0. It is 11 9 8 0 the recommended form of use for compatibility with OPCODE k (literal) all Microchip software tools. d Destination select; k = 9-bit immediate value d = 0 (store result in W) d = 1 (store result in file register ‘f’) Default is d = 1 label Label name TOS Top-of-Stack PC Program Counter WDT Watchdog Timer counter TO Time-out bit PD Power-down bit dest Destination, either the W register or the specified register file location [ ] Options ( ) Contents Æ Assigned to < > Register bit field Œ In the set of italics User defined term (font is courier)  2010 Microchip Technology Inc. DS41326E-page 71

PIC16F526 TABLE 12-2: INSTRUCTION SET SUMMARY Mnemonic, 12-Bit Opcode Status Description Cycles Notes Operands Affected MSb LSb ADDWF f, d Add W and f 1 0001 11df ffff C, DC, Z 1, 2, 4 ANDWF f, d AND W with f 1 0001 01df ffff Z 2, 4 CLRF f Clear f 1 0000 011f ffff Z 4 CLRW — Clear W 1 0000 0100 0000 Z COMF f, d Complement f 1 0010 01df ffff Z DECF f, d Decrement f 1 0000 11df ffff Z 2, 4 DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2, 4 INCF f, d Increment f 1 0010 10df ffff Z 2, 4 INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2, 4 IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2, 4 MOVF f, d Move f 1 0010 00df ffff Z 2, 4 MOVWF f Move W to f 1 0000 001f ffff None 1, 4 NOP — No Operation 1 0000 0000 0000 None RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2, 4 RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2, 4 SUBWF f, d Subtract W from f 1 0000 10df ffff C, DC, Z 1, 2, 4 SWAPF f, d Swap f 1 0011 10df ffff None 2, 4 XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2, 4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 0100 bbbf ffff None 2, 4 BSF f, b Bit Set f 1 0101 bbbf ffff None 2, 4 BTFSC f, b Bit Test f, Skip if Clear 1(2) 0110 bbbf ffff None BTFSS f, b Bit Test f, Skip if Set 1(2) 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Call Subroutine 2 1001 kkkk kkkk None 1 CLRWDT — Clear Watchdog Timer 1 0000 0000 0100 TO, PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR literal with W 1 1101 kkkk kkkk Z MOVLW k Move literal to W 1 1100 kkkk kkkk None OPTION — Load OPTION register 1 0000 0000 0010 None RETLW k Return, place literal in W 2 1000 kkkk kkkk None SLEEP — Go into Standby mode 1 0000 0000 0011 TO, PD TRIS f Load TRIS register 1 0000 0000 0fff None 3 XORLW k Exclusive OR literal to W 1 1111 kkkk kkkk Z Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for GOTO. See Section4.6 “Program Counter”. 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS41326E-page 72  2010 Microchip Technology Inc.

PIC16F526 ADDWF Add W and f BCF Bit Clear f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BCF f,b Operands: 0  f  31 Operands: 0  f  31 d 01 0  b  7 Operation: (W) + (f)  (dest) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is cleared. and register ‘f’. If ‘d’ is’0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W BSF Bit Set f Syntax: [ label ] ANDLW k Syntax: [ label ] BSF f,b Operands: 0  k  255 Operands: 0  f  31 0  b  7 Operation: (W).AND. (k)  (W) Operation: 1  (f<b>) Status Affected: Z Status Affected: None Description: The contents of the W register are AND’ed with the eight-bit literal ‘k’. Description: Bit ‘b’ in register ‘f’ is set. The result is placed in the W register. ANDWF AND W with f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDWF f,d Syntax: [ label ] BTFSC f,b Operands: 0  f  31 Operands: 0  f  31 d [0,1] 0  b  7 Operation: (W) .AND. (f)  (dest) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: The contents of the W register are Description: If bit ‘b’ in register ‘f’ is ‘0’, then the AND’ed with register ‘f’. If ‘d’ is ‘0’, next instruction is skipped. the result is stored in the W register. If bit ‘b’ is ‘0’, then the next instruc- If ‘d’ is ‘1’, the result is stored back tion fetched during the current in register ‘f’. instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction.  2010 Microchip Technology Inc. DS41326E-page 73

PIC16F526 BTFSS Bit Test f, Skip if Set CLRW Clear W Syntax: [ label ] CLRW Syntax: [ label ] BTFSS f,b Operands: None Operands: 0  f  31 0  b < 7 Operation: 00h  (W); 1  Z Operation: skip if (f<b>) = 1 Status Affected: Z Status Affected: None Description: The W register is cleared. Zero bit Description: If bit ‘b’ in register ‘f’ is ‘1’, then the (Z) is set. next instruction is skipped. If bit ‘b’ is ‘1’, then the next instruc- tion fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. CALL Subroutine Call CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  255 Operands: None Operation: (PC) + 1 Top-of-Stack; Operation: 00h  WDT; k  PC<7:0>; 0  WDT prescaler (if assigned); (STATUS<6:5>)  PC<10:9>; 1  TO; 0  PC<8> 1  PD Status Affected: None Status Affected: TO, PD Description: Subroutine call. First, return Description: The CLRWDT instruction resets the address (PC + 1) is PUSHed onto WDT. It also resets the prescaler, if the stack. The eight-bit immediate the prescaler is assigned to the address is loaded into PC WDT and not Timer0. Status bits bits <7:0>. The upper bits TO and PD are set. PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a two-cycle instruction. CLRF Clear f COMF Complement f Syntax: [ label ] CLRF f Syntax: [ label ] COMF f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] Operation: 00h  (f); 1  Z Operation: (f)  (dest) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are cleared and the Z bit is set. complemented. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS41326E-page 74  2010 Microchip Technology Inc.

PIC16F526 DECF Decrement f INCF Increment f Syntax: [ label ] DECF f,d Syntax: [ label ] INCF f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: (f) – 1  (dest) Operation: (f) + 1  (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, Description: The contents of register ‘f’ are the result is stored in the W incremented. If ‘d’ is ‘0’, the result register. If ‘d’ is ‘1’, the result is is placed in the W register. If ‘d’ is stored back in register ‘f’. ‘1’, the result is placed back in register ‘f’. DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: (f) – 1  d; skip if result = 0 Operation: (f) + 1  (dest), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. If the result is ‘0’, the next instruc- If the result is ‘0’, then the next tion, which is already fetched, is instruction, which is already discarded and a NOP is executed fetched, is discarded and a NOP is instead making it a two-cycle executed instead making it a instruction. two-cycle instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  511 Operands: 0  k  255 Operation: k  PC<8:0>; Operation: (W) .OR. (k)  (W) STATUS<6:5>  PC<10:9> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the eight-bit literal ‘k’. The 9-bit immediate value is The result is placed in the loaded into PC bits <8:0>. The W register. upper bits of PC are loaded from STATUS<6:5>. GOTO is a two- cycle instruction.  2010 Microchip Technology Inc. DS41326E-page 75

PIC16F526 IORWF Inclusive OR W with f MOVWF Move W to f Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVWF f Operands: 0  f  31 Operands: 0  f  31 d  [0,1] Operation: (W)  (f) Operation: (W).OR. (f)  (dest) Status Affected: None Status Affected: Z Description: Move data from the W register to Description: Inclusive OR the W register with register ‘f’. register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. MOVF Move f NOP No Operation Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP Operands: 0  f  31 Operands: None d  [0,1] Operation: No operation Operation: (f)  (dest) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register ‘f’ are moved to destination ‘d’. If ‘d’ is ‘0’, destination is the W register. If ‘d’ is ‘1’, the destination is file register ‘f’. ‘d’ = 1 is useful as a test of a file register, since status flag Z is affected. MOVLW Move Literal to W OPTION Load OPTION Register Syntax: [ label ] MOVLW k Syntax: [ label ] OPTION Operands: 0  k  255 Operands: None Operation: k  (W) Operation: (W)  OPTION Status Affected: None Status Affected: None Description: The content of the W register is Description: The eight-bit literal ‘k’ is loaded loaded into the OPTION register. into the W register. The “don’t cares” will assembled as ‘0’s. DS41326E-page 76  2010 Microchip Technology Inc.

PIC16F526 RETLW Return with Literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] RETLW k Syntax: [label ] SLEEP Operands: 0  k  255 Operands: None Operation: k  (W); Operation: 00h  WDT; TOS  PC 0  WDT prescaler; Status Affected: None 1  TO; 0  PD Description: The W register is loaded with the eight-bit literal ‘k’. The program Status Affected: TO, PD, RBWUF counter is loaded from the top of Description: Time-out Status bit (TO) is set. The the stack (the return address). This Power-down Status bit (PD) is is a two-cycle instruction. cleared. RBWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. See Section8.9 “Power-down Mode (Sleep)” on Sleep for more details. RLF Rotate Left f through Carry SUBWF Subtract W from f Syntax: [ label ] RLF f,d Syntax: [label ] SUBWF f,d Operands: 0  f  31 Operands: 0 f 31 d  [0,1] d  [0,1] Operation: See description below Operation: (f) – (W) dest) Status Affected: C Status Affected: C, DC, Z Description: The contents of register ‘f’ are Description: Subtract (2’s complement method) rotated one bit to the left through the W register from register ‘f’. If ‘d’ the Carry flag. If ‘d’ is ‘0’, the result is ‘0’, the result is stored in the W is placed in the W register. If ‘d’ is register. If ‘d’ is ‘1’, the result is ‘1’, the result is stored back in stored back in register ‘f’. register ‘f’. C register ‘f’ RRF Rotate Right f through Carry SWAPF Swap Nibbles in f Syntax: [ label ] RRF f,d Syntax: [ label ] SWAPF f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: See description below Operation: (f<3:0>)  (dest<7:4>); (f<7:4>)  (dest<3:0>) Status Affected: C Status Affected: None Description: The contents of register ‘f’ are rotated one bit to the right through Description: The upper and lower nibbles of the Carry flag. If ‘d’ is ‘0’, the result register ‘f’ are exchanged. If ‘d’ is is placed in the W register. If ‘d’ is ‘0’, the result is placed in W ‘1’, the result is placed back in register. If ‘d’ is ‘1’, the result is register ‘f’. placed in register ‘f’. C register ‘f’  2010 Microchip Technology Inc. DS41326E-page 77

PIC16F526 TRIS Load TRIS Register XORWF Exclusive OR W with f Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d Operands: f = 6 Operands: 0  f  31 Operation: (W)  TRIS register f d  [0,1] Status Affected: None Operation: (W) .XOR. (f) dest) Description: TRIS register ‘f’ (f = 6 or 7) is Status Affected: Z loaded with the contents of the W Description: Exclusive OR the contents of the register W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is XORLW Exclusive OR literal with W stored back in register ‘f’. Syntax: [label ] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. DS41326E-page 78  2010 Microchip Technology Inc.

PIC16F526 13.0 DEVELOPMENT SUPPORT 13.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2010 Microchip Technology Inc. DS41326E-page 79

PIC16F526 13.2 MPLAB C Compilers for Various 13.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 13.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 13.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 13.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS41326E-page 80  2010 Microchip Technology Inc.

PIC16F526 13.7 MPLAB SIM Software Simulator 13.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 13.10 PICkit 3 In-Circuit Debugger/ Programmer and 13.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers signifi- cant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a rugge- dized probe interface and long (up to three meters) inter- connection cables.  2010 Microchip Technology Inc. DS41326E-page 81

PIC16F526 13.11 PICkit 2 Development 13.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 13.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS41326E-page 82  2010 Microchip Technology Inc.

PIC16F526 14.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40°C to +125°C Storage temperature............................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS...............................................................................................................0 to +6.5V Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V Voltage on all other pins with respect to VSS...............................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)..................................................................................................................................700mW Max. current out of VSS pin................................................................................................................................200mA Max. current into VDD pin...................................................................................................................................150mA Input clamp current, IIK (VI < 0 or VI > VDD)20mA Output clamp current, IOK (VO < 0 or VO > VDD)20mA Max. output current sunk by any I/O pin..............................................................................................................25mA Max. output current sourced by any I/O pin.........................................................................................................25mA Max. output current sourced by I/O port ..............................................................................................................75mA Max. output current sunk by I/O port ...................................................................................................................75mA Note1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2010 Microchip Technology Inc. DS41326E-page 83

PIC16F526 FIGURE 14-1: PIC16F526 VOLTAGE-FREQUENCY GRAPH, -40C  TA  +125C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 INTOSC OR 2.5 EC MODE ON LY 2.0 0 4 10 20 25 Frequency (MHz) FIGURE 14-2: MAXIMUM OSCILLATOR FREQUENCY TABLE LP XT e d o XTRC M r ato INTOSC scill EC O HS 0 200 kHz 4 MHz 8 MHz 20 MHz Frequency DS41326E-page 84  2010 Microchip Technology Inc.

PIC16F526 14.1 DC Characteristics: PIC16F526 (Industrial) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature -40C  TA  +85C (industrial) Param Sym. Characteristic Min. Typ.(1) Max. Units Conditions No. D001 VDD Supply Voltage 2.0 5.5 V See Figure14-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure — Vss — V See Section8.4 “Power-on Power-on Reset Reset (POR)” for details D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section8.4 “Power-on Power-on Reset Reset (POR)” for details D005 IDDP Supply Current During Prog/ — 250* — A Erase D010 IDD Supply Current(3, 4, 6) — 175 250 A FOSC = 4MHz, VDD = 2.0V — 400 700 A FOSC = 4MHz, VDD = 5.0V — 250 400 A FOSC = 8MHz, VDD = 2.0V — 0.75 1.2 mA FOSC = 8MHz, VDD = 5.0V — 1.4 2.2 mA FOSC = 20MHz, VDD = 5.0V — 11 22 A FOSC = 32kHz, VDD = 2.0V — 38 55 A FOSC = 32kHz, VDD = 5.0V D020 IPD Power-down Current(5) — 0.1 1.2 A VDD = 2.0V — 0.35 2.2 A VDD = 5.0V D022 IWDT WDT Current(5) — 1.0 3.0 A VDD = 2.0V — 7.0 16.0 A VDD = 5.0V D023 ICMP Comparator Current(5) — 15 26 A VDD = 2.0V (per comparator) — 60 76 A VDD = 5.0V (per comparator) D022 ICVREF CVREF Current(5) — 30 75 A VDD = 2.0V (high range) — 75 135 A VDD = 5.0V (high range) D023 IFVR Internal 0.6V Fixed Voltage — 100 120 A VDD = 2.0V (reference and 1 Reference Current(5) comparator enabled) — 175 205 A VDD = 5.0V (reference and 1 comparator enabled) D024 IAD* A/D Conversion Current — 120 150 A 2.0V — 200 250 A 5.0V * These parameters are characterized but not tested. Note1: Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep. 6: For EXTRC mode, does not include current through REXT. The current through the resistor can be estimated by the formula: I = VDD/2REXT (mA) with REXT in k.  2010 Microchip Technology Inc. DS41326E-page 85

PIC16F526 14.2 DC Characteristics: PIC16F526 (Extended) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature -40C  TA  +125C (extended) Param Sym. Characteristic Min. Typ.(1) Max. Units Conditions No. D001 VDD Supply Voltage 2.0 5.5 V See Figure14-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure — Vss — V See Section8.4 “Power-on Power-on Reset Reset (POR)” for details D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section8.4 “Power-on Power-on Reset Reset (POR)” for details D005 IDDP Supply Current During Prog/ — 250* — A Erase D010 IDD Supply Current(3,4,6) — 175 250 A FOSC = 4MHz, VDD = 2.0V — 400 700 A FOSC = 4MHz, VDD = 5.0V — 250 400 A FOSC = 8MHz, VDD = 2.0V — 0.75 1.2 mA FOSC = 8MHz, VDD = 5.0V — 1.4 2.2 mA FOSC = 20MHz, VDD = 5.0V — 11 26 A FOSC = 32kHz, VDD = 2.0V — 38 110 A FOSC = 32kHz, VDD = 5.0V D020 IPD Power-down Current(5) — 0.1 9.0 A VDD = 2.0V — 0.35 15.0 A VDD = 5.0V D022 IWDT WDT Current(5) — 1.0 18 A VDD = 2.0V — 7.0 22 A VDD = 5.0V D023 ICMP Comparator Current(5) — 15 26 A VDD = 2.0V (per comparator) — 60 76 A VDD = 5.0V (per comparator) D022 IcVREF CvREF Current(5) — 30 75 A VDD = 2.0V (high range) — 75 135 A VDD = 5.0V (high range) D023 IFVR Internal 0.6V Fixed Voltage — 100 130 A VDD = 2.0V (reference and 1 Reference Current(5) comparator enabled) — 175 220 A VDD = 5.0V (reference and 1 comparator enabled) D024 IAD* A/D Conversion Current — 120 150 A 2.0V — 200 250 A 5.0V * These parameters are characterized but not tested. Note1: Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep. 6: For EXTRC mode, does not include current through REXT. The current through the resistor can be estimated by the formula: I = VDD/2REXT (mA) with REXT in k. DS41326E-page 86  2010 Microchip Technology Inc.

PIC16F526 TABLE 14-1: DC CHARACTERISTICS: PIC16F526 (Industrial, Extended) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C (industrial) -40°C  TA  +125°C (extended) Operating voltage VDD range as described in DC spec. Param Sym. Characteristic Min. Typ.† Max. Units Conditions No. VIL Input Low Voltage I/O ports D030 with TTL buffer Vss — 0.8 V For all 4.5  VDD 5.5V D030A Vss — 0.15 VDD V Otherwise D031 with Schmitt Trigger buffer Vss — 0.15 VDD V D032 MCLR, T0CKI Vss — 0.15 VDD V D033 OSC1 (EXTRC mode), EC(1) Vss — 0.15 VDD V D033 OSC1 (HS mode) Vss — 0.3 VDD V D033 OSC1 (XT and LP modes) Vss — 0.3 V VIH Input High Voltage I/O ports — D040 with TTL buffer 2.0 — VDD V 4.5  VDD 5.5V D040A 0.25VDD — VDD V Otherwise + 0.8V D041 with Schmitt Trigger buffer 0.85VDD — VDD V For entire VDD range D042 MCLR, T0CKI 0.85VDD — VDD V D042A OSC1 (EXTRC mode), EC(1) 0.85VDD — VDD V D042A OSC1 (HS mode) 0.7VDD — VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V D070 IPUR PORTB weak pull-up current(4) 50 250 400 A VDD = 5V, VPIN = VSS IIL Input Leakage Current(2,5) D060 I/O ports — — ±1 A Vss VPIN VDD, Pin at high-impedance D061 RB3/MCLR(3) — ±0.7 ±5 A Vss VPIN VDD D063 OSC1 — — ±5 A Vss VPIN VDD, XT, HS and LP osc configuration VOL Output Low Voltage D080 I/O ports/CLKOUT — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, –40C to +85C D080A — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, –40C to +125C VOH Output High Voltage D090 I/O ports/CLKOUT VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, –40C to +85C D090A VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, –40C to +125C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 CIO All I/O pins and OSC2 — — 50 pF Flash Data Memory D120 ED Byte endurance 100K 1M — E/W –40C  TA  +85C D120A ED Byte endurance 10K 100K — E/W +85C  TA  +125C D121 VDRW VDD for read/write VMIN — 5.5 V † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F526 be driven with external clock in RC mode. 2: Negative current is defined as coming out of the pin. 3: This spec. applies to RB3/MCLR configured as RB3 with pull-up disabled. 4: This spec. applies to all weak pull-up devices, including the weak pull-up found on RB3/MCLR. The current value listed will be the same whether or not the pin is configured as RB3 with pull-up enabled or as MCLR. 5: The leakage current on the nMCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage may be measured at different input voltages.  2010 Microchip Technology Inc. DS41326E-page 87

PIC16F526 TABLE 14-2: COMPARATOR SPECIFICATIONS. Standard Operating Conditions (unless otherwise stated) Comparator Specifications Operating temperature -40°C to 125°C Characteristics Sym. Min. Typ. Max. Units Comments Internal Voltage Reference VIVRF 0.50 0.60 0.70 V Input offset voltage VOS —  5.0  10 mV Input common mode voltage* VCM 0 — VDD – 1.5 V CMRR* CMRR 55 — — db Response Time(1)* TRT — 150 400 ns Comparator Mode Change to TMC2COV — — 10 s Output Valid* * These parameters are characterized but not tested. Note1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from VSS to VDD – 1.5V. TABLE 14-3: COMPARATOR VOLTAGE REFERENCE (VREF) SPECIFICATIONS Sym. Characteristics Min. Typ. Max. Units Comments CVRES Resolution — VDD/24* — LSb Low Range (VRR = 1) — VDD/32 — LSb High Range (VRR = 0) Absolute Accuracy(2) — — ±1/2* LSb Low Range (VRR = 1) — — ±1/2* LSb High Range (VRR = 0) Unit Resistor Value (R) — 2K* —  — Settling Time(1) — — 10* s * These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111. 2: Do not use reference externally when VDD < 2.7V. Under this condition, reference should only be used with comparator Voltage Common mode observed. DS41326E-page 88  2010 Microchip Technology Inc.

PIC16F526 TABLE 14-4: A/D CONVERTER CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) A/D Converter Specifications Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ.† Max. Units Conditions No. A01 NR Resolution — — 8 bit A03 EINL Integral Error — — 1.5 LSb VDD = 5.0V A04 EDNL Differential Error — — -1< EDNL 1.7 LSb No missing codes to 8 bits VDD = 5.0V A06 EOFF Offset Error — — 1.5 LSb VDD = 5.0V A07 EGN Gain Error -0.7 — +2.2 LSb VDD = 5.0V A10 — Monotonicity — guaranteed(1) — — VSS  VAIN  VDD A25 VAIN Analog Input VSS — VDD V Voltage A30 ZAIN Recommended — — 10 K Impedance of Analog Voltage Source * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. TABLE 14-5: PULL-UP RESISTOR RANGES VDD (Volts) Temperature (C) Min. Typ. Max. Units RB0/RB1/RB4 2.0 -40 73K 105K 186K  25 73K 113K 187K  85 82K 123K 190K  125 86K 132k 190K  5.5 -40 15K 21K 33K  25 15K 22K 34K  85 19K 26k 35K  125 23K 29K 35K  RB3 2.0 -40 63K 81K 96K  25 77K 93K 116K  85 82K 96k 116K  125 86K 100K 119K  5.5 -40 16K 20k 22K  25 16K 21K 23K  85 24K 25k 28K  125 26K 27K 29K   2010 Microchip Technology Inc. DS41326E-page 89

PIC16F526 14.3 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc Oscillator cy Cycle time os OSC1 drt Device Reset Timer t0 T0CKI io I/O port wdt Watchdog Timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (high-impedance) V Valid L Low Z High-impedance FIGURE 14-3: LOAD CONDITIONS Legend: pin CL CL = 50 pF for all pins except OSC2 15 pF for OSC2 in XT, HS or LP modes when external clock VSS is used to drive OSC1 DS41326E-page 90  2010 Microchip Technology Inc.

PIC16F526 FIGURE 14-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 TABLE 14-6: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial), AC CHARACTERISTICS -40C  TA  +125C (extended) Operating Voltage VDD range is described in Section14.1 “DC Characteristics: PIC16F526 (Industrial)” Param Sym. Characteristic Min. Typ.(1) Max. Units Conditions No. 1A FOSC External CLKIN Frequency(2) DC — 4 MHz XT Oscillator mode DC — 20 MHz HS/EC Oscillator mode DC — 200 kHz LP Oscillator mode Oscillator Frequency(2) — — 4 MHz EXTRC Oscillator mode 0.1 — 4 MHz XT Oscillator mode 4 — 20 MHz HS/EC Oscillator mode — — 200 kHz LP Oscillator mode 1 TOSC External CLKIN Period(2) 250 — — ns XT Oscillator mode 50 — — ns HS/EC Oscillator mode 5 — — s LP Oscillator mode Oscillator Period(2) 250 — — ns EXTRC Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 250 ns HS/EC Oscillator mode 5 — — s LP Oscillator mode 2 TCY Instruction Cycle Time 200 4/FOSC — ns 3 TosL, Clock in (OSC1) Low or High 50* — — ns XT Oscillator TosH Time 2* — — s LP Oscillator 10* — — ns HS/EC Oscillator 4 TosR, Clock in (OSC1) Rise or Fall — — 25* ns XT Oscillator TosF Time — — 50* ns LP Oscillator — — 15* ns HS/EC Oscillator * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.  2010 Microchip Technology Inc. DS41326E-page 91

PIC16F526 TABLE 14-7: CALIBRATED INTERNAL RC FREQUENCIES Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial), AC CHARACTERISTICS -40C  TA  +125C (extended) Operating Voltage VDD range is described in Section14.1 “DC Characteristics: PIC16F526 (Industrial)” Param Freq. Sym. Characteristic Min. Typ.† Max. Units Conditions No. Tolerance F10 FOSC Internal Calibrated 1% 7.92 8.00 8.08 MHz 3.5V, +25C INTOSC Frequency(1) 2% 7.84 8.00 8.16 MHz 2.5V VDD  5.5V 0C  TA  +85C 5% 7.60 8.00 8.40 MHz 2.0V VDD  5.5V -40C  TA  +85C (Ind.) -40C  TA  +125C (Ext.) * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1uF and 0.01uF values in parallel are recommended. DS41326E-page 92  2010 Microchip Technology Inc.

PIC16F526 FIGURE 14-5: I/O TIMING Q4 Q1 Q2 Q3 OSC1 I/O Pin (input) 17 19 18 I/O Pin Old Value New Value (output) 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50pF on I/O pins and CLKOUT. TABLE 14-8: TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) AC -40C  TA  +125C (extended) CHARACTERISTICS Operating Voltage VDD range is described in Section14.1 “DC Characteristics: PIC16F526 (Industrial)” Param Sym. Characteristic Min. Typ.(1) Max. Units No. 17 TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid(2), (3) — — 100* ns 18 TOSH2IOI OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time)(2) 50 — — ns 19 TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 20 — — ns 20 TIOR Port Output Rise Time(3) — 10 50** ns 21 TIOF Port Output Fall Time(3) — 10 58** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure14-3 for loading conditions.  2010 Microchip Technology Inc. DS41326E-page 93

PIC16F526 FIGURE 14-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING VDD MCLR 30 Internal POR 32 32 32 DRT Time-out(2) Internal Reset Watchdog Timer Reset 31 34 34 I/O pin(1) Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT Reset only in XT, LP and HS modes. TABLE 14-9: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) AC CHARACTERISTICS -40C  TA  +125C (extended) Operating Voltage VDD range is described in Section14.1 “DC Characteristics: PIC16F526 (Industrial)” Param Sym. Characteristic Min. Typ.(1) Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2000* — — ns VDD = 5.0V 31 TWDT Watchdog Timer Time-out Period 9* 18* 30* ms VDD = 5.0V (Industrial) (no prescaler) 9* 18* 40* ms VDD = 5.0V (Extended) 32 TDRT Device Reset Timer Period Standard 9* 18* 30* ms VDD = 5.0V (Industrial) 9* 18* 40* ms VDD = 5.0V (Extended) Short 0.5* 1.125* 2* ms VDD = 5.0V (Industrial) 0.5* 1.125* 2.5* ms VDD = 5.0V (Extended) 34 TIOZ I/O High-impedance from MCLR — — 2000* ns low * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41326E-page 94  2010 Microchip Technology Inc.

PIC16F526 FIGURE 14-7: TIMER0 CLOCK TIMINGS T0CKI 40 41 42 TABLE 14-10: TIMER0 CLOCK REQUIREMENT Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) AC CHARACTERISTICS -40C  TA  +125C (extended) Operating Voltage VDD range is described in Section14.1 “DC Characteristics: PIC16F526 (Industrial)” Param Sym. Characteristic Min. Typ.(1) Max. Units Conditions No. 40 Tt0H T0CKI High Pulse No Prescaler 0.5 TCY + 20* — — ns Width With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse No Prescaler 0.5 TCY + 20* — — ns Width With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* N — — ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. DS41326E-page 95

PIC16F526 TABLE 14-11: FLASH DATA MEMORY WRITE/ERASE TIME Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) AC CHARACTERISTICS -40C  TA  +125C (extended) Operating Voltage VDD range is described in Section14.1 “DC Characteristics: PIC16F526 (Industrial)” Param Sym. Characteristic Min. Typ.(1) Max. Units Conditions No. 43 TDW Flash Data Memory 2 3.5 5 ms Write Cycle Time 44 TDE Flash Data Memory 2 3.5 5 ms Erase Cycle Time * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41326E-page 96  2010 Microchip Technology Inc.

PIC16F526 15.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean+3) or (mean - 3) respectively, where s is a standard deviation, over each temperature range. FIGURE 15-1: IDD VS. FOSC Over VDD (HS Mode) 3.00 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 2.50 (-40°C to 125°C) Max. 5V 2.00 A) m 1.50 (D Typical 5V D I 1.00 0.50 Max. 2V Typical 2V 0.00 5 10 15 20 25 Fosc (MHz)  2010 Microchip Technology Inc. DS41326E-page 97

PIC16F526 FIGURE 15-2: TYPICAL IDD vs. FOSC OVER VDD (XT, EXTRC mode) 800 Typical: Statistical Mean @25°C 700 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 600 500 5V A) 400  (D ID 300 200 2V 100 0 0 1 2 3 4 5 FOSC (MHz) FIGURE 15-3: MAXIMUM IDD vs. FOSC OVER VDD (XT, EXTRC mode) 800 5V Typical: Statistical Mean @25°C 700 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 600 500 A)  400 (D D I 300 2V 200 100 0 0 1 2 3 4 5 FOSC (MHz) DS41326E-page 98  2010 Microchip Technology Inc.

PIC16F526 FIGURE 15-4: IDD vs. VDD OVER FOSC (LP MODE) 120 Typical: Statistical Mean @25°C  Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ 100 (-40°C to 125°C) 32 kHz Maximum Extended 80 A)  (D 60 32 kHz Maximum Industrial D I 32 kHz Typical 40 20 0 1 2 3 4 5 6 VDD (V)  2010 Microchip Technology Inc. DS41326E-page 99

PIC16F526 FIGURE 15-5: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 0.45 Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0.35 0.30 A) 0.25  (D P 0.20 I 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-6: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 18.0 Typical: Statistical Mean @25°C 16.0 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 14.0 Max. 125°C 12.0 A) 10.0  (D P 8.0 I 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41326E-page 100  2010 Microchip Technology Inc.

PIC16F526 FIGURE 15-7: TYPICAL WDT IPD vs. VDD 9 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 7 (-40°C to 125°C) 6 A) 5  (PD 4 I 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-8: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE 25.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 20.0 Max. 125°C 15.0 A)  (D P I 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2010 Microchip Technology Inc. DS41326E-page 101

PIC16F526 FIGURE 15-9: COMPARATOR IPD vs. VDD (COMPARATOR ENABLED) 80 Typical: Statistical Mean @25°C Maximum Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Typical 60 A)  (PD 40 I 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-10: WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER) 50 Typical: Statistical Mean @25°C 45 Max. 125°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 40 Max. 85°C 35 30 ms) Typical. 25°C e ( 25 m Ti 20 Min. -40°C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41326E-page 102  2010 Microchip Technology Inc.

PIC16F526 FIGURE 15-11: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 0.6 Max. 85°C 0.5 V) (L 0.4 O V 0.3 Typical 25°C 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 15-12: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C 0.40 MaximTuympi:c aMl:e Santa (tiWstoicraslt -MCeaasne @Te2m5p×)C + 3 Maximum: Mea s( -+4 03×C to 125×C) (-40°C to 125°C) Max. 125°C 0.35 Max. 85°C 0.30 0.25 V) (L Typ. 25°C O V 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA)  2010 Microchip Technology Inc. DS41326E-page 103

PIC16F526 FIGURE 15-13: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C 2.0 V) (H O V 1.5 Typical: Statistical Mean @25°C 1.0 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 15-14: VOH vs. IOH OVER TE(MPERAT, URE (VDD = 5).0V) 5.5 5.0 Max. -40°C Typ. 25°C 4.5 V) Min. 125°C (H O V 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) DS41326E-page 104  2010 Microchip Technology Inc.

PIC16F526 FIGURE 15-15: TTL INPUT THRESHOLD VIN vs. VDD (TTL Input, -40×C TO 125×C) 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. -40°C 1.3 Typ. 25°C V) (N 1.1 VI Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-16: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) VIH Min. -40°C 3.0 2.5 V) (N VI 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2010 Microchip Technology Inc. DS41326E-page 105

PIC16F526 FIGURE 15-17: DEVICE RESET TIMER (HS, XT AND LP) vs. VDD Maximum (Sleep Mode all Peripherals Disabled) 45 40 35 Max. 125°C 30 ms) 25 RT ( Max. 85°C D 20 Typical. 25°C 15 Min. -40°C 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Note: See Table14-9 if another clock mode is selected. DS41326E-page 106  2010 Microchip Technology Inc.

PIC16F526 16.0 PACKAGING INFORMATION 16.1 Package Marking Information 14-Lead PDIP (300 mil) Example XXXXXXXXXXXXXX PIC16F526 XXXXXXXXXXXXXX -I/PG e3 0215 YYWWNNN 0410017 14-Lead SOIC (3.90 mm) Example XXXXXXXXXXX PIC16F526-E XXXXXXXXXXX /SLG0125 YYWWNNN 0431017 14-Lead TSSOP (4.4 mm) Example XXXXXXXX 16F526-I YYWW 0431 NNN 017 16-Lead QFN Example XXX MG1 YYWW 0431 NNN 017 TABLE 16-1: 16-LEAD 3X3 QFN (MG) TOP MARKING Part Number Marking PIC16F526-I/MG MG1 PIC16F526-E/MG MG2 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2010 Microchip Technology Inc. DS41326E-page 107

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(cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:20)(cid:4)(cid:29)(cid:4).(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2(cid:2)1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)(cid:4)01 DS41326E-page 108  2010 Microchip Technology Inc.

PIC16F526 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)!(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)"(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)!(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)(cid:31)(cid:7)##(cid:27)$%(cid:9)(cid:23)&’(cid:24)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)!"(cid:18)((cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 3 e h b α h φ c A A2 A1 L β L1 6(cid:15)(cid:7)% (cid:6)(cid:19)99(cid:19)(cid:6)-(cid:13)-(cid:26)(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:29)(cid:23) (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:29)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)% (cid:25) < < (cid:29)(cid:20)(cid:5)0 (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:29)(cid:20)(cid:3)0 < < (cid:22)%(cid:28)(cid:15)"(cid:10)$$(cid:2)(cid:2)* (cid:25)(cid:29) (cid:4)(cid:20)(cid:29)(cid:4) < (cid:4)(cid:20)(cid:3)0 :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)"%(cid:11) - ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22)+ (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) ,(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) >(cid:20)?0(cid:2)1(cid:22)+ +(cid:11)(cid:28)&$(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)%(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)0 < (cid:4)(cid:20)0(cid:4) 3(cid:10)(cid:10)%(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) < (cid:29)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)%(cid:12)(cid:9)(cid:7)(cid:15)% 9(cid:29) (cid:29)(cid:20)(cid:4)(cid:23)(cid:2)(cid:26)-3 3(cid:10)(cid:10)%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B < >B 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:29)(cid:5) < (cid:4)(cid:20)(cid:3)0 9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:4)(cid:20),(cid:29) < (cid:4)(cid:20)0(cid:29) (cid:6)(cid:10)(cid:16)"(cid:2)(cid:21)(cid:9)(cid:28)$%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) 0B < (cid:29)0B (cid:6)(cid:10)(cid:16)"(cid:2)(cid:21)(cid:9)(cid:28)$%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)%%(cid:10)& (cid:5) 0B < (cid:29)0B (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) *(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)$(cid:7)(cid:8)(cid:28)(cid:15)%(cid:2)+(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)%(cid:14)(cid:9)(cid:7) %(cid:7)(cid:8)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:4)(cid:20)(cid:29)0(cid:2)&&(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2 1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)-32 (cid:26)(cid:14)$(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)’(cid:2)! !(cid:28)(cid:16)(cid:16)(cid:18)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2)$(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)$(cid:10)(cid:9)&(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)!(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)?01  2010 Microchip Technology Inc. DS41326E-page 109

PIC16F526 (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS41326E-page 110  2010 Microchip Technology Inc.

PIC16F526 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9))*(cid:14)(cid:19)(cid:9)!*#(cid:14)(cid:19)+(cid:9)!(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)"(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)!)(cid:21)(cid:9)(cid:22)(cid:9)(cid:3)&(cid:3)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29))!!"(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 e b c φ A A2 A1 L1 L 6(cid:15)(cid:7)% (cid:6)(cid:19)99(cid:19)(cid:6)-(cid:13)-(cid:26)(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:29)(cid:23) (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?0(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)% (cid:25) < < (cid:29)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20)>(cid:4) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)(cid:4)0 (cid:22)%(cid:28)(cid:15)"(cid:10)$$(cid:2) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)0 < (cid:4)(cid:20)(cid:29)0 :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)"%(cid:11) - ?(cid:20)(cid:23)(cid:4)(cid:2)1(cid:22)+ (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) (cid:23)(cid:20),(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)0(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) (cid:23)(cid:20)(cid:24)(cid:4) 0(cid:20)(cid:4)(cid:4) 0(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)%(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) 9 (cid:4)(cid:20)(cid:23)0 (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)0 3(cid:10)(cid:10)%(cid:12)(cid:9)(cid:7)(cid:15)% 9(cid:29) (cid:29)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26)-3 3(cid:10)(cid:10)%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B < >B 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) < (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:4)(cid:20)(cid:29)(cid:24) < (cid:4)(cid:20),(cid:4) (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! 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DS41326E-page 111

PIC16F526 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41326E-page 112  2010 Microchip Technology Inc.

PIC16F526 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS41326E-page 113

PIC16F526 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41326E-page 114  2010 Microchip Technology Inc.

PIC16F526 APPENDIX A: REVISION HISTORY Revision A (August 2007) Original release of this document. Revision B (December 2008) Added DC and AC Characteristics graphs; Updated Electrical Characteristics section; added I/O diagrams; updated the Flash Data Memory Control Section; made various changes to the Special Features of the CPU Section and made general edits. Miscellaneous updates. Revision C (July 2009) Removed “Preliminary” status; Revised Table 6-3: I/O Pins; Revised Table 8-3: Reset Conditions; Revised Table 14-4: A/D Converter Char. Revision D (March 2010) Added Package Drawings and Package Marking Information for the 16-Lead Package Quad Flat, No Lead Package (MG) - 3x3x0.9 mm Body (QFN); Updated the Product Identification System section. Revision E (June 2010) Revised Section 6 (I/O) Figures 6-1, 6-4 and 6-6.  2010 Microchip Technology Inc. DS41326E-page 115

PIC16F526 NOTES: DS41326E-page 116  2010 Microchip Technology Inc.

PIC16F526 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.  2010 Microchip Technology Inc. DS41326E-page 117

PIC16F526 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16F526 Literature Number: DS41326E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41326E-page 118  2010 Microchip Technology Inc.

PIC16F526 INDEX A Program Memory (PIC16F526)..................................15 Microchip Internet Web Site..............................................115 A/D MPLAB ASM30 Assembler, Linker, Librarian.....................80 Specifications..............................................................89 MPLAB Integrated Development Environment Software....79 ALU.....................................................................................11 MPLAB PM3 Device Programmer......................................82 Assembler MPLAB REAL ICE In-Circuit Emulator System..................81 MPASM Assembler.....................................................80 MPLINK Object Linker/MPLIB Object Librarian..................80 B O Block Diagram Option Register...................................................................19 Comparator for the PIC16F526...................................65 OSC selection.....................................................................43 On-Chip Reset Circuit.................................................51 OSCCAL Register...............................................................20 Timer0.........................................................................37 Oscillator Configurations.....................................................45 TMR0/WDT Prescaler.................................................41 Oscillator Types Watchdog Timer..........................................................54 HS...............................................................................45 Brown-Out Protection Circuit..............................................55 LP...............................................................................45 C RC..............................................................................45 C Compilers XT...............................................................................45 MPLAB C18................................................................80 P Carry...................................................................................11 PIC16F526 Device Varieties.................................................9 Clock Divisors.....................................................................59 POR Clocking Scheme................................................................14 Device Reset Timer (DRT)...................................43, 53 Code Protection............................................................43, 57 PD...............................................................................55 CONFIG1 Register..............................................................44 Power-on Reset (POR)...............................................43 Configuration Bits................................................................43 TO...............................................................................55 Customer Change Notification Service.............................115 PORTB...............................................................................27 Customer Notification Service...........................................115 PORTC...............................................................................27 Customer Support.............................................................115 Power-down Mode..............................................................56 D Prescaler............................................................................40 Data Memory (SRAM and FSRs) Program Counter................................................................21 Register File Map..................................................16, 17 Q DC and AC Characteristics.................................................97 Q cycles..............................................................................14 Graphs and Tables.....................................................97 Development Support.........................................................79 R Digit Carry...........................................................................11 RC Oscillator.......................................................................46 E Reader Response.............................................................116 Read-Modify-Write..............................................................36 Errata....................................................................................5 Registers F CONFIG1 (Configuration Word Register 1)................44 Flash Data Memory Control................................................23 Special Function.........................................................16 FSR.....................................................................................22 Reset..................................................................................43 Fuses. See Configuration Bits S I Sleep............................................................................43, 56 I/O Interfacing.....................................................................29 Software Simulator (MPLAB SIM)......................................81 I/O Ports..............................................................................27 Special................................................................................17 I/O Programming Considerations........................................36 Special Features of the CPU..............................................43 ID Locations..................................................................43, 57 Special Function Registers...........................................16, 17 INDF....................................................................................22 Stack...................................................................................21 Indirect Data Addressing.....................................................22 STATUS register.................................................................55 Instruction Cycle.................................................................14 Status Register.............................................................11, 18 Instruction Flow/Pipelining..................................................14 T Instruction Set Summary.....................................................72 Timer0 Internet Address................................................................115 Timer0........................................................................37 L Timer0 (TMR0) Module..............................................37 Loading of PC.....................................................................21 TMR0 with External Clock..........................................39 Timing Diagrams and Specifications..................................91 M Timing Parameter Symbology and Load Conditions..........90 Memory Organization..........................................................15 TRIS Register.....................................................................27 Memory Map...............................................................15 PIC16F526..................................................................15  2010 Microchip Technology Inc. DS41326E-page 119

PIC16F526 W Wake-up from Sleep...........................................................56 Watchdog Timer (WDT)................................................43, 53 Period..........................................................................53 Programming Considerations.....................................53 WWW Address..................................................................115 WWW, On-Line Support........................................................5 Z Zero bit................................................................................11 DS41326E-page 120  2010 Microchip Technology Inc.

PIC16F526 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F526-E/P 301 = Extended Temp., PDIP Range package, QTP pattern #301 b) PIC16F526-I/SL = Industrial Temp., SOIC package c) PIC16F526T-E/P = Extended Temp., PDIP Device: PIC16F526 PIC16F526T(1) package, Tape and Reel d) PIC16F526T-I/MG = Industrial Temp., QFN Package, Tape and Reel Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Package: P = Plastic (PDIP)(2) SL = 14L Small Outline, 3.90 mm (SOIC)(2) ST = Thin Shrink Small Outline (TSSOP)(2) MG = 16-Lead 3x3 (QFN)(2) Note1: T = in tape and reel SOIC, TSSOP and Pattern: Special Requirements QFN packages only 2: Pb-free.  2010 Microchip Technology Inc. DS41326E-page 121

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