PIC12F508/509/16F505 Data Sheet 8/14-Pin, 8-Bit Flash Microcontrollers © 2009 Microchip Technology Inc. DS41236E

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of Microchip MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries. WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard, arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41236E-page 2 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 8/14-Pin, 8-Bit Flash Microcontrollers Devices Included In This Data Sheet: Low-Power Features/CMOS Technology: • PIC12F508 • PIC12F509 • PIC16F505 • Operating Current: - < 175μA @ 2V, 4MHz, typical High-Performance RISC CPU: • Standby Current: - 100nA @ 2V, typical • Only 33 Single-Word Instructions to Learn • Low-Power, High-Speed Flash Technology: • All Single-Cycle Instructions Except for Program - 100,000 Flash endurance Branches, which are Two-Cycle - > 40 year retention • 12-Bit Wide Instructions • Fully Static Design • 2-Level Deep Hardware Stack • Wide Operating Voltage Range: 2.0V to 5.5V • Direct, Indirect and Relative Addressing modes for Data and Instructions • Wide Temperature Range: • 8-Bit Wide Data Path - Industrial: -40°C to +85°C • 8 Special Function Hardware Registers - Extended: -40°C to +125°C • Operating Speed: Peripheral Features (PIC12F508/509): - DC – 20MHz clock input (PIC16F505 only) - DC – 200ns instruction cycle (PIC16F505 • 6 I/O Pins: only) - 5 I/O pins with individual direction control - DC – 4MHz clock input - 1 input only pin - DC – 1000ns instruction cycle - High current sink/source for direct LED drive - Wake-on-change Special Microcontroller Features: - Weak pull-ups • 4MHz Precision Internal Oscillator: • 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit - Factory calibrated to ±1% Programmable Prescaler • In-Circuit Serial Programming™ (ICSP™) Peripheral Features (PIC16F505): • In-Circuit Debugging (ICD) Support • Power-On Reset (POR) • 12 I/O Pins: • Device Reset Timer (DRT) - 11 I/O pins with individual direction control • Watchdog Timer (WDT) with Dedicated On-Chip - 1 input only pin RC Oscillator for Reliable Operation - High current sink/source for direct LED drive • Programmable Code Protection - Wake-on-change • Multiplexed MCLR Input Pin - Weak pull-ups • Internal Weak Pull-Ups on I/O Pins • 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit • Power-Saving Sleep mode Programmable Prescaler • Wake-Wp from Sleep on Pin Change • Selectable Oscillator Options: - INTRC: 4MHz precision Internal oscillator - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator - HS: High-speed crystal/resonator (PIC16F505 only) - LP: Power-saving, low-frequency crystal - EC: High-speed external clock input (PIC16F505 only) © 2009 Microchip Technology Inc. DS41236E-page 3

PIC12F508/509/16F505 Pin Diagrams PDIP, SOIC, TSSOP PDIP, SOIC, MSOP VDD 1 14 VSS VDD 1 09 8 VSS RB5/OSC1/CLKIN 2 13 RB0/ICSPDAT GP5/OSC1/CLKIN 2 08/5 7 GP0/ICSPDAT RB4/ROBS3C/R2MC/CC5LL/TKR0O/VCUPKTPI 345 C16F505 111201 RRRBCB120/ICSPCLK GP3/GMPC4L/RO/SVCP2P 34 PIC12F5 65 GGPP12//ITC0SCPKCILK PI RC4 6 9 RC1 RC3 7 8 RC2 DFN VDD 1 09 8 VSS 5 GP5/OSC1/CLKIN 2 08/ 7 GP0/ICSPDAT 5 GP4/OSC2 3 2F 6 GP1/ICSPCLK 1 GP3/MCLR/VPP 4 PIC 5 GP2/T0CKI PIC16F505 16-Pin Diagram (QFN) DD C C SS V N N V 6 5 4 3 1 1 1 1 RB5/OSC1/CLKIN 1 12 RB0/ICSPDAT RB4/OSC2/CLKOUT 2 11 RB1/ICSPCLK PIC16F505 RB3/MCLR/VPP 3 10 RB2 RC5/TOCKI 4 9 RC0 5 6 7 8 4 3 2 1 C C C C R R R R DS41236E-page 4 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 Program Memory Data Memory Timers Device I/O 8-bit Flash (words) SRAM (bytes) PIC12F508 512 25 6 1 PIC12F509 1024 41 6 1 PIC16F505 1024 72 12 1 © 2009 Microchip Technology Inc. DS41236E-page 5

PIC12F508/509/16F505 Table of Contents 1.0 General Description......................................................................................................................................................................7 2.0 PIC12F508/509/16F505 Device Varieties ...................................................................................................................................9 3.0 Architectural Overview...............................................................................................................................................................11 4.0 Memory Organization.................................................................................................................................................................17 5.0 I/O Port.......................................................................................................................................................................................31 6.0 Timer0 Module and TMR0 Register...........................................................................................................................................35 7.0 Special Features Of The CPU....................................................................................................................................................41 8.0 Instruction Set Summary............................................................................................................................................................57 9.0 Development Support.................................................................................................................................................................65 10.0 Electrical Characteristics............................................................................................................................................................69 11.0 DC and AC Characteristics Graphs and Charts.........................................................................................................................81 12.0 Packaging Information................................................................................................................................................................91 Index..................................................................................................................................................................................................105 The Microchip Web Site.....................................................................................................................................................................107 Customer Change Notification Service..............................................................................................................................................107 Customer Support..............................................................................................................................................................................107 Reader Response..............................................................................................................................................................................108 Product Identification System.............................................................................................................................................................109 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS41236E-page 6 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 1.0 GENERAL DESCRIPTION 1.1 Applications The PIC12F508/509/16F505 devices from Microchip The PIC12F508/509/16F505 devices fit in applications Technology are low-cost, high-performance, 8-bit, ranging from personal care appliances and security fully-static, Flash-based CMOS microcontrollers. They systems to low-power remote transmitters/receivers. employ a RISC architecture with only 33 single-word/ The Flash technology makes customizing application single-cycle instructions. All instructions are single programs (transmitter codes, appliance settings, cycle (200μs) except for program branches, which receiver frequencies, etc.) extremely fast and conve- take two cycles. The PIC12F508/509/16F505 devices nient. The small footprint packages, for through hole or deliver performance an order of magnitude higher than surface mounting, make these microcontrollers perfect their competitors in the same price category. The 12-bit for applications with space limitations. Low cost, low wide instructions are highly symmetrical, resulting in a power, high performance, ease-of-use and I/O flexibil- typical 2:1 code compression over other 8-bit ity make the PIC12F508/509/16F505 devices very ver- microcontrollers in its class. The easy to use and easy satile even in areas where no microcontroller use has to remember instruction set reduces development time been considered before (e.g., timer functions, logic and significantly. PLDs in larger systems and coprocessor applications). The PIC12F508/509/16F505 products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for exter- nal Reset circuitry. There are four oscillator configura- tions to choose from (six on the PIC16F505), including INTRC Internal Oscillator mode and the power-saving LP (Low-Power) Oscillator mode. Power-Saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC12F508/509/16F505 devices are available in the cost-effective Flash programmable version, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibility. The PIC12F508/509/16F505 products are supported by a full-featured macro assembler, a software simula- tor, an in-circuit emulator, a ‘C’ compiler, a low-cost development programmer and a full featured program- mer. All the tools are supported on IBM® PC and compatible machines. TABLE 1-1: PIC12F508/509/16F505 DEVICES PIC12F508 PIC12F509 PIC16F505 Clock Maximum Frequency of Operation (MHz) 4 4 20 Memory Flash Program Memory (words) 512 1024 1024 Data Memory (bytes) 25 41 72 Peripherals Timer Module(s) TMR0 TMR0 TMR0 Wake-up from Sleep on Pin Change Yes Yes Yes Features I/O Pins 5 5 11 Input Pins 1 1 1 Internal Pull-ups Yes Yes Yes In-Circuit Serial Programming Yes Yes Yes Number of Instructions 33 33 33 Packages 8-pin PDIP, SOIC, 8-pin PDIP, SOIC, 14-pin PDIP, SOIC, MSOP, DFN MSOP, DFN TSSOP The PIC12F508/509/16F505 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. The PIC12F508/509/16F505 devices use serial programming with data pin RB0/GP0 and clock pin RB1/GP1. © 2009 Microchip Technology Inc. DS41236E-page 7

PIC12F508/509/16F505 NOTES: DS41236E-page 8 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 2.0 PIC12F508/509/16F505 DEVICE 2.2 Serialized Quick Turn VARIETIES ProgrammingSM (SQTPSM) Devices A variety of packaging options are available. Depend- Microchip offers a unique programming service, where ing on application and production requirements, the a few user-defined locations in each device are proper device option can be selected using the programmed with different serial numbers. The serial information in this section. When placing orders, please numbers may be random, pseudo-random or use the PIC12F508/509/16F505 Product Identification sequential. System at the back of this data sheet to specify the Serial programming allows each device to have a correct part number. unique number, which can serve as an entry code, password or ID number. 2.1 Quick Turn Programming (QTP) Devices Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details. © 2009 Microchip Technology Inc. DS41236E-page 9

PIC12F508/509/16F505 NOTES: DS41236E-page 10 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 3.0 ARCHITECTURAL OVERVIEW The PIC12F508/509/16F505 devices contain an 8-bit ALU and working register. The ALU is a general The high performance of the PIC12F508/509/16F505 purpose arithmetic unit. It performs arithmetic and devices can be attributed to a number of architectural Boolean functions between data in the working register features commonly found in RISC microprocessors. and any register file. To begin with, the PIC12F508/509/16F505 devices The ALU is 8 bits wide and capable of addition, sub- use a Harvard architecture in which program and data traction, shift and logical operations. Unless otherwise are accessed on separate buses. This improves mentioned, arithmetic operations are two’s comple- bandwidth over traditional von Neumann architec- ment in nature. In two-operand instructions, one tures where program and data are fetched on the operand is typically the W (working) register. The other same bus. Separating program and data memory fur- operand is either a file register or an immediate ther allows instructions to be sized differently than the constant. In single operand instructions, the operand is 8-bit wide data word. Instruction opcodes are 12 bits either the W register or a file register. wide, making it possible to have all single-word instructions. A 12-bit wide program memory access The W register is an 8-bit working register used for ALU bus fetches a 12-bit instruction in a single cycle. A operations. It is not an addressable register. two-stage pipeline overlaps fetch and execution of Depending on the instruction executed, the ALU may instructions. Consequently, all instructions (33) affect the values of the Carry (C), Digit Carry (DC) and execute in a single cycle (200ns @ 20MHz, 1μs @ Zero (Z) bits in the STATUS register. The C and DC bits 4MHz) except for program branches. operate as a borrow and digit borrow out bit, respec- Table3-1 below lists program memory (Flash) and data tively, in subtraction. See the SUBWF and ADDWF memory (RAM) for the PIC12F508/509/16F505 instructions for examples. devices. Simplified block diagrams are shown in Figure3-1 and Figure3-2, with the corresponding pin described in TABLE 3-1: PIC12F508/509/16F505 Table3-2 and Table3-3. MEMORY Memory Device Program Data PIC12F508 512 x 12 25 x 8 PIC12F509 1024 x 12 41 x 8 PIC16F505 1024 x 12 72 x 8 The PIC12F508/509/16F505 devices can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC12F508/509/ 16F505 devices have a highly orthogonal (symmetri- cal) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. This symmetrical nature and lack of “special optimal situations” make programming with the PIC12F508/509/16F505 devices simple, yet efficient. In addition, the learning curve is reduced significantly. © 2009 Microchip Technology Inc. DS41236E-page 11

PIC12F508/509/16F505 FIGURE 3-1: PIC12F508/509 BLOCK DIAGRAM 12 Data Bus 8 GPIO Program Counter Flash GP0/ISCPDAT 512 x 12 or 1024 x 12 GP1/ISCPCLK RAM GP2/T0CKI PMreomgroarmy SSttaacckk 12 2451F x ilx e8 8 or GGPP43//OMSCCLR2/VPP GP5/OSC1/CLKIN Registers Program 12 Bus RAM Addr 9 Addr MUX Instruction Reg Direct Addr 5 Indirect 5-7 Addr FSR Reg Status Reg 8 3 MUX Device Reset Timer Instruction DeCcoodnetr oalnd Power-on ALU Reset 8 OSC1/CLKIN Timing Watchdog W Reg OSC2 Generation Timer Internal RC OSC Timer0 MCLR VDD, VSS DS41236E-page 12 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 TABLE 3-2: PIC12F508/509 PINOUT DESCRIPTION Input Output Name Function Description Type Type GP0/ICSPDAT GP0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin. GP1/ICSPCLK GP1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPCLK ST CMOS In-Circuit Serial Programming clock pin. GP2/T0CKI GP2 TTL CMOS Bidirectional I/O pin. T0CKI ST — Clock input to TMR0. GP3/MCLR/VPP GP3 TTL — Input pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. MCLR ST — Master Clear (Reset). When configured as MCLR, this pin is an active-low Reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation or the device will enter Programming mode. Weak pull-up always on if configured as MCLR. VPP HV — Programming voltage input. GP4/OSC2 GP4 TTL CMOS Bidirectional I/O pin. OSC2 — XTAL Oscillator crystal output. Connections to crystal or resonator in Crystal Oscillator mode (XT and LP modes only, GPIO in other modes). GP5/OSC1/CLKIN GP5 TTL CMOS Bidirectional I/O pin. OSC1 XTAL — Oscillator crystal input. CLKIN ST — External clock source input. VDD VDD — P Positive supply for logic and I/O pins. VSS VSS — P Ground reference for logic and I/O pins. Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input, ST = Schmitt Trigger input, HV = High Voltage © 2009 Microchip Technology Inc. DS41236E-page 13

PIC12F508/509/16F505 FIGURE 3-2: PIC16F505 BLOCK DIAGRAM 12 Data Bus 8 PORTB Program Counter Flash RB0/ICSPCLK 1K x 12 RB1/ICSPDAT RAM RB2 Program Memory Stack 1 72 bytes RB3/MCLR/VPP Stack 2 File RB4/OSC2/CLKOUT Registers RB5/OSC1/CLKIN Program 12 Bus RAM Addr 9 PORTC Addr MUX Instruction Reg RC0 Direct Addr 5 Indirect RC1 5-7 Addr RC2 RC3 FSR Reg RC4 RC5/T0CKI Status Reg 8 3 MUX Device Reset Timer Instruction Power-on ALU Decode and Reset Control 8 Watchdog Timer W Reg Timing OSC1/CLKIN Generation OSC2/CLKOUT Internal RC OSC Timer0 MCLR VDD, VSS DS41236E-page 14 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 TABLE 3-3: PIC16F505 PINOUT DESCRIPTION Input Output Name Function Description Type Type RB0/ICSPDAT RB0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin. RB1/ICSPCLK RB1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPCLK ST CMOS In-Circuit Serial Programming clock pin. RB2 RB2 TTL CMOS Bidirectional I/O pin. RB3/MCLR/VPP RB3 TTL — Input port. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. MCLR ST — Master Clear (Reset). When configured as MCLR, this pin is an active-low Reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation or the device will enter Programming mode. Weak pull-up always on if configured as MCLR. VPP HV — Programming voltage input. RB4/OSC2/CLKOUT RB4 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. OSC2 — XTAL Oscillator crystal output. Connections to crystal or resonator in Crystal Oscillator mode (XT, HS and LP modes only). CLKOUT — CMOS In EXTRC and INTRC modes, the pin output can be configured for CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RB5/OSC1/CLKIN RB5 TTL CMOS Bidirectional I/O pin. OSC1 XTAL — Crystal input. CLKIN ST — External clock source input. RC0 RC0 TTL CMOS Bidirectional I/O pin. RC1 RC1 TTL CMOS Bidirectional I/O pin. RC2 RC2 TTL CMOS Bidirectional I/O pin. RC3 RC3 TTL CMOS Bidirectional I/O pin. RC4 RC4 TTL CMOS Bidirectional I/O pin. RC5/T0CKI RC5 TTL CMOS Bidirectional I/O pin. T0CKI ST — Clock input to TMR0. VDD VDD — P Positive supply for logic and I/O pins. VSS VSS — P Ground reference for logic and I/O pins. Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input, ST = Schmitt Trigger input, HV = High Voltage © 2009 Microchip Technology Inc. DS41236E-page 15

PIC12F508/509/16F505 3.1 Clocking Scheme/Instruction 3.2 Instruction Flow/Pipelining Cycle An instruction cycle consists of four Q cycles (Q1, Q2, The clock input (OSC1/CLKIN pin) is internally divided Q3 and Q4). The instruction fetch and execute are by four to generate four non-overlapping quadrature pipelined such that fetch takes one instruction cycle, clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC while decode and execute take another instruction is incremented every Q1 and the instruction is fetched cycle. However, due to the pipelining, each instruction from program memory and latched into the instruction effectively executes in one cycle. If an instruction register in Q4. It is decoded and executed during the causes the PC to change (e.g., GOTO), then two cycles following Q1 through Q4. The clocks and instruction are required to complete the instruction (Example3-1). execution flow is shown in Figure3-3 and Example3-1. A fetch cycle begins with the PC incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC + 1 PC + 2 Fetch INST (PC) Execute INST (PC – 1) Fetch INST (PC + 1) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 03H Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTB, BIT1 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. DS41236E-page 16 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR THE The PIC12F508/509/16F505 memories are organized PIC12F508/509 into program memory and data memory. For devices with more than 512 bytes of program memory, a paging PC<11:0> scheme is used. Program memory pages are accessed CALL, RETLW 12 using one STATUS register bit. For the PIC12F509 and PIC16F505, with data memory register files of more Stack Level 1 than 32 registers, a banking scheme is used. Data Stack Level 2 memory banks are accessed using the File Select Register (FSR). Reset Vector(1) 0000h 4.1 Program Memory Organization for the PIC12F508/509 On-chip Program Memory The PIC12F508 device has a 10-bit Program Counter y (PC) and PIC12F509 has a 11-bit Program Counter or me (sPpCac) ec.apable of addressing a 2K x 12 program memory er MeSpac 512 Word 0012F00Fhh s Only the first 512 x 12 (0000h-01FFh) for the U PIC12F508, and 1K x 12 (0000h-03FFh) for the On-chip Program PIC12F509 are physically implemented (see Memory Figure4-1). Accessing a location above these boundaries will cause a wrap-around within the first 1024 Word 03FFh 512 x 12 space (PIC12F508) or 1K x 12 space 0400h (PIC12F509). The effective Reset vector is a 0000h (see Figure4-1). Location 01FFh (PIC12F508) and location 03FFh (PIC12F509) contain the internal clock oscillator calibration value. This value should never be overwritten. 7FFh Note 1: Address 0000h becomes the effective Reset vector. Location 01FFh, 03FFh (PIC12F508, PIC12F509) contains the MOVLW XX internal oscillator calibration value. © 2009 Microchip Technology Inc. DS41236E-page 17

PIC12F508/509/16F505 4.2 Program Memory Organization 4.3 Data Memory Organization For The PIC16F505 Data memory is composed of registers or bytes of The PIC16F505 device has a 11-bit Program Counter RAM. Therefore, data memory for a device is specified (PC) capable of addressing a 2K x 12 program memory by its register file. The register file is divided into two space. functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). The 1K x 12 (0000h-03FFh) for the PIC16F505 are physically implemented. Refer to Figure4-2. The Special Function Registers include the TMR0 Accessing a location above this boundary will cause a register, the Program Counter (PCL), the STATUS wrap-around within the first 1K x 12 space. The register, the I/O registers (ports) and the File Select effective Reset vector is at 0000h (see Figure4-2). Register (FSR). In addition, Special Function Registers Location 03FFh contains the internal oscillator are used to control the I/O port configuration and calibration value. This value should never be prescaler options. overwritten. The General Purpose Registers are used for data and control information under command of the instructions. FIGURE 4-2: PROGRAM MEMORY MAP For the PIC12F508/509, the register file is composed of AND STACK FOR THE 7 Special Function Registers, 9 General Purpose PIC16F505 Registers and 16 or 32 General Purpose Registers accessed by banking (see Figure4-3 and Figure4-4). PC<11:0> CALL, RETLW 12 For the PIC16F505, the register file is composed of 8 Special Function Registers, 8 General Purpose Stack Level 1 Registers and 64 General Purpose Registers accessed Stack Level 2 by banking (Figure4-5). 4.3.1 GENERAL PURPOSE REGISTER Reset Vector(1) 0000h FILE The General Purpose Register file is accessed, either directly or indirectly, through the File Select Register (FSR). See Section4.9 “Indirect Data Addressing: y INDF and FSR Registers”. or me ec Mpa 01FFh er S 0200h s U On-chip Program Memory 1024 Words 03FFh 0400h 7FFh Note 1: Address 0000h becomes the effective Reset vector. Location 03FFh contains the MOVLW XX internal oscillator calibration value. DS41236E-page 18 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 FIGURE 4-3: PIC12F508 REGISTER FIGURE 4-4: PIC12F509 REGISTER FILE MAP FILE MAP FSR<5> 0 1 File Address File Address 00h INDF(1) 00h INDF(1) 20h 01h TMR0 01h TMR0 02h PCL 02h PCL 03h STATUS 03h STATUS Addresses map 04h FSR back to 04h FSR addresses 05h OSCCAL 05h OSCCAL in Bank 0. 06h GPIO 06h GPIO 07h 07h General Purpose Registers General Purpose 0Fh 2Fh Registers 10h 30h General General Purpose Purpose Registers Registers 1Fh 1Fh 3Fh Bank 0 Bank 1 Note 1: Not a physical register. See Section4.9 Note 1: Not a physical register. See Section4.9 “Indirect Data Addressing: INDF and “Indirect Data Addressing: INDF and FSR FSR Registers”. Registers”. FIGURE 4-5: PIC16F505 REGISTER FILE MAP FSR<6:5> 00 01 10 11 File Address 00h INDF(1) 20h 40h 60h 01h TMR0 02h PCL 03h STATUS Addresses map back to addresses in Bank 0. 04h FSR 05h OSCCAL 06h PORTB 07h POR TC 08h General Purpose 0Fh Registers 2Fh 4Fh 6Fh 10h 30h 50h 70h General General General General Purpose Purpose Purpose Purpose Registers Registers Registers Registers 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: Not a physical register. See Section4.9 “Indirect Data Addressing: INDF and FSR Registers”. © 2009 Microchip Technology Inc. DS41236E-page 19

PIC12F508/509/16F505 4.3.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC12F508/509) Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On Page # Reset(2) 00h INDF Uses Contents of FSR to Address Data Memory (not a physical xxxx xxxx 28 register) 01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 35 02h(1) PCL Low-order 8 bits of PC 1111 1111 27 03h STATUS GPWUF — PA0(5) TO PD Z DC C 0-01 1xxx(3) 22 04h FSR Indirect Data Memory Address Pointer 111x xxxx 28 04h(4) FSR Indirect Data Memory Address Pointer 110x xxxx 28 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 26 06h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 31 N/A TRISGPIO — — I/O Control Register --11 1111 31 N/A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 24 Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition. Note 1: The upper byte of the Program Counter is not directly accessible. See Section4.7 “Program Counter” for an explanation of how to access these bits. 2: Other (non Power-up) Resets include external Reset through MCLR, Watchdog Timer and wake-up on pin change Reset. 3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. 4: PIC12F509 only. 5: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508. DS41236E-page 20 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 TABLE 4-2: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC16F505) Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On Page # Reset(2) 00h INDF Uses Contents of FSR to Address Data Memory (not a physical xxxx xxxx 28 register) 01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 35 02h(1) PCL Low-order 8 bits of PC 1111 1111 27 03h STATUS RBWUF — PA0 TO PD Z DC C 0-01 1xxx 22 04h FSR Indirect Data Memory Address Pointer 100x xxxx 28 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 26 06h PORTB — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx 31 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx 31 N/A TRISB — — I/O Control Register --11 1111 31 N/A TRISC — — I/O Control Register --11 1111 31 N/A OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 25 Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition. Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. 2: Other (non Power-up) Resets include external reset through MCLR, Watchdog Timer and wake-up on pin change Reset. © 2009 Microchip Technology Inc. DS41236E-page 21

PIC12F508/509/16F505 4.4 STATUS Register For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register This register contains the arithmetic status of the ALU, as 000u u1uu (where u = unchanged). the Reset status and the page preselect bit. Therefore, it is recommended that only BCF, BSF and The STATUS register can be the destination for any MOVWF instructions be used to alter the STATUS regis- instruction, as with any other register. If the STATUS ter. These instructions do not affect the Z, DC or C bits register is the destination for an instruction that affects from the STATUS register. For other instructions which the Z, DC or C bits, then the write to these three bits is do affect Status bits, see Section8.0 “Instruction Set disabled. These bits are set or cleared according to the Summary”. device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 4-1: STATUS REGISTER (ADDRESS: 03h) (PIC12F508/509) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x GPWUF — PA0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPWUF: GPIO Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 Reserved: Do not use bit 5 PA0: Program Page Preselect bits(1) 1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh) Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended, since this may affect upward compatibility with future products. bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred Note 1: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508. DS41236E-page 22 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 REGISTER 4-2: STATUS REGISTER (ADDRESS: 03h) (PIC16F505) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x RBWUF — PA0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBWUF: PORTB Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 Reserved: Do not use bit 5 PA0: Program Page Preselect bits 1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh) Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended, since this may affect upward compatibility with future products. bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred © 2009 Microchip Technology Inc. DS41236E-page 23

PIC12F508/509/16F505 4.5 OPTION Register The OPTION register is a 8-bit wide, write-only register, Note: If TRIS bit is set to ‘0’, the wake-up on which contains various control bits to configure the change and pull-up functions are disabled Timer0/WDT prescaler and Timer0. for that pin (i.e., note that TRIS overrides By executing the OPTION instruction, the contents of Option control of GPPU/RBPU and the W register will be transferred to the OPTION regis- GPWU/RBWU). ter. A Reset sets the OPTION<7:0> bits. Note: If the T0CS bit is set to ‘1’, it will override the TRIS function on the T0CKI pin. REGISTER 4-3: OPTION REGISTER (PIC12F508/509) W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPWU: Enable Wake-up on Pin Change bit (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 6 GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin) 0 = Transition on internal instruction cycle clock, FOSC/4 bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on the T0CKI pin 0 = Increment on low-to-high transition on the T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 RateWDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 DS41236E-page 24 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 REGISTER 4-4: OPTION REGISTER (PIC16F505) W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBWU: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 6 RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 5 T0CS: Timer0 clock Source Select bit 1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin) 0 = Transition on internal instruction cycle clock, FOSC/4 bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on the T0CKI pin 0 = Increment on low-to-high transition on the T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 RateWDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 © 2009 Microchip Technology Inc. DS41236E-page 25

PIC12F508/509/16F505 4.6 OSCCAL Register After you move in the calibration constant, do not change the value. See Section7.2.5 “Internal 4MHz The Oscillator Calibration (OSCCAL) register is used to RC Oscillator”. calibrate the internal precision 4MHz oscillator. It contains seven bits for calibration. Note: Erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. REGISTER 4-5: OSCCAL REGISTER (ADDRESS: 05h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 CAL<6:0>: Oscillator Calibration bits 0111111 =Maximum frequency • • • 0000001 0000000 =Center frequency 1111111 • • • 1000000 =Minimum frequency bit 0 Unimplemented: Read as ‘0’ DS41236E-page 26 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 4.7 Program Counter 4.7.1 EFFECTS OF RESET As a program instruction is executed, the Program The PC is set upon a Reset, which means that the PC Counter (PC) will contain the address of the next addresses the last location in the last page (i.e., the program instruction to be executed. The PC value is oscillator calibration instruction). After executing increased by one every instruction cycle, unless an MOVLW XX, the PC will roll over to location 00h and instruction changes the PC. begin executing user code. For a GOTO instruction, bits 8:0 of the PC are provided The STATUS register page preselect bits are cleared by the GOTO instruction word. The Program Counter upon a Reset, which means that page0 is pre-selected. (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS Therefore, upon a Reset, a GOTO instruction will register provides page information to bit 9 of the PC automatically cause the program to jump to page0 until (Figure4-6). the value of the page bits is altered. For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are 4.8 Stack provided by the instruction word. However, PC<8> The PIC12F508/509/16F505 devices have a 2-deep, does not come from the instruction word, but is always 12-bit wide hardware PUSH/POP stack. cleared (Figure4-6). A CALL instruction will PUSH the current value of Stack Instructions where the PCL is the destination, or modify 1 into Stack 2 and then PUSH the current PC value, PCL instructions, include MOVWF PC, ADDWF PC and incremented by one, into Stack Level 1. If more than two BSF PC,5. sequential CALLs are executed, only the most recent two Note: Because PC<8> is cleared in the CALL return addresses are stored. instruction or any modify PCL instruction, A RETLW instruction will POP the contents of Stack all subroutine calls or computed jumps are Level 1 into the PC and then copy Stack Level 2 limited to the first 256 locations of any contents into Stack Level 1. If more than two sequential program memory page (512 words long). RETLWs are executed, the stack will be filled with the address previously stored in Stack Level 2. Note that FIGURE 4-6: LOADING OF PC the Wregister will be loaded with the literal value BRANCH INSTRUCTIONS specified in the instruction. This is particularly useful for the implementation of data look-up tables within the GOTO Instruction program memory. 11 10 9 8 7 0 Note1: There are no Status bits to indicate stack PC PCL overflows or stack underflow conditions. 2: There are no instruction mnemonics Instruction Word called PUSH or POP. These are actions PA0 that occur from the execution of the CALL 7 0 and RETLW instructions. Status CALL or Modify PCL Instruction 11 10 9 8 7 0 PC PCL Instruction Word Reset to ‘0’ PA0 7 0 Status © 2009 Microchip Technology Inc. DS41236E-page 27

PIC12F508/509/16F505 4.9 Indirect Data Addressing: INDF EXAMPLE 4-1: HOW TO CLEAR RAM and FSR Registers USING INDIRECT ADDRESSING The INDF register is not a physical register. Addressing INDF actually addresses the register MOVLW 0x10 ;initialize pointer MOVWF FSR ;to RAM whose address is contained in the FSR register (FSR NEXT CLRF INDF ;clear INDF is a pointer). This is indirect addressing. ;register INCF FSR,F ;inc pointer 4.9.1 INDIRECT ADDRESSING BTFSC FSR,4 ;all done? • Register file 07 contains the value 10h GOTO NEXT ;NO, clear next CONTINUE • Register file 08 contains the value 0Ah : ;YES, continue • Load the value 07 into the FSR register : • A read of the INDF register will return the value of10h The FSR is a 5-bit wide register. It is used in conjunction • Increment the value of the FSR register by one with the INDF register to indirectly address the data (FSR = 08) memory area. • A read of the INDR register now will return the value of 0Ah. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a PIC12F508 – Does not use banking. FSR <7:5> are no operation (although Status bits may be affected). unimplemented and read as ‘1’s. A simple program to clear RAM locations 10h-1Fh PIC12F509 – Uses FSR<5>. Selects between bank 0 using indirect addressing is shown in Example4-1. and bank 1. FSR<7:6> are unimplemented, read as ‘1’. PIC16F505 – Uses FSR<6:5>. Selects from bank 0 to bank 3. FSR<7> is unimplemented, read as ‘1’. FIGURE 4-7: DIRECT/INDIRECT ADDRESSING (PIC12F508/509) Direct Addressing Indirect Addressing (FSR) 6 5 4 (opcode) 0 6 5 4 (FSR) 0 Bank Select Location Select Bank Location Select 00 01 00h Addresses map back to addresses in Bank 0. Data 0Fh Memory(1) 10h 1Fh 3Fh Bank 0 Bank 1(2) Note 1: For register map detail, see Section4.3 “Data Memory Organization”. 2: PIC12F509. DS41236E-page 28 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 FIGURE 4-8: DIRECT/INDIRECT ADDRESSING (PIC16F505) Direct Addressing Indirect Addressing (FSR) 6 5 4 (opcode) 0 6 5 4 (FSR) 0 Bank Select Location Select Bank Location Select 00 01 10 11 00h Addresses map back to addresses in Bank 0. Data 0Fh Memory(1) 10h 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register map detail, see Section4.3 “Data Memory Organization”. © 2009 Microchip Technology Inc. DS41236E-page 29

PIC12F508/509/16F505 NOTES: DS41236E-page 30 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 5.0 I/O PORT 5.4 I/O Interfacing As with any other register, the I/O register(s) can be The equivalent circuit for an I/O port pin is shown in written and read under program control. However, read Figure5-2. All port pins, except RB3/GP3 which is instructions (e.g., MOVF PORTB,W) always read the I/O input only, may be used for both input and output oper- pins independent of the pin’s Input/Output modes. On ations. For input operations, these ports are non-latch- Reset, all I/O ports are defined as input (inputs are at ing. Any input must be present until read by an input high-impedance) since the I/O control registers are all instruction (e.g., MOVF PORTB, W). The outputs are set. latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the correspond- Note: On the PIC12F508/509, I/O PORTB is ref- ing direction control bit in TRIS must be cleared (= 0). erenced as GPIO. On the PIC16F505, I/O For use as an input, the corresponding TRIS bit must PORTB is referenced as PORTB. be set. Any I/O pin (except RB3/GP3) can be programmed individually as input or output. 5.1 PORTB/GPIO FIGURE 5-1: PIC12F508/509/16F505 PORTB/GPIO is an 8-bit I/O register. Only the low- EQUIVALENT CIRCUIT order 6 bits are used (RB/GP<5:0>). Bits 7 and 6 are unimplemented and read as ‘0’s. Please note that RB3/ FOR A SINGLE I/O PIN GP3 is an input only pin. The Configuration Word can Data set several I/O’s to alternate functions. When acting as Bus D Q alternate functions, the pins will read as ‘0’ during a port Data read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4 WR Latch VDD VDD can be configured with weak pull-ups and also for Port CK Q wake-up on change. The wake-up on change and weak P pull-up functions are not pin selectable. If RB3/GP3/ MCLR is configured as MCLR, weak pull-up is always on and wake-up on change for this pin is not enabled. W N I/O Reg pin D Q 5.2 PORTC (PIC16F505 Only) TRIS VSS VSS Latch PORTC is an 8-bit I/O register. Only the low-order 6 bits TRIS ‘f’ CK Q are used (RC<5:0>). Bits 7 and 6 are unimplemented and read as ‘0’s. Note: On power-up, TOCKI functionality is Reset (1) enabled in the OPTION register and must be disabled to allow RC5 to be used as general purpose I/O. RD Port 5.3 TRIS Registers Note 1: See Table3-3 for buffer type. The Output Driver Control register is loaded with the contents of the W register by executing the TRIS f instruction. A ‘1’ from a TRIS register bit puts the corre- sponding output driver in a High-Impedance mode. A ‘0’ puts the contents of the output data latch on the selected pins, enabling the output buffer. The excep- tions are RB3/GP3, which is input only and the T0CKI pin, which may be controlled by the OPTION register. See Register4-3 and Register4-4. Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. The TRIS registers are “write-only” and are set (output drivers disabled) upon Reset. © 2009 Microchip Technology Inc. DS41236E-page 31

PIC12F508/509/16F505 TABLE 5-1: SUMMARY OF PORT REGISTERS Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets N/A TRISGPIO(1) — — I/O Control Register --11 1111 --11 1111 N/A TRISB(2) — — I/O Control Register --11 1111 --11 1111 N/A TRISC(2) — — I/O Control Register --11 1111 --11 1111 N/A OPTION(1) GPWU GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A OPTION(2) RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 03h STATUS(1) GPWUF — PAO TO PD Z DC C 0-01 1xxx q00q quuu(3) 03h STATUS(2) RBWUF — PAO TO PD Z DC C 0-01 1xxx q00q quuu(3) 06h GPIO(1) — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu 06h PORTB(2) — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu 07h PORTC(2) — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu Legend: Shaded cells are not used by Port registers, read as ‘0’. – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = depends on condition. Note 1: PIC12F508/509 only. 2: PIC16F505 only. 3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. DS41236E-page 32 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 5.5 I/O Programming Considerations EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN 5.5.1 BIDIRECTIONAL I/O PORTS I/O PORT(e.g., PIC16F505) Some instructions operate internally as read followed ;Initial PORTB Settings by write operations. The BCF and BSF instructions, for ;PORTB<5:3> Inputs example, read the entire port into the CPU, execute the ;PORTB<2:0> Outputs bit operation and re-write the result. Caution must be ; used when these instructions are applied to a port ; PORTB latch PORTB pins ; ---------- ---------- where one or more pins are used as input/outputs. For BCF PORTB, 5 ;--01 -ppp --11 pppp example, a BSF operation on bit 5 of PORTB/GPIO will BCF PORTB, 4 ;--10 -ppp --11 pppp cause all eight bits of PORTB/GPIO to be read into the MOVLW 007h; CPU, bit 5 to be set and the PORTB/GPIO value to be TRIS PORTB ;--10 -ppp --11 pppp written to the output latches. If another bit of PORTB/ ; GPIO is used as a bidirectional I/O pin (say bit 0) and it Note 1: The user may have expected the pin values to is defined as an input at this time, the input signal pres- be ‘--00 pppp’. The 2nd BCF caused RB5 to ent on the pin itself would be read into the CPU and be latched as the pin value (High). rewritten to the data latch of this particular pin, overwrit- ing the previous content. As long as the pin stays in the 5.5.2 SUCCESSIVE OPERATIONS ON Input mode, no problem occurs. However, if bit 0 is I/O PORTS switched into Output mode later on, the content of the data latch may now be unknown. The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be Example5-1 shows the effect of two sequential valid at the beginning of the instruction cycle (Figure5-2). Read-Modify-Write instructions (e.g., BCF, BSF, etc.) Therefore, care must be exercised if a write followed by on an I/O port. a read operation is carried out on the same I/O port. The A pin actively outputting a high or a low should not be sequence of instructions should allow the pin voltage to driven from external devices at the same time in order stabilize (load dependent) before the next instruction to change the level on this pin (“wired OR”, “wired causes that file to be read into the CPU. Otherwise, the AND”). The resulting high output currents may damage previous state of that pin may be read into the CPU rather the chip. than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-2: SUCCESSIVE I/O OPERATION (PIC16F505 Shown) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB Instruction followed by a read from PORTB. Fetched MOVWF PORTB MOVF PORTB, W NOP NOP Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle RB<5:0> TPD = propagation delay Port pin Port pin Therefore, at higher clock frequencies, a written here sampled here write followed by a read may be problematic. Instruction Executed MOVWF PORTB MOVF PORTB,W NOP (Write to PORTB) (Read PORTB) © 2009 Microchip Technology Inc. DS41236E-page 33

PIC12F508/509/16F505 NOTES: DS41236E-page 34 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 6.0 TIMER0 MODULE AND TMR0 Counter mode is selected by setting the T0CS bit REGISTER (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The The Timer0 module has the following features: T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restric- • 8-bit timer/counter register, TMR0 tions on the external clock input are discussed in detail • Readable and writable in Section6.1 “Using Timer0 with an External • 8-bit software programmable prescaler Clock”. • Internal or external clock select: The prescaler may be used by either the Timer0 - Edge select for external clock module or the Watchdog Timer, but not both. The Figure6-1 is a simplified block diagram of the Timer0 prescaler assignment is controlled in software by the module. control bit, PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not Timer mode is selected by clearing the T0CS bit readable or writable. When the prescaler is assigned to (OPTION<5>). In Timer mode, the Timer0 module will the Timer0 module, prescale values of 1:2, 1:4,..., increment every instruction cycle (without prescaler). If 1:256 are selectable. Section6.2 “Prescaler” details TMR0 register is written, the increment is inhibited for the operation of the prescaler. the following two cycles (Figure6-2 and Figure6-3). The user can work around this by writing an adjusted A summary of registers associated with the Timer0 value to the TMR0 register. module is found in Table6-1. FIGURE 6-1: TIMER0 BLOCK DIAGRAM Data Bus (GP2/RC5)/T0CKI FOSC/4 0 Pin PSOUT 8 1 Sync with 1 Internal TMR0 Reg Clocks PrPorgersacmalmera(2b)le 0 PSOUT T0SE (2 TCY delay) Sync 3 PS2, PS1, PS0(1) PSA(1) T0CS(1) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure6-5). FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 (Program Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 © 2009 Microchip Technology Inc. DS41236E-page 35

PIC12F508/509/16F505 FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2Q3 Q4 (Program Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 NT0 NT0 + 1 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets 01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter xxxx xxxx uuuu uuuu N/A OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A TRISGPIO(1), (3) — — I/O Control Register --11 1111 --11 1111 N/A TRISC(2), (3) — — RC5 RC4 RC3 RC2 RC1 RC0 --11 1111 --11 1111 Legend: Shaded cells are not used by Timer0. – = unimplemented, x = unknown, u = unchanged. Note 1: PIC12F508/509 only. 2: PIC16F505 only. 3: The TRIS of the T0CKI pin is overridden when T0CS = 1. DS41236E-page 36 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 6.1 Using Timer0 with an External When a prescaler is used, the external clock input is Clock divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. When an external clock input is used for Timer0, it must For the external clock to meet the sampling require- meet certain requirements. The external clock require- ment, the ripple counter must be taken into account. ment is due to internal phase clock (TOSC) synchroni- Therefore, it is necessary for T0CKI to have a period of zation. Also, there is a delay in the actual incrementing at least 4 TOSC (and a small RC delay of 4 Tt0H) of Timer0 after synchronization. divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate 6.1.1 EXTERNAL CLOCK the minimum pulse width requirement of Tt0H. Refer to SYNCHRONIZATION parameters 40, 41 and 42 in the electrical specification When no prescaler is used, the external clock input is of the desired device. the same as the prescaler output. The synchronization 6.1.2 TIMER0 INCREMENT DELAY of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and Since the prescaler output is synchronized with the Q4 cycles of the internal phase clocks (Figure6-4). internal clocks, there is a small delay from the time the Therefore, it is necessary for T0CKI to be high for at external clock edge occurs to the time the Timer0 least 2 TOSC (and a small RC delay of 2 Tt0H) and low module is actually incremented. Figure6-4 shows the for at least 2 TOSC (and a small RC delay of 2 Tt0H). delay from the external clock edge to the timer Refer to the electrical specification of the desired incrementing. device. FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Small pulse Prescaler Output (2) misses sampling (1) External Clock/Prescaler (3) Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = ±4 TOSC max. 2: External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. © 2009 Microchip Technology Inc. DS41236E-page 37

PIC12F508/509/16F505 6.2 Prescaler EXAMPLE 6-1: CHANGING PRESCALER (TIMER0 → WDT) An 8-bit counter is available as a prescaler for the CLRWDT ;Clear WDT Timer0 module or as a postscaler for the Watchdog CLRF TMR0 ;Clear TMR0 & Prescaler Timer (WDT), respectively (see Section7.6 “Watch- MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7) dog Timer (WDT)”). For simplicity, this counter is OPTION ;are required only if being referred to as “prescaler” throughout this data ;desired sheet. CLRWDT ;PS<2:0> are 000 or 001 MOVLW ‘00xx1xxx’b;Set Postscaler to Note: The prescaler may be used by either the OPTION ;desired WDT rate Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the To change the prescaler from the WDT to the Timer0 Timer0 module means that there is no module, use the sequence shown in Example6-2. This prescaler for the WDT and vice versa. sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before The PSA and PS<2:0> bits (OPTION<3:0>) determine switching the prescaler. prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions EXAMPLE 6-2: CHANGING PRESCALER writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, (WDT → TIMER0) BSF 1, x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler CLRWDT ;Clear WDT and along with the WDT. The prescaler is neither readable ;prescaler MOVLW ‘xxxx0xxx’ ;Select TMR0, new nor writable. On a Reset, the prescaler contains all ‘0’s. ;prescale value and ;clock source 6.2.1 SWITCHING PRESCALER OPTION ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). To avoid an unintended device Reset, the following instruction sequence (Example6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. DS41236E-page 38 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER(1), (2) TCY (= FOSC/4) Data Bus 0 8 (GP2/RC5)/T0CKI M 1 pin U M 1 X Sync U 2 TMR0 Reg 0 X Cycles T0SE T0CS PSA 0 8-bit Prescaler M U 1 X Watchdog 8 Timer 8-to-1 MUX PS<2:0> PSA 0 1 WDT Enable bit MUX PSA WDT Time-out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. 2: T0CKI is shared with pin RC5 on the PIC16F505 and pin GP2 on the PIC12F508/509. © 2009 Microchip Technology Inc. DS41236E-page 39

PIC12F508/509/16F505 NOTES: DS41236E-page 40 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 7.0 SPECIAL FEATURES OF THE The PIC12F508/509/16F505 devices have a Watchdog CPU Timer, which can be shut off only through Configuration bit WDTE. It runs off of its own RC oscillator for added What sets a microcontroller apart from other reliability. If using HS (PIC16F505), XT or LP selectable processors are special circuits that deal with the needs oscillator options, there is always an 18ms (nominal) of real-time applications. The PIC12F508/509/16F505 delay provided by the Device Reset Timer (DRT), microcontrollers have a host of such features intended intended to keep the chip in Reset until the crystal to maximize system reliability, minimize cost through oscillator is stable. If using INTRC or EXTRC, there is elimination of external components, provide power- an 18ms delay only on VDD power-up. With this timer saving operating modes and offer code protection. on-chip, most applications need no external Reset These features are: circuitry. • Oscillator Selection The Sleep mode is designed to offer a very low-current • Reset: Power-Down mode. The user can wake-up from Sleep through a change on input pins or through a Watchdog - Power-on Reset (POR) Timer time-out. Several oscillator options are also - Device Reset Timer (DRT) made available to allow the part to fit the application, - Wake-up from Sleep on Pin Change including an internal 4MHz oscillator. The EXTRC • Watchdog Timer (WDT) oscillator option saves system cost while the LP crystal • Sleep option saves power. A set of Configuration bits are used to select various options. • Code Protection • ID Locations 7.1 Configuration Bits • In-Circuit Serial Programming™ • Clock Out The PIC12F508/509/16F505 Configuration Words consist of 12 bits. Configuration bits can be programmed to select various device configurations. Three bits are for the selection of the oscillator type; (two bits on the PIC12F508/509), one bit is the Watchdog Timer enable bit, one bit is the MCLR enable bit and one bit is for code protection (Register7-1, Register7-2). © 2009 Microchip Technology Inc. DS41236E-page 41

PIC12F508/509/16F505 REGISTER 7-1: CONFIGURATION WORD FOR PIC12F508/509(1) — — — — — — — MCLRE CP WDTE FOSC1 FOSC0 bit 11 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 11-5 Unimplemented: Read as ‘0’ bit 4 MCLRE: GP3/MCLR Pin Function Select bit 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital input, MCLR internally tied to VDD bit 3 CP: Code Protection bit 1 = Code protection off 0 = Code protection on bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC<1:0>: Oscillator Selection bits 11 = EXTRC = external RC oscillator 10 = INTRC = internal RC oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Refer to the “PIC12F508/509 Memory Programming Specifications” (DS41227) to determine how to access the Configuration Word. The Configuration Word is not user addressable during device operation. DS41236E-page 42 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 REGISTER 7-2: CONFIGURATION WORD FOR PIC16F505(1) — — — — — — MCLRE CP WDTE FOSC2 FOSC1 FOSC0 bit 11 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 11-6 Unimplemented: Read as ‘0’ bit 5 MCLRE: RB3/MCLR Pin Function Select bit 1 = RB3/MCLR pin function is MCLR 0 = RB3/MCLR pin function is digital input, MCLR internally tied to VDD bit 4 CP: Code Protection bit 1 = Code protection off 0 = Code protection on bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 FOSC<1:0>: Oscillator Selection bits 111 = External RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 110 = External RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 101 = Internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 100 = Internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 011 = EC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Note 1: Refer to the “PIC16F505 Memory Programming Specifications” (DS41226) to determine how to access the Configuration Word. The Configuration Word is not user addressable during device operation. © 2009 Microchip Technology Inc. DS41236E-page 43

PIC12F508/509/16F505 7.2 Oscillator Configurations FIGURE 7-1: CRYSTAL OPERATION (OR CERAMIC 7.2.1 OSCILLATOR TYPES RESONATOR) The PIC12F508/509/16F505 devices can be operated (HS, XT OR LP OSC in up to six different oscillator modes. The user can CONFIGURATION) program up to three Configuration bits (FOSC<1:0> [PIC12F508/509], FOSC<2:0> [PIC16F505]). To select C1(1) OSC1 PIC12F508/509 PIC16F505 one of these modes: Sleep • LP: Low-Power Crystal XTAL RF(3) • XT: Crystal/Resonator To internal logic • HS: High-Speed Crystal/Resonator OSC2 RS(2) (PIC16F505 only) C2(1) • INTRC: Internal 4MHz Oscillator • EXTRC: External Resistor/Capacitor Note 1: See Capacitor Selection tables for recommended values of C1 and C2. • EC: External High-Speed Clock Input 2: A series resistor (RS) may be required for AT (PIC16F505 only) strip cut crystals. 3: RF approx. value = 10MΩ. 7.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS In HS (PIC16F505), XT or LP modes, a crystal or FIGURE 7-2: EXTERNAL CLOCK INPUT ceramic resonator is connected to the (GP5/RB5)/ OPERATION (HS, XT OR OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins LP OSC to establish oscillation (Figure7-1). The PIC12F508/ CONFIGURATION) 509/16F505 oscillator designs require the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers Clock from OSC1 specifications. When in HS (PIC16F505), XT or LP ext. system PIC12F508/509 modes, the device can have an external clock source PIC16F505 drive the (GP5/RB5)/OSC1/CLKIN pin (Figure7-2). Open OSC2 When the part is used in this fashion, the output drive levels on the OSC2 pin are very weak. This pin should be left open and unloaded. Also, when using this mode, the external clock should observe the frequency limits TABLE 7-1: CAPACITOR SELECTION FOR for the clock mode chosen (HS, XT or LP). CERAMIC RESONATORS – PIC12F508/509/16F505(1) Note1: This device has been designed to per- form to the parameters of its data sheet. Osc Resonator Cap. Range Cap. Range It has been tested to an electrical Type Freq. C1 C2 specification designed to determine its XT 4.0 MHz 30 pF 30 pF conformance with these parameters. HS(2) 16 MHz 10-47 pF 10-47 pF Due to process differences in the manufacture of this device, this device Note 1: These values are for design guidance may have different performance charac- only. Since each resonator has its own teristics than its earlier version. These characteristics, the user should consult differences may cause this device to the resonator manufacturer for perform differently in your application appropriate values of external than the earlier version of this device. components. 2: The user should verify that the device 2: PIC16F505 only. oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the Oscillator mode may be required. DS41236E-page 44 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 TABLE 7-2: CAPACITOR SELECTION FOR FIGURE 7-3: EXTERNAL PARALLEL CRYSTAL OSCILLATOR – RESONANT CRYSTAL PIC12F508/509/16F505(2) OSCILLATOR CIRCUIT Osc Resonator Cap. Range Cap. Range +5V To Other Type Freq. C1 C2 Devices 10k LP 32kHz(1) 15pF 15pF 4.7k 74AS04 XT 200 kHz 47-68 pF 47-68 pF 74AS04 CLKIN 1 MHz 15 pF 15 pF PIC16F505 4 MHz 15 pF 15 pF PIC12F508 HS(3) 20 MHz 15-47 pF 15-47 pF 10k PIC12F509 Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is XTAL recommended. 10k 2: These values are for design guidance only. Rs may be required to avoid over- 20 pF 20 pF driving crystals with low drive level specifi- cation. Since each crystal has its own Figure7-4 shows a series resonant oscillator circuit. characteristics, the user should consult This circuit is also designed to use the fundamental the crystal manufacturer for appropriate frequency of the crystal. The inverter performs a 180- values of external components. degree phase shift in a series resonant oscillator 3: PIC16F505 only. circuit. The 330Ω resistors provide the negative feedback to bias the inverters in their linear region. 7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT FIGURE 7-4: EXTERNAL SERIES Either a prepackaged oscillator or a simple oscillator RESONANT CRYSTAL circuit with TTL gates can be used as an external OSCILLATOR CIRCUIT crystal oscillator circuit. Prepackaged oscillators To Other provide a wide operating range and better stability. A 330 330 Devices well-designed crystal oscillator will provide good perfor- mance with TTL gates. Two types of crystal oscillator 74AS04 74AS04 74AS04 circuits can be used: one with parallel resonance, or CLKIN one with series resonance. 0.1 mF PIC16F505 PIC12F508 Figure7-3 shows implementation of a parallel resonant XTAL PIC12F509 oscillator circuit. The circuit is designed to use the fun- damental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel 7.2.4 EXTERNAL RC OSCILLATOR oscillator requires. The 4.7kΩ resistor provides the negative feedback for stability. The 10kΩ potentiome- For timing insensitive applications, the RC device ters bias the 74AS04 in the linear region. This circuit option offers additional cost savings. The RC oscillator could be used for external oscillator designs. frequency is a function of the supply voltage, the resis- tor (REXT) and capacitor (CEXT) values, and the operat- ing temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal pro- cess parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure7-5 shows how the R/C combination is connected to the PIC12F508/509/16F505 devices. For REXT values below 3.0kΩ, the oscillator operation may become unstable, or stop completely. For very high REXT values (e.g.,1MΩ), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping REXT between 5.0kΩ and 100kΩ. © 2009 Microchip Technology Inc. DS41236E-page 45

PIC12F508/509/16F505 Although the oscillator will operate with no external In addition, a calibration instruction is programmed into capacitor (CEXT = 0pF), we recommend using values the last address of memory, which contains the above 20pF for noise and stability reasons. With no or calibration value for the internal RC oscillator. This small external capacitance, the oscillation frequency location is always uncode protected, regardless of the can vary dramatically due to changes in external code-protect settings. This value is programmed as a capacitances, such as PCB trace capacitance or MOVLW XX instruction where XX is the calibration value, package lead frame capacitance. and is placed at the Reset vector. This will load the W register with the calibration value upon Reset and the Section10.0 “Electrical Characteristics” shows RC PC will then roll over to the users program at address frequency variation from part-to-part due to normal 0x000. The user then has the option of writing the value process variation. The variation is larger for larger val- to the OSCCAL Register (05h) or ignoring it. ues of R (since leakage current variation will affect RC frequency more for large R) and for smaller values of C OSCCAL, when written to with the calibration value, will (since variation of input capacitance will affect RC “trim” the internal oscillator to remove process variation frequency more). from the oscillator frequency. Also, see the Electrical Specifications section for Note: Erasing the device will also erase the pre- variation of oscillator frequency due to VDD for given programmed internal calibration value for REXT/CEXT values, as well as frequency variation due the internal oscillator. The calibration to operating temperature for given R, C and VDD value must be read prior to erasing the values. part so it can be reprogrammed correctly later. FIGURE 7-5: EXTERNAL RC For the PIC12F508/509/16F505 devices, only bits OSCILLATOR MODE <7:1> of OSCCAL are implemented. Bits CAL6-CAL0 are used for calibration. Adjusting CAL6-CAL0 from VDD ‘0000000’ to ‘1111111’ changes the clock speed. See Register4-5 for more information. REXT Internal OSC1 clock Note: The 0 bit of OSCCAL is unimplemented and should be written as ‘0’ when N modifying OSCCAL for compatibility with CEXT PIC16F505 future devices. PIC12F508 VSS PIC12F509 FOSC/4 OSC2/CLKOUT 7.2.5 INTERNAL 4MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4MHz (nominal) system clock at VDD = 5V and 25°C, (see Section10.0 “Electrical Characteristics” for information on variation over voltage and temperature). DS41236E-page 46 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 7.3 Reset Some registers are not reset in any way, they are unknown on POR and unchanged in any other Reset. The device differentiates between various kinds of Most other registers are reset to “Reset state” on Reset: Power-on Reset (POR), MCLR, WDT or Wake-up on • Power-on Reset (POR) pin change Reset during normal operation. They are • MCLR Reset during normal operation not affected by a WDT Reset during Sleep or MCLR Reset during Sleep, since these Resets are viewed as • MCLR Reset during Sleep resumption of normal operation. The exceptions to this • WDT time-out Reset during normal operation are TO, PD and RBWUF/GPWUF bits. They are set or • WDT time-out Reset during Sleep cleared differently in different Reset situations. These • Wake-up from Sleep on pin change bits are used in software to determine the nature of Reset. See Table7-4 for a full description of Reset states of all registers. TABLE 7-3: RESET CONDITIONS FOR REGISTERS – PIC12F508/509 MCLR Reset, WDT Time-out, Register Address Power-on Reset Wake-up On Pin Change W — qqqq qqqu(1) qqqq qqqu(1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx q00q quuu(2), (3) FSR(4) 04h 110x xxxx 11uu uuuu FSR(5) 04h 111x xxxx 111u uuuu OSCCAL 05h 1111 111- uuuu uuu- GPIO 06h --xx xxxx --uu uuuu OPTION — 1111 1111 1111 1111 TRIS — --11 1111 --11 1111 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. 2: See Table7-5 for Reset value for specific conditions. 3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. 4: PIC12F509 only. 5: PIC12F508 only. © 2009 Microchip Technology Inc. DS41236E-page 47

PIC12F508/509/16F505 TABLE 7-4: RESET CONDITIONS FOR REGISTERS – PIC16F505 MCLR Reset, WDT Time-out, Register Address Power-on Reset Wake-up On Pin Change W — qqqq qqqu(1) qqqq qqqu(1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx q00q quuu(2), (3) FSR 04h 100x xxxx 1uuu uuuu OSCCAL 05h 1111 111- uuuu uuu- PORTB 06h --xx xxxx --uu uuuu PORTC 07h --xx xxxx --uu uuuu OPTION — 1111 1111 1111 1111 TRISB — --11 1111 --11 1111 TRISC — --11 1111 --11 1111 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. 2: See Table7-5 for Reset value for specific conditions. 3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. TABLE 7-5: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h PCL Addr: 02h Power-on Reset 0001 1xxx 1111 1111 MCLR Reset during normal operation 000u uuuu 1111 1111 MCLR Reset during Sleep 0001 0uuu 1111 1111 WDT Reset during Sleep 0000 0uuu 1111 1111 WDT Reset normal operation 0000 uuuu 1111 1111 Wake-up from Sleep on pin change 1001 0uuu 1111 1111 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’. DS41236E-page 48 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 7.3.1 MCLR ENABLE The Power-on Reset circuit and the Device Reset Timer (see Section7.5 “Device Reset Timer (DRT)”) This Configuration bit, when unprogrammed (left in the circuit are closely related. On power-up, the Reset latch ‘1’ state), enables the external MCLR function. When is set and the DRT is reset. The DRT timer begins programmed, the MCLR function is tied to the internal counting once it detects MCLR to be high. After the VDD and the pin is assigned to be an input only. See time-out period, which is typically 18ms, it will reset the Figure7-6. Reset latch and thus end the on-chip Reset signal. FIGURE 7-6: MCLR SELECT A power-up example where MCLR is held low is shown in Figure7-8. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of GPWU/RBWU Reset TDRT msec after MCLR goes high. (GP3/RB3)/MCLR/VPP In Figure7-9, the on-chip Power-on Reset feature is being used (MCLR and VDD are tied together or the pin is programmed to be (GP3/RB3). The VDD is stable MCLRE Internal MCLR before the start-up timer times out and there is no prob- lem in getting a proper Reset. However, Figure7-10 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses that MCLR is 7.4 Power-on Reset (POR) high and when MCLR and VDD actually reach their full value, is too long. In this situation, when the start-up The PIC12F508/509/16F505 devices incorporate an timer times out, VDD has not reached the VDD (min) on-chip Power-on Reset (POR) circuitry, which value and the chip may not function correctly. For such provides an internal chip Reset for most power-up situations, we recommend that external RC circuits be situations. used to achieve longer POR delay times (Figure7-9). The on-chip POR circuit holds the chip in Reset until Note: When the devices start normal operation VDD has reached a high enough level for proper (exit the Reset condition), device operat- operation. To take advantage of the internal POR, ing parameters (voltage, frequency, tem- program the (GP3/RB3)/MCLR/VPP pin as MCLR and perature, etc.) must be met to ensure tie through a resistor to VDD, or program the pin as operation. If these conditions are not met, (GP3/RB3). An internal weak pull-up resistor is the device must be held in Reset until the implemented using a transistor (refer to Table10-2 for operating conditions are met. the pull-up resistor ranges). This will eliminate external For additional information, refer to Application Notes RC components usually needed to create a Power-on AN522 “Power-Up Considerations” (DS00522) and Reset. A maximum rise time for VDD is specified. See AN607 “Power-up Trouble Shooting” (DS00607). Section10.0 “Electrical Characteristics” for details. When the devices start normal operation (exit the Reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the devices must be held in Reset until the operating parameters are met. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure7-7. © 2009 Microchip Technology Inc. DS41236E-page 49

PIC12F508/509/16F505 FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) (GP3/RB3)/MCLR/VPP MCLR Reset S Q MCLRE R Q WDT Reset WDT Time-out Start-up Timer CHIP Reset Pin Change (10 μs or 18 ms) Sleep Wake-up on pin Change Reset FIGURE 7-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) VDD MCLR Internal POR TDRT DRT Time-out Internal Reset FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR Internal POR TDRT DRT Time-out Internal Reset DS41236E-page 50 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min. © 2009 Microchip Technology Inc. DS41236E-page 51

PIC12F508/509/16F505 7.5 Device Reset Timer (DRT) TABLE 7-6: DRT (DEVICE RESET TIMER PERIOD) On the PIC12F508/509/16F505 devices, the DRT runs any time the device is powered up. DRT runs from Oscillator Subsequent POR Reset Reset and varies based on oscillator selection and Configuration Resets Reset type (see Table7-6). INTOSC, EXTRC 18ms (typical) 10μs (typical) The DRT operates on an internal RC oscillator. The HS(1), XT, LP 18ms (typical) 18ms (typical) processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and EC(1) 18ms (typical) 10μs (typical) for the oscillator to stabilize. Note 1: PIC16F505 only. Oscillator circuits based on crystals or ceramic resona- tors require a certain time after power-up to establish a 7.6.1 WDT PERIOD stable oscillation. The on-chip DRT keeps the devices in The WDT has a nominal time-out period of 18ms, (with a Reset condition for approximately 18ms after MCLR no prescaler). If a longer time-out period is desired, a has reached a logic high (VIH MCLR) level. prescaler with a division ratio of up to 1:128 can be Programming (GP3/RB3)/MCLR/VPP as MCLR and assigned to the WDT (under software control) by using an external RC network connected to the MCLR writing to the OPTION register. Thus, a time-out period input is not required in most cases. This allows savings of a nominal 2.3 seconds can be realized. These in cost-sensitive and/or space restricted applications, as periods vary with temperature, VDD and part-to-part well as allowing the use of the (GP3/RB3)/MCLR/VPP process variations (see DC specs). pin as a general purpose input. Under worst case conditions (VDD = Min., Temperature The Device Reset Time delays will vary from chip-to- = Max., max. WDT prescaler), it may take several chip due to VDD, temperature and process variation. seconds before a WDT time-out occurs. See AC parameters for details. 7.6.2 WDT PROGRAMMING The DRT will also be triggered upon a Watchdog Timer time-out from Sleep. This is particularly important for CONSIDERATIONS applications using the WDT to wake from Sleep mode The CLRWDT instruction clears the WDT and the automatically. postscaler, if assigned to the WDT, and prevents it from Reset sources are POR, MCLR, WDT time-out and timing out and generating a device Reset. wake-up on pin change. See Section7.9.2 “Wake-up The SLEEP instruction resets the WDT and the post- from Sleep”, Notes 1, 2 and 3. scaler, if assigned to the WDT. This gives the maximum Sleep time before a WDT wake-up Reset. 7.6 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the external RC oscillator of the (GP5/RB5)/OSC1/CLKIN pin and the internal 4MHz oscillator. This means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or Sleep, a WDT Reset or wake-up Reset, generates a device Reset. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer Reset. The WDT can be permanently disabled by programming the configuration WDTE as a ‘0’ (see Section7.1 “Configuration Bits”). Refer to the PIC12F508/509/16F505 Programming Specifications to determine how to access the Configuration Word. DS41236E-page 52 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 FIGURE 7-11: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure6-5) 0 M Watchdog 1 U PPoossttssccaalleerr Time X 8-to-1 MUX PS<2:0> PSA WDT Enable Configuration To Timer0 (Figure6-4) Bit 0 1 MUX PSA WDT Time-out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. TABLE 7-7: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets N/A OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: Shaded boxes = Not used by Watchdog Timer. – = unimplemented, read as ‘0’, u = unchanged. Note 1: PIC12F508/509 only. 2: PIC16F505 only. © 2009 Microchip Technology Inc. DS41236E-page 53

PIC12F508/509/16F505 7.7 Time-out Sequence, Power-down FIGURE 7-13: BROWN-OUT and Wake-up from Sleep Status PROTECTION CIRCUIT 2 Bits (TO, PD, GPWUF/RBWUF) VDD VDD The TO, PD and (GPWUF/RBWUF) bits in the STATUS register can be tested to determine if a Reset R1 PIC16F505 condition has been caused by a Power-up condition, a PIC12F508 MCLR or Watchdog Timer (WDT) Reset. Q1MCLR(2)PIC12F509 TABLE 7-8: TO/PD/(GPWUF/RBWUF) R2 40k(1) STATUS AFTER RESET GPWUF/ TO PD Reset Caused By RBWUF Note 1: This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns 0 0 0 WDT wake-up from Sleep off when VDD is below a certain level such 0 0 u WDT time-out (not from that: Sleep) R1 0 1 0 MCLR wake-up from Sleep VDD • R1 + R2 = 0.7V 0 1 1 Power-up 2: Pin must be confirmed as MCLR. 0 u u MCLR not during Sleep 1 1 0 Wake-up from Sleep on pin FIGURE 7-14: BROWN-OUT change PROTECTION CIRCUIT 3 Legend: u = unchanged VDD Note 1: The TO, PD and GPWUF/RBWUF bits maintain their status (u) until a Reset MCP809 Bypass VDD occurs. A low-pulse on the MCLR input VSS Capacitor does not change the TO, PD and VDD GPWUF/RBWUF Status bits. RST MCLR 7.8 Reset on Brown-out PIC16F505 PIC12F508 A brown-out is a condition where device power (VDD) PIC12F509 dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. Note: This brown-out protection circuit employs Microchip Technology’s MCP809 micro- To reset PIC12F508/509/16F505 devices when a controller supervisor. There are 7 different brown-out occurs, external brown-out protection trip point selections to accommodate 5V to circuits may be built, as shown in Figure7-12 and 3V systems. Figure7-13. FIGURE 7-12: BROWN-OUT PROTECTION CIRCUIT 1 VDD VDD 33k PIC16F505 PIC12F508 10k Q1 MCLR(2)PIC12F509 40k(1) Note 1: This circuit will activate Reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). 2: Pin must be confirmed as MCLR. DS41236E-page 54 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 7.9 Power-down Mode (Sleep) 7.10 Program Verification/Code Protection A device may be powered down (Sleep) and later powered up (wake-up from Sleep). If the code protection bit has not been programmed, the on-chip program memory can be read out for 7.9.1 SLEEP verification purposes. The Power-Down mode is entered by executing a The first 64 locations and the last location (OSCCAL) SLEEP instruction. can be read, regardless of the code protection bit If enabled, the Watchdog Timer will be cleared but setting. keeps running, the TO bit (STATUS<4>) is set, the PD The last memory location can be read regardless of the bit (STATUS<3>) is cleared and the oscillator driver is code protection bit setting on the PIC12F508/509/ turned off. The I/O ports maintain the status they had 16F505 devices. before the SLEEP instruction was executed (driving high, driving low or high-impedance). 7.11 ID Locations Note: A Reset generated by a WDT time-out Four memory locations are designated as ID locations does not drive the MCLR pin low. where the user can store checksum or other code For lowest current consumption while powered down, identification numbers. These locations are not the T0CKI input should be at VDD or VSS and the accessible during normal execution, but are readable (GP3/RB3)/MCLR/VPP pin must be at a logic high and writable during Program/Verify. level if MCLR is enabled. Use only the lower 4 bits of the ID locations and always program the upper 8 bits as ‘0’s. 7.9.2 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of 7.12 In-Circuit Serial Programming™ the following events: The PIC12F508/509/16F505 microcontrollers can be 1. An external Reset input on (GP3/RB3)/MCLR/ serially programmed while in the end application circuit. VPP pin, when configured as MCLR. This is simply done with two lines for clock and data, 2. A Watchdog Timer time-out Reset (if WDT was and three other lines for power, ground and the enabled). programming voltage. This allows customers to manu- 3. A change on input pin GP0/RB0, GP1/RB1, facture boards with unprogrammed devices and then GP3/RB3 or RB4 when wake-up on change is program the microcontroller just before shipping the enabled. product. This also allows the most recent firmware, or These events cause a device Reset. The TO, PD and a custom firmware, to be programmed. GPWUF/RBWUF bits can be used to determine the The devices are placed into a Program/Verify mode by cause of device Reset. The TO bit is cleared if a WDT holding the GP1/RB1 and GP0/RB0 pins low while time-out occurred (and caused wake-up). The PD bit, raising the MCLR (VPP) pin from VIL to VIHH (see which is set on power-up, is cleared when SLEEP is programming specification). GP1/RB1 becomes the invoked. The GPWUF/RBWUF bit indicates a change programming clock and GP0/RB0 becomes the in state while in Sleep at pins GP0/RB0, GP1/RB1, programming data. Both GP1/RB1 and GP0/RB0 are GP3/RB3 or RB4 (since the last file or bit operation on Schmitt Trigger inputs in this mode. GP/RB port). After Reset, a 6-bit command is then supplied to the Note: Caution: Right before entering Sleep, device. Depending on the command, 14 bits of program read the input pins. When in Sleep, wake- data are then supplied to or from the device, depending up occurs when the values at the pins if the command was a Load or a Read. For complete change from the state they were in at the details of serial programming, please refer to the last reading. If a wake-up on change PIC12F508/509/16F505 Programming Specifications. occurs and the pins are not read before re- A typical In-Circuit Serial Programming connection is entering Sleep, a wake-up will occur shown in Figure7-15. immediately even if no pins change while in Sleep mode. The WDT is cleared when the device wakes from Sleep, regardless of the wake-up source. © 2009 Microchip Technology Inc. DS41236E-page 55

PIC12F508/509/16F505 FIGURE 7-15: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections External PIC16F505 Connector Signals PIC12F508 PIC12F509 +5V VDD 0V VSS VPP MCLR/VPP CLK GP1/RB1 Data I/O GP0/RB0 VDD To Normal Connections DS41236E-page 56 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 8.0 INSTRUCTION SET SUMMARY All instructions are executed within a single instruction cycle, unless a conditional test is true or the program The PIC16 instruction set is highly orthogonal and is counter is changed as a result of an instruction. In this comprised of three basic categories. case, the execution takes two instruction cycles. One • Byte-oriented operations instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4MHz, the normal • Bit-oriented operations instruction execution time is 1μs. If a conditional test is • Literal and control operations true or the program counter is changed as a result of an Each PIC16 instruction is a 12-bit word divided into an instruction, the instruction execution time is 2μs. opcode, which specifies the instruction type, and one Figure8-1 shows the three general formats that the or more operands which further specify the operation instructions can have. All examples in the figure use of the instruction. The formats for each of the catego- the following format to represent a hexadecimal ries is presented in Figure8-1, while the various number: opcode fields are summarized in Table8-1. 0xhhh For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination where ‘h’ signifies a hexadecimal digit. designator. The file register designator specifies which file register is to be used by the instruction. FIGURE 8-1: GENERAL FORMAT FOR INSTRUCTIONS The destination designator specifies where the result of the operation is to be placed. If ‘d’ is ‘0’, the result is Byte-oriented file register operations placed in the W register. If ‘d’ is ‘1’, the result is placed 11 6 5 4 0 in the file register specified in the instruction. OPCODE d f (FILE #) For bit-oriented instructions, ‘b’ represents a bit field d = 0 for destination W designator which selects the number of the bit affected d = 1 for destination f by the operation, while ‘f’ represents the number of the f = 5-bit file register address file in which the bit is located. Bit-oriented file register operations For literal and control operations, ‘k’ represents an 11 8 7 5 4 0 8or 9-bit constant or literal value. OPCODE b (BIT #) f (FILE #) TABLE 8-1: OPCODE FIELD b = 3-bit bit address DESCRIPTIONS f = 5-bit file register address Field Description Literal and control operations (except GOTO) f Register file address (0x00 to 0x7F) 11 8 7 0 W Working register (accumulator) OPCODE k (literal) b Bit address within an 8-bit file register k = 8-bit immediate value k Literal field, constant data or label x Don’t care location (= 0 or 1) Literal and control operations – GOTO instruction The assembler will generate code with x = 0. It is 11 9 8 0 the recommended form of use for compatibility with OPCODE k (literal) all Microchip software tools. d Destination select; k = 9-bit immediate value d = 0 (store result in W) d = 1 (store result in file register ‘f’) Default is d = 1 label Label name TOS Top-of-Stack PC Program Counter WDT Watchdog Timer counter TO Time-out bit PD Power-down bit dest Destination, either the W register or the specified register file location [ ] Options ( ) Contents → Assigned to < > Register bit field ∈ In the set of italics User defined term (font is courier) © 2009 Microchip Technology Inc. DS41236E-page 57

PIC12F508/509/16F505 TABLE 8-2: INSTRUCTION SET SUMMARY Mnemonic, 12-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected ADDWF f, d Add W and f 1 0001 11df ffff C, DC, Z 1, 2, 4 ANDWF f, d AND W with f 1 0001 01df ffff Z 2, 4 CLRF f Clear f 1 0000 011f ffff Z 4 CLRW — Clear W 1 0000 0100 0000 Z COMF f, d Complement f 1 0010 01df ffff Z DECF f, d Decrement f 1 0000 11df ffff Z 2, 4 DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2, 4 INCF f, d Increment f 1 0010 10df ffff Z 2, 4 INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2, 4 IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2, 4 MOVF f, d Move f 1 0010 00df ffff Z 2, 4 MOVWF f Move W to f 1 0000 001f ffff None 1, 4 NOP — No Operation 1 0000 0000 0000 None RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2, 4 RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2, 4 SUBWF f, d Subtract W from f 1 0000 10df ffff C, DC, Z 1, 2, 4 SWAPF f, d Swap f 1 0011 10df ffff None 2, 4 XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2, 4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 0100 bbbf ffff None 2, 4 BSF f, b Bit Set f 1 0101 bbbf ffff None 2, 4 BTFSC f, b Bit Test f, Skip if Clear 1(2) 0110 bbbf ffff None BTFSS f, b Bit Test f, Skip if Set 1(2) 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Call Subroutine 2 1001 kkkk kkkk None 1 CLRWDT — Clear Watchdog Timer 1 0000 0000 0100 TO, PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR literal with W 1 1101 kkkk kkkk Z MOVLW k Move literal to W 1 1100 kkkk kkkk None OPTION — Load OPTION register 1 0000 0000 0010 None RETLW k Return, place literal in W 2 1000 kkkk kkkk None SLEEP — Go into Standby mode 1 0000 0000 0011 TO, PD TRIS f Load TRIS register 1 0000 0000 0fff None 3 XORLW k Exclusive OR literal to W 1 1111 kkkk kkkk Z Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for GOTO. See Section4.7 “Program Counter”. 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS41236E-page 58 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 ADDWF Add W and f BCF Bit Clear f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BCF f,b Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + (f) → (dest) Operation: 0 → (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is cleared. and register ‘f’. If ‘d’ is’0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W BSF Bit Set f Syntax: [ label ] ANDLW k Syntax: [ label ] BSF f,b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 31 Operation: (W).AND. (k) → (W) 0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: Z Status Affected: None Description: The contents of the W register are AND’ed with the eight-bit literal ‘k’. Description: Bit ‘b’ in register ‘f’ is set. The result is placed in the W register. ANDWF AND W with f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDWF f,d Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) .AND. (f) → (dest) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: The contents of the W register are Description: If bit ‘b’ in register ‘f’ is ‘0’, then the AND’ed with register ‘f’. If ‘d’ is ‘0’, next instruction is skipped. the result is stored in the W register. If bit ‘b’ is ‘0’, then the next instruc- If ‘d’ is ‘1’, the result is stored back tion fetched during the current in register ‘f’. instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction. © 2009 Microchip Technology Inc. DS41236E-page 59

PIC12F508/509/16F505 BTFSS Bit Test f, Skip if Set CLRW Clear W Syntax: [ label ] CLRW Syntax: [ label ] BTFSS f,b Operands: 0 ≤ f ≤ 31 Operands: None 0 ≤ b < 7 Operation: 00h → (W); 1 → Z Operation: skip if (f<b>) = 1 Status Affected: Z Status Affected: None Description: The W register is cleared. Zero bit Description: If bit ‘b’ in register ‘f’ is ‘1’, then the (Z) is set. next instruction is skipped. If bit ‘b’ is ‘1’, then the next instruc- tion fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. CALL Subroutine Call CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 ≤ k ≤ 255 Operands: None Operation: (PC) + 1→ Top-of-Stack; Operation: 00h → WDT; k → PC<7:0>; 0 → WDT prescaler (if assigned); (STATUS<6:5>) → PC<10:9>; 1 → TO; 0 → PC<8> 1 → PD Status Affected: None Status Affected: TO, PD Description: Subroutine call. First, return Description: The CLRWDT instruction resets the address (PC + 1) is PUSHed onto WDT. It also resets the prescaler, if the stack. The eight-bit immediate the prescaler is assigned to the address is loaded into PC WDT and not Timer0. Status bits bits <7:0>. The upper bits TO and PD are set. PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a two-cycle instruction. CLRF Clear f COMF Complement f Syntax: [ label ] CLRF f Syntax: [ label ] COMF f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 Operation: 00h → (f); d ∈ [0,1] 1 → Z Operation: (f) → (dest) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are cleared and the Z bit is set. complemented. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS41236E-page 60 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 DECF Decrement f INCF Increment f Syntax: [ label ] DECF f,d Syntax: [ label ] INCF f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: (f) – 1 → (dest) Operation: (f) + 1 → (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, Description: The contents of register ‘f’ are the result is stored in the W incremented. If ‘d’ is ‘0’, the result register. If ‘d’ is ‘1’, the result is is placed in the W register. If ‘d’ is stored back in register ‘f’. ‘1’, the result is placed back in register ‘f’. DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: (f) – 1 → d; skip if result = 0 Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. If the result is ‘0’, the next instruc- If the result is ‘0’, then the next tion, which is already fetched, is instruction, which is already discarded and a NOP is executed fetched, is discarded and a NOP is instead making it a two-cycle executed instead making it a instruction. two-cycle instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0 ≤ k ≤ 511 Operands: 0 ≤ k ≤ 255 Operation: k → PC<8:0>; Operation: (W) .OR. (k) → (W) STATUS<6:5> → PC<10:9> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the eight-bit literal ‘k’. The 9-bit immediate value is The result is placed in the loaded into PC bits <8:0>. The W register. upper bits of PC are loaded from STATUS<6:5>. GOTO is a two- cycle instruction. © 2009 Microchip Technology Inc. DS41236E-page 61

PIC12F508/509/16F505 IORWF Inclusive OR W with f MOVWF Move W to f Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVWF f Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (W) → (f) Operation: (W).OR. (f) → (dest) Status Affected: None Status Affected: Z Description: Move data from the W register to Description: Inclusive OR the W register with register ‘f’. register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. MOVF Move f NOP No Operation Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP Operands: 0 ≤ f ≤ 31 Operands: None d ∈ [0,1] Operation: No operation Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register ‘f’ are moved to destination ‘d’. If ‘d’ is ‘0’, destination is the W register. If ‘d’ is ‘1’, the destination is file register ‘f’. ‘d’ = 1 is useful as a test of a file register, since status flag Z is affected. MOVLW Move Literal to W OPTION Load OPTION Register Syntax: [ label ] MOVLW k Syntax: [ label ] OPTION Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W) Operation: (W) → OPTION Status Affected: None Status Affected: None Description: The content of the W register is Description: The eight-bit literal ‘k’ is loaded loaded into the OPTION register. into the W register. The “don’t cares” will assembled as ‘0’s. DS41236E-page 62 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 RETLW Return with Literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] RETLW k Syntax: [label ] SLEEP Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W); Operation: 00h → WDT; TOS → PC 0 → WDT prescaler; Status Affected: None 1 → TO; 0 → PD Description: The W register is loaded with the eight-bit literal ‘k’. The program Status Affected: TO, PD, RBWUF counter is loaded from the top of Description: Time-out Status bit (TO) is set. The the stack (the return address). This Power-down Status bit (PD) is is a two-cycle instruction. cleared. RBWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. See Section7.9 “Power-down Mode (Sleep)” on Sleep for more details. RLF Rotate Left f through Carry SUBWF Subtract W from f Syntax: [ label ] RLF f,d Syntax: [label ] SUBWF f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: See description below Operation: (f) – (W) → (dest) Status Affected: C Status Affected: C, DC, Z Description: The contents of register ‘f’ are Description: Subtract (2’s complement method) rotated one bit to the left through the W register from register ‘f’. If ‘d’ the Carry flag. If ‘d’ is ‘0’, the result is ‘0’, the result is stored in the W is placed in the W register. If ‘d’ is register. If ‘d’ is ‘1’, the result is ‘1’, the result is stored back in stored back in register ‘f’. register ‘f’. C register ‘f’ RRF Rotate Right f through Carry SWAPF Swap Nibbles in f Syntax: [ label ] RRF f,d Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: See description below Operation: (f<3:0>) → (dest<7:4>); (f<7:4>) → (dest<3:0>) Status Affected: C Status Affected: None Description: The contents of register ‘f’ are rotated one bit to the right through Description: The upper and lower nibbles of the Carry flag. If ‘d’ is ‘0’, the result register ‘f’ are exchanged. If ‘d’ is is placed in the W register. If ‘d’ is ‘0’, the result is placed in W ‘1’, the result is placed back in register. If ‘d’ is ‘1’, the result is register ‘f’. placed in register ‘f’. C register ‘f’ © 2009 Microchip Technology Inc. DS41236E-page 63

PIC12F508/509/16F505 TRIS Load TRIS Register XORWF Exclusive OR W with f Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d Operands: f = 6 Operands: 0 ≤ f ≤ 31 Operation: (W) → TRIS register f d ∈ [0,1] Status Affected: None Operation: (W) .XOR. (f) → (dest) Description: TRIS register ‘f’ (f = 6 or 7) is Status Affected: Z loaded with the contents of the W Description: Exclusive OR the contents of the register W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is XORLW Exclusive OR literal with W stored back in register ‘f’. Syntax: [label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. DS41236E-page 64 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 9.0 DEVELOPMENT SUPPORT 9.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software • Integrated Development Environment development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software operating system-based application that contains: • Assemblers/Compilers/Linkers • A single graphical interface to all debugging tools - MPASMTM Assembler - Simulator - MPLAB C18 and MPLAB C30 C Compilers - Programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) • Simulators • A full-featured editor with color-coded context - MPLAB SIM Software Simulator • A multiple project manager • Emulators • Customizable data windows with direct edit of contents - MPLAB ICE 2000 In-Circuit Emulator • High-level source code debugging - MPLAB REAL ICE™ In-Circuit Emulator • Visual device initializer for easy register • In-Circuit Debugger initialization - MPLAB ICD 2 • Mouse over variable inspection • Device Programmers • Drag and drop variables from source to watch - PICSTART® Plus Development Programmer windows - MPLAB PM3 Device Programmer • Extensive on-line help - PICkit™ 2 Development Programmer • Integration of select third party tools, such as • Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR Boards and Evaluation Kits C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2009 Microchip Technology Inc. DS41236E-page 65

PIC12F508/509/16F505 9.2 MPASM Assembler 9.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: • Support for the entire dsPIC30F instruction set • Integration into MPLAB IDE projects • Support for fixed-point and floating-point data • User-defined macros to streamline • Command line interface assembly code • Rich directive set • Conditional assembly for multi-purpose source files • Flexible macro language • Directives that allow complete control over the • MPLAB IDE compatibility assembly process 9.6 MPLAB SIM Software Simulator 9.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an The MPLAB C18 and MPLAB C30 Code Development instruction level. On any given instruction, the data Systems are complete ANSI C compilers for areas can be examined or modified and stimuli can be Microchip’s PIC18 and PIC24 families of microcon- applied from a comprehensive stimulus controller. trollers and the dsPIC30 and dsPIC33 family of digital Registers can be logged to files for further run-time signal controllers. These compilers provide powerful analysis. The trace buffer and logic analyzer display integration capabilities, superior code optimization and extend the power of the simulator to record and track ease of use not found with other compilers. program execution, actions on I/O, most peripherals For easy source level debugging, the compilers provide and internal registers. symbol information that is optimized to the MPLAB IDE The MPLAB SIM Software Simulator fully supports debugger. symbolic debugging using the MPLAB C18 and MPLAB C30 CCompilers, and the MPASM and 9.4 MPLINK Object Linker/ MPLAB ASM30 Assemblers. The software simulator MPLIB Object Librarian offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an The MPLINK Object Linker combines relocatable excellent, economical software development tool. objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS41236E-page 66 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 9.7 MPLAB ICE 2000 9.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes microcontrollers. Software control of the MPLAB ICE the in-circuit debugging capability built into theFlash 2000 In-Circuit Emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers cost- editing, building, downloading and source debugging effective, in-circuit Flash debugging from the graphical from a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step- ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB ICE 2000 In-Circuit Emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 9.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display simple, unified application. (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various 9.8 MPLAB REAL ICE In-Circuit package types. The ICSP™ cable assembly is included Emulator System as a standard item. In Stand-Alone mode, the MPLAB MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set Microchip Flash DSC and MCU devices. It debugs and code protection in this mode. The MPLAB PM3 programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable. with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large included with each kit. memory devices and incorporates an SD/MMC card for file storage and secure data applications. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, Low- Voltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2009 Microchip Technology Inc. DS41236E-page 67

PIC12F508/509/16F505 9.11 PICSTART Plus Development 9.13 Demonstration, Development and Programmer Evaluation Boards The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func- Integrated Development Environment software makes tional systems. Most boards include prototyping areas for using the programmer simple and efficient. The adding custom circuitry and provide application firmware PICSTART Plus Development Programmer supports and source code for examination and modification. most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs, Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232 PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional The PICSTART Plus Development Programmer is CE EEPROM memory. compliant. The demonstration and development boards can be used in teaching environments, for prototyping custom 9.12 PICkit 2 Development Programmer circuits and for learning about various microcontroller The PICkit™ 2 Development Programmer is a low-cost applications. programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ an easy-to-use interface for programming many of demonstration/development board series of circuits, Microchip’s baseline, mid-range and PIC18F families Microchip has a line of evaluation kits and of Flash memory microcontrollers. The PICkit 2 Starter demonstration software for analog filter design, Kit includes a prototyping development board, twelve KEELOQ® security ICs, CAN, IrDA®, PowerSmart sequential lessons, software and HI-TECH’s PICC™ battery management, SEEVAL® evaluation system, Lite C compiler, and is designed to help get up to speed Sigma-Delta ADC, flow rate sensing, plus many more. quickly using PIC® microcontrollers. The kit provides Check the Microchip web page (www.microchip.com) everything needed to program, evaluate and develop for the complete list of demonstration, development applications using Microchip’s powerful, mid-range and evaluation kits. Flash memory family of microcontrollers. DS41236E-page 68 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 10.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40°C to +125°C Storage temperature............................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS...............................................................................................................0 to +6.5V Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V Voltage on all other pins with respect to VSS...............................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)..................................................................................................................................800mW Max. current out of VSS pin................................................................................................................................200mA Max. current into VDD pin...................................................................................................................................150mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)...........................................................................................................±20mA Max. output current sunk by any I/O pin..............................................................................................................25mA Max. output current sourced by any I/O pin.........................................................................................................25mA Max. output current sourced by I/O port ..............................................................................................................75mA Max. output current sunk by I/O port ...................................................................................................................75mA Note1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS41236E-page 69

PIC12F508/509/16F505 FIGURE 10-1: PIC12F508/509/16F505 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 6.0 5.5 (PIC16F505 only) 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 20 25 Frequency (MHz) FIGURE 10-2: MAXIMUM OSCILLATOR FREQUENCY TABLE LP XT e d o INTOSC M r ato EXTRC scill EC(1) O HS(1) 0 200 kHz 4 MHz 20 MHz Frequency (MHz) Note 1: For PIC16F505 only. DS41236E-page 70 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 10.1 DC Characteristics: PIC12F508/509/16F505 (Industrial) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) Param Sym. Characteristic Min. Typ(1) Max. Units Conditions No. D001 VDD Supply Voltage 2.0 5.5 V See Figure10-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure — Vss — V See Section7.4"Power-on Power-on Reset Reset (POR)" for details D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section7.4"Power-on Power-on Reset Reset (POR)" for details D010 IDD Supply Current(3,4) — 175 275 μA FOSC = 4MHz, VDD = 2.0V — 0.625 1.1 mA FOSC = 4MHz, VDD = 5.0V — 500 650 μA FOSC = 10MHz, VDD = 3.0V — 1.5 2.2 mA FOSC = 20MHz, VDD = 5.0V (PIC16F505 only) — 11 20 μA FOSC = 32kHz, VDD = 2.0V — 38 54 μA FOSC = 32kHz, VDD = 5.0V D020 IPD Power-down Current(5) — 0.1 1.2 μA VDD = 2.0V — 0.35 2.4 μA VDD = 5.0V D022 IWDT WDT Current(5) — 1.0 3.0 μA VDD = 2.0V — 7.0 16.0 μA VDD = 5.0V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep. © 2009 Microchip Technology Inc. DS41236E-page 71

PIC12F508/509/16F505 10.2 DC Characteristics: PIC12F508/509/16F505 (Extended) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature -40°C ≤ TA ≤ +125°C (extended) Param Sym. Characteristic Min. Typ(1) Max. Units Conditions No. D001 VDD Supply Voltage 2.0 5.5 V See Figure10-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure — Vss — V See Section7.4"Power-on Power-on Reset Reset (POR)" for details D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section7.4"Power-on Power-on Reset Reset (POR)" for details D010 IDD Supply Current(3,4) — 175 275 μA FOSC = 4MHz, VDD = 2.0V — 0.625 1.1 mA FOSC = 4MHz, VDD = 5.0V — 500 650 μA FOSC = 10MHz, VDD = 3.0V — 1.5 2.2 mA FOSC = 20MHz, VDD = 5.0V (PIC16F515 only) — 11 26 μA FOSC = 32kHz, VDD = 2.0V — 38 110 μA FOSC = 32kHz, VDD = 5.0V D020 IPD Power-down Current(5) — 0.1 9.0 μA VDD = 2.0V — 0.35 15.0 μA VDD = 5.0V D022 IWDT WDT Current(5) — 1.0 18 μA VDD = 2.0V — 7.0 22 μA VDD = 5.0V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep. DS41236E-page 72 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 TABLE 10-1: DC CHARACTERISTICS: PIC12F508/509/16F505 (Industrial, Extended) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating temperature --4400°°CC ≤≤ TTAA ≤≤ ++8152°5C°C ( in(edxutestnrdiael)d) Operating voltage VDD range as described in DC specification Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer Vss — 0.8V V For all 4.5 ≤ VDD ≤ 5.5V D030A Vss — 0.15 VDD V Otherwise D031 with Schmitt Trigger buffer Vss — 0.15 VDD V D032 MCLR, T0CKI Vss — 0.15 VDD V D033 OSC1 (in EXTRC) Vss — 0.15 VDD V (Note1) D033 OSC1 (in HS) Vss — 0.3 VDD V (Note1) D033 OSC1 (in XT and LP) Vss — 0.3 V (Note1) VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V 4.5 ≤ VDD ≤ 5.5V D040A 0.25 VDD — VDD V Otherwise + 0.8 D041 with Schmitt Trigger buffer 0.85 VDD — VDD V For entire VDD range D042 MCLR, T0CKI 0.85 VDD — VDD V D043 OSC1 (in EXTRC) 0.85 VDD — VDD V (Note1) D043 OSC1 (in HS) 0.7 VDD — VDD V (Note1) D043 OSC1 (in XT and LP) 1.6 — VDD V D070 IPUR GPIO/PORTB weak pull-up 50 250 400 μA VDD = 5V, VPIN = VSS current(4) IIL Input Leakage Current(2), (3) D060 I/O ports — — ± 1 μA Vss ≤ VPIN ≤ VDD, Pin at high-impedance D061 GP3/RB3/MCLRI(5) — ± 0.7 ± 5 μA Vss ≤ VPIN ≤ VDD D063 OSC1 — — ± 5 μA Vss ≤ VPIN ≤ VDD, XT, HS and LP oscillator configuration Output Low Voltage D080 I/O ports/CLKOUT — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D080A — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C D083 OSC2 — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C D083A — — 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40°C to +125°C Output High Voltage D090 I/O ports/CLKOUT(3) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C D090A VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C D092 OSC2 VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C D092A VDD – 0.7 — — V IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C Capacitive Loading Specs on Output Pins D100 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 — — 50 pF † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F508/509/ 16F505 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: The specification applies to all weak pull-up devices, including the weak pull-up on GP3/MCLR. The current listed will be the same whether GP3/MCLR is configured as GP3 with a weak pull-up or enabled as MCLR. 5: This specification applies when GP3/RB3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is higher than the standard I/O logic. © 2009 Microchip Technology Inc. DS41236E-page 73

PIC12F508/509/16F505 TABLE 10-2: PULL-UP RESISTOR RANGES – PIC12F508/509/16F505 VDD (Volts) Temperature (°C) Min. Typ. Max. GP0(RBO)/GP1(RB1) 2.0 –40 73K 105K 186K 25 73K 113K 187K 85 82K 123K 190K 125 86K 132k 190K 5.5 –40 15K 21K 33K 25 15K 22K 34K 85 19K 26k 35K 125 23K 29K 35K GP3(RB3) 2.0 –40 63K 81K 96K 25 77K 93K 116K 85 82K 96k 116K 125 86K 100K 119K 5.5 –40 16K 20k 22K 25 16K 21K 23K 85 24K 25k 28K 125 26K 27K 29K * These parameters are characterized but not tested. DS41236E-page 74 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 10.3 Timing Parameter Symbology and Load Conditions – PIC12F508/509/16F505 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc Oscillator cy Cycle time os OSC1 drt Device Reset Timer t0 T0CKI io I/O port wdt Watchdog Timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (high-impedance) V Valid L Low Z High-impedance FIGURE 10-3: LOAD CONDITIONS – PIC12F508/509/16F505 Legend: pin CL CL = 50 pF for all pins except OSC2 15 pF for OSC2 in XT, HS or LP modes when external clock VSS is used to drive OSC1 FIGURE 10-4: EXTERNAL CLOCK TIMING – PIC12F508/509/16F505 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 © 2009 Microchip Technology Inc. DS41236E-page 75

PIC12F508/509/16F505 TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS – PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), AC CHARACTERISTICS -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section10.1"Power- on Reset (POR)" Param Sym. Characteristic Min. Typ(1) Max. Units Conditions No. 1A FOSC External CLKIN Frequency(2) DC — 4 MHz XT Oscillator mode DC — 20 MHz EC, HS Oscillator mode (PIC16F505 only) DC — 200 kHz LP Oscillator mode Oscillator Frequency(2) — — 4 MHz EXTRC Oscillator mode 0.1 — 4 MHz XT Oscillator mode 4 — 20 MHz HS Oscillator mode (PIC16F505 only) — — 200 kHz LP Oscillator mode 1 TOSC External CLKIN Period(2) 250 — — ns XT Oscillator mode 50 — — ns EC, HS Oscillator mode (PIC16F505 only) 5 — — μs LP Oscillator mode Oscillator Period(2) 250 — — ns EXTRC Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 250 ns HS Oscillator mode (PIC16F505 only) 5 — — μs LP Oscillator mode 2 TCY Instruction Cycle Time 200 4/FOSC — ns 3 TosL, Clock in (OSC1) Low or High 50* — — ns XT Oscillator TosH Time 2* — — μs LP Oscillator 10* — — ns EC, HS Oscillator (PIC16F505 only) 4 TosR, Clock in (OSC1) Rise or Fall — — 25* ns XT Oscillator TosF Time — — 50* ns LP Oscillator — — 15* ns EC, HS Oscillator (PIC16F505 only) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. DS41236E-page 76 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 TABLE 10-4: CALIBRATED INTERNAL RC FREQUENCIES – PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) Param Freq Sym. Characteristic Min. Typ† Max. Units Conditions No. Tolerance F10 FOSC Internal Calibrated ± 1% 3.96 4.00 4.04 MHz VDD = 3.5V, TA = 25°C INTOSC Frequency(1) ± 2% 3.92 4.00 4.08 MHz 2.5V ≤ VDD ≤ 5.5V 0°C ≤ TA ≤ +85°C ± 5% 3.80 4.00 4.20 MHz 2.0V ≤ VDD ≤ 5.5V -40°C ≤ TA ≤ +85°C (Ind.) -40°C ≤ TA ≤ +125°C (Ext.) * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1uF and 0.01uF values in parallel are recommended. FIGURE 10-5: I/O TIMING – PIC12F508/509/16F505 Q4 Q1 Q2 Q3 OSC1 I/O Pin (input) 17 19 18 I/O Pin Old Value New Value (output) 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50pF on I/O pins and CLKOUT. © 2009 Microchip Technology Inc. DS41236E-page 77

PIC12F508/509/16F505 TABLE 10-5: TIMING REQUIREMENTS – PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) AC Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) CHARACTERISTICS -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section10.1"Power-on Reset (POR)" Param Sym. Characteristic Min. Typ(1) Max. Units No. 17 TOSH2IOV OSC1↑ (Q1 cycle) to Port Out Valid(2), (3) — — 100* ns 18 TOSH2IOI OSC1↑ (Q2 cycle) to Port Input Invalid (I/O in hold time)(2) 50 — — ns 19 TIOV2OSH Port Input Valid to OSC1↑ (I/O in setup time) 20 — — ns 20 TIOR Port Output Rise Time(3) — 10 25** ns 21 TIOF Port Output Fall Time(3) — 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure10-3 for loading conditions. FIGURE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING – PIC12F508/509/16F505 VDD MCLR 30 Internal POR 32 32 32 DRT Timeout(2) Internal Reset Watchdog Timer Reset 31 34 34 I/O pin(1) Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT Reset only in XT, LP and HS (PIC16F505) modes. DS41236E-page 78 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 TABLE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Param Sym. Characteristic Min. Typ(1) Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2000* — — ns VDD = 5.0V 31 TWDT Watchdog Timer Time-out Period 9* 18* 30* ms VDD = 5.0V (Industrial) (no prescaler) 9* 18* 40* ms VDD = 5.0V (Extended) 32 TDRT Device Reset Timer Period(2) 9* 18* 30* ms VDD = 5.0V (Industrial) 9* 18* 40* ms VDD = 5.0V (Extended) 34 TIOZ I/O High-impedance from MCLR — — 2000* ns low * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. DS41236E-page 79

PIC12F508/509/16F505 FIGURE 10-7: TIMER0 CLOCK TIMINGS – PIC12F508/509/16F505 T0CKI 40 41 42 TABLE 10-7: TIMER0 CLOCK REQUIREMENTS – PIC12F508/509/16F505 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) AC CHARACTERISTICS -40°C ≤ TA ≤ +125°C (extended) Operating Voltage VDD range is described in Section10.1"Power-on Reset (POR)" Param Sym. Characteristic Min. Typ(1) Max. Units Conditions No. 40 Tt0H T0CKI High Pulse No Prescaler 0.5 TCY + 20* — — ns Width With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse No Prescaler 0.5 TCY + 20* — — ns Width With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* N — — ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41236E-page 80 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 11.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean+3σ) or (mean - 3σ) respectively, where s is a standard deviation, over each temperature range. FIGURE 11-1: IDD vs. VDD at FOSC = 4 MHz 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst-Case Temp) + 3σ Maximum (-40°C to 125°C) 1,000 4 MHz 800 A) Typical μ (D ID 600 4 MHz 400 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2009 Microchip Technology Inc. DS41236E-page 81

PIC12F508/509/16F505 FIGURE 11-2: IDD VS. FOSC Over VDD (HS MODE, PIC16F505 only) 3.00 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 2.50 (-40°C to 125°C) Max. 5V 2.00 A) Typical 5V m 1.50 (D D I 1.00 Max. 3V 0.50 Typical 3V 0.00 5 10 15 20 25 Fosc (MHz) FIGURE 11-3: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.35 0.30 A) 0.25 μ (D P 0.20 I 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41236E-page 82 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 FIGURE 11-4: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 Typical: Statistical Mean @25°C 16.0 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 14.0 Max. 125°C 12.0 A) 10.0 μ (D P 8.0 I 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 11-5: TYPICAL WDT IPD vs. VDD 9 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 7 (-40°C to 125°C) 6 A) 5 μ (D P 4 I 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2009 Microchip Technology Inc. DS41236E-page 83

PIC12F508/509/16F505 FIGURE 11-6: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 20.0 Max. 125°C 15.0 A) μ (D P I 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 11-7: WDT TIME-OUT or DEVICE RESET TIMER vs. VDD OVER TEMPERATURE (NO WDT PRESCALER)(1) 50 Typical: Statistical Mean @25°C 45 Max. 125°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 40 Max. 85°C 35 30 ms) Typical. 25°C e ( 25 m Ti 20 Min. -40°C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Note 1: Device Reset Timer (DRT) values are for case of Reset of power-up. Table7-6 shows DRT values for the case of other types of Reset events. DS41236E-page 84 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 FIGURE 11-8: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. 125°C 0.6 0.5 Max. 85°C V) (L 0.4 O V 0.3 Typical 25°C 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 11-9: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C 0.40 MaximTuympi:c aMl:e Santa (tiWstoicraslt -MCeaasne @Te2m5p×)C + 3σ Maximum: Mea s( -+4 03×C to 125×C) (-40°C to 125°C) Max. 125°C 0.35 Max. 85°C 0.30 0.25 V) (L Typ. 25°C O V 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) © 2009 Microchip Technology Inc. DS41236E-page 85

PIC12F508/509/16F505 FIGURE 11-10: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C 2.0 V) (H O V 1.5 Typical: Statistical Mean @25°C 1.0 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 11-11: VOH vs. IOH OVER TE(MPERAT, URE (VDD = 5).0V) 5.5 5.0 Max. -40°C Typ. 25°C 4.5 V) Min. 125°C (H O V 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) DS41236E-page 86 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 FIGURE 11-12: TTL INPUT THRESHOLD VIN vs. VDD (TTL Input, -40×C TO 125×C) 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. -40°C 1.3 Typ. 25°C V) (N 1.1 VI Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 11-13: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) VIH Min. -40°C 3.0 2.5 V) (N VI 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2009 Microchip Technology Inc. DS41236E-page 87

PIC12F508/509/16F505 FIGURE 11-14: TYPICAL INTOSC FREQUENCY CHANGE vs VDD (25°C) 55 44 33 %) 22 n ( atio 11 r b Cali 00 m o e fr -1-1 g n a h -2-2 C -3-3 -4-4 -5-5 22 22..55 33 33..55 44 44..55 55 55..55 VDD (V) FIGURE 11-15: TYPICAL INTOSC FREQUENCY CHANGE vs VDD (-40°C) 55 44 33 %) 22 n ( atio 11 r b ali 00 C m o e fr -1-1 g n a h -2-2 C -3-3 -4-4 -5-5 22 22..55 33 33..55 44 44..55 55 55..55 VDD (V) DS41236E-page 88 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 FIGURE 11-16: TYPICAL INTOSC FREQUENCY CHANGE vs VDD (85°C) 55 44 33 %) 22 n ( atio 11 r b Cali 00 m o e fr -1-1 g n a h -2-2 C -3-3 -4-4 -5-5 22 22..55 33 33..55 44 44..55 55 55..55 VDD (V) FIGURE 11-17: TYPICAL INTOSC FREQUENCY CHANGE vs VDD (125°C 55 44 33 %) 22 n ( atio 11 r b ali 00 C m o e fr -1-1 g n a h -2-2 C -3-3 -4-4 -5-5 22 22..55 33 33..55 44 44..55 55 55..55 VDD (V) © 2009 Microchip Technology Inc. DS41236E-page 89

PIC12F508/509/16F505 NOTES: DS41236E-page 90 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 12.0 PACKAGING INFORMATION 12.1 Package Marking Information 8-Lead PDIP Example XXXXXXXX 12F508-I XXXXXNNN /P e 3 017 YYWW 0610 8-Lead SOIC (3.90 mm) Example XXXXXXXX 12F509-I XXXXYYWW /SN e 3 0610 NNN 017 8-Lead MSOP Example XXXXXX 12F509 YWWNNN 0610017 8-Lead 2x3 DFN* Example X X X B E Q Y W W 6 1 0 N N 1 7 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2009 Microchip Technology Inc. DS41236E-page 91

PIC12F508/509/16F505 12.1 Package Marking Information (Continued) 14-Lead PDIP (300 mil) Example XXXXXXXXXXXXXX PIC16F505 XXXXXXXXXXXXXX -I/P e3 0215 YYWWNNN 0610017 14-Lead SOIC (3.90 mm) Example XXXXXXXXXXX PIC16F505-E XXXXXXXXXXX /SL0125 YYWWNNN 0610017 14-Lead TSSOP (4.4 mm) Example XXXXXXXX 16F505-I YYWW 0610 NNN 017 16-Lead QFN Example XXXXXXX 16F505 XXXXXXX -I/MG YYWWNNN 0610017 TABLE 12-1: 8-LEAD 2X3 DFN (MC) TOP MARKING Part Number Marking PIC12F508 (T) - I/MC BN0 PIC12F508-E/MC BP0 PIC12F509 (T) - I/MC BQ0 PIC12F509-E/MC BR0 DS41236E-page 92 © 2009 Microchip Technology Inc.

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(cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)-(cid:23)< (cid:20)-?(cid:29) (cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2(cid:2)1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)<1 © 2009 Microchip Technology Inc. DS41236E-page 93

PIC12F508/509/16F505 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D e N E E1 NOTE1 1 2 3 α b h h c A A2 φ A1 L L1 β 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:5)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)(cid:3)(cid:29) = = (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2)+ (cid:25)(cid:30) (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)(cid:3)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) -(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:23)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), ,(cid:11)(cid:28)’%(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)(cid:29) = (cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) = (cid:30)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:23)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:30)(cid:5) = (cid:4)(cid:20)(cid:3)(cid:29) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:30) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:29)B = (cid:30)(cid:29)B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:29)B = (cid:30)(cid:29)B (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:5)1 DS41236E-page 94 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2009 Microchip Technology Inc. DS41236E-page 95

PIC12F508/509/16F505 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)((cid:13)(cid:14)"(cid:26)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:9)(cid:6)(cid:14))(cid:6)*(cid:5)(cid:8)(cid:19)( (cid:20)(cid:8)(cid:28)( !(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 e b c φ A A2 A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)<(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:23)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) -(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) -(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)<(cid:4) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:4)(cid:20)(cid:24)(cid:29)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)< = (cid:4)(cid:20)(cid:3)- 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)(cid:23)(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:30)(cid:30)1 DS41236E-page 96 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)+(cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14))(cid:6)*(cid:5)(cid:8)(cid:19)(’(cid:20)(cid:8)(cid:21)(cid:8),-(cid:22)-(cid:23)%&(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:15)+(cid:30)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D e b N N L K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A NOTE2 A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:29)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . -(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) (cid:30)(cid:20)-(cid:4) = (cid:30)(cid:20)(cid:29)(cid:29) .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) (cid:30)(cid:20)(cid:29)(cid:4) = (cid:30)(cid:20)(cid:5)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:4) (cid:4)(cid:20)(cid:3)(cid:29) (cid:4)(cid:20)-(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:29)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# C (cid:4)(cid:20)(cid:3)(cid:4) = = (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2)(cid:11)(cid:28) (cid:14)(cid:2)(cid:10)(cid:15)(cid:14)(cid:2)(cid:10)(cid:9)(cid:2)’(cid:10)(cid:9)(cid:14)(cid:2)(cid:14)$(cid:12)(cid:10)!(cid:14)#(cid:2)&(cid:7)(cid:14)(cid:2))(cid:28)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:14)(cid:15)#!(cid:20) -(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:3)-, © 2009 Microchip Technology Inc. DS41236E-page 97

PIC12F508/509/16F505 ./(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:18)(cid:3)(cid:4)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)(cid:9)(cid:20)(cid:8)(cid:21)(cid:8)(cid:22)(cid:23)(cid:23)(cid:8)(cid:24)(cid:13)(cid:10)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:9)(cid:15)(cid:17)(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:30)(cid:23) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)(cid:5)-(cid:29) (cid:20)(cid:5)(cid:29)(cid:4) (cid:20)(cid:5)(cid:5)(cid:29) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:29) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2(cid:2)1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:4)(cid:29)1 DS41236E-page 98 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 ./(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:4)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 3 e h b α h φ c A A2 A1 L β L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:30)(cid:23) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:5)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)(cid:3)(cid:29) = = (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2)+ (cid:25)(cid:30) (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)(cid:3)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) -(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) <(cid:20)?(cid:29)(cid:2)1(cid:22), ,(cid:11)(cid:28)’%(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)(cid:29) = (cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) = (cid:30)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:23)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:30)(cid:5) = (cid:4)(cid:20)(cid:3)(cid:29) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:30) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:29)B = (cid:30)(cid:29)B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:29)B = (cid:30)(cid:29)B (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)?(cid:29)1 © 2009 Microchip Technology Inc. DS41236E-page 99

PIC12F508/509/16F505 ./(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)01(cid:13)(cid:18)(cid:8) 1"(cid:13)(cid:18))(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) 0(cid:20)(cid:8)(cid:21)(cid:8)/%/(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)0 !(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 e b c φ A A2 A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:30)(cid:23) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)<(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:23)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:23)(cid:20)-(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:23)(cid:20)(cid:24)(cid:4) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)(cid:30)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:30)(cid:24) = (cid:4)(cid:20)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)<(cid:5)1 DS41236E-page 100 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009 Microchip Technology Inc. DS41236E-page 101

PIC12F508/509/16F505 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41236E-page 102 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 APPENDIX A: REVISION HISTORY Revision A (April 2004) Original data sheet for PIC12F508/509/16F505 devices Revision B (June 2005) Update packages Revision C (03/2007) Revised Table 3-2 Legend; Revised Table 3-3 RB3 and Legend; Revised Table 10-4 F10; Replaced Package Drawings (Rev. AN); Added DFN package; Replaced Development Support Section; Revised Product ID System. Revision D (12/2007) Revised Title; Operating Current; Table 1-1 added DFN and revised note; Revised Section 3.0, last paragraph; Revised Figure 4-4; Revised Table 4-2 (FSR); Revised Register 7-1 and Register 7-2; Revised Section 7.2.2; Revised Table 7-3, Note 2; Revised Table 7-4 (FSR) and Note 2; Deleted Section 7.3.1: External Clock In and Figure 7-6; Revised new Section 7.3.1; Replaced TBD with new data in Tables 10-4 and 10-5; Revised Tables 10-1 (Industrial), 10-2 (Extended), and Tables 10-1 (Industrial, Extended) and 10-2 (Pull-up Resistor Ranges), 10-3, 10-4 and 10-6; Revised Figure 10-1, Figure 10-2; Section 11.0, Added Char data; Revised Package Marking Information; Revised Product ID System. Revision E (08/2009) Added PIC16F505 16-Pin diagram (QFN); Added Note after subsection 5.2 PORTC; Updated Note 4 and deleted Note 5, Table 10-1; Deleted Param. No. D061 (Table 10-1) and Param. No. D061A becomes D061; Added QFN Package Information; Revised Product Identification System; Added Figures 11-14, 11-15, 11- 16, 11-7 to Char Data section; Other minor corrections; Removed Preliminary status. © 2009 Microchip Technology Inc. DS41236E-page 103

PIC12F508/509/16F505 NOTES: DS41236E-page 104 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 INDEX A MPLAB Integrated Development Environment Software....65 MPLAB PM3 Device Programmer......................................67 ALU.....................................................................................11 MPLAB REAL ICE In-Circuit Emulator System..................67 Assembler MPLINK Object Linker/MPLIB Object Librarian..................66 MPASM Assembler.....................................................66 O B Option Register...................................................................24 Block Diagram OSC selection.....................................................................41 On-Chip Reset Circuit.................................................50 OSCCAL Register...............................................................26 Timer0.........................................................................35 Oscillator Configurations.....................................................44 TMR0/WDT Prescaler.................................................39 Oscillator Types Watchdog Timer..........................................................53 HS...............................................................................44 Brown-Out Protection Circuit..............................................54 LP...............................................................................44 C RC..............................................................................44 C Compilers XT...............................................................................44 MPLAB C18................................................................66 P MPLAB C30................................................................66 PIC12F508/509/16F505 Device Varieties............................9 Carry...................................................................................11 PICSTART Plus Development Programmer.......................68 Clocking Scheme................................................................16 POR Code Protection............................................................41, 55 Device Reset Timer (DRT)...................................41, 52 Configuration Bits................................................................41 PD.........................................................................54, 41 Configuration Word.............................................................43 TO...............................................................................54 Customer Change Notification Service.............................107 PORTB...............................................................................31 Customer Notification Service...........................................107 Power-down Mode..............................................................55 Customer Support.............................................................107 Prescaler............................................................................38 D Program Counter................................................................27 DC and AC Characteristics.................................................81 Q Development Support.........................................................65 Q cycles..............................................................................16 Digit Carry...........................................................................11 R E RC Oscillator.......................................................................45 Errata....................................................................................6 Reader Response.............................................................108 F Read-Modify-Write..............................................................33 Family of Devices Register File Map PIC12F508/509/PIC16F505..........................................7 PIC12F508.................................................................19 FSR.....................................................................................28 PIC12F509.................................................................19 PIC16F505.................................................................19 I Registers I/O Interfacing.....................................................................31 Special Function.........................................................20 I/O Ports..............................................................................31 Reset..................................................................................41 I/O Programming Considerations........................................33 Reset on Brown-Out...........................................................54 ID Locations..................................................................41, 55 S INDF....................................................................................28 Sleep............................................................................41, 55 Indirect Data Addressing.....................................................28 Software Simulator (MPLAB SIM)......................................66 Instruction Cycle.................................................................16 Special Features of the CPU..............................................41 Instruction Flow/Pipelining..................................................16 Special Function Registers.................................................20 Instruction Set Summary.....................................................58 Stack...................................................................................27 Internet Address................................................................107 Status Register.............................................................11, 22 L T Loading of PC.....................................................................27 Timer0 M Timer0........................................................................35 Memory Organization..........................................................17 Timer0 (TMR0) Module..............................................35 Data Memory..............................................................18 TMR0 with External Clock..........................................37 Program Memory (PIC12F508/509)............................17 Timing Diagrams and Specifications..................................75 Program Memory (PIC16F505)...................................18 Timing Parameter Symbology and Load Conditions..........75 Microchip Internet Web Site..............................................107 TRIS Registers...................................................................31 MPLAB ASM30 Assembler, Linker, Librarian.....................66 MPLAB ICD 2 In-Circuit Debugger.....................................67 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator......................................................67 © 2009 Microchip Technology Inc. DS41236E-page 105

PIC12F508/509/16F505 W Wake-up from Sleep...........................................................55 Watchdog Timer (WDT)................................................41, 52 Period..........................................................................52 Programming Considerations.....................................52 WWW Address..................................................................107 WWW, On-Line Support........................................................6 Z Zero bit................................................................................11 DS41236E-page 106 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS41236E-page 107

PIC12F508/509/16F505 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC12F508/509/16F505 Literature Number: DS41236E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41236E-page 108 © 2009 Microchip Technology Inc.

PIC12F508/509/16F505 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC12F508-E/P 301 = Extended Temp., PDIP Range package, QTP pattern #301 b) PIC12F508-I/SN = Industrial Temp., SOIC package c) PIC12F508T-E/P = Extended Temp., PDIP Device: PIC16F505 package, Tape and Reel PIC12F508 PIC12F509 PIC16F505T(1) PIC12F508T(2) PIC12F509T(2) Temperature I = -40°C to +85°C (Industrial) Range: E = -40°C to +125°C (Extended) Package: MC = 8L DFN 2x3 (DUAL Flatpack No-Leads)(3, 4) MS = Micro-Small Outline Package (MSOP)(3, 4) P = Plastic (PDIP)(4) Note1: T = in tape and reel SOIC, TSSOP and SL = 14L Small Outline, 3.90 mm (SOIC)(4) QFN packages only SN = 8L Small Outline, 3.90 mm Narrow (SOIC)(4) 2: T = in tape and reel SOIC and MSOP ST = Thin Shrink Small Outline (TSSOP)(4) packages only. MG = 16L QFN (3x3x0.9)(5) 3: PIC12F508/PIC12F509 only. 4: Pb-free. 5: PIC16F505 only. Pattern: Special Requirements Note: Tape and Reel available for only the following packages: SOIC, MSOP and TSSOP. © 2009 Microchip Technology Inc. DS41236E-page 109

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16F505T-I/ST PIC16F505T-I/SL PIC16F505-I/P PIC12F508-E/SN PIC12F508-E/MS PIC12F509-I/MS PIC12F509-I/SN PIC12F508-I/P PIC12F508T-I/MS PIC12F508T-I/SN PIC12F509T-I/MS PIC12F509T-I/SN PIC12F509-I/P PIC12F508-E/P PIC12F508-I/SN PIC12F508-I/MS PIC12F509-E/MS PIC12F509-E/SN PIC16F505- I/ST PIC16F505-I/SL PIC16F505-E/P PIC16F505-E/SL PIC16F505-E/ST PIC12F508T-I/MC PIC12F509-I/MC PIC12F509-I/SM PIC12F509T-I/MC PIC12F509-E/P PIC12F509T-E/SM PIC12F509T-E/SN PIC12F508T-E/SN PIC12F509-E/SM PIC12F509T-I/SM PIC12F508-I/MC PIC12F508-E/MC PIC12F509-E/MC PIC16F505-E/MG PIC16F505-I/MG PIC16F505T-I/MG