PIC16(L)F1938/9 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver High-Performance RISC CPU: PIC16LF193X Low-Power Features: • Only 49 Instructions to Learn: • Standby Current: - All single-cycle instructions except branches - 60nA @ 1.8V, typical • Operating Speed: • Operating Current: - DC – 32MHz oscillator/clock input - 43A/MHz @ 1.8V, typical - DC – 125ns instruction cycle • Timer1 Oscillator Current: • Up to 16K x 14 Words of Flash Program Memory - 600 nA @ 32 kHz, 1.8V, typical • Up to 1024 Bytes of Data Memory (RAM) • Low-Power Watchdog Timer Current: • Interrupt Capability with automatic context saving - 500 nA @ 1.8V, typical • 16-Level Deep Hardware Stack Peripheral Features: • Direct, Indirect and Relative Addressing modes • Processor Read Access to Program Memory • Up to 35 I/O Pins and 1 Input-only pin: • Pinout Compatible to other 28/40-pin PIC16CXXX - High-current source/sink for direct LED drive and PIC16FXXX Microcontrollers - Individually programmable Interrupt-on-pin change pins Special Microcontroller Features: - Individually programmable weak pull-ups • Precision Internal Oscillator: • Integrated LCD Controller: - Factory calibrated to ±1%, typical - Up to 96 segments - Software selectable frequency range from - Variable clock input 32MHz to 31kHz - Contrast control • Power-Saving Sleep mode - Internal voltage reference selections • Power-on Reset (POR) • Capacitive Sensing module (mTouchTM): • Power-up Timer (PWRT) and Oscillator Start-up - Up to 16 selectable channels Timer (OST) • A/D Converter: • Brown-out Reset (BOR): - 10-bit resolution and up to 14 channels - Selectable between two trip points - Selectable 1.024/2.048/4.096V voltage - Disable in Sleep option reference • Multiplexed Master Clear with Pull-up/Input Pin • Timer0: 8-Bit Timer/Counter with 8-Bit • Programmable Code Protection Programmable Prescaler • Wide Operating Voltage Range: • Enhanced Timer1: - 1.8V-5.5V (PIC16F193X) - Dedicated low-power 32 kHz oscillator driver - 1.8V-3.6V (PIC16LF193X) - 16-bit timer/counter with prescaler - External Gate Input mode with toggle and single-shot modes - Interrupt-on-gate completion • Timer2, 4, 6: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler • Two Capture, Compare, PWM Modules (CCP): - 16-bit Capture, max. resolution 125ns - 16-bit Compare, max. resolution 125ns - 10-bit PWM, max. frequency 31.25kHz • Three Enhanced Capture, Compare, PWM modules (ECCP): - 3 PWM time-base options - Auto-shutdown and auto-restart - PWM steering - Programmable Dead-band Delay  2011-2013 Microchip Technology Inc. DS40001574C-page 1

PIC16(L)F1938/9 Peripheral Features (Continued): • 2 Comparators: - Rail-to-rail inputs/outputs • Master Synchronous Serial Port (MSSP) with SPI - Power mode control and I 2 CTM with: - Software enable hysteresis - 7-bit address masking • Voltage Reference module: - SMBus/PMBusTM compatibility - Fixed Voltage Reference (FVR) with 1.024V, - Auto-wake-up on start 2.048V and 4.096V output levels • Enhanced Universal Synchronous Asynchronous - 5-bit rail-to-rail resistive DAC with positive Receiver Transmitter (EUSART): and negative reference selection - RS-232, RS-485 and LIN compatible - Auto-Baud Detect • SR Latch (555 Timer): - Multiple Set/Reset input options - Emulates 555 Timer applications PIC16(L)F193X/194X FAMILY TYPES Device Data Sheet Index Program MemoryFlash (words) Data EEPROM(bytes) Data SRAM(bytes) (2)I/O’s 10-bit ADC (ch) Cap Sense (ch) Comparators Timers(8/16-bit) EUSART 2MSSP (IC™/SPI) ECCP CCP CD (Com/Seg/Total) (1)Debug XLP L PIC16(L)F1933 (1) 4096 256 256 25 11 8 2 4/1 1 1 3 2 4/16/60(3) I/H/E Y PIC16(L)F1934 (2) 4096 256 256 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H/E Y PIC16(L)F1936 (2) 8192 256 512 25 11 8 2 4/1 1 1 3 2 4/16/60(3) I/H/E Y PIC16(L)F1937 (2) 8192 256 512 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H/E Y PIC16(L)F1938 (3) 16384 256 1024 25 11 8 2 4/1 1 1 3 2 4/16/60(3) I/H/E Y PIC16(L)F1939 (3) 16384 256 1024 36 14 16 2 4/1 1 1 3 2 4/24/96 I/H/E Y PIC16(L)F1946 (4) 8192 256 512 54 17 17 3 4/1 2 2 3 2 4/46/184 I Y PIC16(L)F1947 (4) 16384 256 1024 54 17 17 3 4/1 2 2 3 2 4/46/184 I Y Note 1: Debugging Methods: (I) – Integrated On-Chip; (H) – using Debug Header; (E) – using Emulation Header. 2: One pin is input-only. 3: COM3 and SEG15 share the same physical pin, therefore SEG15 is not available when using 1/4 multiplex displays. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS41575 PIC16(L)F1933 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers. 2: DS41364 PIC16(L)F1934/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers. 3: DS41574 PIC16(L)F1938/9 Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers. 4: DS41414 PIC16(L)F1946/1947 Data Sheet, 64-Pin Flash, 8-bit Microcontrollers. Note: For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. DS40001574C-page 2  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 PIN DIAGRAMS Pin Diagram – 28-Pin SPDIP/SOIC/SSOP VPP/MCLR/RE3 1 28 RB7/ICSPDAT/ICDDAT RA0 2 27 RB6/ICSPCLK/ICDCLK RA1 3 26 RB5 RA2 4 25 RB4 RA3 5 24 RB3 RRRVAAAS457S 6789 PIC16F1938 PIC16LF1938 22220312 RRRVDBBBD210 RA6 10 19 VSS RC0 11 18 RC7 RC1 12 17 RC6 RC2 13 16 RC5 RC3 14 15 RC4 Pin Diagram – 28-Pin QFN/UQFN TK AL DC DD CC PP T/IK/I VAL R/DC LPP CSS MCC 1 0 3/7/I6/I54 A A EBBBB R R RRRRR 8765432 2222222 RA2 1 21 RB3 RA3 2 20 RB2 RA4 3 PIC16F1938 19 RB1 RA5 4 PIC16LF1938 18 RB0 VSS 5 17 VDD RA7 6 16 VSS RA6 7 15 RC7 01234 8911111 0 1 23 456 C C CC CCC R R RR RRR Note: It is recommended that the exposed bottom pad be connected to VSS.  2011-2013 Microchip Technology Inc. DS40001574C-page 3

PIC16(L)F1938/9 Pin Diagram – 40-Pin PDIP VPP/MCLR/RE3 1 40 RB7/ICSPDAT/ICDDAT RA0 2 39 RB6/ICSPCLK/ICDCLK RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 7 34 RB1 RE0 8 33 RB0 RRVVEEDSD12S 9111102 PIC16F1939PIC16LF1939 33322109 VVRRDSDDSD76 RA7 13 28 RD5 RA6 14 27 RD4 RC0 15 26 RC7 RC1 16 25 RC6 RC2 17 24 RC5 RC3 18 23 RC4 RD0 19 22 RD3 RD1 20 21 RD2 Pin Diagram – 40-Pin UQFN 5x5 6543210321 CCCDDDDCCC RRRRRRRRRR 0987654321 4333333333 RC7 1 30 RC0 RD4 2 29 RA6 RD5 3 28 RA7 RD6 4 27 VSS RD7 5 PIC16F1939 26 VDD VSS 6 PIC16LF1939 25 RE2 VDD 7 24 RE1 RB0 8 23 RE0 RB1 9 22 RA5 RB2 10 21 RA4 1234567890 1111111112 B3B4B5B6B7E3A0A1A2A3 RRRRRRRRRR K/T/R/ LAL CDC PPM K/ICST/ICSV/PP LA CD DD CC II Note: It is recommended that the exposed bottom pad be connected to VSS. DS40001574C-page 4  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 Pin Diagram – 44-Pin QFN 8x8 65432103210 CCCDDDDCCCC RRRRRRRRRRR 43210987654 RC7 14444433333333 RA6 RD4 2 32 RA7 RD5 3 31 VSS RD6 4 30 VSS RD7 5 PIC16F1939 29 NC VSS 6 PIC16LF1939 28 VDD VDD 7 27 RE2 VDD 8 26 RE1 RB0 9 25 RE0 RB1 10 24 RA5 RB2 11 23 RA4 23456789012 11111111222 RB3NCRB4RB5RB6RB7RE3RA0RA1RA2RA3 K/T/R/ CLDACL PPM CSCS/P K/IT/IVP LA CD DD CC II Note: It is recommended that the exposed bottom pad be connected to VSS. Pin Diagram – 44-Pin TQFP 6543210321 CCCDDDDCCCC RRRRRRRRRRN 43210987654 RC7 14444433333333 NC RD4 2 32 RC0 RD5 3 31 RA6 RD6 4 30 RA7 RD7 5 PIC16F1939 29 VSS VSS 6 PIC16LF1939 28 VDD VDD 7 27 RE2 RB0 8 26 RE1 RB1 9 25 RE0 RB2 10 24 RA5 RB3 11 23 RA4 23456789012 11111111222 CC456730123 NNBBBBEAAAA RRRRRRRRR K/T/R/ CLDACL PPM K/ICST/ICSV/PP LA CD DD CC II  2011-2013 Microchip Technology Inc. DS40001574C-page 5

PIC16(L)F1938/9 TABLE 1: 28-PIN SUMMARY (PIC16F1938, PIC16LF1938) P O I/O SPDIP/SOIC/SS Pin QFN/UQFN ANSEL A/D Cap Sense Comparator SR Latch Timers CCP EUSART MSSP LCD Interrupt Pull-up Basic n 8- Pi 2 8- 2 RA0 2 27 Y AN0 — CC21O2IUNT0(-1/) SRNQ(1) — — — SS(1) SEG12 — — VCAP(2) RA1 3 28 Y AN1 — C12IN1- — — — — — SEG7 — — — RA2 4 1 Y AN2/ — C2IN+/ — — — — — COM2 — — — VREF- DACOUT RA3 5 2 Y AN3/ — C1IN+ — — — — — SEG15/ — — — VREF+ COM3 RA4 6 3 Y — CPS6 C1OUT SRQ T0CKI CCP5 — — SEG4 — — — RA5 7 4 Y AN4 CPS7 C2OUT(1) SRNQ(1) — — — SS(1) SEG5 — — VCAP(2) RA6 10 7 — — — — — — — — — SEG1 — — OSC2/ CLKOUT VCAP(2) RA7 9 6 — — — — — — — — — SEG2 — — OSC1/ CLKIN RB0 21 18 Y AN12 CPS0 — SRI — CCP4 — — SEG0 INT/ Y — IOC RB1 22 19 Y AN10 CPS1 C12IN3- — — P1C — — VLCD1 IOC Y — RB2 23 20 Y AN8 CPS2 — — — P1B — — VLCD2 IOC Y — RB3 24 21 Y AN9 CPS3 C12IN2- — — CCP2(1)/ — — VLCD3 IOC Y — P2A(1) RB4 25 22 Y AN11 CPS4 — — — P1D — — COM0 IOC Y — RB5 26 23 Y AN13 CPS5 — — T1G(1) P2B(1) — — COM1 IOC Y — CCP3(1)/ P3A(1) RB6 27 24 — — — — — — — — — SEG14 IOC Y ICSPCLK/ ICDCLK RB7 28 25 — — — — — — — — — SEG13 IOC Y ICSPDAT/ ICDDAT RC0 11 8 — — — — — T1OSO/ P2B(1) — — — — — — T1CKI RC1 12 9 — — — — — T1OSI CCP2(1)/ — — — — — — P2A(1) RC2 13 10 — — — — — — CCP1/ — — SEG3 — — — P1A RC3 14 11 — — — — — — — — SCK/SCL SEG6 — — — RC4 15 12 — — — — — T1G(1) — — SDI/SDA SEG11 — — — RC5 16 13 — — — — — — — — SDO SEG10 — — — RC6 17 14 — — — — — — CCP3(1) TX/CK — SEG9 — — — P3A(1) RC7 18 15 — — — — — — P3B RX/DT — SEG8 — — — RE3 1 26 — — — — — — — — — — — Y MCLR/VPP VDD 20 17 — — — — — — — — — — — — VDD Vss 8, 5, — — — — — — — — — — — — VSS 19 16 Note 1: Pin functions can be moved using the APFCON register. 2: PIC16F1938 devices only. DS40001574C-page 6  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 2: 40/44-PIN SUMMARY (PIC16F1939, PIC16LF1939) I/O 40-Pin PDIP 40-Pin UQFN 44-Pin TQFP 44-Pin QFN ANSEL A/D Cap Sense Comparator SR Latch Timers CCP EUSART MSSP LCD Interrupt Pull-up Basic RA0 2 17 19 19 Y AN0 — CC21O2IUNT0(-1/) SRNQ(1) — — — SS(1) SEG12 — — VCAP RA1 3 18 20 20 Y AN1 — C12IN1- — — — — — SEG7 — — — RA2 4 19 21 21 Y AN2/ — C2IN+/ — — — — — COM2 — — — VREF- DACOUT RA3 5 20 22 22 Y AN3/ — C1IN+ — — — — — SEG15 — — — VREF+ RA4 6 21 23 23 Y — CPS6 C1OUT SRQ T0CKI — — SEG4 — — — RA5 7 22 24 24 Y AN4 CPS7 C2OUT(1) SRNQ(1) — — — SS(1) SEG5 — — VCAP RA6 14 29 31 33 — — — — — — — — — SEG1 — — OSC2/ CLKOUT VCAP RA7 13 28 30 32 — — — — — — — — — SEG2 — — OSC1/ CLKIN RB0 33 8 8 9 Y AN12 CPS0 — SRI — — — — SEG0 INT/ Y — IOC RB1 34 9 9 10 Y AN10 CPS1 C12IN3- — — — — — VLCD1 IOC Y — RB2 35 10 10 11 Y AN8 CPS2 — — — — — — VLCD2 IOC Y — RB3 36 11 11 12 Y AN9 CPS3 C12IN2- — — CCP2(1)/ — — VLCD3 IOC Y — P2A(1) RB4 37 12 14 14 Y AN11 CPS4 — — — — — — COM0 IOC Y — RB5 38 13 15 15 Y AN13 CPS5 — — T1G(1) CCP3(1)/ — — COM1 IOC Y — P3A(1) RB6 39 14 16 16 — — — — — — — — — SEG14 IOC Y ICSPCLK/ ICDCLK RB7 40 15 17 17 — — — — — — — — — SEG13 IOC Y ICSPDAT/ ICDDAT RC0 15 30 32 34 — — — — — T1OSO/ P2B(1) — — — — — — T1CKI RC1 16 31 35 35 — — — — — T1OSI CCP2(1)/ — — — — — — P2A(1) RC2 17 32 36 36 — — — — — — CCP1/ — — SEG3 — — — P1A RC3 18 37 37 37 — — — — — — — — SCK/SCL SEG6 — — — RC4 23 38 42 42 — — — — — T1G(1) — — SDI/SDA SEG11 — — — RC5 24 39 43 43 — — — — — — — — SDO SEG10 — — — RC6 25 40 44 44 — — — — — — — TX/CK — SEG9 — — — RC7 26 1 1 1 — — — — — — — RX/DT — SEG8 — — — RD0 19 34 38 38 Y — CPS8 — — — — — — COM3 — — — RD1 20 35 39 39 Y — CPS9 — — — CCP4 — — — — — — RD2 21 36 40 40 Y — CPS10 — — — P2B(1) — — — — — — RD3 22 37 41 41 Y — CPS11 — — — P2C — — SEG16 — — — RD4 27 2 2 2 Y — CPS12 — — — P2D — — SEG17 — — — RD5 28 3 3 3 Y — CPS13 — — — P1B — — SEG18 — — — RD6 29 4 4 4 Y — CPS14 — — — P1C — — SEG19 — — — RD7 30 5 5 5 Y — CPS15 — — — P1D — — SEG20 — — — RE0 8 23 25 25 Y AN5 — — — — CCP3(1) — — SEG21 — — — P3A(1) RE1 9 24 26 26 Y AN6 — — — — P3B — — SEG22 — — — RE2 10 25 27 27 Y AN7 — — — — CCP5 — — SEG23 — — — RE3 1 16 18 18 — — — — — — — — — — — Y MCLR/VPP VDD 11, 7, 7, 7,8, — — — — — — — — — — — — VDD 32 26 28 28 Vss 12, 6, 6, 6,30, — — — — — — — — — — — — VSS 31 27 29 31 Note 1: Pin functions can be moved using the APFCON register.  2011-2013 Microchip Technology Inc. DS40001574C-page 7

PIC16(L)F1938/9 TABLE OF CONTENTS 1.0 Device Overview........................................................................................................................................................................11 2.0 Enhanced Mid-Range CPU........................................................................................................................................................19 3.0 Memory Organization.................................................................................................................................................................21 4.0 Device Configuration..................................................................................................................................................................53 5.0 Oscillator Module (With Fail-Safe Clock Monitor).......................................................................................................................59 6.0 Resets........................................................................................................................................................................................77 7.0 Interrupts....................................................................................................................................................................................85 8.0 Low Dropout (LDO) Voltage Regulator......................................................................................................................................99 9.0 Power-Down Mode (Sleep)......................................................................................................................................................101 10.0 Watchdog Timer (WDT)...........................................................................................................................................................103 11.0 Data EEPROM and Flash Program Memory Control...............................................................................................................107 12.0 I/O Ports...................................................................................................................................................................................121 13.0 Interrupt-On-Change................................................................................................................................................................143 14.0 Fixed Voltage Reference..........................................................................................................................................................147 15.0 Analog-to-Digital Converter (ADC) Module..............................................................................................................................151 16.0 Temperature Indicator Module.................................................................................................................................................165 17.0 Digital-to-Analog Converter (DAC) Module..............................................................................................................................167 18.0 Comparator Module..................................................................................................................................................................171 19.0 SR Latch...................................................................................................................................................................................181 20.0 Timer0 Module.........................................................................................................................................................................187 21.0 Timer1 Module with Gate Control.............................................................................................................................................191 22.0 Timer2/4/6 Modules..................................................................................................................................................................203 23.0 Capture/Compare/PWM Modules (ECCP1, ECCP2, ECCP3, CCP4, CCP5)..........................................................................207 24.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................237 25.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................289 26.0 Capacitive Sensing Module......................................................................................................................................................317 27.0 Liquid Crystal Display (LCD) Driver Module.............................................................................................................................327 28.0 In-Circuit Serial Programming™ (ICSP™)...............................................................................................................................361 29.0 Instruction Set Summary..........................................................................................................................................................365 30.0 Electrical Specifications............................................................................................................................................................379 31.0 DC and AC Characteristics Graphs and Charts.......................................................................................................................411 32.0 Development Support...............................................................................................................................................................445 33.0 Packaging Information..............................................................................................................................................................451 Appendix A: Data Sheet Revision History..........................................................................................................................................473 Appendix B: Migrating From Other PIC® Devices..............................................................................................................................473 Index..................................................................................................................................................................................................475 The Microchip Web Site.....................................................................................................................................................................483 Customer Change Notification Service..............................................................................................................................................483 Customer Support..............................................................................................................................................................................483 Reader Response..............................................................................................................................................................................484 Product Identification System.............................................................................................................................................................485 DS40001574C-page 8  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2011-2013 Microchip Technology Inc. DS40001574C-page 9

PIC16(L)F1938/9 NOTES: DS40001574C-page 10  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 1.0 DEVICE OVERVIEW The PIC16(L)F1938/9 are described within this data sheet. They are available in 28/40/44-pin packages. Figure1-1 shows a block diagram of the PIC16(L)F1938/9 devices. Table1-2 shows the pin out descriptions. Reference Table1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY 9 9 8/ 8/ 3 3 9 9 1 1 Peripheral F F 6 L 1 6 C 1 PI PIC ADC ● ● Capacitive Sensing Module ● ● Digital-to-Analog Converter (DAC) ● ● EUSART ● ● Fixed Voltage Reference (FVR) ● ● LCD ● ● SR Latch ● ● Temperature Indicator ● ● Capture/Compare/PWM Modules ECCP1 ● ● ECCP2 ● ● ECCP3 ● ● CCP4 ● ● CCP5 ● ● Comparators C1 ● ● C2 ● ● Master Synchronous Serial Ports MSSP1 ● ● Timers Timer0 ● ● Timer1 ● ● Timer2 ● ● Timer4 ● ● Timer6 ● ●  2011-2013 Microchip Technology Inc. DS40001574C-page 11

PIC16(L)F1938/9 FIGURE 1-1: PIC16(L)F1938/9 BLOCK DIAGRAM Program Flash Memory RAM EEPROM PORTA OSC2/CLKOUT Timing Generation OSC1/CLKIN CPU PORTB INTRC Oscillator Figure2-1 PORTC MCLR PORTD SR ADC PORTE Timer0 Timer1 Timer2 Timer4 Timer6 Comparators Latch 10-Bit LCD ECCP1 ECCP2 ECCP3 CCP4 CCP5 MSSP EUSART Note 1: See applicable chapters for more information on peripherals. DS40001574C-page 12  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 1-2: PIC16(L)F1938/9 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/C12IN0-/C2OUT(1)/ RA0 TTL CMOS General purpose I/O. SRNQ(1)/SS(1)/VCAP(2)/SEG12 AN0 AN — A/D Channel 0 input. C12IN0- AN — Comparator C1 or C2 negative input. C2OUT — CMOS Comparator C2 output. SRNQ — CMOS SR Latch inverting output. SS ST — Slave Select input. VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F1938/9 only). SEG12 — AN LCD Analog output. RA1/AN1/C12IN1-/SEG7 RA1 TTL CMOS General purpose I/O. AN1 AN — A/D Channel 1 input. C12IN1- AN — Comparator C1 or C2 negative input. SEG7 — AN LCD Analog output. RA2/AN2/C2IN+/VREF-/ RA2 TTL CMOS General purpose I/O. DACOUT/COM2 AN2 AN — A/D Channel 2 input. C2IN+ AN — Comparator C2 positive input. VREF- AN — A/D Negative Voltage Reference input. DACOUT — AN Voltage Reference output. COM2 — AN LCD Analog output. RA3/AN3/C1IN+/VREF+/ RA3 TTL CMOS General purpose I/O. COM3(3)/SEG15 AN3 AN — A/D Channel 3 input. C1IN+ AN — Comparator C1 positive input. VREF+ AN — A/D Voltage Reference input. COM3(3) — AN LCD Analog output. SEG15 — AN LCD Analog output. RA4/C1OUT/CPS6/T0CKI/SRQ/ RA4 TTL CMOS General purpose I/O. CCP5/SEG4 C1OUT — CMOS Comparator C1 output. CPS6 AN — Capacitive sensing input 6. T0CKI ST — Timer0 clock input. SRQ — CMOS SR Latch non-inverting output. CCP5 ST CMOS Capture/Compare/PWM5. SEG4 — AN LCD Analog output. RA5/AN4/C2OUT(1)/CPS7/ RA5 TTL CMOS General purpose I/O. SRNQ(1)/SS(1)/VCAP(2)/SEG5 AN4 AN — A/D Channel 4 input. C2OUT — CMOS Comparator C2 output. CPS7 AN — Capacitive sensing input 7. SRNQ — CMOS SR Latch inverting output. SS ST — Slave Select input. VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F1938/9 only). SEG5 — AN LCD Analog output. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels XTAL= Crystal HV = High Voltage I2C™ = Schmitt Trigger input with I2C levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F1938/9 devices only. 3: PIC16(L)F1938 devices only. 4: PORTD is available on PIC16(L)F1939 devices only. 5: RE<2:0> are available on PIC16(L)F1939 devices only.  2011-2013 Microchip Technology Inc. DS40001574C-page 13

PIC16(L)F1938/9 TABLE 1-2: PIC16(L)F1938/9 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RA6/OSC2/CLKOUT/VCAP(2)/ RA6 TTL CMOS General purpose I/O. SEG1 OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F1938/9 only). SEG1 — AN LCD Analog output. RA7/OSC1/CLKIN/SEG2 RA7 TTL CMOS General purpose I/O. OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes). CLKIN CMOS — External clock input (EC mode). SEG2 — AN LCD Analog output. RB0/AN12/CPS0/CCP4/SRI/INT/ RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. SEG0 Individually enabled pull-up. AN12 AN — A/D Channel 12 input. CPS0 AN — Capacitive sensing input 0. CCP4 ST CMOS Capture/Compare/PWM4. SRI — ST SR Latch input. INT ST — External interrupt. SEG0 — AN LCD analog output. RB1/AN10/C12IN3-/CPS1/P1C/ RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. VLCD1 Individually enabled pull-up. AN10 AN — A/D Channel 10 input. C12IN3- AN — Comparator C1 or C2 negative input. CPS1 AN — Capacitive sensing input 1. P1C — CMOS PWM output. VLCD1 AN — LCD analog input. RB2/AN8/CPS2/P1B/VLCD2 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN8 AN — A/D Channel 8 input. CPS2 AN — Capacitive sensing input 2. P1B — CMOS PWM output. VLCD2 AN — LCD analog input. RB3/AN9/C12IN2-/CPS3/ RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. CCP2(1)/P2A(1)/VLCD3 Individually enabled pull-up. AN9 AN — A/D Channel 9 input. C12IN2- AN — Comparator C1 or C2 negative input. CPS3 AN — Capacitive sensing input 3. CCP2 ST CMOS Capture/Compare/PWM2. P2A — CMOS PWM output. VLCD3 AN — LCD analog input. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels XTAL= Crystal HV = High Voltage I2C™ = Schmitt Trigger input with I2C levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F1938/9 devices only. 3: PIC16(L)F1938 devices only. 4: PORTD is available on PIC16(L)F1939 devices only. 5: RE<2:0> are available on PIC16(L)F1939 devices only. DS40001574C-page 14  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 1-2: PIC16(L)F1938/9 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RB4/AN11/CPS4/P1D/COM0 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN11 AN — A/D Channel 11 input. CPS4 AN — Capacitive sensing input 4. P1D — CMOS PWM output. COM0 — AN LCD Analog output. RB5/AN13/CPS5/P2B/CCP3(1)/ RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. P3A(1)/T1G(1)/COM1 Individually enabled pull-up. AN13 AN — A/D Channel 13 input. CPS5 AN — Capacitive sensing input 5. P2B — CMOS PWM output. CCP3 ST CMOS Capture/Compare/PWM3. P3A — CMOS PWM output. T1G ST — Timer1 Gate input. COM1 — AN LCD Analog output. RB6/ICSPCLK/ICDCLK/SEG14 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ICSPCLK ST — Serial Programming Clock. ICDCLK ST — In-Circuit Debug Clock. SEG14 — AN LCD Analog output. RB7/ICSPDAT/ICDDAT/SEG13 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ICSPDAT ST CMOS ICSP™ Data I/O. ICDDAT ST CMOS In-Circuit Data I/O. SEG13 — AN LCD Analog output. RC0/T1OSO/T1CKI/P2B(1) RC0 ST CMOS General purpose I/O. T1OSO XTAL XTAL Timer1 oscillator connection. T1CKI ST — Timer1 clock input. P2B — CMOS PWM output. RC1/T1OSI/CCP2(1)/P2A(1) RC1 ST CMOS General purpose I/O. T1OSI XTAL XTAL Timer1 oscillator connection. CCP2 ST CMOS Capture/Compare/PWM2. P2A — CMOS PWM output. RC2/CCP1/P1A/SEG3 RC2 ST CMOS General purpose I/O. CCP1 ST CMOS Capture/Compare/PWM1. P1A — CMOS PWM output. SEG3 — AN LCD Analog output. RC3/SCK/SCL/SEG6 RC3 ST CMOS General purpose I/O. SCK ST CMOS SPI clock. SCL I2C OD I2C™ clock. SEG6 — AN LCD Analog output. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels XTAL= Crystal HV = High Voltage I2C™ = Schmitt Trigger input with I2C levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F1938/9 devices only. 3: PIC16(L)F1938 devices only. 4: PORTD is available on PIC16(L)F1939 devices only. 5: RE<2:0> are available on PIC16(L)F1939 devices only.  2011-2013 Microchip Technology Inc. DS40001574C-page 15

PIC16(L)F1938/9 TABLE 1-2: PIC16(L)F1938/9 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RC4/SDI/SDA/T1G(1)/SEG11 RC4 ST CMOS General purpose I/O. SDI ST — SPI data input. SDA I2C OD I2C™ data input/output. T1G ST — Timer1 Gate input. SEG11 — AN LCD Analog output. RC5/SDO/SEG10 RC5 ST CMOS General purpose I/O. SDO — CMOS SPI data output. SEG10 — AN LCD Analog output. RC6/TX/CK/CCP3/P3A/SEG9 RC6 ST CMOS General purpose I/O. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. CCP3 ST CMOS Capture/Compare/PWM3. P3A — CMOS PWM output. SEG9 — AN LCD Analog output. RC7/RX/DT/P3B/SEG8 RC7 ST CMOS General purpose I/O. RX ST — USART asynchronous input. DT ST CMOS USART synchronous data. P3B — CMOS PWM output. SEG8 — AN LCD Analog output. RD0(4)/CPS8/COM3 RD0 ST CMOS General purpose I/O. CPS8 AN — Capacitive sensing input 8. COM3 — AN LCD analog output. RD1(4)/CPS9/CCP4 RD1 ST CMOS General purpose I/O. CPS9 AN — Capacitive sensing input 9. CCP4 ST CMOS Capture/Compare/PWM4. RD2(4)/CPS10/P2B RD2 ST CMOS General purpose I/O. CPS10 AN — Capacitive sensing input 10. P2B — CMOS PWM output. RD3(4)/CPS11/P2C/SEG16 RD3 ST CMOS General purpose I/O. CPS11 AN — Capacitive sensing input 11. P2C — CMOS PWM output. SEG16 — AN LCD analog output. RD4(4)/CPS12/P2D/SEG17 RD4 ST CMOS General purpose I/O. CPS12 AN — Capacitive sensing input 12. P2D — CMOS PWM output. SEG17 — AN LCD analog output. RD5(4)/CPS13/P1B/SEG18 RD5 ST CMOS General purpose I/O. CPS13 AN — Capacitive sensing input 13. P1D — CMOS PWM output. SEG18 — AN LCD analog output. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels XTAL= Crystal HV = High Voltage I2C™ = Schmitt Trigger input with I2C levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F1938/9 devices only. 3: PIC16(L)F1938 devices only. 4: PORTD is available on PIC16(L)F1939 devices only. 5: RE<2:0> are available on PIC16(L)F1939 devices only. DS40001574C-page 16  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 1-2: PIC16(L)F1938/9 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RD6(4)/CPS14/P1C/SEG19 RD6 ST CMOS General purpose I/O. CPS14 AN — Capacitive sensing input 14. P1C — CMOS PWM output. SEG19 — AN LCD analog output. RD7(4)/CPS15/P1D/SEG20 RD7 ST CMOS General purpose I/O. CPS15 AN — Capacitive sensing input 15. P1D — CMOS PWM output. SEG20 — AN LCD analog output. RE0(5)/AN5/P3A(1)/CCP3(1)/ RE0 ST CMOS General purpose I/O. SEG21 AN5 AN — A/D Channel 5 input. P3A — CMOS PWM output. CCP3 ST CMOS Capture/Compare/PWM3. SEG21 — AN LCD analog output. RE1(5)/AN6/P3B/SEG22 RE1 ST CMOS General purpose I/O. AN6 AN — A/D Channel 6 input. P3B — CMOS PWM output. SEG22 — AN LCD analog output. RE2(5)/AN7/CCP5/SEG23 RE2 ST CMOS General purpose I/O. AN7 AN — A/D Channel 7 input. CCP5 ST CMOS Capture/Compare/PWM5. SEG23 — AN LCD analog output. RE3/MCLR/VPP RE3 TTL — General purpose input. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels XTAL= Crystal HV = High Voltage I2C™ = Schmitt Trigger input with I2C levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F1938/9 devices only. 3: PIC16(L)F1938 devices only. 4: PORTD is available on PIC16(L)F1939 devices only. 5: RE<2:0> are available on PIC16(L)F1939 devices only.  2011-2013 Microchip Technology Inc. DS40001574C-page 17

PIC16(L)F1938/9 NOTES: DS40001574C-page 18  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. • Automatic Interrupt Context Saving • 16-level Stack with Overflow and Underflow • File Select Registers • Instruction Set 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section7.5 “Automatic Context Saving”, for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Under- flow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a soft- ware Reset. See section Section3.5 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section3.6 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section29.0 “Instruction Set Summary” for more details.  2011-2013 Microchip Technology Inc. DS40001574C-page 19

PIC16(L)F1938/9 FIGURE 2-1: CORE BLOCK DIAGRAM 15 CCCooonnnfffiiiggguuurrraaatttiiiooonnn 15 888 DDDaaatttaaa BBBuuusss PPPrrrooogggrrraaammm CCCooouuunnnttteeerrr Flash X U Program M Memory 1886 -LLLeeevvveeell lSS Sttaataccckkk RAM (((111335---bbbiiittt))) PPPrrrooogggrrraaammm BBBuuusss 111444 Program Memory 9 RAM Addr Read (PMR) AAAddddddrrr MMMUUUXXX IIInnnssstttrrruuuccctttiiiooonnn Rrreeeggg Indirect DDDiiirrreeecccttt AAAddddddrrr 777 12 Addr 12 15 FFFSSSRRR 0rr eeRggeg FFFSSSRRR1 rrReeeggg 15 SSSTTTAAATTTUUUSSS Rrreeeggg 888 333 MMMUUUXXX Power-up Timer IIInnnssstttrrruuuccctttiiiooonnn Oscillator DDDeeecccooodddeee a &&nd Start-up Timer AAALLLUUU CCCooonnntttrrrooolll Power-on OSC1/CLKIN Reset 888 TTTiiimmmiiinnnggg Watchdog OSC2/CLKOUT GGGeeennneeerrraaatttiiiooonnn Timer W reg Brown-out Reset IIInnnttteeerrrnnnaaalll OOOsssccciiillllllaaatttooorrr BBBllloooccckkk VVVDDDDDD VVVSSSSSS DS40001574C-page 20  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 3.0 MEMORY ORGANIZATION The following features are associated with access and control of program memory and data memory: These devices contain the following types of memory: • PCL and PCLATH • Program Memory • Stack - Configuration Words • Indirect Addressing - Device ID - User ID 3.1 Program Memory Organization - Flash Program Memory The enhanced mid-range core has a 15-bit program • Data Memory counter capable of addressing a 32K x 14 program - Core Registers memory space. Table3-1 shows the memory sizes - Special Function Registers implemented for the PIC16(L)F1938/9 family. Accessing - General Purpose RAM a location above these boundaries will cause a - Common RAM wrap-around within the implemented memory space. • Data EEPROM memory(1) The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure3-1). Note1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) Last Program Memory Address PIC16F1938/PIC16LF1938 16,384 3FFFh PIC16F1939/PIC16LF1939 16,384 3FFFh  2011-2013 Microchip Technology Inc. DS40001574C-page 21

PIC16(L)F1938/9 FIGURE 3-1: PROGRAM MEMORY MAP 3.1.1 READING PROGRAM MEMORY AS AND STACK FOR DATA 16 KW PARTS There are two methods of accessing constants in pro- gram memory. The first method is to use tables of RETLW instructions. The second method is to set an PC<14:0> FSR to point to the program memory. CALL, CALLW 15 RETURN, RETLW 3.1.1.1 RETLW Instruction Interrupt, RETFIE The RETLW instruction can be used to provide access Stack Level 0 to tables of constants. The recommended way to create Stack Level 1 such a table is shown in Example3-1. Stack Level 15 EXAMPLE 3-1: RETLW INSTRUCTION constants Reset Vector 0000h BRW ;Add Index in W to ;program counter to ;select data Interrupt Vector 0004h RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data 0005h RETLW DATA2 Page 0 RETLW DATA3 07FFh 0800h Page 1 my_function ;… LOTS OF CODE… 0FFFh MOVLW DATA_INDEX 1000h call constants On-chip Page 2 ;… THE CONSTANT IS IN W Program 17FFh Memory 1800h The BRW instruction makes this type of table very sim- Page 3 ple to implement. If your code must remain portable 1FFFh with previous generations of microcontrollers, then the Page 4 2000h BRW instruction is not available so the older table read method must be used. Page 7 3FFFh Rollover to Page 0 4000h Rollover to Page 7 7FFFh DS40001574C-page 22  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 3.1.1.2 Indirect Read with FSR 3.2.1 CORE REGISTERS The program memory can be accessed as data by set- The core registers contain the registers that directly ting bit 7 of the FSRxH register and reading the match- affect the basic operation of the PIC16(L)F1938/9. ing INDFx register. The MOVIW instruction will place the These registers are listed below: lower eight bits of the addressed word in the W register. • INDF0 Writes to the program memory cannot be performed via • INDF1 the INDF registers. Instructions that access the pro- gram memory via the FSR require one extra instruction • PCL cycle to complete. Example3-2 demonstrates access- • STATUS ing the program memory via an FSR. • FSR0 Low The HIGH directive will set bit<7> if a label points to a • FSR0 High location in program memory. • FSR1 Low • FSR1 High EXAMPLE 3-2: ACCESSING PROGRAM • BSR MEMORY VIA FSR • WREG constants • PCLATH RETLW DATA0 ;Index0 data • INTCON RETLW DATA1 ;Index1 data RETLW DATA2 Note: The core registers are the first 12 RETLW DATA3 addresses of every data memory bank. my_function ;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure3-2): • 12 core registers • 20 Special Function Registers (SFR) • Up to 80 bytes of General Purpose RAM (GPR) • 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section3.6 “Indirect Addressing” for more information. Data Memory uses a 12-bit address. The upper seven bits of the address define the Bank address and the lower five bits select the registers/RAM in that bank.  2011-2013 Microchip Technology Inc. DS40001574C-page 23

PIC16(L)F1938/9 3.2.1.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register3-1, contains: as ‘000u u1uu’ (where u = unchanged). • the arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, • the Reset status SWAPF and MOVWF instructions are used to alter the The STATUS register can be the destination for any STATUS register, because these instructions do not instruction, like any other register. If the STATUS affect any Status bits. For other instructions not register is the destination for an instruction that affects affecting any Status bits (Refer to Section29.0 the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”). disabled. These bits are set or cleared according to the Note1: The C and DC bits operate as Borrow device logic. Furthermore, the TO and PD bits are not and Digit Borrow out bits, respectively, in writable. Therefore, the result of an instruction with the subtraction. STATUS register as destination may be different than intended. 3.3 Register Definitions: Status REGISTER 3-1: STATUS: STATUS REGISTER U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — — — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS40001574C-page 24  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 3.3.1 SPECIAL FUNCTION REGISTER 3.3.4 DEVICE MEMORY MAPS The Special Function Registers are registers used by The memory maps for the device family are as shown the application to control the desired operation of in Table3-2. peripheral functions in the device. The registers asso- ciated with the operation of the peripherals are TABLE 3-2: MEMORY MAP TABLES described in the appropriate peripheral chapter of this data sheet. Device Banks Table No. 3.3.2 GENERAL PURPOSE RAM PIC16F1938 0-7 Table3-3 PIC16LF1938 8-15 Table3-4, Table3-7 There are up to 80bytes of GPR in each data memory bank. 16-23 Table3-5 23-31 Table3-6, Table3-9 3.3.2.1 Linear Access to GPR PIC16F1939 0-7 Table3-3 The general purpose RAM can be accessed in a PIC16LF1939 8-15 Table3-4, Table3-8 non-banked method via the FSRs. This can simplify 16-23 Table3-5 access to large memory structures. See Section3.6.2 “Linear Data Memory” for more information. 23-31 Table3-6, Table3-9 3.3.3 COMMON RAM There are 16 bytes of common RAM accessible from all banks. FIGURE 3-2: BANKED MEMORY PARTITIONING 7-bit Bank Offset Memory Region 00h Core Registers (12 bytes) 0Bh 0Ch Special Function Registers (20 bytes maximum) 1Fh 20h General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh  2011-2013 Microchip Technology Inc. DS40001574C-page 25

D TABLE 3-3: PIC16(L)F1938/9 MEMORY MAP, BANKS 0-7 P S 40 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 I 0 C 0 000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0 1 57 001h INDF1 081h INDF1 101h INDF1 181h INDF1 201h INDF1 281h INDF1 301h INDF1 381h INDF1 1 4C 002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL 6 -p 003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS ag 004h FSR0L 084h FSR0L 104h FSR0L 184h FSR0L 204h FSR0L 284h FSR0L 304h FSR0L 384h FSR0L ( e L 2 005h FSR0H 085h FSR0H 105h FSR0H 185h FSR0H 205h FSR0H 285h FSR0H 305h FSR0H 385h FSR0H 6 006h FSR1L 086h FSR1L 106h FSR1L 186h FSR1L 206h FSR1L 286h FSR1L 306h FSR1L 386h FSR1L ) F 007h FSR1H 087h FSR1H 107h FSR1H 187h FSR1H 207h FSR1H 287h FSR1H 307h FSR1H 387h FSR1H 008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR 1 009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG 9 00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH 3 00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON 8 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch — 28Ch — 30Ch — 38Ch — 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 30Dh — 38Dh — / 9 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh — 20Eh — 28Eh — 30Eh — 38Eh — 00Fh PORTD(1) 08Fh TRISD(1) 10Fh LATD(1) 18Fh ANSELD(1) 20Fh — 28Fh — 30Fh — 38Fh — 010h PORTE 090h TRISE 110h LATE(1) 190h ANSELE(1) 210h WPUE 290h — 310h — 390h — 011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSPBUF 291h CCPR1L 311h CCPR3L 391h — 012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSPADD 292h CCPR1H 312h CCPR3H 392h — 013h PIR3 093h PIE3 113h CM2CON0 193h EEDATL 213h SSPMSK 293h CCP1CON 313h CCP3CON 393h — 014h — 094h — 114h CM2CON1 194h EEDATH 214h SSPSTAT 294h PWM1CON 314h PWM3CON 394h IOCBP 015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSPCON1 295h CCP1AS 315h CCP3AS 395h IOCBN 016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSPCON2 296h PSTR1CON 316h PSTR3CON 396h IOCBF 017h TMR1H 097h WDTCON 117h FVRCON 197h — 217h SSPCON3 297h — 317h — 397h — 018h T1CON 098h OSCTUNE 118h DACCON0 198h — 218h — 298h CCPR2L 318h CCPR4L 398h — 019h T1GCON 099h OSCCON 119h DACCON1 199h RC1REG 219h — 299h CCPR2H 319h CCPR4H 399h — 01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TX1REG 21Ah — 29Ah CCP2CON 31Ah CCP4CON 39Ah — 01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh — 29Bh PWM2CON 31Bh — 39Bh — 01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch CCP2AS 31Ch CCPR5L 39Ch — 01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh PSTR2CON 31Dh CCPR5H 39Dh — 01Eh CPSCON0 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh CCPTMRS0 31Eh CCP5CON 39Eh —  2 01Fh CPSCON1 09Fh — 11Fh — 19Fh BAUDCON 21Fh — 29Fh CCPTMRS1 31Fh — 39Fh — 01 020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h 1 -2 General General General General General General General General 01 Purpose Purpose Purpose Purpose Purpose Purpose 32Fh Purpose Purpose 3 M Register Register Register Register Register Register 330h Register Register 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes ic roc 06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh h ip 070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h T Accesses Accesses Accesses Accesses Accesses Accesses Accesses ec Common RAM 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh h n 07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh o lo gy Legend: = Unimplemented data memory locations, read as ‘0’. In Note 1: Not available on PIC16(L)F1938. c .

D TABLE 3-4: PIC16(L)F1938/9 MEMORY MAP, BANKS 8-15 P S 40 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 I 0 C 01 400h INDF0 480h INDF0 500h INDF0 580h INDF0 600h INDF0 680h INDF0 700h INDF0 780h INDF0 57 401h INDF1 481h INDF1 501h INDF1 581h INDF1 601h INDF1 681h INDF1 701h INDF1 781h INDF1 1 4 C 402h PCL 482h PCL 502h PCL 582h PCL 602h PCL 682h PCL 702h PCL 782h PCL 6 -page 440043hh SFTSART0ULS 448843hh SFTSART0ULS 550043hh SFTSART0ULS 558843hh SFTSART0ULS 660034hh SFTSART0ULS 668834hh SFTSART0ULS 770034hh SFTSART0ULS 778834hh SFTSART0ULS (L 2 405h FSR0H 485h FSR0H 505h FSR0H 585h FSR0H 605h FSR0H 685h FSR0H 705h FSR0H 785h FSR0H 7 ) 406h FSR1L 486h FSR1L 506h FSR1L 586h FSR1L 606h FSR1L 686h FSR1L 706h FSR1L 786h FSR1L F 407h FSR1H 487h FSR1H 507h FSR1H 587h FSR1H 607h FSR1H 687h FSR1H 707h FSR1H 787h FSR1H 408h BSR 488h BSR 508h BSR 588h BSR 608h BSR 688h BSR 708h BSR 788h BSR 1 409h WREG 489h WREG 509h WREG 589h WREG 609h WREG 689h WREG 709h WREG 789h WREG 9 40Ah PCLATH 48Ah PCLATH 50Ah PCLATH 58Ah PCLATH 60Ah PCLATH 68Ah PCLATH 70Ah PCLATH 78Ah PCLATH 3 40Bh INTCON 48Bh INTCON 50Bh INTCON 58Bh INTCON 60Bh INTCON 68Bh INTCON 70Bh INTCON 78Bh INTCON 8 40Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch — 40Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh — /9 40Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70Eh — 78Eh — 40Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh — 78Fh — 410h — 490h — 510h — 590h — 610h — 690h — 710h — 790h — 411h — 491h — 511h — 591h — 611h — 691h — 711h — 791h 412h — 492h — 512h — 592h — 612h — 692h — 712h — 792h 413h — 493h — 513h — 593h — 613h — 693h — 713h — 793h 414h — 494h — 514h — 594h — 614h — 694h — 714h — 794h 415h TMR4 495h — 515h — 595h — 615h — 695h — 715h — 795h 416h PR4 496h — 516h — 596h — 616h — 696h — 716h — 796h 417h T4CON 497h — 517h — 597h — 617h — 697h — 717h — 797h 418h — 498h — 518h — 598h — 618h — 698h — 718h — 798h 419h — 499h — 519h — 599h — 619h — 699h — 719h — 799h 41Ah — 49Ah — 51Ah — 59Ah — 61Ah — 69Ah — 71Ah — 79Ah 41Bh — 49Bh — 51Bh — 59Bh — 61Bh — 69Bh — 71Bh — 79Bh See Table3-7 or Table3-8 41Ch TMR6 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch 41Dh PR6 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh 41Eh T6CON 49Eh — 51Eh — 59Eh — 61Eh — 69Eh — 71Eh — 79Eh  2 41Fh — 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh 01 420h 4A0h 520h 5A0h 620h General Purpose 6A0h 720h 7A0h 1-2 General General General General Register 01 Purpose Purpose Purpose Purpose 48 Bytes Unimplemented Unimplemented 3 M 8R0e gBiystteesr 8R0e gBiystteesr 8R0e gBiystteesr 8R0e gBiystteesr Unimplemented Read as ‘0’ Read as ‘0’ icroc 46Fh 4EFh 56Fh 5EFh 66Fh Read as ‘0’ 6EFh 76Fh 7EFh h ip 470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h Te Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses ch 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh n olo 47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh g y In Legend: = Unimplemented data memory locations, read as ‘0’. c .

D TABLE 3-5: PIC16(L)F1938/9 MEMORY MAP, BANKS 16-23 P S 40 BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23 I 0 C 0 800h INDF0 880h INDF0 900h INDF0 980h INDF0 A00h INDF0 A80h INDF0 B00h INDF0 B80h INDF0 1 57 801h INDF1 881h INDF1 901h INDF1 981h INDF1 A01h INDF1 A81h INDF1 B01h INDF1 B81h INDF1 1 4C 802h PCL 882h PCL 902h PCL 982h PCL A02h PCL A82h PCL B02h PCL B82h PCL 6 -p 803h STATUS 883h STATUS 903h STATUS 983h STATUS A03h STATUS A83h STATUS B03h STATUS B83h STATUS ag 804h FSR0L 884h FSR0L 904h FSR0L 984h FSR0L A04h FSR0L A84h FSR0L B04h FSR0L B84h FSR0L ( e L 2 805h FSR0H 885h FSR0H 905h FSR0H 985h FSR0H A05h FSR0H A85h FSR0H B05h FSR0H B85h FSR0H 8 806h FSR1L 886h FSR1L 906h FSR1L 986h FSR1L A06h FSR1L A86h FSR1L B06h FSR1L B86h FSR1L ) F 807h FSR1H 887h FSR1H 907h FSR1H 987h FSR1H A07h FSR1H A87h FSR1H B07h FSR1H B87h FSR1H 808h BSR 888h BSR 908h BSR 988h BSR A08h BSR A88h BSR B08h BSR B88h BSR 1 809h WREG 889h WREG 909h WREG 989h WREG A09h WREG A89h WREG B09h WREG B89h WREG 9 80Ah PCLATH 88Ah PCLATH 90Ah PCLATH 98Ah PCLATH A0Ah PCLATH A8Ah PCLATH B0Ah PCLATH B8Ah PCLATH 3 80Bh INTCON 88Bh INTCON 90Bh INTCON 98Bh INTCON A0Bh INTCON A8Bh INTCON B0Bh INTCON B8Bh INTCON 8 80Ch — 88Ch — 90Ch — 98Ch — A0Ch — A8Ch — B0Ch — B8Ch — 80Dh — 88Dh — 90Dh — 98Dh — A0Dh — A8Dh — B0Dh — B8Dh — / 9 80Eh — 88Eh — 90Eh — 98Eh — A0Eh — A8Eh — B0Eh — B8Eh — 80Fh — 88Fh — 90Fh — 98Fh — A0Fh — A8Fh — B0Fh — B8Fh — 810h — 890h — 910h — 990h — A10h — A90h — B10h — B90h — 811h — 891h — 911h — 991h — A11h — A91h — B11h — B91h — 812h — 892h — 912h — 992h — A12h — A92h — B12h — B92h — 813h — 893h — 913h — 993h — A13h — A93h — B13h — B93h — 814h — 894h — 914h — 994h — A14h — A94h — B14h — B94h — 815h — 895h — 915h — 995h — A15h — A95h — B15h — B95h — 816h — 896h — 916h — 996h — A16h — A96h — B16h — B96h — 817h — 897h — 917h — 997h — A17h — A97h — B17h — B97h — 818h — 898h — 918h — 998h — A18h — A98h — B18h — B98h — 819h — 899h — 919h — 999h — A19h — A99h — B19h — B99h — 81Ah — 89Ah — 91Ah — 99Ah — A1Ah — A9Ah — B1Ah — B9Ah — 81Bh — 89Bh — 91Bh — 99Bh — A1Bh — A9Bh — B1Bh — B9Bh — 81Ch — 89Ch — 91Ch — 99Ch — A1Ch — A9Ch — B1Ch — B9Ch — 81Dh — 89Dh — 91Dh — 99Dh — A1Dh — A9Dh — B1Dh — B9Dh — 81Eh — 89Eh — 91Eh — 99Eh — A1Eh — A9Eh — B1Eh — B9Eh —  81Fh — 89Fh — 91Fh — 99Fh — A1Fh — A9Fh — B1Fh — B9Fh — 20 820h 8A0h 920h 9A0h A20h AA0h B20h BA0h 1 1 -20 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented 13 Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ M icro 86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh ch 870h 8F0h 970h 9F0h A70h AF0h B70h BF0h ip Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses T 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh e c h 87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh n o log Legend: = Unimplemented data memory locations, read as ‘0’. y In c .

D TABLE 3-6: PIC16(L)F1938/9 MEMORY MAP, BANKS 24-31 P S 40 BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31 I 0 C 01 C00h INDF0 C80h INDF0 D00h INDF0 D80h INDF0 E00h INDF0 E80h INDF0 F00h INDF0 F80h INDF0 57 C01h INDF1 C81h INDF1 D01h INDF1 D81h INDF1 E01h INDF1 E81h INDF1 F01h INDF1 F81h INDF1 1 4 C C02h PCL C82h PCL D02h PCL D82h PCL E02h PCL E82h PCL F02h PCL F82h PCL 6 -p C03h STATUS C83h STATUS D03h STATUS D83h STATUS E03h STATUS E83h STATUS F03h STATUS F83h STATUS age C04h FSR0L C84h FSR0L D04h FSR0L D84h FSR0L E04h FSR0L E84h FSR0L F04h FSR0L F84h FSR0L (L 2 C05h FSR0H C85h FSR0H D05h FSR0H D85h FSR0H E05h FSR0H E85h FSR0H F05h FSR0H F85h FSR0H 9 ) C06h FSR1L C86h FSR1L D06h FSR1L D86h FSR1L E06h FSR1L E86h FSR1L F06h FSR1L F86h FSR1L F C07h FSR1H C87h FSR1H D07h FSR1H D87h FSR1H E07h FSR1H E87h FSR1H F07h FSR1H F87h FSR1H C08h BSR C88h BSR D08h BSR D88h BSR E08h BSR E88h BSR F08h BSR F88h BSR 1 C09h WREG C89h WREG D09h WREG D89h WREG E09h WREG E89h WREG F09h WREG F89h WREG 9 C0Ah PCLATH C8Ah PCLATH D0Ah PCLATH D8Ah PCLATH E0Ah PCLATH E8Ah PCLATH F0Ah PCLATH F8Ah PCLATH 3 C0Bh INTCON C8Bh INTCON D0Bh INTCON D8Bh INTCON E0Bh INTCON E8Bh INTCON F0Bh INTCON F8Bh INTCON 8 C0Ch — C8Ch — D0Ch — D8Ch — E0Ch — E8Ch — F0Ch — F8Ch C0Dh — C8Dh — D0Dh — D8Dh — E0Dh — E8Dh — F0Dh — F8Dh / 9 C0Eh — C8Eh — D0Eh — D8Eh — E0Eh — E8Eh — F0Eh — F8Eh C0Fh — C8Fh — D0Fh — D8Fh — E0Fh — E8Fh — F0Fh — F8Fh C10h — C90h — D10h — D90h — E10h — E90h — F10h — F90h C11h — C91h — D11h — D91h — E11h — E91h — F11h — F91h C12h — C92h — D12h — D92h — E12h — E92h — F12h — F92h C13h — C93h — D13h — D93h — E13h — E93h — F13h — F93h C14h — C94h — D14h — D94h — E14h — E94h — F14h — F94h C15h — C95h — D15h — D95h — E15h — E95h — F15h — F95h C16h — C96h — D16h — D96h — E16h — E96h — F16h — F96h C17h — C97h — D17h — D97h — E17h — E97h — F17h — F97h C18h — C98h — D18h — D98h — E18h — E98h — F18h — F98h See Table3-9 C19h — C99h — D19h — D99h — E19h — E99h — F19h — F99h C1Ah — C9Ah — D1Ah — D9Ah — E1Ah — E9Ah — F1Ah — F9Ah C1Bh — C9Bh — D1Bh — D9Bh — E1Bh — E9Bh — F1Bh — F9Bh C1Ch — C9Ch — D1Ch — D9Ch — E1Ch — E9Ch — F1Ch — F9Ch C1Dh — C9Dh — D1Dh — D9Dh — E1Dh — E9Dh — F1Dh — F9Dh C1Eh — C9Eh — D1Eh — D9Eh — E1Eh — E9Eh — F1Eh — F9Eh  2 C1Fh — C9Fh — D1Fh — D9Fh — E1Fh — E9Fh — F1Fh — F9Fh 0 C20h CA0h D20h DA0h E20h EA0h F20h FA0h 1 1 -2 0 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented 13 Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ M ic ro C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh ch C70h CF0h D70h DF0h E70h EF0h F70h FF0h ip T Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses e 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh c hn CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh o log Legend: = Unimplemented data memory locations, read as ‘0’. y In c .

PIC16(L)F1938/9 TABLE 3-7: PIC16(L)F1938 MEMORY MAP, TABLE 3-8: PIC16(L)F1939 MEMORY MAP, BANK 15 BANK 15 Bank 15 Bank 15 791h LCDCON 791h LCDCON 792h LCDPS 792h LCDPS 793h LCDREF 793h LCDREF 794h LCDCST 794h LCDCST 795h LCDRL 795h LCDRL 796h — 796h — 797h — 797h — 798h LCDSE0 798h LCDSE0 799h LCDSE1 799h LCDSE1 79Ah — 79Ah LCDSE2 79Bh — 79Bh — 79Ch — 79Ch — 79Dh — 79Dh — 79Eh — 79Eh — 79Fh — 79Fh — 7A0h LCDDATA0 7A0h LCDDATA0 7A1h LCDDATA1 7A1h LCDDATA1 7A2h — 7A2h LCDDATA2 7A3h LCDDATA3 7A3h LCDDATA3 7A4h LCDDATA4 7A4h LCDDATA4 7A5h — 7A5h LCDDATA5 7A6h LCDDATA6 7A6h LCDDATA6 7A7h LCDDATA7 7A7h LCDDATA7 7A8h LCDDATA8 7A8h — 7A9h LCDDATA9 7A9h LCDDATA9 7AAh LCDDATA10 7AAh LCDDATA10 7ABh LCDDATA11 7ABh — 7ACh — 7ACh — 7ADh — 7ADh — 7AEh — 7AEh — 7AFh — 7AFh — 7B0h — 7B0h — 7B1h — 7B1h — 7B2h — 7B2h — 7B3h — 7B3h — 7B4h — 7B4h — 7B5h — 7B5h — 7B6h — 7B6h — 7B7h — 7B7h — 7B8h 7B8h Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ 7EFh 7EFh Legend: = Unimplemented data memory locations, read Legend: = Unimplemented data memory locations, read as ‘0’. as ‘0’. DS40001574C-page 30  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 3-9: PIC16(L)F1938/9 MEMORY 3.3.5 SPECIAL FUNCTION REGISTERS MAP, BANK 31 SUMMARY Bank 31 The Special Function Register Summary for the device family are as follows: F8Ch Unimplemented Device Bank(s) Page No. Read as ‘0’ 0 32 FE3h 1 33 FE4h STATUS_SHAD 2 34 FE5h WREG_SHAD FE6h BSR_SHAD 3 35 FE7h PCLATH_SHAD 4 36 FE8h FSR0L_SHAD FE9h FSR0H_SHAD 5 37 FEAh FSR1L_SHAD PIC16(L)F1938/9 6 38 FEBh FSR1H_SHAD 7 39 FECh — FEDh STKPTR 8 40 FEEh TOSL 9-14 41 FEFh TOSH 15 42 Legend: = Unimplemented data memory locations, read as ‘0’. 16-30 44 31 45  2011-2013 Microchip Technology Inc. DS40001574C-page 31

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 0 000h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 001h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 002h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 003h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 004h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 005h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 006h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 007h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 008h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 009h(2) WREG Working Register 0000 0000 uuuu uuuu 00Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 00Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu 00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 00Fh(3) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 010h PORTE — — — — RE3 RE2(3) RE1(3) RE0(3) ---- xxxx ---- uuuu 011h PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 012h PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 0000 00-0 0000 00-0 013h PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — -000 0-0- -000 0-0- 014h — Unimplemented — — 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 0000 00-0 uuuu uu-u 019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu DONE 01Ah TMR2 Timer 2 Module Register 0000 0000 0000 0000 01Bh PR2 Timer 2 Period Register 1111 1111 1111 1111 01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000 01Dh — Unimplemented — — 01Eh CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 00-- 0000 00-- 0000 01Fh CPSCON1 — — — — CPSCH<3:0> ---- 0000 ---- 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’. DS40001574C-page 32  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 1 080h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 081h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 082h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 083h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 084h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 085h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 086h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 087h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 088h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 089h(2) WREG Working Register 0000 0000 uuuu uuuu 08Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 08Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111 08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111 08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111 08Fh(3) TRISD PORTD Data Direction Register 1111 1111 1111 1111 090h TRISE — — — — —(4) TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 ---- 1111 091h PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 092h PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 0000 00-0 0000 00-0 093h PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — -000 0-0- -000 0-0- 094h — Unimplemented — — 095h OPTION_REG WPUEN INTEDG TMROCS TMROSE PSA PS<2:0> 1111 1111 1111 1111 096h PCON STKOVF STKUNF — — RMCLR RI POR BOR 00-- 11qq qq-- qquu 097h WDTCON — — WDTPS<4:0> SWDTEN --01 0110 --01 0110 098h OSCTUNE — — TUN<5:0> --00 0000 --00 0000 099h OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 0011 1-00 0011 1-00 09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 00q0 0q0- qqqq qq0- 09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu 09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu 09Dh ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000 09Eh ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000 09Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’.  2011-2013 Microchip Technology Inc. DS40001574C-page 33

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 2 100h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 101h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 102h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 103h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 104h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 105h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 106h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 107h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 108h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 109h(2) WREG Working Register 0000 0000 uuuu uuuu 10Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 10Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu 10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu 10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu 10Fh(3) LATD PORTD Data Latch xxxx xxxx uuuu uuuu 110h LATE — — — — — LATE2(3) LATE1(3) LATE0(3) ---- -xxx ---- -uuu 111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100 112h CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 — — C1NCH<1:0> 0000 --00 0000 --00 113h CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 0000 -100 0000 -100 114h CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0 — — C2NCH<1:0> 0000 --00 0000 --00 115h CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00 116h BORCON SBOREN — — — — — — BORRDY 1--- ---q u--- ---u 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR<1:0> 0q00 0000 0q00 0000 118h DACCON0 DACEN DACLPS DACOE --- DACPSS<1:0> --- DACNSS 000- 00-0 000- 00-0 119h DACCON1 --- --- --- DACR<4:0> ---0 0000 ---0 0000 11Ah SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000 11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000 11Ch — Unimplemented — — 11Dh APFCON — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL -000 0000 -000 0000 11Eh — Unimplemented — — 11Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’. DS40001574C-page 34  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 3 180h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 181h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 182h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 183h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 184h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 185h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 186h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 187h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 188h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 189h(2) WREG Working Register 0000 0000 uuuu uuuu 18Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 18Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 18Ch ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111 18Dh ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111 18Eh — Unimplemented — — 18Fh(3) ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111 190h(3) ANSELE — — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111 191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000 192h EEADRH —(4) EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000 193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu 194h EEDATH — — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu 195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000 196h EECON2 EEPROM control register 2 0000 0000 0000 0000 197h — Unimplemented — — 198h — Unimplemented — — 199h RCREG USART Receive Data Register 0000 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRGL BRG<7:0> 0000 0000 0000 0000 19Ch SPBRGH BRG<15:8> 0000 0000 0000 0000 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’.  2011-2013 Microchip Technology Inc. DS40001574C-page 35

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 4 200h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 201h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 202h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 203h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 204h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 205h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 206h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 207h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 208h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 209h(2) WREG Working Register 0000 0000 uuuu uuuu 20Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 20Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 20Ch — Unimplemented — — 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 20Eh — Unimplemented — — 20Fh — Unimplemented — — 210h WPUE — — — — WPUE3 — — — ---- 1--- ---- 1--- 211h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSPADD ADD<7:0> 0000 0000 0000 0000 213h SSPMSK MSK<7:0> 1111 1111 1111 1111 214h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 215h SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000 216h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h — Unimplemented — — 219h — Unimplemented — — 21Ah — Unimplemented — — 21Bh — Unimplemented — — 21Ch — Unimplemented — — 21Dh — Unimplemented — — 21Eh — Unimplemented — — 21Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’. DS40001574C-page 36  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 5 280h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 281h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 282h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 283h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 284h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 285h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 286h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 287h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 288h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 289h(2) WREG Working Register 0000 0000 uuuu uuuu 28Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 28Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 28Ch — Unimplemented — — 28Dh — Unimplemented — — 28Eh — Unimplemented — — 28Fh — Unimplemented — — 290h — Unimplemented — — 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000 294h PWM1CON P1RSEN P1DC<6:0> 0000 0000 0000 0000 295h CCP1AS CCP1ASE CCP1AS2 CCP1AS1 CCP1AS0 PSS1AC<1:0> PSS1BD<1:0> 0000 0000 0000 0000 296h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001 297h — Unimplemented — — 298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu 299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu 29Ah CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 0000 0000 0000 0000 29Bh PWM2CON P2RSEN P2DC<6:0> 0000 0000 0000 0000 29Ch CCP2AS CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC<1:0> PSS2BD<1:0> 0000 0000 0000 0000 29Dh PSTR2CON — — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001 29Eh CCPTMRS0 C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000 29Fh CCPTMRS1 — — — — — — C5TSEL<1:0> ---- --00 ---- --00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’.  2011-2013 Microchip Technology Inc. DS40001574C-page 37

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 6 300h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 301h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 302h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 303h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 304h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 305h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 306h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 307h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 308h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 309h(2) WREG Working Register 0000 0000 uuuu uuuu 30Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 30Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 30Ch — Unimplemented — — 30Dh — Unimplemented — — 30Eh — Unimplemented — — 30Fh — Unimplemented — — 310h — Unimplemented — — 311h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu 312h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu 313h CCP3CON P3M<1:0> DC3B<1:0> CCP3M<1:0> 0000 0000 0000 0000 314h PWM3CON P3RSEN P3DC<6:0> 0000 0000 0000 0000 315h CCP3AS CCP3ASE CCP3AS2 CCP3AS1 CCP3AS0 PSS3AC<1:0> PSS3BD<1:0> 0000 0000 0000 0000 316h PSTR3CON — — — STR3SYNC STR3D STR3C STR3B STR3A ---0 0001 ---0 0001 317h — Unimplemented — — 318h CCPR4L Capture/Compare/PWM Register 4 (LSB) xxxx xxxx uuuu uuuu 319h CCPR4H Capture/Compare/PWM Register 4 (MSB) xxxx xxxx uuuu uuuu 31Ah CCP4CON — — DC4B<1:0> CCP4M<3:0> --00 0000 --00 0000 31Bh — Unimplemented — — 31Ch CCPR5L Capture/Compare/PWM Register 5 (LSB) xxxx xxxx uuuu uuuu 31Dh CCPR5H Capture/Compare/PWM Register 5 (MSB) xxxx xxxx uuuu uuuu 31Eh CCP5CON — — DC5B<1:0> CCP5M<3:0> --00 0000 --00 0000 31Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’. DS40001574C-page 38  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 7 380h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 381h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 382h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 383h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 384h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 385h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 386h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 387h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 388h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 389h(2) WREG Working Register 0000 0000 uuuu uuuu 38Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 38Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 38Ch — Unimplemented — — 38Dh — Unimplemented — — 38Eh — Unimplemented — — 38Fh — Unimplemented — — 390h — Unimplemented — — 391h — Unimplemented — — 392h — Unimplemented — — 393h — Unimplemented — — 394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000 395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000 396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000 397h — Unimplemented — — 398h — Unimplemented — — 399h — Unimplemented — — 39Ah — Unimplemented — — 39Bh — Unimplemented — — 39Ch — Unimplemented — — 39Dh — Unimplemented — — 39Eh — Unimplemented — — 39Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’.  2011-2013 Microchip Technology Inc. DS40001574C-page 39

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 8 400h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 401h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 402h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 403h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 404h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 405h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 406h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 407h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 408h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 409h(2) WREG Working Register 0000 0000 uuuu uuuu 40Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 40Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 40Ch — Unimplemented — — 40Dh — Unimplemented — — 40Eh — Unimplemented — — 40Fh — Unimplemented — — 410h — Unimplemented — — 411h — Unimplemented — — 412h — Unimplemented — — 413h — Unimplemented — — 414h — Unimplemented — — 415h TMR4 Timer 4 Module Register 0000 0000 0000 0000 416h PR4 Timer 4 Period Register 1111 1111 1111 1111 417h T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 -000 0000 418h — Unimplemented — — 419h — Unimplemented — — 41Ah — Unimplemented — — 41Bh — Unimplemented — — 41Ch TMR6 Timer 6 Module Register 0000 0000 0000 0000 41Dh PR6 Timer 6 Period Register 1111 1111 1111 1111 41Eh T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000 -000 0000 41Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’. DS40001574C-page 40  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Banks 9-14 x00h/ INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx x80h(2) (not a physical register) x00h/ INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx x81h(2) (not a physical register) x02h/ PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x82h(2) x03h/ STATUS — — — TO PD Z DC C ---1 1000 ---q quuu x83h(2) x04h/ FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x84h(2) x05h/ FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x85h(2) x06h/ FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x86h(2) x07h/ FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x87h(2) x08h/ BSR — — — BSR<4:0> ---0 0000 ---0 0000 x88h(2) x09h/ WREG Working Register 0000 0000 uuuu uuuu x89h(2) x0Ah/ PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 x8Ah(1),(2) x0Bh/ INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 x8Bh(2) x0Ch/ — Unimplemented — — x8Ch — x1Fh/ x9Fh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’.  2011-2013 Microchip Technology Inc. DS40001574C-page 41

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 15 780h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 781h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 782h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 783h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 784h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 785h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 786h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 787h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 788h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 789h(2) WREG Working Register 0000 0000 uuuu uuuu 78Ah(1, 2) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 78Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 78Ch — Unimplemented — — 78Dh — Unimplemented — — 78Eh — Unimplemented — — 78Fh — Unimplemented — — 790h — Unimplemented — — 791h LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 000- 0011 000- 0011 792h LCDPS WFT BIASMD LCDA WA LP<3:0> 0000 0000 0000 0000 793h LCDREF LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE — 000- 000- 000- 000- 794h LCDCST — — — — — LCDCST<2:0> ---- -000 ---- -000 795h LCDRL LRLAP<1:0> LRLBP<1:0> — LRLAT<2:0> 0000 -000 0000 -000 796h — Unimplemented — — 797h — Unimplemented — — 798h LCDSE0 SE<7:0> 0000 0000 uuuu uuuu 799h LCDSE1 SE<15:8> 0000 0000 uuuu uuuu 79Ah LCDSE2(3) SE<23:16> 0000 0000 uuuu uuuu 79Bh — Unimplemented — — 79Ch — Unimplemented — — 79Dh — Unimplemented — — 79Eh — Unimplemented — — 79Fh — Unimplemented — — 7A0h LCDDATA0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 7A1h LCDDATA1 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 7A2h LCDDATA2(3) SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 7A3h LCDDATA3 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 7A4h LCDDATA4 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 7A5h LCDDATA5(3) SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’. DS40001574C-page 42  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 15 (Continued) 7A6h LCDDATA6 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 7A7h LCDDATA7 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 7A8h LCDDATA8(3) SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 7A9h LCDDATA9 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 7AAh LCDDATA10 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 7ABh LCDDATA11(3) SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx uuuu uuuu COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 7ACh — Unimplemented — — — 7EFh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’.  2011-2013 Microchip Technology Inc. DS40001574C-page 43

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Banks 16-30 x00h/ INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx x80h(2) (not a physical register) x00h/ INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx x81h(2) (not a physical register) x02h/ PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x82h(2) x03h/ STATUS — — — TO PD Z DC C ---1 1000 ---q quuu x83h(2) x04h/ FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x84h(2) x05h/ FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x85h(2) x06h/ FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x86h(2) x07h/ FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x87h(2) x08h/ BSR — — — BSR<4:0> ---0 0000 ---0 0000 x88h(2) x09h/ WREG Working Register 0000 0000 uuuu uuuu x89h(2) x0Ah/ PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 x8Ah(1),(2) x0Bh/ INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 x8Bh(2) x0Ch/ — Unimplemented — — x8Ch — x1Fh/ x9Fh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’. DS40001574C-page 44  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 31 F80h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) F81h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) F82h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 F83h(2) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu F84h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu F85h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 F86h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu F87h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 F88h(2) BSR — — — BSR<4:0> ---0 0000 ---0 0000 F89h(2) WREG Working Register 0000 0000 uuuu uuuu F8Ah(1),(2 PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 ) F8Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 F8Ch — Unimplemented — — — FE3h FE4h STATUS_ Z_SHAD DC_SHA C_SHAD ---- -xxx ---- -uuu D SHAD FE5h WREG_ Working Register Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu SHAD FE6h BSR_ Bank Select Register Normal (Non-ICD) Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ Program Counter Latch High Register Normal (Non-ICD) Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu SHAD FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu SHAD FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu SHAD FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu SHAD FECh — Unimplemented — — FEDh STKPTR — — — Current Stack pointer ---1 1111 ---1 1111 FEEh TOSL Top of Stack Low byte xxxx xxxx uuuu uuuu FEFh TOSH — Top of Stack High byte -xxx xxxx -uuu uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 4: Unimplemented, read as ‘1’.  2011-2013 Microchip Technology Inc. DS40001574C-page 45

PIC16(L)F1938/9 3.4 PCL and PCLATH 3.4.3 COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte A computed function CALL allows programs to maintain comes from the PCL register, which is a readable and tables of functions and provide another way to execute writable register. The high byte (PC<14:8>) is not directly state machines or look-up tables. When performing a readable or writable and comes from PCLATH. On any table read using a computed function CALL, care Reset, the PC is cleared. Figure3-3 shows the five should be exercised if the table location crosses a PCL situations for the loading of the PC. memory boundary (each 256-byte block). If using the CALL instruction, the PCH<2:0> and PCL FIGURE 3-3: LOADING OF PC IN registers are loaded with the operand of the CALL DIFFERENT SITUATIONS instruction. PCH<6:3> is loaded with PCLATH<6:3>. The CALLW instruction enables computed calls by com- 14 PCH PCL 0 Instruction with PC PCL as bining PCLATH and W to form the destination address. Destination A computed CALLW is accomplished by loading the W 6 7 0 8 register with the desired address and executing CALLW. PCLATH ALU Result The PCL register is loaded with the value of W and PCH is loaded with PCLATH. 14 PCH PCL 0 3.4.4 BRANCHING PC GOTO, CALL The branching instructions add an offset to the PC. 6 4 0 11 This allows relocatable code and code that crosses PCLATH OPCODE <10:0> page boundaries. There are two forms of branching, 14 PCH PCL 0 BRW and BRA. The PC will have incremented to fetch PC CALLW the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be 6 7 0 8 crossed. PCLATH W If using BRW, load the W register with the desired 14 PCH PCL 0 unsigned address and execute BRW. The entire PC will PC BRW be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC+1+, 15 PC + W the signed value of the operand of the BRA instruction. 14 PCH PCL 0 PC BRA 15 PC + OPCODE <8:0> 3.4.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Coun- ter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being writ- ten to the PCL register. 3.4.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). DS40001574C-page 46  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 3.5 Stack 3.5.1 ACCESSING THE STACK All devices have a 16-levelx15-bit wide hardware The stack is available through the TOSH, TOSL and stack (refer to Figure3-1). The stack space is not part STKPTR registers. STKPTR is the current value of the of either program or data space. The PC is PUSHed Stack Pointer. TOSH:TOSL register pair points to the onto the stack when CALL or CALLW instructions are TOP of the stack. Both registers are read/writable. TOS executed or an interrupt causes a branch. The stack is is split into TOSH and TOSL due to the 15-bit size of the POPed in the event of a RETURN, RETLW or a RETFIE PC. To access the stack, adjust the value of STKPTR, instruction execution. PCLATH is not affected by a which will position TOSH:TOSL, then read/write to PUSH or POP operation. TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0’ (Configuration Words). This Note: Care should be taken when modifying the means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled. times, the seventeenth PUSH overwrites the value that During normal program operation, CALL, CALLW and was stored from the first PUSH. The eighteenth PUSH Interrupts will increment STKPTR while RETLW, overwrites the second PUSH (and so on). The RETURN, and RETFIE will decrement STKPTR. At any STKOVF and STKUNF flag bits will be set on an Over- time STKPTR can be inspected to see how much stack flow/Underflow, regardless of whether the Reset is is left. The STKPTR always points at the currently used enabled. place on the stack. Therefore, a CALL or CALLW will Note1: There are no instructions/mnemonics increment the STKPTR and then write the PC, and a called PUSH or POP. These are actions return will unload the PC and then decrement the STK- that occur from the execution of the PTR. CALL, CALLW, RETURN, RETLW and Reference Figure3-4 through Figure3-7 for examples RETFIE instructions or the vectoring to of accessing the stack. an interrupt address. FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 Stack Reset Disabled TOSH:TOSL 0x0F STKPTR = 0x1F (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The 0x08 empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack 0x07 Overflow/Underflow Reset is enabled, the 0x06 TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is 0x05 disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x04 0x03 0x02 0x01 0x00 Stack Reset Enabled TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F (STVREN = 1)  2011-2013 Microchip Technology Inc. DS40001574C-page 47

PIC16(L)F1938/9 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the return address will be placed in the 0x07 Program Counter and the Stack Pointer 0x06 decremented to the empty state (0x1F). 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL 0x00 Return Address STKPTR = 0x00 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an 0x0B interrupt, the stack looks like the figure on the left. A series of RETURN instructions 0x0A will repeatedly place the return addresses into the Program Counter and pop the stack. 0x09 0x08 0x07 TOSH:TOSL 0x06 Return Address STKPTR = 0x06 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address DS40001574C-page 48  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address When the stack is full, the next CALL or 0x09 Return Address an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 0x08 Return Address so the stack will wrap and overwrite the return address at 0x00. If the Stack 0x07 Return Address Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will 0x06 Return Address not be overwritten. 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address TOSH:TOSL 0x00 Return Address STKPTR = 0x10 3.5.2 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.6 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2011-2013 Microchip Technology Inc. DS40001574C-page 49

PIC16(L)F1938/9 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Reserved 0x7FFF Address Range 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS40001574C-page 50  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing Indirect Addressing 4 BSR 0 6 From Opcode 0 7 FSRxH 0 7 FSRxL 0 0 0 0 0 Bank Select Location Select Bank Select Location Select 00000 00001 00010 11111 0x00 0x7F Bank 0 Bank 1 Bank 2 Bank 31  2011-2013 Microchip Technology Inc. DS40001574C-page 51

PIC16(L)F1938/9 3.6.2 LINEAR DATA MEMORY 3.6.3 PROGRAM FLASH MEMORY The linear data memory is the region from FSR To make constant data access easier, the entire address 0x2000 to FSR address 0x29AF. This region is program Flash memory is mapped to the upper half of a virtual region that points back to the 80-byte blocks of the FSR address space. When the MSB of FSRnH is GPR memory in all the banks. set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the Unimplemented memory reads as 0x00. Use of the lower eight bits of each memory location is accessible linear data memory region allows buffers to be larger via INDF. Writing to the program Flash memory cannot than 80 bytes because incrementing the FSR beyond be accomplished via the FSR/INDF interface. All one bank will go directly to the GPR memory of the next instructions that access program Flash memory via the bank. FSR/INDF interface will require one additional The 16 bytes of common memory are not included in instruction cycle to complete. the linear data memory region. FIGURE 3-11: PROGRAM FLASH FIGURE 3-10: LINEAR DATA MEMORY MEMORY MAP MAP 7 FSRnH 0 7 FSRnL 0 7 FSRnH 0 7 FSRnL 0 1 0 0 1 Location Select 0x8000 0x0000 Location Select 0x2000 0x020 Bank 0 0x06F 0x0A0 Bank 1 Program 0x0EF Flash 0x120 Memory (low 8 Bank 2 bits) 0x16F 0xF20 Bank 30 0xFFFF 0x7FFF 0x29AF 0xF6F DS40001574C-page 52  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2011-2013 Microchip Technology Inc. DS40001574C-page 53

PIC16(L)F1938/9 4.2 Register Definitions: Configuration REGISTER 4-1: CONFIGURATION WORD 1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 FCMEN IESO CLKOUTEN BOREN<1:0> CPD bit 13 bit 8 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> bit7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit 1 = CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT 0 = CLKOUT function is enabled on RA6/CLKOUT bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR disabled bit 8 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 7 CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: RE3/MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = RE3/MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = RE3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit.. bit 5 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off. DS40001574C-page 54  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 4-1: CONFIGURATION WORD 1 (CONTINUED) bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode: CLKIN on RA7/OSC1/CLKIN 110 = ECM: External Clock, Medium-Power mode: CLKIN on RA7/OSC1/CLKIN 101 = ECL: External Clock, Low-Power mode: CLKIN on RA7/OSC1/CLKIN 100 = INTOSC oscillator: I/O function on RA7/OSC1/CLKIN 011 = EXTRC oscillator: RC function on RA7/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off.  2011-2013 Microchip Technology Inc. DS40001574C-page 55

PIC16(L)F1938/9 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1/1 R/P-1/1 U-1 R/P-1/1 R/P-1/1 R/P-1/1 LVP(1) DEBUG(3) — BORV STVREN PLLEN bit 13 bit 8 U-1 U-1 R/P-1/1 R/P-1/1 U-1 U-1 R/P-1/1 R/P-1/1 — — VCAPEN<1:0>(2) — — WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR/VPP must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(3) 1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger bit 11 Unimplemented: Read as ‘1’ bit 10 BORV: Brown-out Reset Voltage Selection bit(4) 1 = Brown-out Reset voltage (VBOR – see Table30-5), low trip point selected 0 = Brown-out Reset voltage (VBOR – see Table30-5), high trip point selected bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7-6 Unimplemented: Read as ‘1’ bit 5-4 VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits(2) 00 = VCAP functionality is enabled on RA0 01 = VCAP functionality is enabled on RA5 10 = VCAP functionality is enabled on RA6 11 = No capacitor on VCAP pin bit 3-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 16 kW Flash memory: 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 3FFFh may be modified by EECON control 01 = 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by EECON control 00 = 000h to 3FFFh write-protected, no addresses may be modified by EECON control Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. 2: Reads as ‘11’ on PIC16LF193X only. 3: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. 4: See Table30-5, VBOR parameter, for specific trip point voltages. DS40001574C-page 56  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section4.4 “Write Protection” for more information. 4.3.2 DATA EEPROM PROTECTION The entire data EEPROM is protected from external reads and writes by the CPD bit. When CPD = 0, external reads and writes of data EEPROM are inhibited. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 4.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected. 4.5 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section4.6 “Device ID and Revision ID” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF 190X Memory Programming Specification” (DS41397).  2011-2013 Microchip Technology Inc. DS40001574C-page 57

PIC16(L)F1938/9 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.7 Register Definitions: Device ID REGISTER 4-3: DEVICEID: DEVICE ID REGISTER(1) R R R R R R DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 13 bit 8 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13-5 DEV<8:0>: Device ID bits DEVICEID<13:0> DEVICE DEV<8:0> REV<4:0> PIC16F1938 10 0011 101 X XXXX PIC16F1939 10 0011 110 X XXXX PIC16LF1938 10 0100 101 X XXXX PIC16LF1939 10 0100 110 X XXXX bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision (see the table under DEV<8:0> above). Note 1: This location cannot be written. DS40001574C-page 58  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 5.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of eight FAIL-SAFE CLOCK MONITOR) clock modes. 1. ECL – External Clock Low-Power mode 5.1 Overview (0MHz to 0.5MHz) 2. ECM – External Clock Medium-Power mode The oscillator module has a wide variety of clock (0.5MHz to 4MHz) sources and selection features that allow it to be used 3. ECH – External Clock High-Power mode in a wide range of applications while maximizing perfor- (4MHz to 32MHz) mance and minimizing power consumption. Figure5-1 4. LP – 32kHz Low-Power Crystal mode illustrates a block diagram of the oscillator module. 5. XT – Medium Gain Crystal or Ceramic Resonator Clock sources can be supplied from external oscillators, Oscillator mode (up to 4 MHz) quartz crystal resonators, ceramic resonators and 6. HS – High Gain Crystal or Ceramic Resonator Resistor-Capacitor (RC) circuits. In addition, the system mode (4 MHz to 20 MHz) clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds 7. RC – External Resistor-Capacitor (RC) selectable via software. Additional clock features 8. INTOSC – Internal oscillator (31kHz to 32 MHz) include: Clock Source modes are selected by the FOSC<2:0> • Selectable system clock source between external bits in the Configuration Words. The FOSC bits or internal sources via software. determine the type of oscillator that will be used when • Two-Speed Start-up mode, which minimizes the device is first powered. latency between external oscillator start-up and The EC clock mode relies on an external logic level code execution. signal as the device clock source. The LP, XT, and HS • Fail-Safe Clock Monitor (FSCM) designed to clock modes require an external crystal or resonator to detect a failure of the external clock source (LP, be connected to the device. Each mode is optimized for XT, HS, EC or RC modes) and switch a different frequency range. The RC clock mode automatically to the internal oscillator. requires an external resistor and capacitor to set the • Oscillator Start-up Timer (OST) ensures stability oscillator frequency. of crystal oscillator sources The INTOSC internal oscillator block produces low, medium, and high frequency clock sources, designated LFINTOSC, MFINTOSC, and HFINTOSC. (see Internal Oscillator Block, Figure5-1). A wide selection of device clock frequencies may be derived from these three clock sources.  2011-2013 Microchip Technology Inc. DS40001574C-page 59

PIC16(L)F1938/9 FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM External Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL Sleep OSC1 Oscillator Timer1 FOSC<2:0> = 100 T1OSC X CPU and T1OSO U Peripherals M T1OSCEN Enable T1OSI Oscillator IRCF<3:0> Internal Oscillator 16 MHz 8 MHz Internal Oscillator 4 MHz Block 2 MHz er 1 MHz Clock HFPLL 16 MHz scal 500 kHz UX Control (HFINTOSC) ost 250 kHz M P 125 kHz FOSC<2:0> SCS<1:0> 500 kHz Source 500 kHz 62.5 kHz (MFINTOSC) 31.25 kHz Clock Source Option for other modules 31 kHz 31 kHz Source 31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules DS40001574C-page 60  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 5.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully clock source to function. Examples are: oscillator mod- static, stopping the external clock input will have the ules (EC mode), quartz crystal resonators or ceramic effect of halting the device while leaving all data intact. resonators (LP, XT and HS modes) and Resis- Upon restarting the external clock, the device will tor-Capacitor (RC) mode circuits. resume operation as if no time had elapsed. Internal clock sources are contained within the oscilla- FIGURE 5-2: EXTERNAL CLOCK (EC) tor module. The internal oscillator block has two inter- MODE OPERATION nal oscillators and a dedicated Phase Lock Loop (HFPLL) that are used to generate three internal sys- tem clock sources: the 16MHz High-Frequency Inter- Clock from OSC1/CLKIN nal Oscillator (HFINTOSC), 500 kHZ (MFINTOSC) and Ext. System the 31kHz Low-Frequency Internal Oscillator PIC® MCU (LFINTOSC). OSC2/CLKOUT The system clock can be selected between external or FOSC/4 or I/O(1) internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section5.3 Note 1: Output depends upon CLKOUTEN bit of the “Clock Switching” for additional information. Configuration Words. 5.2.1 EXTERNAL CLOCK SOURCES 5.2.1.2 LP, XT, HS Modes An external clock source can be used as the device system clock by performing one of the following The LP, XT and HS modes support the use of quartz actions: crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure5-3). The three modes select • Program the FOSC<2:0> bits in the Configuration a low, medium or high gain setting of the internal Words to select an external clock source that will inverter-amplifier to support various resonator types be used as the default system clock upon a and speed. device Reset. • Write the SCS<1:0> bits in the OSCCON register LP Oscillator mode selects the lowest gain setting of the to switch the system clock source to: internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to - Timer1 Oscillator during run-time, or drive only 32.768 kHz tuning-fork type crystals (watch - An external clock source determined by the crystals). value of the FOSC bits. XT Oscillator mode selects the intermediate gain See Section5.3 “Clock Switching”for more informa- setting of the internal inverter-amplifier. XT mode tion. current consumption is the medium of the three modes. This mode is best suited to drive resonators with a 5.2.1.1 EC Mode medium drive level specification. The External Clock (EC) mode allows an externally HS Oscillator mode selects the highest gain setting of the generated logic level signal to be the system clock internal inverter-amplifier. HS mode current consumption source. When operating in this mode, an external clock is the highest of the three modes. This mode is best source is connected to the OSC1 input. suited for resonators that require a high drive setting. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure5-2 shows the pin connections for EC Figure5-3 and Figure5-4 show typical circuits for mode. quartz crystal and ceramic resonators, respectively. EC mode has three power modes to select from through Configuration Words: • High power, 4-32MHz (FOSC = 111) • Medium power, 0.5-4MHz (FOSC = 110) • Low power, 0-0.5MHz (FOSC = 101)  2011-2013 Microchip Technology Inc. DS40001574C-page 61

PIC16(L)F1938/9 FIGURE 5-3: QUARTZ CRYSTAL FIGURE 5-4: CERAMIC RESONATOR OPERATION (LP, XT OR OPERATION HS MODE) (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN OSC1/CLKIN C1 To Internal C1 To Internal Logic Logic QCruyasrttazl RF(2) Sleep RP(3) RF(2) Sleep C2 RS(1) OSC2/CLKOUT C2 Ceramic RS(1) OSC2/CLKOUT Resonator Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 3: An additional parallel feedback resistor (RP) Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator according to type, package and operation. manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 5.2.1.3 Oscillator Start-up Timer (OST) 2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts expected for the application. 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer 3: For oscillator design assistance, reference (PWRT) has expired (if configured), or a wake-up from the following Microchip Applications Notes: Sleep. During this time, the program counter does not • AN826, “Crystal Oscillator Basics and increment and program execution is suspended. The Crystal Selection for rfPIC® and PIC® OST ensures that the oscillator circuit, using a quartz Devices” (DS00826) crystal resonator or ceramic resonator, has started and • AN849, “Basic PIC® Oscillator Design” is providing a stable system clock to the oscillator (DS00849) module. • AN943, “Practical PIC® Oscillator In order to minimize latency between external oscillator Analysis and Design” (DS00943) start-up and code execution, the Two-Speed Clock • AN949, “Making Your Oscillator Work” Start-up mode can be selected (see Section5.4 (DS00949) “Two-Speed Clock Start-up Mode”). 5.2.1.4 4X PLL The oscillator module contains a 4X PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4X PLL must fall within specifications. See the PLL Clock Timing Specifications in the applicable Electrical Specifications Chapter. The 4X PLL may be enabled for use by one of two methods: 1. Program the PLLEN bit in Configuration Words to a ‘1’. 2. Write the SPLLEN bit in the OSCCON register to a ‘1’. If the PLLEN bit in Configuration Words is programmed to a ‘1’, then the value of SPLLEN is ignored. DS40001574C-page 62  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 5.2.1.5 TIMER1 Oscillator 5.2.1.6 External RC Mode The Timer1 Oscillator is a separate crystal oscillator The external Resistor-Capacitor (RC) modes support that is associated with the Timer1 peripheral. It is opti- the use of an external RC circuit. This allows the mized for timekeeping operations with a 32.768 kHz designer maximum flexibility in frequency choice while crystal connected between the T1OSO and T1OSI keeping costs to a minimum when clock accuracy is not device pins. required. The Timer1 Oscillator can be used as an alternate sys- The RC circuit connects to OSC1. OSC2/CLKOUT is tem clock source and can be selected during run-time available for general purpose I/O or CLKOUT. The using clock switching. Refer to Section5.3 “Clock function of the OSC2/CLKOUT pin is determined by the Switching” for more information. state of the CLKOUTEN bit in Configuration Words. Figure5-6 shows the external RC mode connections. FIGURE 5-5: QUARTZ CRYSTAL OPERATION (TIMER1 FIGURE 5-6: EXTERNAL RC MODES OSCILLATOR) VDD PIC® MCU PIC® MCU REXT T1OSI OSC1/CLKIN Internal Clock C1 To Internal CEXT Logic 32.768 kHz VSS Quartz Crystal FOSC/4 or I/O(1) OSC2/CLKOUT C2 T1OSO Recommended values: 10 k  REXT  100 k, <3V 3 k  REXT  100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: Quartz crystal characteristics vary Note 1: Output depends upon CLKOUTEN bit of the according to type, package and Configuration Words. manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values 2: Always verify oscillator performance over and the operating temperature. Other factors affecting the VDD and temperature range that is the oscillator frequency are: expected for the application. • threshold voltage variation 3: For oscillator design assistance, reference • component tolerances the following Microchip Applications Notes: • packaging variations in capacitance • AN826, “Crystal Oscillator Basics and The user also needs to take into account variation due Crystal Selection for rfPIC® and PIC® to tolerance of external RC components used. Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) • TB097, “Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288)  2011-2013 Microchip Technology Inc. DS40001574C-page 63

PIC16(L)F1938/9 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.1 HFINTOSC The device may be configured to use the internal oscil- The High-Frequency Internal Oscillator (HFINTOSC) is lator block as the system clock by performing one of the a factory calibrated 16MHz internal clock source. The following actions: frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register5-3). • Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which The output of the HFINTOSC connects to a postscaler will be used as the default system clock upon a and multiplexer (see Figure5-1). One of multiple device Reset. frequencies derived from the HFINTOSC can be • Write the SCS<1:0> bits in the OSCCON register selected via software using the IRCF<3:0> bits of the to switch the system clock source to the internal OSCCON register. See Section5.2.2.7 “Internal oscillator during run-time. See Section5.3 Oscillator Clock Switch Timing” for more information. “Clock Switching”for more information. The HFINTOSC is enabled by: In INTOSC mode, OSC1/CLKIN is available for general • Configure the IRCF<3:0> bits of the OSCCON purpose I/O. OSC2/CLKOUT is available for general register for the desired HF frequency, and purpose I/O or CLKOUT. • FOSC<2:0> = 100, or The function of the OSC2/CLKOUT pin is determined • Set the System Clock Source (SCS) bits of the by the CLKOUTEN bit in Configuration Words. OSCCON register to ‘1x’. The internal oscillator block has two independent A fast startup oscillator allows internal circuits to power oscillators and a dedicated Phase-Lock Loop, HFPLL up and stabilize before switching to HFINTOSC. that can produce one of three internal system clock The High Frequency Internal Oscillator Ready bit sources. (HFIOFR) of the OSCSTAT register indicates when the 1. The HFINTOSC (High-Frequency Internal HFINTOSC is running. Oscillator) is factory calibrated and operates at The High Frequency Internal Oscillator Status Locked 16MHz. The HFINTOSC source is generated bit (HFIOFL) of the OSCSTAT register indicates when from the 500 kHz MFINTOSC source and the the HFINTOSC is running within 2% of its final value. dedicated Phase-Lock Loop, HFPLL. The frequency of the HFINTOSC can be The High Frequency Internal Oscillator Stable bit user-adjusted via software using the OSCTUNE (HFIOFS) of the OSCSTAT register indicates when the register (Register5-3). HFINTOSC is running within 0.5% of its final value. 2. The MFINTOSC (Medium-Frequency Internal 5.2.2.2 MFINTOSC Oscillator) is factory calibrated and operates at 500kHz. The frequency of the MFINTOSC can The Medium-Frequency Internal Oscillator be user-adjusted via software using the (MFINTOSC) is a factory calibrated 500kHz internal OSCTUNE register (Register5-3). clock source. The frequency of the MFINTOSC can be 3. The LFINTOSC (Low-Frequency Internal altered via software using the OSCTUNE register Oscillator) is uncalibrated and operates at (Register5-3). 31kHz. The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure5-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section5.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The MFINTOSC is enabled by: • Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running. DS40001574C-page 64  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 5.2.2.3 Internal Oscillator Frequency 5.2.2.5 Internal Oscillator Frequency Adjustment Selection The 500 kHz internal oscillator is factory calibrated. The system clock speed can be selected via software This internal oscillator can be adjusted in software by using the Internal Oscillator Frequency Select bits writing to the OSCTUNE register (Register5-3). Since IRCF<3:0> of the OSCCON register. the HFINTOSC and MFINTOSC clock sources are The output of the 16MHz HFINTOSC and 31kHz derived from the 500 kHz internal oscillator a change in LFINTOSC connects to a postscaler and multiplexer the OSCTUNE register value will apply to both. (see Figure5-1). The Internal Oscillator Frequency The default value of the OSCTUNE register is ‘0’. The Select bits IRCF<3:0> of the OSCCON register select value is a 6-bit two’s complement number. A value of the frequency output of the internal oscillators. One of 1Fh will provide an adjustment to the maximum the following frequencies can be selected via software: frequency. A value of 20h will provide an adjustment to • HFINTOSC the minimum frequency. - 32 MHz (requires 4X PLL) When the OSCTUNE register is modified, the oscillator - 16 MHz frequency will begin shifting to the new frequency. Code - 8 MHz execution continues during this shift. There is no - 4 MHz indication that the shift has occurred. - 2 MHz OSCTUNE does not affect the LFINTOSC frequency. - 1 MHz Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer - 500 kHz (Default after Reset) (PWRT), Watchdog Timer (WDT), Fail-Safe Clock - 250 kHz Monitor (FSCM) and peripherals, are not affected by the - 125 kHz change in frequency. - 62.5 kHz 5.2.2.4 LFINTOSC - 31.25 kHz • LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31kHz internal clock source. - 31 kHz The output of the LFINTOSC connects to a multiplexer Note: Following any Reset, the IRCF<3:0> bits (see Figure5-1). Select 31kHz, via software, using the of the OSCCON register are set to ‘0111’ IRCF<3:0> bits of the OSCCON register. See and the frequency selection is set to Section5.2.2.7 “Internal Oscillator Clock Switch 500kHz. The user can modify the IRCF Timing” for more information. The LFINTOSC is also bits to select a different frequency. the frequency for the Power-up Timer (PWRT), The IRCF<3:0> bits of the OSCCON register allow Watchdog Timer (WDT) and Fail-Safe Clock Monitor duplicate selections for some frequencies. These dupli- (FSCM). cate choices can offer system design trade-offs. Lower The LFINTOSC is enabled by selecting 31kHz power consumption can be obtained when changing (IRCF<3:0> bits of the OSCCON register=000) as the oscillator sources for a given frequency. Faster transi- system clock source (SCS bits of the OSCCON tion times can be obtained between frequency changes register= 1x), or when any of the following are that use the same oscillator source. enabled: • Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ Peripherals that use the LFINTOSC are: • Power-up Timer (PWRT) • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running.  2011-2013 Microchip Technology Inc. DS40001574C-page 65

PIC16(L)F1938/9 5.2.2.6 32 MHz Internal Oscillator 5.2.2.7 Internal Oscillator Clock Switch Frequency Selection Timing The Internal Oscillator Block can be used with the 4X When switching between the HFINTOSC, MFINTOSC PLL associated with the External Oscillator Block to and the LFINTOSC, the new oscillator may already be produce a 32 MHz internal system clock source. The shut down to save power (see Figure5-7). If this is the following settings are required to use the 32 MHz inter- case, there is a delay after the IRCF<3:0> bits of the nal clock source: OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will • The FOSC bits in Configuration Words must be reflect the current active status of the HFINTOSC, set to use the INTOSC source as the device sys- MFINTOSC and LFINTOSC oscillators. The sequence tem clock (FOSC<2:0> = 100). of a frequency selection is as follows: • The SCS bits in the OSCCON register must be cleared to use the clock determined by 1. IRCF<3:0> bits of the OSCCON register are FOSC<2:0> in Configuration Words modified. (SCS<1:0>=00). 2. If the new clock is shut down, a clock start-up • The IRCF bits in the OSCCON register must be delay is started. set to the 8 MHz HFINTOSC set to use 3. Clock switch circuitry waits for a falling edge of (IRCF<3:0>=1110). the current clock. • The SPLLEN bit in the OSCCON register must be 4. The current clock is held low and the clock set to enable the 4xPLL, or the PLLEN bit of the switch circuitry waits for a rising edge in the new Configuration Words must be programmed to a clock. ‘1’. 5. The new clock is now active. Note: When using the PLLEN bit of the 6. The OSCSTAT register is updated as required. Configuration Words, the 4xPLL cannot 7. Clock switch is complete. be disabled by software and the 8 MHz See Figure5-7 for more details. HFINTOSC option will no longer be available. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay The 4xPLL is not available for use with the internal before the new frequency is selected. Clock switching oscillator when the SCS bits of the OSCCON register time delays are shown in Table5-1. are set to ‘1x’. The SCS bits must be set to ‘00’ to use Start-up delay specifications are located in the the 4xPLL with the internal oscillator. oscillator tables in the applicable Electrical Specifications Chapter. DS40001574C-page 66  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ LFINTOSC (FSCM and WDT disabled) MFINTOSC HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled) MFINTOSC HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC   IRCF <3:0> 0 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> = 0  0 System Clock  2011-2013 Microchip Technology Inc. DS40001574C-page 67

PIC16(L)F1938/9 5.3 Clock Switching 5.3.3 TIMER1 OSCILLATOR The system clock source can be switched between The Timer1 oscillator is a separate crystal oscillator external and internal clock sources via software using associated with the Timer1 peripheral. It is optimized the System Clock Select (SCS) bits of the OSCCON for timekeeping operations with a 32.768 kHz crystal register. The following clock sources can be selected connected between the T1OSO and T1OSI device using the SCS bits: pins. • Default system oscillator determined by FOSC The Timer1 oscillator is enabled using the T1OSCEN bits in Configuration Words control bit in the T1CON register. See Section21.0 “Timer1 Module with Gate Control” for more • Timer1 32 kHz crystal oscillator information about the Timer1 peripheral. • Internal Oscillator Block (INTOSC) 5.3.4 TIMER1 OSCILLATOR READY 5.3.1 SYSTEM CLOCK SELECT (SCS) (T1OSCR) BIT BITS The user must ensure that the Timer1 Oscillator is The System Clock Select (SCS) bits of the OSCCON ready to be used before it is selected as a system clock register selects the system clock source that is used for source. The Timer1 Oscillator Ready (T1OSCR) bit of the CPU and peripherals. the OSCSTAT register indicates whether the Timer1 • When the SCS bits of the OSCCON register = 00, oscillator is ready to be used. After the T1OSCR bit is the system clock source is determined by value of set, the SCS bits can be configured to select the Timer1 the FOSC<2:0> bits in the Configuration Words. oscillator. • When the SCS bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscil- lator delays are shown in Table5-1. 5.3.2 OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the Timer1 oscillator. DS40001574C-page 68  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 5.4 Two-Speed Clock Start-up Mode 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode provides additional power savings by minimizing the latency between external Two-Speed Start-up mode is configured by the oscillator start-up and code execution. In applications following settings: that make heavy use of the Sleep mode, Two-Speed • IESO (of the Configuration Words) = 1; Inter- Start-up will remove the external oscillator start-up nal/External Switchover bit (Two-Speed Start-up time from the time spent awake and can reduce the mode enabled). overall power consumption of the device. This mode • SCS (of the OSCCON register) = 00. allows the application to wake-up from Sleep, perform • FOSC<2:0> bits in the Configuration Words a few instructions using the INTOSC internal oscillator configured for LP, XT or HS mode. block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up mode is entered after: Two-Speed Start-up provides benefits when the oscil- • Power-on Reset (POR) and, if enabled, after lator module is configured for LP, XT, or HS modes. Power-up Timer (PWRT) has expired, or The Oscillator Start-up Timer (OST) is enabled for • Wake-up from Sleep. these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT reg- ister is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 5-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) 31kHz Sleep/POR MFINTOSC(1) 31.25kHz-500 kHz 2 cycles HFINTOSC(1) 31.25kHz-16MHz Sleep/POR EC, RC(1) DC – 32MHz 2 cycles LFINTOSC EC, RC(1) DC – 32MHz 1 cycle of each Timer1 Oscillator Sleep/POR 32kHz-20MHz 1024 Clock Cycles (OST) LP, XT, HS(1) MFINTOSC(1) 31.25kHz-500kHz Any clock source 2s (approx.) HFINTOSC(1) 31.25kHz-16MHz Any clock source LFINTOSC(1) 31kHz 1 cycle of each Any clock source Timer1 Oscillator 32kHz 1024 Clock Cycles (OST) PLL inactive PLL active 16-32MHz 2ms (approx.) Note 1: PLL inactive.  2011-2013 Microchip Technology Inc. DS40001574C-page 69

PIC16(L)F1938/9 5.4.2 TWO-SPEED START-UP 5.4.3 CHECKING TWO-SPEED CLOCK SEQUENCE STATUS 1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCSTAT 2. Instructions begin execution by the internal register will confirm if the microcontroller is running oscillator at the frequency set in the IRCF<3:0> from the external clock source, as defined by the bits of the OSCCON register. FOSC<2:0> bits in the Configuration Words, or the internal oscillator. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. 5. OSTS is set. 6. System clock held low until the next falling edge of new clock (LP, XT or HS mode). 7. System clock is switched to external clock source. FIGURE 5-8: TWO-SPEED START-UP INTOSC TTOST OSC1 0 1 1022 1023 OSC2 Program Counter P C - N PC PC + 1 System Clock DS40001574C-page 70  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset, to continue operating should the external oscillator fail. executing a SLEEP instruction or changing the SCS bits The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bits are the Oscillator Start-up Timer (OST) has expired. The changed, the OST is restarted. While the OST is FSCM is enabled by setting the FCMEN bit in the running, the device continues to operate from the Configuration Words. The FSCM is applicable to all INTOSC selected in OSCCON. When the OST times external Oscillator modes (LP, XT, HS, EC, Timer1 out, the Fail-Safe condition is cleared after successfully Oscillator and RC). switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the FIGURE 5-9: FSCM BLOCK DIAGRAM OSFIF flag will again become set by hardware. Clock Monitor 5.5.4 RESET OR WAKE-UP FROM SLEEP Latch External S Q The FSCM is designed to detect an oscillator failure Clock after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after LFINTOSC any type of Reset. The OST is not used with the EC or Oscillator ÷ 64 R Q RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When 31 kHz 488 Hz the FSCM is enabled, the Two-Speed Start-up is also (~32 s) (~2 ms) enabled. Therefore, the device will always be executing code while the OST is operating. Sample Clock Clock Failure Note: Due to the wide range of oscillator start-up Detected times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate 5.5.1 FAIL-SAFE DETECTION amount of time, the user should check the The FSCM module detects a failed oscillator by Status bits in the OSCSTAT register to comparing the external oscillator to the FSCM sample verify the oscillator start-up and that the clock. The sample clock is generated by dividing the system clock switchover has successfully LFINTOSC by 64. See Figure5-9. Inside the fail completed. detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2011-2013 Microchip Technology Inc. DS40001574C-page 71

PIC16(L)F1938/9 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS40001574C-page 72  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 5.6 Register Definitions: Oscillator Control REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0 SPLLEN IRCF<3:0> — SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Words = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Words = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 1111 = 16MHz HF 1110 = 8MHz or 32 MHz HF (see Section5.2.2.1 “HFINTOSC”) 1101 = 4MHz HF 1100 = 2MHz HF 1011 = 1MHz HF 1010 = 500kHz HF(1) 1001 = 250kHz HF(1) 1000 = 125kHz HF(1) 0111 = 500kHz MF (default upon Reset) 0110 = 250kHz MF 0101 = 125kHz MF 0100 = 62.5kHz MF 0011 = 31.25kHz HF(1) 0010 = 31.25kHz MF 000x = 31kHz LF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words. Note 1: Duplicate frequency derived from HFINTOSC.  2011-2013 Microchip Technology Inc. DS40001574C-page 73

PIC16(L)F1938/9 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/q R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator is ready 0 = Timer1 oscillator is not ready If T1OSCEN = 0: 1 = Timer1 clock source is always ready bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Time-out Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<2:0> = 100) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS40001574C-page 74  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 = Minimum frequency • • • 111111 = 000000 = Oscillator module is running at the factory-calibrated frequency. 000001 = • • • 011110 = 011111 = Maximum frequency TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 73 OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 74 OSCTUNE — — TUN<5:0> 75 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE(1) 92 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF(1) 95 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 197 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Note 1: PIC16F1934 only. TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 54 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> 13:8 — — LVP DEBUG — BORV STVREN PLLEN CONFIG2 56 7:0 — — VCAPEN<1:0>(1) — — WRT<1:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Note 1: PIC16F193X only.  2011-2013 Microchip Technology Inc. DS40001574C-page 75

PIC16(L)F1938/9 NOTES: DS40001574C-page 76  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 6.0 RESETS There are multiple ways to reset this device: • Power-on Reset (POR) • Brown-out Reset (BOR) • MCLR Reset • WDT Reset • RESET instruction • Stack Overflow • Stack Underflow • Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure6-1. FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Stack Overflow/Underflow Reset Pointer External Reset MCLRE MCLR Sleep WDT Time-out Device Power-on Reset Reset VDD Brown-out Reset BOR Enable PWRT Zero 64 ms LFINTOSC PWRTEN  2011-2013 Microchip Technology Inc. DS40001574C-page 77

PIC16(L)F1938/9 6.1 Power-on Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when VDD reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for performance may require greater than minimum VDD. execution protection can be implemented. The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in Configu- conditions have been met. ration Words. The four operating modes are: 6.1.1 POWER-UP TIMER (PWRT) • BOR is always on • BOR is off when in Sleep The Power-up Timer provides a nominal 64ms time- out on POR or Brown-out Reset. • BOR is controlled by software • BOR is always off The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to Refer to Table6-3 for more information. rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by enabled by clearing the PWRTE bit in Configuration configuring the BORV bit in Configuration Words. Words. A VDD noise rejection filter prevents the BOR from trig- The Power-up Timer starts after the release of the POR gering on small events. If VDD falls below VBOR for a and BOR. duration greater than parameter TBORDC, the device For additional information, refer to Application Note will reset. See Figure6-2 for more information. AN607, “Power-up Trouble Shooting” (DS00607). TABLE 6-1: BOR OPERATING MODES Device Device Operation upon BOREN<1:0> SBOREN Device Mode BOR Mode Operation upon wake- up from release of POR Sleep 11 X X Active Waits for BOR ready(1) Awake Active 10 X Waits for BOR ready Sleep Disabled 1 Active Begins immediately 01 X 0 Disabled Begins immediately 00 X X Disabled Begins immediately Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. 6.2.1 BOR IS ALWAYS ON BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. When the BOREN bits of Configuration Words are pro- grammed to ‘11’, the BOR is always on. The device 6.2.3 BOR CONTROLLED BY SOFTWARE start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. When the BOREN bits of Configuration Words are pro- grammed to ‘01’, the BOR is controlled by the BOR protection is active during Sleep. The BOR does SBOREN bit of the BORCON register. The device start- not delay wake-up from Sleep. up is not delayed by the BOR ready condition or the 6.2.2 BOR IS OFF IN SLEEP VDD level. BOR protection begins as soon as the BOR circuit is When the BOREN bits of Configuration Words are pro- ready. The status of the BOR circuit is reflected in the grammed to ‘10’, the BOR is on, except in Sleep. The BORRDY bit of the BORCON register. device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is unchanged by Sleep. DS40001574C-page 78  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal < TPWRT Reset TPWRT(1) VDD VBOR Internal Reset TPWRT(1) Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’. 6.3 Register Definitions: BOR Control REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN — — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Words  01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive  2011-2013 Microchip Technology Inc. DS40001574C-page 79

PIC16(L)F1938/9 6.4 MCLR 6.8 Programming Mode Exit The MCLR is an optional external input that can reset Upon exit of Programming mode, the device will the device. The MCLR function is controlled by the behave as if a POR had just occurred. MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table6-2). 6.9 Power-Up Timer The Power-up Timer optionally delays device execution TABLE 6-2: MCLR CONFIGURATION after a BOR or POR event. This timer is typically used to MCLRE LVP MCLR allow VDD to stabilize before allowing the device to start running. 0 0 Disabled The Power-up Timer is controlled by the PWRTE bit of 1 0 Enabled Configuration Words. x 1 Enabled 6.10 Start-up Sequence 6.4.1 MCLR ENABLED Upon the release of a POR or BOR, the following must When MCLR is enabled and the pin is held low, the occur before the device will begin executing: device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. 1. Power-up Timer runs to completion (if enabled). 2. Oscillator start-up timer runs to completion (if The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. required for oscillator source). 3. MCLR must be released (if enabled). Note: A Reset does not drive the MCLR pin low. The total time-out will vary based on oscillator configu- 6.4.2 MCLR DISABLED ration and Power-up Timer configuration. See Section5.0 “Oscillator Module (With Fail-Safe When MCLR is disabled, the pin functions as a general Clock Monitor)” for more information. purpose input and the internal weak pull-up is under The Power-up Timer and oscillator start-up timer run software control. See Section12.11 “PORTE independently of MCLR Reset. If MCLR is kept low Registers” for more information. long enough, the Power-up Timer and oscillator start- up timer will expire. Upon bringing MCLR high, the 6.5 Watchdog Timer (WDT) Reset device will begin execution immediately (see Figure6- The Watchdog Timer generates a Reset if the firmware 3). This is useful for testing purposes or to synchronize does not issue a CLRWDT instruction within the time-out more than one device operating in parallel. period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section10.0 “Watchdog Timer” for more information. 6.6 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Table6-4 for default conditions after a RESET instruction has occurred. 6.7 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section3.5.2 “Overflow/Underflow Reset” for more information. DS40001574C-page 80  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC  2011-2013 Microchip Technology Inc. DS40001574C-page 81

PIC16(L)F1938/9 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table6-3 and Table6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RMCLR RI POR BOR TO PD Condition 0 0 1 1 0 x 1 1 Power-on Reset 0 0 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 0 x x 0 Illegal, PD is set on POR 0 0 1 1 u 0 1 1 Brown-out Reset u u u u u u 0 u WDT Reset u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u 1 0 Interrupt Wake-up from Sleep u u 0 u u u u u MCLR Reset during normal operation u u 0 u u u 1 0 MCLR Reset during Sleep u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS(2) Program STATUS PCON Condition Counter Register Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-- uuuu RESET Instruction Executed 0000h ---u uuuu uu-- u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as ‘0’. DS40001574C-page 82  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 6.12 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Reset Instruction Reset (RI) • Stack Overflow Reset (STKOVF) • Stack Underflow Reset (STKUNF) • MCLR Reset (RMCLR) The PCON register bits are shown in Register6-2. 6.13 Register Definitions: Power Control (PCON) REGISTER 6-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u STKOVF STKUNF — — RMCLR RI POR BOR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or set to ‘0’ by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or set to ‘0’ by firmware bit 5-4 Unimplemented: Read as ‘0’ bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)  2011-2013 Microchip Technology Inc. DS40001574C-page 83

PIC16(L)F1938/9 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BORCON SBOREN — — — — — — BORRDY 79 PCON STKOVF STKUNF — — RMCLR RI POR BOR 83 STATUS — — — TO PD Z DC C 24 WDTCON — — WDTPS<4:0> SWDTEN 105 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS40001574C-page 84  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • Operation • Interrupt Latency • Interrupts During Sleep • INT Pin • Automatic Context Saving Many peripherals produce Interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure7-1. FIGURE 7-1: INTERRUPT LOGIC TMR0IF Wake-up TMR0IE (If in Sleep mode) INTF Peripheral Interrupts INTE (TMR1IF) PIR1<0> IOCIF (TMR1IE) PIE1<0> Interrupt IOCIE to CPU PEIE PIRn<7> GIE PIEn<7>  2011-2013 Microchip Technology Inc. DS40001574C-page 85

PIC16(L)F1938/9 7.1 Operation 7.2 Interrupt Latency Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the are enabled by setting the following bits: interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous • GIE bit of the INTCON register interrupts is three or four instruction cycles. For • Interrupt Enable bit(s) for the specific interrupt asynchronous interrupts, the latency is three to five event(s) instruction cycles, depending on when the interrupt • PEIE bit of the INTCON register (if the Interrupt occurs. See Figure7-2 and Figure7-3 for more details. Enable bit of the interrupt event is contained in the PIE1, PIE2 and PIE3 registers) The INTCON, PIR1, PIR2 and PIR3 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See Section7.5 “Automatic Context Saving”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. DS40001574C-page 86  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 7-2: INTERRUPT LATENCY OSC1 Q1Q2Q3 Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC PC-1 PC PC+1 0004h 0005h Execute 1 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC+1/FSR New PC/ PC PC-1 PC ADDR PC+1 0004h 0005h Execute 2 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h)  2011-2013 Microchip Technology Inc. DS40001574C-page 87

PIC16(L)F1938/9 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 (3) CLKOUT (4) INT pin (1) (1) (2) INTF (5) Interrupt Latency GIE INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in the applicable Electrical Specifications Chapter”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS40001574C-page 88  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section9.0 “Power- Down Mode (Sleep)” for more details. 7.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • W register • STATUS register (except for TO and PD) • BSR register • FSR registers • PCLATH register Upon exiting the Interrupt Service Routine, these regis- ters are automatically restored. Any modifications to these registers during the ISR will be lost. If modifica- tions to any of these registers are desired, the corre- sponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved.  2011-2013 Microchip Technology Inc. DS40001574C-page 89

PIC16(L)F1938/9 7.6 Register Definitions: Interrupt Control REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register have been cleared by software. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. DS40001574C-page 90  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 Gate Acquisition interrupt 0 = Disables the Timer1 Gate Acquisition interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2011-2013 Microchip Technology Inc. DS40001574C-page 91

PIC16(L)F1938/9 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit 1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2 LCDIE: LCD Module Interrupt Enable bit 1 = Enables the LCD module interrupt 0 = Disables the LCD module interrupt bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001574C-page 92  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 CCP5IE: CCP5 Interrupt Enable bit 1 = Enables the CCP5 interrupt 0 = Disables the CCP5 interrupt bit 5 CCP4IE: CCP4 Interrupt Enable bit 1 = Enables the CCP4 interrupt 0 = Disables the CCP4 interrupt bit 4 CCP3IE: CCP3 Interrupt Enable bit 1 = Enables the CCP3 interrupt 0 = Disables the CCP3 interrupt bit 3 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the TMR6 to PR6 Match interrupt 0 = Disables the TMR6 to PR6 Match interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 Match interrupt 0 = Disables the TMR4 to PR4 Match interrupt bit 0 Unimplemented: Read as ‘0’ Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2011-2013 Microchip Technology Inc. DS40001574C-page 93

PIC16(L)F1938/9 REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001574C-page 94  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 C2IF: Comparator C2 Interrupt Flag 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 C1IF: Comparator C1 Interrupt Flag 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 LCDIF: LCD Module Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2011-2013 Microchip Technology Inc. DS40001574C-page 95

PIC16(L)F1938/9 REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 CCP5IF: CCP5 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 CCP4IF: CCP4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 CCP3IF: CCP3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 Unimplemented: Read as ‘0’ bit 1 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 Unimplemented: Read as ‘0’ Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001574C-page 96  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 OPTION_REG WPUEN INTEDG TMROCS TMROSE PSA PS<2:0> 187 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 92 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 93 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 95 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 96 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.  2011-2013 Microchip Technology Inc. DS40001574C-page 97

PIC16(L)F1938/9 NOTES: DS40001574C-page 98  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 8.0 LOW DROPOUT (LDO) On power-up, the external capacitor will load the LDO VOLTAGE REGULATOR voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source The PIC16F193X has an internal Low Dropout charges the external capacitor. After the cap is fully Regulator (LDO) which provides operation above 3.6V. charged, the device is released from Reset. For more The LDO regulates a voltage for the internal device information on the constant current rate, refer to the logic while permitting the VDD and I/O pins to operate LDO Regulator Characteristics Table in Section30.0 at a higher voltage. There is no user enable/disable “Electrical Specifications”. control available for the LDO, it is always active. The PIC16LF193X operates at a maximum VDD of 3.6V and does not incorporate an LDO. A device I/O pin may be configured as the LDO voltage output, identified as the VCAP pin. Although not required, an external low-ESR capacitor may be con- nected to the VCAP pin for additional regulator stability. The VCAPEN<1:0> bits of Configuration Words deter- mines which pin is assigned as the VCAP pin. Refer to Table8-1. TABLE 8-1: VCAPEN<1:0> SELECT BITS VCAPEN<1:0> Pin 00 RA0 01 RA5 10 RA6 11 No VCAP TABLE 8-2: SUMMARY OF CONFIGURATION WORD WITH LDO Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — LVP DEBUG — BORV STVREN PLLEN CONFIG2 56 7:0 — — VCAPEN<1:0>(1) — — WRT1 WRT0 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO. Note 1: PIC16F193X only.  2011-2013 Microchip Technology Inc. DS40001574C-page 99

PIC16(L)F1938/9 NOTES: DS40001574C-page 100  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-Down mode is entered by executing a The device can wake-up from Sleep through one of the SLEEP instruction. following events: Upon entering Sleep mode, the following conditions 1. External Reset input on MCLR pin, if enabled exist: 2. BOR Reset, if enabled 1. WDT will be cleared but keeps running, if 3. POR Reset enabled for operation during Sleep. 4. Watchdog Timer, if enabled 2. PD bit of the STATUS register is cleared. 5. Any external interrupt 3. TO bit of the STATUS register is set. 6. Interrupts by peripherals capable of running dur- 4. CPU clock is disabled. ing Sleep (see individual peripheral for more 5. 31 kHz LFINTOSC is unaffected and peripherals information) that operate from it may continue operation in The first three events will cause a device Reset. The Sleep. last three events are considered a continuation of pro- 6. Timer1 oscillator is unaffected and peripherals gram execution. To determine whether a device Reset that operate from it may continue operation in or wake-up event occurred, refer to Section6.11 Sleep. “Determining the Cause of a Reset”. 7. ADC is unaffected, if the dedicated FRC clock is When the SLEEP instruction is being executed, the next selected. instruction (PC + 1) is prefetched. For the device to 8. Capacitive Sensing oscillator is unaffected. wake-up through an interrupt event, the corresponding 9. I/O ports maintain the status they had before interrupt enable bit must be enabled. Wake-up will SLEEP was executed (driving high, low or high- occur regardless of the state of the GIE bit. If the GIE impedance). bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is 10. Resets other than WDT are not affected by enabled, the device executes the instruction after the Sleep mode. SLEEP instruction, the device will then call the Interrupt Refer to individual chapters for more details on Service Routine. In cases where the execution of the peripheral operation during Sleep. instruction following SLEEP is not desirable, the user To minimize current consumption, the following condi- should have a NOP after the SLEEP instruction. tions should be considered: The WDT is cleared when the device wakes up from • I/O pins should not be floating Sleep, regardless of the source of wake-up. • External circuitry sinking current from I/O pins • Internal circuitry sourcing current from I/O pins • Current draw from pins with internal weak pull-ups • Modules using 31 kHz LFINTOSC • Modules using Timer1 oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching cur- rents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section17.0 “Digital-to-Analog Con- verter (DAC) Module” and Section14.0 “Fixed Volt- age Reference (FVR)” for more information on these modules.  2011-2013 Microchip Technology Inc. DS40001574C-page 101

PIC16(L)F1938/9 9.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the execu- tion of a SLEEP instruction When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit - SLEEP instruction will be completely exe- and interrupt flag bit set, one of the following will occur: cuted - Device will immediately wake-up from Sleep • If the interrupt occurs before the execution of a SLEEP instruction - WDT and WDT prescaler will be cleared - SLEEP instruction will execute as a NOP. - TO bit of the STATUS register will be set - WDT and WDT prescaler will not be cleared - PD bit of the STATUS register will be cleared. - TO bit of the STATUS register will not be set Even if the flag bits were checked before executing a - PD bit of the STATUS register will not be SLEEP instruction, it may be possible for flag bits to cleared. become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) CLKOUT(2) TOST(3) Interrupt flag Interrupt Latency(4) GIE bit Processor in (INTCON reg.) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC - 1) Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. 3: TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes. 4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 145 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 145 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 145 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 92 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 93 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 95 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 96 STATUS — — — TO PD Z DC C 24 WDTCON — — WDTPS<4:0> SWDTEN 105 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode. DS40001574C-page 102  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 10.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0>=01 SWDTEN 23-bit Programmable WDTE<1:0>=11 LFINTOSC WDT Time-out Prescaler WDT WDTE<1:0>=10 Sleep WDTPS<4:0>  2011-2013 Microchip Technology Inc. DS40001574C-page 103

PIC16(L)F1938/9 10.1 Independent Clock Source 10.3 Time-Out Period The WDT derives its time base from the 31kHz The WDTPS bits of the WDTCON register set the LFINTOSC internal oscillator. Time intervals in this time-out period from 1 ms to 256 seconds (nominal). chapter are based on a nominal interval of 1ms. See After a Reset, the default time-out period is 2 seconds. the Electrical Specifications Chapters for the LFINTOSC tolerances. 10.4 Clearing the WDT 10.2 WDT Operating Modes The WDT is cleared when any of the following condi- tions occur: The Watchdog Timer module has four operating modes • Any Reset controlled by the WDTE<1:0> bits in Configuration • CLRWDT instruction is executed Words. See Table10-1. • Device enters Sleep 10.2.1 WDT IS ALWAYS ON • Device wakes up from Sleep When the WDTE bits of Configuration Words are set to • Oscillator fail ‘11’, the WDT is always on. • WDT is disabled WDT protection is active during Sleep. • Oscillator Start-up TImer (OST) is running See Table10-2 for more information. 10.2.2 WDT IS OFF IN SLEEP When the WDTE bits of Configuration Words are set to 10.5 Operation During Sleep ‘10’, the WDT is on, except in Sleep. When the device enters Sleep, the WDT is cleared. If WDT protection is not active during Sleep. the WDT is enabled during Sleep, the WDT resumes counting. 10.2.3 WDT CONTROLLED BY SOFTWARE When the device exits Sleep, the WDT is cleared When the WDTE bits of Configuration Words are set to again. The WDT remains clear until the OST, if ‘01’, the WDT is controlled by the SWDTEN bit of the enabled, completes. See Section5.0 “Oscillator WDTCON register. Module (With Fail-Safe Clock Monitor)” for more WDT protection is unchanged by Sleep. See information on the OST. Table10-1 for more details. When a WDT time-out occurs while the device is in TABLE 10-1: WDT OPERATING MODES Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the Device WDT STATUS register are changed to indicate the event. See WDTE<1:0> SWDTEN Mode Mode Section3.0 “Memory Organization” and STATUS register (Register3-1) for more information. 11 X X Active Awake Active 10 X Sleep Disabled 1 Active 01 X 0 Disabled 00 X X Disabled TABLE 10-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0>=00 WDTE<1:0>=01 and SWDTEN = 0 WDTE<1:0>=10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) Unaffected DS40001574C-page 104  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 10.6 Register Definitions: Watchdog Control REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 — — WDTPS<4:0> SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 00000 = 1:32 (Interval 1ms typ) 00001 = 1:64 (Interval 2ms typ) 00010 = 1:128 (Interval 4ms typ) 00011 = 1:256 (Interval 8ms typ) 00100 = 1:512 (Interval 16ms typ) 00101 = 1:1024 (Interval 32ms typ) 00110 = 1:2048 (Interval 64ms typ) 00111 = 1:4096 (Interval 128ms typ) 01000 = 1:8192 (Interval 256ms typ) 01001 = 1:16384 (Interval 512ms typ) 01010 = 1:32768 (Interval 1s typ) 01011 = 1:65536 (Interval 2s typ) (Reset value) 01100 = 1:131072 (217) (Interval 4s typ) 01101 = 1:262144 (218) (Interval 8s typ) 01110 = 1:524288 (219) (Interval 16s typ) 01111 = 1:1048576 (220) (Interval 32s typ) 10000 = 1:2097152 (221) (Interval 64s typ) 10001 = 1:4194304 (222) (Interval 128s typ) 10010 = 1:8388608 (223) (Interval 256s typ) 10011 = Reserved. Results in minimum interval (1:32) • • • 11111 = Reserved. Results in minimum interval (1:32) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored.  2011-2013 Microchip Technology Inc. DS40001574C-page 105

PIC16(L)F1938/9 TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 73 STATUS — — — TO PD Z DC C 24 WDTCON — — WDTPS<4:0> SWDTEN 105 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer. TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 54 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer. DS40001574C-page 106  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 11.0 DATA EEPROM AND FLASH 11.1 EEADRL and EEADRH Registers PROGRAM MEMORY The EEADRH:EEADRL register pair can address up to CONTROL a maximum of 256bytes of data EEPROM or up to a maximum of 32K words of program memory. The Data EEPROM and Flash program memory are readable and writable during normal operation (full VDD When selecting a program address value, the MSB of range). These memories are not directly mapped in the the address is written to the EEADRH register and the register file space. Instead, they are indirectly LSB is written to the EEADRL register. When selecting addressed through the Special Function Registers a EEPROM address value, only the LSB of the address (SFRs). There are six SFRs used to access these is written to the EEADRL register. memories: 11.1.1 EECON1 AND EECON2 REGISTERS • EECON1 EECON1 is the control register for EE memory • EECON2 accesses. • EEDATL Control bit EEPGD determines if the access will be a • EEDATH program or data memory access. When clear, any • EEADRL subsequent operations will operate on the EEPROM • EEADRH memory. When set, any subsequent operations will When interfacing the data memory block, EEDATL operate on the program memory. On Reset, EEPROM is holds the 8-bit data for read/write, and EEADRL holds selected by default. the address of the EEDATL location being accessed. Control bits RD and WR initiate read and write, These devices have 256 bytes of data EEPROM with respectively. These bits cannot be cleared, only set, in an address range from 0h to 0FFh. software. They are cleared in hardware at completion When accessing the program memory block, the EED- of the read or write operation. The inability to clear the ATH:EEDATL register pair forms a 2-byte word that WR bit in software prevents the accidental, premature holds the 14-bit data for read/write, and the EEADRL termination of a write operation. and EEADRH registers form a 2-byte word that holds The WREN bit, when set, will allow a write operation to the 15-bit address of the program memory location occur. On power-up, the WREN bit is clear. The being read. WRERR bit is set when a write operation is interrupted The EEPROM data memory allows byte read and write. by a Reset during normal operation. In these situations, An EEPROM byte write automatically erases the loca- following Reset, the user can check the WRERR bit tion and writes the new data (erase before write). and execute the appropriate error handling routine. The write time is controlled by an on-chip timer. The Interrupt flag bit EEIF of the PIR2 register is set when write/erase voltages are generated by an on-chip write is complete. It must be cleared in the software. charge pump rated to operate over the voltage range of Reading EECON2 will read all ‘0’s. The EECON2 reg- the device for byte or word operations. ister is used exclusively in the data EEPROM write Depending on the setting of the Flash Program sequence. To enable writes, a specific pattern must be Memory Self Write Enable bits WRT<1:0> of the written to EECON2. Configuration Words, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are always allowed. When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory.  2011-2013 Microchip Technology Inc. DS40001574C-page 107

PIC16(L)F1938/9 11.2 Using the Data EEPROM 11.2.2 WRITING TO THE DATA EEPROM MEMORY The data EEPROM is a high-endurance, byte address- able array that has been optimized for the storage of To write an EEPROM data location, the user must first frequently changing information (e.g., program vari- write the address to the EEADRL register and the data ables or other data that are updated often). When vari- to the EEDATL register. Then the user must follow a ables in one section change frequently, while variables specific sequence to initiate the write for each byte. in another section do not change, it is possible to The write will not initiate if the above sequence is not exceed the total number of write cycles to the followed exactly (write 55h to EECON2, write AAh to EEPROM without exceeding the total number of write EECON2, then set the WR bit) for each byte. Interrupts cycles to a single byte. Refer to Section30.0 “Electri- should be disabled during this codesegment. cal Specifications”. If this is the case, then a refresh Additionally, the WREN bit in EECON1 must be set to of the array must be performed. For this reason, vari- enable write. This mechanism prevents accidental ables that change infrequently (such as constants, IDs, writes to data EEPROM due to errant (unexpected) calibration, etc.) should be stored in Flash program code execution (i.e., lost programs). The user should memory. keep the WREN bit clear at all times, except when 11.2.1 READING THE DATA EEPROM updating EEPROM. The WREN bit is not cleared byhardware. MEMORY After a write sequence has been initiated, clearing the To read a data memory location, the user must write the WREN bit will not affect this write cycle. The WR bit will address to the EEADRL register, clear the EEPGD and be inhibited from being set unless the WREN bit is set. CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next At the completion of the write cycle, the WR bit is cycle, in the EEDATL register; therefore, it can be read cleared in hardware and the EE Write Complete in the next instruction. EEDATL will hold this value until Interrupt Flag bit (EEIF) is set. The user can either another read or until it is written to by the user (during enable this interrupt or poll this bit. EEIF must be a write operation). cleared by software. 11.2.3 PROTECTION AGAINST SPURIOUS EXAMPLE 11-1: DATA EEPROM READ WRITE BANKSELEEADRL ; MOVLW DATA_EE_ADDR ; There are conditions when the user may not want to MOVWF EEADRL ;Data Memory write to the data EEPROM memory. To protect against ;Address to read spurious EEPROM writes, various mechanisms have BCF EECON1, CFGS ;Deselect Config space been built-in. On power-up, WREN is cleared. Also, the BCF EECON1, EEPGD;Point to DATA memory Power-up Timer (64ms duration) prevents EEPROM BSF EECON1, RD ;EE Read write. MOVF EEDATL, W ;W = EEDATL The write initiate sequence and the WREN bit together help prevent an accidental write during: • Brown-out Note: Data EEPROM can be read regardless of • Power Glitch the setting of the CPD bit. • Software Malfunction 11.2.4 DATA EEPROM OPERATION DURING CODE-PROTECT Data memory can be code-protected by programming the CPD bit in the Configuration Words to ‘0’. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. DS40001574C-page 108  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 EXAMPLE 11-2: DATA EEPROM WRITE BANKSEL EEADRL ; MOVLW DATA_EE_ADDR ; MOVWF EEADRL ;Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATL ;Data Memory Value to write BCF EECON1, CFGS ;Deselect Configuration space BCF EECON1, EEPGD ;Point to DATA memory BSF EECON1, WREN ;Enable writes BCF INTCON, GIE ;Disable INTs. MOVLW 55h ; RequiredSequence MMMBOOOSVVVFWLWFWF E0EEEAEECACCOhOONNN221, WR ;;;;WWSerriit ttWeeR 5Ab5Aihht to begin write BSF INTCON, GIE ;Enable Interrupts BCF EECON1, WREN ;Disable writes BTFSC EECON1, WR ;Wait for write to complete GOTO $-2 ;Done FIGURE 11-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR PC PC + 1 EEADRH,EEADRL PPCC ++ 33 PC + 4 PC + 5 Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4) INSTR(PC - 1) BSF EECON1,RD INSTR(PC + 1) Forced NOP INSTR(PC + 3) INSTR(PC + 4) executed here executed here executed here executed here executed here executed here RD bit EEDATH EEDATL Register  2011-2013 Microchip Technology Inc. DS40001574C-page 109

PIC16(L)F1938/9 11.3 Flash Program Memory Overview 11.3.1 READING THE FLASH PROGRAM MEMORY It is important to understand the Flash program mem- ory structure for erase and programming operations. To read a program memory location, the user must: Flash Program memory is arranged in rows. A row con- 1. Write the Least and Most Significant address sists of a fixed number of 14-bit program memory bits to the EEADRH:EEADRL register pair. words. A row is the minimum block size that can be 2. Clear the CFGS bit of the EECON1 register. erased by user software. 3. Set the EEPGD control bit of the EECON1 Flash program memory may only be written or erased register. if the destination address is in a segment of memory 4. Then, set control bit RD of the EECON1 register. that is not write-protected, as defined in bits WRT<1:0> Once the read control bit is set, the program memory of Configuration Words. Flash controller will use the second instruction cycle to After a row has been erased, the user can reprogram read the data. This causes the second instruction all or a portion of this row. Data to be written into the immediately following the “BSF EECON1,RD” instruction program memory row is written to 14-bit wide data write to be ignored. The data is available in the very next cycle, latches. These write latches are not directly accessible in the EEDATH:EEDATL register pair; therefore, it can to the user, but may be loaded via sequential writes to be read as two bytes in the following instructions. the EEDATH:EEDATL register pair. EEDATH:EEDATL register pair will hold this value until Note: If the user wants to modify only a portion another read or until it is written to by the user. of a previously programmed row, then the Note1: The two instructions following a program contents of the entire row must be read and saved in RAM prior to the erase. memory read are required to be NOPs. This prevents the user from executing a The number of data write latches may not be equivalent two-cycle instruction on the next to the number of row locations. During programming, instruction after the RD bit is set. user software may need to fill the set of write latches 2: Flash program memory can be read and initiate a programming operation multiple times in regardless of the setting of the CP bit. order to fully reprogram an erased row. For example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times. The size of a program memory row and the number of program memory write latches may vary by device. See Table11-1 for details. TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Device Erase Block (Row) Size/Boundary Number of Write Latches/Boundary PIC16(L)F1938 32 words, EEADRL<4:0> = 00000 32 words, EEADRL<4:0> = 00000 PIC16(L)F1939 DS40001574C-page 110  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 EXAMPLE 11-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI: PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL EEADRL ; Select Bank for EEPROM registers MOVLW PROG_ADDR_LO ; MOVWF EEADRL ; Store LSB of address MOVLW PROG_ADDR_HI ; MOVWL EEADRH ; Store MSB of address BCF EECON1,CFGS ; Do not select Configuration Space BSF EECON1,EEPGD ; Select Program Memory BCF INTCON,GIE ; Disable interrupts BSF EECON1,RD ; Initiate read NOP ; Executed (Figure 11-1) NOP ; Ignored (Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2011-2013 Microchip Technology Inc. DS40001574C-page 111

PIC16(L)F1938/9 11.3.2 ERASING FLASH PROGRAM The following steps should be completed to load the MEMORY write latches and program a block of program memory. These steps are divided into two parts. First, all write While executing code, program memory can only be latches are loaded with data except for the last program erased by rows. To erase a row: memory location. Then, the last write latch is loaded 1. Load the EEADRH:EEADRL register pair with and the programming sequence is initiated. A special the address of new row to be erased. unlock sequence is required to load a write latch with 2. Clear the CFGS bit of the EECON1 register. data or initiate a Flash programming operation. This 3. Set the EEPGD, FREE, and WREN bits of the unlock sequence should not be interrupted. EECON1 register. 1. Set the EEPGD and WREN bits of the EECON1 4. Write 55h, then AAh, to EECON2 (Flash register. programming unlock sequence). 2. Clear the CFGS bit of the EECON1 register. 5. Set control bit WR of the EECON1 register to 3. Set the LWLO bit of the EECON1 register. When begin the erase operation. the LWLO bit of the EECON1 register is ‘1’, the 6. Poll the FREE bit in the EECON1 register to write sequence will only load the write latches determine when the row erase has completed. and will not initiate the write to Flash program memory. See Example11-4. 4. Load the EEADRH:EEADRL register pair with After the “BSF EECON1,WR” instruction, the processor the address of the location to be written. requires two cycles to set up the erase operation. The 5. Load the EEDATH:EEDATL register pair with user must place two NOP instructions after the WR bit is the program memory data to be written. set. The processor will halt internal operations for the 6. Write 55h, then AAh, to EECON2, then set the typical 2ms erase time. This is not Sleep mode as the WR bit of the EECON1 register (Flash clocks and peripherals will continue to run. After the programming unlock sequence). The write latch erase cycle, the processor will resume operation with is now loaded. the third instruction after the EECON1 write instruction. 7. Increment the EEADRH:EEADRL register pair 11.3.3 WRITING TO FLASH PROGRAM to point to the next location. MEMORY 8. Repeat steps 5 through 7 until all but the last Program memory is programmed using the following write latch has been loaded. steps: 9. Clear the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is 1. Load the starting address of the word(s) to be ‘0’, the write sequence will initiate the write to programmed. Flash program memory. 2. Load the write latches with data. 10. Load the EEDATH:EEDATL register pair with 3. Initiate a programming operation. the program memory data to be written. 4. Repeat steps 1 through 3 until all data is written. 11. Write 55h, then AAh, to EECON2, then set the Before writing to program memory, the word(s) to be WR bit of the EECON1 register (Flash written must be erased or previously unwritten. Pro- programming unlock sequence). The entire gram memory can only be erased one row at a time. No latch block is now written to Flash program automatic erase occurs upon the initiation of the write. memory. Program memory can be written one or more words at It is not necessary to load the entire write latch block a time. The maximum number of words written at one with user program data. However, the entire write latch time is equal to the number of write latches. See block will be written to program memory. Figure11-2 (block writes to program memory with 8 An example of the complete write sequence for eight write latches) for more details. The write latches are words is shown in Example11-5. The initial address is aligned to the address boundary defined by EEADRL loaded into the EEADRH:EEADRL register pair; the as shown in Table11-1. Write operations do not cross eight words of data are loaded using indirect these boundaries. At the completion of a program addressing. memory write operation, the write latches are reset to contain 0x3FFF. Note: The code sequence provided in Example11-5 must be repeated multiple times to fully program an erased program memory row. DS40001574C-page 112  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 After the “BSF EECON1,WR” instruction, the processor continue to run. The processor does not stall when requires two cycles to set up the write operation. The LWLO = 1, loading the write latches. After the write user must place two NOP instructions after the WR bit is cycle, the processor will resume operation with the third set. The processor will halt internal operations for the instruction after the EECON1 write instruction. typical 2ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will FIGURE 11-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 8 WRITE LATCHES 7 5 0 7 0 EEDATH EEDATA 6 8 First word of block Last word of block to be written to be written 14 14 14 14 EEADRL<2:0> = 000 EEADRL<2:0> = 001 EEADRL<2:0> = 010 EEADRL<2:0> = 111 Buffer Register Buffer Register Buffer Register Buffer Register Program Memory  2011-2013 Microchip Technology Inc. DS40001574C-page 113

PIC16(L)F1938/9 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL EEADRL MOVF ADDRL,W ; Load lower 8 bits of erase address boundary MOVWF EEADRL MOVF ADDRH,W ; Load upper 6 bits of erase address boundary MOVWF EEADRH BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space BSF EECON1,FREE ; Specify an erase operation BSF EECON1,WREN ; Enable writes MOVLW 55h ; Start of required sequence to initiate erase MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne reer aasree ignored as processor ; halts to begin erase sequence NOP ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts DS40001574C-page 114  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 EXAMPLE 11-5: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL ; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) ; BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL EEADRH ; Bank 3 MOVF ADDRH,W ; Load initial address MOVWF EEADRH ; MOVF ADDRL,W ; MOVWF EEADRL ; MOVLW LOW DATA_ADDR ; Load initial data address MOVWF FSR0L ; MOVLW HIGH DATA_ADDR ; Load initial data address MOVWF FSR0H ; BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space BSF EECON1,WREN ; Enable writes BSF EECON1,LWLO ; Only Load Write Latches LOOP MOVIW FSR0++ ; Load first data byte into lower MOVWF EEDATL ; MOVIW FSR0++ ; Load second data byte into upper MOVWF EEDATH ; MOVF EEADRL,W ; Check if lower bits of address are '000' XORLW 0x07 ; Check if we're on the last of 8 addresses ANDLW 0x07 ; BTFSC STATUS,Z ; Exit if last of eight words, GOTO START_WRITE ; MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne rwer iatree ignored as processor ; halts to begin write sequence NOP ; Processor will stop here and wait for write to complete. ; After write processor continues with 3rd instruction. INCF EEADRL,F ; Still loading latches Increment address GOTO LOOP ; Write next latches START_WRITE BCF EECON1,LWLO ; No more loading latches - Actually start Flash program ; memory write MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne rwer iatree ignored as processor ; halts to begin write sequence NOP ; Processor will stop here and wait for write complete. ; after write processor continues with 3rd instruction BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts  2011-2013 Microchip Technology Inc. DS40001574C-page 115

PIC16(L)F1938/9 11.4 Modifying Flash Program Memory 11.5 User ID, Device ID and Configuration Word Access When modifying existing data in a program memory row, and data within that row must be preserved, it must Instead of accessing program memory or EEPROM first be read and saved in a RAM image. Program data memory, the User ID’s, Device ID/Revision ID and memory is modified using the following steps: Configuration Words can be accessed when CFGS=1 1. Load the starting address of the row to be mod- in the EECON1 register. This is the region that would ified. be pointed to by PC<15>=1, but not all addresses are accessible. Different access may exist for reads and 2. Read the existing data from the row into a RAM writes. Refer to Table11-2. image. 3. Modify the RAM image to contain the new data When read access is initiated on an address outside the to be written into program memory. parameters listed in Table11-2, the EEDATH:EEDATL register pair is cleared. 4. Load the starting address of the row to be rewrit- ten. 5. Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. 8. Repeat steps 6 and 7 as many times as required to reprogram the erased row. TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS=1) Address Function Read Access Write Access 8000h-8003h User IDs Yes Yes 8006h Device ID/Revision ID Yes No 8007h-8008h Configuration Words 1 and 2 Yes No EXAMPLE 11-3: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL EEADRL ; Select correct Bank MOVLW PROG_ADDR_LO ; MOVWF EEADRL ; Store LSB of address CLRF EEADRH ; Clear MSB of address BSF EECON1,CFGS ; Select Configuration Space BCF INTCON,GIE ; Disable interrupts BSF EECON1,RD ; Initiate read NOP ; Executed (See Figure 11-1) NOP ; Ignored (See Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS40001574C-page 116  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 11.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example11-6) to the desired value to be written. Example11-6 shows how to verify a write to EEPROM. EXAMPLE 11-6: EEPROM WRITE VERIFY BANKSELEEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL, W ; BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue  2011-2013 Microchip Technology Inc. DS40001574C-page 117

PIC16(L)F1938/9 11.7 Register Definitions: EEPROM and Flash Control REGISTER 11-1: EEDATL: EEPROM DATA LOW-BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 11-2: EEDATH: EEPROM DATA HIGH-BYTE REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — EEDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 EEDAT<13:8>: Read/write value for Most Significant bits of program memory REGISTER 11-3: EEADRL: EEPROM ADDRESS LOW-BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address REGISTER 11-4: EEADRH: EEPROM ADDRESS HIGH-BYTE REGISTER U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — EEADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address DS40001574C-page 118  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Accesses program space Flash memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, User ID and Device ID Registers 0 = Accesses Flash Program or data EEPROM Memory bit 5 LWLO: Load Write Latches Only bit If CFGS=1 (Configuration space) OR CFGS=0 and EEPGD=1 (program Flash): 1 = The next WR command does not initiate a write; only the program memory latches are updated. 0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write of all the data stored in the program memory latches. If CFGS=0 and EEPGD=0: (Accessing data EEPROM) LWLO is ignored. The next WR command initiates a write to the data EEPROM. bit 4 FREE: Program Flash Erase Enable bit If CFGS=1 (Configuration space) OR CFGS=0 and EEPGD=1 (program Flash): 1 = Performs an erase operation on the next WR command (cleared by hardware after comple- tion of erase). 0 = Performs a write operation on the next WR command. If EEPGD=0 and CFGS=0: (Accessing data EEPROM) FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle. bit 3 WRERR: EEPROM Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit). 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash and data EEPROM bit 1 WR: Write Control bit 1 = Initiates a program Flash or data EEPROM program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash or data EEPROM is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash or data EEPROM data read.  2011-2013 Microchip Technology Inc. DS40001574C-page 119

PIC16(L)F1938/9 REGISTER 11-6: EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. Refer to Section11.2.2 “Writing to the Data EEPROM Memory” for more information. TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 119 EECON2 EEPROM Control Register 2 (not a physical register) 107* EEADRL EEADRL<7:0> 118 EEADRH —(1) EEADRH<6:0 118 EEDATL EEDATL<7:0> 118 EEDATH — — EEDATH<5:0> 118 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 92 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 95 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by data EEPROM module. * Page provides register information. Note 1: Unimplemented, read as ‘1’. DS40001574C-page 120  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of Read LATx TRISx the device) • LATx registers (output latch) D Q Some ports may have one or more of the following Write LATx Write PORTx additional registers. These registers are: CK VDD • ANSELx (analog select) Data Register • WPUx (weak pull-up) Data Bus In general, when a peripheral is enabled on a port pin, I/O pin that pin cannot be used as a general purpose output. Read PORTx However, the pin can still be read. To peripherals VSS ANSELx TABLE 12-1: PORT AVAILABILITY PER DEVICE A B C EXAMPLE 12-1: INITIALIZING PORTA T T T Device R R R ; This code example illustrates O O O P P P ; initializing the PORTA register. The ; other ports are initialized in the same PIC16F1933 ● ● ; manner. PIC16F1934 ● ● ● BANKSEL PORTA ; CLRF PORTA ;Init PORTA TABLE 12-2: PORT AVAILABILITY PER BANKSEL LATA ;Data Latch DEVICE CLRF LATA ; BANKSEL ANSELA ; A B C D E CLRF ANSELA ;digital I/O T T T T T Device R R R R R BANKSEL TRISA ; O O O O O MOVLW B'00111000' ;Set RA<5:3> as inputs P P P P P MOVWF TRISA ;and set RA<2:0> as PIC16(L)F1938 ● ● ● ● ;outputs PIC16(L)F1939 ● ● ● ● ● The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure12-1.  2011-2013 Microchip Technology Inc. DS40001574C-page 121

PIC16(L)F1938/9 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register12-1. For this device family, the following functions can be moved between different pins. • SS (Slave Select) • P2B output • CCP2/P2A output • CCP3/P3A output • Timer1 Gate • SR Latch SRNQ output • Comparator C2 output These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. DS40001574C-page 122  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 12.2 Register Definitions: Alternate Pin Function Control REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’. bit 6 CCP3SEL: CCP3 Input/Output Pin Selection bit For 28-Pin Devices (PIC16F1933/1936/1938): 0 = CCP3/P3A function is on RC6/TX/CK/CCP3/P3A/SEG9 1 = CCP3/P3A function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1 For 40-Pin Devices (PIC16F1934/1937/1939): 0 = CCP3/P3A function is on RE0/AN5/CCP3/P3A/SEG21 1 = CCP3/P3A function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1 bit 5 T1GSEL: Timer1 Gate Input Pin Selection bit 0 = T1G function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1 1 = T1G function is on RC4/SDI/SDA/T1G/SEG11 bit 4 P2BSEL: CCP2 PWM B Output Pin Selection bit For 28-Pin Devices (PIC16F1933/1936/1938): 0 = P2B function is on RC0/T1OSO/T1CKI/P2B 1 = P2B function is on RB5/AN13/P2B/CPS5/T1G/COM1 For 40-Pin Devices (PIC16F1934/1937/1939): 0 = P2B function is on RC0/T1OSO/T1CKI/P2B 1 = P2B function is on RD2/CPS10/P2B bit 3 SRNQSEL: SR Latch nQ Output Pin Selection bit 0 = SRnQ function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/VCAP 1 = SRnQ function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/VCAP bit 2 C2OUTSEL: Comparator C2 Output Pin Selection bit 0 = C2OUT function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/VCAP 1 = C2OUT function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/VCAP bit 1 SSSEL: SS Input Pin Selection bit 0 = SS function is on RA5/AN4/C2OUT/SRNQ/SS/CPS7/SEG5/VCAP 1 = SS function is on RA0/AN0/C12IN0-/C2OUT/SRNQ/SS/SEG12/VCAP bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit 0 = CCP2/P2A function is on RC1/T1OSI/CCP2/P2A 1 = CCP2/P2A function is on RB3/AN9/C12IN2-/CPS3/CCP2/P2A/VLCD3  2011-2013 Microchip Technology Inc. DS40001574C-page 123

PIC16(L)F1938/9 12.3 PORTA Registers 12.3.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA Each PORTA pin is multiplexed with other functions. The (Register12-3). Setting a TRISA bit (= 1) will make the pins, their combined functions and their output priorities corresponding PORTA pin an input (i.e., disable the are shown in Table12-3. output driver). Clearing a TRISA bit (= 0) will make the When multiple outputs are enabled, the actual pin corresponding PORTA pin an output (i.e., enables control goes to the peripheral with the highest priority. output driver and puts the contents of the output latch Analog input functions, such as ADC, comparator and on the selected pin). Example12-1 shows how to CapSense inputs, are not shown in the priority lists. initialize an I/O port. These inputs are active when the I/O pin is set for Reading the PORTA register (Register12-2) reads the Analog mode using the ANSELx registers. Digital status of the pins, whereas writing to it will write to the output functions may control the pin when it is in Analog PORT latch. All write operations are read-modify-write mode with the priority shown in Table12-3. operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then TABLE 12-3: PORTA OUTPUT PRIORITY written to the PORT data latch (LATA). The TRISA register (Register12-3) controls the Pin Name Function Priority(1) PORTA pin output drivers, even when they are being RA0 VCAP used as analog inputs. The user should ensure the bits SEG12 (LCD) in the TRISA register are maintained set when using SRNQ (SR Latch) them as analog inputs. I/O pins configured as analog C2OUT (Comparator) inputs always read ‘0’. RA0 12.3.1 ANSELA REGISTER RA1 SEG7 (LCD) RA1 The ANSELA register (Register12-5) is used to RA2 COM2 (LCD) configure the Input mode of an I/O pin to analog. DACOUT (DAC) Setting the appropriate ANSELA bit high will cause all RA2 digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. RA3 COM3 (LCD) 28-pin only SEG15 The state of the ANSELA bits has no effect on digital RA3 output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode RA4 SEG4 (LCD) will be analog. This can cause unexpected behavior SRQ (SR Latch) when executing read-modify-write instructions on the C1OUT (Comparator) affected port. CCP5, 28-pin only RA4 Note: The ANSELA bits default to the Analog RA5 VCAP (enabled by Config. Word) mode after Reset. To use any pins as SEG5 (LCD) digital general purpose or peripheral SRNQ (SR Latch) inputs, the corresponding ANSEL bits C2OUT (Comparator) must be initialized to ‘0’ by user software. RA5 RA6 VCAP (enabled by Config. Word) OSC2 (enabled by Config. Word) CLKOUT (enabled by Config. Word) SEG1 (LCD) RA6 RA7 OSC1/CLKIN (enabled by Config. Word) SEG2 (LCD) RA7 Note 1: Priority listed from highest to lowest. DS40001574C-page 124  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 12.4 Register Definitions: PORTA Control REGISTER 12-2: PORTA: PORTA REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RA<7:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-3: TRISA: PORTA TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 LATA<7:0>: PORTA Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values.  2011-2013 Microchip Technology Inc. DS40001574C-page 125

PIC16(L)F1938/9 REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS40001574C-page 126  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 12-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — CHS<4:0> GO/DONE ADON 155 ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 156 ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 126 APFCON — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 123 CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 175 CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 175 CM1CON1 C1NTP C1INTN C1PCH<1:0> — — C1NCH<1:0> 176 CM2CON1 C2NTP C2INTN C2PCH<1:0> — — C2NCH<1:0> 176 CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 321 CPSCON1 — — — — CPSCH<3:0> 322 DACCON0 DACEN DACLPS DACOE --- DACPSS<1:0> --- DACNSS 168 LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 125 LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 327 LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 331 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 331 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 187 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 125 SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 182 SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 283 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: PIC16F193X only. TABLE 12-5: SUMMARY OF CONFIGURATION WORD WITH PORTA Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 54 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> 13:8 — — LVP DEBUG — BORV STVREN PLLEN CONFIG2 56 7:0 — — VCAPEN<1:0>(1) — — WRT<1:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. Note 1: PIC16F193X only.  2011-2013 Microchip Technology Inc. DS40001574C-page 127

PIC16(L)F1938/9 12.5 PORTB Registers 12.5.3 ANSELB REGISTER PORTB is an 8-bit wide, bidirectional port. The The ANSELB register (Register12-9) is used to corresponding data direction register is TRISB configure the Input mode of an I/O pin to analog. (Register12-7). Setting a TRISB bit (= 1) will make the Setting the appropriate ANSELB bit high will cause all corresponding PORTB pin an input (i.e., put the digital reads on the pin to be read as ‘0’ and allow corresponding output driver in a High-Impedance mode). analog functions on the pin to operate correctly. Clearing a TRISB bit (= 0) will make the corresponding The state of the ANSELB bits has no effect on digital PORTB pin an output (i.e., enable the output driver and output functions. A pin with TRIS clear and ANSELB set put the contents of the output latch on the selected pin). will still operate as a digital output, but the Input mode Example12-1 shows how to initialize an I/O port. will be analog. This can cause unexpected behavior Reading the PORTB register (Register12-6) reads the when executing read-modify-write instructions on the status of the pins, whereas writing to it will write to the affected port. PORT latch. All write operations are read-modify-write Note: The ANSELB bits default to the Analog operations. Therefore, a write to a port implies that the mode after Reset. To use any pins as port pins are read, this value is modified and then written digital general purpose or peripheral to the PORT data latch (LATB). inputs, the corresponding ANSEL bits The TRISB register (Register12-7) controls the PORTB must be initialized to ‘0’ by user software. pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. 12.5.1 WEAK PULL-UPS Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:0> enable or disable each pull-up (see Register12-10). Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the WPUEN bit of the OPTION_REG register. 12.5.2 INTERRUPT-ON-CHANGE All of the PORTB pins are individually configurable as an interrupt-on-change pin. Control bits IOCB<7:0> enable or disable the interrupt function for each pin. The interrupt-on-change feature is disabled on a Power-on Reset. Reference Section13.0 “Interrupt-On-Change” for more information. DS40001574C-page 128  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 12.5.4 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table12-6. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the priority list. TABLE 12-6: PORTB OUTPUT PRIORITY Pin Name Function Priority(1) RB0 SEG0 (LCD) CCP4, 28-pin only RB0 RB1 P1C (ECCP1), 28-pin only RB1 RB2 P1B (ECCP1), 28-pin only RB2 RB3 CCP2/P2A RB3 RB4 COM0 P1D, 28-pin only RB4 RB5 COM1 P2B, 28-pin only CCP3/P3A RB5 RB6 ICSPCLK (Programming) ICDCLK (enabled by Config. Word) SEG14 (LCD) RB6 RB7 ICSPDAT (Programming) ICDDAT (enabled by Config. Word) SEG13 (LCD) RB7 Note 1: Priority listed from highest to lowest.  2011-2013 Microchip Technology Inc. DS40001574C-page 129

PIC16(L)F1938/9 12.6 Register Definitions: PORTB Control REGISTER 12-6: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RB<7:0>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 12-7: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output REGISTER 12-8: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 LATB<7:0>: PORTB Output Latch Value bits(1) Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. DS40001574C-page 130  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 12-9: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Function on Pins RB<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 12-10: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output.  2011-2013 Microchip Technology Inc. DS40001574C-page 131

PIC16(L)F1938/9 TABLE 12-7: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — CHS<4:0> GO/DONE ADON 155 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 131 APFCON — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 123 CCPxCON PxM<1:0> DCxB<1:0> CCPxM<3:0> 228 CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 321 CPSCON1 — — — — CPSCH<3:> 322 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 145 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 145 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 145 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 130 LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 327 LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 331 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 331 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 187 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 130 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 198 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 130 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 131 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. DS40001574C-page 132  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 12.7 PORTC Registers 12.7.1 PORTC FUNCTIONS AND OUTPUT PRIORITIES PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC Each PORTC pin is multiplexed with other functions. The (Register12-12). Setting a TRISC bit (= 1) will make the pins, their combined functions and their output priorities corresponding PORTC pin an input (i.e., put the are shown in Table12-8. corresponding output driver in a High-Impedance mode). When multiple outputs are enabled, the actual pin Clearing a TRISC bit (= 0) will make the corresponding control goes to the peripheral with the highest priority. PORTC pin an output (i.e., enable the output driver and Analog input and some digital input functions are not put the contents of the output latch on the selected pin). included in the list below. These input functions can Example12-1 shows how to initialize an I/O port. remain active when the pin is configured as an output. Reading the PORTC register (Register12-11) reads the Certain digital input functions override other port status of the pins, whereas writing to it will write to the functions and are included in priority list. PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the TABLE 12-8: PORTC OUTPUT PRIORITY port pins are read, this value is modified and then written to the PORT data latch (LATC). Pin Name Function Priority(1) The TRISC register (Register12-12) controls the RC0 T1OSO (Timer1 Oscillator) PORTC pin output drivers, even when they are being CCP2/P2B used as analog inputs. The user should ensure the bits in RC0 the TRISC register are maintained set when using them RC1 T1OSI (Timer1 Oscillator) as analog inputs. I/O pins configured as analog inputs CCP2/P2A always read ‘0’. RC1 RC2 SEG3 (LCD) CCP1/P1A RC2 RC3 SEG6 (LCD) SCL (MSSP) SCK (MSSP) RC3 RC4 SEG11 (LCD) SDA (MSSP) RC4 RC5 SEG10 (LCD) SDO (MSSP) RC5 RC6 ISEG9 (LCD) TX (EUSART) CK (EUSART) CCP3/P3A, 28-pin only RC6 RC7 SEG8 (LCD) DT (EUSART) CCP3/P3B, 28 pin only RC7 Note 1: Priority listed from highest to lowest.  2011-2013 Microchip Technology Inc. DS40001574C-page 133

PIC16(L)F1938/9 12.8 Register Definitions: PORTC Control REGISTER 12-11: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 12-12: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output REGISTER 12-13: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits(1) Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. DS40001574C-page 134  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 12-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 123 CCPxCON PxM<1:0> DCxB<1:0> CCPxM<3:0> 228 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 134 LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 327 LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 331 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 331 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 134 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 297 SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 283 SSPSTAT SMP CKE D/A P S R/W UA BF 282 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 197 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 296 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.  2011-2013 Microchip Technology Inc. DS40001574C-page 135

PIC16(L)F1938/9 12.9 PORTD Registers 12.9.2 PORTD FUNCTIONS AND OUTPUT (PIC16(L)F1939 only) PRIORITIES Each PORTD pin is multiplexed with other functions. The PORTD is a 8-bit wide, bidirectional port. The pins, their combined functions and their output priorities corresponding data direction register is TRISD are shown in Table12-10. (Register12-14). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the When multiple outputs are enabled, the actual pin corresponding output driver in a High-Impedance mode). control goes to the peripheral with the highest priority. Clearing a TRISD bit (= 0) will make the corresponding Analog input and some digital input functions are not PORTD pin an output (i.e., enable the output driver and included in the list below. These input functions can put the contents of the output latch on the selected pin). remain active when the pin is configured as an output. Example12-1 shows how to initialize an I/O port. Certain digital input functions override other port Reading the PORTD register (Register12-14) reads the functions and are included in priority list. status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write TABLE 12-10: PORTD OUTPUT PRIORITY operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written Pin Name Function Priority(1) to the PORT data latch (LATD). RD0 COM3 (LCD) Note: PORTD is available on PIC16(L)F1939 RD0 only. RD1 CCP4 (CCP) RD1 The TRISD register (Register12-15) controls the PORTD pin output drivers, even when they are being RD2 P2B (CCP) used as analog inputs. The user should ensure the bits RD2 in the TRISD register are maintained set when using RD3 SEG16 (LCD) them as analog inputs. I/O pins configured as analog P2C (CCP) inputs always read ‘0’. RD3 12.9.1 ANSELD REGISTER RD4 SEG17 (LCD) P2D (CCP) The ANSELD register (Register12-17) is used to RD4 configure the Input mode of an I/O pin to analog. RD5 SEG18 (LCD) Setting the appropriate ANSELD bit high will cause all P1B (CCP) digital reads on the pin to be read as ‘0’ and allow RD5 analog functions on the pin to operate correctly. RD6 SEG19 (LCD) The state of the ANSELD bits has no effect on digital P1C (CCP) output functions. A pin with TRIS clear and ANSEL set RD6 will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior RD7 SEG20 (LCD) when executing read-modify-write instructions on the P1D (CCP) affected port. RD7 Note 1: Priority listed from highest to lowest. Note: The ANSELD bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. DS40001574C-page 136  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 12.10 Register Definitions: PORTD Control REGISTER 12-14: PORTD: PORTD REGISTER(1) R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: PORTD is not implemented on PIC16(L)F1938 devices, read as ‘0’. REGISTER 12-15: TRISD: PORTD TRI-STATE REGISTER(1) R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output Note 1: TRISD is not implemented on PIC16(L)F1938 devices, read as ‘0’. 2: PORTD implemented on PIC16(L)F1939 devices only.  2011-2013 Microchip Technology Inc. DS40001574C-page 137

PIC16(L)F1938/9 REGISTER 12-16: LATD: PORTD DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 LATD<7:0>: PORTD Output Latch Value bits(1,2) Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is return of actual I/O pin values. 2: PORTD implemented on PIC16(L)F1939 devices only. REGISTER 12-17: ANSELD: PORTD ANALOG SELECT REGISTER(2) R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RD<7:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2: ANSELD register is not implemented on the PIC16(L)F1938. Read as ‘0’. 3: PORTD implemented on PIC16(L)F1939 devices only. TABLE 12-11: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1) Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 138 CCPxCON PxM<1:0> DCxB<1:0> CCPxM<3:0> 228 CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 321 CPSCON1 — — — — CPSCH<3:0> 322 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 138 LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 327 LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 331 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 137 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 137 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers are not implemented on the PIC16(L)F1938 devices, read as ‘0’. DS40001574C-page 138  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 12.11 PORTE Registers 12.11.2 PORTE FUNCTIONS AND OUTPUT PRIORITIES PORTE is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a Each PORTE pin is multiplexed with other functions. The TRISE bit (= 1) will make the corresponding PORTE pin pins, their combined functions and their output priorities an input (i.e., put the corresponding output driver in a are shown in Table12-12. High-Impedance mode). Clearing a TRISE bit (= 0) will When multiple outputs are enabled, the actual pin make the corresponding PORTE pin an output (i.e., control goes to the peripheral with the lowest number in enable the output driver and put the contents of the the following lists. output latch on the selected pin). The exception is RE3, Analog input and some digital input functions are not which is input only and its TRIS bit will always read as included in the list below. These input functions can ‘1’. Example12-1 shows how to initialize an I/O port. remain active when the pin is configured as an output. Reading the PORTE register (Register12-18) reads Certain digital input functions override other port the status of the pins, whereas writing to it will write to functions and are included in priority list. the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a TABLE 12-12: PORTE OUTPUT PRIORITY port implies that the port pins are read, this value is modified and then written to the PORT data latch Pin Name Function Priority(1) (LATE). RE3 reads ‘0’ when MCLRE = 1. RE0 SEG21 (LCD) Note: RE<2:0> and TRISE<2:0> pins are CCP3/P3A (CCP) available on PIC16(L)F1939 only. RE0 RE1 SEG22 (LCD) 12.11.1 ANSELE REGISTER P3B (CCP) The ANSELE register (Register12-21) is used to RE1 configure the Input mode of an I/O pin to analog. RE2 SEG23 (LCD) Setting the appropriate ANSELE bit high will cause all CCP5 (CCP) digital reads on the pin to be read as ‘0’ and allow RE2 analog functions on the pin to operate correctly. Note 1: Priority listed from highest to lowest. The state of the ANSELE bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. The TRISE register (Register12-19) controls the PORTE pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISE register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. Note: The ANSELE bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software.  2011-2013 Microchip Technology Inc. DS40001574C-page 139

PIC16(L)F1938/9 12.12 Register Definitions: PORTE Control REGISTER 12-18: PORTE: PORTE REGISTER U-0 U-0 U-0 U-0 R-x/u R/W-x/u R/W-x/u R/W-x/u — — — — RE3 RE2(1) RE1(1) RE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 RE<3:0>: PORTE I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: RE<2:0> are not implemented on the PIC16(L)F1938. Read as ‘0’. REGISTER 12-19: TRISE: PORTE TRI-STATE REGISTER U-0 U-0 U-0 U-0 U-1(2) R/W-1 R/W-1 R/W-1 — — — — — TRISE2(1) TRISE1(1) TRISE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 Unimplemented: Read as ‘1’ bit 2-0 TRISE<2:0>: RE<2:0> Tri-State Control bits(1) 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output Note 1: TRISE<2:0> are not implemented on the PIC16(L)F1938. Read as ‘0’. 2: Unimplemented, read as ‘1’. DS40001574C-page 140  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 12-20: LATE: PORTE DATA LATCH REGISTER U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u — — — — — LATE2(2) LATE1(2) LATE0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 LATE<3:0>: PORTE Output Latch Value bits(1) Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of actual I/O pin values. 2: LATE register is not implemented on the PIC16(L)F1938. Read as ‘0’ REGISTER 12-21: ANSELE: PORTE ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 — — — — — ANSE2(2) ANSE1(2) ANSE0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSE<2:0>: Analog Select between Analog or Digital Function on Pins RE<2:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2: ANSELE register is not implemented on the PIC16(L)F1938. Read as ‘0’  2011-2013 Microchip Technology Inc. DS40001574C-page 141

PIC16(L)F1938/9 REGISTER 12-22: WPUE: WEAK PULL-UP PORTE REGISTER U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0 — — — — WPUE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 WPUE: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 2-0 Unimplemented: Read as ‘0’ Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — CHS<4:0> GO/DONE ADON 155 ANSELE — — — — — ANSE2(1) ANSE1(1) ANSE0(1) 141 CCPxCON PxM<1:0> DCxB<1:0> CCPxM<3:0> 228 LATE — — — — — LATE2(1) LATE1(1) LATE0(1) 141 LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 327 LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 331 PORTE — — — — RE3 RE2(1) RE1(1) RE0(1) 140 TRISE — — — — —(2) TRISE2(1) TRISE1(1) TRISE0(1) 140 WPUE — — — — WPUE3 — — — 142 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Note 1: These bits are not implemented on the PIC16(L)F1938 devices, read as ‘0’. 2: Unimplemented, read as ‘1’. DS40001574C-page 142  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 13.0 INTERRUPT-ON-CHANGE 13.3 Interrupt Flags The PORTB pins can be configured to operate as The IOCBFx bits located in the IOCBF register are Interrupt-On-Change (IOC) pins. An interrupt can be status flags that correspond to the Interrupt-on-change generated by detecting a signal that has either a rising pins of PORTB. If an expected edge is detected on an edge or a falling edge. Any individual PORT IOC pin, or appropriately enabled pin, then the status flag for that pin combination of PORT IOC pins, can be configured to will be set, and an interrupt will be generated if the IOCIE generate an interrupt. The Interrupt-on-change module bit is set. The IOCIF bit of the INTCON register reflects has the following features: the status of all IOCBFx bits. • Interrupt-on-Change enable (Master Switch) 13.4 Clearing Interrupt Flags • Individual pin configuration • Rising and falling edge detection The individual status flags, (IOCBFx bits), can be • Individual pin interrupt flags cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated Figure13-1 is a block diagram of the IOC module. status flag will be set at the end of the sequence, regardless of the value actually being written. 13.1 Enabling the Module In order to ensure that no detected edge is lost while To allow individual PORTB pins to generate an interrupt, clearing flags, only AND operations masking out known the IOCIE bit of the INTCON register must be set. If the changed bits should be performed. The following IOCIE bit is disabled, the edge detection on the pin will sequence is an example of what should be performed. still occur, but an interrupt will not be generated. EXAMPLE 13-1: CLEARING INTERRUPT 13.2 Individual Pin Configuration FLAGS (PORTA EXAMPLE) For each PORTB pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a MOVLW 0xff rising edge, the associated IOCBPx bit of the IOCBP XORWF IOCBF, W register is set. To enable a pin to detect a falling edge, ANDWF IOCBF, F the associated IOCBNx bit of the IOCBN register is set. A pin can be configured to detect rising and falling 13.5 Operation in Sleep edges simultaneously by setting both the IOCBPx bit and the IOCBNx bit of the IOCBP and IOCBN registers, The interrupt-on-change interrupt sequence will wake respectively. the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCBF register will be updated prior to the first instruction executed out of Sleep.  2011-2013 Microchip Technology Inc. DS40001574C-page 143

PIC16(L)F1938/9 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q Q4Q1 CK edge detect R RBx data bus = S to data bus IOCBPx D Q 0 or 1 D Q IOCBFx CK write IOCBFx CK IOCIE R Q2 from all other IOCBFx individual IOC interrupt pin detectors to CPU core Q1 Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q3 Q4 Q4 Q4 Q4 Q4Q1 Q4Q1 Q4Q1 Q4Q1 DS40001574C-page 144  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 13.6 Register Definitions: Interrupt-On-Change REGISTER 13-1: IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-2: IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBN<7:0>: Interrupt-on-Change Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-3: IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-0 IOCBF<7:0>: Interrupt-on-Change Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx=1 and a rising edge was detected on RBx, or when IOCBNx=1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change.  2011-2013 Microchip Technology Inc. DS40001574C-page 145

PIC16(L)F1938/9 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 131 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 145 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 145 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 145 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 130 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change. DS40001574C-page 146  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 14.0 FIXED VOLTAGE REFERENCE 14.1 Independent Gain Amplifiers (FVR) The output of the FVR supplied to the ADC, Comparators, DAC and CPS is routed through two The Fixed Voltage Reference, or FVR, is a stable independent programmable gain amplifiers. Each voltage reference, independent of VDD, with 1.024V, amplifier can be configured to amplify the reference 2.048V or 4.096V selectable output levels. The output voltage by 1x, 2x or 4x, to produce the three possible of the FVR can be configured to supply a reference voltage levels. voltage to the following: The ADFVR<1:0> bits of the FVRCON register are • ADC input channel used to enable and configure the gain amplifier settings • ADC positive reference for the reference supplied to the ADC module. Refer- • Comparator positive input ence Section15.0 “Analog-to-Digital Converter • Digital-to-Analog Converter (DAC) (ADC) Module” for additional information. • Capacitive Sensing (CPS) module The CDAFVR<1:0> bits of the FVRCON register are used • LCD bias generator to enable and configure the gain amplifier settings for the The FVR can be enabled by setting the FVREN bit of reference supplied to the DAC, CPS and Comparator module. Reference Section17.0 “Digital-to-Analog the FVRCON register. Converter (DAC) Module”, Section18.0 “Comparator Module” and Section26.0 “Capacitive Sensing (CPS) Module” for additional information. 14.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See in the applicable Electrical Specifications Chapter for the minimum delay requirement. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 X1 X2 FVR BUFFER1 X4 (To ADC Module) CDAFVR<1:0> 2 X1 X2 FVR BUFFER2 X4 (To Comparators, DAC) FVR VREF 1.024V Fixed (To LCD Bias Generator) Reference + FVREN _ FVRRDY Any peripheral requiring the Fixed Reference (See Table14-1)  2011-2013 Microchip Technology Inc. DS40001574C-page 147

PIC16(L)F1938/9 14.3 Register Definitions: FVR Control REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FVREN FVRRDY(1) TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bit 11 =Comparator and DAC and CPS Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 =Comparator and DAC and CPS Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 =Comparator and DAC and CPS Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 =Comparator and DAC and CPS Fixed Voltage Reference Peripheral output is off bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit 11 =ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 =ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 =ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 =ADC Fixed Voltage Reference Peripheral output is of Note 1: FVRRDY is always ‘1’ on devices with LDO (PIC16F193X). 2: Fixed Voltage Reference output cannot exceed VDD. 3: See Section16.0 “Temperature Indicator Module” for additional information. TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 148 Legend: Shaded cells are not used with the Fixed Voltage Reference. DS40001574C-page 148  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 15.0 ANALOG-TO-DIGITAL The ADC can generate an interrupt upon completion of CONVERTER (ADC) MODULE a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure15-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 15-1: ADC BLOCK DIAGRAM VREF- ADNREF = 1 ADNREF = 0 VSS VDD ADPREF = 00 ADPREF = 11 VREF+ ADPREF = 10 AN0 00000 AN1 00001 VREF-/AN2 00010 VREF+/AN3 00011 AN4 00100 AN5(2) 00101 AN6(2) 00110 AN7(2) 00111 Ref+ Ref- AN8 01000 ADC AN9 01001 GO/DONE 10 AN10 01010 AN11 01011 ADFM 0 = Left Justify 1 = Right Justify AN12 01100 ADON(1) 16 AN13 01101 VSS ADRESH ADRESL Temperature Indicator 11101 DAC_output 11110 FVR Buffer1 11111 CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: Not available on PIC16(L)F1938.  2011-2013 Microchip Technology Inc. DS40001574C-page 149

PIC16(L)F1938/9 15.1 ADC Configuration 15.1.4 CONVERSION CLOCK When configuring and using the ADC the following The source of the conversion clock is software select- functions must be considered: able via the ADCS bits of the ADCON1 register. There are seven possible clock options: • Port configuration • FOSC/2 • Channel selection • FOSC/4 • ADC voltage reference selection • FOSC/8 • ADC conversion clock source • FOSC/16 • Interrupt control • FOSC/32 • Result formatting • FOSC/64 15.1.1 PORT CONFIGURATION • FRC (dedicated internal oscillator) The ADC can be used to convert both analog and The time to complete one bit conversion is defined as digital signals. When converting analog signals, the I/O TAD. One full 10-bit conversion requires 11.5 TAD pin should be configured for analog by setting the periods as shown in Figure15-2. associated TRIS and ANSEL bits. Refer to For correct conversion, the appropriate TAD specifica- Section12.0 “I/O Ports” for more information. tion must be met. Refer to the A/D conversion require- Note: Analog voltages on any pin that is defined ments in the applicable Electrical Specifications as a digital input may cause the input buf- Chapter for more information. Table15-1 gives exam- fer to conduct excess current. ples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the 15.1.2 CHANNEL SELECTION system clock frequency will change the There are up to 17 channel selections available: ADC clock frequency, which may adversely affect the ADC result. • AN<13:0> pins • Temperature Indicator • DAC Output • FVR (Fixed Voltage Reference) Output Refer to Section16.0 “Temperature Indicator Mod- ule”, Section17.0 “Digital-to-Analog Converter (DAC) Module” and Section14.0 “Fixed Voltage Reference (FVR)” for more information on these chan- nel selections. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section15.2 “ADC Operation” for more information. 15.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: • VREF+ pin • VDD The ADNREF bits of the ADCON1 register provides control of the negative voltage reference. The negative voltage reference can be: • VREF- pin • VSS See Section14.0 “Fixed Voltage Reference (FVR)” for more details on the fixed voltage reference. DS40001574C-page 150  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES Device Frequency (FOSC) ADC Clock Period (TAD) Device Frequency (FOSC) ADC ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Clock Source Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3) Fosc/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3) Fosc/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.0 s(3) Fosc/64 110 2.0 s 3.2 s 4.0 s 8.0 s(3) 16.0 s(3) 64.0 s(3) FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 1.6 s for VDD. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.  2011-2013 Microchip Technology Inc. DS40001574C-page 151

PIC16(L)F1938/9 15.1.5 INTERRUPTS 15.1.6 RESULT FORMATTING The ADC module allows for the ability to generate an The 10-bit A/D conversion result can be supplied in two interrupt upon completion of an Analog-to-Digital formats, left justified or right justified. The ADFM bit of conversion. The ADC Interrupt Flag is the ADIF bit in the ADCON1 register controls the output format. the PIR1 register. The ADC Interrupt Enable is the Figure15-3 shows the two output formats. ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruc- tion is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execu- tion, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. FIGURE 15-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result DS40001574C-page 152  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 15.2 ADC Operation 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This 15.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC To enable the ADC module, the ADON bit of the option. When the FRC clock source is selected, the ADCON0 register must be set to a ‘1’. Setting the GO/ ADC waits one additional instruction before starting the DONE bit of the ADCON0 register to a ‘1’ will start the conversion. This allows the SLEEP instruction to be Analog-to-Digital conversion. executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device Note: The GO/DONE bit should not be set in the will wake-up from Sleep when the conversion same instruction that turns on the ADC. completes. If the ADC interrupt is disabled, the ADC Refer to Section15.2.6 “A/D Conver- module is turned off after the conversion completes, sion Procedure”. although the ADON bit remains set. 15.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conver- When the conversion is complete, the ADC module will: sion to be aborted and the ADC module is turned off, • Clear the GO/DONE bit although the ADON bit remains set. • Set the ADIF Interrupt Flag bit 15.2.5 SPECIAL EVENT TRIGGER • Update the ADRESH and ADRESL registers with new conversion result The Special Event Trigger of the CCPx/ECCPX module allows periodic ADC measurements without software 15.2.3 TERMINATING A CONVERSION intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to If a conversion must be terminated before completion, zero. the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with TABLE 15-2: SPECIAL EVENT TRIGGER the partially complete Analog-to-Digital conversion Device CCPx/ECCPx sample. Incomplete bits will match the last bit converted. PIC16(L)F193X CCP5 Note: A device Reset forces all registers to their Using the Special Event Trigger does not assure proper Reset state. Thus, the ADC module is ADC timing. It is the user’s responsibility to ensure that turned off and any pending conversion is the ADC timing requirements are met. terminated. Refer to Section23.0 “Capture/Compare/PWM Modules” for more information.  2011-2013 Microchip Technology Inc. DS40001574C-page 153

PIC16(L)F1938/9 15.2.6 A/D CONVERSION PROCEDURE EXAMPLE 15-1: A/D CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. 1. Configure Port: ; • Disable pin output driver (Refer to the TRIS ;Conversion start & polling for completion register) ; are included. • Configure pin as analog (Refer to the ANSEL ; register) BANKSEL ADCON1 ; MOVLW B’11110000’ ;Right justify, Frc 2. Configure the ADC module: ;clock • Select ADC conversion clock MOVWF ADCON1 ;Vdd and Vss Vref • Configure voltage reference BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input • Select ADC input channel BANKSEL ANSEL ; • Turn on ADC module BSF ANSEL,0 ;Set RA0 to analog 3. Configure ADC interrupt (optional): BANKSEL ADCON0 ; • Clear ADC interrupt flag MOVLW B’00000001’ ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On • Enable ADC interrupt CALL SampleTime ;Acquisiton delay • Enable peripheral interrupt BSF ADCON0,ADGO ;Start conversion • Enable global interrupt(1) BTFSC ADCON0,ADGO ;Is conversion done? 4. Wait the required acquisition time(2). GOTO $-1 ;No, test again BANKSEL ADRESH ; 5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits 6. Wait for ADC conversion to complete by one of MOVWF RESULTHI ;store in GPR space the following: BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits • Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result. 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section15.4 “A/D Acquisition Requirements”. DS40001574C-page 154  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 15.3 Register Definitions: ADC Control REGISTER 15-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CHS<4:0> GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 11111 =FVR (Fixed Voltage Reference) Buffer 1 Output(2) 11110 =DAC output(1) 11101 =Temperature Indicator(3) 11100 =Reserved. No channel connected. • • • 01110 =Reserved. No channel connected. 01101 =AN13 01100 =AN12 01011 =AN11 01010 =AN10 01001 =AN9 01000 =AN8 00111 =AN7(4) 00110 =AN6(4) 00101 =AN5(4) 00100 =AN4 00011 =AN3 00010 =AN2 00001 =AN1 00000 =AN0 bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: See Section17.0 “Digital-to-Analog Converter (DAC) Module” for more information. 2: See Section14.0 “Fixed Voltage Reference (FVR)” for more information. 3: See Section16.0 “Temperature Indicator Module” for more information. 4: Not available on the PIC16(L)F1933/1936/1938.  2011-2013 Microchip Technology Inc. DS40001574C-page 155

PIC16(L)F1938/9 REGISTER 15-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded. bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 111 =FRC (clock supplied from a dedicated RC oscillator) 110 =FOSC/64 101 =FOSC/16 100 =FOSC/4 011 =FRC (clock supplied from a dedicated RC oscillator) 010 =FOSC/32 001 =FOSC/8 000 =FOSC/2 bit 3 Unimplemented: Read as ‘0’ bit 2 ADNREF: A/D Negative Voltage Reference Configuration bit 1 = VREF- is connected to external VREF- pin(1) 0 = VREF- is connected to VSS bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits 11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1) 10 = VREF+ is connected to external VREF+ pin(1) 01 = Reserved 00 = VREF+ is connected to VDD Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See the applicable Electrical Specifications Chapter for details. DS40001574C-page 156  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 15-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 15-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<1:0> — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use.  2011-2013 Microchip Technology Inc. DS40001574C-page 157

PIC16(L)F1938/9 REGISTER 15-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 15-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result DS40001574C-page 158  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 15.4 A/D Acquisition Requirements source impedance is decreased, the acquisition time may be decreased. After the analog input channel is For the ADC to meet its specified accuracy, the charge selected (or changed), an A/D acquisition must be holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate charge to the input channel voltage level. The Analog the minimum acquisition time, Equation15-1 may be Input model is shown in Figure15-4. The source used. This equation assumes that 1/2 LSb error is used impedance (RS) and the internal sampling switch (RSS) (1,024 steps for the ADC). The 1/2 LSb error is the impedance directly affect the time required to charge maximum error allowed for the ADC to meet its the capacitor CHOLD. The sampling switch (RSS) specified resolution. impedance varies over the device voltage (VDD), refer to Figure15-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 15-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– ------n----+----1------------ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb 2 –1 –TC  ---------- RC VAPPLIED1–e  = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– ------n---+-----1------------ ;combining [1] and [2]   2  –1 Note: Where n = number of bits of the ADC. Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/2047) = –13.5pF1k+7k+10k ln(0.0004885) = 1.20µs Therefore: TACQ = 2µs+1.20µs+50°C- 25°C0.05µs/°C = 4.45µs Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification.  2011-2013 Microchip Technology Inc. DS40001574C-page 159

PIC16(L)F1938/9 FIGURE 15-4: ANALOG INPUT MODEL VDD Analog Sampling Input Switch VT  0.6V Rs pin RIC  1k SS Rss VA C5 PpIFN VT  0.6V I LEAKAGE(1) CHOLD = 10 pF VSS/VREF- 6V 5V RSS Legend: CHOLD = Sample/Hold Capacitance VDD4V 3V CPIN = Input Capacitance 2V I LEAKAGE = Leakage current at the pin due to various junctions 5 6 7891011 RIC = Interconnect Resistance Sampling Switch RSS = Resistance of Sampling Switch (k) SS = Sampling Switch VT = Threshold Voltage Note 1: Refer to in the applicable Electrical Specifications Chapter. FIGURE 15-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh 3FCh e od 3FBh C ut p ut O C D 03h A 02h 01h 00h Analog Input Voltage 0.5 LSB 1.5 LSB Zero-Scale VREF- Transition Full-Scale Transition VREF+ DS40001574C-page 160  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — CHS<4:0> GO/DONE ADON 155 ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 156 ADRESH A/D Result Register High 157 ADRESL A/D Result Register Low 157 ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 126 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 131 ANSELE — — — — — ANSE2 ANSE1 ANSE0 141 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 228 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 130 TRISE — — — — —(2) TRISE2(1) TRISE1(1) TRISE0(1) 140 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 148 DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 168 DACCON1 — — — DACR<4:0> 168 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for ADC module. Note 1: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 2: Unimplemented, read as ‘1’.  2011-2013 Microchip Technology Inc. DS40001574C-page 161

PIC16(L)F1938/9 NOTES: DS40001574C-page 162  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 16.0 TEMPERATURE INDICATOR FIGURE 16-1: TEMPERATURE CIRCUIT MODULE DIAGRAM This family of devices is equipped with a temperature circuit designed to measure the operating temperature VDD of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The TSEN output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. TSRNG The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A one- point calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point VOUT To ADC calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal Temperature Indicator” (DS01333) for more details regarding the calibration process. 16.1 Circuit Operation 16.2 Minimum Operating VDD Figure16-1 shows a simplified block diagram of the When the temperature circuit is operated in low range, temperature circuit. The proportional voltage output is the device may be operated at any operating voltage achieved by measuring the forward voltage drop across that is within specifications. multiple silicon junctions. When the temperature circuit is operated in high range, Equation16-1 describes the output characteristics of the device operating voltage, VDD, must be high the temperature indicator. enough to ensure that the temperature circuit is correctly biased. EQUATION 16-1: VOUT RANGES Table16-1 shows the recommended minimum VDD vs. range setting. High Range: VOUT = VDD - 4VT TABLE 16-1: RECOMMENDED VDD VS. Low Range: VOUT = VDD - 2VT RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 The temperature sense circuit is integrated with the 3.6V 1.8V Fixed Voltage Reference (FVR) module. See Section14.0 “Fixed Voltage Reference (FVR)” for 16.3 Temperature Output more information. The output of the circuit is measured using the internal The circuit is enabled by setting the TSEN bit of the Analog-to-Digital Converter. A channel is reserved for FVRCON register. When disabled, the circuit draws no the temperature circuit output. Refer to Section15.0 current. “Analog-to-Digital Converter (ADC) Module” for The circuit operates in either high or low range. The high detailed information. range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This 16.4 ADC Acquisition Time provides more resolution over the temperature range, but may be less consistent from part to part. This range To ensure accurate temperature measurements, the requires a higher bias voltage to operate and thus, a user must wait at least 200s after the ADC input higher VDD is needed. multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, The low range is selected by clearing the TSRNG bit of the user must wait 200s between sequential the FVRCON register. The low range generates a lower conversions of the temperature indicator output. voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.  2011-2013 Microchip Technology Inc. DS40001574C-page 163

PIC16(L)F1938/9 TABLE 16-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR<1:0> 118 Legend: Shaded cells are unused by the temperature indicator module. DS40001574C-page 164  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 17.0 DIGITAL-TO-ANALOG 17.1 Output Voltage Selection CONVERTER (DAC) MODULE The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 The Digital-to-Analog Converter supplies a variable register. voltage reference, ratiometric with the input source, with 32 selectable output levels. The DAC output voltage is determined by the following equations: The input of the DAC can be connected to: • External VREF pins • VDD supply voltage • FVR (Fixed Voltage Reference) The output of the DAC can be configured to supply a reference voltage to the following: • Comparator positive input • ADC input channel • DACOUT pin • Capacitive Sensing module (CPS) The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register. EQUATION 17-1: DAC OUTPUT VOLTAGE IF DACEN = 1  DACR4:0 VOUT = VSOURCE+–VSOURCE------------------------------ +VSOURCE-  5  2 IF DACEN = 0 & DACLPS = 1 & DACR[4:0] = 11111 VOUT = VSOURCE+ IF DACEN = 0 & DACLPS = 0 & DACR[4:0] = 00000 VOUT = VSOURCE– VSOURCE+ = VDD, VREF, or FVR BUFFER 2 VSOURCE- = VSS 17.2 Ratiometric Output Level 17.3 DAC Voltage Reference Output The DAC output value is derived using a resistor ladder The DAC can be output to the DACOUT pin by setting with each end of the ladder tied to a positive and the DACOE bit of the DACCON0 register to ‘1’. negative voltage reference input source. If the voltage Selecting the DAC reference voltage for output on the of either input source fluctuates, a similar fluctuation will DACOUT pin automatically overrides the digital output result in the DAC output value. buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been The value of the individual resistors within the ladder configured for DAC reference voltage output will can be found in Section30.0 “Electrical always return a ‘0’. Specifications”. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to DACOUT. Figure17-2 shows an example buffering technique.  2011-2013 Microchip Technology Inc. DS40001574C-page 165

PIC16(L)F1938/9 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSOURCE+ VDD DACR<4:0> 5 VREF+ R R DACPSS<1:0> 2 R DACEN DACLPS R R X 32 U DAC Output (to Comparator M and Steps 1 ADC modules) o- 2-t R 3 R DACOUT R DACOE DACNSS VREF- VSOURCE- VSS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC R Module + Voltage DACOUT – Buffered DAC Output Reference Output Impedance DS40001574C-page 166  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 17.4 Low-Power Voltage State This is also the method used to output the voltage level from the FVR to an output pin. See Section17.5 In order for the DAC module to consume the least “Operation During Sleep” for more information. amount of power, one of the two voltage reference input Reference Figure17-3 for output clamping examples. sources to the resistor ladder must be disconnected. Either the positive voltage source, (VSOURCE+), or the 17.4.2 OUTPUT CLAMPED TO NEGATIVE negative voltage source, (VSOURCE-) can be disabled. VOLTAGE SOURCE The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the The DAC output voltage can be set to VSOURCE- with the least amount of power consumption by performing DACLPS bit in the DACCON0 register disables the the following: positive voltage source. • Clearing the DACEN bit in the DACCON0 register. 17.4.1 OUTPUT CLAMPED TO POSITIVE • Clearing the DACLPS bit in the DACCON0 register. VOLTAGE SOURCE • Configuring the DACNSS bits to the proper The DAC output voltage can be set to VSOURCE+ with negative source. the least amount of power consumption by performing • Configuring the DACR<4:0> bits to ‘00000’ in the the following: DACCON1 register. • Clearing the DACEN bit in the DACCON0 register. This allows the comparator to detect a zero-crossing • Setting the DACLPS bit in the DACCON0 register. while not consuming additional current through the DAC • Configuring the DACPSS bits to the proper module. positive source. Reference Figure17-3 for output clamping examples. • Configuring the DACR<4:0> bits to ‘11111’ in the DACCON1 register. FIGURE 17-3: OUTPUT VOLTAGE CLAMPING EXAMPLES Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source VSOURCE+ VSOURCE+ R R DACR<4:0> = 11111 R R DACEN = 0 DACEN = 0 DACLPS = 1 DAC Voltage Ladder DACLPS = 0 DAC Voltage Ladder (see Figure17-1) (see Figure17-1) R R DACR<4:0> = 00000 VSOURCE- VSOURCE- 17.5 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 17.6 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared.  2011-2013 Microchip Technology Inc. DS40001574C-page 167

PIC16(L)F1938/9 17.7 Register Definitions: DAC Control REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 DACLPS: DAC Low-Power Voltage State Select bit 1 = DAC Positive reference source selected 0 = DAC Negative reference source selected bit 5 DACOE: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin bit 4 Unimplemented: Read as ‘0’ bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits 11 = Reserved, do not use 10 = FVR Buffer2 output 01 = VREF+ pin 00 = VDD bit 1 Unimplemented: Read as ‘0’ bit 0 DACNSS: DAC Negative Source Select bits 1 = VREF- 0 = VSS REGISTER 17-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — DACR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR<4:0>: DAC Voltage Output Select bits TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 148 DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 168 DACCON1 — — — DACR<4:0> 168 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module. DS40001574C-page 168  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 18.0 COMPARATOR MODULE FIGURE 18-1: SINGLE COMPARATOR Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and VIN+ + providing a digital indication of their relative magnitudes. Output Comparators are very useful mixed signal building VIN- – blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: • Independent comparator control VIN- • Programmable input selection VIN+ • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change Output • Wake-up from Sleep • Programmable Speed/Power optimization • PWM shutdown Note: The black areas of the output of the • Programmable and fixed voltage reference comparator represents the uncertainty 18.1 Comparator Overview due to input offsets and response time. A single comparator is shown in Figure18-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level.  2011-2013 Microchip Technology Inc. DS40001574C-page 169

PIC16(L)F1938/9 FIGURE 18-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<1:0> CxON(1) 2 Interrupt CxINTP det C12IN0- 0 Set CxIF C12IN1- 1 MUX Interrupt CxINTN C12IN2- 2 (2) det CXPOL C12IN3- 3 CxVN - to CMxCON0 (CxOUT) Cx(3) D Q and CM2CON1 (MCxOUT) + CxVP Q1 EN CXIN+ 0 MUX CxHYS DAC Output 1 (2) CxSP async_CxOUT to PWM FVR Buffer2 2 3 CXSYNC VSS CxON CXOE TRIS bit CXPCH<1:0> 0 CXOUT 2 D Q 1 (from Timer1) T1CLK to T1G MUX and SR Latch sync_CxOUT Note 1: When CxON = 0, the Comparator will produce a ‘0’ at the output. 2: When CxON = 0, all multiplexer inputs are disconnected. 3: Output of comparator can be frozen during debugging. DS40001574C-page 170  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 18.2 Comparator Control 18.2.3 COMPARATOR OUTPUT POLARITY Each comparator has two control registers: CMxCON0 Inverting the output of the comparator is functionally and CMxCON1. equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by The CMxCON0 registers (see Register18-1) contain setting the CxPOL bit of the CMxCON0 register. Control and Status bits for the following: Clearing the CxPOL bit results in a non-inverted output. • Enable Table18-1 shows the output state versus input • Output selection conditions, including polarity control. • Output polarity TABLE 18-1: COMPARATOR OUTPUT • Speed/Power selection STATE VS. INPUT • Hysteresis enable CONDITIONS • Output synchronization Input Condition CxPOL CxOUT The CMxCON1 registers (see Register18-2) contain CxVN > CxVP 0 0 Control bits for the following: CxVN < CxVP 0 1 • Interrupt enable CxVN > CxVP 1 1 • Interrupt edge polarity CxVN < CxVP 1 0 • Positive input channel selection • Negative input channel selection 18.2.4 COMPARATOR SPEED/POWER SELECTION 18.2.1 COMPARATOR ENABLE The trade-off between speed or power can be opti- Setting the CxON bit of the CMxCON0 register enables mized during program execution with the CxSP control the comparator for operation. Clearing the CxON bit bit. The default state for this bit is ‘1’ which selects the disables the comparator resulting in minimum current Normal speed mode. Device power consumption can consumption. be optimized at the cost of slower comparator propaga- 18.2.2 COMPARATOR OUTPUT tion delay by clearing the CxSP bit to ‘0’. SELECTION The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set Note1: The CxOE bit of the CMxCON0 register overrides the PORT data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched.  2011-2013 Microchip Technology Inc. DS40001574C-page 171

PIC16(L)F1938/9 18.3 Comparator Hysteresis 18.5 Comparator Interrupt A selectable amount of separation voltage can be An interrupt can be generated upon a change in the added to the input pins of each comparator to provide a output value of the comparator for each comparator, a hysteresis function to the overall operation. Hysteresis rising edge detector and a Falling edge detector are is enabled by setting the CxHYS bit of the CMxCON0 present. register. When either edge detector is triggered and its associ- See Section30.0 “Electrical Specifications” for ated enable bit is set (CxINTP and/or CxINTN bits of more information. the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. 18.4 Timer1 Gate Operation To enable the interrupt, you must set the following bits: The output resulting from a comparator operation can • CxON, CxPOL and CxSP bits of the CMxCON0 be used as a source for gate control of Timer1. See register Section21.6 “Timer1 Gate” for more information. • CxIE bit of the PIE2 register This feature is useful for timing the duration or interval • CxINTP bit of the CMxCON1 register (for a rising of an analog event. edge detection) It is recommended that the comparator output be • CxINTN bit of the CMxCON1 register (for a falling synchronized to Timer1. This ensures that Timer1 does edge detection) not increment while a change in the comparator is • PEIE and GIE bits of the INTCON register occurring. The associated interrupt flag bit, CxIF bit of the PIR2 18.4.1 COMPARATOR OUTPUT register, must be cleared in software. If another edge is SYNCHRONIZATION detected while this flag is being cleared, the flag will still be set at the end of the sequence. The output from either comparator, C1 or C2, can be synchronized with Timer1 by setting the CxSYNC bit of Note: Although a comparator is disabled, an the CMxCON0 register. interrupt can be generated by changing the output polarity with the CxPOL bit of Once enabled, the comparator output is latched on the the CMxCON0 register, or by switching falling edge of the Timer1 source clock. If a prescaler is the comparator on or off with the CxON bit used with Timer1, the comparator output is latched after of the CMxCON0 register. the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the 18.6 Comparator Positive Input Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Selection Block Diagram (Figure18-2) and the Timer1 Block Configuring the CxPCH<1:0> bits of the CMxCON1 Diagram (Figure21-1) for more information. register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: • CxIN+ analog pin • DAC Output • FVR (Fixed Voltage Reference) • VSS (Ground) See Section14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section17.0 “Digital-to-Analog Converter (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. DS40001574C-page 172  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 18.7 Comparator Negative Input 18.10 Analog Input Connection Selection Considerations The CxNCH<1:0> bits of the CMxCON0 register direct A simplified circuit for an analog input is shown in one of four analog pins to the comparator inverting Figure18-3. Since the analog input pins share their input. connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The Note: To use CxIN+ and CxINx- pins as analog analog input, therefore, must be between VSS and VDD. input, the appropriate bits must be set in If the input voltage deviates from this range by more the ANSEL register and the correspond- than 0.6V in either direction, one of the diodes is for- ing TRIS bits must also be set to disable ward biased and a latch-up may occur. the output drivers. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component 18.8 Comparator Response Time connected to an analog input pin, such as a capacitor or The comparator output is indeterminate for a period of a Zener diode, should have very little leakage current to time after the change of an input source or the selection minimize inaccuracies introduced. of a new reference voltage. This period is referred to as the response time. The response time of the comparator Note1: When reading a PORT register, all pins differs from the settling time of the voltage reference. configured as analog inputs will read as a Therefore, both of these times must be considered when ‘0’. Pins configured as digital inputs will determining the total response time to a comparator convert as an analog input, according to input change. See the Comparator and Voltage Refer- the input specification. ence Specifications in Section30.0 “Electrical Specifi- cations” for more details. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to 18.9 Interaction with ECCP Logic consume more current than is specified. The C1 and C2 comparators can be used as general purpose comparators. Their outputs can be brought out to the C1OUT and C2OUT pins. When the ECCP Auto-Shutdown is active it can use one or both comparator signals. If auto-restart is also enabled, the comparators can be configured as a closed loop analog feedback to the ECCP, thereby, creating an analog controlled PWM. Note: When the Comparator module is first initialized the output state is unknown. Upon initialization, the user should verify the output state of the comparator prior to relying on the result, primarily when using the result in connection with other peripheral features, such as the ECCP Auto-Shutdown mode.  2011-2013 Microchip Technology Inc. DS40001574C-page 173

PIC16(L)F1938/9 FIGURE 18-3: ANALOG INPUT MODEL VDD Analog Input Rs < 10K pin VT  0.6V RIC To Comparator VA C5 PpIFN VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage Note1: See Section30.0 “Electrical Specifications”. DS40001574C-page 174  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 18.11 Register Definitions: Comparator Control REGISTER 18-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and consumes no active power bit 6 CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous.  2011-2013 Microchip Technology Inc. DS40001574C-page 175

PIC16(L)F1938/9 REGISTER 18-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 CxINTP CxINTN CxPCH<1:0> — — CxNCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits 11 = CxVP connects to VSS 10 = CxVP connects to FVR Voltage Reference 01 = CxVP connects to DAC Voltage Reference 00 = CxVP connects to CxIN+ pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CxNCH<1:0>: Comparator Negative Input Channel Select bits 11 = CxVN connects to C12IN3- pin 10 = CxVN connects to C12IN2- pin 01 = CxVN connects to C12IN1- pin 00 = CxVN connects to C12IN0- pin REGISTER 18-3: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0 — — — — — — MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit DS40001574C-page 176  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CM1CON0 C1ON C1OUT C1OE C1POL --- C1SP C1HYS C1SYNC 175 CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 175 CM1CON1 C1NTP C1INTN C1PCH<1:0> — — C1NCH<1:0> 176 CM2CON1 C2NTP C2INTN C2PCH<1:0> — — C2NCH<1:0> 176 CMOUT — — — — — — MC2OUT MC1OUT 176 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 148 DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 168 DACCON1 — — — DACR<4:0> 168 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 92 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 95 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 130 ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 126 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 131 Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.  2011-2013 Microchip Technology Inc. DS40001574C-page 177

PIC16(L)F1938/9 NOTES: DS40001574C-page 178  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 19.0 SR LATCH The module consists of a single SR Latch with multiple Set and Reset inputs as well as separate latch outputs. The SR Latch module includes the following features: • Programmable input selection • SR Latch output is available externally • Separate Q and Q outputs • Firmware Set and Reset The SR Latch can be used in a variety of analog appli- cations, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing applications. 19.1 Latch Operation The latch is a Set-Reset Latch that does not depend on a clock source. Each of the Set and Reset inputs are active-high. The latch can be Set or Reset by: • Software control (SRPS and SRPR bits) • Comparator C1 output (sync_C1OUT) • Comparator C2 output (sync_C2OUT) • SRI pin • Programmable clock (SRCLK) The SRPS and the SRPR bits of the SRCON0 register may be used to Set or Reset the SR Latch, respec- tively. The latch is Reset-dominant. Therefore, if both Set and Reset inputs are high, the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset operation. The output from Comparator C1 or C2 can be used as the Set or Reset inputs of the SR Latch. The output of either Comparator can be synchronized to the Timer1 clock source. See Section18.0 “Comparator Mod- ule” and Section21.0 “Timer1 Module with Gate Control” for more information. An external source on the SRI pin can be used as the Set or Reset inputs of the SR Latch. An internal clock source is available that can periodically Set or Reset the SR Latch. The SRCLK<2:0> bits in the SRCON0 register are used to select the clock source period. The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to Set or Reset the SR Latch, respectively.  2011-2013 Microchip Technology Inc. DS40001574C-page 179

PIC16(L)F1938/9 19.2 Latch Output 19.3 Effects of a Reset The SRQEN and SRNQEN bits of the SRCON0 regis- Upon any device Reset, the SR Latch output is not ini- ter control the Q and Q latch outputs. Both of the SR tialized to a known state. The user’s firmware is Latch outputs may be directly output to an I/O pin at the responsible for initializing the latch output before same time. The Q latch output pin function can be enabling the output pins. moved to an alternate pin using the SRNQSEL bit of the APFCON register. The applicable TRIS bit of the corresponding port must be cleared to enable the port pin output driver. FIGURE 19-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRLEN SRPS Pulse SRQEN Gen(2) SRI SRSPE S Q SRCLK SRQ SRSCKE sync_C2OUT(3) SRSC2E sync_C1OUT(3) SR SRSC1E Latch(1) SRPR Pulse Gen(2) SRI SRRPE R Q SRCLK SRNQ SRRCKE SRLEN sync_C2OUT(3) SRNQEN SRRC2E sync_C1OUT(3) SRRC1E Note 1: If R=1 and S=1 simultaneously, Q=0, Q=1 2: Pulse generator causes a 1 Q-state pulse width. 3: Name denotes the connection point at the comparator output. DS40001574C-page 180  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 19-1: SRCLK FREQUENCY TABLE SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 62.5kHz 39.0kHz 31.3kHz 7.81kHz 1.95kHz 110 256 125kHz 78.1kHz 62.5kHz 15.6kHz 3.90kHz 101 128 250kHz 156kHz 125kHz 31.25kHz 7.81kHz 100 64 500kHz 313kHz 250kHz 62.5kHz 15.6kHz 011 32 1MHz 625kHz 500kHz 125kHz 31.3 kHz 010 16 2MHz 1.25MHz 1MHz 250kHz 62.5kHz 001 8 4MHz 2.5MHz 2MHz 500kHz 125kHz 000 4 8MHz 5MHz 4MHz 1MHz 250kHz  2011-2013 Microchip Technology Inc. DS40001574C-page 181

PIC16(L)F1938/9 19.4 Register Definitions: SR Latch Control REGISTER 19-1: SRCON0: SR LATCH CONTROL 0 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/S-0/0 R/S-0/0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared S = Bit is set only bit 7 SRLEN: SR Latch Enable bit 1 = SR Latch is enabled 0 = SR Latch is disabled bit 6-4 SRCLK<2:0>: SR Latch Clock Divider bits 111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock 110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock 101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock 100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock 011 = Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock 010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock 001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock 000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock bit 3 SRQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRQ pin 0 = External Q output is disabled If SRLEN = 0: SR Latch is disabled bit 2 SRNQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRnQ pin 0 = External Q output is disabled If SRLEN = 0: SR Latch is disabled bit 1 SRPS: Pulse Set Input of the SR Latch bit(1) 1 = Pulse set input for 1 Q-clock period 0 = No effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit(1) 1 = Pulse reset input for 1 Q-clock period 0 = No effect on reset input. Note 1: Set only, always reads back ‘0’. DS40001574C-page 182  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 19-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SR Latch is set when the SRI pin is high. 0 = SRI pin has no effect on the set input of the SR Latch bit 6 SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR Latch is pulsed with SRCLK 0 = SRCLK has no effect on the set input of the SR Latch bit 5 SRSC2E: SR Latch C2 Set Enable bit 1 = SR Latch is set when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the set input of the SR Latch bit 4 SRSC1E: SR Latch C1 Set Enable bit 1 = SR Latch is set when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the set input of the SR Latch bit 3 SRRPE: SR Latch Peripheral Reset Enable bit 1 = SR Latch is reset when the SRI pin is high. 0 = SRI pin has no effect on the reset input of the SR Latch bit 2 SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR Latch is pulsed with SRCLK 0 = SRCLK has no effect on the reset input of the SR Latch bit 1 SRRC2E: SR Latch C2 Reset Enable bit 1 = SR Latch is reset when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the reset input of the SR Latch bit 0 SRRC1E: SR Latch C1 Reset Enable bit 1 = SR Latch is reset when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the reset input of the SR Latch TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 126 SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 182 SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 183 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the SR Latch module.  2011-2013 Microchip Technology Inc. DS40001574C-page 183

PIC16(L)F1938/9 NOTES: DS40001574C-page 184  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 20.0 TIMER0 MODULE When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The Timer0 module is an 8-bit timer/counter with the following features: Note: The value written to the TMR0 register can be adjusted, in order to account for • 8-bit timer/counter register (TMR0) the two instruction cycle delay when • 8-bit prescaler (independent of Watchdog Timer) TMR0 is written. • Programmable internal or external clock source • Programmable external clock edge selection 20.1.2 8-BIT COUNTER MODE • Interrupt on overflow In 8-Bit Counter mode, the Timer0 module will increment • TMR0 can be used to gate Timer1 on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. Figure20-1 is a block diagram of the Timer0 module. 8-Bit Counter mode using the T0CKI pin is selected by 20.1 Timer0 Operation setting the TMR0CS bit in the OPTION_REG register to ‘1’ and resetting the T0XCS bit in the CPSCON0 register The Timer0 module can be used as either an 8-bit timer to ‘0’. or an 8-bit counter. 8-Bit Counter mode using the Capacitive Sensing Oscillator (CPSCLK) signal is selected by setting the 20.1.1 8-BIT TIMER MODE TMR0CS bit in the OPTION_REG register to ‘1’ and The Timer0 module will increment every instruction setting the T0XCS bit in the CPSCON0 register to ‘1’. cycle, if used without a prescaler. 8-bit Timer mode is The rising or falling transition of the incrementing edge selected by clearing the TMR0CS bit of the for either input source is determined by the TMR0SE bit OPTION_REG register. in the OPTION_REG register. FIGURE 20-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 Sync 0 1 2 TCY TMR0 0 CPSCLK Set Flag bit TMR0IF 1 TMR0SE TMR0CS 8-bit on Overflow Prescaler PSA Overflow to Timer1 T0XCS 8 PS<2:0>  2011-2013 Microchip Technology Inc. DS40001574C-page 185

PIC16(L)F1938/9 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 20.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 20.1.5 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section30.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS40001574C-page 186  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 20.2 Register Definitions: Timer0 Control REGISTER 20-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate 000 1 : 2 001 1 : 4 010 1 : 8 011 1 : 16 100 1 : 32 101 1 : 64 110 1 : 128 111 1 : 256 TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 321 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 187 TMR0 Timer0 Module Register 185* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information.  2011-2013 Microchip Technology Inc. DS40001574C-page 187

PIC16(L)F1938/9 NOTES: DS40001574C-page 188  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 21.0 TIMER1 MODULE WITH GATE • Gate Toggle mode CONTROL • Gate Single-pulse mode • Gate Value Status The Timer1 module is a 16-bit timer/counter with the • Gate Event Interrupt following features: Figure21-1 is a block diagram of the Timer1 module. • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 2-bit prescaler • Dedicated 32 kHz oscillator circuit • Optionally synchronized comparator out • Multiple Timer1 gate (count enable) sources • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with CCP/ECCP) • Selectable Gate Source Polarity FIGURE 21-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G MUX T1G 00 T1GSPM FrOomve Trfilmower0 01 T1G_IN 0 0 T1GVAL D Q Data Bus sync_C1OUT 10 SAicnqg.l eC Ponutlrsoel 1 Q1 EN T1GRCDON D Q 1 sync_C2OUT 11 CK Q T1GGO/DONE Interrupt Set TMR1ON R det TMR1GIF T1GPOL T1GTM TMR1GE Set flag bit TMR1ON TMR1IF on To Comparator Module Overflow TMR1(2) EN Synchronized TMR1H TMR1L T1CLK 0 clock input Q D 1 TMR1CS<1:0> T1SYNC T1OSO OUT T1OSC CPSCLK 11 Prescaler Synchronize(3) 1 1, 2, 4, 8 det T1OSI EN 10 2 0 FOSC T1CKPS<1:0> Internal 01 T1OSCEN Clock IFnOteSrCn/a2l Sleep input FOSC/4 Clock Internal 00 (1) Clock T1CKI To LCD and Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2011-2013 Microchip Technology Inc. DS40001574C-page 189

PIC16(L)F1938/9 21.1 Timer1 Operation 21.2 Clock Source Selection The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> and T1OSCEN bits of the T1CON which is accessed through the TMR1H:TMR1L register register are used to select the clock source for Timer1. pair. Writes to TMR1H or TMR1L directly update the Table21-2 displays the clock source selections. counter. 21.2.1 INTERNAL CLOCK SOURCE When used with an internal clock source, the module is a timer and increments on every instruction cycle. When the internal clock source is selected the When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples can be used as either a timer or counter and incre- of FOSC as determined by the Timer1 prescaler. ments on every selected edge of the external source. When the FOSC internal clock source is selected, the Timer1 is enabled by configuring the TMR1ON and Timer1 register value will increment by four counts every TMR1GE bits in the T1CON and T1GCON registers, instruction clock cycle. Due to this condition, a 2LSB respectively. Table21-1 displays the Timer1 enable error in resolution will occur when reading the Timer1 selections. value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. TABLE 21-1: TIMER1 ENABLE The following asynchronous sources may be used: SELECTIONS • Asynchronous event on the T1G pin to Timer1 Timer1 TMR1ON TMR1GE gate Operation • C1 or C2 comparator input to Timer1 gate 0 0 Off 21.2.2 EXTERNAL CLOCK SOURCE 0 1 Off 1 0 Always On When the external clock source is selected, the Timer1 module may work as a timer or a counter. 1 1 Count Enabled When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external 32.768kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • Timer1 enabled after POR • Write to TMR1H or TMR1L • Timer1 is disabled • Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. TABLE 21-2: CLOCK SOURCE SELECTIONS TMR1CS<1:0> T1OSCEN Clock Source 11 x Capacitive Sensing Oscillator, CPSCLK 10 0 External Clocking on T1CKI Pin 01 x System Clock (FOSC) 00 x Instruction Clock (FOSC/4) DS40001574C-page 190  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 21.3 Timer1 Prescaler 21.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER Timer1 has four prescaler options allowing 1, 2, 4 or 8 MODE divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The Reading TMR1H or TMR1L while the timer is running prescale counter is not directly readable or writable; from an external asynchronous clock will ensure a valid however, the prescaler counter is cleared upon a write to read (taken care of in hardware). However, the user TMR1H or TMR1L. should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the 21.4 Timer1 Oscillator timer may overflow between the reads. For writes, it is recommended that the user simply stop A dedicated low-power 32.768kHz oscillator circuit is the timer and write the desired values. A write built-in between pins T1OSI (input) and T1OSO contention may occur by writing to the timer registers, (amplifier output). This internal circuit is to be used in while the register is incrementing. This may produce an conjunction with an external 32.768kHz crystal. unpredictable value in the TMR1H:TMR1L register pair. The oscillator circuit is enabled by setting the T1OSCEN bit of the T1CON register. The oscillator will 21.6 Timer1 Gate continue to run during Sleep. Timer1 can be configured to count freely or the count Note: The oscillator requires a start-up and can be enabled and disabled using Timer1 gate stabilization time before use. Thus, circuitry. This is also referred to as Timer1 Gate Enable. T1OSCEN should be set and a suitable delay observed prior to using Timer1. A Timer1 gate can also be driven by multiple selectable suitable delay similar to the OST delay sources. can be implemented in software by 21.6.1 TIMER1 GATE ENABLE clearing the TMR1IF bit then presetting the TMR1H:TMR1L register pair to The Timer1 Gate Enable mode is enabled by setting FC00h. The TMR1IF flag will be set when the TMR1GE bit of the T1GCON register. The polarity 1024 clock cycles have elapsed, thereby of the Timer1 Gate Enable mode is configured using indicating that the oscillator is running and the T1GPOL bit of the T1GCON register. reasonably stable. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock 21.5 Timer1 Operation in source. When Timer1 Gate Enable mode is disabled, Asynchronous Counter Mode no incrementing will occur and Timer1 will hold the current count. See Figure21-3 for timing details. If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer TABLE 21-3: TIMER1 GATE ENABLE increments asynchronously to the internal phase clocks. If the external clock source is selected then the SELECTIONS timer will continue to run during Sleep and can T1CLK T1GPOL T1G Timer1 Operation generate an interrupt on overflow, which will wake-up the processor. However, special precautions in  0 0 Counts software are needed to read/write the timer (see  0 1 Holds Count Section21.5.1 “Reading and Writing Timer1 in  1 0 Holds Count Asynchronous Counter Mode”).  1 1 Counts Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.  2011-2013 Microchip Technology Inc. DS40001574C-page 191

PIC16(L)F1938/9 21.6.2 TIMER1 GATE SOURCE Timer1 Gate Toggle mode is enabled by setting the SELECTION T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This Timer1 gate source selections are shown in Table21-4. is necessary in order to control which edge is Source selection is controlled by the T1GSS bits of the measured. T1GCON register. The polarity for each available source is also selectable. Polarity selection is con- Note: Enabling Toggle mode at the same time trolled by the T1GPOL bit of the T1GCON register. as changing the gate polarity may result in indeterminate operation. TABLE 21-4: TIMER1 GATE SOURCES 21.6.4 TIMER1 GATE SINGLE-PULSE T1GSS Timer1 Gate Source MODE 00 Timer1 Gate Pin When Timer1 Gate Single-Pulse mode is enabled, it is 01 Overflow of Timer0 possible to capture a single pulse gate event. Timer1 (TMR0 increments from FFh to 00h) Gate Single-Pulse mode is first enabled by setting the 10 Comparator 1 Output sync_C1OUT T1GSPM bit in the T1GCON register. Next, the (optionally Timer1 synchronized output) T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next 11 Comparator 2 Output sync_C2OUT incrementing edge. On the next trailing edge of the (optionally Timer1 synchronized output) pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to 21.6.2.1 T1G Pin Gate Operation increment Timer1 until the T1GGO/DONE bit is once The T1G pin is one source for Timer1 gate control. It again set in software. See Figure21-5 for timing details. can be used to supply an external source to the Timer1 If the Single Pulse Gate mode is disabled by clearing the gate circuitry. T1GSPM bit in the T1GCON register, the T1GGO/DONE 21.6.2.2 Timer0 Overflow Gate Operation bit should also be cleared. Enabling the Toggle mode and the Single-Pulse mode When Timer0 increments from FFh to 00h, a simultaneously will permit both sections to work low-to-high pulse will automatically be generated and together. This allows the cycle times on the Timer1 internally supplied to the Timer1 gate circuitry. Gate source to be measured. See Figure21-6 for 21.6.2.3 Comparator C1 Gate Operation timing details. The output resulting from a Comparator 1 operation can 21.6.5 TIMER1 GATE VALUE STATUS be selected as a source for Timer1 gate control. The When Timer1 Gate Value Status is utilized, it is possible Comparator 1 output (sync_C1OUT) can be to read the most current level of the gate control value. synchronized to the Timer1 clock or left asynchronous. The value is stored in the T1GVAL bit in the T1GCON For more information see Section18.4.1 “Comparator register. The T1GVAL bit is valid even when the Timer1 Output Synchronization”. gate is not enabled (TMR1GE bit is cleared). 21.6.2.4 Comparator C2 Gate Operation 21.6.6 TIMER1 GATE EVENT INTERRUPT The output resulting from a Comparator 2 operation When Timer1 Gate Event Interrupt is enabled, it is pos- can be selected as a source for Timer1 gate control. sible to generate an interrupt upon the completion of a The Comparator 2 output (sync_C2OUT) can be gate event. When the falling edge of T1GVAL occurs, synchronized to the Timer1 clock or left asynchronous. the TMR1GIF flag bit in the PIR1 register will be set. If For more information see Section18.4.1 “Comparator the TMR1GIE bit in the PIE1 register is set, then an Output Synchronization”. interrupt will be recognized. 21.6.3 TIMER1 GATE TOGGLE MODE The TMR1GIF flag bit operates even when the Timer1 When Timer1 Gate Toggle mode is enabled, it is possi- gate is not enabled (TMR1GE bit is cleared). ble to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure21-4 for timing details. DS40001574C-page 192  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 21.7 Timer1 Interrupt 21.9 ECCP/CCP Capture/Compare Time Base The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls The CCP modules use the TMR1H:TMR1L register over, the Timer1 interrupt flag bit of the PIR1 register is pair as the time base when operating in Capture or set. To enable the interrupt on rollover, you must set Compare mode. these bits: In Capture mode, the value in the TMR1H:TMR1L • TMR1ON bit of the T1CON register register pair is copied into the CCPR1H:CCPR1L • TMR1IE bit of the PIE1 register register pair on a configured event. • PEIE bit of the INTCON register In Compare mode, an event is triggered when the value • GIE bit of the INTCON register CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a The interrupt is cleared by clearing the TMR1IF bit in Special Event Trigger. the Interrupt Service Routine. For more information, see Section23.0 Note: The TMR1H:TMR1L register pair and the “Capture/Compare/PWM Modules”. TMR1IF bit should be cleared before enabling interrupts. 21.10 ECCP/CCP Special Event Trigger 21.8 Timer1 Operation During Sleep When any of the CCP’s are configured to trigger a special event, the trigger will clear the TMR1H:TMR1L Timer1 can only operate during Sleep when setup in register pair. This special event does not cause a Asynchronous Counter mode. In this mode, an external Timer1 interrupt. The CCP module may still be config- crystal or clock source can be used to increment the ured to generate a CCP interrupt. counter. To set up the timer to wake the device: In this mode of operation, the CCPR1H:CCPR1L • TMR1ON bit of the T1CON register must be set register pair becomes the period register for Timer1. • TMR1IE bit of the PIE1 register must be set Timer1 should be synchronized and FOSC/4 should be • PEIE bit of the INTCON register must be set selected as the clock source in order to utilize the • T1SYNC bit of the T1CON register must be set Special Event Trigger. Asynchronous operation of • TMR1CS bits of the T1CON register must be Timer1 can cause a Special Event Trigger to be configured missed. • T1OSCEN bit of the T1CON register must be In the event that a write to TMR1H or TMR1L coincides configured with a Special Event Trigger from the CCP, the write will take precedence. The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON For more information, see Section15.2.5 “Special register is set, the device will call the Interrupt Service Event Trigger”. Routine. Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 21-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2011-2013 Microchip Technology Inc. DS40001574C-page 193

PIC16(L)F1938/9 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 DS40001574C-page 194  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 Cleared by TMR1GIF Cleared by software Set by hardware on software falling edge of T1GVAL  2011-2013 Microchip Technology Inc. DS40001574C-page 195

PIC16(L)F1938/9 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 Set by hardware on Cleared by TMR1GIF Cleared by software falling edge of T1GVAL software DS40001574C-page 196  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 21.11 Register Definitions: Timer1 Control REGISTER 21-1: T1CON: TIMER1 CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 =Timer1 clock source is Capacitive Sensing Oscillator (CPSCLK) 10 =Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 =Timer1 clock source is system clock (FOSC) 00 =Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled bit 2 T1SYNC: Timer1 Synchronization Control bit 1 = Do not synchronize asynchronous clock input 0 = Synchronize asynchronous clock input with system clock (FOSC) bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop  2011-2013 Microchip Technology Inc. DS40001574C-page 197

PIC16(L)F1938/9 REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> DONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 11 = Comparator 2 optionally synchronized output (sync_C2OUT) 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 01 = Timer0 overflow output 00 = Timer1 gate pin DS40001574C-page 198  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 21-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 131 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 228 CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 228 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 193* TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 193* TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 130 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 197 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 198 DONE Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information.  2011-2013 Microchip Technology Inc. DS40001574C-page 199

PIC16(L)F1938/9 NOTES: DS40001574C-page 200  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 22.0 TIMER2/4/6 MODULES There are up to three identical Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also Timer2/4/6). Note: The ‘x’ variable used in this section is used to designate Timer2, Timer4, or Timer6. For example, TxCON references T2CON, T4CON, or T6CON. PRx refer- ences PR2, PR4, or PR6. The Timer2/4/6 modules incorporate the following features: • 8-bit Timer and Period registers (TMRx and PRx, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMRx match with PRx, respectively • Optional use as the shift clock for the MSSP module (Timer2 only) See Figure22-1 for a block diagram of Timer2/4/6. FIGURE 22-1: TIMER2/4/6 BLOCK DIAGRAM Prescaler Reset FOSC/4 TMRx TMRx Output 1:1, 1:4, 1:16, 1:64 2 Comparator Postscaler Sets Flag bit TMRxIF EQ 1:1 to 1:16 TxCKPS<1:0> PRx 4 TxOUTPS<3:0>  2011-2013 Microchip Technology Inc. DS40001574C-page 201

PIC16(L)F1938/9 22.1 Timer2/4/6 Operation 22.3 Timer2/4/6 Output The clock input to the Timer2/4/6 modules is the The unscaled output of TMRx is available primarily to system instruction clock (FOSC/4). the CCP modules, where it is used as a time base for operations in PWM mode. TMRx increments from 00h on each clock edge. Timer2 can be optionally used as the shift clock source A 4-bit counter/prescaler on the clock input allows direct for the MSSP module operating in SPI mode. input, divide-by-4 and divide-by-16 prescale options. Additional information is provided in Section24.0 These options are selected by the prescaler control bits, “Master Synchronous Serial Port Module” TxCKPS<1:0> of the TxCON register. The value of TMRx is compared to that of the Period register, PRx, on 22.4 Timer2/4/6 Operation During Sleep each clock cycle. When the two values match, the comparator generates a match signal as the timer The Timer2/4/6 timers cannot be operated while the output. This signal also resets the value of TMRx to 00h processor is in Sleep mode. The contents of the TMRx on the next cycle and drives the output and PRx registers will remain unchanged while the counter/postscaler (see Section22.2 “Timer2/4/6 processor is in Sleep mode. Interrupt”). The TMRx and PRx registers are both directly readable and writable. The TMRx register is cleared on any device Reset, whereas the PRx register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • a write to the TMRx register • a write to the TxCON register • Power-on Reset (POR) • Brown-out Reset (BOR) • MCLR Reset • Watchdog Timer (WDT) Reset • Stack Overflow Reset • Stack Underflow Reset • RESET Instruction Note: TMRx is not cleared when TxCON is written. 22.2 Timer2/4/6 Interrupt Timer2/4/6 can also generate an optional device interrupt. The Timer2/4/6 output signal (TMRx-to-PRx match) provides the input for the 4-bit counter/postscaler. This counter generates the TMRx match interrupt flag which is latched in TMRxIF of the PIRx register. The interrupt is enabled by setting the TMRx Match Interrupt Enable bit, TMRxIE, of the PIEx register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, TxOUTPS<3:0>, of the TxCON register. DS40001574C-page 202  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 22.5 Register Definitions: Timer2/4/6 Control REGISTER 22-1: TxCON: TIMER2/TIMER4/TIMER6 CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — TxOUTPS<3:0> TMRxON TxCKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TxOUTPS<3:0>: Timerx Output Postscaler Select bits 1111 =1:16 Postscaler 1110 =1:15 Postscaler 1101 =1:14 Postscaler 1100 =1:13 Postscaler 1011 =1:12 Postscaler 1010 =1:11 Postscaler 1001 =1:10 Postscaler 1000 =1:9 Postscaler 0111 =1:8 Postscaler 0110 =1:7 Postscaler 0101 =1:6 Postscaler 0100 =1:5 Postscaler 0011 =1:4 Postscaler 0010 =1:3 Postscaler 0001 =1:2 Postscaler 0000 =1:1 Postscaler bit 2 TMRxON: Timerx On bit 1 = Timerx is on 0 = Timerx is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 11 =Prescaler is 64 10 =Prescaler is 16 01 =Prescaler is 4 00 =Prescaler is 1  2011-2013 Microchip Technology Inc. DS40001574C-page 203

PIC16(L)F1938/9 TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 228 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 93 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 96 PR2 Timer2 Module Period Register 201* PR4 Timer4 Module Period Register 201* PR6 Timer6 Module Period Register 201* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 203 T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> 203 T6CON — T6OUTPS<3:0> TMR2ON T6CKPS<1:0> 203 TMR2 Holding Register for the 8-bit TMR2 Register 201* TMR4 Holding Register for the 8-bit TMR4 Register(1) 201* TMR6 Holding Register for the 8-bit TMR6 Register(1) 201* Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information. DS40001574C-page 204  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 23.0 CAPTURE/COMPARE/PWM MODULES Note1: In devices with more than one CCP The Capture/Compare/PWM module is a peripheral module, it is very important to pay close which allows the user to time and control different attention to the register names used. A events, and to generate Pulse-Width Modulation number placed after the module acronym (PWM) signals. In Capture mode, the peripheral allows is used to distinguish between separate the timing of the duration of an event. The Compare modules. For example, the CCP1CON mode allows the user to trigger an external event when and CCP2CON control the same a predetermined amount of time has expired. The operational aspects of two completely PWM mode can generate Pulse-Width Modulated different CCP modules. signals of varying frequency and duty cycle. 2: Throughout this section, generic This family of devices contains three Enhanced references to a CCP module in any of its Capture/Compare/PWM modules (ECCP1, ECCP2, operating modes may be interpreted as and ECCP3) and two standard Capture/Compare/PWM being equally applicable to ECCP1, modules (CCP4 and CCP5). ECCP2, ECCP3, CCP4 and CCP5. Register names, module signals, I/O pins, The Capture and Compare functions are identical for all and bit names may use the generic five CCP modules (ECCP1, ECCP2, ECCP3, CCP4, designator ‘x’ to indicate the use of a and CCP5). The only differences between CCP numeral to distinguish a particular module, modules are in the Pulse-Width Modulation (PWM) when required. function. The standard PWM function is identical in modules, CCP4 and CCP5. In CCP modules ECCP1, ECCP2, and ECCP3, the Enhanced PWM function has slight variations from one another. Full-Bridge ECCP modules have four available I/O pins while Half-Bridge ECCP modules only have two available I/O pins. See Table23-1 for more information. TABLE 23-1: PWM RESOURCES Device Name ECCP1 ECCP2 ECCP3 CCP4 CCP5 Enhanced PWM Enhanced PWM Enhanced PWM PIC16F/LF1933/36/38 Standard PWM Standard PWM Full-Bridge Half-Bridge Half-Bridge Enhanced PWM Enhanced PWM Enhanced PWM PIC16F/LF1934/37/39 Standard PWM Standard PWM Full-Bridge Full-Bridge Half-Bridge  2011-2013 Microchip Technology Inc. DS40001574C-page 205

PIC16(L)F1938/9 23.1 Capture Mode 23.1.2 TIMER1 MODE RESOURCE The Capture mode function described in this section is Timer1 must be running in Timer mode or Synchronized available and identical for CCP modules ECCP1, Counter mode for the CCP module to use the capture ECCP2, ECCP3, CCP4 and CCP5. feature. In Asynchronous Counter mode, the capture operation may not work. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the See Section21.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register 23.1.3 SOFTWARE INTERRUPT MODE pair, respectively. An event is defined as one of the When the Capture mode is changed, a false capture following and is configured by the CCPxM<3:0> bits of interrupt may be generated. The user should keep the the CCPxCON register: CCPxIE interrupt enable bit of the PIEx register clear to • Every falling edge avoid false interrupts. Additionally, the user should • Every rising edge clear the CCPxIF interrupt flag bit of the PIRx register • Every 4th rising edge following any change in Operating mode. • Every 16th rising edge Note: Clocking Timer1 from the system clock When a capture is made, the Interrupt Request Flag bit (FOSC) should not be used in Capture CCPxIF of the PIRx register is set. The interrupt flag mode. In order for Capture mode to must be cleared in software. If another capture occurs recognize the trigger event on the CCPx before the value in the CCPRxH, CCPRxL register pair pin, Timer1 must be clocked from the is read, the old captured value is overwritten by the new instruction clock (FOSC/4) or from an captured value. external clock source. Figure23-1 shows a simplified diagram of the Capture 23.1.4 CCP PRESCALER operation. There are four prescaler settings specified by the 23.1.1 CCP PIN CONFIGURATION CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not In Capture mode, the CCPx pin should be configured in Capture mode, the prescaler counter is cleared. Any as an input by setting the associated TRIS control bit. Reset will clear the prescaler counter. Also, the CCPx pin function can be moved to Switching from one capture prescaler to another does alternative pins using the APFCON register. Refer to not clear the prescaler and may generate a false Section12.1 “Alternate Pin Function” for more interrupt. To avoid this unexpected operation, turn the details. module off by clearing the CCPxCON register before Note: If the CCPx pin is configured as an output, changing the prescaler. Example23-1 demonstrates a write to the port can cause a capture the code to perform this function. condition. EXAMPLE 23-1: CHANGING BETWEEN FIGURE 23-1: CAPTURE MODE CAPTURE PRESCALERS OPERATION BLOCK BANKSELCCPxCON ;Set Bank bits to point DIAGRAM ;to CCPxCON CLRF CCPxCON ;Turn CCP module off Set Flag bit CCPxIF (PIRx register) MOVLW NEW_CAPT_PS;Load the W reg with Prescaler ;the new prescaler  1, 4, 16 ;move value and CCP ON CCPx CCPRxH CCPRxL MOVWF CCPxCON ;Load CCPxCON with this pin ;value and Capture Edge Detect Enable 23.1.5 CAPTURE DURING SLEEP TMR1H TMR1L Capture mode depends upon the Timer1 module for CCPxM<3:0> proper operation. There are two options for driving the System Clock (FOSC) Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. DS40001574C-page 206  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 23.1.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section12.1 “Alternate Pin Function” for more information. TABLE 23-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 123 CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 228 CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) 206 CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 206 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 92 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 93 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 95 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 95 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 197 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 198 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 193 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 193 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 130 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 137 TRISE — — — — —(3) TRISE2(2) TRISE1(2) TRISE0(2) 140 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode. Note 1: Applies to ECCP modules only. 2: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 3: Unimplemented, read as ‘1’.  2011-2013 Microchip Technology Inc. DS40001574C-page 207

PIC16(L)F1938/9 23.2 Compare Mode 23.2.2 TIMER1 MODE RESOURCE The Compare mode function described in this section In Compare mode, Timer1 must be running in either is available and identical for CCP modules ECCP1, Timer mode or Synchronized Counter mode. The ECCP2, ECCP3, CCP4 and CCP5. compare operation may not work in Asynchronous Counter mode. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL See Section21.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a Note: Clocking Timer1 from the system clock match occurs, one of the following events can occur: (FOSC) should not be used in Compare • Toggle the CCPx output mode. In order for Compare mode to recognize the trigger event on the CCPx • Set the CCPx output pin, TImer1 must be clocked from the • Clear the CCPx output instruction clock (FOSC/4) or from an • Generate a Special Event Trigger external clock source. • Generate a Software Interrupt The action on the pin is based on the value of the 23.2.3 SOFTWARE INTERRUPT MODE CCPxM<3:0> control bits of the CCPxCON register. At When Generate Software Interrupt mode is chosen the same time, the interrupt flag CCPxIF bit is set. (CCPxM<3:0>=1010), the CCPx module does not All Compare modes can generate an interrupt. assert control of the CCPx pin (see the CCPxCON register). Figure23-2 shows a simplified diagram of the Compare operation. 23.2.4 SPECIAL EVENT TRIGGER FIGURE 23-2: COMPARE MODE When Special Event Trigger mode is chosen (CCPxM<3:0>=1011), the CCPx module does the OPERATION BLOCK following: DIAGRAM • Resets Timer1 CCPxM<3:0> • Starts an ADC conversion if ADC is enabled Mode Select The CCPx module does not assert control of the CCPx Set CCPxIF Interrupt Flag pin in this mode. (PIRx) CCPx 4 The Special Event Trigger output of the CCP occurs Pin CCPRxH CCPRxL immediately upon a match between the TMR1H, Q S Output Comparator TMR1L register pair and the CCPRxH, CCPRxL regis- R Logic Match ter pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The TMR1H TMR1L TRIS Special Event Trigger output starts an A/D conversion Output Enable (if the A/D module is enabled). This allows the Special Event Trigger CCPRxH, CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1. TABLE 23-3: SPECIAL EVENT TRIGGER 23.2.1 CCP PIN CONFIGURATION Device CCPx/ECCPx The user must configure the CCPx pin as an output by clearing the associated TRIS bit. PIC16F193X/LF193X CCP5 Also, the CCPx pin function can be moved to Refer to Section15.2.5 “Special Event Trigger”for alternative pins using the APFCON register. Refer to more information. Section12.1 “Alternate Pin Function” for more details. Note1: The Special Event Trigger from the CCP module does not set interrupt flag bit Note: Clearing the CCPxCON register will force TMR1IF of the PIR1 register. the CCPx compare output latch to the 2: Removing the match condition by default low level. This is not the PORT I/O changing the contents of the CCPRxH data latch. and CCPRxL register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. DS40001574C-page 208  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 23.2.5 COMPARE DURING SLEEP 23.2.6 ALTERNATE PIN LOCATIONS The Compare mode is dependent upon the system This module incorporates I/O pins that can be moved to clock (FOSC) for proper operation. Since FOSC is shut other locations with the use of the alternate pin function down during Sleep mode, the Compare mode will not register, APFCON. To determine which pins can be function properly during Sleep. moved and what their default locations are upon a Reset, see Section12.1 “Alternate Pin Function” for more information. TABLE 23-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 123 CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 228 CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) 206 CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 206 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 92 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 93 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 95 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 96 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 197 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 198 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 193 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 193 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 130 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 137 TRISE — — — — —(3) TRISE2(2) TRISE1(2) TRISE0(2) 140 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode. Note 1: Applies to ECCP modules only. 2: These bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 3: Unimplemented, read as ‘1’.  2011-2013 Microchip Technology Inc. DS40001574C-page 209

PIC16(L)F1938/9 23.3 PWM Overview FIGURE 23-3: CCP PWM OUTPUT SIGNAL Pulse-Width Modulation (PWM) is a scheme that Period provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles Pulse Width a square wave where the high portion of the signal is TMRx = PRx considered the on state and the low portion of the signal TMRx = CCPRxH:CCPxCON<5:4> is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in TMRx = 0 steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to FIGURE 23-4: SIMPLIFIED PWM BLOCK the load. Lowering the number of steps applied, which DIAGRAM shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete CCPxCON<5:4> cycle or the total amount of on and off time combined. Duty Cycle Registers PWM resolution defines the maximum number of steps CCPRxL that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. CCPRxH(2) (Slave) CCPx The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, Comparator R Q where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher S TMRx (1) duty cycle corresponds to more power applied. TRIS Figure23-3 shows a typical waveform of the PWM signal. Comparator Clear Timer, toggle CCPx pin and 23.3.1 STANDARD PWM OPERATION latch duty cycle PRx The standard PWM function described in this section is Note 1: The 8-bit timer TMRx register is concatenated available and identical for CCP modules ECCP1, with the 2-bit internal system clock (FOSC), or ECCP2, ECCP3, CCP4 and CCP5. 2 bits of the prescaler, to create the 10-bit time The standard PWM mode generates a Pulse-Width base. modulation (PWM) signal on the CCPx pin with up to 10 2: In PWM mode, CCPRxH is a read-only register. bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • PRx registers • TxCON registers • CCPRxL registers • CCPxCON registers Figure23-4 shows a simplified block diagram of PWM operation. Note1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. DS40001574C-page 210  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 23.3.2 SETUP FOR PWM OPERATION When TMRx is equal to PRx, the following three events occur on the next increment cycle: The following steps should be taken when configuring the CCP module for standard PWM operation: • TMRx is cleared • The CCPx pin is set. (Exception: If the PWM duty 1. Disable the CCPx pin output driver by setting the cycle=0%, the pin will not be set.) associated TRIS bit. 2. Timer2/4/6 resource selection: • The PWM duty cycle is latched from CCPRxL into CCPRxH. • Select the Timer2/4/6 resource to be used for PWM generation by setting the CxTSEL<1:0> bits in the CCPTMERSx register. Note: The Timer postscaler (see Section22.1 “Timer2/4/6 Operation”) is not used in the 3. Load the PRx register with the PWM period determination of the PWM frequency. value. 4. Configure the CCP module for the PWM mode 23.3.5 PWM DUTY CYCLE by loading the CCPxCON register with the The PWM duty cycle is specified by writing a 10-bit appropriate values. value to multiple registers: CCPRxL register and 5. Load the CCPRxL register and the DCxBx bits DCxB<1:0> bits of the CCPxCON register. The of the CCPxCON register, with the PWM duty CCPRxL contains the eight MSbs and the DCxB<1:0> cycle value. bits of the CCPxCON register contain the two LSbs. 6. Configure and start Timer2/4/6: CCPRxL and DCxB<1:0> bits of the CCPxCON • Clear the TMRxIF interrupt flag bit of the register can be written to at any time. The duty cycle PIRx register. See Note below. value is not latched into CCPRxH until after the period • Configure the TxCKPS bits of the TxCON completes (i.e., a match between PRx and TMRx register with the Timer prescale value. registers occurs). While using the PWM, the CCPRxH register is read-only. • Enable the Timer by setting the TMRxON bit of the TxCON register. Equation23-2 is used to calculate the PWM pulse 7. Enable PWM output pin: width. • Wait until the Timer overflows and the Equation23-3 is used to calculate the PWM duty cycle TMRxIF bit of the PIRx register is set. See ratio. Note below. • Enable the CCPx pin output driver by clear- EQUATION 23-2: PULSE WIDTH ing the associated TRIS bit. Note: In order to send a complete duty cycle and Pulse Width = CCPRxL:CCPxCON<5:4>  period on the first PWM output, the above TOSC  (TMRx Prescale Value) steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, EQUATION 23-3: DUTY CYCLE RATIO then step 6 may be ignored. 23.3.3 TIMER2/4/6 TIMER RESOURCE Duty Cycle Ratio = ---C----C----P----R---x---L---:--C----C----P----x---C----O----N----<----5---:--4--->------ 4PRx+1 The PWM standard mode makes use of one of the 8-bit Timer2/4/6 timer resources to specify the PWM period. The CCPRxH register and a 2-bit internal latch are Configuring the CxTSEL<1:0> bits in the CCPTMRSx used to double buffer the PWM duty cycle. This double register selects which Timer2/4/6 timer is used. buffering is essential for glitchless PWM operation. 23.3.4 PWM PERIOD The 8-bit timer TMRx register is concatenated with either The PWM period is specified by the PRx register of the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system Timer2/4/6. The PWM period can be calculated using clock is used if the Timer2/4/6 prescaler is set to 1:1. the formula of Equation23-1. When the 10-bit time base matches the CCPRxH and EQUATION 23-1: PWM PERIOD 2-bit latch, then the CCPx pin is cleared (see Figure23-4). PWM Period = PRx+14TOSC (TMRx Prescale Value) Note 1: TOSC = 1/FOSC  2011-2013 Microchip Technology Inc. DS40001574C-page 211

PIC16(L)F1938/9 23.3.6 PWM RESOLUTION EQUATION 23-4: PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution log4PRx+1 Resolution = ------------------------------------------ bits will result in 1024 discrete duty cycles, whereas an 8-bit log2 resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PRx is Note: If the pulse width value is greater than the 255. The resolution is a function of the PRx register period the assigned PWM pin(s) will value as shown by Equation23-4. remain unchanged. TABLE 23-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz) PWM Frequency 1.95 kHz 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz Timer Prescale 16 4 1 1 1 1 PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 23-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale 16 4 1 1 1 1 PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 23-7: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale 16 4 1 1 1 1 PRx Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 DS40001574C-page 212  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 23.3.7 OPERATION IN SLEEP MODE 23.3.10 ALTERNATE PIN LOCATIONS In Sleep mode, the TMRxregister will not increment This module incorporates I/O pins that can be moved to and the state of the module will not change. If the CCPx other locations with the use of the alternate pin function pin is driving a value, it will continue to drive that value. register, APFCON. To determine which pins can be When the device wakes up, TMRx will continue from its moved and what their default locations are upon a previous state. Reset, see Section12.1 “Alternate Pin Function” for more information. 23.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. 23.3.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. TABLE 23-8: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 123 CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 228 CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 229 CCPTMRS1 — — — — — — C5TSEL<1:0> 230 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 92 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 93 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 95 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 96 PRx Timer2/4/6 Period Register 201* TxCON — TxOUTPS<3:0> TMRxON TxCKPS<:0>1 203 TMRx Timer2/4/6 Module Register 201 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 130 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 137 TRISE — — — — —(3) TRISE2(2) TRISE1(2) TRISE0(2) 140 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. Note 1: Applies to ECCP modules only. 2: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 3: Unimplemented, read as ‘1’. * Page provides register information.  2011-2013 Microchip Technology Inc. DS40001574C-page 213

PIC16(L)F1938/9 23.4 PWM (Enhanced Mode) To select an Enhanced PWM Output mode, the PxM bits of the CCPxCON register must be configured The enhanced PWM function described in this section is appropriately. available for CCP modules ECCP1, ECCP2 and The PWM outputs are multiplexed with I/O pins and are ECCP3, with any differences between modules noted. designated PxA, PxB, PxC and PxD. The polarity of the The enhanced PWM mode generates a Pulse-Width PWM pins is configurable and is selected by setting the Modulation (PWM) signal on up to four different output CCPxM bits in the CCPxCON register appropriately. pins with up to 10 bits of resolution. The period, duty Figure23-5 shows an example of a simplified block cycle, and resolution are controlled by the following diagram of the Enhanced PWM module. registers: Table23-9 shows the pin assignments for various • PRx registers Enhanced PWM modes. • TxCON registers • CCPRxL registers Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the • CCPxCON registers CCPx pin. The ECCP modules have the following additional PWM 2: Clearing the CCPxCON register will registers which control Auto-shutdown, Auto-restart, relinquish control of the CCPx pin. Dead-band Delay and PWM Steering modes: 3: Any pin not used in the enhanced PWM • CCPxAS registers mode is available for alternate pin • PSTRxCON registers functions, if applicable. • PWMxCON registers 4: To prevent the generation of an The enhanced PWM module can generate the following incomplete waveform when the PWM is five PWM Output modes: first enabled, the ECCP module waits • Single PWM until the start of a new PWM period before generating a PWM signal. • Half-Bridge PWM • Full-Bridge PWM, Forward mode • Full-Bridge PWM, Reverse mode • Single PWM with PWM Steering mode FIGURE 23-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DCxB<1:0> PxM<1:0> CCPxM<3:0> Duty Cycle Registers 2 4 CCPRxL CCPx/PxA CCPx/PxA TRISx CCPRxH (Slave) PxB PxB Output TRISx Comparator R Q Controller PxC PxC TMRx (1) S TRISx PxD PxD Comparator Clear Timer, TRISx toggle PWM pin and latch duty cycle PRx PWMxCON Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or two bits of the prescaler to create the 10-bit time base. DS40001574C-page 214  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 23-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> CCPx/PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: PWM Steering enables outputs in Single mode. FIGURE 23-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse PRX+1 PxM<1:0> Signal 0 Width Period 00 (Single Output) PxA Modulated Delay Delay PxA Modulated 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>)  2011-2013 Microchip Technology Inc. DS40001574C-page 215

PIC16(L)F1938/9 FIGURE 23-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal 0 Pulse PRx+1 Width Period 00 (Single Output) PxA Modulated PxA Modulated Delay Delay 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>) DS40001574C-page 216  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 23.4.1 HALF-BRIDGE MODE Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be In Half-Bridge mode, two pins are used as outputs to cleared to configure PxA and PxB as outputs. drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM FIGURE 23-8: EXAMPLE OF output signal is output on the PxB pin (see HALF-BRIDGE PWM Figure23-9). This mode can be used for Half-Bridge applications, as shown in Figure23-9, or for Full-Bridge OUTPUT applications, where four power switches are being Period Period modulated with two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in PxA(2) Half-Bridge power devices. The value of the PDC<6:0> td bits of the PWMxCON register sets the number of td instruction cycles before the output is driven active. If the PxB(2) value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See (1) (1) (1) Section23.4.5 “Programmable Dead-Band Delay Mode” for more details of the dead-band delay td = Dead-Band Delay operations. Note 1: At this time, the TMRx register is equal to the PRx register. 2: Output signals are shown as active-high. FIGURE 23-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA - Load FET Driver + PxB - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver PxA Load FET FET Driver Driver PxB  2011-2013 Microchip Technology Inc. DS40001574C-page 217

PIC16(L)F1938/9 23.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure23-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure23-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure23-11. PxA, PxB, PxC and PxD outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs. FIGURE 23-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver PxA Load PxB FET FET Driver Driver PxC QB QD V- PxD DS40001574C-page 218  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 23-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA(2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) (1) Note 1: At this time, the TMRx register is equal to the PRx register. 2: Output signal is shown as active-high.  2011-2013 Microchip Technology Inc. DS40001574C-page 219

PIC16(L)F1938/9 23.4.2.1 Direction Change in Full-Bridge The Full-Bridge mode does not provide dead-band Mode delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation In the Full-Bridge mode, the PxM1 bit in the CCPxCON where dead-band delay is required. This situation register allows users to control the forward/reverse occurs when both of the following conditions are true: direction. When the application firmware changes this direction control bit, the module will change to the new 1. The direction of the PWM output changes when direction on the next PWM cycle. the duty cycle of the output is at or near 100%. 2. The turn off time of the power switch, including A direction change is initiated in software by changing the power device and driver circuit, is greater the PxM1 bit of the CCPxCON register. The following than the turn on time. sequence occurs four Timer cycles prior to the end of the current PWM period: Figure23-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty • The modulated outputs (PxB and PxD) are placed cycle. In this example, at time t1, the output PxA and in their inactive state. PxD become inactive, while output PxC becomes • The associated unmodulated outputs (PxA and active. Since the turn off time of the power devices is PxC) are switched to drive in the opposite longer than the turn on time, a shoot-through current direction. will flow through power devices QC and QD (see • PWM modulation resumes at the beginning of the Figure23-10) for the duration of ‘t’. The same next period. phenomenon will occur to power devices QA and QB See Figure23-12 for an illustration of this sequence. for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 23-12: EXAMPLE OF PWM DIRECTION CHANGE Signal Period(1) Period PxA (Active-High) PxB (Active-High) Pulse Width PxC (Active-High) (2) PxD (Active-High) Pulse Width Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle. 2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts. DS40001574C-page 220  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 23-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential T = TOFF – TON Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver.  2011-2013 Microchip Technology Inc. DS40001574C-page 221

PIC16(L)F1938/9 23.4.3 ENHANCED PWM AUTO-SHUTDOWN MODE Note1: The auto-shutdown condition is a The PWM mode supports an Auto-Shutdown mode that level-based signal, not an edge-based will disable the PWM outputs when an external signal. As long as the level is present, the shutdown event occurs. Auto-Shutdown mode places auto-shutdown will persist. the PWM output pins into a predetermined state. This 2: Writing to the CCPxASE bit is disabled mode is used to help prevent the PWM from damaging while an auto-shutdown condition the application. persists. The auto-shutdown sources are selected using the 3: Once the auto-shutdown condition has CCPxAS2, CCPxAS1 and CCPxAS0 bits of the been removed and the PWM restarted CCPxAS register. A shutdown event may be generated (either through firmware or auto-restart) by: the PWM signal will always restart at the • A logic ‘0’ on the INT pin beginning of the next PWM period. • A logic ‘0’ on a Comparator (async_CxOUT) 4: Prior to an auto-shutdown event caused output by a comparator output or INT pin event, A shutdown condition is indicated by the CCPxASE a software shutdown can be triggered in (Auto-Shutdown Event Status) bit of the CCPxAS firmware by setting the CCPxASE bit of register. If the bit is a ‘0’, the PWM pins are operating the CCPxAS register to ‘1’. The normally. If the bit is a ‘1’, the PWM outputs are in the Auto-Restart feature tracks the active sta- shutdown state. tus of a shutdown caused by a compara- tor output or INT pin event only. If it is When a shutdown event occurs, two things happen: enabled at this time, it will immediately The CCPxASE bit is set to ‘1’. The CCPxASE will clear this bit and restart the ECCP mod- remain set until cleared in firmware or an auto-restart ule at the beginning of the next PWM occurs (see Section23.4.4 “Auto-Restart Mode”). period. The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [PxA/PxC] and [PxB/PxD]. The state of each pin pair is determined by the PSSxAC and PSSxBD bits of the CCPxAS register. Each pin pair may be placed into one of three states: • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) FIGURE 23-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0) Missing Pulse Missing Pulse (Auto-Shutdown) (CCPxASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent CCPxASE bit PWM Shutdown Shutdown Resumes Event Occurs Event Clears CCPxASE Cleared by Firmware DS40001574C-page 222  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 23.4.4 AUTO-RESTART MODE The Enhanced PWM can be configured to automati- cally restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit in the PWMxCON register. If auto-restart is enabled, the CCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCPxASE bit will be cleared via hardware and normal operation will resume. FIGURE 23-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1) Missing Pulse Missing Pulse (Auto-Shutdown) (CCPxASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent CCPxASE bit PWM Shutdown Resumes Event Occurs Shutdown CCPxASE Event Clears Cleared by Hardware  2011-2013 Microchip Technology Inc. DS40001574C-page 223

PIC16(L)F1938/9 23.4.5 PROGRAMMABLE DEAD-BAND FIGURE 23-16: EXAMPLE OF DELAY MODE HALF-BRIDGE PWM OUTPUT In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power Period Period switches normally require more time to turn off than to Pulse Width turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the PxA(2) other turned off), both switches may be on for a short td period of time until one switch completely turns off. td During this brief interval, a very high current PxB(2) (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this (1) (1) (1) potentially destructive shoot-through current from flowing during switching, turning on either of the power td = Dead-Band Delay switches is normally delayed to allow the other switch to completely turn off. Note 1: At this time, the TMRx register is equal to the In Half-Bridge mode, a digitally programmable PRx register. dead-band delay is available to avoid shoot-through 2: Output signals are shown as active-high. current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure23-16 for illustration. The lower seven bits of the associated PWMxCON register (Register23-5) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 23-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA V - Load FET Driver + PxB V - V- DS40001574C-page 224  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 23.4.6 PWM STEERING MODE In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCPxM<3:2>=11 and PxM<1:0>=00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STRx<D:A> bits of the PSTRxCON register, as shown in Table23-9. Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. While the PWM Steering mode is active, CCPxM<1:0> bits of the CCPxCON register select the PWM output polarity for the Px<D:A> pins. The PWM auto-shutdown operation also applies to PWM Steering mode as described in Section23.4.3 “Enhanced PWM Auto-shutdown mode”. An auto-shutdown event will only affect pins that have PWM outputs enabled. FIGURE 23-18: SIMPLIFIED STEERING BLOCK DIAGRAM STRxA PxA Signal PxA pin CCPxM1 1 PORT Data 0 TRIS STRxB PxB pin CCPxM0 1 PORT Data 0 TRIS STRxC PxC pin CCPxM1 1 PORT Data 0 TRIS STRxD PxD pin CCPxM0 1 PORT Data 0 TRIS Note 1: Port outputs are configured as shown when the CCPxCON register bits PxM<1:0>=00 and CCPxM<3:2>=11. 2: Single PWM output requires setting at least one of the STRx bits.  2011-2013 Microchip Technology Inc. DS40001574C-page 225

PIC16(L)F1938/9 23.4.6.1 Steering Synchronization drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are The STRxSYNC bit of the PSTRxCON register gives enable is not recommended since it may result in the user two selections of when the steering event will damage to the application circuits. happen. When the STRxSYNC bit is ‘0’, the steering event will happen at the end of the instruction that The PxA, PxB, PxC and PxD output latches may not be writes to the PSTRxCON register. In this case, the in the proper states when the PWM module is output signal at the Px<D:A> pins may be an initialized. Enabling the PWM pin output drivers at the incomplete PWM waveform. This operation is useful same time as the Enhanced PWM modes may cause when the user firmware needs to immediately remove damage to the application circuit. The Enhanced PWM a PWM signal from the pin. modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM When the STRxSYNC bit is ‘1’, the effective steering pin output drivers. The completion of a full PWM cycle update will happen at the beginning of the next PWM is indicated by the TMRxIF bit of the PIRx register period. In this case, steering on/off the PWM output will being set as the second PWM period begins. always produce a complete PWM waveform. Note: When the microcontroller is released from Figures 23-19 and 23-20 illustrate the timing diagrams Reset, all of the I/O pins are in the of the PWM steering depending on the STRxSYNC high-impedance state. The external cir- setting. cuits must keep the power switch devices 23.4.7 START-UP CONSIDERATIONS in the Off state until the microcontroller drives the I/O pins with the proper signal When any PWM mode is used, the application levels or activates the PWM output(s). hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. The CCPxM<1:0> bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (PxA/PxC and PxB/PxD). The PWM output polarities must be selected before the PWM pin output FIGURE 23-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0) PWM Period PWM STRx P1<D:A> PORT Data PORT Data P1n = PWM FIGURE 23-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRxSYNC = 1) PWM STRx P1<D:A> PORT Data PORT Data P1n = PWM DS40001574C-page 226  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 23-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 228 CCPxAS CCPxASE CCPxAS2 CCPxAS1 CCPxAS0 PSSxAC<1:0> PSSxBD<1:0> 231 CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 229 CCPTMRS1 — — — — — — C5TSEL<1:0> 230 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 92 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 93 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 95 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF — 96 PRx Timer2/4/6 Period Register 201* PSTRxCON — — — STRxSYNC STRxD STRxC STRxB STRxA 233 PWMxCON PxRSEN PxDC<6:0> 232 TxCON — TxOUTPS<3:0> TMRxON TxCKPS<:0>1 203 TMRx Timer2/4/6 Module Register 201 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 130 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 137 TRISE — — — — —(3) TRISE2(2) TRISE1(2) TRISE0(2) 140 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. Note 1: Applies to ECCP modules only. 2: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 3: Unimplemented, read as ‘1’. * Page provides register information.  2011-2013 Microchip Technology Inc. DS40001574C-page 227

PIC16(L)F1938/9 23.5 Register Definitions: CCP Control REGISTER 23-1: CCPxCON: CCPx CONTROL REGISTER R/W-00 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits(1) Capture mode: Unused Compare mode: Unused If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins If CCPxM<3:2> = 11: 00 = Single output; PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive 10 = Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins 11 = Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCPx module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF) 1001 = Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF) 1010 = Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state 1011 = Compare mode: Special Event Trigger (ECCPx resets Timer, sets CCPxIF bit starts A/D conversion if A/D module is enabled)(1) CCP4/CCP5 only: 11xx = PWM mode ECCP1/ECCP2/ECCP3 only: 1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low Note 1: These bits are not implemented on CCP4 and CCP5. DS40001574C-page 228  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 23-2: CCPTMRS0: PWM TIMER SELECTION CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection 00 =CCP4 is based off Timer2 in PWM mode 01 =CCP4 is based off Timer4 in PWM mode 10 =CCP4 is based off Timer6 in PWM mode 11 =Reserved bit 5-4 C3TSEL<1:0>: CCP3 Timer Selection 00 =CCP3 is based off Timer2 in PWM mode 01 =CCP3 is based off Timer4 in PWM mode 10 =CCP3 is based off Timer6 in PWM mode 11 =Reserved bit 3-2 C2TSEL<1:0>: CCP2 Timer Selection 00 =CCP2 is based off Timer2 in PWM mode 01 =CCP2 is based off Timer4 in PWM mode 10 =CCP2 is based off Timer6 in PWM mode 11 =Reserved bit 1-0 C1TSEL<1:0>: CCP1 Timer Selection 00 =CCP1 is based off Timer2 in PWM mode 01 =CCP1 is based off Timer4 in PWM mode 10 =CCP1 is based off Timer6 in PWM mode 11 =Reserved  2011-2013 Microchip Technology Inc. DS40001574C-page 229

PIC16(L)F1938/9 REGISTER 23-3: CCPTMRS1: PWM TIMER SELECTION CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — C5TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 C5TSEL<1:0>: CCP5 Timer Selection 00 =CCP5 is based off Timer2 in PWM mode 01 =CCP5 is based off Timer4 in PWM mode 10 =CCP5 is based off Timer6 in PWM mode 11 =Reserved DS40001574C-page 230  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 23-4: CCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCPxASE CCPxAS2 CCPxAS1 CCPxAS0 PSSxAC<1:0> PSSxBD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCPxASE: CCPx Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; CCPx outputs are in shutdown state 0 = CCPx outputs are operating bit 6 CCPxAS2: CCPx Auto-Shutdown Source 2 Select bit 1 =Auto-shutdown 2 source is enabled, VIL on INT pin 0 =Auto-shutdown 2 source is disabled bit 5 CCPxAS1: CCPx Auto-Shutdown Source 1 Select bit 1 = Auto-shutdown 1 source is enabled, async_CxOUT(1),(2) output low 0 =Auto-shutdown 1 source is disabled bit 4 CCPxAS0: CCPx Auto-Shutdown Source 0 Select bit 1 =Auto-shutdown 0 source is enabled, async_C1OUT(1) output low 0 =Auto-shutdown 0 source is disabled bit 3-2 PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits 00 = Drive pins PxA and PxC to ‘0’ 01 = Drive pins PxA and PxC to ‘1’ 1x = Pins PxA and PxC tri-state bit 1-0 PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits 00 = Drive pins PxB and PxD to ‘0’ 01 = Drive pins PxB and PxD to ‘1’ 1x = Pins PxB and PxD tri-state Note 1: If CxSYNC is enabled, the shutdown will be delayed by Timer1. 2: async_CxOUT = async_C2OUT (for CCP1 and CCP2) async_CxOUT = async_C3OUT (for CCP3)  2011-2013 Microchip Technology Inc. DS40001574C-page 231

PIC16(L)F1938/9 REGISTER 23-5: PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxRSEN PxDC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM bit 6-0 PxDC<6:0>: PWM Delay Count bits PxDCx = Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled. DS40001574C-page 232  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 23-6: PSTRxCON: PWM STEERING CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 — — — STRxSYNC STRxD STRxC STRxB STRxA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRxSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRxD: Steering Enable bit D 1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxD pin is assigned to port pin bit 2 STRxC: Steering Enable bit C 1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxC pin is assigned to port pin bit 1 STRxB: Steering Enable bit B 1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxB pin is assigned to port pin bit 0 STRxA: Steering Enable bit A 1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxA pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2>=11 and PxM<1:0>=00.  2011-2013 Microchip Technology Inc. DS40001574C-page 233

PIC16(L)F1938/9 NOTES: DS40001574C-page 234  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 24.0 MASTER SYNCHRONOUS SERIAL PORT MODULE 24.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) The SPI interface supports the following modes and features: • Master mode • Slave mode • Clock Parity • Slave Select Synchronization (Slave mode only) • Daisy-chain connection of slave devices Figure24-1 is a block diagram of the SPI Interface module. FIGURE 24-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPBUF Reg SDI SSPSR Reg SDO bit 0 Shift Clock SS SS Control 2 (CKP, CKE) Enable Clock Select Edge Select SSPM<3:0> 4 ( T M R 2 O u tp u t ) 2 SCK Edge Prescaler TOSC Select 4, 16, 64 Baud Rate Generator TRIS bit (SSPADD)  2011-2013 Microchip Technology Inc. DS40001574C-page 235

PIC16(L)F1938/9 The I2C interface supports the following modes and features: • Master mode • Slave mode • Byte NACKing (Slave mode) • Limited Multi-master support • 7-bit and 10-bit addressing • Start and Stop interrupts • Interrupt masking • Clock stretching • Bus collision detection • General call address matching • Address masking • Address Hold and Data Hold modes • Selectable SDA hold times Figure24-2 is a block diagram of the I2C Interface module in Master mode. Figure24-3 is a diagram of the I2C Interface module in Slave mode. FIGURE 24-2: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE) Internal data bus [SSPM 3:0] Read Write SSPBUF Baud Rate Generator (SSPADD) SDA Shift SDA in Clock SSPSR ct e Enable (RCEN) MGSeSbnteAarrcatk tbeni ot(,wS SSletoPdpCg ebOitNL,S2b) Clock Cntl arbitrate/BCOL det d off clock source) SCL ceive Clock (Hol e R Start bit detect, Stop bit detect SCL in Write collision detect Set/Reset: S, P, SSPSTAT, WCOL, SSPOV Clock arbitration Reset SEN, PEN (SSPCON2) Bus Collision State counter for Set SSPIF, BCLIF end of XMIT/RCV Address Match detect DS40001574C-page 236  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT Reg)  2011-2013 Microchip Technology Inc. DS40001574C-page 237

PIC16(L)F1938/9 24.2 SPI Mode Overview its SDO pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave The Serial Peripheral Interface (SPI) bus is a device is also sending out the MSb from its shift register synchronous serial data communication bus that (on its SDO pin) and the master device is reading this operates in Full-Duplex mode. Devices communicate bit and saving it as the LSb of its shift register. in a master/slave environment where the master device After eight bits have been shifted out, the master and initiates the communication. A slave device is slave have exchanged register values. controlled through a Chip Select known as Slave Select. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. The SPI bus specifies four signal connections: Whether the data is meaningful or not (dummy data), • Serial Clock (SCK) depends on the application software. This leads to • Serial Data Out (SDO) three scenarios for data transmission: • Serial Data In (SDI) • Master sends useful data and slave sends dummy • Slave Select (SS) data. Figure24-1 shows the block diagram of the MSSP • Master sends useful data and slave sends useful module when operating in SPI mode. data. The SPI bus operates with a single master device and • Master sends dummy data and slave sends useful one or more slave devices. When multiple slave data. devices are used, an independent Slave Select con- Transmissions may involve any number of clock nection is required from the master device to each cycles. When there is no more data to be transmitted, slave device. the master stops sending the clock signal and it dese- Figure24-4 shows a typical connection between a lects the slave. master device and multiple slave devices. Every slave device connected to the bus that has not The master selects only one slave at a time. Most slave been selected through its slave select line must disre- devices have tri-state outputs so their output signal gard the clock and transmission signals and must not appears disconnected from the bus when they are not transmit out any data of its own. selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure24-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the pro- grammed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits infor- mation out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polar- ity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on DS40001574C-page 238  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SCK SCK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS General I/O General I/O SCK SDI SPI Slave SDO #2 SS SCK SDI SPI Slave SDO #3 SS 24.2.1 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation. These are: • MSSP STATUS register (SSPSTAT) • MSSP Control Register 1 (SSPCON1) • MSSP Control Register 3 (SSPCON3) • MSSP Data Buffer register (SSPBUF) • MSSP Address register (SSPADD) • MSSP Shift register (SSPSR) (Not directly accessible) SSPCON1 and SSPSTAT are the control and STATUS registers in SPI mode operation. The SSPCON1 regis- ter is readable and writable. The lower six bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. In one SPI Master mode, SSPADD can be loaded with a value used in the Baud Rate Generator. More infor- mation on the Baud Rate Generator is available in Section24.7 “Baud Rate Generator”. SSPSR is the shift register used for shifting data in and out. SSPBUF provides indirect access to the SSPSR register. SSPBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not buffered. A write to SSPBUF will write to both SSPBUF and SSPSR.  2011-2013 Microchip Technology Inc. DS40001574C-page 239

PIC16(L)F1938/9 24.2.2 SPI MODE OPERATION The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR When initializing the SPI, several options need to be shifts the data in and out of the device, MSb first. The specified. This is done by programming the appropriate SSPBUF holds the data that was written to the SSPSR control bits (SSPCON1<5:0> and SSPSTAT<7:6>). until the received data is ready. Once the eight bits of These control bits allow the following to be specified: data have been received, that byte is moved to the • Master mode (SCK is the clock output) SSPBUF register. Then, the Buffer Full Detect bit, BF • Slave mode (SCK is the clock input) of the SSPSTAT register, and the interrupt flag bit, • Clock Polarity (Idle state of SCK) SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception • Data Input Sample Phase (middle or end of data before reading the data that was just received. Any output time) write to the SSPBUF register during • Clock Edge (output data on rising/falling edge of transmission/reception of data will be ignored and the SCK) write collision detect bit WCOL of the SSPCON1 • Clock Rate (Master mode only) register, will be set. User software must clear the • Slave Select mode (Slave mode only) WCOL bit to allow the following write(s) to the SSPBUF To enable the serial port, SSP Enable bit, SSPEN of the register to complete successfully. SSPCON1 register, must be set. To reset or reconfig- When the application software is expecting to receive ure SPI mode, clear the SSPEN bit, re-initialize the valid data, the SSPBUF should be read before the next SSPCONx registers and then set the SSPEN bit. This byte of data to transfer is written to the SSPBUF. The configures the SDI, SDO, SCK and SS pins as serial Buffer Full bit, BF of the SSPSTAT register, indicates port pins. For the pins to behave as the serial port func- when SSPBUF has been loaded with the received data tion, some must have their data direction bits (in the (transmission is complete). When the SSPBUF is read, TRIS register) appropriately programmed as follows: the BF bit is cleared. This data may be irrelevant if the • SDI must have corresponding TRIS bit set SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception • SDO must have corresponding TRIS bit cleared has completed. If the interrupt method is not going to • SCK (Master mode) must have corresponding be used, then software polling can be done to ensure TRIS bit cleared that a write collision does not occur. • SCK (Slave mode) must have corresponding The SSPSR is not directly readable or writable and can TRIS bit set only be accessed by addressing the SSPBUF register. • SS must have corresponding TRIS bit set Additionally, the SSPSTAT register indicates the Any serial port function that is not desired may be various Status conditions. overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 24-5: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x = 1010 SDO SDI Serial Input Buffer Serial Input Buffer (BUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK Slave Select General I/O SS Processor 1 (optional) Processor 2 DS40001574C-page 240  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 24.2.3 SPI MASTER MODE The clock polarity is selected by appropriately programming the CKP bit of the SSPCON1 register The master can initiate the data transfer at any time and the CKE bit of the SSPSTAT register. This then, because it controls the SCK line. The master would give waveforms for SPI communication as determines when the slave (Processor 2, Figure24-5) shown in Figure24-6, Figure24-8 and Figure24-9, is to broadcast data by the software protocol. where the MSB is transmitted first. In Master mode, the In Master mode, the data is transmitted/received as SPI clock rate (bit rate) is user programmable to be one soon as the SSPBUF register is written to. If the SPI is of the following: only going to receive, the SDO output could be dis- • FOSC/4 (or TCY) abled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin • FOSC/16 (or 4 * TCY) at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY) received, it will be loaded into the SSPBUF register as • Timer2 output/2 if a normal received byte (interrupts and Status bits • Fosc/(4 * (SSPADD + 1)) appropriately set). Figure24-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 24-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF  2011-2013 Microchip Technology Inc. DS40001574C-page 241

PIC16(L)F1938/9 24.2.4 SPI SLAVE MODE 24.2.5 SLAVE SELECT SYNCHRONIZATION In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last The Slave Select can also be used to synchronize com- bit is latched, the SSPIF interrupt flag bit is set. munication. The Slave Select line is held high until the master device is ready to communicate. When the Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a be observed by reading the SCK pin. The Idle state is new transmission is starting. determined by the CKP bit of the SSPCON1 register. If the slave fails to receive the communication properly, While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the the external clock source on the SCK pin. This external Slave Select line returns to a high state. The slave is clock must meet the minimum high and low times as then ready to receive a new transmission when the specified in the electrical specifications. Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will even- While in Sleep mode, the slave can transmit/receive tually become out of sync with the master. If the slave data. The shift register is clocked from the SCK pin misses a bit, it will always be one bit off in future trans- input and when a byte is received, the device will gen- missions. Use of the Slave Select line allows the slave erate an interrupt. If enabled, the device will wake-up and master to align themselves at the beginning of from Sleep. each transmission. 24.2.4.1 Daisy-Chain Configuration The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled The SPI bus can sometimes be connected in a (SSPCON1<3:0> = 0100). daisy-chain configuration. The first slave output is connected to the second slave input, the second slave When the SS pin is low, transmission and reception are output is connected to the third slave input, and so on. enabled and the SDO pin is driven. The final slave output is connected to the master input. When the SS pin goes high, the SDO pin is no longer Each slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down first group of clock pulses. The whole chain acts as one resistors may be desirable depending on the applica- large communication shift register. The daisy-chain tion. feature only requires a single Slave Select line from the master device. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON1<3:0> = Figure24-7 shows the block diagram of a typical 0100), the SPI module will reset if the SS daisy-chain connection when operating in SPI mode. pin is set to VDD. In a daisy-chain configuration, only the most recent 2: When the SPI is used in Slave mode with byte on the bus is required by the slave. Setting the CKE set; the user must enable SS pin BOEN bit of the SSPCON3 register will enable writes control. to the SSPBUF register, even if the previous byte has 3: While operated in SPI Slave mode the not been read. This allows the software to ignore data SMP bit of the SSPSTAT register must that may not apply to it. remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. DS40001574C-page 242  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-7: SPI DAISY-CHAIN CONNECTION SCK SCK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS SCK SDI SPI Slave SDO #2 SS SCK SDI SPI Slave SDO #3 SS FIGURE 24-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Shift register SSPSR and bit count are reset SSPBUF to SSPSR SDO bit 7 bit 6 bit 7 bit 6 bit 0 SDI bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF  2011-2013 Microchip Technology Inc. DS40001574C-page 243

PIC16(L)F1938/9 FIGURE 24-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE=0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active FIGURE 24-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active DS40001574C-page 244  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 24.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmis- In SPI Master mode, module clocks may be operating sion/reception will remain in that state until the device at a different speed than when in Full-Power mode; in wakes. After the device returns to Run mode, the mod- the case of the Sleep mode, all clocks are halted. ule will resume transmitting and receiving data. Special care must be taken by the user when the MSSP In SPI Slave mode, the SPI Transmit/Receive Shift clock is much faster than the system clock. register operates asynchronously to the device. This In Slave mode, when MSSP interrupts are enabled, allows the device to be placed in Sleep mode and data after the master completes sending data, an MSSP to be shifted into the SPI Transmit/Receive Shift interrupt will wake the controller from Sleep. register. When all eight bits have been received, the If an exit from Sleep mode is not desired, MSSP MSSP interrupt flag bit will be set and if enabled, will interrupts should be disabled. wake the device. TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 126 APFCON — CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 123 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 91 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 94 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 239* SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 283 SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 285 SSPSTAT SMP CKE D/A P S R/W UA BF 282 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISB2 TRISC1 TRISC0 134 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. * Page provides register information.  2011-2013 Microchip Technology Inc. DS40001574C-page 245

PIC16(L)F1938/9 24.3 I2C™ Mode Overview FIGURE 24-11: I2C MASTER/ SLAVE CONNECTION The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master VDD devices initiate the communication. A Slave device is controlled through addressing. SCL SCL The I2C bus specifies two signal connections: VDD • Serial Clock (SCL) Master Slave • Serial Data (SDA) Figure24-11 shows the block diagram of the MSSP SDA SDA module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal, supply voltage. Pulling the line to ground is considered which holds the SDA line low to indicate to the transmit- a logical zero and letting the line float is considered a ter that the slave device has received the transmitted logical one. data and is ready to receive more. Figure24-11 shows a typical connection between two The transition of a data bit is always performed while processors configured as master and slave devices. the SCL line is held low. Transitions that occur while the The I2C bus can operate with one or more master SCL line is held high are used to indicate Start and Stop devices and one or more slave devices. bits. There are four potential modes of operation for a given If the master intends to write to the slave, then it repeat- device: edly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the • Master Transmit mode master device is in Master Transmit mode and the (master is transmitting data to a slave) slave is in Slave Receive mode. • Master Receive mode (master is receiving data from a slave) If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and • Slave Transmit mode responds after each byte with an ACK bit. In this exam- (slave is transmitting data to a master) ple, the master device is in Master Receive mode and • Slave Receive mode the slave is Slave Transmit mode. (slave is receiving data from the master) On the last byte of data communicated, the master To begin communication, a master device starts out in device may end the transmission by sending a Stop bit. Master Transmit mode. The master device sends out a If the master device is in Receive mode, it sends the Start bit followed by the address byte of the slave it Stop bit in place of the last ACK bit. A Stop bit is indi- intends to communicate with. This is followed by a sin- cated by a low-to-high transition of the SDA line while gle Read/Write bit, which determines whether the mas- the SCL line is held high. ter intends to transmit to or receive data from the slave device. In some cases, the master may want to maintain con- trol of the bus and re-initiate another transmission. If If the requested slave exists on the bus, it will respond so, the master device may send another Start bit in with an Acknowledge bit, otherwise known as an ACK. place of the Stop bit or last ACK bit when it is in Receive The master then continues in either Transmit mode or mode. Receive mode and the slave continues in the comple- ment, either in Receive mode or Transmit mode, The I2C bus specifies three message protocols; respectively. • Single message where a master writes data to a A Start bit is indicated by a high-to-low transition of the slave. SDA line while the SCL line is held high. Address and • Single message where a master reads data from data bytes are sent out, Most Significant bit (MSb) first. a slave. The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a out as a logical zero when it intends to write data to the combination of writes and reads, to one or more slave. slaves. DS40001574C-page 246  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 When one device is transmitting a logical one, or letting Slave Transmit mode can also be arbitrated, when a the line float, and a second device is transmitting a log- master addresses multiple slaves, but this is less com- ical zero, or holding the line low, the first device can mon. detect that the line is not a logical one. This detection, If two master devices are sending a message to two dif- when used on the SCL line, is called clock stretching. ferent slave devices at the address stage, the master Clock stretching gives slave devices a mechanism to sending the lower slave address always wins arbitra- control the flow of data. When this detection is used on tion. When two master devices send messages to the the SDA line, it is called arbitration. Arbitration ensures same slave address, and addresses can sometimes that there is only one master device communicating at refer to multiple slaves, the arbitration process must any single time. continue into the data stage. 24.3.1 CLOCK STRETCHING Arbitration usually occurs very rarely, but it is a neces- sary process for proper multi-master support. When a slave device has not completed processing data, it can delay the transfer of more data through the 24.4 I2C™ Mode Operation process of Clock Stretching. An addressed slave device may hold the SCL clock line low after receiving All MSSP I2C communication is byte oriented and or sending a bit, indicating that it is not yet ready to con- shifted out MSb first. Six SFR registers and 2 interrupt tinue. The master that is communicating with the slave flags interface the module with the PIC® microcon- will attempt to raise the SCL line in order to transfer the troller and user software. Two pins, SDA and SCL, are next bit, but will detect that the clock line has not yet exercised by the module to communicate with other been released. Because the SCL connection is external I2C devices. open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. 24.4.1 BYTE FORMAT Clock stretching allows receivers that cannot keep up All communication in I2C is done in 9-bit segments. A with a transmitter to control the flow of incoming data. byte is sent from a Master to a Slave or vice-versa, followed by an Acknowledge bit sent back. After the 24.3.2 ARBITRATION eighth falling edge of the SCL line, the device output- Each master device must monitor the bus for Start and ting data on the SDA changes that pin to an input and Stop bits. If the device detects that the bus is busy, it reads in an acknowledge value on the next clock cannot begin a new message until the bus returns to an pulse. Idle state. The clock signal, SCL, is provided by the master. Data However, two master devices may try to initiate a trans- is valid to change while the SCL signal is low, and mission on or about the same time. When this occurs, sampled on the rising edge of the clock. Changes on the process of arbitration begins. Each transmitter the SDA line while the SCL line is high define special checks the level of the SDA data line and compares it conditions on the bus, explained below. to the level that it expects to find. The first transmitter to 24.4.2 DEFINITION OF I2C TERMINOLOGY observe that the two levels do not match, loses arbitra- tion, and must stop transmitting on the SDA line. There is language and terminology in the description For example, if one transmitter holds the SDA line to a of I2C communication that have definitions specific to logical one (lets it float) and a second transmitter holds I2C. That word usage is defined below and may be it to a logical zero (pulls it low), the result is that the used in the rest of this document without explana- SDA line will be low. The first transmitter then observes tion. This table was adapted from the Philips I2C that the level of the line is different than expected and specification. concludes that another transmitter is communicating. 24.4.3 SDA AND SCL PINS The first transmitter to notice this difference is the one Selection of any I2C mode with the SSPEN bit set, that loses arbitration and must stop driving the SDA forces the SCL and SDA pins to be open-drain. These line. If this transmitter is also a master device, it also pins should be set by the user to inputs by setting the must stop driving the SCL line. It then can monitor the appropriate TRIS bits. lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that Note: Data is tied to output zero when an I2C has not noticed any difference between the expected mode is enabled. and actual levels on the SDA line continues with its original transmission. It can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message.  2011-2013 Microchip Technology Inc. DS40001574C-page 247

PIC16(L)F1938/9 24.4.4 SDA HOLD TIME TABLE 24-2: I2C BUS TERMS The hold time of the SDA pin is selected by the SDAHT TERM Description bit of the SSPCON3 register. Hold time is the time SDA Transmitter The device which shifts data out is held valid after the falling edge of SCL. Setting the onto the bus. SDAHT bit selects a longer 300ns minimum hold time Receiver The device which shifts data in and may help on buses with large capacitance. from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Addressed Slave device that has received a Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is out- putting and expected high state. DS40001574C-page 248  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 24.4.5 START CONDITION has the same effect on the slave that a Start would, The I2C specification defines a Start condition as a resetting all slave logic and preparing it to clock in an address. The master may want to address the same or transition of SDA from a high to a low state while SCL another slave. line is high. A Start condition is always generated by the master and signifies the transition of the bus from In 10-bit Addressing Slave mode a Restart is required an Idle to an Active state. Figure24-12 shows wave for the master to clock data out of the addressed forms for Start and Stop conditions. slave. Once a slave has been fully addressed, match- ing both high and low address bytes, the master can A bus collision can occur on a Start condition if the issue a Restart and the high address byte with the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that R/W bit set. The slave logic will then hold the clock and prepare to clock out data. states no bus collision can occur on a Start. After a full match with R/W clear in 10-bit mode, a prior 24.4.6 STOP CONDITION match flag is set and maintained. Until a Stop condi- tion, a high address with R/W clear, or high address A Stop condition is a transition of the SDA line from match fails. low-to-high state while the SCL line is high. Note: At least one SCL low time must appear 24.4.8 START/STOP CONDITION before a Stop is valid, therefore, if the SDA INTERRUPT MASKING line goes low then high again while the SCL The SCIE and PCIE bits of the SSPCON3 register can line stays high, only the Start condition is enable the generation of an interrupt in Slave modes detected. that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already 24.4.7 RESTART CONDITION enabled, these bits will have no effect. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart FIGURE 24-12: I2C START AND STOP CONDITIONS SDA SCL S P Change of Change of Data Allowed Data Allowed Start Stop Condition Condition FIGURE 24-13: I2C RESTART CONDITION Sr Change of Change of Data Allowed Data Allowed Restart Condition  2011-2013 Microchip Technology Inc. DS40001574C-page 249

PIC16(L)F1938/9 24.4.9 ACKNOWLEDGE SEQUENCE 24.5 I2C Slave Mode Operation The ninth SCL pulse for any transferred byte in I2C is The MSSP Slave mode operates in one of four modes dedicated as an Acknowledge. It allows receiving selected in the SSPM bits of SSPCON1 register. The devices to respond back to the transmitter by pulling modes can be divided into 7-bit and 10-bit Addressing the SDA line low. The transmitter must release control mode. 10-bit Addressing modes operate the same as of the line during this time to shift in the response. The 7-bit with some additional overhead for handling the Acknowledge (ACK) is an active-low signal, pulling the larger addresses. SDA line low indicated to the transmitter that the Modes with Start and Stop bit interrupts operated the device has received the transmitted data and is ready same as the other modes with SSPIF additionally to receive more. getting set upon detection of a Start, Restart, or Stop The result of an ACK is placed in the ACKSTAT bit of condition. the SSPCON2 register. 24.5.1 SLAVE MODE ADDRESSES Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to The SSPADD register (Register24-6) contains the the transmitter. The ACKDT bit of the SSPCON2 regis- Slave mode address. The first byte received after a ter is set/cleared to determine the response. Start or Restart condition is compared against the Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the AHEN and DHEN bits of the SSPCON3 register are value is loaded into the SSPBUF register and an inter- clear. rupt is generated. If the value does not match, the module goes idle and no indication is given to the soft- There are certain conditions where an ACK will not be ware that anything happened. sent by the slave. If the BF bit of the SSPSTAT register or the SSPOV bit of the SSPCON1 register are set The SSP Mask register (Register24-5) affects the when a byte is received. address matching process. See Section24.5.9 “SSP Mask Register” for more information. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit of the 24.5.1.1 I2C Slave 7-bit Addressing Mode SSPCON3 register is set. The ACKTIM bit indicates In 7-bit Addressing mode, the LSb of the received data the acknowledge time of the active bus. The ACKTIM byte is ignored when determining if there is an address Status bit is only active when the AHEN bit or DHEN match. bit is enabled. 24.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPADD. Even if there is not an address match; SSPIF and UA are set, and SCL is held low until SSPADD is updated to receive a high byte again. When SSPADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communi- cation. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hard- ware will then acknowledge the read request and pre- pare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS40001574C-page 250  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 24.5.2 SLAVE RECEPTION 24.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPSTAT register is cleared. Slave device reception with AHEN and DHEN set The received address is loaded into the SSPBUF reg- operate the same as without these options with extra ister and acknowledged. interrupts and clock stretching added after the eighth When the overflow condition exists for a received falling edge of SCL. These additional interrupts allow address, then not Acknowledge is given. An overflow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hard- condition is defined as either bit BF of the SSPSTAT register is set, or bit SSPOV of the SSPCON1 register ware. This functionality adds support for PMBus™ that is set. The BOEN bit of the SSPCON3 register modifies was not present on previous versions of this module. this operation. For more information see Register24-4. This list describes the steps that need to be taken by An MSSP interrupt is generated for each transferred slave software to use these options for I2C communi- cation. Figure24-16 displays a module using both data byte. Flag bit, SSPIF, must be cleared by software. address and data holding. Figure24-17 includes the When the SEN bit of the SSPCON2 register is set, SCL operation with the SEN bit of the SSPCON2 register will be held low (clock stretch) following each received set. byte. The clock must be released by setting the CKP 1. S bit of SSPSTAT is set; SSPIF is set if interrupt bit of the SSPCON1 register, except sometimes in 10-bit mode. See Section24.2.3 “SPI Master Mode” on Start detect is enabled. for more detail. 2. Matching address with R/W bit clear is clocked in. SSPIF is set and CKP cleared after the eighth 24.5.2.1 7-bit Addressing Reception falling edge of SCL. This section describes a standard sequence of events 3. Slave clears the SSPIF. for the MSSP module configured as an I2C Slave in 4. Slave can look at the ACKTIM bit of the 7-bit Addressing mode. All decisions made by hard- SSPCON3 register to determine if the SSPIF ware or software and their effect on reception. was after or before the ACK. Figure24-14 and Figure24-15 is used as a visual 5. Slave reads the address value from SSPBUF, reference for this description. clearing the BF flag. This is a step by step process of what typically must 6. Slave sets ACK value clocked out to the master be done to accomplish I2C communication. by setting ACKDT. 1. Start bit detected. 7. Slave releases the clock by setting CKP. 2. S bit of SSPSTAT is set; SSPIF is set if interrupt 8. SSPIF is set after an ACK, not after a NACK. on Start detect is enabled. 9. If SEN=1 the slave hardware will stretch the 3. Matching address with R/W bit clear is received. clock after the ACK. 4. The slave pulls SDA low sending an ACK to the 10. Slave clears SSPIF. master, and sets SSPIF bit. Note: SSPIF is still set after the ninth falling edge 5. Software clears the SSPIF bit. of SCL even if there is no clock stretching 6. Software reads received address from SSPBUF and BF has been cleared. Only if NACK is clearing the BF flag. sent to Master is SSPIF not set 7. If SEN=1; Slave software sets CKP bit to 11. SSPIF set and CKP cleared after eighth falling release the SCL line. edge of SCL for a received data byte. 8. The master clocks out a data byte. 12. Slave looks at ACKTIM bit of SSPCON3 to 9. Slave drives SDA low sending an ACK to the determine the source of the interrupt. master, and sets SSPIF bit. 13. Slave reads the received data from SSPBUF 10. Software clears SSPIF. clearing BF. 11. Software reads the received byte from SSPBUF 14. Steps 7-14 are the same for each received data clearing BF. byte. 12. Steps 8-12 are repeated for all received bytes 15. Communication is ended by either the slave from the Master. sending an ACK=1, or the master sending a Stop condition. If a Stop is sent and Interrupt on 13. Master sends Stop condition, setting P bit of Stop Detect is disabled, the slave will only know SSPSTAT, and the bus goes idle. by polling the P bit of the SSTSTAT register.  2011-2013 Microchip Technology Inc. DS40001574C-page 251

PIC16(L)F1938/9 FIGURE 24-14: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=0, DHEN=0) s d Bus Master senStop condition 1 P SSPIF set on 9thfalling edge of SCL = K 9 C A D0 8 e Master eceiving Data D4D3D2D1 4567 eared by software SSPOV set becausSSPBUF is still full. ACK is not sent. e to R D5 3 Cl v From Sla D7D6K 12 First byte of data is available in SSPBUF C 9 A D0 8 D1 7 d a Receiving Data D5D4D3D2 3456 Cleared by software SSPBUF is re D6 2 D7 1 K 9 C A 8 A1 7 2 6 A s s dre A3 5 d A ng A4 4 vi ecei A5 3 R A6 2 A7 1 S V F O DA CL SPI BF SP S S S S DS40001574C-page 252  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-15: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) Bus Master sends Stop condition P SSPIF set on 9thfalling edge of SCL SCL is not heldlow becauseACK=1 K C 9 A D0 8 e Receive Data D7D6D5D4D3D2D1 1234567 Cleared by software First byte of data is available in SSPBUF SSPOV set becausSSPBUF is still full. ACK is not sent. CKP is written to ‘’ in software, 1releasing SCL N E S K AC 9 D0 8 ’1 o ‘ Data D2D1 67 KP is set t oftware, Receive D7D6D5D4D3 12345 Clock is held low until C Cleared by software SSPBUF is read CKP is written to ‘’ in s1releasing SCL N E S K C A 9 0 = W R/ 8 A1 7 2 6 A s s dre A3 5 d e A A4 4 v ei ec A5 3 R 6 2 A A7 1 S V P SDA SCL SSPIF BF SSPO CK  2011-2013 Microchip Technology Inc. DS40001574C-page 253

PIC16(L)F1938/9 FIGURE 24-16: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=1) Master sendsStop condition =1 P No interruptafter not ACKfrom Slave CK 9 A are T to Received DataCKD7D6D5D4D3D2D1D0 912345678 Cleared by software a is read from SSPBUF Slave softwsets ACKDnot ACK CKP set by software, SCL is released ACKTIM set by hardwareon 8th falling edge of SCL A at D D0 8 g Receiving Data D6D5D4D3D2D1 234567 SPIF is set on h falling edge of CL, after ACK When DHEN=:1CKP is cleared byhardware on 8th fallinedge of SCL KTIM cleared bydware in 9th ng edge of SCL D7 1 S9tS ACharrisi K 9 ce C n A e Aqu De es SCK s sA Master Releato slave for Receiving Address A7A6A5A4A3A2A1 12345678 If AHEN=:1SSPIF is set Address isread from SSBUF Slave softwareclears ACKDT to ACK the receivedbyte When AHEN=:1CKP is cleared by hardwareand SCL is stretched ACKTIM set by hardwareon 8th falling edge of SCL S M SDA SCL SSPIF BF ACKDT CKP ACKTI S P DS40001574C-page 254  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-17: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN= 1, AHEN=1, DHEN=1) Master sendsStop condition P No interrupt afterif not ACKfrom Slave CKP is not clearedif not ACK K 9 C A D0 8 s d D1 7 enK Receive Data D6D5D4D3D2 23456 SSPBUF can beread any time beforenext byte is loaded Slave snot AC Set by software,release SCL D7 1 K C 9 A D0 8 e K sequence Receive Data D7D6D5D4D3D2D1 1245673 Cleared by software Received data isavailable on SSPBUF When DHEN = ;1on the 8th falling edgeof SCL of a receiveddata byte, CKP is cleared ACKTIM is cleared by hardwaron 9th rising edge of SCL C A ster releasesA to slave for ACK 9 aD MS 8 s R/W = 0 Receiving Address A6A5A4A3A2A1 342567 Received address is loaded into SSPBUF Slave software clearACKDT to ACKthe received byte When AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared KTIM is set by hardware8th falling edge of SCL A7 1 ACon S M TI SDA SCL SSPIF BF ACKDT CKP ACK S P  2011-2013 Microchip Technology Inc. DS40001574C-page 255

PIC16(L)F1938/9 24.5.3 SLAVE TRANSMISSION 24.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set A master device can transmit a read request to a and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list SSPSTAT register is set. The received address is below outlines what software for a slave will need to loaded into the SSPBUF register, and an ACK pulse is do to accomplish a standard transmission. sent by the slave on the ninth bit. Figure24-18 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and and the SCL pin is held low (see Section24.5.6 SCL. “Clock Stretching” for more detail). By stretching the 2. S bit of SSPSTAT is set; SSPIF is set if interrupt clock, the master will be unable to assert another clock on Start detect is enabled. pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by data. the Slave setting SSPIF bit. The transmit data must be loaded into the SSPBUF 4. Slave hardware generates an ACK and sets register which also loads the SSPSR register. Then the SSPIF. SCL pin should be released by setting the CKP bit of 5. SSPIF bit is cleared by user. the SSPCON1 register. The eight data bits are shifted 6. Software reads the received address from out on the falling edge of the SCL input. This ensures SSPBUF, clearing BF. that the SDA signal is valid during the SCL high time. 7. R/W is set so CKP was automatically cleared The ACK pulse from the master-receiver is latched on after the ACK. the rising edge of the ninth SCL input pulse. This ACK 8. The slave software loads the transmit data into value is copied to the ACKSTAT bit of the SSPCON2 SSPBUF. register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is 9. CKP bit is set releasing SCL, allowing the latched by the slave, the slave goes idle and waits for master to clock the data out of the slave. another occurrence of the Start bit. If the SDA line was 10. SSPIF is set after the ACK response from the low (ACK), the next transmit data must be loaded into master is loaded into the ACKSTAT register. the SSPBUF register. Again, the SCL pin must be 11. SSPIF bit is cleared. released by setting bit CKP. 12. The slave software checks the ACKSTAT bit to An MSSP interrupt is generated for each data transfer see if the master wants to clock out more data. byte. The SSPIF bit must be cleared by software and Note 1: If the master ACKs the clock will be the SSPSTAT register is used to determine the status stretched. of the byte. The SSPIF bit is set on the falling edge of 2: ACKSTAT is the only bit updated on the the ninth clock pulse. rising edge of SCL (9th) rather than the 24.5.3.1 Slave Mode Bus Collision falling. A slave receives a Read request and begins shifting 13. Steps 9-13 are repeated for each transmitted data out on the SDA line. If a bus collision is detected byte. and the SBCDE bit of the SSPCON3 register is set, the 14. If the master sends a not ACK; the clock is not BCLIF bit of the PIR register is set. Once a bus collision held, but SSPIF is still set. is detected, the slave goes idle and waits to be 15. The master sends a Restart condition or a Stop. addressed again. User software can use the BCLIF bit 16. The slave is no longer addressed. to handle a slave bus collision. DS40001574C-page 256  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-18: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=0) sn do enditi er scon P stp ao MSt K C 9 A Transmitting Data D7D6D5D4D3D2D1D0 12345678 BF is automatically cleared after 8th fallingedge of SCL CKP is not held for not ACK Masters not ACKis copied to ACKSTAT c ati m o ut A K AC 9 D0 8 1 D 7 a Dat D2 6 Transmitting D7D6D5D4D3 12345 Cleared by software Data to transmit isloaded into SSPBUF Set by software c ati m o ut A 1CK =A 9 W R/ 8 eceiving Address A5A4A3A2A1 34567 Received addressis read from SSPBUF When R/W is setSCL is alwaysheld low after 9th SCLfalling edge R/W is copied from the matching address byte Indicates an address has been received R 6 A 2 7 A 1 S T A SDA SCL SSPIF BF CKP ACKST R/W D/A S P  2011-2013 Microchip Technology Inc. DS40001574C-page 257

PIC16(L)F1938/9 24.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPCON3 register enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure24-19 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. Bus starts Idle. 2. Master sends Start condition; the S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSPIF interrupt is generated. 4. Slave software clears SSPIF. 5. Slave software reads ACKTIM bit of SSPCON3 register, and R/W and D/A of the SSPSTAT reg- ister to determine the source of the interrupt. 6. Slave reads the address value from the SSPBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSPCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPIF after the ACK if the R/W bit is set. 11. Slave software clears SSPIF. 12. Slave loads value to transmit to the master into SSPBUF setting the BF bit. Note: SSPBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the ninth SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPCON2 register. 16. Steps 10-15 are repeated for each byte transmit- ted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS40001574C-page 258  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-19: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=1) endsdition sn aster op co P MSt K C A 9 0 D 8 Transmitting Data D5D4D3D2D1 34567 F is automatically eared after 8th fallingge of SCL Master’s ACKresponse is copiedto SSPSTAT CKP not cleared after not ACK D6 2 Bcled 7 D 1 c ati m o AutK C A 9 D0 8 1 a D 7 at D 2 ence omaticTransmitting D7D6D5D4D3D 123456 Cleared by software Data to transmit isloaded into SSPBUF Set by software,releases SCL KTIM is cleared9th rising edge of SCL DAequ Aut ACon Ss K Master releases to slave for ACK W=1AC 9 When R/W = ;1CKP is alwayscleared after ACK Receiving AddressR/ A7A6A5A4A3A2A1 12345678 Received addressis read from SSPBUF Slave clearsACKDT to ACKaddress When AHEN = ;1CKP is cleared by hardwareafter receiving matchingaddress. ACKTIM is set on 8th fallingedge of SCL S SDA SCL SPIF BF CKDT STAT CKP KTIM R/W D/A S A K C C A A  2011-2013 Microchip Technology Inc. DS40001574C-page 259

PIC16(L)F1938/9 24.5.4 SLAVE MODE 10-BIT ADDRESS 24.5.5 10-BIT ADDRESSING WITH RECEPTION ADDRESS OR DATA HOLD This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or for the MSSP module configured as an I2C Slave in DHEN set is the same as with 7-bit modes. The only 10-bit Addressing mode. difference is the need to update the SSPADD register using the UA bit. All functionality, specifically when the Figure24-20 is used as a visual reference for this CKP bit is cleared and SCL line is held low are the description. same. Figure24-21 can be used as a reference of a This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set. slave software to accomplish I2C communication. Figure24-22 shows a standard waveform for a slave 1. Bus starts Idle. transmitter in 10-bit Addressing mode. 2. Master sends Start condition; S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Master sends matching high address with R/W bit clear; UA bit of the SSPSTAT register is set. 4. Slave sends ACK and SSPIF is set. 5. Software clears the SSPIF bit. 6. Software reads received address from SSPBUF clearing the BF flag. 7. Slave loads low address into SSPADD, releasing SCL. 8. Master sends matching low address byte to the Slave; UA bit is set. Note: Updates to the SSPADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPIF is set. Note: If the low address does not match, SSPIF and UA are still set so that the slave soft- ware can set SSPADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPIF. 11. Slave reads the received matching address from SSPBUF clearing BF. 12. Slave loads high address into SSPADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSPIF is set. 14. If SEN bit of SSPCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPIF. 16. Slave reads the received byte from SSPBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS40001574C-page 260  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-20: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) endsdition er scon P stp ao MSt K C 9 A 0 8 D a D1 7 F at dU D 2 6 aB Receive D6D5D4D3D 2345 SCL is held lowwhile CKP = 0 Data is refrom SSP Set by software,releasing SCLyte D7 1 d b e v K cei Receive Data D6D5D4D3D2D1D0AC 92345678 Cleared by software Receive address isread from SSPBUF When SEN = ;1CKP is cleared after9th falling edge of re D7 1 K C e A 9 ess Byt A1A0 78 PADD Receive Second Addr A6A5A4A3A2 23456 Software updates SSand releases SCL A7 1 K C 9 A ve First Address Byte 0A9A811 345678 Set by hardwareon 9th falling edge If address matchesSSPADD it is loaded into SSPBUF When UA = ;1SCL is held low ei 1 2 c e R 1 1 S SDA SCL SPIF BF UA CKP S  2011-2013 Microchip Technology Inc. DS40001574C-page 261

PIC16(L)F1938/9 FIGURE 24-21: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=0) a Receive Data D7D6D5 12 Received datis read from SSPBUF K C 9 A D0 8 D1 7 s e Receive Data D6D5D4D3D2 23456 eared by software Update of SSPADD,clears UA and releasSCL CKP with software ases SCL D7 1 Cl Set rele A U K C 9 A 0 A 8 Receive Second Address Byte A6A5A4A3A2A1 345672 ed by software SSPBUF can beread anytime beforethe next received byte ate to SSPADD isallowed until 9thng edge of SCL A7 1 Clear Updnot falli A U K C 9 A 0 = W 8 R/ e eive First Address Byte A9A8110 34567 Set by hardwareon 9th falling edge Slave software clearsACKDT to ACKthe received byte If when AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared ACKTIM is set by hardwaron 8th falling edge of SCL ec 1 2 R 1 1 S T M SDA SCL SSPIF BF ACKD UA CKP ACKTI DS40001574C-page 262  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN=0, AHEN=0, DHEN=0) ends dition er scon P MastStop K = 1 ds AC 9 en D0 8 K Master snot ACK Transmitting Data Byte D7D6D5D4D3D2D1 1723456 Data to transmit isloaded into SSPBUF Set by softwarereleases SCL Masters not ACis copied K C A 9 e 8 aster sends estart event Receive First Address Byt A9A811110 1672345Sr Set by hardware Received address isread from SSPBUF High address is loadedback into SSPADD When R/W = ;1CKP is cleared on9th falling edge of SCL R/W is copied from thematching address byte MR K yte AC 9 s B A0 8 ed eiving Second Addres A6A5A4A3A2A1 672345 Cleared by software After SSPADD isupdated, UA is clearand SCL is released c Re A7 1 K = 0 AC 9 W 8 Receiving AddressR/ A9A811110 1672345 Set by hardware SSPBUF loadedwith received address UA indicates SSPADDmust be updated Indicates an addresshas been received S AT T S SDA SCL SPIF BF UA CKP ACK R/W D/A S  2011-2013 Microchip Technology Inc. DS40001574C-page 263

PIC16(L)F1938/9 24.5.6 CLOCK STRETCHING 24.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set, the holds the SCL line low effectively pausing communica- clock is always stretched. This is the only time the SCL tion. The slave may stretch the clock to allow more is stretched without CKP being cleared. SCL is time to handle data or prepare a response for the mas- released immediately after a write to SSPADD. ter device. A master device is not concerned with Note: Previous versions of the module did not stretching as anytime it is active on the bus and not stretch the clock if the second address byte transferring data it is stretching. Any stretching done did not match. by a slave is invisible to the master software and han- dled by the hardware that generates SCL. 24.5.6.3 Byte NACKing The CKP bit of the SSPCON1 register is used to con- When AHEN bit of SSPCON3 is set; CKP is cleared by trol stretching in software. Any time the CKP bit is hardware after the eighth falling edge of SCL for a cleared, the module will wait for the SCL line to go low received matching address byte. When DHEN bit of and then hold it. Setting CKP will release SCL and SSPCON3 is set; CKP is cleared after the eighth allow more communication. falling edge of SCL for received data. 24.5.6.1 Normal Clock Stretching Stretching after the eighth falling edge of SCL allows Following an ACK if the R/W bit of SSPSTAT is set, a the slave to look at the received address or data and read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data. allows the slave time to update SSPBUF with data to 24.5.7 CLOCK SYNCHRONIZATION AND transfer to the master. If the SEN bit of SSPCON2 is THE CKP BIT set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait is set by software and communication resumes. for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low Note 1: The BF bit has no effect on if the clock will until the SCL output is already sampled low. There- be stretched or not. This is different than fore, the CKP bit will not assert the SCL line until an previous versions of the module that external I2C master device has already asserted the would not stretch the clock, clear CKP, if SCL line. The SCL output will remain low until the CKP SSPBUF was read before the ninth falling bit is set and all other devices on the I2C bus have edge of SCL. released SCL. This ensures that a write to the CKP bit 2: Previous versions of the module did not will not violate the minimum high time requirement for stretch the clock for a transmission if SCL (see Figure24-23). SSPBUF was loaded before the ninth fall- ing edge of SCL. It is now always cleared for read requests. FIGURE 24-23: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX ‚ – 1 SCL Master device CKP asserts clock Master device releases clock WR SSPCON1 DS40001574C-page 264  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 24.5.8 GENERAL CALL ADDRESS In 10-bit Address mode, the UA bit will not be set on SUPPORT the reception of the general call address. The slave will prepare to receive the second byte as data, just as The addressing procedure for the I2C bus is such that it would in 7-bit mode. the first byte after the Start condition usually deter- mines which device will be the slave addressed by the If the AHEN bit of the SSPCON3 register is set, just as master device. The exception is the general call with any other address reception, the slave hardware address which can address all devices. When this will stretch the clock after the eighth falling edge of address is used, all devices should, in theory, respond SCL. The slave must then set its ACKDT value and with an acknowledge. release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPCON2 register is set, the Slave module will automatically ACK the reception of this address regardless of the value stored in SSPADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPBUF and respond. Figure24-24 shows a general call reception sequence. FIGURE 24-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared by software SSPBUF is read GCEN (SSPCON2<7>) ’1’ 24.5.9 SSP MASK REGISTER An SSP Mask (SSPMSK) register (Register24-5) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the reception of the first (high) byte of the address.  2011-2013 Microchip Technology Inc. DS40001574C-page 265

PIC16(L)F1938/9 24.6 I2C Master Mode 24.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the The master device generates all of the serial clock appropriate SSPM bits in the SSPCON1 register and pulses and the Start and Stop conditions. A transfer is by setting the SSPEN bit. In Master mode, the SDA and ended with a Stop condition or with a Repeated Start SCK pins must be configured as inputs. The MSSP condition. Since the Repeated Start condition is also peripheral hardware will override the output driver TRIS the beginning of the next serial transfer, the I2C bus will not be released. controls when necessary to drive the pins low. Master mode of operation is supported by interrupt In Master Transmitter mode, serial data is output generation on the detection of the Start and Stop con- through SDA, while SCL outputs the serial clock. The ditions. The Stop (P) and Start (S) bits are cleared from first byte transmitted contains the slave address of the a Reset or when the MSSP module is disabled. Control receiving device (7 bits) and the Read/Write (R/W) bit. of the I2C bus may be taken when the P bit is set, or the In this case, the R/W bit will be logic ‘0’. Serial data is bus is Idle. transmitted eight bits at a time. After each byte is trans- mitted, an Acknowledge bit is received. Start and Stop In Firmware Controlled Master mode, user code conditions are output to indicate the beginning and the conducts all I2C bus operations based on Start and end of a serial transfer. Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted con- other communication is done by the user software tains the slave address of the transmitting device directly manipulating the SDA and SCL lines. (7bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave The following events will cause the SSP Interrupt Flag address followed by a ‘1’ to indicate the receive bit. bit, SSPIF, to be set (SSP interrupt, if enabled): Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. • Start condition detected After each byte is received, an Acknowledge bit is • Stop condition detected transmitted. Start and Stop conditions indicate the • Data transfer byte transmitted/received beginning and end of transmission. • Acknowledge transmitted/received A Baud Rate Generator is used to set the clock fre- • Repeated Start generated quency output on SCL. See Section24.7 “Baud Rate Note 1: The MSSP module, when configured in Generator” for more detail. I2C Master mode, does not allow queue- ing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start con- dition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur 2: When in Master mode, Start/Stop detec- tion is masked and an interrupt is gener- ated when the SEN/PEN bit is cleared and the generation is complete. DS40001574C-page 266  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 24.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and begins count- ing. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure24-25). FIGURE 24-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX ‚ – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload 24.6.3 WCOL STATUS FLAG If the user writes the SSPBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPBUF was attempted while the module was not idle. Note: Because queuing of events is not allowed, writing to the lower five bits of SSPCON2 is disabled until the Start condition is complete.  2011-2013 Microchip Technology Inc. DS40001574C-page 267

PIC16(L)F1938/9 24.6.4 I2C MASTER MODE START hardware; the Baud Rate Generator is suspended, CONDITION TIMING leaving the SDA line held low and the Start condition is complete. To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the Note 1: If at the beginning of the Start condition, SDA and SCL pins are sampled high, the Baud Rate the SDA and SCL pins are already sam- Generator is reloaded with the contents of pled low, or if during the Start condition, SSPADD<7:0> and starts its count. If SCL and SDA the SCL line is sampled low before the are both sampled high when the Baud Rate Generator SDA line is driven low, a bus collision times out (TBRG), the SDA pin is driven low. The action occurs, the Bus Collision Interrupt Flag, of the SDA being driven low while SCL is high is the BCLIF, is set, the Start condition is Start condition and causes the S bit of the SSPSTAT1 aborted and the I2C module is reset into register to be set. Following this, the Baud Rate its Idle state. Generator is reloaded with the contents of 2: The Philips I2C™ Specification states that SSPADD<7:0> and resumes its count. When the Baud a bus collision cannot occur on a Start. Rate Generator times out (TBRG), the SEN bit of the SSPCON2 register will be automatically cleared by FIGURE 24-26: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPSTAT<3>) At completion of Start bit, SDA = 1, hardware clears SEN bit SCL = 1 and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here SDA 1st bit 2nd bit TBRG SCL S TBRG DS40001574C-page 268  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 24.6.5 I2C MASTER MODE REPEATED SSPCON2 register will be automatically cleared and START CONDITION TIMING the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is A Repeated Start condition occurs when the RSEN bit detected on the SDA and SCL pins, the S bit of the of the SSPCON2 register is programmed high and the SSPSTAT register will be set. The SSPIF bit will not be Master state machine is no longer active. When the set until the Baud Rate Generator has timed out. RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is Note1: If RSEN is programmed while any other loaded and begins counting. The SDA pin is released event is in progress, it will not take effect. (brought high) for one Baud Rate Generator count 2: A bus collision during the Repeated Start (TBRG). When the Baud Rate Generator times out, if condition occurs if: SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud • SDA is sampled low when SCL Rate Generator is reloaded and begins counting. SDA goes from low-to-high. and SCL must be sampled high for one TBRG. This • SCL goes low before SDA is action is then followed by assertion of the SDA pin asserted low. This may indicate (SDA=0) for one TBRG while SCL is high. SCL is that another master is attempting to asserted low. Following this, the RSEN bit of the transmit a data ‘1’. FIGURE 24-27: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPCON2 occurs here At completion of Start bit, SDA = 1, SDA = 1, hardware clears RSEN bit SCL (no change) SCL = 1 and sets SSPIF TBRG TBRG TBRG SDA 1st bit Write to SSPBUF occurs here TBRG SCL Sr TBRG Repeated Start  2011-2013 Microchip Technology Inc. DS40001574C-page 269

PIC16(L)F1938/9 24.6.6 I2C MASTER MODE 24.6.6.3 ACKSTAT Status Flag TRANSMISSION In Transmit mode, the ACKSTAT bit of the SSPCON2 Transmission of a data byte, a 7-bit address or the register is cleared when the slave has sent an Acknowl- other half of a 10-bit address is accomplished by simply edge (ACK=0) and is set when the slave does not writing a value to the SSPBUF register. This action will Acknowledge (ACK=1). A slave sends an Acknowl- set the Buffer Full flag bit, BF and allow the Baud Rate edge when it has recognized its address (including a Generator to begin counting and start the next trans- general call), or when the slave has properly received mission. Each bit of address/data will be shifted out its data. onto the SDA pin after the falling edge of SCL is 24.6.6.4 Typical transmit sequence: asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL 1. The user generates a Start condition by setting is released high. When the SCL pin is released high, it the SEN bit of the SSPCON2 register. is held that way for TBRG. The data on the SDA pin 2. SSPIF is set by hardware on completion of the must remain stable for that duration and some hold Start. time after the next falling edge of SCL. After the eighth 3. SSPIF is cleared by software. bit is shifted out (the falling edge of the eighth clock), 4. The MSSP module will wait the required start the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to time before any other operation takes place. respond with an ACK bit during the ninth bit time if an 5. The user loads the SSPBUF with the slave address match occurred, or if data was received prop- address to transmit. erly. The status of ACK is written into the ACKSTAT bit 6. Address is shifted out the SDA pin until all eight on the rising edge of the ninth clock. If the master bits are transmitted. Transmission begins as receives an Acknowledge, the Acknowledge Status bit, soon as SSPBUF is written to. ACKSTAT, is cleared. If not, the bit is set. After the ninth 7. The MSSP module shifts in the ACK bit from the clock, the SSPIF bit is set and the master clock (Baud slave device and writes its value into the Rate Generator) is suspended until the next data byte ACKSTAT bit of the SSPCON2 register. is loaded into the SSPBUF, leaving SCL low and SDA 8. The MSSP module generates an interrupt at the unchanged (Figure24-28). end of the ninth clock cycle by setting the SSPIF After the write to the SSPBUF, each bit of the address bit. will be shifted out on the falling edge of SCL until all 9. The user loads the SSPBUF with eight bits of seven address bits and the R/W bit are completed. On data. the falling edge of the eighth clock, the master will 10. Data is shifted out the SDA pin until all eight bits release the SDA pin, allowing the slave to respond with are transmitted. an Acknowledge. On the falling edge of the ninth clock, 11. The MSSP module shifts in the ACK bit from the the master will sample the SDA pin to see if the address slave device and writes its value into the was recognized by a slave. The status of the ACK bit is ACKSTAT bit of the SSPCON2 register. loaded into the ACKSTAT Status bit of the SSPCON2 register. Following the falling edge of the ninth clock 12. Steps 8-11 are repeated for all transmitted data transmission of the address, the SSPIF is set, the BF bytes. flag is cleared and the Baud Rate Generator is turned 13. The user generates a Stop or Restart condition off until another write to the SSPBUF takes place, hold- by setting the PEN or RSEN bits of the ing SCL low and allowing SDA to float. SSPCON2 register. Interrupt is generated once the Stop/Restart condition is complete. 24.6.6.1 BF Status Flag In Transmit mode, the BF bit of the SSPSTAT register is set when the CPU writes to SSPBUF and is cleared when all eight bits are shifted out. 24.6.6.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. DS40001574C-page 270  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-28: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) ACKSTAT in SSPCON2 = 1 P ared by software K e C 9 Cl A > <6 D0 8 e 2 n slave, clear ACKSTAT bit SSPCON Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared by software service routifrom SSP interrupt SSPBUF is written by software From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to CK re R/W = 0 A1A ss and R/W 789 d by hardware ave A2 ddre 6 eare PCON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPBUF written with 7-bit astart transmit 12345 Cleared by software SSPBUF written After Start condition, SEN cl Sn Write SStart co S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W  2011-2013 Microchip Technology Inc. DS40001574C-page 271

PIC16(L)F1938/9 24.6.7 I2C MASTER MODE RECEPTION 24.6.7.4 Typical Receive Sequence: Master mode reception is enabled by programming the 1. The user generates a Start condition by setting Receive Enable bit, RCEN bit of the SSPCON2 the SEN bit of the SSPCON2 register. register. 2. SSPIF is set by hardware on completion of the Start. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the 3. SSPIF is cleared by software. RCEN bit will be disregarded. 4. User writes SSPBUF with the slave address to transmit and the R/W bit set. The Baud Rate Generator begins counting and on each 5. Address is shifted out the SDA pin until all eight rollover, the state of the SCL pin changes bits are transmitted. Transmission begins as (high-to-low/low-to-high) and data is shifted into the soon as SSPBUF is written to. SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the con- 6. The MSSP module shifts in the ACK bit from the tents of the SSPSR are loaded into the SSPBUF, the slave device and writes its value into the BF flag bit is set, the SSPIF flag bit is set and the Baud ACKSTAT bit of the SSPCON2 register. Rate Generator is suspended from counting, holding 7. The MSSP module generates an interrupt at the SCL low. The MSSP is now in Idle state awaiting the end of the ninth clock cycle by setting the SSPIF next command. When the buffer is read by the CPU, bit. the BF flag bit is automatically cleared. The user can 8. User sets the RCEN bit of the SSPCON2 register then send an Acknowledge bit at the end of reception and the Master clocks in a byte from the slave. by setting the Acknowledge Sequence Enable, ACKEN 9. After the falling edge of SCL, SSPIF and BF are bit of the SSPCON2 register. set. 24.6.7.1 BF Status Flag 10. Master clears SSPIF and reads the received byte from SSPBUF, clears BF. In receive operation, the BF bit is set when an address 11. Master sets ACK value sent to slave in ACKDT or data byte is loaded into SSPBUF from SSPSR. It is bit of the SSPCON2 register and initiates the cleared when the SSPBUF register is read. ACK by setting the ACKEN bit. 24.6.7.2 SSPOV Status Flag 12. Masters ACK is clocked out to the Slave and SSPIF is set. In receive operation, the SSPOV bit is set when eight 13. User clears SSPIF. bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 14. Steps 8-13 are repeated for each received byte from the slave. 24.6.7.3 WCOL Status Flag 15. Master sends a not ACK or Stop to end communication. If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). DS40001574C-page 272  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-29: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from MasterMaster configured as a receiverSDA = ACKDT = SDA = ACKDT = 10by programming SSPCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten hereom Slavenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1ACKD0WACK Bus masterACK is not sentterminatestransfer9967895876512343124PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared by softwareCleared by softwareCleared by software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Master configured as a receiverRCEN clearedACK from MasterRCEN clearedSDA = ACKDT = automatically0by programming SSPCON2<3> (RCEN = )automatically1 K fr R/ 8 AC A1 7 Write to SSPCON2<0>(SEN = ),1begin Start condition SEN = 0Write to SSPBUF occurs here,start XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 631245SCLS SSPIF Cleared by softwareSDA = , SCL = 01while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN RCEN  2011-2013 Microchip Technology Inc. DS40001574C-page 273

PIC16(L)F1938/9 24.6.8 ACKNOWLEDGE SEQUENCE 24.6.9 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPCON2 register. At the end of a SSPCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDA pin. If the user wishes to gen- the master will assert the SDA line low. When the SDA erate an Acknowledge, then the ACKDT bit should be line is sampled low, the Baud Rate Generator is cleared. If not, the user should set the ACKDT bit before reloaded and counts down to ‘0’. When the Baud Rate starting an Acknowledge sequence. The Baud Rate Generator times out, the SCL pin will be brought high Generator then counts for one rollover period (TBRG) and one TBRG (Baud Rate Generator rollover count) and the SCL pin is deasserted (pulled high). When the later, the SDA pin will be deasserted. When the SDA SCL pin is sampled high (clock arbitration), the Baud pin is sampled high while SCL is high, the P bit of the Rate Generator counts for TBRG. The SCL pin is then SSPSTAT register is set. A TBRG later, the PEN bit is pulled low. Following this, the ACKEN bit is automatically cleared and the SSPIF bit is set (Figure24-31). cleared, the Baud Rate Generator is turned off and the 24.6.9.1 WCOL Status Flag MSSP module then goes into Idle mode (Figure24-30). If the user writes the SSPBUF when a Stop sequence 24.6.8.1 WCOL Status Flag is in progress, then the WCOL bit is set and the If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write does sequence is in progress, then WCOL is set and the not occur). contents of the buffer are unchanged (the write does not occur). FIGURE 24-30: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in SSPIF set at Cleared in software the end of receive software SSPIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 24-31: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS40001574C-page 274  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 24.6.10 SLEEP OPERATION 24.6.13 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C Slave module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 24.6.11 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, 24.6.12 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF, and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure24-32). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit of the SSPSTAT register is set, SSPBUF can be written to. When the user services the or the bus is Idle, with both the S and P bits clear. When bus collision Interrupt Service Routine and if the I2C the bus is busy, enabling the SSP interrupt will gener- bus is free, the user can resume communication by ate the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge condi- monitored for arbitration to see if the signal level is the tion was in progress when the bus collision occurred, the expected output level. This check is performed by condition is aborted, the SDA and SCL lines are deas- hardware with the result placed in the BCLIF bit. serted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus col- The states where arbitration can be lost are: lision Interrupt Service Routine and if the I2C bus is free, • Address Transfer the user can resume communication by asserting a Start • Data Transfer condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 24-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data does not match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF  2011-2013 Microchip Technology Inc. DS40001574C-page 275

PIC16(L)F1938/9 24.6.13.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure24-35). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure24-33). counts down to zero; if the SCL pin is sampled as ‘0’ b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the (Figure24-34). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a fac- pins are monitored. tor during a Start condition is that no two bus masters can assert a Start condition If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: at the exact same time. Therefore, one master will always assert SDA before the • the Start condition is aborted, other. This condition does not cause a bus • the BCLIF flag is set and collision because the two masters must be • the MSSP module is reset to its Idle state allowed to arbitrate the first address fol- (Figure24-33). lowing the Start condition. If the address is The Start condition begins with the SDA and SCL pins the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded and counts down. If the Start or Stop conditions. SCL pin is sampled low while SDA is high, a bus colli- sion occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 24-33: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared by software S SSPIF SSPIF and BCLIF are cleared by software DS40001574C-page 276  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 24-34: BUS COLLISION DURING START CONDITION (SCL=0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared by software S ’0’ ’0’ SSPIF ’0’ ’0’ FIGURE 24-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCLIF ’0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF by software  2011-2013 Microchip Technology Inc. DS40001574C-page 277

PIC16(L)F1938/9 24.6.13.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure24-36). If SDA is sampled high, the BRG is reloaded and begins During a Repeated Start condition, a bus collision counting. If SDA goes from high-to-low before the BRG occurs if: times out, no bus collision occurs because no two a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time. from low level to high level. If SCL goes from high-to-low before the BRG times out b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision indicating that another master is attempting to occurs. In this case, another master is attempting to transmit a data ‘1’. transmit a data ‘1’ during the Repeated Start condition, When the user releases SDA and the pin is allowed to see Figure24-37. float high, the BRG is loaded with SSPADD and counts If, at the end of the BRG time-out, both SCL and SDA down to zero. The SCL pin is then deasserted and are still high, the SDA pin is driven low and the BRG is when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 24-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared by software S ’0’ SSPIF ’0’ FIGURE 24-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared by software RSEN ’0’ S SSPIF DS40001574C-page 278  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 24.6.13.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD and a) After the SDA pin has been deasserted and counts down to zero. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure24-38). If the SCL pin is sampled low before SDA goes high. low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure24-39). FIGURE 24-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ’0’ SSPIF ’0’ FIGURE 24-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ’0’ SSPIF ’0’  2011-2013 Microchip Technology Inc. DS40001574C-page 279

PIC16(L)F1938/9 TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIE2 OSFIE C2IE C1IE EEIE BCLIE — — CCP2IE(1) 92 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 PIR2 OSFIF C2IF C1IF EEIF BCLIF — — CCP2IF(1) 95 SSPADD ADD<7:0> 286 SSPBUF MSSP Receive Buffer/Transmit Register 239* SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 283 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 284 SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 285 SSPMSK MSK<7:0> 286 SSPSTAT SMP CKE D/A P S R/W UA BF 282 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode. * Page provides register information. Note 1: PIC16F1934 only. DS40001574C-page 280  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 24.7 Baud Rate Generator clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being The MSSP module has a Baud Rate Generator avail- operated in. able for clock generation in both I2C and SPI Master Table24-4 demonstrates clock rates based on modes. The Baud Rate Generator (BRG) reload value instruction cycles and the BRG value loaded into is placed in the SSPADD register (Register24-6). SSPADD. When a write occurs to SSPBUF, the Baud Rate Gen- erator will automatically begin counting down. EQUATION 24-1: Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will FOSC remain in its last state. FCLOCK = ------------------------------------------------- SSPxADD+14 An internal signal “Reload” in Figure24-40 triggers the value from SSPADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module FIGURE 24-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPADD<7:0> SSPM<3:0> Reload Reload SCL Control SSPCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 24-4: MSSP CLOCK RATE W/BRG FCLOCK FOSC FCY BRG Value (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz(1) 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application.  2011-2013 Microchip Technology Inc. DS40001574C-page 281

PIC16(L)F1938/9 24.8 Register Definitions: MSSP Control REGISTER 24-1: SSPSTAT: SSP STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I 2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I 2 C™ mode only: 1 = Enable input logic so that thresholds are compliant with SM bus specification 0 = Disable SM bus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I 2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty DS40001574C-page 282  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 24-2: SSPCON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register (must be cleared in software). 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I 2 C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C Master mode: Unused in this mode bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5) 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: When enabled, the SDA and SCL pins must be configured as inputs. 4: SSPADD values of 0, 1 or 2 are not supported for I2C mode. 5: SSPADD value of ‘0’ is not supported. Use SSPM = 0000 instead.  2011-2013 Microchip Technology Inc. DS40001574C-page 283

PIC16(L)F1938/9 REGISTER 24-3: SSPCON2: SSP CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKMSSP Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). DS40001574C-page 284  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 24-4: SSPCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on ninth rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the SSPCON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPBUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the SSPCON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSPCON1 register and SCL is held low. 0 = Data holding is disabled Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF=1, but hardware continues to write the most recent byte to SSPBUF. 2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. 3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.  2011-2013 Microchip Technology Inc. DS40001574C-page 285

PIC16(L)F1938/9 REGISTER 24-5: SSPMSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 24-6: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode – Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode – Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. DS40001574C-page 286  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 25.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer • Half-duplex synchronous master independent of device program execution. The • Half-duplex synchronous slave EUSART, also known as a Serial Communications • Programmable clock polarity in Synchronous Interface (SCI), can be configured as a full-duplex modes asynchronous system or half-duplex synchronous • Sleep operation system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT The EUSART module implements the following terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems: with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate circuits, serial EEPROMs or other microcontrollers. • Wake-up on Break reception These devices typically do not have internal clocks for • 13-bit Break character transmit baud rate generation and require the external clock signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and receiver are shown in Figure25-1 and Figure25-2. FIGURE 25-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREG Register TXIF 8 MSb LSb TX/CK pin (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT SPEN Baud Rate Generator FOSC ÷ n TX9 BRG16 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 X 0 0 0 SPBRGH SPBRGL BRGH X 1 1 0 0 BRG16 X 1 0 1 0  2011-2013 Microchip Technology Inc. DS40001574C-page 287

PIC16(L)F1938/9 FIGURE 25-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN OERR RCIDL RX/DT pin MSb RSR Register LSb Panind BCuoffnetrrol DReactaovery Stop (8) 7 • • • 1 0 START Baud Rate Generator FOSC RX9 ÷ n BRG16 n + 1 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 FIFO SPBRGH SPBRGL BRGH X 1 1 0 0 FERR RX9D RCREG Register BRG16 X 1 0 1 0 8 Data Bus RCIF Interrupt RCIE The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These registers are detailed in Register25-1, Register25-2 and Register25-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output. DS40001574C-page 288  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 25.1 EUSART Asynchronous Mode 25.1.1.2 Transmitting Data The EUSART transmits and receives data using the A transmission is initiated by writing a character to the standard non-return-to-zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the implemented with two levels: a VOH mark state which previous character has been completely flushed from represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXREG is immediately represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains consecutively transmitted data bits of the same value all or part of a previous character, the new character stay at the output level of that bit without returning to a data is held in the TXREG until the Stop bit of the neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending transmission port idles in the mark state. Each character character in the TXREG is then transferred to the TSR transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits or nine data bits and is always terminated by one or and Stop bit sequence commences immediately more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data following the transfer of the data to the TSR from the format is eight bits. Each transmitted bit persists for a TXREG. period of 1/(Baud Rate). An on-chip dedicated 25.1.1.3 Transmit Data Polarity 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system The polarity of the transmit data can be controlled with oscillator. See Table25-5 for examples of baud rate the SCKP bit of the BAUDCON register. The default configurations. state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the SCKP bit to ‘1’ will invert the The EUSART transmits and receives the LSb first. The transmit data resulting in low true idle and data bits. The EUSART’s transmitter and receiver are functionally SCKP bit controls transmit data polarity in independent, but share the same data format and baud Asynchronous mode only. In Synchronous mode, the rate. Parity is not supported by the hardware, but can SCKP bit has a different function. See Section25.5.1.2 be implemented in software and stored as the ninth “Clock Polarity”. data bit. 25.1.1.4 Transmit Interrupt Flag 25.1.1 EUSART ASYNCHRONOUS TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no The EUSART transmitter block diagram is shown in character is being held for transmission in the TXREG. Figure25-1. The heart of the transmitter is the serial In other words, the TXIF bit is only clear when the TSR Transmit Shift Register (TSR), which is not directly is busy with a character and a new character has been accessible by software. The TSR obtains its data from queued for transmission in the TXREG. The TXIF flag bit the transmit buffer, which is the TXREG register. is not cleared immediately upon writing TXREG. TXIF 25.1.1.1 Enabling the Transmitter becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following The EUSART transmitter is enabled for asynchronous the TXREG write will return invalid results. The TXIF bit operations by configuring the following three control is read-only, it cannot be set or cleared by software. bits: The TXIF interrupt can be enabled by setting the TXIE • TXEN = 1 interrupt enable bit of the PIE1 register. However, the • SYNC = 0 TXIF flag bit will be set whenever the TXREG is empty, • SPEN = 1 regardless of the state of TXIE enable bit. All other EUSART control bits are assumed to be in To use interrupts when transmitting data, set the TXIE their default state. bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character Setting the TXEN bit of the TXSTA register enables the of the transmission to the TXREG. transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note1: The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set.  2011-2013 Microchip Technology Inc. DS40001574C-page 289

PIC16(L)F1938/9 25.1.1.5 TSR Status 25.1.1.7 Asynchronous Transmission Set-up: The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRGL register pair and status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired TRMT bit is set when the TSR register is empty and is baud rate (see Section25.4 “EUSART Baud cleared when a character is transferred to the TSR Rate Generator (BRG)”). register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit. No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 con- poll this bit to determine the TSR status. trol bit. A set ninth data bit will indicate that the Note: The TSR register is not mapped in data eight Least Significant data bits are an address memory, so it is not available to the user. when the receiver is set for address detection. 4. Set SCKP bit if inverted transmit is desired. 25.1.1.6 Transmitting 9-Bit Characters 5. Enable the transmission by setting the TXEN The EUSART supports 9-bit character transmissions. control bit. This will cause the TXIF interrupt bit When the TX9 bit of the TXSTA register is set, the to be set. EUSART will shift nine bits out for each character trans- 6. If interrupts are desired, set the TXIE interrupt mitted. The TX9D bit of the TXSTA register is the ninth, enable bit of the PIE1 register. An interrupt will and Most Significant, data bit. When transmitting 9-bit occur immediately provided that the GIE and data, the TX9D data bit must be written before writing PEIE bits of the INTCON register are also set. the eight Least Significant bits into the TXREG. All nine 7. If 9-bit transmission is selected, the ninth bit bits of data will be transferred to the TSR shift register should be loaded into the TX9D data bit. immediately after the TXREG is written. 8. Load 8-bit data into the TXREG register. This A special 9-bit Address mode is available for use with will start the transmission. multiple receivers. See Section25.1.2.7 “Address Detection” for more information on the address mode. FIGURE 25-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) FIGURE 25-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Transmit Buffer Reg. Empty Flag) 1 TCY TRMT bit Word 1 Word 2 (Transmit Shift Transmit Shift Reg. Transmit Shift Reg. Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. DS40001574C-page 290  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 298 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 297 SPBRGL BRG<7:0> 299* SPBRGH BRG<15:8> 299* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 TXREG EUSART Transmit Data Register 289* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 296 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission. * Page provides register information.  2011-2013 Microchip Technology Inc. DS40001574C-page 291

PIC16(L)F1938/9 25.1.2 EUSART ASYNCHRONOUS 25.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit, systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data Figure25-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts the baud rate, whereas the serial Receive Shift character reception, without generating an error, and Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data are immediately transferred to a two character recovery circuit counts a full bit time to the center of the First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. start of a third character before software must start This repeats until all data bits have been sampled and servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always Access to the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this 25.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this character. See Section25.1.2.4 “Receive Framing The EUSART receiver is enabled for asynchronous Error” for more information on framing errors. operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have • CREN = 1 been received, the character in the RSR is transferred • SYNC = 0 to the EUSART receive FIFO and the RCIF interrupt • SPEN = 1 flag bit of the PIR1 register is set. The top character in All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the their default state. RCREG register. Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun of the TXSTA register configures the EUSART for condition is cleared. See Section25.1.2.5 asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more RCSTA register enables the EUSART. The programmer information on overrun errors. must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. 25.1.2.3 Receive Interrupts Note1: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is cleared for the receiver to function. an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: • RCIE interrupt enable bit of the PIE1 register • PEIE peripheral interrupt enable bit of the INTCON register • GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS40001574C-page 292  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 25.1.2.4 Receive Framing Error 25.1.2.7 Address Detection Each character in the receive FIFO buffer has a A special Address Detection mode is available for use corresponding framing error Status bit. A framing error when multiple receivers share the same transmission indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA FERR bit of the RCSTA register. The FERR bit register. represents the status of the top unread character in the Address detection requires 9-bit character reception. receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters before reading the RCREG. with the ninth data bit set will be transferred to the The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt unread character in the receive FIFO. A framing error bit. All other characters will be ignored. (FERR = 1) does not preclude reception of additional Upon receiving an address character, user software characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon Reading the next character from the FIFO buffer will address match, user software must disable address advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next corresponding framing error. Stop bit occurs. When user software detects the end of The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit. affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. 25.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 25.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG.  2011-2013 Microchip Technology Inc. DS40001574C-page 293

PIC16(L)F1938/9 25.1.2.8 Asynchronous Reception Set-up: 25.1.2.9 9-bit Address Detection Mode Set-up 1. Initialize the SPBRGH, SPBRGL register pair This mode would typically be used in RS-485 systems. and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section25.4 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRGL register pair 2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the 3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section25.4 “EUSART The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”). operation. 2. Clear the ANSEL bit for the RX pin (if applicable). 4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit. PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous INTCON register. operation. 5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the 6. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the 7. The RCIF interrupt flag bit will be set when a INTCON register. character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit. receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN the RCIE interrupt enable bit was also set. bit. 8. Read the RCSTA register to get the error flags 7. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit register. was also set. 10. If an overrun occurred, clear the OERR flag by 9. Read the RCSTA register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. FIGURE 25-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg. Word 1 Word 2 RCREG RCREG RCIDL Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS40001574C-page 294  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 25-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 298 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 RCREG EUSART Receive Data Register 292* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 297 SPBRGL BRG<7:0> 299* SPBRGH BRG<15:8> 299* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 296 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception. * Page provides register information.  2011-2013 Microchip Technology Inc. DS40001574C-page 295

PIC16(L)F1938/9 25.2 Clock Accuracy with The first (preferred) method uses the OSCTUNE Asynchronous Operation register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution The factory calibrates the internal oscillator block out- changes to the system clock source. See Section5.2.2 put (INTOSC). However, the INTOSC frequency may “Internal Clock Sources” for more information. drift as VDD or temperature changes, and this directly The other method adjusts the value in the Baud Rate affects the asynchronous baud rate. Two methods may Generator. This can be done automatically with the be used to adjust the baud rate clock, but both require Auto-Baud Detect feature (see Section25.4.1 a reference clock source of some kind. “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. 25.3 Register Definitions: EUSART Control REGISTER 25-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS40001574C-page 296  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 25-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.  2011-2013 Microchip Technology Inc. DS40001574C-page 297

PIC16(L)F1938/9 REGISTER 25-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS40001574C-page 298  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 25.4 EUSART Baud Rate Generator EXAMPLE 25-1: CALCULATING BAUD (BRG) RATE ERROR The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. FOSC Desired Baud Rate = --------------------------------------------------------------------- By default, the BRG operates in 8-bit mode. Setting the 64[SPBRGH:SPBRG]+1 BRG16 bit of the BAUDCON register selects 16-bit Solving for SPBRGH:SPBRGL: mode. FOSC The SPBRGH, SPBRGL register pair determines the --------------------------------------------- Desired Baud Rate period of the free running baud rate timer. In X = ---------------------------------------------–1 64 Asynchronous mode the multiplier of the baud rate 16000000 period is determined by both the BRGH bit of the TXSTA ------------------------ 9600 register and the BRG16 bit of the BAUDCON register. In = ------------------------–1 64 Synchronous mode, the BRGH bit is ignored. = 25.042 = 25 Table25-3 contains the formulas for determining the baud rate. Example25-1 provides a sample calculation 16000000 Calculated Baud Rate = --------------------------- for determining the baud rate and baud rate error. 6425+1 Typical baud rates and error values for various = 9615 Asynchronous modes have been computed for your convenience and are shown in Table25-3. It may be Calc. Baud Rate–Desired Baud Rate Error = -------------------------------------------------------------------------------------------- advantageous to use the high baud rate (BRGH = 1), Desired Baud Rate or the 16-bit BRG (BRG16 = 1) to reduce the baud rate 9615–9600 error. The 16-bit BRG mode is used to achieve slow = ---------------------------------- = 0.16% 9600 baud rates for fast oscillator frequencies. Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock.  2011-2013 Microchip Technology Inc. DS40001574C-page 299

PIC16(L)F1938/9 TABLE 25-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair TABLE 25-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 298 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 297 SPBRGL BRG<7:0> 299* SPBRGH BRG<15:8> 299* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 296 Legend: — = unimplemented location read as ‘0’. Shaded cells are not used for the Baud Rate Generator. * Page provides register information. DS40001574C-page 300  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5  2011-2013 Microchip Technology Inc. DS40001574C-page 301

PIC16(L)F1938/9 TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — DS40001574C-page 302  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —  2011-2013 Microchip Technology Inc. DS40001574C-page 303

PIC16(L)F1938/9 25.4.1 AUTO-BAUD DETECT and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. Note1: If the WUE bit is set with the ABDEN bit, In the Auto-Baud Detect (ABD) mode, the clock to the auto-baud detection will occur on the byte BRG is reversed. Rather than the BRG clocking the following the Break character (see incoming RX signal, the RX signal is timing the BRG. Section25.4.3 “Auto-Wake-up on The Baud Rate Generator is used to time the period of Break”). a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the that it has five rising edges including the Stop bit edge. incoming character baud rate is within the range of the selected BRG clock source. Setting the ABDEN bit of the BAUDCON register starts Some combinations of oscillator frequency the auto-baud calibration sequence (Figure25-6). and EUSART baud rates are not possible. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of 3: During the auto-baud process, the the receive line, after the Start bit, the SPBRG begins auto-baud counter starts counting at 1. counting up using the BRG counter clock as shown in Upon completion of the auto-baud Table25-6. The fifth rising edge will occur on the RX pin sequence, to achieve maximum accuracy, at the end of the eighth bit period. At that time, an subtract 1 from the SPBRGH:SPBRGL accumulated value totaling the proper BRG period is register pair. left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag TABLE 25-6: BRG COUNTER CLOCK RATES is set. The value in the RCREG needs to be read to BRG Base BRG ABD clear the RCIF interrupt. RCREG content should be BRG16 BRGH Clock Clock discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the 0 0 FOSC/64 FOSC/512 SPBRGL register did not overflow by checking for 00h 0 1 FOSC/16 FOSC/128 in the SPBRGH register. 1 0 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table25-6. During ABD, 1 1 FOSC/4 FOSC/32 both the SPBRGH and SPBRGL registers are used as Note: During the ABD sequence, SPBRGL and a 16-bit counter, independent of the BRG16 bit setting. SPBRGH registers are both used as a 16-bit While calibrating the baud rate period, the SPBRGH counter, independent of BRG16 setting. FIGURE 25-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL XXh 1Ch SPBRGH XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. DS40001574C-page 304  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 25.4.2 AUTO-BAUD OVERFLOW 25.4.3.1 Special Considerations During the course of automatic baud detection, the Break Character ABDOVF bit of the BAUDCON register will be set if the To avoid character errors or character fragments during baud rate counter overflows before the fifth rising edge a wake-up event, the wake-up character must be all is detected on the RX pin. The ABDOVF bit indicates zeros. that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register When the wake-up is enabled the function works pair. After the ABDOVF has been set, the counter con- independent of the low time on the data stream. If the tinues to count until the fifth rising edge is detected on WUE bit is set and a valid non-zero character is the RX pin. Upon detecting the fifth RX edge, the hard- received, the low time from the Start bit to the first rising ware will set the RCIF interrupt flag and clear the edge will be interpreted as the wake-up event. The ABDEN bit of the BAUDCON register. The RCIF flag remaining bits in the character will be received as a can be subsequently cleared by reading the RCREG fragmented character and subsequent characters can register. The ABDOVF flag of the BAUDCON register result in framing or overrun errors. can be cleared by software directly. Therefore, the initial character in the transmission must To terminate the auto-baud process before the RCIF be all ‘0’s. This must be 10 or more bit times, 13-bit flag is set, clear the ABDEN bit then clear the ABDOVF times recommended for LIN bus, or any number of bit bit of the BAUDCON register. The ABDOVF bit will times for standard RS-232 devices. remain set if the ABDEN bit is not cleared first. Oscillator Start-up Time Oscillator start-up time must be considered, especially 25.4.3 AUTO-WAKE-UP ON BREAK in applications using oscillators with longer start-up During Sleep mode, all clocks to the EUSART are intervals (i.e., LP, XT or HS/PLL mode). The Sync suspended. Because of this, the Baud Rate Generator Break (or wake-up signal) character must be of is inactive and a proper character reception cannot be sufficient length, and be followed by a sufficient performed. The Auto-Wake-up feature allows the interval, to allow enough time for the selected oscillator controller to wake-up due to activity on the RX/DT line. to start and provide proper initialization of the EUSART. This feature is available only in Asynchronous mode. WUE Bit The Auto-Wake-up feature is enabled by setting the The wake-up event causes a receive interrupt by WUE bit of the BAUDCON register. Once set, the normal setting the RCIF bit. The WUE bit is cleared in receive sequence on RX/DT is disabled, and the hardware by a rising edge on RX/DT. The interrupt EUSART remains in an Idle state, monitoring for a condition is then cleared in software by reading the wake-up event independent of the CPU mode. A RCREG register and discarding its contents. wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break To ensure that no actual data is lost, check the RCIDL or a wake-up signal character for the LIN protocol.) bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not The EUSART module generates an RCIF interrupt occurring, the WUE bit may then be set just prior to coincident with the wake-up event. The interrupt is entering the Sleep mode. generated synchronously to the Q clocks in normal CPU operating modes (Figure25-7), and asynchronously if the device is in Sleep mode (Figure25-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.  2011-2013 Microchip Technology Inc. DS40001574C-page 305

PIC16(L)F1938/9 FIGURE 25-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 25-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RX/DT Line Note 1 RCIF Cleared due to User Read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. DS40001574C-page 306  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 25.4.4 BREAK CHARACTER SEQUENCE 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is The EUSART module has the capability of sending the then transmitted. special Break character sequences that are required by the LIN bus standard. A Break character consists of a When the TXREG becomes empty, as indicated by the Start bit, followed by 12 ‘0’ bits and a Stop bit. TXIF, the next data byte can be written to TXREG. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character trans- 25.4.5 RECEIVING A BREAK CHARACTER mission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all The Enhanced EUSART module can receive a Break ‘0’s will be transmitted. character in two ways. The SENDB bit is automatically reset by hardware after The first method to detect a Break character uses the the corresponding Stop bit is sent. This allows the user FERR bit of the RCSTA register and the Received data to preload the transmit FIFO with the next transmit byte as indicated by RCREG. The Baud Rate Generator is following the Break character (typically, the Sync assumed to have been initialized to the expected baud character in the LIN specification). rate. The TRMT bit of the TXSTA register indicates when the A Break character has been received when; transmit operation is active or Idle, just as it does during • RCIF bit is set normal transmission. See Figure25-9 for the timing of the Break character sequence. • FERR bit is set • RCREG = 00h 25.4.4.1 Break and Sync Transmit Sequence The second method uses the Auto-Wake-up feature The following sequence will start a message frame described in Section25.4.3 “Auto-Wake-up on header made up of a Break, followed by an auto-baud Break”. By enabling this feature, the EUSART will Sync byte. This sequence is typical of a LIN bus sample the next two transitions on RX/DT, cause an master. RCIF interrupt, and receive the next data byte followed 1. Configure the EUSART for the desired mode. by another interrupt. 2. Set the TXEN and SENDB bits to enable the Note that following a Break character, the user will Break sequence. typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of 3. Load the TXREG with a dummy character to the BAUDCON register before placing the EUSART in initiate transmission (the value is ignored). Sleep mode. 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. FIGURE 25-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit)  2011-2013 Microchip Technology Inc. DS40001574C-page 307

PIC16(L)F1938/9 25.5 EUSART Synchronous Mode Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising Synchronous serial communications are typically used edge of each clock. in systems with a single master and one or more slaves. The master device contains the necessary cir- 25.5.1.3 Synchronous Master Transmission cuitry for baud rate generation and supplies the clock Data is transferred out of the device on the RX/DT pin. for all devices in the system. Slave devices can take The RX/DT and TX/CK pin output drivers are automat- advantage of the master clock by eliminating the inter- ically enabled when the EUSART is configured for nal clock generation circuitry. synchronous master transmit operation. There are two signal lines in Synchronous mode: a A transmission is initiated by writing a character to the bidirectional data line and a clock line. Slaves use the TXREG register. If the TSR still contains all or part of a external clock supplied by the master to shift the serial previous character the new character data is held in the data into and out of their respective receive and trans- TXREG until the last bit of the previous character has mit shift registers. Since the data line is bidirectional, been transmitted. If this is the first character, or the synchronous operation is half-duplex only. Half-duplex previous character has been completely flushed from refers to the fact that master and slave devices can the TSR, the data in the TXREG is immediately trans- receive and transmit data but not both simultaneously. ferred to the TSR. The transmission of the character The EUSART can operate as either a master or slave commences immediately following the transfer of the device. data to the TSR from the TXREG. Start and Stop bits are not used in synchronous trans- Each data bit changes on the leading edge of the missions. master clock and remains valid until the subsequent leading clock edge. 25.5.1 SYNCHRONOUS MASTER MODE The following bits are used to configure the EUSART Note: The TSR register is not mapped in data for Synchronous Master operation: memory, so it is not available to the user. • SYNC = 1 25.5.1.4 Synchronous Master Transmission • CSRC = 1 Set-up: • SREN = 0 (for transmit); SREN = 1 (for receive) 1. Initialize the SPBRGH, SPBRGL register pair • CREN = 0 (for transmit); CREN = 1 (for receive) and the BRGH and BRG16 bits to achieve the • SPEN = 1 desired baud rate (see Section25.4 “EUSART Baud Rate Generator (BRG)”). Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC 2. Enable the synchronous master serial port by bit of the TXSTA register configures the device as a setting bits SYNC, SPEN and CSRC. master. Clearing the SREN and CREN bits of the RCSTA 3. Disable Receive mode by clearing bits SREN register ensures that the device is in the Transmit mode, and CREN. otherwise the device will be configured to receive. Setting 4. Enable Transmit mode by setting the TXEN bit. the SPEN bit of the RCSTA register enables the 5. If 9-bit transmission is desired, set the TX9 bit. EUSART. 6. If interrupts are desired, set the TXIE bit of the 25.5.1.1 Master Clock PIE1 register and the GIE and PEIE bits of the INTCON register. Synchronous data transfers use a separate clock line, 7. If 9-bit transmission is selected, the ninth bit which is synchronous with the data. A device config- should be loaded in the TX9D bit. ured as a master transmits the clock on the TX/CK line. 8. Start transmission by loading data to the TXREG The TX/CK pin output driver is automatically enabled register. when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trail- ing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are gener- ated as there are data bits. 25.5.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. DS40001574C-page 308  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 25-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 25-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 25-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 298 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 297 SPBRGL BRG<7:0> 299* SPBRGH BRG<15:8> 299* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 TXREG EUSART Transmit Data Register 289* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 296 Legend: — = unimplemented location read as ‘0’. Shaded cells are not used for synchronous master transmission. * Page provides register information.  2011-2013 Microchip Technology Inc. DS40001574C-page 309

PIC16(L)F1938/9 25.5.1.5 Synchronous Master Reception set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the Data is received at the RX/DT pin. The RX/DT pin SPEN bit which resets the EUSART. output driver is automatically disabled when the EUSART is configured for synchronous master receive 25.5.1.8 Receiving 9-bit Characters operation. The EUSART supports 9-bit character reception. When In Synchronous mode, reception is enabled by setting the RX9 bit of the RCSTA register is set the EUSART either the Single Receive Enable bit (SREN of the will shift nine bits into the RSR for each character RCSTA register) or the Continuous Receive Enable bit received. The RX9D bit of the RCSTA register is the (CREN of the RCSTA register). ninth, and Most Significant, data bit of the top unread When SREN is set and CREN is clear, only as many character in the receive FIFO. When reading 9-bit data clock cycles are generated as there are data bits in a from the receive FIFO buffer, the RX9D data bit must single character. The SREN bit is automatically cleared be read before reading the eight Least Significant bits at the completion of one character. When CREN is set, from the RCREG. clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character 25.5.1.9 Synchronous Master Reception the CK clock stops immediately and the partial charac- Set-up: ter is discarded. If SREN and CREN are both set, then 1. Initialize the SPBRGH, SPBRGL register pair for SREN is cleared at the completion of the first character the appropriate baud rate. Set or clear the and CREN takes precedence. BRGH and BRG16 bits, as required, to achieve To initiate reception, set either SREN or CREN. Data is the desired baud rate. sampled at the RX/DT pin on the trailing edge of the 2. Clear the ANSEL bit for the RX pin (if applicable). TX/CK clock pin and is shifted into the Receive Shift 3. Enable the synchronous master serial port by Register (RSR). When a complete character is setting bits SYNC, SPEN and CSRC. received into the RSR, the RCIF bit is set and the char- 4. Ensure bits CREN and SREN are clear. acter is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top 5. If interrupts are desired, set the RCIE bit of the character in the receive FIFO are available in RCREG. PIE1 register and the GIE and PEIE bits of the The RCIF bit remains set as long as there are unread INTCON register. characters in the receive FIFO. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for 25.5.1.6 Slave Clock continuous reception, set the CREN bit. Synchronous data transfers use a separate clock line, 8. Interrupt flag bit RCIF will be set when reception which is synchronous with the data. A device configured of a character is complete. An interrupt will be as a slave receives the clock on the TX/CK line. The generated if the enable bit RCIE was set. TX/CK pin output driver is automatically disabled when 9. Read the RCSTA register to get the ninth bit (if the device is configured for synchronous slave transmit enabled) and determine if any error occurred or receive operation. Serial data bits change on the during reception. leading edge to ensure they are valid at the trailing edge 10. Read the 8-bit received data by reading the of each clock. One data bit is transferred for each clock RCREG register. cycle. Only as many clock cycles should be received as 11. If an overrun error occurs, clear the error by there are data bits. either clearing the CREN bit of the RCSTA 25.5.1.7 Receive Overrun Error register or by clearing the SPEN bit which resets the EUSART. The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is DS40001574C-page 310  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 25-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 298 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 RCREG EUSART Receive Data Register 292* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 297 SPBRGL BRG<7:0> 299* SPBRGH BRG<15:8> 299* TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 296 Legend: — = unimplemented location read as ‘0’. Shaded cells are not used for synchronous master reception. * Page provides register information.  2011-2013 Microchip Technology Inc. DS40001574C-page 311

PIC16(L)F1938/9 25.5.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the EUSART for Synchronous slave operation: 1. The first character will immediately transfer to the TSR register and transmit. • SYNC = 1 2. The second word will remain in TXREG register. • CSRC = 0 3. The TXIF bit will not be set. • SREN = 0 (for transmit); SREN = 1 (for receive) 4. After the first character has been shifted out of • CREN = 0 (for transmit); CREN = 1 (for receive) TSR, the TXREG register will transfer the second • SPEN = 1 character to the TSR and the TXIF bit will now be Setting the SYNC bit of the TXSTA register configures the set. device for synchronous operation. Clearing the CSRC bit 5. If the PEIE and TXIE bits are set, the interrupt of the TXSTA register configures the device as a slave. will wake the device from Sleep and execute the Clearing the SREN and CREN bits of the RCSTA register next instruction. If the GIE bit is also set, the ensures that the device is in the Transmit mode, program will call the Interrupt Service Routine. otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the 25.5.2.2 Synchronous Slave Transmission EUSART. Set-up: 25.5.2.1 EUSART Synchronous Slave 1. Set the SYNC and SPEN bits and clear the CSRC bit. Transmit 2. Clear the ANSEL bit for the CK pin (if applicable). The operation of the Synchronous Master and Slave 3. Clear the CREN and SREN bits. modes are identical (see Section25.5.1.3 “Synchronous Master Transmission”), except in the 4. If interrupts are desired, set the TXIE bit of the case of the Sleep mode. PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit transmission is desired, set the TX9 bit. 6. Enable transmission by setting the TXEN bit. 7. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 8. Start transmission by writing the Least Significant eight bits to the TXREG register. TABLE 25-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 298 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 297 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 TXREG EUSART Transmit Data Register 289* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 296 Legend: — = unimplemented location read as ‘0’. Shaded cells are not used for synchronous slave transmission. * Page provides register information. DS40001574C-page 312  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 25.5.2.3 EUSART Synchronous Slave 25.5.2.4 Synchronous Slave Reception Reception Set-up: The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the modes is identical (Section25.5.1.5 “Synchronous CSRC bit. Master Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins • Sleep (if applicable). • CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RCIE bit of the never Idle PIE1 register and the GIE and PEIE bits of the INTCON register. • SREN bit, which is a “don’t care” in Slave mode 4. If 9-bit reception is desired, set the RX9 bit. A character may be received while in Sleep mode by 5. Set the CREN bit to enable reception. setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data 6. The RCIF bit will be set when reception is to the RCREG register. If the RCIE enable bit is set, the complete. An interrupt will be generated if the interrupt generated will wake the device from Sleep RCIE bit was set. and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTA register. 8. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 25-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 298 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 91 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 94 RCREG EUSART Receive Data Register 292* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 297 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 296 Legend: — = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception. * Page provides register information.  2011-2013 Microchip Technology Inc. DS40001574C-page 313

PIC16(L)F1938/9 25.6 EUSART Operation During Sleep 25.6.2 SYNCHRONOUS TRANSMIT DURING SLEEP The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the To transmit during Sleep, all the following conditions system clock and therefore cannot generate the neces- must be met before entering Sleep mode: sary signals to run the Transmit or Receive Shift regis- • RCSTA and TXSTA Control registers must be ters during Sleep. configured for Synchronous Slave Transmission Synchronous Slave mode uses an externally generated (see Section25.5.2.2 “Synchronous Slave clock to run the Transmit and Receive Shift registers. Transmission Set-up:”). • The TXIF interrupt flag must be cleared by writing 25.6.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the SLEEP TSR and transmit buffer. To receive during Sleep, all the following conditions • If interrupts are desired, set the TXIE bit of the must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON reg- ister. • RCSTA and TXSTA Control registers must be • Interrupt enable bits TXIE of the PIE1 register and configured for Synchronous Slave Reception (see PEIE of the INTCON register must set. Section25.5.2.4 “Synchronous Slave Reception Set-up:”). Upon entering Sleep mode, the device will be ready to • If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the PIE1 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been INTCON register. completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and • The RCIF interrupt flag must be cleared by read- the TXIF flag will be set. Thereby, waking the processor ing RCREG to unload any pending characters in from Sleep. At this point, the TXREG is available to the receive buffer. accept another character for transmission, which will Upon entering Sleep mode, the device will be ready to clear the TXIF flag. accept data and clocks on the RX/DT and TX/CK pins, Upon waking from Sleep, the instruction following the respectively. When the data word has been completely SLEEP instruction will be executed. If the Global clocked in by the external device, the RCIF interrupt Interrupt Enable (GIE) bit is also set then the Interrupt flag bit of the PIR1 register will be set. Thereby, waking Service Routine at address 0004h will be called. the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. DS40001574C-page 314  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 26.0 CAPACITIVE SENSING (CPS) MODULE The Capacitive Sensing (CPS) module allows for an interaction with an end user without a mechanical interface. In a typical application, the CPS module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the CPS module. The CPS module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: • Analog MUX for monitoring multiple inputs • Capacitive sensing oscillator • Multiple Current Ranges • Multiple Voltage Reference modes • Multiple timer resources • Software control • Operation during Sleep FIGURE 26-1: CAPACITIVE SENSING BLOCK DIAGRAM Timer0 Module CPSCH<3:0> Set CPSON(2) T0XCS TMR0CS TMR0IF CPS0 FOSC/4 0 Overflow T0CKI 0 TMR0 CPS1 1 CPS2 1 CPS3 CPSRNG<1:0> CPS4 CPSON CPS5 CPS6 Capacitive CPS7 Sensing Timer1 Module Oscillator CPS8(1) TMR1CS<1:0> CPSOSC CPS9(1) FOSC CPS10(1) CPSCLK FOSC/4 CPS11(1) 0 Int. CPS12(1) Ref- Ref. T1TO1CSCKI/ EN TMR1H:TMR1L CPS13(1) 1 ODuAtCpu t 0 T1GSEL<1:0> CPS14(1) Ref+ CPS15(1) 1 FVR T1G Timer1 Gate sync_C1OUT Control Logic CPSOUT sync_C2OUT CPSRM Note 1: Reference CPSCON1 register (Register26-2) for channels implemented on each device. 2: If CPSON=0, disabling capacitive sensing, no channel is selected.  2011-2013 Microchip Technology Inc. DS40001574C-page 315

PIC16(L)F1938/9 FIGURE 26-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM Oscillator Module VDD (1) (2) + - S Q CPSCLK CPSx Analog Pin (1) (2) R - + Internal References 0 0 Ref- Ref+ 1 DAC 1 FVR Output CPSRM Note 1: Module Enable, Voltage Reference mode and Current Range selections are not shown. 2: Comparators remain active in Noise Detection mode. DS40001574C-page 316  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 26.1 Analog MUX 26.3 Voltage Reference Modes The CPS module can monitor up to 16 inputs. The The capacitive sensing oscillator uses voltage refer- capacitive sensing inputs are defined as CPS<15:0>. ences to provide two voltage thresholds for oscillation. To determine if a frequency change has occurred the The upper voltage threshold is referred to as Ref+ and user must: the lower voltage threshold is referred to as Ref-. • Select the appropriate CPS pin by setting the The user can elect to use fixed voltage references, CPSCH<3:0> bits of the CPSCON1 register. which are internal to the capacitive sensing oscillator, • Set the corresponding ANSEL bit. or variable voltage references, which are supplied by the Fixed Voltage Reference (FVR) module and the • Set the corresponding TRIS bit. Digital-to-Analog Converter (DAC) module. • Run the software algorithm. When the fixed voltage references are used, the VSS Selection of the CPSx pin while the module is enabled voltage determines the lower threshold level (Ref-) and will cause the capacitive sensing oscillator to be on the the VDD voltage determines the upper threshold level CPSx pin. Failure to set the corresponding ANSEL and (Ref+). TRIS bits can cause the capacitive sensing oscillator to stop, leading to false frequency readings. When the variable voltage references are used, the DAC voltage determines the lower threshold level 26.2 Capacitive Sensing Oscillator (Ref-) and the FVR voltage determines the upper threshold level (Ref+). An advantage of using these ref- The capacitive sensing oscillator consists of a constant erence sources is that oscillation frequency remains current source and a constant current sink, to produce constant with changes in VDD. a triangle waveform. The CPSOUT bit of the Different oscillation frequencies can be obtained CPSCON0 register shows the status of the capacitive through the use of these variable voltage references. sensing oscillator, whether it is a sinking or sourcing The more the upper voltage reference level is lowered current. The oscillator is designed to drive a capacitive and the more the lower voltage reference level is load (single PCB pad) and at the same time, be a clock raised, the higher the capacitive sensing oscillator fre- source to either Timer0 or Timer1. The oscillator has quency becomes. several different current settings as defined by CPSRNG<1:0> of the CPSCON0 register. The different Selection between the voltage references is controlled by the CPSRM bit of the CPSCON0 register. Setting current settings for the oscillator serve two purposes: this bit selects the variable voltage references and • Maximize the number of counts in a timer for a clearing this bit selects the fixed voltage references. fixed time base. Please see Section14.0 “Fixed Voltage Reference • Maximize the count differential in the timer during (FVR)” and Section17.0 “Digital-to-Analog Con- a change in frequency. verter (DAC) Module” for more information on config- uring the variable voltage levels.  2011-2013 Microchip Technology Inc. DS40001574C-page 317

PIC16(L)F1938/9 26.4 Current Ranges The Noise Detection mode is unique in that it disables the constant current source associated with the The capacitive sensing oscillator can operate within selected input pin, but leaves the rest of the oscillator several different current ranges, depending on the volt- circuitry and pin structure active. This eliminates the age reference mode and current range selections. oscillation frequency on the analog pin and greatly Within each of the two voltage reference modes there reduces the current consumed by the oscillator mod- are four current ranges. ule. Selection between the voltage reference modes is con- When noise is introduced onto the pin, the oscillator is trolled by the CPSRM bit of the CPSCON0 register. driven at the frequency determined by the noise. This Clearing this bit selects the fixed voltage references produces a detectable signal at the comparator stage, provided by the capacitive sensing oscillator module. indicating the presence of activity on the pin. Setting this bit selects the variable voltage references Figure26-2 shows a more detailed drawing of the supplied by the Fixed Voltage reference (FVR) module constant current sources and comparators associated and the Digital-to-Analog Converter (DAC) module. with the oscillator and input pin. See Section26.3 “Voltage Reference Modes” for more information on configuring the voltage refer- ences. Selecting the current range within each voltage reference mode is controlled by configuring the CPSRNG<1:0> bits in the CPSCON0 register. See Table26-1 for proper current mode selection. TABLE 26-1: CURRENT RANGE SELECTION Voltage Reference CPSRM CPSRNG<1:0> Current Range(1) Mode 00 Off 01 Low 0 Fixed 10 Medium 11 High 00 Noise Detection 01 Low 1 Variable 10 Medium 11 High Note 1: See Power-Down Currents (IPD) in Section30.0 “Electrical Specifications” for more information. DS40001574C-page 318  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 26.5 Timer Resources 26.7 Software Control To measure the change in frequency of the capacitive The software portion of the CPS module is required to sensing oscillator, a fixed time base is required. For the determine the change in frequency of the capacitive period of the fixed time base, the capacitive sensing sensing oscillator. This is accomplished by the oscillator is used to clock either Timer0 or Timer1. The following: frequency of the capacitive sensing oscillator is equal • Setting a fixed time base to acquire counts on to the number of counts in the timer divided by the Timer0 or Timer1. period of the fixed time base. • Establishing the nominal frequency for the capacitive sensing oscillator. 26.6 Fixed Time Base • Establishing the reduced frequency for the To measure the frequency of the capacitive sensing capacitive sensing oscillator due to an additional oscillator, a fixed time base is required. Any timer capacitive load. resource or software loop can be used to establish the • Set the frequency threshold. fixed time base. It is up to the end user to determine the method in which the fixed time base is generated. 26.7.1 NOMINAL FREQUENCY (NO CAPACITIVE LOAD) Note: The fixed time base can not be generated by the timer resource that the capacitive To determine the nominal frequency of the capacitive sensing oscillator is clocking. sensing oscillator: • Remove any extra capacitive load on the selected 26.6.1 TIMER0 CPSx pin. To select Timer0 as the timer resource for the CPS • At the start of the fixed time base, clear the timer module: resource. • Set the T0XCS bit of the CPSCON0 register. • At the end of the fixed time base save the value in the timer resource. • Clear the TMR0CS bit of the OPTION_REG register. The value of the timer resource is the number of oscillations of the capacitive sensing oscillator for the When Timer0 is chosen as the timer resource, the given time base. The frequency of the capacitive capacitive sensing oscillator will be the clock source for sensing oscillator is equal to the number of counts on Timer0. Refer to Section20.0 “Timer0 Module” for in the timer divided by the period of the fixed time base. additional information. 26.7.2 REDUCED FREQUENCY 26.6.2 TIMER1 (ADDITIONAL CAPACITIVE LOAD) To select Timer1 as the timer resource for the CPS module, set the TMR1CS<1:0> of the T1CON register The extra capacitive load will cause the frequency of the to ‘11’. When Timer1 is chosen as the timer resource, capacitive sensing oscillator to decrease. To determine the capacitive sensing oscillator will be the clock the reduced frequency of the capacitive sensing source for Timer1. Because the Timer1 module has a oscillator: gate control, developing a time base for the frequency • Add a typical capacitive load on the selected measurement can be simplified by using the Timer0 CPSx pin. overflow flag. • Use the same fixed time base as the nominal It is recommend that the Timer0 overflow flag, in con- frequency measurement. junction with the Toggle mode of the Timer1 gate, be • At the start of the fixed time base, clear the timer used to develop the fixed time base required by the resource. software portion of the CPS module. Refer to Section • At the end of the fixed time base save the value in “” for additional information. the timer resource. The value of the timer resource is the number of oscil- TABLE 26-2: TIMER1 ENABLE FUNCTION lations of the capacitive sensing oscillator with an addi- TMR1ON TMR1GE Timer1 Operation tional capacitive load. The frequency of the capacitive sensing oscillator is equal to the number of counts on 0 0 Off in the timer divided by the period of the fixed time base. 0 1 Off This frequency should be less than the value obtained 1 0 On during the nominal frequency measurement. 1 1 Count Enabled by input  2011-2013 Microchip Technology Inc. DS40001574C-page 319

PIC16(L)F1938/9 26.7.3 FREQUENCY THRESHOLD The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, “Software Handling for Capacitive Sensing” (DS01103) for more detailed information on the software required for CPS module. Note: For more information on general capacitive sensing refer to Application Notes: • AN1101, “Introduction to Capacitive Sensing” (DS01101) • AN1102, “Layout and Physical Design Guidelines for Capacitive Sensing” (DS01102) 26.8 Operation during Sleep The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts. Note: Timer0 does not operate when in Sleep, and therefore cannot be used for capacitive sense measurements in Sleep. DS40001574C-page 320  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 26.9 Register Definitions: CPS Control REGISTER 26-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPSON: CPS Module Enable bit 1 = CPS module is enabled 0 = CPS module is disabled bit 6 CPSRM: Capacitive Sensing Reference Mode bit 1 = Capacitive Sensing module is in Variable Voltage Reference mode. 0 = Capacitive Sensing module is in Fixed Variable Voltage Reference mode. bit 5-4 Unimplemented: Read as ‘0’ bit 3-2 CPSRNG<1:0>: Capacitive Sensing Current Range If CPSRM = 0 (Fixed Voltage Reference mode): 00 = Oscillator is off 01 = Oscillator is in Low-Current Range 10 = Oscillator is in Medium-Current Range 11 = Oscillator is in High-Current Range If CPSRM = 1 (Variable Voltage Reference mode): 00 = Oscillator is on. Noise Detection mode. 01 = Oscillator is in Low-Current Range. 10 = Oscillator is in Medium-Current Range. 11 = Oscillator is in High-Current Range. bit 1 CPSOUT: Capacitive Sensing Oscillator Status bit 1 = Oscillator is sourcing current (Current flowing out of the pin) 0 = Oscillator is sinking current (Current flowing into the pin) bit 0 T0XCS: Timer0 External Clock Source Select bit If TMR0CS = 1: The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0: 1 = Timer0 clock source is the capacitive sensing oscillator, CPSCLK 0 = Timer0 clock source is the T0CKI pin If TMR0CS = 0: Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4  2011-2013 Microchip Technology Inc. DS40001574C-page 321

PIC16(L)F1938/9 REGISTER 26-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0/0(2) R/W-0/0 R/W-0/0 R/W-0/0 — — — — CPSCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CPSCH<3:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected. If CPSON = 1: 0000 = channel 0, (CPS0) 0001 = channel 1, (CPS1) 0010 = channel 2, (CPS2) 0011 = channel 3, (CPS3) 0100 = channel 4, (CPS4) 0101 = channel 5, (CPS5) 0110 = channel 6, (CPS6) 0111 = channel 7, (CPS7) 1000 = channel 8, (CPS8(1)) 1001 = channel 9, (CPS9(1)) 1010 = channel 10, (CPS10(1)) 1011 = channel 11, (CPS11(1)) 1100 = channel 12, (CPS12(1)) 1101 = channel 13, (CPS13(1)) 1110 = channel 14, (CPS14(1)) 1111 = channel 15, (CPS15(1)) Note 1: These channels are not implemented on the PIC16(L)F1938. 2: This bit is not implemented on PIC16(L)F1938, read as ‘0’ DS40001574C-page 322  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 126 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 131 ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 138 CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 321 CPSCON1 — — — — CPSCH<3:0> 322 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 187 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 197 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 125 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 130 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 137 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the CPS module. Note 1: PIC16(L)F1939 only.  2011-2013 Microchip Technology Inc. DS40001574C-page 323

PIC16(L)F1938/9 NOTES: DS40001574C-page 324  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 27.0 LIQUID CRYSTAL DISPLAY (LCD) DRIVER MODULE Note: COM3 and SEG15 share the same physical pin on the PIC16(L)F1938, therefore The Liquid Crystal Display (LCD) Driver module SEG15 is not available when using 1/4 generates the timing control to drive a static or multiplex displays. multiplexed LCD panel. In the PIC16(L)F193X device, the module drives the panels of up to four commons and up to 24 segments. The LCD module also provides control of the LCD pixel data. The LCD Driver module supports: • Direct driving of LCD panel • Three LCD clock sources with selectable prescaler • Up to four common pins: - Static (1 common) - 1/2 multiplex (2 commons) - 1/3 multiplex (3 commons) - 1/4 multiplex (4 commons) • Segment pins up to: - 16 (PIC16(L)F1938) - 24 (PIC16(L)F1939) • Static, 1/2 or 1/3 LCD Bias FIGURE 27-1: LCD DRIVER MODULE BLOCK DIAGRAM LCDDATAx SEG<23:0>(1, 3) Data Bus MUX To I/O Pads(1) Registers Timing Control LCDCON COM<3:0>(3) LCDPS To I/O Pads(1) LCDSEn FOSC/256 Clock Source T1OSC Select and Prescaler LFINTOSC Note 1: These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module. 2: SEG<23:0> on PIC16(L)F1939, SEG<15:0> on PIC16(L)F1938. 3: COM3 and SEG15 share the same physical pin on the PIC16(L)F1938, therefore SEG15 is not available when using 1/4 multiplex displays.  2011-2013 Microchip Technology Inc. DS40001574C-page 325

PIC16(L)F1938/9 27.1 LCD Registers TABLE 27-1: LCD SEGMENT AND DATA REGISTERS The module contains the following registers: # of LCD Registers • LCD Control register (LCDCON) Device • LCD Phase register (LCDPS) Segment Data Enable • LCD Reference Ladder register (LCDRL) PIC16(L)F1938 2 8 • LCD Contrast Control register (LCDCST) • LCD Reference Voltage Control register PIC16(L)F1939 3 12 (LCDREF) The LCDCON register (Register27-1) controls the • Up to three LCD Segment Enable registers operation of the LCD Driver module. The LCDPS reg- (LCDSEn) ister (Register27-2) configures the LCD clock source • Up to 12 LCD data registers (LCDDATAn) prescaler and the type of waveform; Type-A or Type-B. The LCDSEn registers (Register27-5) configure the functions of the port pins. The following LCDSEn registers are available: • LCDSE0 SE<7:0> • LCDSE1 SE<15:8> • LCDSE2 SE<23:16>(1) Note1: PIC16(L)F1939 only. Once the module is initialized for the LCD panel, the individual bits of the LCDDATAn registers are cleared/set to represent a clear/dark pixel, respectively: • LCDDATA0 SEG<7:0>COM0 • LCDDATA1 SEG<15:8>COM0 • LCDDATA2 SEG<23:16>COM0(1) • LCDDATA3 SEG<7:0>COM1 • LCDDATA4 SEG<15:8>COM1 • LCDDATA5 SEG<23:16>COM1(1) • LCDDATA6 SEG<7:0>COM2 • LCDDATA7 SEG<15:8>COM2 • LCDDATA8 SEG<23:16>COM2(1) • LCDDATA9 SEG<7:0>COM3 • LCDDATA10 SEG<15:8>COM3 • LCDDATA11 SEG<23:16>COM3(1) Note1: PIC16(L)F1939 only. As an example, LCDDATAn is detailed in Register27-6. Once the module is configured, the LCDEN bit of the LCDCON register is used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN bit of the LCDCON register. DS40001574C-page 326  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 27.2 Register Definitions: LCD Control REGISTER 27-1: LCDCON: LIQUID CRYSTAL DISPLAY (LCD) CONTROL REGISTER R/W-0/0 R/W-0/0 R/C-0/0 U-0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7 LCDEN: LCD Driver Enable bit 1 = LCD Driver module is enabled 0 = LCD Driver module is disabled bit 6 SLPEN: LCD Driver Enable in Sleep Mode bit 1 = LCD Driver module is disabled in Sleep mode 0 = LCD Driver module is enabled in Sleep mode bit 5 WERR: LCD Write Failed Error bit 1 = LCDDATAn register written while the WA bit of the LCDPS register = 0 (must be cleared in software) 0 = No LCD write error bit 4 Unimplemented: Read as ‘0’ bit 3-2 CS<1:0>: Clock Source Select bits 00 = FOSC/256 01 = T1OSC (Timer1) 1x = LFINTOSC (31 kHz) bit 1-0 LMUX<1:0>: Commons Select bits Maximum Number of Pixels LMUX<1:0> Multiplex Bias PIC16(L)F1938 PIC16(L)F1939 00 Static (COM0) 16 24 Static 01 1/2 (COM<1:0>) 32 48 1/2 or 1/3 10 1/3 (COM<2:0>) 48 72 1/2 or 1/3 11 1/4 (COM<3:0>) 60(1) 96 1/3 Note 1: On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 64 pixels.  2011-2013 Microchip Technology Inc. DS40001574C-page 327

PIC16(L)F1938/9 REGISTER 27-2: LCDPS: LCD PHASE REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 WFT BIASMD LCDA WA LP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7 WFT: Waveform Type bit 1 = Type-B phase changes on each frame boundary 0 = Type-A phase changes within each common type bit 6 BIASMD: Bias Mode Select bit When LMUX<1:0> = 00: 0 = Static Bias mode (do not set this bit to ‘1’) When LMUX<1:0> = 01: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 10: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 11: 0 = 1/3 Bias mode (do not set this bit to ‘1’) bit 5 LCDA: LCD Active Status bit 1 = LCD Driver module is active 0 = LCD Driver module is inactive bit 4 WA: LCD Write Allow Status bit 1 = Writing to the LCDDATAn registers is allowed 0 = Writing to the LCDDATAn registers is not allowed bit 3-0 LP<3:0>: LCD Prescaler Selection bits 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1 DS40001574C-page 328  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 27-3: LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7 LCDIRE: LCD Internal Reference Enable bit 1 = Internal LCD Reference is enabled and connected to the Internal Contrast Control circuit 0 = Internal LCD Reference is disabled bit 6 LCDIRS: LCD Internal Reference Source bit If LCDIRE = 1: 0 = Internal LCD Contrast Control is powered by VDD 1 = Internal LCD Contrast Control is powered by a 3.072V output of the FVR. If LCDIRE=0: Internal LCD Contrast Control is unconnected. LCD bandgap buffer is disabled. bit 5 LCDIRI: LCD Internal Reference Ladder Idle Enable bit Allows the Internal FVR buffer to shut down when the LCD Reference Ladder is in power mode ‘B’ 1 = When the LCD Reference Ladder is in power mode ‘B’, the LCD Internal FVR buffer is disabled. 0 = The LCD Internal FVR Buffer ignores the LCD Reference Ladder Power mode. bit 4 Unimplemented: Read as ‘0’ bit 3 VLCD3PE: VLCD3 Pin Enable bit 1 = The VLCD3 pin is connected to the internal bias voltage LCDBIAS3(1) 0 = The VLCD3 pin is not connected bit 2 VLCD2PE: VLCD2 Pin Enable bit 1 = The VLCD2 pin is connected to the internal bias voltage LCDBIAS2(1) 0 = The VLCD2 pin is not connected bit 1 VLCD1PE: VLCD1 Pin Enable bit 1 = The VLCD1 pin is connected to the internal bias voltage LCDBIAS1(1) 0 = The VLCD1 pin is not connected bit 0 Unimplemented: Read as ‘0’ Note 1: Normal pin controls of TRISx and ANSELx are unaffected.  2011-2013 Microchip Technology Inc. DS40001574C-page 329

PIC16(L)F1938/9 REGISTER 27-4: LCDCST: LCD CONTRAST CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — — LCDCST<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LCDCST<2:0>: LCD Contrast Control bits Selects the resistance of the LCD contrast control resistor ladder Bit Value=Resistor ladder 000 = Minimum Resistance (maximum contrast). Resistor ladder is shorted. 001 = Resistor ladder is at 1/7th of maximum resistance 010 = Resistor ladder is at 2/7th of maximum resistance 011 = Resistor ladder is at 3/7th of maximum resistance 100 = Resistor ladder is at 4/7th of maximum resistance 101 = Resistor ladder is at 5/7th of maximum resistance 110 = Resistor ladder is at 6/7th of maximum resistance 111 = Resistor ladder is at maximum resistance (minimum contrast). DS40001574C-page 330  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 REGISTER 27-5: LCDSEn: LCD SEGMENT ENABLE REGISTERS R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SEn SEn SEn SEn SEn SEn SEn SEn bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SEn: Segment Enable bits 1 = Segment function of the pin is enabled 0 = I/O function of the pin is enabled REGISTER 27-6: LCDDATAn: LCD DATA REGISTERS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SEGx-COMy: Pixel On bits 1 = Pixel on (dark) 0 = Pixel off (clear)  2011-2013 Microchip Technology Inc. DS40001574C-page 331

PIC16(L)F1938/9 27.3 LCD Clock Source Selection Using bits CS<1:0> of the LCDCON register can select any of these clock sources. The LCD module has three possible clock sources: 27.3.1 LCD PRESCALER • FOSC/256 • T1OSC A 4-bit counter is available as a prescaler for the LCD • LFINTOSC clock. The prescaler is not directly readable or writable; its value is set by the LP<3:0> bits of the LCDPS register, The first clock source is the system clock divided by which determine the prescaler assignment and prescale 256 (FOSC/256). This divider ratio is chosen to provide ratio. about 1 kHz output when the system clock is 8MHz. The divider is not programmable. Instead, the LCD The prescale values are selectable from 1:1 through prescaler bits LP<3:0> of the LCDPS register are used 1:16. to set the LCD frame clock rate. The second clock source is the T1OSC. This also gives about 1 kHz when a 32.768 kHz crystal is used with the Timer1 oscillator. To use the Timer1 oscillator as a clock source, the T1OSCEN bit of the T1CON register should be set. The third clock source is the 31kHz LFINTOSC, which provides approximately 1 kHz output. The second and third clock sources may be used to continue running the LCD while the processor is in Sleep. FIGURE 27-2: LCD CLOCK GENERATION 0 12 3 FOSC ÷256 To Ladder M MM M O OO O Power Control C CC C ÷4 Static T1OSC 32 kHz Crystal Osc. ÷2 1/2 4-bit Prog ÷ 32 Segment ÷1, 2, 3, 4 Prescaler Clock Ring Counter Counter 1/3, LFINTOSC 1/4 Nominal=31kHz LP<3:0> CS<1:0> LMUX<1:0> DS40001574C-page 332  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 27.4 LCD Bias Voltage Generation TABLE 27-2: LCD BIAS VOLTAGES The LCD module can be configured for one of three Static Bias 1/2 Bias 1/3 Bias bias types: LCD Bias 0 VSS VSS VSS • Static Bias (2 voltage levels: VSS and VLCD) LCD Bias 1 — 1/2 VDD 1/3 VDD • 1/2 Bias (3 voltage levels: VSS, 1/2VLCD and LCD Bias 2 — 1/2 VDD 2/3 VDD VLCD) LCD Bias 3 VLCD3 VLCD3 VLCD3 • 1/3 Bias (4 voltage levels: VSS, 1/3VLCD, So that the user is not forced to place external compo- 2/3VLCD and VLCD) nents and use up to three pins for bias voltage generation, internal contrast control and an internal reference ladder are provided internally to the PIC16(L)F193X. Both of these features may be used in conjunction with the exter- nal VLCD<3:1> pins, to provide maximum flexibility. Refer to Figure27-3. FIGURE 27-3: LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM LCDIRE VDD LCDIRS LCDA 1.024V from FVR 3.072V x 3 LCDIRE LCDRLP1 LCDIRS LCDRLP0 LCDA LCDCST<2:0> VLCD3PE LCDA VLCD3 lcdbias3 VLCD2PE VLCD2 lcdbias2 BIASMD VLCD1PE VLCD1 lcdbias1 lcdbias0  2011-2013 Microchip Technology Inc. DS40001574C-page 333

PIC16(L)F1938/9 27.5 LCD Bias Internal Reference 27.5.2 POWER MODES Ladder The internal reference ladder may be operated in one of three power modes. This allows the user to trade off LCD The internal reference ladder can be used to divide the contrast for power in the specific application. The larger LCD bias voltage two or three equally spaced voltages the LCD glass, the more capacitance is present on a that will be supplied to the LCD segment pins. To create physical LCD segment, requiring more current to this, the reference ladder consists of three matched maintain the same contrast level. resistors. Refer to Figure27-3. Three different power modes are available, LP, MP and 27.5.1 BIAS MODE INTERACTION HP. The internal reference ladder can also be turned off for applications that wish to provide an external ladder When in 1/2 Bias mode (BIASMD = 1), then the middle or to minimize power consumption. Disabling the resistor of the ladder is shorted out so that only two internal reference ladder results in all of the ladders voltages are generated. The current consumption of the being disconnected, allowing external voltages to be ladder is higher in this mode, with the one resistor supplied. removed. Whenever the LCD module is inactive (LCDA=0), the TABLE 27-3: LCD INTERNAL LADDER internal reference ladder will be turned off. POWER MODES (1/3 BIAS) Power Nominal Resistance of Nominal Mode Entire Ladder IDD Low 3Mohm 1µA Medium 300kohm 10µA High 30kohm 100µA DS40001574C-page 334  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 27.5.3 AUTOMATIC POWER MODE The LCDRL register allows switching between two SWITCHING power modes, designated ‘A’ and ‘B’. ‘A’ Power mode is active for a programmable time, beginning at the As an LCD segment is electrically only a capacitor, cur- time when the LCD segments transition. ‘B’ Power rent is drawn only during the interval where the voltage mode is the remaining time before the segments or is switching. To minimize total device current, the LCD commons change again. The LRLAT<2:0> bits select internal reference ladder can be operated in a different how long, if any, that the ‘A’ Power mode is active. power mode for the transition portion of the duration. Refer to Figure27-4. This is controlled by the LCDRL Register (Register27-7). To implement this, the 5-bit prescaler used to divide the 32kHz clock down to the LCD controller’s 1kHz base rate is used to select the power mode. FIGURE 27-4: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A Single Segment Time 32 kHz Clock Ladder Power ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F ‘H00 ‘H01 Control Segment Clock LRLAT<2:0> ‘H3 Segment Data LRLAT<2:0> Power Mode Power Mode A Power Mode B Mode A V COM0 1 V 0 V 1 SEG0 V 0 V 1 COM0-SEG0 V 0 -V 1  2011-2013 Microchip Technology Inc. DS40001574C-page 335

D FIGURE 27-5: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) P S 4 0 I 0 C 0 15 Single Segment Time Single Segment Time 7 1 4 C 6 -pag 32 kHz Clock ( e L 3 36 Ladder Power ) Control ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F F 1 Segment Clock 9 3 Segment Data 8 / 9 Power Mode Power Mode A Power Mode B Power Mode A Power Mode B LRLAT<2:0> = 011 LRLAT<2:0> = 011 V 2 V 1 COM0-SEG0 V0 -V 1 -V 2  2 0 1 1 -2 0 1 3 M ic ro c h ip T e c h n o lo g y In c .

 FIGURE 27-6: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE B WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) 2 0 1 1 -20 Single Segment Time Single Segment Time Single Segment Time Single Segment Time 1 3 M ic 32 kHz Clock ro c h ip T Ladder Power e Control ‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F ‘H10 ‘H11 ‘H12 ‘H13 ‘H1E ‘H1F ‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F ‘H10 ‘H11 ‘H12 ‘H13 ‘H1E ‘H1F c h n olo Segment Clock g y In c . Segment Data Power Mode Power Mode A Power Mode B Power Mode A Power Mode B Power Mode A Power Mode B Power Mode A Power Mode B LRLAT<2:0> = 011 LRLAT<2:0> = 011 LRLAT<2:0> = 011 LRLAT<2:0> = 011 V2 V1 COM0-SEG0 V0 -V1 P -V2 I C 1 6 ( L D ) S4 F 0 00 1 1 5 9 7 4 C 3 -p a 8 g e 3 /9 3 7

PIC16(L)F1938/9 REGISTER 27-7: LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 LRLAP<1:0> LRLBP<1:0> — LRLAT<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits During Time interval A (Refer to Figure27-4): 00 = Internal LCD Reference Ladder is powered down and unconnected 01 = Internal LCD Reference Ladder is powered in Low-Power mode 10 = Internal LCD Reference Ladder is powered in Medium-Power mode 11 = Internal LCD Reference Ladder is powered in High-Power mode bit 5-4 LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits During Time interval B (Refer to Figure27-4): 00 = Internal LCD Reference Ladder is powered down and unconnected 01 = Internal LCD Reference Ladder is powered in Low-Power mode 10 = Internal LCD Reference Ladder is powered in Medium-Power mode 11 = Internal LCD Reference Ladder is powered in High-Power mode bit 3 Unimplemented: Read as ‘0’ bit 2-0 LRLAT<2:0>: LCD Reference Ladder A Time interval control bits Sets the number of 32 kHz clocks that the A Time interval power mode is active For type A waveforms (WFT = 0): 000 =Internal LCD Reference Ladder is always in ‘B’ Power mode 001 =Internal LCD Reference Ladder is in ‘A’ Power mode for 1 clock and ‘B’ Power mode for 15 clocks 010 =Internal LCD Reference Ladder is in ‘A’ Power mode for 2 clocks and ‘B’ Power mode for 14 clocks 011 =Internal LCD Reference Ladder is in ‘A’ Power mode for 3 clocks and ‘B’ Power mode for 13 clocks 100 =Internal LCD Reference Ladder is in ‘A’ Power mode for 4 clocks and ‘B’ Power mode for 12 clocks 101 = Internal LCD Reference Ladder is in ‘A’ Power mode for 5 clocks and ‘B’ Power mode for 11 clocks 110 =Internal LCD Reference Ladder is in ‘A’ Power mode for 6 clocks and ‘B’ Power mode for 10 clocks 111 = Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 9 clocks For type B waveforms (WFT = 1): 000 = Internal LCD Reference Ladder is always in ‘B’ Power mode. 001 =Internal LCD Reference Ladder is in ‘A’ Power mode for 1 clock and ‘B’ Power mode for 31 clocks 010 =Internal LCD Reference Ladder is in ‘A’ Power mode for 2 clocks and ‘B’ Power mode for 30 clocks 011 =Internal LCD Reference Ladder is in ‘A’ Power mode for 3 clocks and ‘B’ Power mode for 29 clocks 100 =Internal LCD Reference Ladder is in ‘A’ Power mode for 4 clocks and ‘B’ Power mode for 28 clocks 101 = Internal LCD Reference Ladder is in ‘A’ Power mode for 5 clocks and ‘B’ Power mode for 27 clocks 110 =Internal LCD Reference Ladder is in ‘A’ Power mode for 6 clocks and ‘B’ Power mode for 26 clocks 111 = Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 25 clocks DS40001574C-page 338  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 27.5.4 CONTRAST CONTROL The contrast control circuit is used to decrease the output voltage of the signal source by a total of The LCD contrast control circuit consists of a approximately 10%, when LCDCST=111. seven-tap resistor ladder, controlled by the LCDCST bits. Refer to Figure27-7. Whenever the LCD module is inactive (LCDA=0), the contrast control ladder will be turned off (open). FIGURE 27-7: INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM VDDIO 7 Stages R R R R 3.072V Analog From FVR MUX Buffer 7 To top of Reference Ladder 0 LCDCST<2:0> 3 Internal Reference Contrast control 27.5.5 INTERNAL REFERENCE 27.5.6 VLCD<3:1> PINS Under firmware control, an internal reference for the The VLCD<3:1> pins provide the ability for an external LCD bias voltages can be enabled. When enabled, the LCD bias network to be used instead of the internal source of this voltage can be either VDDIO or a voltage ladder. Use of the VLCD<3:1> pins does not prevent 3times the main Fixed Voltage Reference (3.072V). use of the internal ladder. Each VLCD pin has an When no internal reference is selected, the LCD con- independent control in the LCDREF register trast control circuit is disabled and LCD bias must be (Register27-3), allowing access to any or all of the provided externally. LCD Bias signals. This architecture allows for maximum flexibility in different applications Whenever the LCD module is inactive (LCDA=0), the internal reference will be turned off. For example, the VLCD<3:1> pins may be used to add capacitors to the internal reference ladder, increasing When the internal reference is enabled and the Fixed the drive capacity. Voltage Reference is selected, the LCDIRI bit can be used to minimize power consumption by tying into the For applications where the internal contrast control is LCD reference ladder automatic power mode switch- insufficient, the firmware can choose to only enable the ing. When LCDIRI=1 and the LCD reference ladder is VLCD3 pin, allowing an external contrast control circuit in power mode ‘B’, the LCD internal FVR buffer is to use the internal reference divider. disabled. Note: The LCD module automatically turns on the fixed voltage reference when needed.  2011-2013 Microchip Technology Inc. DS40001574C-page 339

PIC16(L)F1938/9 27.6 LCD Multiplex Types TABLE 27-5: FRAME FREQUENCY FORMULAS The LCD Driver module can be configured into one of four multiplex types: Multiplex Frame Frequency = • Static (only COM0 is used) Static Clock source/(4 x 1 x (LCD Prescaler) x • 1/2 multiplex (COM<1:0> are used) 32)) • 1/3 multiplex (COM<2:0> are used) 1/2 Clock source/(2 x 2 x (LCD Prescaler) x • 1/4 multiplex (COM<3:0> are used) 32)) 1/3 Clock source/(1 x 3 x (LCD Prescaler) x The LMUX<1:0> bit setting of the LCDCON register 32)) decides which of the LCD common pins are used (see Table27-4 for details). 1/4 Clock source/(1 x 4 x (LCD Prescaler) x 32)) If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. If the pin is a COM drive, Note: Clock source is FOSC/256, T1OSC or then the TRIS setting of that pin is overridden. LFINTOSC. TABLE 27-4: COMMON PIN USAGE TABLE 27-6: APPROXIMATE FRAME FREQUENCY (IN Hz) USING LMUX Multiplex COM3 COM2 COM1 FOSC @ 8 MHz, TIMER1 @ <1:0> 32.768 kHz OR LFINTOSC Static 00 Unused Unused Unused LP<3:0> Static 1/2 1/3 1/4 1/2 01 Unused Unused Active 1/3 10 Unused Active Active 2 122 122 162 122 1/4 11 Active Active Active 3 81 81 108 81 4 61 61 81 61 27.7 Segment Enables 5 49 49 65 49 The LCDSEn registers are used to select the pin 6 41 41 54 41 function for each segment pin. The selection allows 7 35 35 47 35 each pin to operate as either an LCD segment driver or as one of the pin’s alternate functions. To configure the pin as a segment pin, the corresponding bits in the LCDSEn registers must be set to ‘1’. If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. Any bit set in the LCDSEn registers overrides any bit settings in the corresponding TRIS register. Note: On a Power-on Reset, these pins are configured as normal I/O, not LCD pins. 27.8 Pixel Control The LCDDATAx registers contain bits which define the state of each pixel. Each bit defines one unique pixel. Register27-6 shows the correlation of each bit in the LCDDATAx registers to the respective common and segment signals. Any LCD pixel location not being used for display can be used as general purpose RAM. 27.9 LCD Frame Frequency The rate at which the COM and SEG outputs change is called the LCD frame frequency. DS40001574C-page 340  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 27-7: LCD SEGMENT MAPPING WORKSHEET LCD COM0 COM1 COM2 COM3 Function LCDDATAx LCD LCDDATAx LCD LCDDATAx LCD LCDDATAx LCD Address Segment Address Segment Address Segment Address Segment SEG0 LCDDATA0, 0 LCDDATA3, 0 LCDDATA6, 0 LCDDATA9, 0 SEG1 LCDDATA0, 1 LCDDATA3, 1 LCDDATA6, 1 LCDDATA9, 1 SEG2 LCDDATA0, 2 LCDDATA3, 2 LCDDATA6, 2 LCDDATA9, 2 SEG3 LCDDATA0, 3 LCDDATA3, 3 LCDDATA6, 3 LCDDATA9, 3 SEG4 LCDDATA0, 4 LCDDATA3, 4 LCDDATA6, 4 LCDDATA9, 4 SEG5 LCDDATA0, 5 LCDDATA3, 5 LCDDATA6, 5 LCDDATA9, 5 SEG6 LCDDATA0, 6 LCDDATA3, 6 LCDDATA6, 6 LCDDATA9, 6 SEG7 LCDDATA0, 7 LCDDATA3, 7 LCDDATA6, 7 LCDDATA9, 7 SEG8 LCDDATA1, 0 LCDDATA4, 0 LCDDATA7, 0 LCDDATA10, 0 SEG9 LCDDATA1, 1 LCDDATA4, 1 LCDDATA7, 1 LCDDATA10, 1 SEG10 LCDDATA1, 2 LCDDATA4, 2 LCDDATA7, 2 LCDDATA10, 2 SEG11 LCDDATA1, 3 LCDDATA4, 3 LCDDATA7, 3 LCDDATA10, 3 SEG12 LCDDATA1, 4 LCDDATA4, 4 LCDDATA7, 4 LCDDATA10, 4 SEG13 LCDDATA1, 5 LCDDATA4, 5 LCDDATA7, 5 LCDDATA10, 5 SEG14 LCDDATA1, 6 LCDDATA4, 6 LCDDATA7, 6 LCDDATA10, 6 SEG15 LCDDATA1, 7 LCDDATA4, 7 LCDDATA7, 7 LCDDATA10, 7 SEG16 LCDDATA2, 0 LCDDATA5, 0 LCDDATA8, 0 LCDDATA11, 0 SEG17 LCDDATA2, 1 LCDDATA5, 1 LCDDATA8, 1 LCDDATA11, 1 SEG18 LCDDATA2, 2 LCDDATA5, 2 LCDDATA8, 2 LCDDATA11, 2 SEG19 LCDDATA2, 3 LCDDATA5, 3 LCDDATA8, 3 LCDDATA11, 3 SEG20 LCDDATA2, 4 LCDDATA5, 4 LCDDATA8, 4 LCDDATA11, 4 SEG21 LCDDATA2, 5 LCDDATA5, 5 LCDDATA8, 5 LCDDATA11, 5 SEG22 LCDDATA2, 6 LCDDATA5, 6 LCDDATA8, 6 LCDDATA11, 6 SEG23 LCDDATA2, 7 LCDDATA5, 7 LCDDATA8, 7 LCDDATA11, 7  2011-2013 Microchip Technology Inc. DS40001574C-page 341

PIC16(L)F1938/9 27.10 LCD Waveform Generation The LCDs can be driven by two types of waveform: Type-A and Type-B. In Type-A waveform, the phase LCD waveforms are generated so that the net AC changes within each common type, whereas in Type-B voltage across the dark pixel should be maximized and waveform, the phase changes on each frame the net AC voltage across the clear pixel should be boundary. Thus, Type-A waveform maintains 0VDC minimized. The net DC voltage across any pixel should over a single frame, whereas Type-B waveform takes be zero. two frames. The COM signal represents the time slice for each Note1: If Sleep has to be executed with LCD common, while the SEG contains the pixel data. Sleep disabled (LCDCON<SLPEN> is The pixel signal (COM-SEG) will have no DC ‘1’), then care must be taken to execute component and it can take only one of the two RMS Sleep only when VDC on all the pixels is values. The higher RMS value will create a dark pixel ‘0’. and a lower RMS value will create a clear pixel. 2: When the LCD clock source is FOSC/256, As the number of commons increases, the delta if Sleep is executed, irrespective of the between the two RMS values decreases. The delta LCDCON<SLPEN> setting, the LCD represents the maximum contrast that the display can immediately goes into Sleep. Thus, take have. care to see that VDC on all pixels is ‘0’ when Sleep is executed. Figure27-8 through Figure27-18 provide waveforms for static, half-multiplex, 1/3-multiplex and 1/4-multiplex drives for Type-A and Type-B waveforms. FIGURE 27-8: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE V 1 COM0 pin V COM0 0 V 1 SEG0 pin V 0 V 1 SEG1 pin V 0 V 1 COM0-SEG0 V0 segment voltage (active) -V1 COM0-SEG1 V 0 segment voltage 1 Frame (inactive) 76543 2 10 GGGGG G GG EEEEE E EE SSSSS S SS DS40001574C-page 342  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 27-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V 2 COM0 pin V COM1 1 V 0 V 2 COM1 pin V COM0 1 V 0 V 2 SEG0 pin V1 V 0 V 2 SEG1 pin V1 V 0 3 2 1 0 V G G G G 2 E E E E S S S S V 1 COM0-SEG0 V0 segment voltage (active) -V1 -V 2 V 2 V 1 COM0-SEG1 V0 segment voltage -V (inactive) 1 -V 2 1 Frame 1 Segment Time Note: 1 Frame = 2 single segment times.  2011-2013 Microchip Technology Inc. DS40001574C-page 343

PIC16(L)F1938/9 FIGURE 27-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V COM1 2 COM0 pin V 1 V 0 COM0 V 2 COM1 pin V 1 V 0 V 2 SEG0 pin V 1 V 0 V 2 EG3 EG2 EG1 EG0SEG1 pin V1 S S S S V 0 V 2 V 1 COM0-SEG0 V0 segment voltage (active) -V1 -V 2 V 2 V 1 COM0-SEG1 V0 segment voltage -V (inactive) 1 -V 2 2 Frames 1 Segment Time Note: 1 Frame = 2 single segment times. DS40001574C-page 344  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 27-11: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V 3 V 2 COM1 COM0 pin V 1 V 0 V 3 COM0 V 2 COM1 pin V 1 V 0 V 3 V 2 SEG0 pin V 1 V 0 V 3 V 2 3 2 1 0 SEG1 pin G G G G V E E E E 1 S S S S V 0 V 3 V 2 V 1 COM0-SEG0 V0 segment voltage (active) -V1 -V 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V0 segment voltage -V (inactive) 1 -V 2 1 Frame -V 3 1 Segment Time Note: 1 Frame = 2 single segment times.  2011-2013 Microchip Technology Inc. DS40001574C-page 345

PIC16(L)F1938/9 FIGURE 27-12: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V 3 V COM1 2 COM0 pin V 1 V 0 V 3 COM0 V 2 COM1 pin V 1 V 0 V 3 V 2 SEG0 pin V 1 V 0 V 3 V 2 3 2 1 0 SEG1 pin G G G G V E E E E 1 S S S S V 0 V 3 V 2 V 1 COM0-SEG0 V0 segment voltage (active) -V1 -V 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V0 segment voltage -V (inactive) 1 2 Frames -V2 -V 3 1 Segment Time Note: 1 Frame = 2 single segment times. DS40001574C-page 346  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 27-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V 2 COM0 pin V 1 V 0 V 2 COM2 COM1 pin V 1 V 0 COM1 V 2 COM0 COM2 pin V 1 V 0 V 2 SEG0 and V SEG2 pins 1 V 0 V 2 SEG1 pin V 1 2 1 0 V G G G 0 E E E S S S V 2 V 1 COM0-SEG0 V 0 segment voltage -V (inactive) 1 -V 2 V 2 V 1 COM0-SEG1 V 0 segment voltage -V (active) 1 -V 2 1 Frame 1 Segment Time Note: 1 Frame = 2 single segment times.  2011-2013 Microchip Technology Inc. DS40001574C-page 347

PIC16(L)F1938/9 FIGURE 27-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V 2 COM0 pin V 1 V 0 COM2 V 2 COM1 pin V 1 COM1 V COM0 0 V 2 COM2 pin V 1 V 0 V 2 SEG0 pin V 1 V 2 1 0 0 G G G E E E S S S V 2 SEG1 pin V 1 V 0 V 2 V 1 COM0-SEG0 V 0 segment voltage -V (inactive) 1 -V 2 V 2 V 1 COM0-SEG1 V 0 segment voltage -V (active) 1 -V 2 2 Frames 1 Segment Time Note: 1 Frame = 2 single segment times. DS40001574C-page 348  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 27-15: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V 3 V 2 COM0 pin V 1 V 0 COM2 V3 V 2 COM1 pin V 1 COM1 V COM0 0 V 3 V 2 COM2 pin V 1 V 0 V 3 V 2 SEG0 and V SEG2 pins 1 V 2 1 0 0 G G G E E E V S S S 3 V 2 SEG1 pin V 1 V 0 V 3 V 2 V 1 COM0-SEG0 V 0 segment voltage -V (inactive) 1 -V 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V 0 segment voltage -V (active) 1 -V 2 -V 3 1 Frame 1 Segment Time Note: 1 Frame = 2 single segment times.  2011-2013 Microchip Technology Inc. DS40001574C-page 349

PIC16(L)F1938/9 FIGURE 27-16: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V 3 V 2 COM0 pin V 1 V 0 COM2 V3 V 2 COM1 pin V 1 COM1 V COM0 0 V 3 V 2 COM2 pin V 1 V 0 V 3 V 2 SEG0 pin V 1 V 2 1 0 0 G G G E E E V S S S 3 V 2 SEG1 pin V 1 V 0 V 3 V 2 V 1 COM0-SEG0 V 0 segment voltage -V (inactive) 1 -V 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V 0 segment voltage -V (active) 1 -V 2 -V 3 2 Frames 1 Segment Time Note: 1 Frame = 2 single segment times. DS40001574C-page 350  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 27-17: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 V 3 V COM0 pin 2 V COM2 1 V 0 V 3 V COM1 pin 2 COM1 V1 V 0 COM0 V 3 V COM2 pin 2 V 1 V 0 V 3 V COM3 pin 2 V 1 V 0 V 3 V SEG0 pin 2 V 1 V 0 V 3 1 0 V EG EG SEG1 pin V21 S S V 0 V 3 V 2 V 1 COM0-SEG0 V0 segment voltage -V1 -V (active) 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V0 segment voltage -V1 -V (inactive) 2 -V 3 1 Frame 1 Segment Time Note: 1 Frame = 2 single segment times.  2011-2013 Microchip Technology Inc. DS40001574C-page 351

PIC16(L)F1938/9 FIGURE 27-18: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 V 3 V COM0 pin 2 V 1 COM2 V 0 V 3 V COM1 pin 2 COM1 V1 V 0 COM0 V 3 V COM2 pin 2 V 1 V 0 V 3 V COM3 pin 2 V 1 V 0 V 3 V SEG0 pin 2 V 1 V 0 V 3 EG1 EG0 SEG1 pin VV21 S S V 0 V 3 V 2 V 1 COM0-SEG0 V0 segment voltage -V1 -V (active) 2 -V 3 V 3 V 2 V 1 COM0-SEG1 V0 segment voltage -V1 -V (inactive) 2 -V 2 Frames 3 1 Segment Time Note: 1 Frame = 2 single segment times. DS40001574C-page 352  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 27.11 LCD Interrupts The LCD module provides an interrupt in two cases. An interrupt when the LCD controller goes from active to inactive controller. An interrupt also provides unframed boundaries for Type B waveform. The LCD timing gen- eration provides an interrupt that defines the LCD frame timing. 27.11.1 LCD INTERRUPT ON MODULE SHUTDOWN An LCD interrupt is generated when the module completes shutting down (LCDA goes from ‘1’ to ‘0’). 27.11.2 LCD FRAME INTERRUPTS A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes access- ing all pixel data required for a frame. This will occur at a fixed interval before the frame boundary (TFINT), as shown in Figure27-19. The LCD controller will begin to access data for the next frame within the interval from the interrupt to when the controller begins to access data after the interrupt (TFWR). New data must be writ- ten within TFWR, as this is when the LCD controller will begin to access the data for the next frame. When the LCD driver is running with Type-B waveforms and the LMUX<1:0> bits are not equal to ‘00’ (static drive), there are some additional issues that must be addressed. Since the DC voltage on the pixel takes two frames to maintain zero volts, the pixel data must not change between subsequent frames. If the pixel data were allowed to change, the waveform for the odd frames would not necessarily be the complement of the waveform generated in the even frames and a DC component would be introduced into the panel. Therefore, when using Type-B waveforms, the user must synchronize the LCD pixel updates to occur within a subframe after the frame interrupt. To correctly sequence writing while in Type-B, the interrupt will only occur on complete phase intervals. If the user attempts to write when the write is disabled, the WERR bit of the LCDCON register is set and the write does not occur. Note: The LCD frame interrupt is not generated when the Type-A waveform is selected and when the Type-B with no multiplex (static) is selected.  2011-2013 Microchip Technology Inc. DS40001574C-page 353

PIC16(L)F1938/9 FIGURE 27-19: WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE (EXAMPLE – TYPE-B, NON-STATIC) LCD Controller Accesses Interrupt Next Frame Data Occurs V 3 V 2 COM0 V 1 V 0 V 3 V 2 COM1 V 1 V 0 V 3 V 2 COM2 V 1 V 0 COM3 V3 V 2 V 1 V 0 2 Frames TFINT Frame Frame TFWR Frame Boundary Boundary Boundary TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2 TFINT = (TFWR/2 – (2 TCY + 40 ns)) minimum =1.5(TFRAME/4) – (2 TCY + 40 ns) (TFWR/2 – (1 TCY + 40 ns)) maximum=1.5(TFRAME/4) – (1 TCY + 40 ns) DS40001574C-page 354  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 27.12 Operation During Sleep Table27-8 shows the status of the LCD module during a Sleep while using each of the three available clock The LCD module can operate during Sleep. The sources. selection is controlled by bit SLPEN of the LCDCON register. Setting the SLPEN bit allows the LCD module Note: When the LCDEN bit is cleared, the LCD to go to Sleep. Clearing the SLPEN bit allows the module will be disabled at the completion module to continue to operate during Sleep. of frame. At this time, the port pins will revert to digital functionality. To minimize If a SLEEP instruction is executed and SLPEN = 1, the power consumption due to floating digital LCD module will cease all functions and go into a very inputs, the LCD pins should be driven low low-current consumption mode. The module will stop using the PORT and TRIS registers. operation immediately and drive the minimum LCD voltage on both segment and common lines. If a SLEEP instruction is executed and SLPEN = 0, the Figure27-20 shows this operation. module will continue to display the current contents of the LCDDATA registers. To allow the module to The LCD module can be configured to operate during continue operation while in Sleep, the clock source Sleep. The selection is controlled by bit SLPEN of the must be either the LFINTOSC or T1OSC external LCDCON register. Clearing SLPEN and correctly oscillator. While in Sleep, the LCD data cannot be configuring the LCD module clock will allow the LCD changed. The LCD module current consumption will module to operate during Sleep. Setting SLPEN and not decrease in this mode; however, the overall correctly executing the LCD module shutdown will consumption of the device will be lower due to shut disable the LCD module during Sleep and save power. down of the core and other peripheral functions. If a SLEEP instruction is executed and SLPEN = 1, the Table27-8 shows the status of the LCD module during LCD module will immediately cease all functions, drive Sleep while using each of the three available clock the outputs to Vss and go into a very low-current mode. sources: The SLEEP instruction should only be executed after the LCD module has been disabled and the current TABLE 27-8: LCD MODULE STATUS cycle completed, thus ensuring that there are no DC voltages on the glass. To disable the LCD module, DURING SLEEP clear the LCDEN bit. The LCD module will complete the Operational disabling process after the current frame, clear the Clock Source SLPEN During Sleep LCDA bit and optionally cause an interrupt. 0 Yes The steps required to properly enter Sleep with the T1OSC LCD disabled are: 1 No 0 Yes • Clear LCDEN LFINTOSC • Wait for LCDA = 0 either by polling or by interrupt 1 No • Execute SLEEP 0 No FOSC/4 If SLPEN = 0 and SLEEP is executed while the LCD 1 No module clock source is FOSC/4, then the LCD module will halt with the pin driving the last LCD voltage pattern. Prolonged exposure to a fixed LCD voltage Note: The LFINTOSC or external T1OSC pattern will cause damage to the LCD glass. To prevent oscillator must be used to operate the LCD glass damage, either perform the proper LCD LCD module during Sleep. module shutdown prior to Sleep, or change the LCD If LCD interrupts are being generated (Type-B wave- module clock to allow the LCD module to continue form with a multiplex mode not static) and LCDIE = 1, operation during Sleep. the device will awaken from Sleep on the next frame If a SLEEP instruction is executed and SLPEN = 0 and boundary. the LCD module clock is either T1OSC or LFINTOSC, the module will continue to display the current contents of the LCDDATA registers. While in Sleep, the LCD data cannot be changed. If the LCDIE bit is set, the device will wake from Sleep on the next LCD frame boundary. The LCD module current consumption will not decrease in this mode; however, the overall device power consumption will be lower due to the shutdown of the CPU and other peripherals.  2011-2013 Microchip Technology Inc. DS40001574C-page 355

PIC16(L)F1938/9 FIGURE 27-20: SLEEP ENTRY/EXIT WHEN SLPEN = 1 V 3 V 2 V 1 COM0 V 0 V 3 V 2 V 1 COM1 V0 V 3 V 2 V 1 COM2 V0 V 3 V 2 V 1 SEG0 V 0 2 Frames SLEEP Instruction Execution Wake-up DS40001574C-page 356  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 27.13 Configuring the LCD Module 27.15 LCD Current Consumption The following is the sequence of steps to configure the When using the LCD module the current consumption LCD module. consists of the following three factors: 1. Select the frame clock prescale using bits • Oscillator Selection LP<3:0> of the LCDPS register. • LCD Bias Source 2. Configure the appropriate pins to function as • Capacitance of the LCD segments segment drivers using the LCDSEn registers. The current consumption of just the LCD module can 3. Configure the LCD module for the following be considered negligible compared to these other using the LCDCON register: factors. - Multiplex and Bias mode, bits LMUX<1:0> - Timing source, bits CS<1:0> 27.15.1 OSCILLATOR SELECTION - Sleep mode, bit SLPEN The current consumed by the clock source selected 4. Write initial values to pixel data registers, LCD- must be considered when using the LCD module. See DATA0 through LCDDATA11 (LCDDATA23 on the applicable Electrical Specifications Chapter for PIC16F1938). oscillator current consumption information. 5. Clear LCD Interrupt Flag, LCDIF bit of the PIR2 27.15.2 LCD BIAS SOURCE register and if desired, enable the interrupt by setting bit LCDIE of the PIE2 register. The LCD bias source, internal or external, can contrib- 6. Configure bias voltages by setting the LCDRL, ute significantly to the current consumption. Use the LCDREF and the associated ANSELx highest possible resistor values while maintaining registers as needed. contrast to minimize current. 7. Enable the LCD module by setting bit LCDEN of 27.15.3 CAPACITANCE OF THE LCD the LCDCON register. SEGMENTS 27.14 Disabling the LCD Module The LCD segments which can be modeled as capaci- tors which must be both charged and discharged every To disable the LCD module, write all ‘0’s to the frame. The size of the LCD segment and its technology LCDCON register. determines the segment’s capacitance.  2011-2013 Microchip Technology Inc. DS40001574C-page 357

PIC16(L)F1938/9 TABLE 27-9: SUMMARY OF REGISTERS ASSOCIATED WITH LCD OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 90 LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 327 LCDCST — — — — — LCDCST<2:0> 330 LCDDATA0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 331 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 LCDDATA1 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 331 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 LCDDATA2 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 331 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 LCDDATA3 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 331 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 LCDDATA4 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 331 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 LCDDATA5 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 331 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 LCDDATA6 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 331 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 LCDDATA7 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 331 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 LCDDATA8 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 331 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 LCDDATA9 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 331 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 LCDDATA10 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 331 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 LCDDATA11 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 331 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 LCDPS WFT BIASMD LCDA WA LP<3:0> 328 LCDREF LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE — 329 LCDRL LRLAP<1:0> LRLBP<1:0> — LRLAT<2:0> 338 LCDSE0 SE<7:0> 331 LCDSE1 SE<15:8> 331 LCDSE2 SE<23:16> 331 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 92 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF — CCP2IF 95 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 197 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the LCD module. DS40001574C-page 358  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 28.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirec- tional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16193X/PIC16LF193X Memory Programming Specification” (DS41360A). 28.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. Some programmers produce VPP greater than VIHH (9.0V), an external circuit is required to limit the VPP voltage. See Figure28-1 for example circuit. FIGURE 28-1: VPP LIMITER EXAMPLE CIRCUIT RJ11-6PIN 1 6 VPP 2 5 VDD 3 4 VSS 4 3 ICSP_DATA 5 2 ICSP_CLOCK 6 1 NC RJ11-6PIN To MPLAB® ICD 2 R1 To Target Board 270 Ohm LM431BCMX 23 A U1 K1 A 6 A NC4 7 A NC5 VREF 8 R2 R3 10k 1% 24k 1% Note: The MPLAB® ICD 2 produces a VPP voltage greater than the maximum VPP specification of the PIC16(L)F193X.  2011-2013 Microchip Technology Inc. DS40001574C-page 359

PIC16(L)F1938/9 28.2 Low-Voltage Programming Entry FIGURE 28-2: ICD RJ-11 STYLE Mode CONNECTOR INTERFACE The Low-Voltage Programming Entry mode allows the PIC16(L)F193X devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the ICSPDAT Low-Voltage ICSP mode, the LVP bit must be 2 4 6 NC VDD programmed to ‘0’. ICSPCLK 1 3 5 Target Entry into the Low-Voltage Programming Entry mode requires the following steps: VPP/MCLR VSS PC Board Bottom Side 1. MCLR is brought to VIL. 2. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Pin Description* Once the key sequence is complete, MCLR must be 1 = VPP/MCLR held at VIL for as long as Program/Verify mode is to be 2 = VDD Target maintained. 3 = VSS (ground) If low-voltage programming is enabled (LVP = 1), the 4 = ICSPDAT MCLR Reset function is automatically enabled and 5 = ICSPCLK cannot be disabled. See Section6.4 “MCLR” for more 6 = No Connect information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1inch 28.3 Common Programming Interfaces spacing. Refer to Figure28-3. Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure28-2. FIGURE 28-3: PICkit™ STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 1 = VPP/MCLR 2 2 = VDD Target 3 4 3 = VSS (ground) 5 4 = ICSPDAT 6 5 = ICSPCLK 6 = No Connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins. DS40001574C-page 360  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure28-4 for more information. FIGURE 28-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming VDD Device to be Signals Programmed VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required).  2011-2013 Microchip Technology Inc. DS40001574C-page 361

PIC16(L)F1938/9 NOTES: DS40001574C-page 362  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations Each PIC16 instruction is a 14-bit word containing the Any instruction that specifies a file register as part of operation code (opcode) and all required operands. the instruction performs a Read-Modify-Write (R-M-W) The opcodes are broken into three broad categories. operation. The register is read, the data is modified, and the result is stored according to either the instruc- • Byte Oriented tion, or the destination designator ‘d’. A read operation • Bit Oriented is performed on a register even if the instruction writes • Literal and Control to that register. The literal and control category contains the most varied instruction word format. TABLE 29-1: OPCODE FIELD DESCRIPTIONS Table29-3 lists the instructions recognized by the MPASMTM assembler. Field Description All instructions are executed within a single instruction f Register file address (0x00 to 0x7F) cycle, with the following exceptions, which may take W Working register (accumulator) two or three cycles: b Bit address within an 8-bit file register • Subroutine takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two k Literal field, constant data or label cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1). • Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0. BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for • One additional instruction cycle will be used when compatibility with all Microchip software tools. any instruction references an indirect file register d Destination select; d = 0: store result in W, and the file select register is pointing to program d = 1: store result in file register f. memory. Default is d = 1. One instruction cycle consists of four oscillator cycles; n FSR or INDF number. (0-1) for an oscillator frequency of 4 MHz, this gives a mm Pre-post increment-decrement mode nominal instruction execution rate of 1 MHz. selection All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a TABLE 29-2: ABBREVIATION hexadecimal digit. DESCRIPTIONS Field Description PC Program Counter TO Time-out bit C Carry bit DC Digit carry bit Z Zero bit PD Power-down bit  2011-2013 Microchip Technology Inc. DS40001574C-page 363

PIC16(L)F1938/9 FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value MOVLP instruction only 13 7 6 0 OPCODE k (literal) k = 7-bit immediate value MOVLB instruction only 13 5 4 0 OPCODE k (literal) k = 5-bit immediate value BRA instruction only 13 9 8 0 OPCODE k (literal) k = 9-bit immediate value FSR Offset instructions 13 7 6 5 0 OPCODE n k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 3 2 1 0 OPCODE n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE DS40001574C-page 364  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 29-3: PIC16(L)F193X ENHANCED INSTRUCTION SET Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2 ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2 ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2 LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2 LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0000 00xx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 2 INCF f, d Increment f 1 00 1010 dfff ffff Z 2 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 2 MOVWF f Move W to f 1 00 0000 1fff ffff 2 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2 SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 2 BIT-ORIENTED SKIP OPERATIONS BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2 LITERAL OPERATIONS ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLB k Move literal to BSR 1 00 0000 001k kkkk MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk MOVLW k Move literal to W 1 11 0000 kkkk kkkk SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.  2011-2013 Microchip Technology Inc. DS40001574C-page 365

PIC16(L)F1938/9 TABLE 29-3: PIC16(L)F193X ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected CONTROL OPERATIONS BRA k Relative Branch 2 11 001k kkkk kkkk BRW – Relative Branch with W 2 00 0000 0000 1011 CALL k Call Subroutine 2 10 0kkk kkkk kkkk CALLW – Call Subroutine with W 2 00 0000 0000 1010 GOTO k Go to address 2 10 1kkk kkkk kkkk RETFIE k Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 0100 kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 INHERENT OPERATIONS CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD NOP – No Operation 1 00 0000 0000 0000 OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010 RESET – Software device Reset 1 00 0000 0000 0001 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD TRIS f Load TRIS register with W 1 00 0000 0110 0fff C-COMPILER OPTIMIZED ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3 modifier, mm k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2 MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3 modifier, mm k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2 Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions. DS40001574C-page 366  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 29.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k Operands: -32  k  31 Operands: 0  k  255 n  [ 0, 1] Operation: (W) .AND. (k)  (W) Operation: FSR(n) + k  FSR(n) Status Affected: Z Status Affected: None Description: The contents of W register are Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The the contents of the FSRnH:FSRnL result is placed in the W register. register pair. FSRn is limited to the range 0000h - FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W ANDWF AND W with f Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d Operands: 0  k  255 Operands: 0  f  127 d 0,1 Operation: (W) + k  (W) Operation: (W) .AND. (f)  (destination) Status Affected: C, DC, Z Status Affected: Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the Description: AND the W register with register ‘f’. If result is placed in the W register. ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWF Add W and f ASRF Arithmetic Right Shift Syntax: [ label ] ADDWF f,d Syntax: [ label ] ASRF f {,d} Operands: 0  f  127 Operands: 0  f  127 d 0,1 d [0,1] Operation: (W) + (f)  (destination) Operation: (f<7>) dest<7> (f<7:1>)  dest<6:0>, Status Affected: C, DC, Z (f<0>)  C, Description: Add the contents of the W register Status Affected: C, Z with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the Description: The contents of register ‘f’ are shifted result is stored back in register ‘f’. one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in reg- ister ‘f’. ADDWFC ADD W and CARRY bit to f register f C Syntax: [ label ] ADDWFC f {,d} Operands: 0  f  127 d [0,1] Operation: (W) + (f) + (C)  dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data mem- ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.  2011-2013 Microchip Technology Inc. DS40001574C-page 367

PIC16(L)F1938/9 BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 0  b  7 0  b  7 Operation: 0  (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b [ label ] BRA $+k Operands: 0  f  127 Operands: -256label-PC+1255 0  b < 7 -256  k  255 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k  PC Status Affected: None Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Description: Add the signed 9-bit literal ‘k’ to the instruction is executed. PC. Since the PC will have incre- If bit ‘b’ is ‘1’, then the next mented to fetch the next instruction, instruction is discarded and a NOP is the new address will be PC+1+k. executed instead, making this a This instruction is a 2-cycle instruc- 2-cycle instruction. tion. This branch has a limited range. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W)  PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incre- mented to fetch the next instruction, the new address will be PC+1+(W). This instruction is a 2-cycle instruc- tion. BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0  f  127 0  b  7 Operation: 1  (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. DS40001574C-page 368  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<6:3>)  PC<14:11> 1  TO Status Affected: None 1  PD Description: Call Subroutine. First, return address Status Affected: TO, PD (PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch- The eleven-bit immediate address is dog Timer. It also resets the prescaler loaded into PC bits <10:0>. The upper of the WDT. bits of the PC are loaded from Status bits TO and PD are set. PCLATH. CALL is a 2-cycle instruc- tion. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: (PC) +1  TOS, (W)  PC<7:0>, Operation: (f)  (destination) (PCLATH<6:0>) PC<14:8> Status Affected: Z Description: The contents of register ‘f’ are com- Status Affected: None plemented. If ‘d’ is ‘0’, the result is Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is return address (PC + 1) is pushed stored back in register ‘f’. onto the return stack. Then, the con- tents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a two-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the and the Z bit is set. result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h  (W) 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set.  2011-2013 Microchip Technology Inc. DS40001574C-page 369

PIC16(L)F1938/9 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre- mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. is placed back in register ‘f’. If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is NOP is executed instead, making it a executed instead, making it a 2-cycle 2-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<6:3>  PC<14:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. The OR’ed with the 8-bit literal ‘k’. The eleven-bit immediate value is loaded result is placed in the W register. into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis- mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is is placed back in register ‘f’. placed back in register ‘f’. DS40001574C-page 370  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 LSLF Logical Left Shift MOVF Move f Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d Operands: 0  f  127 Operands: 0  f  127 d [0,1] d  [0,1] Operation: (f<7>)  C Operation: (f)  (dest) (f<6:0>)  dest<7:1> Status Affected: Z 0  dest<0> Description: The contents of register f is moved to Status Affected: C, Z a destination dependent upon the Description: The contents of register ‘f’ are shifted status of d. If d = 0, one bit to the left through the Carry flag. destination is W register. If d = 1, the A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, destination is file register f itself. d = 1 the result is placed in W. If ‘d’ is ‘1’, the is useful to test a file register since result is stored back in register ‘f’. status flag Z is affected. Words: 1 C register f 0 Cycles: 1 Example: MOVF FSR, 0 After Instruction LSRF Logical Right Shift W = value in FSR register Syntax: [ label ] LSRF f {,d} Z = 1 Operands: 0  f  127 d [0,1] Operation: 0  dest<7> (f<7:1>)  dest<6:0>, (f<0>)  C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘0’ is shifted into the MSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 0 register f C  2011-2013 Microchip Technology Inc. DS40001574C-page 371

PIC16(L)F1938/9 MOVIW Move INDFn to W MOVLP Move literal to PCLATH Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k [ label ] MOVIW --FSRn Operands: 0  k  127 [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-- Operation: k  PCLATH [ label ] MOVIW k[FSRn] Status Affected: None Operands: n  [0,1] Description: The seven-bit literal ‘k’ is loaded into the mm  [00,01, 10, 11] PCLATH register. -32  k  31 Operation: INDFn  W Effective address is determined by MOVLW Move literal to W • FSR + 1 (preincrement) Syntax: [ label ] MOVLW k • FSR - 1 (predecrement) • FSR + k (relative offset) Operands: 0  k  255 After the Move, the FSR value will be Operation: k  (W) either: • FSR + 1 (all increments) Status Affected: None • FSR - 1 (all decrements) Description: The eight-bit literal ‘k’ is loaded into W • Unchanged register. The “don’t cares” will assem- Status Affected: Z ble as ‘0’s. Words: 1 Mode Syntax mm Cycles: 1 Preincrement ++FSRn 00 Example: MOVLW 0x5A Predecrement --FSRn 01 After Instruction W = 0x5A Postincrement FSRn++ 10 Postdecrement FSRn-- 11 MOVWF Move W to f Syntax: [ label ] MOVWF f Description: This instruction is used to move data between W and one of the indirect Operands: 0  f  127 registers (INDFn). Before/after this Operation: (W)  (f) move, the pointer (FSRn) is updated by Status Affected: None pre/post incrementing/decrementing it. Description: Move data from W register to register Note: The INDFn registers are not ‘f’. physical registers. Any instruction that Words: 1 accesses an INDFn register actually accesses the register at the address Cycles: 1 specified by the FSRn. Example: MOVWF OPTION_REG Before Instruction FSRn is limited to the range 0000h - OPTION_REG = 0xFF FFFFh. Incrementing/decrementing it W = 0x4F beyond these bounds will cause it to After Instruction wrap-around. OPTION_REG = 0x4F W = 0x4F MOVLB Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0  k  15 Operation: k  BSR Status Affected: None Description: The 5-bit literal ‘k’ is loaded into the Bank Select Register (BSR). DS40001574C-page 372  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] NOP Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn Operands: None [ label ] MOVWI FSRn++ Operation: No operation [ label ] MOVWI FSRn-- [ label ] MOVWI k[FSRn] Status Affected: None Operands: n  [0,1] Description: No operation. mm  [00,01, 10, 11] Words: 1 -32  k  31 Cycles: 1 Operation: W  INDFn Example: NOP Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be Load OPTION_REG Register either: OPTION with W • FSR + 1 (all increments) • FSR - 1 (all decrements) Syntax: [ label ] OPTION Unchanged Operands: None Status Affected: None Operation: (W)  OPTION_REG Status Affected: None Mode Syntax mm Description: Move data from W register to Preincrement ++FSRn 00 OPTION_REG register. Predecrement --FSRn 01 Postincrement FSRn++ 10 Words: 1 Postdecrement FSRn-- 11 Cycles: 1 Example: OPTION Description: This instruction is used to move data Before Instruction between W and one of the indirect OPTION_REG = 0xFF registers (INDFn). Before/after this W = 0x4F move, the pointer (FSRn) is updated by After Instruction pre/post incrementing/decrementing it. OPTION_REG = 0x4F W = 0x4F Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually RESET Software Reset accesses the register at the address specified by the FSRn. Syntax: [ label ] RESET Operands: None FSRn is limited to the range 0000h - FFFFh. Incrementing/decrementing it Operation: Execute a device Reset. Resets the beyond these bounds will cause it to nRI flag of the PCON register. wrap-around. Status Affected: None Description: This instruction provides a way to The increment/decrement operation on execute a hardware Reset by soft- FSRn WILL NOT affect any Status bits. ware.  2011-2013 Microchip Technology Inc. DS40001574C-page 373

PIC16(L)F1938/9 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] RETFIE Syntax: [ label ] RETURN Operands: None Operands: None Operation: TOS  PC, Operation: TOS  PC 1  GIE Status Affected: None Status Affected: None Description: Return from subroutine. The stack is Description: Return from Interrupt. Stack is POPed POPed and the top of the stack (TOS) and Top-of-Stack (TOS) is loaded in is loaded into the program counter. the PC. Interrupts are enabled by This is a 2-cycle instruction. setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 RETLW Return with literal in W RLF Rotate Left f through Carry Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d Operands: 0  k  255 Operands: 0  f  127 d  [0,1] Operation: k  (W); TOS  PC Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the 8-bit Description: The contents of register ‘f’ are rotated literal ‘k’. The program counter is one bit to the left through the Carry loaded from the top of the stack (the flag. If ‘d’ is ‘0’, the result is placed in return address). This is a 2-cycle the W register. If ‘d’ is ‘1’, the result is instruction. stored back in register ‘f’. Words: 1 C Register f Cycles: 2 Words: 1 Example: CALL TABLE;W contains table Cycles: 1 ;offset value • ;W now has table value Example: RLF REG1,0 TABLE • Before Instruction • REG1 = 1110 0110 ADDWF PC ;W = offset C = 0 RETLW k1 ;Begin table After Instruction RETLW k2 ; REG1 = 1110 0110 • W = 1100 1100 • C = 1 • RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 DS40001574C-page 374  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 SUBLW Subtract W from literal RRF Rotate Right f through Carry Syntax: [ label ] SUBLW k Syntax: [ label ] RRF f,d Operands: 0 k 255 Operands: 0  f  127 d  [0,1] Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s com- plement method) from the 8-bit literal Description: The contents of register ‘f’ are rotated ‘k’. The result is placed in the W regis- one bit to the right through the Carry ter. flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is C = 0 W  k placed back in register ‘f’. C = 1 W  k C Register f DC = 0 W<3:0>  k<3:0> DC = 1 W<3:0>  k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] SLEEP Syntax: [ label ] SUBWF f,d Operands: None Operands: 0 f 127 d  [0,1] Operation: 00h  WDT, 0  WDT prescaler, Operation: (f) - (W) destination) 1  TO, Status Affected: C, DC, Z 0  PD Description: Subtract (2’s complement method) W Status Affected: TO, PD register from register ‘f’. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is result is stored in the W cleared. Time-out Status bit, TO is register. If ‘d’ is ‘1’, the result is stored set. Watchdog Timer and its pres- back in register ‘f. caler are cleared. The processor is put into Sleep mode C = 0 W  f with the oscillator stopped. C = 1 W  f DC = 0 W<3:0>  f<3:0> DC = 1 W<3:0>  f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB f {,d} Operands: 0  f  127 d  [0,1] Operation: (f) – (W) – (B) dest Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s comple- ment method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.  2011-2013 Microchip Technology Inc. DS40001574C-page 375

PIC16(L)F1938/9 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k Operands: 0  f  127 Operands: 0 k 255 d  [0,1] Operation: (W) .XOR. k W) Operation: (f<3:0>)  (destination<7:4>), Status Affected: Z (f<7:4>)  (destination<3:0>) Description: The contents of the W register are Status Affected: None XOR’ed with the 8-bit literal ‘k’. The Description: The upper and lower nibbles of regis- result is placed in the W register. ter ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. XORWF Exclusive OR W with f TRIS Load TRIS Register with W Syntax: [ label ] XORWF f,d Syntax: [ label ] TRIS f Operands: 0  f  127 Operands: 5  f  7 d  [0,1] Operation: (W)  TRIS register ‘f’ Operation: (W) .XOR. (f) destination) Status Affected: None Status Affected: Z Description: Move data from W register to TRIS Description: Exclusive OR the contents of the W register. register with register ‘f’. If ‘d’ is ‘0’, the When ‘f’ = 5, TRISA is loaded. result is stored in the W register. If ‘d’ When ‘f’ = 6, TRISB is loaded. is ‘1’, the result is stored back in regis- When ‘f’ = 7, TRISC is loaded. ter ‘f’. DS40001574C-page 376  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 30.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias.......................................................................................................-40°C to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F1938/39 ........................................................................ -0.3V to +6.5V Voltage on VCAP pin with respect to VSS, PIC16F1938/39..................................................................-0.3V to +4.0V Voltage on VDD with respect to VSS, PIC16LF1938/39 ...................................................................... -0.3V to +4.0V Voltage on MCLR with respect to Vss .................................................................................................-0.3V to +9.0V Voltage on all other pins with respect to VSS ...........................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)...............................................................................................................................800 mW Maximum current out of VSS pin, -40°C  TA  +85°C for industrial............................................................... 255 mA Maximum current out of VSS pin, -40°C  TA  +125°C for extended............................................................ 105 mA Maximum current into VDD pin, -40°C  TA  +85°C for industrial.................................................................. 170 mA Maximum current into VDD pin, -40°C  TA  +125°C for extended................................................................. 70 mA Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA Maximum output current sunk by any I/O pin....................................................................................................25 mA Maximum output current sourced by any I/O pin..............................................................................................25 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.  2011-2013 Microchip Technology Inc. DS40001574C-page 377

PIC16(L)F1938/9 FIGURE 30-1: PIC16F1938/9 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C 5.5 ) V ( D D V 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-1 for each Oscillator mode’s supported frequencies. FIGURE 30-2: PIC16LF1938/9 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C V) 3.6 ( D D V 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-1 for each Oscillator mode’s supported frequencies. DS40001574C-page 378  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 30-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 ± 3% C) ° 60 ( re ± 2% u at r e p 25 m e T 0 -20 ± 5% -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2011-2013 Microchip Technology Inc. DS40001574C-page 379

PIC16(L)F1938/9 30.1 DC Characteristics: PIC16(L)F1938/39-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) PIC16LF1938/39 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1938/39 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. D001 VDD Supply Voltage PIC16LF1938/39 1.8 — 3.6 V FOSC  16MHz: 2.5 — 3.6 V FOSC  32MHz (Note 2) D001 PIC16F1938/39 1.8 — 5.5 V FOSC  16MHz: 2.5 — 5.5 V FOSC  32MHz (Note 2) D002* VDR RAM Data Retention Voltage(1) PIC16LF1938/39 1.5 — — V Device in Sleep mode D002* PIC16F1938/39 1.7 — — V Device in Sleep mode VPOR* Power-on Reset Release Voltage D002A PIC16LF1938/39 — 1.6 — V D002A PIC16F1938/39 — 1.6 — V VPORR* Power-on Reset Rearm Voltage D002B PIC16LF1938/39 — 0.8 — V Device in Sleep mode D002B PIC16F1938/39 — 1.5 — V Device in Sleep mode D003 VADFVR Fixed Voltage Reference Voltage -8 — 6 % 1.024V, VDD  2.5V for ADC 2.048V, VDD  2.5V 4.096V, VDD  4.75V D003A VCDAFVR Fixed Voltage Reference Voltage -11 — 7 % 1.024V, VDD  2.5V for Comparator and DAC 2.048V, VDD  2.5V 4.096V, VDD  4.75V D003B VLCDFVR Fixed Voltage Reference Voltage -11 — 10 % 3.072V, VDD  3.6V for LCD Bias, Initial Accuracy D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See Section6.1 “Power-on Reset Power-on Reset signal (POR)” for details. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation. DS40001574C-page 380  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 30-4: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR(1) POR REARM VSS TVLOW(2) TPOR(3) Note 1: When NPOR is low, the device is held in Reset. 2: TPOR 1s typical. 3: TVLOW 2.7s typical.  2011-2013 Microchip Technology Inc. DS40001574C-page 381

PIC16(L)F1938/9 30.2 DC Characteristics: PIC16F/LF1938/39-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) PIC16LF1938/9 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1938/9 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D009 LDO Regulator — 350 — A — HS, EC OR INTOSC/INTOSCIO (8-16MHZ) Clock modes with all VCAP pins disabled — 50 — A — All VCAP pins disabled — 30 — A — VCAP enabled on RA0, RA5 or RA6 — 5 — A — LP Clock mode and Sleep (requires FVR and BOR to be disabled) D010 — 5.2 16 A 1.8 FOSC = 32kHz — 7.6 20 A 3.0 LP Oscillator mode (Note 4), -40°C  TA  +85°C D010 — 26 45 A 1.8 FOSC = 32kHz — 32 50 A 3.0 LP Oscillator mode (Note 4, 5), -40°C  TA  +85°C — 35 55 A 5.0 D010A — 5.2 16 A 1.8 FOSC = 32kHz — 7.6 20 A 3.0 LP Oscillator mode (Note 4) -40°C  TA  +125°C D010A — 26 55 A 1.8 FOSC = 32kHz — 32 70 A 3.0 LP Oscillator mode (Note 4, 5) -40°C  TA  +125°C — 35 75 A 5.0 D011 — 54 130 A 1.8 FOSC = 1MHz XT Oscillator mode — 110 170 A 3.0 D011 — 80 150 A 1.8 FOSC = 1MHz XT Oscillator mode (Note 5) — 140 210 A 3.0 — 190 280 A 5.0 D012 — 200 300 A 1.8 FOSC = 4MHz XT Oscillator mode — 350 480 A 3.0 D012 — 220 320 A 1.8 FOSC = 4MHz XT Oscillator mode (Note 5) — 390 520 A 3.0 — 470 630 A 5.0 Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k 4: FVR and BOR are disabled. 5: 0.1F capacitor on VCAP (RA0). 6: 8 MHz crystal oscillator with 4x PLL enabled. DS40001574C-page 382  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 30.2 DC Characteristics: PIC16F/LF1938/39-I/E (Industrial, Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF1938/9 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1938/9 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D013 — 4.7 130 A 1.8 FOSC = 500kHz EC Oscillator Low-Power mode — 24 200 A 3.0 D013 — 26 120 A 1.8 FOSC = 500kHz EC Oscillator Low-Power mode (Note 5) — 49 220 A 3.0 — 53 250 A 5.0 D014 — 170 250 A 1.8 FOSC = 4MHz — 310 420 A 3.0 EC Oscillator mode Medium-Power mode D014 — 200 280 A 1.8 FOSC = 4MHz — 340 470 A 3.0 EC Oscillator mode (Note 5) Medium-Power mode — 430 550 A 5.0 D015 — 2.6 3.5 mA 3.0 FOSC = 32MHz EC Oscillator High-Power mode — 3.3 4.2 mA 3.6 D015 — 2.7 3.5 mA 3.0 FOSC = 32MHz EC Oscillator High-Power mode (Note 5) — 3.0 3.9 mA 5.0 D016 — 3.1 12 A 1.8 FOSC = 32kHz LFINTOSC mode, 85°C — 5.5 16 A 3.0 D016 — 24 48 A 1.8 FOSC = 32kHz LFINTOSC mode, 85°C (Note 5) — 30 53 A 3.0 — 31 58 A 5.0 Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k 4: FVR and BOR are disabled. 5: 0.1F capacitor on VCAP (RA0). 6: 8 MHz crystal oscillator with 4x PLL enabled.  2011-2013 Microchip Technology Inc. DS40001574C-page 383

PIC16(L)F1938/9 30.2 DC Characteristics: PIC16F/LF1938/39-I/E (Industrial, Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF1938/9 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1938/9 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D017 — 90 160 A 1.8 FOSC = 500kHz MFINTOSC mode — 120 190 A 3.0 D017 — 120 190 A 1.8 FOSC = 500kHz — 150 240 A 3.0 MFINTOSC mode (Note 5) — 190 320 A 5.0 D018 — 0.6 0.8 mA 1.8 FOSC = 8MHz HFINTOSC mode — 1.0 1.3 mA 3.0 D018 — 0.7 0.9 mA 1.8 FOSC = 8MHz — 1.0 1.4 mA 3.0 HFINTOSC mode (Note 5) — 1.2 1.5 mA 5.0 D019 — 1.0 1.2 mA 1.8 FOSC = 16MHz HFINTOSC mode — 1.6 2.0 mA 3.0 D019 — 1.0 1.3 mA 1.8 FOSC = 16MHz — 1.6 2.0 mA 3.0 HFINTOSC mode (Note 5) — 1.8 2.2 mA 5.0 D020 — 3.0 3.9 mA 3.0 FOSC = 32MHz HFINTOSC mode — 3.7 4.6 mA 3.6 D020 — 3.0 3.9 mA 3.0 FOSC = 32MHz — 3.3 4.1 mA 5.0 HFINTOSC mode D021 — 200 300 A 1.8 FOSC = 4MHz EXTRC mode (Note 3) — 350 490 A 3.0 D021 — 210 300 A 1.8 FOSC = 4MHz — 370 500 A 3.0 EXTRC mode (Note 3, Note 5) — 460 590 A 5.0 D022 — 3.0 3.9 mA 3.0 FOSC = 32MHz HS Oscillator mode (Note 6) — 3.7 4.6 mA 3.6 D022 — 3.0 3.9 mA 3.0 FOSC = 32MHz — 3.3 4.1 mA 5.0 HS Oscillator mode (Note 5, Note 6) Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k 4: FVR and BOR are disabled. 5: 0.1F capacitor on VCAP (RA0). 6: 8 MHz crystal oscillator with 4x PLL enabled. DS40001574C-page 384  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 30.3 DC Characteristics: PIC16(L)F1938/39-I/E (Power-Down) Standard Operating Conditions (unless otherwise stated) PIC16LF1938/39 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1938/39 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D023 Base IPD — 0.06 1.0 8.0 A 1.8 WDT, BOR, FVR, and T1OSC — 0.08 2.0 9.0 A 3.0 disabled, all Peripherals Inactive D023 Base IPD — 15 35 45 A 1.8 WDT, BOR, FVR, and T1OSC — 18 40 50 A 3.0 disabled, all Peripherals Inactive — 19 45 55 A 5.0 D024 — 0.5 6.0 9.0 A 1.8 LPWDT Current (Note 1) — 0.8 7.0 10 A 3.0 D024 — 16 35 45 A 1.8 LPWDT Current (Note 1) — 19 40 50 A 3.0 — 20 45 55 A 5.0 D025 — 8.5 23 30 A 1.8 FVR current — 8.5 26 33 A 3.0 D025 — 32 55 70 A 1.8 FVR current (Note 4) — 39 72 80 A 3.0 — 70 100 110 A 5.0 D026 — 7.5 25 28 A 3.0 BOR Current (Note 1) D026 — 34 57 67 A 3.0 BOR Current (Note 1, Note 4) — 67 120 130 A 5.0 D027 — 0.6 5.0 9.0 A 1.8 T1OSC Current (Note 1) — 1.8 6.0 12 A 3.0 D027 — 16 45 50 A 1.8 T1OSC Current (Note 1) — 21 50 55 A 3.0 — 25 55 65 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: A/D oscillator source is FRC. 4: 0.1F capacitor on VCAP (RA0).  2011-2013 Microchip Technology Inc. DS40001574C-page 385

PIC16(L)F1938/9 30.3 DC Characteristics: PIC16(L)F1938/39-I/E (Power-Down) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF1938/39 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1938/39 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D028 — 0.1 5.0 8.0 A 1.8 A/D Current (Note 1, Note 3), no — 0.1 6.0 9.0 A 3.0 conversion in progress D028 — 16 35 45 A 1.8 A/D Current (Note 1, Note 3), no — 21 40 50 A 3.0 conversion in progress — 25 50 60 A 5.0 D028A — 250 — — A 1.8 A/D Current (Note 1, Note 3), — 250 — — A 3.0 conversion in progress D028A — 280 — — A 1.8 A/D Current (Note 1, Note 3), — 280 — — A 3.0 conversion in progress — 280 — — A 5.0 D029* — 3.5 — — A 1.8 Cap Sense, Low-Power mode — 7.0 — — A 3.0 D029* — 17 — — A 1.8 Cap Sense, Low-Power mode — 21 — — A 3.0 — 22 — — A 5.0 D030 — 1 — — A 3.0 LCD Bias Ladder, Low power — 10 — — A 3.0 LCD Bias Ladder, Medium power — 75 — — A 3.0 LCD Bias Ladder, High power D030 — 1 — — A 5.0 LCD Bias Ladder, Low power — 10 — — A 5.0 LCD Bias Ladder, Medium power — 75 — — A 5.0 LCD Bias Ladder, High power D031 — 7.6 22 25 A 1.8 Comparator, Low-Power mode — 8.0 23 27 A 3.0 D031 — 24 50 60 A 1.8 Comparator, Low-Power mode — 26 70 80 A 3.0 — 28 75 85 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: A/D oscillator source is FRC. 4: 0.1F capacitor on VCAP (RA0). DS40001574C-page 386  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 30.4 DC Characteristics: PIC16(L)F1938/39-I/E Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature-40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage I/O PORT: D032 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V D032A — — 0.15VDD V 1.8V  VDD  4.5V D033 with Schmitt Trigger buffer — — 0.2VDD V 2.0V  VDD  5.5V with I2C™ levels — — 0.3VDD V with SMBus levels — — 0.8 V 2.7V  VDD  5.5V D034 MCLR, OSC1 (RC mode)(1) — — 0.2VDD V D034A OSC1 (HS mode) — — 0.3VDD V VIH Input High Voltage I/O ports: D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V D040A 0.25VDD + — — V 1.8V  VDD  4.5V 0.8 D041 with Schmitt Trigger buffer 0.8VDD — — V 2.0V  VDD  5.5V with I2C™ levels 0.7VDD — — V with SMBus levels 2.1 — — V 2.7V  VDD  5.5V D042 MCLR 0.8VDD — — V D043A OSC1 (HS mode) 0.7VDD — — V D043B OSC1 (RC mode) 0.9VDD — — V (Note 1) VDD > 2.0V IIL Input Leakage Current(2) D060 I/O ports — ± 5 ± 125 nA VSS  VPIN  VDD, Pin at high- impedance @ 85°C ± 5 ± 1000 nA 125°C D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD @ 85°C IPUR Weak Pull-up Current D070* 25 100 200 VDD = 3.3V, VPIN = VSS 25 140 300 A VDD = 5.0V, VPIN = VSS VOL Output Low Voltage(4) D080 I/O ports IOL = 8mA, VDD = 5V — — 0.6 V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V VOH Output High Voltage(4) D090 I/O ports IOH = 3.5mA, VDD = 5V VDD - 0.7 — — V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode.  2011-2013 Microchip Technology Inc. DS40001574C-page 387

PIC16(L)F1938/9 30.4 DC Characteristics: PIC16(L)F1938/39-I/E (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature-40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF VCAP Capacitor Charging D102 Charging current — 200 — A D102A Source/sink capability when — 0.0 — mA charging complete * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode. DS40001574C-page 388  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 30.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP/RE3 pin 8.0 — 9.0 V (Note 3, Note 4) D111 IDDP Supply Current during — — 10 mA Programming D112 VDD for Bulk Erase 2.7 — VDD V max. D113 VPEW VDD for Write or Row Erase VDD — VDD V min. max. D114 IPPPGM Current on MCLR/VPP during Erase/ — 1.0 — mA Write D115 IDDPGM Current on VDD during Erase/Write — 5.0 — mA Data EEPROM Memory D116 ED Byte Endurance 100K — — E/W -40C to +85C D117 VDRW VDD for Read/Write VDD — VDD V min. max. D118 TDEW Erase/Write Cycle Time — 4.0 5.0 ms D119 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D120 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +85°C Cycles before Refresh(2) Program Flash Memory D121 EP Cell Endurance 10K — — E/W -40C to +85C (Note 1) D122 VPRW VDD for Read/Write VDD — VDD V min. max. D123 TIW Self-timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Refer to Section11.2 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP voltage must be placed between the MPLAB ICD 2 and target system when programming or debugging with the MPLAB ICD 2.  2011-2013 Microchip Technology Inc. DS40001574C-page 389

PIC16(L)F1938/9 30.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance Junction to Ambient 60.0 C/W 28-pin SPDIP package 69.7 C/W 28-pin SOIC package 71.0 C/W 28-pin SSOP package 27.5 C/W 28-pin UQFN 4x4mm package 31.1 C/W 28-pin QFN 6x6mm package 47.2 C/W 40-pin PDIP package 49.8 C/W 44-pin TQFP package 29.0 C/W 44-pin QFN 8x8mm package TH02 JC Thermal Resistance Junction to Case 29.0 C/W 28-pin SPDIP package 18.9 C/W 28-pin SOIC package 24.0 C/W 28-pin SSOP package 24.0 C/W 28-pin UQFN 4x4mm package 5.0 C/W 28-pin QFN 6x6mm package 24.7 C/W 40-pin PDIP package 26.7 C/W 44-pin TQFP package 2.0 C/W 44-pin QFN 8x8mm package TH03 TJMAX Maximum Junction Temperature 150 C TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature 3: TJ = Junction Temperature DS40001574C-page 390  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 30.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O PORT t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 30-5: LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins, 15 pF for OSC2 output  2011-2013 Microchip Technology Inc. DS40001574C-page 391

PIC16(L)F1938/9 30.8 AC Characteristics: PIC16(L)F1938/39-I/E FIGURE 30-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 30-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz EC Oscillator mode (low) DC — 4 MHz EC Oscillator mode (medium) DC — 20 MHz EC Oscillator mode (high) Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 4 MHz HS Oscillator mode 1 — 20 MHz HS Oscillator mode, VDD > 2.7V DC — 4 MHz RC Oscillator mode, VDD > 2.0V OS02 TOSC External CLKIN Period(1) 27 —  s LP Oscillator mode 250 —  ns XT Oscillator mode 50 —  ns HS Oscillator mode 50 —  ns EC Oscillator mode Oscillator Period(1) — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC OS04* TosH, External CLKIN High, 2 — — s LP oscillator TosL External CLKIN Low 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TosR, External CLKIN Rise, 0 —  ns LP oscillator TosF External CLKIN Fall 0 —  ns XT oscillator 0 —  ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. DS40001574C-page 392  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 30-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Freq. Sym. Characteristic Min. Typ† Max. Units Conditions No. Tolerance OS08 HFOSC Internal Calibrated HFINTOSC ±2% — 16.0 — MHz 0°C  TA  +60°C, VDD 2.5V Frequency(1) ±3% — 16.0 — MHz 60°C TA 85°C, VDD 2.5V ±5% — 16.0 — MHz -40°C  TA  +125°C OS08A MFOSC Internal Calibrated MFINTOSC ±2% — 500 — kHz 0°C  TA  +60°C, VDD 2.5V Frequency(1) ±3% — 500 — kHz 60°C TA 85°C, VDD 2.5V ±5% — 500 — kHz -40°C  TA  +125°C OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz -40°C  TA  +125°C OS10* TIOSC ST HFINTOSC — — 3.2 8 s Wake-up from Sleep Start-up Time MFINTOSC — — 24 35 s Wake-up from Sleep Start-up Time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. TABLE 30-3: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 8 MHz F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz F12 TRC PLL Start-up Time (Lock Time) — — 2 ms F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% % * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19  2011-2013 Microchip Technology Inc. DS40001574C-page 393

PIC16(L)F1938/9 TABLE 30-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS11 TosH2ckL FOSC to CLKOUT (1) — — 70 ns VDD = 3.3-5.0V OS12 TosH2ckH FOSC to CLKOUT (1) — — 72 ns VDD = 3.3-5.0V OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3-5.0V OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns VDD = 3.3-5.0V (I/O in hold time) OS17 TioV2osH Port input valid to Fosc(Q2 cycle) 20 — — ns (I/O in setup time) OS18 TioR Port output rise time — 40 72 ns VDD = 1.8V — 15 32 VDD = 3.3-5.0V OS19 TioF Port output fall time — 28 55 ns VDD = 1.8V — 15 30 VDD = 3.3-5.0V OS20* Tinp INT pin input high or low time 25 — — ns OS21* Tioc Interrupt-on-change new input level 25 — — ns time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. FIGURE 30-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. DS40001574C-page 394  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2ms delay if PWRTE = 0.  2011-2013 Microchip Technology Inc. DS40001574C-page 395

PIC16(L)F1938/9 TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDTLP Low-Power Watchdog Timer 10 16 27 ms VDD = 3.3V-5V Time-out Period 1:16 Prescaler used 32 TOST Oscillator Start-up Timer Period(1) — 1024 — Tosc 33* TPWRT Power-up Timer Period, PWRTE=0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low — — 2.0 s or Watchdog Timer Reset 35 VBOR Brown-out Reset Voltage(2) 2.55 2.7 2.85 V BORV = 0 1.80 1.9 2.11 V BORV = 1 36* VHYST Brown-out Reset Hysteresis 20 35 60 mV -40°C to +85°C 37* TBORDC Brown-out Reset DC Response 1 3 35 s VDD  VBOR Time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. 2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. FIGURE 30-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 DS40001574C-page 396  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 30-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value Period 30 or TCY + 40 (1, 2, 4, 8) N Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range 32.4 32.768 33.1 kHz (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync Increment mode * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure30-5 for load conditions. TABLE 30-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. CC01* TccL CCPx Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCPx Input Period 3TCY + 40 — — ns N = prescale value (1, 4 or 16) N * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2011-2013 Microchip Technology Inc. DS40001574C-page 397

PIC16(L)F1938/9 TABLE 30-8: PIC16(L)F1938/39 A/D CONVERTER (ADC) CHARACTERISTICS:(1),(2),(3) Standard Operating Conditions (unless otherwise stated) Operating temperature Tested at 25°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — ±1 ±1.7 LSb VREF = 3.0V AD03 EDL Differential Error — ±1 ±1 LSb No missing codes VREF = 3.0V AD04 EOFF Offset Error — ±1 ±2.5 LSb VREF = 3.0V AD05 EGN Gain Error — ±1 ±2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage(4) 1.8 — VDD V VREF = (VREF+ minus VREF-) AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01F capacitor is Analog Voltage Source present on input pin. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. 4: ADC Reference Voltage (Ref+) is the selected reference input, VREF+ pin, VDD pin or the FVR Buffer1. When the FVR is selected as the reference input, the FVR Buffer1 output selection must be 2.048V or 4.096V, (ADFVR<1:0> = 1x). TABLE 30-9: PIC16(L)F1938/39 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD130* TAD A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal RC Oscillator 1.0 2.5 6.0 s ADCS<1:0> = 11 (ADRC mode) Period AD131 TCNV Conversion Time (not including — 11 — TAD Set GO/DONE bit to conversion Acquisition Time)(1) complete AD132* TACQ Acquisition Time — 5.0 — s * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. DS40001574C-page 398  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 30-12: PIC16(L)F1938/39 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 (TOSC/2(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. FIGURE 30-13: PIC16(L)F1938/39 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.  2011-2013 Microchip Technology Inc. DS40001574C-page 399

PIC16(L)F1938/9 TABLE 30-10: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param Sym. Characteristics Min. Typ. Max. Units Comments No. CM01 VIOFF Input Offset Voltage — ±7.5 ±60 mV High-Power mode, VICM = VDD/2 CM02 VICM Input Common Mode Voltage 0 — VDD V CM03 CMRR Common Mode Rejection Ratio — 50 — dB CM04A Response Time Rising Edge — 400 800 ns High-Power mode CM04B Response Time Falling Edge — 200 400 ns High-Power mode TRESP CM04C Response Time Rising Edge — 1200 — ns Low-Power mode CM04D Response Time Falling Edge — 550 — ns Low-Power mode CM05 TMC2OV Comparator Mode Change to — — 10 s Output Valid* CM06 CHYSTER Comparator Hysteresis — 45 — mV Hysteresis ON * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. 2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled. TABLE 30-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions: 2.5V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param Sym. Characteristics Min. Typ. Max. Units Comments No. DAC01* CLSB Step Size — VDD/32 — V DAC02* CACC Absolute Accuracy — —  1/2 LSb DAC03* CR Unit Resistor Value (R) — 5000 —  DAC04* CST Settling Time(1) — — 10 s * These parameters are characterized but not tested. Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’. FIGURE 30-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US120 US122 Note: Refer to Figure30-5 for load conditions. DS40001574C-page 400  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 30-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. US120 TCKH2DTV SYNC XMIT (Master and Slave) 3.0-5.5V — 80 ns Clock high to data-out valid 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time 3.0-5.5V — 45 ns (Master mode) 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns FIGURE 30-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure30-5 for load conditions. TABLE 30-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK  (DT hold time) 10 — ns US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns  2011-2013 Microchip Technology Inc. DS40001574C-page 401

PIC16(L)F1938/9 FIGURE 30-16: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SCK (CKP = 1) SP79 SP78 SP80 SDO MSb bit 6 - - - - - -1 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure30-5 for load conditions. FIGURE 30-17: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SP78 SDO MSb bit 6 - - - - - -1 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure30-5 for load conditions. DS40001574C-page 402  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 30-18: SPI SLAVE MODE TIMING (CKE=0) SS SP70 SCK SP83 (CKP = 0) SP71 SP72 SP78 SP79 SCK (CKP = 1) SP79 SP78 SP80 SDO MSb bit 6 - - - - - -1 LSb SP75, SP76 SP77 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure30-5 for load conditions. FIGURE 30-19: SPI SLAVE MODE TIMING (CKE=1) SP82 SS SP70 SCK SP83 (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure30-5 for load conditions.  2011-2013 Microchip Technology Inc. DS40001574C-page 403

PIC16(L)F1938/9 TABLE 30-14: SPI MODE REQUIREMENTS Param Symbol Characteristic Min. Typ† Max. Units Conditions No. SP70* TSSL2SCH, SS to SCK or SCK input TCY — — ns TSSL2SCL SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns SP73* TDIV2SCH, Setup time of SDI data input to SCK edge 100 — — ns TDIV2SCL SP74* TSCH2DIL, Hold time of SDI data input to SCK edge 100 — — ns TSCL2DIL SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns 1.8-5.5V — 25 50 ns SP76* TDOF SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time 3.0-5.5V — 10 25 ns (Master mode) 1.8-5.5V — 25 50 ns SP79* TSCF SCK output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, SDO data output valid after 3.0-5.5V — — 50 ns TSCL2DOV SCK edge 1.8-5.5V — — 145 ns SP81* TDOV2SCH, SDO data output setup to SCK edge Tcy — — ns TDOV2SCL SP82* TSSL2DOV SDO data output valid after SS edge — — 50 ns SP83* TSCH2SSH, SS after SCK edge 1.5TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-20: I2C™ BUS START/STOP BITS TIMING SCL SP91 SP93 SP90 SP92 SDA Start Stop Condition Condition Note: Refer to Figure30-5 for load conditions. DS40001574C-page 404  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 30-15: I2C™ BUS START/STOP BITS REQUIREMENTS Param Symbol Characteristic Min. Typ Max. Units Conditions No. SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — Start condition SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first Hold time 400 kHz mode 600 — — clock pulse is generated SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. FIGURE 30-21: I2C™ BUS DATA TIMING SP103 SP100 SP102 SP101 SCL SP90 SP106 SP107 SP91 SP92 SDA In SP110 SP109 SP109 SDA Out Note: Refer to Figure30-5 for load conditions.  2011-2013 Microchip Technology Inc. DS40001574C-page 405

PIC16(L)F1938/9 TABLE 30-16: I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP module 1.5TCY — SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP module 1.5TCY — SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF SP103* TF SDA and SCL fall 100 kHz mode — 250 ns time 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from 10-400 pF SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s SP107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2) time 400 kHz mode 100 — ns SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start SP111 CB Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT=1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS40001574C-page 406  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 TABLE 30-17: CAP SENSE OSCILLATOR SPECIFICATIONS Param. Symbol Characteristic Min. Typ† Max. Units Conditions No. CS01* ISRC Current Source High — -8 — A Medium — -1.5 — A Low — -0.3 — A CS02* ISNK Current Sink High — 7.5 — A Medium — 1.5 — A Low — 0.25 — A CS03* VCTH Cap Threshold — 0.8 — V CS04* VCTL Cap Threshold — 0.4 — V CS05* VCHYST Cap Hysteresis High — 525 — mV (VCTH-VCTL) Medium — 375 — mV Low — 300 — mV * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-22: CAP SENSE OSCILLATOR VCTH VCTL ISRC ISNK Enabled Enabled  2011-2013 Microchip Technology Inc. DS40001574C-page 407

PIC16(L)F1938/9 NOTES: DS40001574C-page 408  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean+3) or (mean-3) respectively, where  is a standard deviation, over each temperature range.  2011-2013 Microchip Technology Inc. DS40001574C-page 409

PIC16(L)F1938/9 FIGURE 31-1: IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16LF1938/9 ONLY 14 Max: 85°C + 3(cid:305) Max. 12 Typical: 25°C 10 Typical 8 A) μ ( D D 6 I 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-2: IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16F1938/9 ONLY 60 Max: 85°C + 3(cid:305) 50 Max. Typical: 25°C 40 Typical A) (μ 30 D D I 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001574C-page 410  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1938/9 ONLY 450 400 Typical: 25°C 4 MHz XT 350 300 4 MHz EXTRC A) 250 μ ( D 200 D I 150 1 MHz XT 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1938/9 ONLY 450 400 Max: 85°C + 3(cid:305) 4 MHz XT 350 300 A) 250 4 MHz EXTRC μ ( D D 200 I 150 1 MHz XT 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 411

PIC16(L)F1938/9 FIGURE 31-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1938/9 ONLY 600 500 Typical: 25°C 4 MHz XT 400 4 MHz EXTRC A) μ 300 ( D D 1 MHz XT I 200 100 1 MHz EXTRC 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-6: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1938/9 ONLY 600 4 MHz XT Max: 85°C + 3(cid:305) 500 4 MHz EXTRC 400 A) 300 μ ( 1 MHz XT D D I 200 1 MHz EXTRC 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001574C-page 412  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-7: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz, PIC16LF1938/9 ONLY 12 Max: 85°C + 3(cid:305) 10 Typical: 25°C Max. 8 Typical A) μ 6 ( D D I 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-8: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz, PIC16F1938/9 ONLY 50 45 Max. 40 35 Typical A) 30 μ ( 25 D D I 20 15 Max: 85°C + 3(cid:305) 10 Typical: 25°C 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 413

PIC16(L)F1938/9 FIGURE 31-9: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz, PIC16LF1938/9 ONLY 60 Max. Max: 85°C + 3(cid:305) 50 Typical: 25°C 40 A) Typical μ 30 ( D D I 20 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-10: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz, PIC16F1938/9 ONLY 90 Max. 80 70 60 Typical A) μ 50 ( D D I 40 30 20 Max: 85°C + 3(cid:305) 10 Typical: 25°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001574C-page 414  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-11: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16LF1938/9 ONLY 450 400 Typical: 25°C 4 MHz 350 300 A) 250 μ ( D 200 D I 150 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-12: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16LF1938/9 ONLY 500 450 Max: 85°C + 3(cid:305) 4 MHz 400 350 300 A) (μ 250 D D I 200 150 1 MHz 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 415

PIC16(L)F1938/9 FIGURE 31-13: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16F1938/9 ONLY 500 450 Typical: 25°C 4 MHz 400 350 300 A) μ ( 250 D D I 200 1 MHz 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-14: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16F1938/9 ONLY 600 500 Max: 85°C + 3(cid:305) 4 MHz 400 A) μ ( 300 D D I 200 1 MHz 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001574C-page 416  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-15: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16LF1938/9 ONLY 3.5 3.0 Typical: 25°C 32 MHz (PLL) 2.5 A) 2.0 m ( DD 1.5 16 MHz I 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-16: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16LF1938/9 ONLY 4.0 3.5 Max: 85°C + 3(cid:305) 32 MHz (PLL) 3.0 2.5 A) m 2.0 ( D D 16 MHz I 1.5 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 417

PIC16(L)F1938/9 FIGURE 31-17: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16F1938/9 ONLY 3.5 32 MHz (PLL) 3.0 Typical: 25°C 2.5 2.0 A) m 16 MHz ( D 1.5 D I 8 MHz 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-18: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16F1938/9 ONLY 3.5 32 MHz (PLL) 3.0 Max: 85°C + 3(cid:305) 2.5 A) 2.0 16 MHz m ( D 1.5 D I 8 MHz 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001574C-page 418  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-19: IDD, LFINTOSC, FOSC = 31 kHz, PIC16LF1938/9 ONLY 12 Max: 85°C + 3(cid:305) 10 Typical: 25°C Max. 8 A) Typical μ ( D 6 D I 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-20: IDD, LFINTOSC, FOSC = 31 kHz, PIC16F1938/9 ONLY 50 45 Max. 40 35 Typical A) μ 30 ( D ID 25 20 15 Max: 85°C + 3(cid:305) 10 Typical: 25°C 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 419

PIC16(L)F1938/9 FIGURE 31-21: IDD, MFINTOSC, FOSC = 500 kHz, PIC16LF1938/9 ONLY 180 Max: 85°C + 3(cid:305) 160 Max. Typical: 25°C 140 120 Typical A) 100 μ ( D 80 D I 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-22: IDD, MFINTOSC, FOSC = 500 kHz, PIC16F1938/9 ONLY 300 Max: 85°C + 3(cid:305) Max. 250 Typical: 25°C 200 A) Typical (μ 150 D D I 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001574C-page 420  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-23: IDD TYPICAL, HFINTOSC, PIC16LF1938/9 ONLY 4.0 3.5 Typical: 25°C 32 MHz (PLL) 3.0 2.5 A) m ( 2.0 16 MHz D D I 1.5 8 MHz 1.0 0.5 4 MHz 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-24: IDD MAXIMUM, HFINTOSC, PIC16LF1938/9 ONLY 4.5 4.0 Max: 85°C + 3(cid:305) 32 MHz (PLL) 3.5 3.0 A) 2.5 m ( DD 2.0 16 MHz I 1.5 8 MHz 1.0 0.5 4 MHz 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 421

PIC16(L)F1938/9 FIGURE 31-25: IDD TYPICAL, HFINTOSC, PIC16F1938/9 ONLY 4.0 3.5 Typical: 25°C 32 MHz (PLL) 3.0 2.5 A) m 2.0 16 MHz ( D D I 1.5 8 MHz 1.0 0.5 4 MHz 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-26: IDD MAXIMUM, HFINTOSC, PIC16F1938/9 ONLY 4.0 32 MHz (PLL) 3.5 Max: 85°C + 3(cid:305) 3.0 2.5 A) m 2.0 16 MHz ( D D I 1.5 8 MHz 1.0 0.5 4 MHz 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001574C-page 422  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-27: IDD TYPICAL, HS OSCILLATOR, PIC16LF1938/9 ONLY 4.5 4.0 Typical: 25°C 32 MHz (PLL) 3.5 3.0 A) 2.5 m 20 MHz ( 2.0 D D I 1.5 8 MHz 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-28: IDD MAXIMUM, HS OSCILLATOR, PIC16LF1938/9 ONLY 5.0 4.5 Max: 85°C + 3(cid:305) 32 MHz (PLL) 4.0 3.5 3.0 A) 2.5 20 MHz m ( DD 2.0 I 1.5 8 MHz 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 423

PIC16(L)F1938/9 FIGURE 31-29: IDD TYPICAL, HS OSCILLATOR, PIC16F1938/9 ONLY 3.5 32 MHz (PLL) 3.0 Typical: 25°C 2.5 20 MHz 2.0 A) m ( 1.5 D D I 8 MHz 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-30: IDD MAXIMUM, HS OSCILLATOR, PIC16F1938/9 ONLY 4.0 3.5 Max: 85°C + 3(cid:305) 32 MHz (PLL) 3.0 2.5 20 MHz A) m 2.0 ( D D I 1.5 8 MHz 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001574C-page 424  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-31: IPD BASE, LOW-POWER SLEEP MODE, PIC16LF1938/9 ONLY 11,,220000 Max. 1,000 Max: 85°C + 3(cid:305) Typical: 25°C 800 A)A nn (( 660000 DD PP II 400 200 Typical 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-32: IPD BASE, LOW-POWER SLEEP MODE, PIC16F1938/9 ONLY 4455 MMax: 8855°°CC ++ 33(cid:305) 40 Max. Typical: 25°C 35 30 Typical A)A 2255 nn (( DD PP 2200 II 15 10 5 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 425

PIC16(L)F1938/9 FIGURE 31-33: IPD, WATCHDOG TIMER (WDT), PIC16LF1938/9 ONLY 22..55 2.0 Max: 85°C + 3(cid:305) Typical: 25°C Max. 1.5 A)A) μμ d (d ( pp 11.00 I Typical 0.5 00..00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-34: IPD, WATCHDOG TIMER (WDT), PIC16F1938/9 ONLY 4455 40 Max. 35 30 Typical A)A 2255 μμ (( DD PP 2200 II 15 10 Max: 85°C + 3(cid:305) 5 Typical: 25°C 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001574C-page 426  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FpIG,URE 31-35: IPD, FIXED VOLTAG(E REF)ERENCE (FVR), PIC16LF1938/9 ONLY 1144 MMax. 12 10 Typical 8 A)A μμ (( DD 66 PP II 4 Max: 85°C + 3(cid:305) 2 Typical: 25°C 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-36: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1938/9 ONLY 112200 Max. 100 Typical 80 A)A μμ (( 6600 DD PP II 40 Max: 85°C + 3(cid:305) 20 Typical: 25°C 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 427

PIC16(L)F1938/9 FIGURE 31-37: IPD, BROWN-OUT RESET (BOR), BORV = 0, PIC16LF1938/9 ONLY 1122 MMaaxx.. 10 Typical 8 A)A) 66 μμ (( DD P I 4 Max: 85°C + 3(cid:305) 2 Typical: 25°C 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-38: IPD, BROWN-OUT RESET (BOR), BORV = 0, PIC16F1938/9 ONLY 5500 4455 Max. 40 35 Typical 30 A)A) 2255 μμ (( DD PP 2200 I 15 Max: 85°C + 3(cid:305) 10 Typical: 25°C 5 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001574C-page 428  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FpIGURE 31-39: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16LF1938/9 ONLY 1144 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) 12 Typical: 25°C 10 8 Max. A)A μμ (( DD 66 PP II Typical 4 2 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VVDD((VV)) FIGURE 31-40: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16F1938/9 ONLY 6600 Max: 85°C + 3(cid:305) 50 Typical: 25°C Max. 40 A)A Typical μμ (( 3300 DD PP II 20 10 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 429

PIC16(L)F1938/9 FIGURE 31-41: IPD, CAPACITIVE SENSING (CPS) MODULE, LOW-CURRENT RANGE (CPSRM = 0, CPSRNG = 01), PIC16LF1938/9 ONLY 88 7 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) MMax. Typical: 25°C 6 5 A)A TTyyppiiccaall μμ 44 (( DD PP II 3 2 1 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-42: IPD, CAPACITIVE SENSING (CPS) MODULE, LOW-CURRENT RANGE (CPSRM = 0, CPSRNG = 01), PIC16F1938/9 ONLY 4455 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) 40 Typical: 25°C Max. 35 30 Typical A)A 2255 μμ (( DD PP 2200 II 15 10 5 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001574C-page 430  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-43: IPD, CAPACITIVE SENSING (CPS) MODULE, MEDIUM-CURRENT RANGE (CPSRM = 0, CPSRNG = 10), PIC16LF1938/9 ONLY 1166 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) 14 Max. Typical: 25°C 12 10 A)A μμ 88 TTyyppiiccaall (( DD PP II 6 4 2 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-44: IPD, CAPACITIVE SENSING (CPS) MODULE, MEDIUM-CURRENT RANGE (CPSRM = 0, CPSRNG = 10), PIC16F1938/9 ONLY 6600 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) Typical: 25°C 50 Max. 40 A)A Tyyppical μμ (( 3300 DD PP II 20 10 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 431

PIC16(L)F1938/9 FIGURE 31-45: IPD, CAPACITIVE SENSING (CPS) MODULE, HIGH-CURRENT RANGE (CPSRM = 0, CPSRNG = 11), PIC16LF1938/9 ONLY 7700 Max: 85°C + 3(cid:305) 60 Typical: 25°C Max. 50 40 A)A TTyyppiiccaall μμ (( PDPD 3300 II 20 10 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-46: IPD, CAPACITIVE SENSING (CPS) MODULE, HIGH-CURRENT RANGE (CPSRM = 0, CPSRNG = 11), PIC16F1938/9 ONLY 114400 120 Max: 85°C + 3(cid:305) Typical: 25°C Max. 100 A)A 8800 μμ TTyyppiiccaall (( DD IIPP 6600 40 20 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001574C-page 432  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-47: IPD, COMPARATOR, LOW-POWER MODE, (CxSP = 0), PIC16LF1938/9 ONLY 3300 MMaaxx. 25 20 Typical A) μ (( DD 1155 PP II 10 5 Max: 85°C + 3(cid:305) Typical: 25°C 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VVDD((VV)) FIGURE 31-48: IPD, COMPARATOR, LOW-POWER MODE, (CxSP = 0), PIC16F1938/9 ONLY 6600 50 Max. 40 Typical A)A ((μμ 3300 DD PP II 20 Max: 85°C + 3(cid:305) 10 Typical: 25°C 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 433

PIC16(L)F1938/9 FIGURE 31-49: IPD, COMPARATOR, NORMAL-POWER MODE, (CxSP = 1), PIC16LF1938/9 ONLY 6600 50 Max. 40 A)A Typical ((μμ 3300 DD PP II 20 10 Max: 85°C + 3(cid:305) Typical: 25°C 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-50: IPD, COMPARATOR, NORMAL-POWER MODE, (CxSP = 1), PIC16F1938/9 ONLY 8800 70 MMax. 60 50 Typical A)A) μμ 4400 (( DD PP II 3300 20 Max: 85°C + 3(cid:305) 10 Typical: 25°C 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001574C-page 434  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-51: VOH VS. IOH OVER TEMPERATURE, VDD = 5.0V, PIC16F1938/9 ONLY 6 Max: 125°C+ 3(cid:305) Typical: 25°C 5 Min: -40°C-3(cid:305) 4 Min. (-40°C) V) (H 3 O V 2 Typical (25°C) 1 Max. (125°C) 0 -30 -25 -20 -15 -10 -5 0 IOH(mA) FIGURE 31-52: VOL VS. IOL OVER TEMPERATURE, VDD = 5.0V, PIC16F1938/9 ONLY 5 Max: 125°C+ 3(cid:305) 4 Typical: 25°C Min: -40°C-3(cid:305) 3 V) ( L O Max. (125°C) Typical (25°C) Min. (-40°C) V 2 1 0 0 10 20 30 40 50 60 70 80 IOL(mA)  2011-2013 Microchip Technology Inc. DS40001574C-page 435

PIC16(L)F1938/9 FIGURE 31-53: VOH VS. IOH OVER TEMPERATURE, VDD = 3.0V 3.5 Max: 125°C+ 3(cid:305) 3.0 Typical: 25°C Min: -40°C-3(cid:305) 2.5 V) 2.0 ( H O V 1.5 Min. (-40°C) Typical (25°C) Max. (125°C) 1.0 0.5 0.0 -14 -12 -10 -8 -6 -4 -2 0 IOH(mA) FIGURE 31-54: VOL VS. IOL OVER TEMPERATURE, VDD = 3.0V 3.0 Max: 125°C+ 3(cid:305) 2.5 Typical: 25°C Min: -40°C-3(cid:305) 2.0 Max. (125°C) Typical (25°C) Min. (-40°C) V) ( 1.5 L O V 1.0 0.5 0.0 0 5 10 15 20 25 30 IOL(mA) DS40001574C-page 436  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-55: VOH VS. IOH OVER TEMPERATURE, VDD = 1.8V 2.0 1.8 Max: 125°C+ 3(cid:305) Typical: 25°C 1.6 Min: -40°C-3(cid:305) 1.4 1.2 V) (H 1.0 O V 0.8 Min. (-40°C) Typical (25°C) Max. (125°C) 0.6 0.4 0.2 0.0 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IOH(mA) FIGURE 31-56: VOL VS. IOL OVER TEMPERATURE, VDD = 1.8V 1.8 1.6 Max: 125°C+ 3(cid:305) Typical: 25°C 1.4 Min: -40°C-3(cid:305) 1.2 V)1.0 (L Max. (125°C) Typical (25°C) Min. (-40°C) O V0.8 0.6 0.4 0.2 0.0 0 1 2 3 4 5 6 7 8 9 10 IOL(mA)  2011-2013 Microchip Technology Inc. DS40001574C-page 437

PIC16(L)F1938/9 FIGURE 31-57: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 1.64 Typical ) 1.62 V ge ( 1.60 Min. a t ol 1.58 V 1.56 1.54 Max: Typical + 3(cid:305) Typical: 25°C 1.52 Min: Typical -3(cid:305) 1.50 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-58: POR REARM VOLTAGE, PIC16F1938/9 ONLY 1.54 1.52 Max: Typical + 3(cid:305) Typical: 25°C 1.50 Min: Typical -3(cid:305) Max. 1.48 ) 1.46 V e ( g 1.44 ta Typical ol 1.42 V 1.40 1.38 Min. 1.36 1.34 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) DS40001574C-page 438  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-59: BROWN-OUT RESET VOLTAGE, BORV = 1 2.10 Max: Typical + 3(cid:305) 2.05 Min: Typical -3(cid:305) 2.00 Max. 1.95 ) V ge ( 1.90 a t ol V 1.85 Min. 1.80 1.75 1.70 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-60: BROWN-OUT RESET HYSTERESIS, BORV = 1 70 Max. 60 50 Typical ) V 40 m e ( g a 30 t ol V Min. 20 Max: Typical + 3(cid:305) 10 Typical: 25°C Min: Typical -3(cid:305) 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C)  2011-2013 Microchip Technology Inc. DS40001574C-page 439

PIC16(L)F1938/9 FIGURE 31-61: BROWN-OUT RESET VOLTAGE, BORV = 0 2.90 2.85 Max: Typical + 3(cid:305) Min: Typical -3(cid:305) 2.80 Max. 2.75 ) 2.70 V ge ( 2.65 ta Min. ol 2.60 V 2.55 2.50 2.45 2.40 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-62: BROWN-OUT RESET HYSTERESIS, BORV = 0 90 80 Max. 70 60 ) V m 50 Typical e ( g 40 a t ol V 30 20 Max: Typical + 3(cid:305) Min. Typical: 25°C 10 Min: Typical -3(cid:305) 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) DS40001574C-page 440  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-63: WDT TIME-OUT PERIOD 24 Max: Typical + 3(cid:305)(-40°C to +125°C) 22 Typical: statistical mean @ 25°C Max. Min: Typical -3(cid:305)(-40°C to +125°C) 20 ) ms 18 Typical e ( m 16 Ti 14 Min. 12 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-64: PWRT PERIOD 110 100 Max. 90 ) s 80 Typical m e ( m 70 Ti Min. 60 Max: Typical + 3(cid:305)(-40°C to +125°C) 50 Typical: statistical mean @ 25°C Min: Typical -3(cid:305)(-40°C to +125°C) 40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 441

PIC16(L)F1938/9 FIGURE 31-65: COMPARATOR HYSTERESIS, NORMAL-POWER MODE (CxSP = 1, CxHYS = 1) 100 90 80 Max. 70 ) V m 60 ( s si 50 e Typical r e st 40 Max: Typical + 3(cid:305) y Typical: 25°C H 30 Min: Typical -3(cid:305) 20 Min. 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-66: COMPARATOR HYSTERESIS, LOW-POWER MODE (CxSP = 0, CxHYS = 1) 25 Max: Typical + 3(cid:305) 20 Typical: 25°C Min: Typical -3(cid:305) ) V m 15 ( s Max. si e r e t 10 s y H Typical 5 Min. 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001574C-page 442  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 FIGURE 31-67: COMPARATOR RESPONSE TIME, NORMAL-POWER MODE, (CxSP = 1) 400 350 300 250 ) s Max. n e ( 200 m Ti 150 Typical 100 Max: Typical + 3(cid:305) 50 Typical: 25°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-68: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL-POWER MODE (CxSP = 1) 260 Max: 125°C+ 3(cid:305) 240 Typical: 25°C Min: -45°C-3(cid:305) 220 ) s n e ( 200 m Ti 180 Max. (125°C) 160 Typical (25°C) Min. (-40°C) 140 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2011-2013 Microchip Technology Inc. DS40001574C-page 443

PIC16(L)F1938/9 FIGURE 31-69: COMPARATOR INPUT OFFSET AT 25°C, NORMAL-POWER MODE, (CxSP = 1), PIC16F1938/9 ONLY 60 40 Max. 20 ) V m Typical e ( 0 g a t ol Min. V t -20 e s f Of Max: Typical + 3(cid:305) -40 Typical: 25°C Min: Typical -3(cid:305) -60 0.0 1.0 2.0 3.0 4.0 5.0 Common Mode Voltage (V) DS40001574C-page 444  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 32.0 DEVELOPMENT SUPPORT 32.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2011-2013 Microchip Technology Inc. DS40001574C-page 445

PIC16(L)F1938/9 32.2 MPLAB XC Compilers 32.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 32.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 32.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001574C-page 446  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 32.6 MPLAB X SIM Software Simulator 32.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 32.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 32.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 32.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2011-2013 Microchip Technology Inc. DS40001574C-page 447

PIC16(L)F1938/9 32.11 Demonstration/Development 32.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001574C-page 448  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC16F1938 -I/SPe3 1148017 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX PIC16F1938 XXXXXXXXXXXXXXXXXXXX -I/SOe3 XXXXXXXXXXXXXXXXXXXX YYWWNNN 1110017 28-Lead SSOP (5.30 mm) Example PIC16F1938 -I/SSe3 1148017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PICmicro® device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2011-2013 Microchip Technology Inc. DS40001574C-page 449

PIC16(L)F1938/9 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 XXXXXXXX 16LF1938 XXXXXXXX -E/MLe3 YYWWNNN 1048017 28-Lead UQFN (4x4x0.5 mm) Example PIC16 PIN 1 PIN 1 F1938 -I/MVe3 148017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PICmicro® device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS40001574C-page 450  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 Package Marking Information (Continued) 40-Lead PDIP (600 mil) Example XXXXXXXXXXXXXXXXXX PIC16F1939 XXXXXXXXXXXXXXXXXX -I/Pe3 XXXXXXXXXXXXXXXXXX YYWWNNN 1148017 40-Lead UQFN (5x5x0.5 mm) Example PIN 1 PIN 1 PIC16 F1939 -I/MVe3 1148017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PICmicro® device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2011-2013 Microchip Technology Inc. DS40001574C-page 451

PIC16(L)F1938/9 Package Marking Information (Continued) 44-Lead QFN (8x8x0.9 mm) Example PIN 1 PIN 1 XXXXXXXXXXX 16F1939 XXXXXXXXXXX -I/MLe3 XXXXXXXXXXX 0810017 YYWWNNN 44-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX PIC16F1939 XXXXXXXXXX -I/PTe3 XXXXXXXXXX 0810017 YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PICmicro® device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS40001574C-page 452  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 33.2 Package Details The following sections give the technical details of the packages. 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(cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1  2011-2013 Microchip Technology Inc. DS40001574C-page 453

PIC16(L)F1938/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001574C-page 454  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS40001574C-page 455

PIC16(L)F1938/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001574C-page 456  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)#$(cid:12)(cid:13)(cid:11)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)%(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:10)(cid:24)(cid:9)(cid:25)(cid:9)&’(cid:26)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:10)%(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:30)(cid:4)(cid:20)(cid:3)(cid:4) (cid:30)(cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)-1  2011-2013 Microchip Technology Inc. DS40001574C-page 457

PIC16(L)F1938/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001574C-page 458  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)((cid:21)(cid:7)(cid:8)(cid:9))(cid:16)(cid:7)(cid:18)*(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)+(cid:6)(cid:9)(cid:23),(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)-.-(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)()! /(cid:12)(cid:18)#(cid:9)(cid:27)’&&(cid:9)(cid:28)(cid:28)(cid:9)0(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13)+(cid:18)# !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)- (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# A (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)(cid:29)1  2011-2013 Microchip Technology Inc. DS40001574C-page 459

PIC16(L)F1938/9 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)((cid:21)(cid:7)(cid:8)(cid:9))(cid:16)(cid:7)(cid:18)*(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)+(cid:6)(cid:9)(cid:23),(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)-.-(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)()! /(cid:12)(cid:18)#(cid:9)(cid:27)’&&(cid:9)(cid:28)(cid:28)(cid:9)0(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13)+(cid:18)# !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS40001574C-page 460  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS40001574C-page 461

PIC16(L)F1938/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001574C-page 462  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9  2011-2013 Microchip Technology Inc. DS40001574C-page 463

PIC16(L)F1938/9 1(cid:27)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)-(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c b1 A1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:29) = (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:29)(cid:24)(cid:4) = (cid:20)?(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:23)<(cid:29) = (cid:20)(cid:29)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)(cid:24)<(cid:4) = (cid:3)(cid:20)(cid:4)(cid:24)(cid:29) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) = (cid:20)(cid:3)(cid:4)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< = (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)-(cid:4) = (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) = (cid:20)(cid:4)(cid:3)- : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:5)(cid:4)(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)?1 DS40001574C-page 464  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS40001574C-page 465

PIC16(L)F1938/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001574C-page 466  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS40001574C-page 467

PIC16(L)F1938/9 DS40001574C-page 468  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9  2011-2013 Microchip Technology Inc. DS40001574C-page 469

PIC16(L)F1938/9 DS40001574C-page 470  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 11(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)2#(cid:12)(cid:13)(cid:9)((cid:21)(cid:7)(cid:8)(cid:9))(cid:16)(cid:7)(cid:18)3(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)2(cid:24)(cid:9)(cid:25)(cid:9)4(cid:27).4(cid:27).4(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)*(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)2()(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)9(cid:14)(cid:28)#! 7 (cid:23)(cid:23) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)<(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:24)(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ -(cid:20)(cid:29)@ (cid:5)@ : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:5) (cid:4)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:30)(cid:30)@ (cid:30)(cid:3)@ (cid:30)-@ (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:30)(cid:30)@ (cid:30)(cid:3)@ (cid:30)-@ !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ,(cid:11)(cid:28)’%(cid:14)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:8)(cid:10)(cid:9)(cid:15)(cid:14)(cid:9)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:2)(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)W(cid:2)!(cid:7)X(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:30)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)?1  2011-2013 Microchip Technology Inc. DS40001574C-page 471

PIC16(L)F1938/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001574C-page 472  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 APPENDIX A: DATA SHEET APPENDIX B: MIGRATING FROM REVISION HISTORY OTHER PIC® DEVICES Revision A (05/2011) This discusses some of the issues in migrating from Original release of this data sheet. other PIC® devices to the PIC16(L)F193X family of devices. Revision B (02/2012) B.1 PIC16F917 to PIC16(L)F193X Added new Family Types table; Updated Register 4-3; Added DC and AC Characteristics Graphs; Updated TABLE B-1: FEATURE COMPARISON the Electrical Specifications section; Updated the Feature PIC16F917 PIC16F1938 Packaging Information section; Other minor corrections. Max. Operating Speed 20MHz 32MHz Max. Program 8K 8K Revision C (06/2013) Memory (Words) Max. SRAM (Bytes) 368 512 Revised Data Sheet to Final status. A/D Resolution 10-bit 10-bit Timers (8/16-bit) 2/1 4/1 Oscillator Modes 4 8 Brown-out Reset Y Y Internal Pull-ups RB<7:0> RB<7:0> Interrupt-on-change RB<7:4> RB<7:0> Comparator 2 2 AUSART/EUSART 1/0 0/1 Extended WDT Y Y Software Control N Y Option of WDT/BOR INTOSC Frequencies 30kHz - 500kHz - 8MHz 32MHz Clock Switching Y Y Capacitive Sensing N Y CCP/ECCP 2/0 2/3 Enhanced PIC16 CPU N Y MSSP/SSP 0/1 1/0 LCD Y Y  2011-2013 Microchip Technology Inc. DS40001574C-page 473

PIC16(L)F1938/9 NOTES: DS40001574C-page 474  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 INDEX A Digital-to-Analog Converter (DAC)...........................166 EUSART Receive.....................................................288 A/D EUSART Transmit....................................................287 Specifications............................................................398 External RC Mode......................................................63 Absolute Maximum Ratings (PIC16(L)F1938/9)...............377 Fail-Safe Clock Monitor (FSCM).................................71 AC Characteristics Generic I/O Port........................................................121 Industrial and Extended............................................392 Interrupt Logic.............................................................85 Load Conditions........................................................391 LCD Clock Generation..............................................332 ACKSTAT.........................................................................270 On-Chip Reset Circuit.................................................77 ACKSTAT Status Flag......................................................270 PIC16(L)F1938/9........................................................12 ADC..................................................................................149 PIC16(L)F1938/9, Core..............................................20 Acquisition Requirements.........................................159 PWM (Enhanced).....................................................214 Associated registers..................................................161 Resonator Operation..................................................62 Block Diagram...........................................................149 Timer0......................................................................185 Calculating Acquisition Time.....................................159 Timer1......................................................................189 Channel Selection.....................................................150 Timer1 Gate..............................................194, 195, 196 Configuration.............................................................150 Timer2/4/6................................................................201 Configuring Interrupt.................................................154 Voltage Reference....................................................147 Conversion Clock......................................................150 Voltage Reference Output Buffer Example..............166 Conversion Procedure..............................................154 BORCON Register..............................................................79 Internal Sampling Switch (RSS) Impedance..............159 BRA..................................................................................368 Interrupts...................................................................152 Break Character (12-bit) Transmit and Receive...............307 Operation..................................................................153 Brown-out Reset (BOR)......................................................79 Operation During Sleep............................................153 Timing and Characteristics.......................................395 Port Configuration.....................................................150 Reference Voltage (VREF).........................................150 C Source Impedance....................................................159 C Compilers Special Event Trigger................................................153 MPLAB C18..............................................................446 Starting an A/D Conversion......................................152 CALL.................................................................................369 ADCON0 Register.......................................................33, 155 CALLW.............................................................................369 ADCON1 Register.......................................................33, 156 Capacitive Sensing...........................................................315 ADDFSR...........................................................................367 Associated registers w/ Capacitive Sensing.............323 ADDWFC..........................................................................367 Specifications...........................................................407 ADRESH Register...............................................................33 Capture Module. See Enhanced Capture/Compare/ ADRESH Register (ADFM = 0).........................................157 PWM(ECCP) ADRESH Register (ADFM = 1).........................................158 Capture/Compare/PWM...................................................205 ADRESL Register (ADFM = 0)..........................................157 Capture/Compare/PWM (CCP) ADRESL Register (ADFM = 1)..........................................158 Associated Registers w/ Capture.............................207 Alternate Pin Function.......................................................122 Associated Registers w/ Compare...........................209 Analog-to-Digital Converter. See ADC Associated Registers w/ PWM.........................213, 227 ANSELA Register.............................................................126 Capture Mode...........................................................206 ANSELB Register.............................................................131 CCPx Pin Configuration............................................206 ANSELD Register.............................................................138 Compare Mode.........................................................208 ANSELE Register.............................................................141 CCPx Pin Configuration....................................208 APFCON Register.............................................................123 Software Interrupt Mode...........................206, 208 Assembler Special Event Trigger.......................................208 MPASM Assembler...................................................446 Timer1 Mode Resource............................206, 208 B Prescaler..................................................................206 PWM Mode BAUDCON Register..........................................................298 Duty Cycle........................................................211 BF.............................................................................270, 272 Effects of Reset................................................213 BF Status Flag..........................................................270, 272 Example PWM Frequencies and Block Diagram Resolutions, 20 MHZ................................212 Capacitive Sensing...........................................315, 316 Example PWM Frequencies and Block Diagrams Resolutions, 32 MHZ................................212 (CCP) Capture Mode Operation...............................206 Example PWM Frequencies and ADC..........................................................................149 Resolutions, 8 MHz..................................212 ADC Transfer Function.............................................160 Operation in Sleep Mode..................................213 Analog Input Model...........................................160, 174 Resolution........................................................212 CCP PWM.................................................................210 System Clock Frequency Changes..................213 Clock Source...............................................................60 PWM Operation........................................................210 Comparator...............................................................170 PWM Overview.........................................................210 Compare...................................................................208 PWM Period.............................................................211 Crystal Operation..................................................62, 63 PWM Setup..............................................................211  2011-2013 Microchip Technology Inc. DS40001574C-page 475

PIC16(L)F1938/9 CCP1CON Register......................................................37, 38 Industrial and Extended (PIC16(L)F1938/9).............380 CCPR1H Register.........................................................37, 38 Development Support.......................................................445 CCPR1L Register..........................................................37, 38 Device Configuration..........................................................53 CCPTMRS0 Register........................................................229 Code Protection..........................................................57 CCPTMRS1 Register........................................................230 Configuration Word.....................................................53 CCPxAS Register..............................................................231 User ID.................................................................57, 58 CCPxCON (ECCPx) Register...........................................228 Device Overview.........................................................11, 103 Clock Accuracy with Asynchronous Operation.................296 Digital-to-Analog Converter (DAC)...................................165 Clock Sources Effects of a Reset.....................................................166 External Modes...........................................................61 Specifications...........................................................400 EC.......................................................................61 E HS.......................................................................61 LP........................................................................61 ECCP/CCP. See Enhanced Capture/Compare/PWM OST.....................................................................62 EEADR Registers.............................................................107 RC.......................................................................63 EEADRH Registers...........................................................107 XT.......................................................................61 EEADRL Register.............................................................118 Internal Modes............................................................64 EEADRL Registers...........................................................107 HFINTOSC..........................................................64 EECON1 Register.....................................................107, 119 Internal Oscillator Clock Switch Timing...............66 EECON2 Register.....................................................107, 120 LFINTOSC..........................................................65 EEDATH Register.............................................................118 MFINTOSC.........................................................64 EEDATL Register.............................................................118 Clock Switching...................................................................68 EEPROM Data Memory CMOUT Register...............................................................176 Avoiding Spurious Write...........................................108 CMxCON0 Register..........................................................175 Write Verify...............................................................117 CMxCON1 Register..........................................................176 Effects of Reset Code Examples PWM mode...............................................................213 A/D Conversion.........................................................154 Electrical Specifications (PIC16(L)F1938/9).....................377 Changing Between Capture Prescalers....................206 Enhanced Capture/Compare/PWM (ECCP).....................205 Initializing PORTA.....................................................121 Enhanced PWM Mode..............................................214 Initializing PORTE.....................................................140 Auto-Restart.....................................................223 Write Verify...............................................................117 Auto-shutdown..................................................222 Writing to Flash Program Memory............................115 Direction Change in Full-Bridge Output Mode..220 Comparator Full-Bridge Application......................................218 Associated Registers........................................177, 178 Full-Bridge Mode..............................................218 Operation..................................................................169 Half-Bridge Application.....................................217 Comparator Module..........................................................169 Half-Bridge Application Examples....................224 Cx Output State Versus Input Conditions.................171 Half-Bridge Mode..............................................217 Comparator Specifications................................................400 Output Relationships (Active-High and Comparators Active-Low)...............................................215 C2OUT as T1 Gate...................................................191 Output Relationships Diagram..........................216 Compare Module. See Enhanced Capture/ Programmable Dead Band Delay.....................224 Compare/PWM (ECCP) Shoot-through Current......................................224 CONFIG1 Register..............................................................54 Start-up Considerations....................................226 CONFIG2 Register..............................................................56 Specifications...........................................................397 Core Registers....................................................................32 Enhanced Mid-range CPU..................................................19 CPSCON0 Register..........................................................321 Enhanced Universal Synchronous Asynchronous CPSCON1 Register..........................................................322 Receiver Transmitter (EUSART)..............................287 Customer Change Notification Service.............................483 Errata....................................................................................9 Customer Notification Service...........................................483 EUSART...........................................................................287 Customer Support.............................................................483 Associated Registers Baud Rate Generator.......................................300 D Asynchronous Mode.................................................289 DACCON0 (Digital-to-Analog Converter Control 0) 12-bit Break Transmit and Receive..................307 Register.....................................................................168 Associated Registers DACCON1 (Digital-to-Analog Converter Control 1) Receive....................................................295 Register.....................................................................168 Transmit....................................................291 Data EEPROM Memory....................................................107 Auto-Wake-up on Break...................................305 Associated Registers................................................120 Baud Rate Generator (BRG)............................299 Code Protection........................................................108 Clock Accuracy.................................................296 Reading.....................................................................108 Receiver...........................................................292 Writing.......................................................................108 Setting up 9-bit Mode with Address Detect......294 Data Memory.......................................................................23 Transmitter.......................................................289 DC and AC Characteristics...............................................409 Baud Rate Generator (BRG) Graphs and Tables...................................................409 Auto Baud Rate Detect.....................................304 DC Characteristics Baud Rate Error, Calculating............................299 Extended and Industrial (PIC16(L)F1938/9).............387 Baud Rates, Asynchronous Modes..................301 DS40001574C-page 476  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 Formulas...........................................................300 BTFSC......................................................................368 High Baud Rate Select (BRGH Bit)..................299 BTFSS......................................................................368 Synchronous Master Mode...............................308, 312 CALL.........................................................................369 Associated Registers CALLW.....................................................................369 Receive.....................................................311 CLRF........................................................................369 Transmit....................................................309 CLRW.......................................................................369 Reception..........................................................310 CLRWDT..................................................................369 Transmission....................................................308 COMF.......................................................................369 Synchronous Slave Mode DECF........................................................................369 Associated Registers DECFSZ...................................................................370 Receive.....................................................313 GOTO.......................................................................370 Transmit....................................................312 INCF.........................................................................370 Reception..........................................................313 INCFSZ.....................................................................370 Transmission....................................................312 IORLW......................................................................370 Extended Instruction Set IORWF......................................................................370 ADDFSR...................................................................367 LSLF.........................................................................371 LSRF........................................................................371 F MOVF.......................................................................371 Fail-Safe Clock Monitor.......................................................71 MOVIW.....................................................................372 Fail-Safe Condition Clearing.......................................71 MOVLB.....................................................................372 Fail-Safe Detection.....................................................71 MOVLW....................................................................372 Fail-Safe Operation.....................................................71 MOVWF....................................................................372 Reset or Wake-up from Sleep.....................................71 MOVWI.....................................................................373 Firmware Instructions........................................................363 NOP..........................................................................373 Fixed Voltage Reference (FVR) OPTION....................................................................373 Associated Registers................................................148 RESET......................................................................373 Flash Program Memory....................................................107 RETFIE.....................................................................374 Erasing......................................................................112 RETLW.....................................................................374 Modifying...................................................................116 RETURN...................................................................374 Writing.......................................................................112 RLF...........................................................................374 FSR Register32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45 RRF..........................................................................375 FVRCON (Fixed Voltage Reference Control) Register.....148 SLEEP......................................................................375 SUBLW.....................................................................375 I SUBWF.....................................................................375 I2C Mode (MSSP) SUBWFB..................................................................375 Acknowledge Sequence Timing................................274 SWAPF.....................................................................376 Bus Collision TRIS.........................................................................376 During a Repeated Start Condition...................278 XORLW....................................................................376 During a Stop Condition....................................279 XORWF....................................................................376 Effects of a Reset......................................................275 INTCON Register................................................................90 I2C Clock Rate w/BRG..............................................281 Internal Oscillator Block Master Mode INTOSC Operation..........................................................266 Specifications...................................................393 Reception..........................................................272 Internal Sampling Switch (RSS) Impedance.....................159 Start Condition Timing..............................268, 269 Internet Address...............................................................483 Transmission....................................................270 Interrupt-On-Change.........................................................143 Multi-Master Communication, Bus Collision Associated Registers................................................146 and Arbitration..................................................275 Interrupts............................................................................85 Multi-Master Mode....................................................275 ADC..........................................................................154 Read/Write Bit Information (R/W Bit)........................251 Associated registers w/ Interrupts..............................97 Slave Mode Configuration Word w/ Clock Sources........................75 Transmission....................................................256 TMR1........................................................................193 Sleep Operation........................................................275 INTOSC Specifications.....................................................393 Stop Condition Timing...............................................274 IOCBF Register................................................................145 INDF Register32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45 IOCBN Register................................................................145 Indirect Addressing.............................................................49 IOCBP Register................................................................145 Instruction Format.............................................................364 L Instruction Set...................................................................363 ADDLW.....................................................................367 LATA Register..........................................................125, 134 ADDWF.....................................................................367 LATB Register..................................................................130 ADDWFC..................................................................367 LATD Register..................................................................138 ANDLW.....................................................................367 LATE Register..................................................................141 ANDWF.....................................................................367 LCD BCF...........................................................................368 Bias Voltage Generation...................................333, 334 BRA...........................................................................368 Clock Source Selection............................................332 BSF...........................................................................368 Configuring the Module............................................357  2011-2013 Microchip Technology Inc. DS40001574C-page 477

PIC16(L)F1938/9 Disabling the Module................................................357 Two-Speed Clock Start-up..........................................69 Frame Frequency......................................................340 OSCSTAT Register............................................................74 Interrupts...................................................................353 OSCTUNE Register............................................................75 LCDCON Register....................................................326 P LCDPS Register........................................................326 Multiplex Types.........................................................340 P1A/P1B/P1C/P1D.See Enhanced Capture/ Operation During Sleep............................................355 Compare/PWM (ECCP)............................................214 Pixel Control..............................................................340 Packaging.........................................................................449 Prescaler...................................................................332 Marking.............................................449, 450, 451, 452 Segment Enables......................................................340 PDIP Details.............................................................453 Waveform Generation...............................................342 PCL and PCLATH...............................................................20 LCDCON Register.....................................................326, 327 PCL Register32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45 LCDCST Register.............................................................330 PCLATH Register32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 44, LCDDATAx Registers...............................................331, 338 45 LCDPS Register........................................................326, 328 PCON Register.............................................................33, 83 LP Bits.......................................................................332 PIE1 Register................................................................33, 91 LCDREF Register.............................................................329 PIE2 Register................................................................33, 92 LCDRL Register................................................................338 PIE3 Register......................................................................93 LCDSEn Registers............................................................331 Pin Diagram Liquid Crystal Display (LCD) Driver..................................325 28-pin QFN/UQFN........................................................3 Load Conditions................................................................391 28-pin SPDIP/SOIC/SSOP...........................................3 LSLF..................................................................................371 40-pin PDIP..................................................................4 LSRF.................................................................................371 44-pin QFN...................................................................5 44-pin TQFP.................................................................5 M 44-pin UQFN.................................................................4 Master Synchronous Serial Port. See MSSP Pinout Descriptions MCLR..................................................................................80 PIC16(L)1938/9..........................................................13 Internal........................................................................80 PIR1 Register...............................................................32, 94 Memory Organization PIR2 Register...............................................................32, 95 Data............................................................................23 PIR3 Register.....................................................................96 Program......................................................................21 PORTA.............................................................................124 Microchip Internet Web Site..............................................483 ANSELA Register.....................................................124 Migrating from other PIC Microcontroller Devices.............473 Associated Registers................................................127 MOVIW..............................................................................372 Configuration Word w/ PORTA.................................127 MOVLB..............................................................................372 PORTA Register...................................................32, 34 MOVWI..............................................................................373 Specifications...........................................................394 MPLAB ASM30 Assembler, Linker, Librarian...................446 PORTA Register...............................................................125 MPLAB Integrated Development Environment Software..445 PORTB.............................................................................128 MPLAB PM3 Device Programmer.....................................447 Additional Pin Functions MPLAB REAL ICE In-Circuit Emulator System.................447 Weak Pull-up....................................................129 MPLINK Object Linker/MPLIB Object Librarian................446 ANSELB Register.....................................................128 MSSP................................................................................235 Associated Registers................................................132 SPI Mode..................................................................238 Interrupt-on-Change.................................................128 SSPBUF Register.....................................................241 P1B/P1C/P1D.See Enhanced Capture/Compare/ SSPSR Register.......................................................241 PWM+ (ECCP+)...............................................128 Pin Descriptions and Diagrams................................129 O PORTB Register...................................................32, 34 OPCODE Field Descriptions.............................................363 PORTB Register...............................................................130 OPTION............................................................................373 PORTC.............................................................................133 OPTION Register..............................................................187 Associated Registers................................................135 OSCCON Register..............................................................73 P1A.See Enhanced Capture/Compare/PWM+ Oscillator (ECCP+)...........................................................133 Associated Registers..................................................75 Pin Descriptions and Diagrams................................133 Oscillator Module................................................................59 PORTC Register...................................................32, 34 ECH............................................................................59 Specifications...........................................................394 ECL.............................................................................59 PORTC Register...............................................................134 ECM............................................................................59 PORTD.............................................................................136 HS...............................................................................59 Additional Pin Functions INTOSC......................................................................59 ANSELD Register.............................................136 LP................................................................................59 Associated Registers................................................138 RC...............................................................................59 P1B/P1C/P1D.See Enhanced Capture/Compare/ XT...............................................................................59 PWM+ (ECCP+)...............................................136 Oscillator Parameters........................................................393 Pin Descriptions and Diagrams................................136 Oscillator Specifications....................................................392 PORTD Register...................................................32, 34 Oscillator Switching PORTD Register...............................................................137 Fail-Safe Clock Monitor...............................................71 PORTE.............................................................................139 DS40001574C-page 478  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 ANSELE Register.....................................................139 IOCBN (Interrupt-on-Change Negative Edge)..........145 Associated Registers................................................142 IOCBP (Interrupt-on-Change Positive Edge)............145 Pin Descriptions and Diagrams.................................139 LATA (Data Latch PORTA)......................................125 PORTE Register...................................................32, 34 LATB (Data Latch PORTB)......................................130 PORTE Register...............................................................140 LATC (Data Latch PORTC)......................................134 Power-Down Mode (Sleep)...............................................101 LATD (Data Latch PORTD)......................................138 Associated Registers................................................102 LATE (Data Latch PORTE)......................................141 Power-on Reset..................................................................78 LCDCON (LCD Control)...........................................327 Power-up Timer (PWRT)....................................................78 LCDCST (LCD Contrast Control).............................330 PR2 Register.................................................................32, 40 LCDDATAx (LCD Data)....................................331, 338 Precision Internal Oscillator Parameters...........................393 LCDPS (LCD Phase)................................................328 Program Memory................................................................21 LCDREF (LCD Reference Voltage Control).............329 Map and Stack............................................................22 LCDRL (LCD Reference Voltage Control)................338 Programming Mode Exit.....................................................80 LCDSEn (LCD Segment Enable).............................331 Programming, Device Instructions....................................363 OPTION_REG (OPTION).........................................187 PSTRxCON Register........................................................233 OSCCON (Oscillator Control).....................................73 PWM (ECCP Module) OSCSTAT (Oscillator Status).....................................74 PWM Steering...........................................................225 OSCTUNE (Oscillator Tuning)....................................75 Steering Synchronization..........................................226 PCON (Power Control Register).................................83 PWM Mode. See Enhanced Capture/Compare/PWM......214 PCON (Power Control)...............................................83 PWM Steering...................................................................225 PIE1 (Peripheral Interrupt Enable 1)..........................91 PWMxCON Register.........................................................232 PIE2 (Peripheral Interrupt Enable 2)..........................92 PIE3 (Peripheral Interrupt Enable 3)..........................93 R PIR1 (Peripheral Interrupt Register 1)........................94 RCREG.............................................................................294 PIR2 (Peripheral Interrupt Request 2)........................95 RCREG Register.................................................................35 PIR3 (Peripheral Interrupt Request 3)........................96 RCSTA Register.........................................................35, 297 PORTA.....................................................................125 Reader Response.............................................................484 PORTB.....................................................................130 Read-Modify-Write Operations.........................................363 PORTC.....................................................................134 Register PORTD.....................................................................137 RCREG Register.......................................................304 PORTE.....................................................................140 Registers PSTRxCON (PWM Steering Control).......................233 ADCON0 (ADC Control 0)........................................155 PWMxCON (Enhanced PWM Control).....................232 ADCON1 (ADC Control 1)........................................156 RCSTA (Receive Status and Control)......................297 ADRESH (ADC Result High) with ADFM = 0)...........157 Special Function, Summary........................................32 ADRESH (ADC Result High) with ADFM = 1)...........158 SRCON0 (SR Latch Control 0).................................182 ADRESL (ADC Result Low) with ADFM = 0)............157 SRCON1 (SR Latch Control 1).................................183 ADRESL (ADC Result Low) with ADFM = 1)............158 SSPADD (MSSP Address and Baud Rate, ANSELA (PORTA Analog Select).............................126 I2C Mode).........................................................286 ANSELB (PORTB Analog Select).............................131 SSPCON1 (MSSP Control 1)...................................283 ANSELD (PORTD Analog Select)............................138 SSPCON2 (SSP Control 2)......................................284 ANSELE (PORTE Analog Select).............................141 SSPCON3 (SSP Control 3)......................................285 APFCON (Alternate Pin Function Control)................123 SSPMSK (SSP Mask)..............................................286 BAUDCON (Baud Rate Control)...............................298 SSPSTAT (SSP Status)...........................................282 BORCON Brown-out Reset Control)...........................79 STATUS.....................................................................24 CCPTMRS0 (PWM Timer Selection Control 0)........229 T1CON (Timer1 Control)..........................................197 CCPTMRS1 (PWM Timer Selection Control 1)........230 T1GCON (Timer1 Gate Control)...............................198 CCPxAS (CCPx Auto-Shutdown Control).................231 TRISA (Tri-State PORTA)........................................125 CCPxCON (ECCPx Control).....................................228 TRISB (Tri-State PORTB)........................................130 CMOUT (Comparator Output)...................................176 TRISC (Tri-State PORTC)........................................134 CMxCON0 (Cx Control)............................................175 TRISD (Tri-State PORTD)........................................137 CMxCON1 (Cx Control 1).........................................176 TRISE (Tri-State PORTE)........................................140 Configuration Word 1..................................................54 TXCON.....................................................................203 Configuration Word 2..................................................56 TXSTA (Transmit Status and Control)......................296 CPSCON0 (Capacitive Sensing Control Register 0) 321 WDTCON (Watchdog Timer Control).......................105 CPSCON1 (Capacitive Sensing Control Register 1) 322 WPUB (Weak Pull-up PORTB).................................131 DACCON0................................................................168 RESET..............................................................................373 DACCON1................................................................168 Reset..................................................................................77 EEADRL (EEPROM Address)..................................118 Reset Instruction.................................................................80 EECON1 (EEPROM Control 1).................................119 Resets................................................................................77 EECON2 (EEPROM Control 2).................................120 Associated Registers..................................................84 EEDATH (EEPROM Data)........................................118 Revision History................................................................473 EEDATL (EEPROM Data)........................................118 S FVRCON...................................................................148 INTCON (Interrupt Control).........................................90 Shoot-through Current......................................................224 IOCBF (Interrupt-on-Change Flag)...........................145 Software Simulator (MPLAB SIM)....................................447  2011-2013 Microchip Technology Inc. DS40001574C-page 479

PIC16(L)F1938/9 SPBRG Register...........................................................34, 35 TXCON.............................................................203 SPBRGH...........................................................................299 Timing Diagrams SPBRGL............................................................................299 A/D Conversion.........................................................399 Special Event Trigger........................................................153 A/D Conversion (Sleep Mode)..................................399 Special Function Registers (SFRs).....................................32 Acknowledge Sequence...........................................274 SPI Mode (MSSP) Asynchronous Reception..........................................294 Associated Registers................................................245 Asynchronous Transmission.....................................290 SPI Clock..................................................................241 Asynchronous Transmission (Back to Back)............290 SR Latch...........................................................................180 Auto Wake-up Bit (WUE) During Normal Operation.306 Associated registers w/ SR Latch.............................183 Auto Wake-up Bit (WUE) During Sleep....................306 SRCON0 Register.............................................................182 Automatic Baud Rate Calibration..............................304 SRCON1 Register.............................................................183 Baud Rate Generator with Clock Arbitration.............267 SSPADD Register.......................................................36, 286 BRG Reset Due to SDA Arbitration During Start SSPBUF Register...............................................................36 Condition..........................................................277 SSPCON Register...............................................................36 Brown-out Reset (BOR)............................................395 SSPCON1 Register...........................................................283 Brown-out Reset Situations........................................79 SSPCON2 Register...........................................................284 Bus Collision During a Repeated Start Condition SSPCON3 Register...........................................................285 (Case 1)............................................................278 SSPMSK Register.............................................................286 Bus Collision During a Repeated Start Condition SSPOV..............................................................................272 (Case 2)............................................................278 SSPOV Status Flag...........................................................272 Bus Collision During a Start Condition (SCL = 0).....277 SSPSTAT Register.....................................................36, 282 Bus Collision During a Stop Condition (Case 1).......279 R/W Bit......................................................................251 Bus Collision During a Stop Condition (Case 2).......279 Stack...................................................................................47 Bus Collision During Start Condition (SDA only)......276 Accessing....................................................................47 Bus Collision for Transmit and Acknowledge...........275 Reset...........................................................................49 CLKOUT and I/O......................................................393 Stack Overflow/Underflow...................................................80 Clock Synchronization..............................................264 STATUS Register................................................................24 Clock Timing.............................................................392 SUBWFB...........................................................................375 Comparator Output...................................................169 Enhanced Capture/Compare/PWM (ECCP).............397 T Fail-Safe Clock Monitor (FSCM).................................72 T1CON Register..........................................................32, 197 First Start Bit Timing.................................................268 T1GCON Register.............................................................198 Full-Bridge PWM Output...........................................219 T2CON Register............................................................32, 40 Half-Bridge PWM Output..................................217, 224 Temperature Indicator I2C Bus Data.............................................................405 Associated Registers................................................164 I2C Bus Start/Stop Bits.............................................404 Temperature Indicator Module..........................................163 I2C Master Mode (7 or 10-Bit Transmission)............271 Thermal Considerations (PIC16(L)F1938/9).....................390 I2C Master Mode (7-Bit Reception)...........................273 Timer0...............................................................................185 I2C Stop Condition Receive or Transmit Mode.........274 Associated Registers................................................187 INT Pin Interrupt.........................................................88 Operation..................................................................185 Internal Oscillator Switch Timing................................67 Specifications............................................................397 LCD Interrupt Timing in Quarter-Duty Cycle Drive...354 Timer1...............................................................................189 LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00.356 Associated registers..................................................199 PWM Auto-shutdown................................................223 Asynchronous Counter Mode...................................191 Firmware Restart..............................................222 Reading and Writing.........................................191 PWM Direction Change............................................220 Clock Source Selection.............................................190 PWM Direction Change at Near 100% Duty Cycle...221 Interrupt.....................................................................193 PWM Output (Active-High).......................................215 Operation..................................................................190 PWM Output (Active-Low)........................................216 Operation During Sleep............................................193 Repeat Start Condition.............................................269 Oscillator...................................................................191 Reset Start-up Sequence...........................................81 Prescaler...................................................................191 Reset, WDT, OST and Power-up Timer...................394 Specifications............................................................397 Send Break Character Sequence.............................307 Timer1 Gate SPI Master Mode (CKE = 1, SMP = 1).....................402 Selecting Source...............................................191 SPI Mode (Master Mode)..........................................241 TMR1H Register.......................................................189 SPI Slave Mode (CKE = 0).......................................403 TMR1L Register........................................................189 SPI Slave Mode (CKE = 1).......................................403 Timer2 Synchronous Reception (Master Mode, SREN).......311 Associated registers..................................................204 Synchronous Transmission......................................309 Timer2/4/6.........................................................................201 Synchronous Transmission (Through TXEN)...........309 Associated registers..................................................204 Timer0 and Timer1 External Clock...........................396 Timers Timer1 Incrementing Edge.......................................193 Timer1 Two Speed Start-up....................................................70 T1CON..............................................................197 Type-A in 1/2 MUX, 1/2 Bias Drive...........................343 T1GCON...........................................................198 Type-A in 1/2 MUX, 1/3 Bias Drive...........................345 Timer2/4/6 DS40001574C-page 480  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 Type-A in 1/3 MUX, 1/2 Bias Drive...........................347 Type-A in 1/3 MUX, 1/3 Bias Drive...........................349 Type-A in 1/4 MUX, 1/3 Bias Drive...........................351 Type-A/Type-B in Static Drive...................................342 Type-B in 1/2 MUX, 1/2 Bias Drive...........................344 Type-B in 1/2 MUX, 1/3 Bias Drive...........................346 Type-B in 1/3 MUX, 1/2 Bias Drive...........................348 Type-B in 1/3 MUX, 1/3 Bias Drive...........................350 Type-B in 1/4 MUX, 1/3 Bias Drive...........................352 USART Synchronous Receive (Master/Slave).........401 USART Synchronous Transmission (Master/Slave).400 Wake-up from Interrupt.............................................102 Timing Diagrams and Specifications PLL Clock..................................................................393 Timing Parameter Symbology...........................................391 Timing Requirements I2C Bus Data.............................................................406 I2C Bus Start/Stop Bits.............................................405 SPI Mode..................................................................404 TMR0 Register....................................................................32 TMR1H Register.................................................................32 TMR1L Register..................................................................32 TMR2 Register..............................................................32, 40 TRIS..................................................................................376 TRISA Register...........................................................33, 125 TRISB...............................................................................128 TRISB Register...........................................................33, 130 TRISC...............................................................................133 TRISC Register...........................................................33, 134 TRISD...............................................................................136 TRISD Register...........................................................33, 137 TRISE...............................................................................139 TRISE Register...........................................................33, 140 Two-Speed Clock Start-up Mode........................................69 TXCON (Timer2/4/6) Register..........................................203 TXREG..............................................................................289 TXREG Register.................................................................35 TXSTA Register..........................................................35, 296 BRGH Bit..................................................................299 U USART Synchronous Master Mode Requirements, Synchronous Receive..............401 Requirements, Synchronous Transmission......401 Timing Diagram, Synchronous Receive...........401 Timing Diagram, Synchronous Transmission...400 V VREF. SEE ADC Reference Voltage W Wake-up on Break............................................................305 Wake-up Using Interrupts.................................................102 Watchdog Timer (WDT)......................................................80 Associated Registers................................................106 Modes.......................................................................104 WCOL.......................................................267, 270, 272, 274 WCOL Status Flag....................................267, 270, 272, 274 WDTCON Register...........................................................105 WPUB Register.................................................................131 Write Protection..................................................................57 WWW Address..................................................................483 WWW, On-Line Support...................................................2, 9  2011-2013 Microchip Technology Inc. DS40001574C-page 481

PIC16(L)F1938/9 NOTES: DS40001574C-page 482  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011-2013 Microchip Technology Inc. DS40001574C-page 483

DEVICE FAMILY NOTES: DS40001574C-page 484  2011-2013 Microchip Technology Inc.

PIC16(L)F1938/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) - X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC16LF1938 - I/P = Industrial temp., Plastic DIP package, low-voltage VDD limits. Option Range b) PIC16F1939 - I/PT = Industrial temp., TQFP package, standard VDD limits. c) PIC16F1939 - E/ML = Extended temp., QFN Device: PIC16F1938, PIC16LF1938 package, standard VDD limits. PIC16F1939, PIC16LF1939 Tape and Reel Blank = Standard packaging (tube or tray) Option: T = Tape and Reel(1) Temperature I = -40C to +85C Range: E = -40C to +125C Package: ML = QFN MV = UQFN Note1: Tape and Reel identifier only appears in the P = PDIP catalog part number description. This PT = TQFP identifier is used for ordering purposes and is SO = SOIC not printed on the device package. Check SP = SPDIP with your Microchip Sales Office for package SS = SSOP availability with the Tape and Reel option. Pattern: 3-Digit Pattern Code for QTP (blank otherwise)  2011-2013 Microchip Technology Inc. DS40001574C-page 485

PIC16(L)F1938/9 NOTES: DS40001574C-page 486  2011-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip WARRANTIES OF ANY KIND WHETHER EXPRESS OR Technology Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2011-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620772690 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2011-2013 Microchip Technology Inc. DS40001574C-page 487

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16F1938-E/MV PIC16F1938-I/MV PIC16F1938T-I/MV PIC16LF1938-E/MV PIC16LF1938-I/MV PIC16LF1938T- I/MV PIC16LF1939-I/MV PIC16F1939-I/MV PIC16F1939-E/MV PIC16F1939T-I/MV PIC16LF1939-E/MV PIC16LF1939T-I/MV PIC16F1938-E/ML PIC16F1938-E/SO PIC16F1938-E/SP PIC16F1938-E/SS PIC16F1938-I/ML PIC16F1938-I/SO PIC16F1938-I/SP PIC16F1938-I/SS PIC16F1938T-I/ML PIC16F1938T-I/SO PIC16F1938T-I/SS PIC16F1939-E/ML PIC16F1939-E/P PIC16F1939-E/PT PIC16F1939-I/ML PIC16F1939-I/P PIC16F1939-I/PT PIC16F1939T-I/ML PIC16F1939T-I/PT PIC16LF1938-E/ML PIC16LF1938-E/SO PIC16LF1938-E/SP PIC16LF1938- E/SS PIC16LF1938-I/ML PIC16LF1938-I/SO PIC16LF1938-I/SP PIC16LF1938-I/SS PIC16LF1938T-I/ML PIC16LF1938T-I/SO PIC16LF1938T-I/SS PIC16LF1939-E/ML PIC16LF1939-E/P PIC16LF1939-E/PT PIC16LF1939- I/ML PIC16LF1939-I/P PIC16LF1939-I/PT PIC16LF1939T-I/ML PIC16LF1939T-I/PT PIC16F1938T-E/SS