PIC16(L)F1826/27 Data Sheet 18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology  2011 Microchip Technology Inc. DS41391D

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-124-7 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41391D-page 2  2011 Microchip Technology Inc.

PIC16(L)F1826/27 18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology High-Performance RISC CPU: Extreme Low-Power Management PIC16LF1826/27 with nanoWatt XLP: • C Compiler Optimized Architecture • 256bytes Data EEPROM • Operating Current: 75A @ 1 MHz, 1.8V, typical • Up to 8 Kbytes Linear Program Memory • Sleep mode: 30 nA Addressing • Watchdog Timer: 500 nA • Up to 384bytes Linear Data Memory Addressing • Timer1 Oscillator: 600 nA @ 32 kHz • Interrupt Capability with Automatic Context Saving Analog Features: • 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset • Analog-to-Digital Converter (ADC) Module: • Direct, Indirect and Relative Addressing modes: - 10-bit resolution, 12 channels - Two full 16-bit File Select Registers (FSRs) - Auto acquisition capability - FSRs can read program and data memory - Conversion available during Sleep • Analog Comparator Module: Flexible Oscillator Structure: - Two rail-to-rail analog comparators - Power mode control • Precision 32MHz Internal Oscillator Block: - Software controllable hysteresis - Factory calibrated to ± 1%, typical • Voltage Reference Module: - Software selectable frequencies range of - Fixed Voltage Reference (FVR) with 1.024V, 31kHz to 32MHz 2.048V and 4.096V output levels • 31 kHz Low-Power Internal Oscillator - 5-bit rail-to-rail resistive DAC with positive • Four Crystal modes up to 32MHz and negative reference selection • Three External Clock modes up to 32MHz • 4X Phase-Lock Loop (PLL) Peripheral Highlights: • Fail-Safe Clock Monitor: • 15 I/O Pins and 1 Input Only Pin: - Allows for safe shutdown if peripheral clock - High current sink/source 25mA/25mA stops - Programmable weak pull-ups • Two-Speed Oscillator Start-up - Programmable interrupt-on- change pins • Reference Clock Module: • Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler - Programmable clock output frequency and • Enhanced Timer1: duty-cycle - 16-bit timer/counter with prescaler Special Microcontroller Features: - External Gate Input mode - Dedicated, low-power 32 kHz oscillator driver • 1.8V-5.5V Operation – PIC16F1826/27 • Up to three Timer2-types: 8-Bit Timer/Counter with • 1.8V-3.6V Operation – PIC16LF1826/27 8-Bit Period Register, Prescaler and Postscaler • Self-Programmable under Software Control • Up to two Capture, Compare, PWM (CCP) Modules • Power-on Reset (POR), Power-up Timer (PWRT) • Up to two Enhanced CCP (ECCP) Modules: and Oscillator Start-up Timer (OST) - Software selectable time bases • Programmable Brown-out Reset (BOR) - Auto-shutdown and auto-restart • Extended Watchdog Timer (WDT): - PWM steering - Programmable period from 1ms to 268s • Up to two Master Synchronous Serial Port • Programmable Code Protection (MSSP) with SPI and I2CTM with: • In-Circuit Serial Programming™ (ICSP™) via - 7-bit address masking two pins - SMBus/PMBusTM compatibility • In-Circuit Debug (ICD) via two pins • Enhanced Universal Synchronous Asynchronous • Enhance Low-Voltage Programming Receiver Transmitter (EUSART) Module • Power-Saving Sleep mode • mTouch™ Sensing Oscillator Module: - Up to 12 input channels • Data Signal Modulator Module: - Selectable modulator and carrier sources • SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications  2011 Microchip Technology Inc. DS41391D-page 3

PIC16(L)F1826/27 PIC16(L)F1826/27 Family Types Device PMreomWordsgroarmy SRAMM(bytes)eDmatoaData EEPROMr y(bytes) (1)I/O’s 10-bit ADC (ch) CapSense (ch) Comparators Timers (8/16-bit) EUSART MSSP ECCP (Full-Bridge) ECCP (Half-Bridge) CCP SR Latch PIC16LF1826 2K 256 256 16 12 12 2 2/1 1 1 1 — — Yes PIC16F1826 2K 256 256 16 12 12 2 2/1 1 1 1 — — Yes PIC16LF1827 4K 384 256 16 12 12 2 4/1 1 2 1 1 2 Yes PIC16F1827 4K 384 256 16 12 12 2 4/1 1 2 1 1 2 Yes Note 1: One pin is input only. Pin Diagram – 18-Pin PDIP, SOIC (PIC16(L)F1826/27) PDIP, SOIC RA2 1 18 RA1 RA3 2 17 RA0 RA4 3 16 RA7 7 RA5/MCLR/VPP 4 6/2 15 RA6 2 VSS 5 F18 14 VDD L) RB0 6 6( 13 RB7 1 C RB1 7 PI 12 RB6 RB2 8 11 RB5 RB3 9 10 RB4 Pin Diagram – 20-Pin SSOP (PIC16(L)F1826/27) SSOP RA2 1 20 RA1 RA3 2 19 RA0 RA4 3 18 RA7 RA5/MCLR/VPP 4 7 17 RA6 2 VSS 5 26/ 16 VDD 8 1 VSS 6 L)F 15 VDD 6( RB0 7 C1 14 RB7 PI RB1 8 13 RB6 RB2 9 12 RB5 RB3 10 11 RB4 DS41391D-page 4  2011 Microchip Technology Inc.

PIC16(L)F1826/27 Pin Diagram – 28-Pin QFN/UQFN (PIC16(L)F1826/27) QFN/UQFN 4 3 2 1 0 A A A A A R R R R R C C N N 8 7 6 5 4 3 2 RA5/MCLR/VPP 12 2 2 2 2 2 221 RA7 NC 2 20 RA6 VSS 3 19 VDD NC 4 PIC16(L)F1826/27 18 NC VSS 5 17 VDD NC 6 16 RB7 RB0 7 15 RB6 8 9 0 1 2 3 4 1 1 1 1 1 C C N N 1 2 3 4 5 B B B B B R R R R R  2011 Microchip Technology Inc. DS41391D-page 5

D TABLE 1: 18/20/28-PIN SUMMARY (PIC16(L)F1826/27) P S 4 1391D-page 6 I/O 18-Pin PDIP/SOIC 20-Pin SSOP 28-Pin QFN/UQFN ANSEL A/D Reference Cap Sense Comparator SR Latch Timers CCP EUSART MSSP Interrupt Modulator Pull-up Basic IC16(L RA0 17 19 23 Y AN0 — CPS0 C12IN0- — — — — SDO2(2) — — N — ) RA1 18 20 24 Y AN1 — CPS1 C12IN1- — — — — SS2(2) — — N — F RA2 1 1 26 Y AN2 VREF- CPS2 C12IN2- — — — — — — — N — 1 DACOUT C12IN+ 8 RA3 2 2 27 Y AN3 VREF+ CPS3 C12IN3- SRQ — CCP3(2) — — — — N — C1IN+ 2 C1OUT 6 RA4 3 3 28 Y AN4 — CPS4 C2OUT SRNQ T0CKI CCP4(2) — — — — N — / RA5 4 4 1 N — — — — — — — — SS1(1) — — Y(3) MCLR, VPP 2 RA6 15 17 20 N — — — — — — P1D(1) — SDO1(1) — — N OSC2 7 P2B(1,2) CLKOUT CLKR RA7 16 18 21 N — — — — — — P1C(1) — — — — N OSC1 CCP2(1,2) CLKIN P2A(1,2) RB0 6 7 7 N — — — — SRI T1G CCP1(1) — — INT — Y — P1A(1) IOC FLT0 RB1 7 8 8 Y AN11 — CPS11 — — — — RX(1,4) SDA1 IOC — Y — DT(1,4) SDI1 RB2 8 9 9 Y AN10 — CPS10 — — — — RX(1),DT(1) SDA2(2) IOC MDMIN Y — TX(1,4) SDI2(2) CK(1,4) SDO1(1,4) RB3 9 10 10 Y AN9 — CPS9 — — — CCP1(1,4) — — IOC MDOUT Y — P1A(1,4) RB4 10 11 12 Y AN8 — CPS8 — — — — — SCL1 IOC MDCIN2 Y — SCK1 RB5 11 12 13 Y AN7 — CPS7 — — — P1B TX(1) SCL2(2) IOC — Y — CK(1) SCK2(2)  2 SS1(1,4) 01 RB6 12 13 15 Y AN5 — CPS5 — — T1CKI P1C(1,4) — — IOC — Y ICSPCLK/ 1 T1OSI CCP2(1,2,4) ICDCLK M P2A(1,2,4) icro RB7 13 14 16 Y AN6 — CPS6 — — T1OSO P1D(1,4) — — IOC MDCIN1 Y ICSPDAT/ ch P2B(1,2,4) ICDDAT ip T VDD 14 15,16 17,19 — — — — — — — — — — — — — VDD ec Vss 5 5,6 3,5 — — — — — — — — — — — — — VSS h n Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. o lo 2: Functions are only available on the PIC16(L)F1827. g 3: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. y In 4: Default function location. c .

PIC16(L)F1826/27 Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Enhanced Mid-Range CPU........................................................................................................................................................15 3.0 Memory Organization.................................................................................................................................................................17 4.0 Device Configuration..................................................................................................................................................................43 5.0 Oscillator Module (With Fail-Safe Clock Monitor).......................................................................................................................51 6.0 Reference Clock Module............................................................................................................................................................69 7.0 Resets........................................................................................................................................................................................73 8.0 Interrupts....................................................................................................................................................................................81 9.0 Power-Down Mode (Sleep)........................................................................................................................................................95 10.0 Watchdog Timer (WDT).............................................................................................................................................................97 11.0 Data EEPROM and Flash Program Memory Control...............................................................................................................101 12.0 I/O Ports...................................................................................................................................................................................117 13.0 Interrupt-on-Change.................................................................................................................................................................131 14.0 Fixed Voltage Reference (FVR)...............................................................................................................................................135 15.0 Temperature Indicator..............................................................................................................................................................137 16.0 Analog-to-Digital Converter (ADC) Module..............................................................................................................................139 17.0 Digital-to-Analog Converter (DAC) Module..............................................................................................................................153 18.0 SR Latch...................................................................................................................................................................................157 19.0 Comparator Module..................................................................................................................................................................163 20.0 Timer0 Module.........................................................................................................................................................................173 21.0 Timer1 Module.........................................................................................................................................................................177 22.0 Timer2/4/6 Modules..................................................................................................................................................................191 23.0 Data Signal Modulator (DSM)..................................................................................................................................................193 24.0 Capture/Compare/PWM (ECCP1, ECCP2, ECCP3, CCP4) Modules.....................................................................................203 25.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................231 26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................285 27.0 Capacitive Sensing Module......................................................................................................................................................315 28.0 In-Circuit Serial Programming™ (ICSP™)................................................................................................................................321 29.0 Instruction Set Summary..........................................................................................................................................................325 30.0 Electrical Specifications............................................................................................................................................................339 31.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................371 32.0 Development Support...............................................................................................................................................................379 33.0 Packaging Information..............................................................................................................................................................383 Appendix A: Revision History.............................................................................................................................................................393 Appendix B: Device Differences........................................................................................................................................................393 Index..................................................................................................................................................................................................395 The Microchip Web Site.....................................................................................................................................................................403 Customer Change Notification Service..............................................................................................................................................403 Customer Support..............................................................................................................................................................................403 Reader Response..............................................................................................................................................................................404 Product Identification System............................................................................................................................................................405  2011 Microchip Technology Inc. DS41391D-page 7

PIC16(L)F1826/27 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41391D-page 8  2011 Microchip Technology Inc.

PIC16(L)F1826/27 1.0 DEVICE OVERVIEW The PIC16(L)F1826/27 are described within this data sheet. They are available in 18/20/28-pin packages. Figure1-1 shows a block diagram of the PIC16(L)F1826/27 devices. Table1-2 shows the pinout descriptions. Reference Table1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY 6 7 2 2 8 8 1 1 F F Peripheral F/L (L) 6 6 1 1 C C PI PI ADC ● ● Capacitive Sensing Module ● ● Digital-to-Analog Converter (DAC) ● ● Digital Signal Modulator (DSM) ● ● EUSART ● ● Fixed Voltage Reference (FVR) ● ● Reference Clock Module ● ● SR Latch ● ● Capture/Compare/PWM Modules ECCP1 ● ● ECCP2 ● CCP3 ● CCP4 ● Comparators C1 ● ● C2 ● ● Master Synchronous Serial Ports MSSP1 ● ● MSSP2 ● Timers Timer0 ● ● Timer1 ● ● Timer2 ● ● Timer4 ● Timer6 ●  2011 Microchip Technology Inc. DS41391D-page 9

PIC16(L)F1826/27 FIGURE 1-1: PIC16(L)F1826/27 BLOCK DIAGRAM Program Flash Memory RAM EEPROM CLKR Clock Reference OSC2/CLKOUT Timing OSC1/CLKIN Generation PORTA CPU INTRC Oscillator (Figure2-1) PORTB MCLR SR ADC Timer2- Timer0 Timer1 DAC Comparators Latch 10-Bit Types ECCPx CCPx MSSPx Modulator EUSART FVR CapSense Note 1: See applicable chapters for more information on peripherals. 2: See Table1-1 for peripherals available on specific devices. DS41391D-page 10  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/CPS0/C12IN0-/ RA0 TTL CMOS General purpose I/O. SDO2(2) AN0 AN — A/D Channel 0 input. CPS0 AN — Capacitive sensing input 0. C12IN0- AN — Comparator C1 or C2 negative input. SDO2 — CMOS SPI data output. RA1/AN1/CPS1/C12IN1-/SS2(2) RA1 TTL CMOS General purpose I/O. AN1 AN — A/D Channel 1 input. CPS1 AN — Capacitive sensing input 1. C12IN1- AN — Comparator C1 or C2 negative input. SS2 ST — Slave Select input 2. RA2/AN2/CPS2/C12IN2-/ RA2 TTL CMOS General purpose I/O. C12IN+/VREF-/DACOUT AN2 AN — A/D Channel 2 input. CPS2 AN — Capacitive sensing input 2. C12IN2- AN — Comparator C1 or C2 negative input. C12IN+ AN — Comparator C1 or C2 positive input. VREF- AN — A/D Negative Voltage Reference input. DACOUT — AN Voltage Reference output. RA3/AN3/CPS3/C12IN3-/C1IN+/ RA3 TTL CMOS General purpose I/O. VREF+/C1OUT/CCP3(2)/SRQ AN3 AN — A/D Channel 3 input. CPS3 AN — Capacitive sensing input 3. C12IN3- AN — Comparator C1 or C2 negative input. C1IN+ AN — Comparator C1 positive input. VREF+ AN — A/D Voltage Reference input. C1OUT — CMOS Comparator C1 output. CCP3 ST CMOS Capture/Compare/PWM3. SRQ — CMOS SR latch non-inverting output. RA4/AN4/CPS4/C2OUT/T0CKI/ RA4 TTL CMOS General purpose I/O. CCP4(2)/SRNQ AN4 AN — A/D Channel 4 input. CPS4 AN — Capacitive sensing input 4. C2OUT — CMOS Comparator C2 output. T0CKI ST — Timer0 clock input. CCP4 ST CMOS Capture/Compare/PWM4. SRNQ — CMOS SR latch inverting output. RA5/MCLR/VPP/SS1(1,2) RA5 TTL CMOS General purpose I/O. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. SS1 ST — Slave Select input 1. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16(L)F1827. 3: Default function location.  2011 Microchip Technology Inc. DS41391D-page 11

PIC16(L)F1826/27 TABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RA6/OSC2/CLKOUT/CLKR/ RA6 TTL CMOS General purpose I/O. P1D(1)/P2B(1,2)/SDO1(1) OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. CLKR — CMOS Clock Reference Output. P1D — CMOS PWM output. P2B — CMOS PWM output. SDO1 — CMOS SPI data output 1. RA7/OSC1/CLKIN/P1C(1)/ RA7 TTL CMOS General purpose I/O. CCP2(1,2)/P2A(1,2) OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes). CLKIN CMOS — External clock input (EC mode). P1C — CMOS PWM output. CCP2 ST CMOS Capture/Compare/PWM2. P2A — CMOS PWM output. RB0/T1G/CCP1(1)/P1A(1)/INT/ RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. SRI/FLT0 Individually enabled pull-up. T1G ST — Timer1 Gate input. CCP1 ST CMOS Capture/Compare/PWM1. P1A — CMOS PWM output. INT ST — External interrupt. SRI ST — SR latch input. FLT0 ST — ECCP Auto-Shutdown Fault input. RB1/AN11/CPS11/RX(1,3)/ RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. DT(1,3)/SDA1/SDI1 Individually enabled pull-up. AN11 AN — A/D Channel 11 input. CPS11 AN — Capacitive sensing input 11. RX ST — USART asynchronous input. DT ST CMOS USART synchronous data. SDA1 I2C™ OD I2C™ data input/output 1. SDI1 CMOS — SPI data input 1. RB2/AN10/CPS10/MDMIN/ RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. TX(1,3)/CK(1,3)/RX(1)/DT(1)/ Individually enabled pull-up. SDA2(2)/SDI2(2)/SDO1(1,3) AN10 AN — A/D Channel 10 input. CPS10 AN — Capacitive sensing input 10. MDMIN — CMOS Modulator source input. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. RX ST — USART asynchronous input. DT ST CMOS USART synchronous data. SDA2 I2C™ OD I2C™ data input/output 2. SDI2 ST — SPI data input 2. SDO1 — CMOS SPI data output 1. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16(L)F1827. 3: Default function location. DS41391D-page 12  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RB3/AN9/CPS9/MDOUT/ RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. CCP1(1,3)/P1A(1,3) Individually enabled pull-up. AN9 AN — A/D Channel 9 input. CPS9 AN — Capacitive sensing input 9. MDOUT — CMOS Modulator output. CCP1 ST CMOS Capture/Compare/PWM1. P1A — CMOS PWM output. RB4/AN8/CPS8/SCL1/SCK1/ RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. MDCIN2 Individually enabled pull-up. AN8 AN — A/D Channel 8 input. CPS8 AN — Capacitive sensing input 8. SCL1 I2C™ OD I2C™ clock 1. SCK1 ST CMOS SPI clock 1. MDCIN2 ST — Modulator Carrier Input 2. RB5/AN7/CPS7/P1B/TX(1)/CK(1)/ RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. SCL2(2)/SCK2(2)/SS1(1,3) Individually enabled pull-up. AN7 AN — A/D Channel 7 input. CPS7 AN — Capacitive sensing input 7. P1B — CMOS PWM output. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. SCL2 I2C™ OD I2C™ clock 2. SCK2 ST CMOS SPI clock 2. SS1 ST — Slave Select input 1. RB6/AN5/CPS5/T1CKI/T1OSI/ RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. P1C(1,3)/CCP2(1,2,3)/P2A(1,2,3)/ Individually enabled pull-up. ICSPCLK AN5 AN — A/D Channel 5 input. CPS5 AN — Capacitive sensing input 5. T1CKI ST — Timer1 clock input. T1OSO XTAL XTAL Timer1 oscillator connection. P1C — CMOS PWM output. CCP2 ST CMOS Capture/Compare/PWM2. P2A — CMOS PWM output. ICSPCLK ST — Serial Programming Clock. RB7/AN6/CPS6/T1OSO/ RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. P1D(1,3)/P2B(1,2,3)/MDCIN1/ Individually enabled pull-up. ICSPDAT AN6 AN — A/D Channel 6 input. CPS6 AN — Capacitive sensing input 6. T1OSO XTAL XTAL Timer1 oscillator connection. P1D — CMOS PWM output. P2B — CMOS PWM output. MDCIN1 ST — Modulator Carrier Input 1. ICSPDAT ST CMOS ICSP™ Data I/O. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16(L)F1827. 3: Default function location.  2011 Microchip Technology Inc. DS41391D-page 13

PIC16(L)F1826/27 TABLE 1-2: PIC16(L)F1826/27 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16(L)F1827. 3: Default function location. DS41391D-page 14  2011 Microchip Technology Inc.

PIC16(L)F1826/27 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. • Automatic Interrupt Context Saving • 16-level Stack with Overflow and Underflow • File Select Registers • Instruction Set 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section8.5 “Automatic Context Saving”, for more information. 2.2 16-level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Under- flow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a soft- ware Reset. See section Section3.4 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section3.4 “Stack”for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section29.0 “Instruction Set Summary” for more details.  2011 Microchip Technology Inc. DS41391D-page 15

PIC16(L)F1826/27 FIGURE 2-1: CORE BLOCK DIAGRAM 15 CCCooonnnfffiiiggguuurrraaatttiiiooonnn 15 888 DDDaaatttaaa BBBuuusss PPPrrrooogggrrraaammm CCCooouuunnnttteeerrr Flash X U Program M Memory 1886 -LLLeeevvveeell lSS Sttaataccckkk RAM (((111335---bbbiiittt))) PPPrrrooogggrrraaammm 111444 Program Memory 12 RAM Addr BBBuuusss Read (PMR) AAAddddddrrr MMMUUUXXX IIInnnssstttrrruuuccctttiiiooonnn Rrreeeggg Indirect DDDiiirrreeecccttt AAAddddddrrr 777 Addr 5 12 12 15 BFFSSSRRR Rrreeeggg FFFSSSRRR 0rr eeRggeg FFFSSSRRR1 rrReeeggg 15 SSSTTTAAATTTUUUSSS Rrreeeggg 888 333 MMMUUUXXX Power-up Timer IIInnnssstttrrruuuccctttiiiooonnn Oscillator DDDeeecccooodddeee a &&nd Start-up Timer AAALLLUUU CCCooonnntttrrrooolll Power-on OSC1/CLKIN Reset 888 TTTiiimmmiiinnnggg Watchdog OSC2/CLKOUT GGGeeennneeerrraaatttiiiooonnn Timer W reg Brown-out Reset IIInnnttteeerrrnnnaaalll OOOsssccciiillllllaaatttooorrr BBBllloooccckkk VVVDDDDDD VVVSSSSSS DS41391D-page 16  2011 Microchip Technology Inc.

PIC16(L)F1826/27 3.0 MEMORY ORGANIZATION The following features are associated with access and control of program memory and data memory: There are three types of memory in PIC16(L)F1826/27: • PCL and PCLATH Data Memory, Program Memory and Data EEPROM Memory(1). • Stack • Indirect Addressing • Program Memory • Data Memory 3.1 Program Memory Organization - Core Registers - Special Function Registers The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program - General Purpose RAM memory space. Table3-1 shows the memory sizes - Common RAM implemented for the PIC16(L)F1826/27 family. - Device Memory Maps Accessing a location above these boundaries will cause - Special Function Registers Summary a wrap-around within the implemented memory space. • Data EEPROM memory(1) The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures3-1 and3-2). Note1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) Last Program Memory Address PIC16(L)F1826 2,048 07FFh PIC16(L)F1827 4,096 0FFFh  2011 Microchip Technology Inc. DS41391D-page 17

PIC16(L)F1826/27 FIGURE 3-1: PROGRAM MEMORY MAP FIGURE 3-2: PROGRAM MEMORY MAP AND STACK FOR AND STACK FOR PIC16(L)F1826 PIC16(L)F1827 PC<14:0> PC<14:0> CALL, CALLW 15 CALL, CALLW 15 RETURN, RETLW RETURN, RETLW Interrupt, RETFIE Interrupt, RETFIE Stack Level 0 Stack Level 0 Stack Level 1 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h Interrupt Vector 0004h On-chip 0005h 0005h Program Page 0 Page 0 Memory 07FFh On-chip 07FFh Program 0800h 0800h Rollover to Page 0 Memory Wraps to Page 0 Page 1 0FFFh 1000h Rollover to Page 0 Wraps to Page 0 Wraps to Page 0 Rollover to Page 0 Rollover to Page 1 7FFFh 7FFFh DS41391D-page 18  2011 Microchip Technology Inc.

PIC16(L)F1826/27 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in pro- gram memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example3-1. EXAMPLE 3-1: RETLW INSTRUCTION constants BRW ;Add Index in W to ;program counter to ;select data RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very sim- ple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used.  2011 Microchip Technology Inc. DS41391D-page 19

PIC16(L)F1826/27 3.1.1.2 Indirect Read with FSR 3.2.1 CORE REGISTERS The program memory can be accessed as data by set- The core registers contain the registers that directly ting bit 7 of the FSRxH register and reading the match- affect the basic operation. The core registers occupy ing INDFx register. The MOVIW instruction will place the the first 12 addresses of every data memory bank lower 8 bits of the addressed word in the W register. (addresses x00h/x08h through x0Bh/x8Bh). These Writes to the program memory cannot be performed via registers are listed below in Table3-2. For for detailed the INDF registers. Instructions that access the pro- information, see Table3-5. gram memory via the FSR require one extra instruction cycle to complete. Example3-2 demonstrates access- TABLE 3-2: CORE REGISTERS ing the program memory via an FSR. The HIGH directive will set bit<7> if a label points to a location in program memory. Addresses BANKx x00h or x80h INDF0 EXAMPLE 3-2: ACCESSING PROGRAM x01h or x81h INDF1 MEMORY VIA FSR x02h or x82h PCL constants x03h or x83h STATUS RETLW DATA0 ;Index0 data x04h or x84h FSR0L RETLW DATA1 ;Index1 data x05h or x85h FSR0H RETLW DATA2 x06h or x86h FSR1L RETLW DATA3 my_function x07h or x87h FSR1H ;… LOTS OF CODE… x08h or x88h BSR MOVLW LOW constants x09h or x89h WREG MOVWF FSR1L x0Ah or x8Ah PCLATH MOVLW HIGH constants x0Bh or x8Bh INTCON MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure3-3): • 12 core registers • 20 Special Function Registers (SFR) • Up to 80 bytes of General Purpose RAM (GPR) • 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section3.5 “Indirect Addressing” for more information. Data Memory uses a 12-bit address. The upper 7-bit of the address define the Bank address and the lower 5-bits select the registers/RAM in that bank. DS41391D-page 20  2011 Microchip Technology Inc.

PIC16(L)F1826/27 3.2.1.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register3-1, contains: as ‘000u u1uu’ (where u = unchanged). • the arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, • the Reset status SWAPF and MOVWF instructions are used to alter the The STATUS register can be the destination for any STATUS register, because these instructions do not instruction, like any other register. If the STATUS affect any Status bits. For other instructions not register is the destination for an instruction that affects affecting any Status bits (Refer to Section29.0 the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”). disabled. These bits are set or cleared according to the Note1: The C and DC bits operate as Borrow device logic. Furthermore, the TO and PD bits are not and Digit Borrow out bits, respectively, in writable. Therefore, the result of an instruction with the subtraction. STATUS register as destination may be different than intended. REGISTER 3-1: STATUS: STATUS REGISTER U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — — — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.  2011 Microchip Technology Inc. DS41391D-page 21

PIC16(L)F1826/27 3.2.2 SPECIAL FUNCTION REGISTER FIGURE 3-3: BANKED MEMORY PARTITIONING The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function 7-bit Bank Offset Memory Region Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the 00h operation of the peripherals are described in the Core Registers appropriate peripheral chapter of this data sheet. (12 bytes) 0Bh 3.2.3 GENERAL PURPOSE RAM 0Ch There are up to 80bytes of GPR in each data memory Special Function Registers bank. The Special Function Registers occupy the 20 (20 bytes maximum) bytes after the core registers of every data memory 1Fh bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 20h 3.2.3.1 Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section3.5.2 “Linear Data Memory” for more information. General Purpose RAM (80 bytes maximum) 3.2.4 COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table3-3 and Table3-4. DS41391D-page 22  2011 Microchip Technology Inc.

 TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP 20 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 1 1 000h 080h 100h 180h 200h 280h 300h 380h M Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers icro (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) c h 00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh ip T 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch — 30Ch — 38Ch — e 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 30Dh — 38Dh — c h 00Eh — 08Eh — 10Eh — 18Eh — 20Eh — 28Eh — 30Eh — 38Eh — n o 00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh — log 010h — 090h — 110h — 190h — 210h — 290h — 310h — 390h — y In 011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSP1BUF 291h CCPR1L 311h CCPR3L(1) 391h — c. 012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSP1ADD 292h CCPR1H 312h CCPR3H(1) 392h — 013h PIR3(1) 093h PIE3(1) 113h CM2CON0 193h EEDATL 213h SSP1MASK 293h CCP1CON 313h CCP3CON(1) 393h — 014h PIR4(1) 094h PIE4(1) 114h CM2CON1 194h EEDATH 214h SSP1STAT 294h PWM1CON 314h — 394h IOCBP 015h TMR0 095h OPTION 115h CMOUT 195h EECON1 215h SSP1CON 295h CCP1AS 315h — 395h IOCBN 016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSP1CON2 296h PSTR1CON 316h — 396h IOCBF 017h TMR1H 097h WDTCON 117h FVRCON 197h — 217h SSP1CON3 297h — 317h — 397h — 018h T1CON 098h OSCTUNE 118h DACCON0 198h — 218h — 298h CCPR2L(1) 318h CCPR4L(1) 398h — 019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h SSP2BUF(1) 299h CCPR2H(1) 319h CCPR4H(1) 399h — 01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah SSP2ADD(1) 29Ah CCP2CON(1) 31Ah CCP4CON(1) 39Ah CLKRCON 01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh SSP2MASK(1) 29Bh PWM2CON(1) 31Bh — 39Bh — 01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch SSP2STAT(1) 29Ch CCP2AS(1) 31Ch — 39Ch MDCON 01Dh — 09Dh ADCON0 11Dh APFCON0 19Dh RCSTA 21Dh SSP2CON(1) 29Dh PSTR2CON(1) 31Dh — 39Dh MDSRC 01Eh CPSCON0 09Eh ADCON1 11Eh APFCON1 19Eh TXSTA 21Eh SSP2CON2(1) 29Eh CCPTMRS(1) 31Eh — 39Eh MDCARL 01Fh CPSCON1 09Fh — 11Fh — 19Fh BAUDCON 21Fh SSP2CON3(1) 29Fh — 31Fh — 39Fh MDCARH 020h 0A0h 120h 1A0h 220h General 2A0h 320h 3A0h Purpose General General General Register Purpose Purpose Purpose 48 Bytes(1) Unimplemented Unimplemented Unimplemented General Register Register Register Read as ‘0’ Read as ‘0’ Read as ‘0’ Purpose 80 Bytes 80 Bytes 80 Bytes(1) Unimplemented P 06Fh Register 0EFh 16Fh 1EFh 26Fh Read as ‘0’ 2EFh 36Fh 3EFh I 070h 96 Bytes 0F0h 170h 1F0h 270h 2F0h 370h 3F0h C Accesses Accesses Accesses Accesses Accesses Accesses Accesses 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 1 07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh 6 ( Legend: = Unimplemented data memory locations, read as ‘0’ L Note 1: Available only on PIC16(L)F1827. ) F 1 D S 8 4 1 2 3 9 1 6 D -p / a 2 g e 2 7 3

D TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP (CONTINUED) P S 41 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 I 3 C 91 400h 480h 500h 580h 600h 680h 700h 780h D-p Co(rTea bRleeg3is-2te)rs Co(rTea bRleeg3is-2te)rs Co(rTea bRleeg3is-2te)rs Co(rTea bRleeg3is-2te)rs Co(rTea bRleeg3is-2te)rs Co(rTea bRleeg3is-2te)rs Co(rTea bRleeg3is-2te)rs Co(rTea bRleeg3is-2te)rs 1 age 40Bh 48Bh 50Bh 58Bh 60Bh 68Bh 70Bh 78Bh 6 2 40Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch — ( 4 L 40Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh — 40Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70Eh — 78Eh — ) 40Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh — 78Fh — F 410h — 490h — 510h — 590h — 610h — 690h — 710h — 790h — 1 411h — 491h — 511h — 591h — 611h — 691h — 711h — 791h — 8 412h — 492h — 512h — 592h — 612h — 692h — 712h — 792h — 2 413h — 493h — 513h — 593h — 613h — 693h — 713h — 793h — 414h — 494h — 514h — 594h — 614h — 694h — 714h — 794h — 6 415h TMR4(1) 495h — 515h — 595h — 615h — 695h — 715h — 795h — / 2 416h PR4(1) 496h — 516h — 596h — 616h — 696h — 716h — 796h — 7 417h T4CON(1) 497h — 517h — 597h — 617h — 697h — 717h — 797h — 418h — 498h — 518h — 598h — 618h — 698h — 718h — 798h — 419h — 499h — 519h — 599h — 619h — 699h — 719h — 799h — 41Ah — 49Ah — 51Ah — 59Ah — 61Ah — 69Ah — 71Ah — 79Ah — 41Bh — 49Bh — 51Bh — 59Bh — 61Bh — 69Bh — 71Bh — 79Bh — 41Ch TMR6(1) 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch — 41Dh PR6(1) 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh — 41Eh T6CON(1) 49Eh — 51Eh — 59Eh — 61Eh — 69Eh — 71Eh — 79Eh — 41Fh — 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh — 420h 4A0h 520h 5A0h 620h 6A0h 720h 7A0h Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh 470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses  2 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 01 47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh 1 M Legend: = Unimplemented data memory locations, read as ‘0’ ic ro c h ip T e c h n o lo g y In c .

 TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP (CONTINUED) 2 0 1 BANK16 BANK17 BANK18 BANK19 BANK20 BANK21 BANK22 BANK23 1 M 800h 880h 900h 980h A00h A80h B00h B80h icro Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers c (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) h ip 80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh Te 80Ch 88Ch 90Ch 98Ch A0Ch A8Ch B0Ch B8Ch ch Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented no Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ log 86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh y In 870h Common RAM 8F0h Common RAM 970h Common RAM 9F0h Common RAM A70h Common RAM AF0h Common RAM B70h Common RAM BF0h Common RAM c . (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31 C00h C80h D00h D80h E00h E80h F00h F80h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh F8Bh C0Ch C8Ch D0Ch D8Ch E0Ch E8Ch F0Ch F8Ch Unimplemented Read as ‘0’ Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented F9Fh Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ FA0h See Table3-4 for more information C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh C70h CF0h D70h DF0h E70h EF0h F70h FF0h Common RAM Common RAM Accesses Accesses Accesses Accesses Accesses Accesses (Accesses (Accesses P 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh) 70h – 7Fh) C7Fh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh I C Legend: = Unimplemented data memory locations, read as ‘0’ 1 6 ( L ) F 1 D S 8 4 1 2 3 9 1 6 D -p / a 2 g e 2 7 5

PIC16(L)F1826/27 TABLE 3-4: PIC16(L)F1826/27 MEMORY MAP (CONTINUED) Bank 31 F80h Core Registers (Table3-2) F8Bh F8Ch Unimplemented Read as ‘0’ FE3h FE4h STATUS_SHAD FE5h WREG_SHAD FE6h BSR_SHAD FE7h PCLATH_SHAD FE8h FSR0L_SHAD FE9h FSR0H_SHAD FEAh FSR1L_SHAD FEBh FSR1H_SHAD FECh — FEDh STKPTR FEEh TOSL FEFh TOSH FF0h Common RAM (Accesses 70h – 7Fh) FFFh = Unimplemented data memory locations, read as ‘0’, DS41391D-page 26  2011 Microchip Technology Inc.

PIC16(L)F1826/27 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table3-5 can be addressed from any Bank. TABLE 3-5: CORE FUNCTION REGISTERS SUMMARY Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 0-31 x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory INDF0 xxxx xxxx uuuu uuuu x80h (not a physical register) x01h or Addressing this location uses contents of FSR1H/FSR1L to address data memory INDF1 xxxx xxxx uuuu uuuu x81h (not a physical register) x02h or PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x82h x03h or STATUS — — — TO PD Z DC C ---1 1000 ---q quuu x83h x04h or FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x84h x05h or FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x85h x06h or FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x86h x07h or FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x87h x08h or BSR — — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 x88h x09h or WREG Working Register 0000 0000 uuuu uuuu x89h x0Ah or PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 x8Ah x0Bh or INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 x8Bh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’.  2011 Microchip Technology Inc. DS41391D-page 27

PIC16(L)F1826/27 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 0 00Ch PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx xxxx xxxx 00Dh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx xxxx xxxx 00Eh — Unimplemented — — 00Fh — Unimplemented — — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF(1) 0000 0--0 0000 0--0 013h PIR3(1) — — CCP4IF CCP3IF TMR6IF — TMR4IF — --00 0-0- --00 0-0- 014h PIR4(1) — — — — — — BCL2IF SSP2IF ---- --00 ---- --00 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 018h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 0000 00-0 uuuu uu-u 019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu DONE 01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000 01Bh PR2 Timer2 Period Register 1111 1111 1111 1111 01Ch T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 01Dh — Unimplemented — — 01Eh CPSCON0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 0--- 0000 01Fh CPSCON1 — — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 ---- 0000 ---- 0000 Bank 1 08Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 08Eh — Unimplemented — — 08Fh — Unimplemented — — 090h — Unimplemented — — 091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 092h PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE(1) 0000 0--0 0000 0--0 093h PIE3(1) — — CCP4IE CCP3IE TMR6IE — TMR4IE — --00 0-0- --00 0-0- 094h PIE4(1) — — — — — — BCL2IE SSP2IE ---- --00 ---- --00 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 096h PCON STKOVF STKUNF — — RMCLR RI POR BOR 00-- 11qq qq-- qquu 097h WDTCON — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110 098h OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --00 0000 099h OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0 — SCS1 SCS0 0011 1-00 0011 1-00 09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q 09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu 09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu 09Dh ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON -000 0000 -000 0000 09Eh ADCON1 ADFM ADCS2 ADCS1 ADCS0 — ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000 09Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1827 only. DS41391D-page 28  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 2 10Ch LATA LATA7 LATA6 — LATA4 LATA3 LATA2 LATA1 LATA0 xx-x xxxx uu-u uuuu 10Dh LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx uuuu uuuu 10Eh — Unimplemented — — 10Fh — Unimplemented — — 110h — Unimplemented — — 111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100 112h CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 — — C1NCH<1:0> 0000 --00 0000 --00 113h CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 0000 -100 0000 -100 114h CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0 — — C2NCH1 C2NCH0 0000 --00 0000 --00 115h CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00 116h BORCON SBOREN — — — — — — BORRDY 1--- ---q u--- ---u 117h FVRCON FVREN FVRRDY Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 0qrr 0000 0qrr 0000 118h DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — DACNSS 000- 00-0 000- 00-0 119h DACCON1 — — — DACR4 DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 0000 11Ah SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000 11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000 11Ch — Unimplemented — — 11Dh APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(1) CCP2SEL(1) P1DSEL P1CSEL CCP1SEL 0000 0000 0000 0000 11Eh APFCON1 — — — — — — — TXCKSEL ---- ---0 ---- ---0 11Fh — Unimplemented — — Bank 3 18Ch ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 ---1 1111 ---1 1111 18Dh ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — 1111 111- 1111 111- 18Eh — Unimplemented — — 18Fh — Unimplemented — — 190h — Unimplemented — — 191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000 192h EEADRH — EEPROM / Program Memory Address Register High Byte -000 0000 -000 0000 193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu 194h EEDATH — — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu 195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000 196h EECON2 EEPROM control register 2 0000 0000 0000 0000 197h — Unimplemented — — 198h — Unimplemented — — 199h RCREG USART Receive Data Register 0000 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000 19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 29

PIC16(L)F1826/27 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 4 20Ch WPUA — — WPUA5 — — — — — --1- ---- --1- ---- 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 20Eh — Unimplemented — — 20Fh — Unimplemented — — 210h — Unimplemented — — 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 0000 0000 0000 0000 213h SSP1MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111 214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h — Unimplemented — — 219h SSP2BUF(1) Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 21Ah SSP2ADD(1) ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 0000 0000 0000 0000 21Bh SSP2MSK(1) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111 21Ch SSP2STAT(1) SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 21Dh SSP2CON1(1) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 21Eh SSP2CON2(1) GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 21Fh SSP2CON3(1) ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 Bank 5 28Ch — Unimplemented — — 28Dh — Unimplemented — — 28Eh — Unimplemented — — 28Fh — Unimplemented — — 290h — Unimplemented — — 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 293h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 294h PWM1CON P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 0000 0000 295h CCP1AS CCP1ASE CCP1AS2 CCP1AS1 CCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000 296h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001 297h — Unimplemented — — 298h CCPR2L(1) Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu 299h CCPR2H(1) Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu 29Ah CCP2CON(1) P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000 29Bh PWM2CON(1) P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 0000 0000 29Ch CCP2AS(1) CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000 29Dh PSTR2CON(1) — — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001 29Eh CCPTMRS(1) C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000 29Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1827 only. DS41391D-page 30  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 6 30Ch — Unimplemented — — 30Dh — Unimplemented — — 30Eh — Unimplemented — — 30Fh — Unimplemented — — 310h — Unimplemented — — 311h CCPR3L(1) Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu 312h CCPR3H(1) Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu 313h CCP3CON(1) — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000 314h — Unimplemented — — 315h — Unimplemented — — 316h — Unimplemented — — 317h — Unimplemented — — 318h CCPR4L(1) Capture/Compare/PWM Register 4 (LSB) xxxx xxxx uuuu uuuu 319h CCPR4H(1) Capture/Compare/PWM Register 4 (MSB) xxxx xxxx uuuu uuuu 31Ah CCP4CON(1) — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000 31Bh — Unimplemented — — 31Ch — Unimplemented — — 31Dh — Unimplemented — — 31Eh — Unimplemented — — 31Fh — Unimplemented — — Bank 7 38Ch — Unimplemented — — 38Dh — Unimplemented — — 38Eh — Unimplemented — — 38Fh — Unimplemented — — 390h — Unimplemented — — 391h — Unimplemented — — 392h — Unimplemented — — 393h — Unimplemented — — 394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000 395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000 396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000 397h — Unimplemented — — 398h — Unimplemented — — 399h — Unimplemented — — 39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC1 CLKRDC0 CLKRDIV2 CLKRDIV1 CLKRDIV0 0011 0000 0011 0000 39Bh — Unimplemented — — 39Ch MDCON MDEN MDOE MDSLR MDOPOL — — — MDBIT 0010 ---0 0010 ---0 39Dh MDSRC MDMSODIS — — — MDMS3 MDMS2 MDMS1 MDMS0 x--- xxxx u--- uuuu 39Eh MDCARL MDCLODIS MDCLPOL MDCLSYNC — MDCL3 MDCL2 MDCL1 MDCL0 xxx- xxxx uuu- uuuu 39Fh MDCARH MDCHODIS MDCHPOL MDCHSYNC — MDCH3 MDCH2 MDCH1 MDCH0 xxx- xxxx uuu- uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 31

PIC16(L)F1826/27 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 8 40Ch — Unimplemented — — 40Dh — Unimplemented — — 40Eh — Unimplemented — — 40Fh — Unimplemented — — 410h — Unimplemented — — 411h — Unimplemented — — 412h — Unimplemented — — 413h — Unimplemented — — 414h — Unimplemented — — 415h TMR4(1) Timer4 Module Register 0000 0000 0000 0000 416h PR4(1) Timer4 Period Register 1111 1111 1111 1111 417h T4CON(1) — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000 418h — Unimplemented — — 419h — Unimplemented — — 41Ah — Unimplemented — — 41Bh — Unimplemented — — 41Ch TMR6(1) Timer6 Module Register 0000 0000 0000 0000 41Dh PR6(1) Timer6 Period Register 1111 1111 1111 1111 41Eh T6CON(1) — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 -000 0000 -000 0000 41Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1827 only. DS41391D-page 32  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 9 48Ch — Unimplemented — — — 49Fh Bank 10 50Ch — Unimplemented — — — 51Fh Bank 11 58Ch — Unimplemented — — — 59Fh Bank 12 60Ch — Unimplemented — — — 61Fh Bank 13 68Ch — Unimplemented — — — 69Fh Bank 14 70Ch — Unimplemented — — — 71Fh Bank 15 78Ch — Unimplemented — — — 79Fh Bank 16 80Ch — Unimplemented — — — 86Fh Bank 17 88Ch — Unimplemented — — — 8EFh Bank 18 90Ch — Unimplemented — — — 96Fh Bank 19 98Ch — Unimplemented — — — 9EFh Bank 20 A0Ch — Unimplemented — — — A6Fh Bank 21 A8Ch — Unimplemented — — — AEFh Bank 22 B0Ch — Unimplemented — — — B6Fh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 33

PIC16(L)F1826/27 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 23 B8Ch — Unimplemented — — — BEFh Bank 24 C0Ch — Unimplemented — — — C6Fh Bank 25 C8Ch — Unimplemented — — — CEFh Bank 26 D0Ch — Unimplemented — — — D6Fh Bank 27 D8Ch — Unimplemented — — — DEFh Bank 28 E0Ch — Unimplemented — — — E6Fh Bank 29 E8Ch — Unimplemented — — — EEFh Bank 30 F0Ch — Unimplemented — — — F6Fh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1827 only. DS41391D-page 34  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 31 F8Ch — Unimplemented — — — FE3h FE4h STATUS_ — — — — — Z_SHAD DC_ C_SHAD ---- -xxx ---- -uuu SHAD SHAD FE5h WREG_ Working Register Shadow 0000 0000 uuuu uuuu SHAD FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu SHAD FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu SHAD FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FECh — Unimplemented — — FEDh STKPTR — — — Current Stack pointer ---1 1111 ---1 1111 FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu uuuu FEFh TOSH — Top-of-Stack High byte -xxx xxxx -uuu uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 35

PIC16(L)F1826/27 3.3 PCL and PCLATH 3.3.3 COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte A computed function CALL allows programs to maintain comes from the PCL register, which is a readable and tables of functions and provide another way to execute writable register. The high byte (PC<14:8>) is not directly state machines or look-up tables. When performing a readable or writable and comes from PCLATH. On any table read using a computed function CALL, care Reset, the PC is cleared. Figure3-4 shows the five should be exercised if the table location crosses a PCL situations for the loading of the PC. memory boundary (each 256-byte block). If using the CALL instruction, the PCH<2:0> and PCL FIGURE 3-4: LOADING OF PC IN registers are loaded with the operand of the CALL DIFFERENT SITUATIONS instruction. PCH<6:3> is loaded with PCLATH<6:3>. The CALLW instruction enables computed calls by com- 14 PCH PCL 0 Instruction with PC PCL as bining PCLATH and W to form the destination address. Destination A computed CALLW is accomplished by loading the W 6 7 0 8 register with the desired address and executing CALLW. PCLATH ALU Result The PCL register is loaded with the value of W and PCH is loaded with PCLATH. 14 PCH PCL 0 3.3.4 BRANCHING PC GOTO, CALL The branching instructions add an offset to the PC. 6 4 0 11 This allows relocatable code and code that crosses PCLATH OPCODE <10:0> page boundaries. There are two forms of branching, 14 PCH PCL 0 BRW and BRA. The PC will have incremented to fetch PC CALLW the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be 6 7 0 8 crossed. PCLATH W If using BRW, load the W register with the desired 14 PCH PCL 0 unsigned address and execute BRW. The entire PC will PC BRW be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC+1+, 15 PC + W the signed value of the operand of the BRA instruction. 14 PCH PCL 0 PC BRA 15 PC + OPCODE <8:0> 3.3.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Coun- ter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter will change to the values con- tained in the PCLATH register and those being written to the PCL register. 3.3.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556). DS41391D-page 36  2011 Microchip Technology Inc.

PIC16(L)F1826/27 3.4 Stack 3.4.1 ACCESSING THE STACK All devices have a 16-levelx15-bit wide hardware The stack is available through the TOSH, TOSL and stack (refer to Figures3-5 through3-8). The stack STKPTR registers. STKPTR is the current value of the space is not part of either program or data space. The Stack Pointer. TOSH:TOSL register pair points to the PC is PUSHed onto the stack when CALL or CALLW TOP of the stack. Both registers are read/writable. TOS instructions are executed or an interrupt causes a is split into TOSH and TOSL due to the 15-bit size of the branch. The stack is POPed in the event of a RETURN, PC. To access the stack, adjust the value of STKPTR, RETLW or a RETFIE instruction execution. PCLATH is which will position TOSH:TOSL, then read/write to not affected by a PUSH or POP operation. TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Word 2). This Note: Care should be taken when modifying the means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled. times, the seventeenth PUSH overwrites the value that During normal program operation, CALL, CALLW and was stored from the first PUSH. The eighteenth PUSH Interrupts will increment STKPTR while RETLW, overwrites the second PUSH (and so on). The RETURN, and RETFIE will decrement STKPTR. At any STKOVF and STKUNF flag bits will be set on an Over- time STKPTR can be inspected to see how much stack flow/Underflow, regardless of whether the Reset is is left. The STKPTR always points at the currently used enabled. place on the stack. Therefore, a CALL or CALLW will Note1: There are no instructions/mnemonics increment the STKPTR and then write the PC, and a called PUSH or POP. These are actions return will unload the PC and then decrement STKPTR. that occur from the execution of the Reference Figure3-5 through Figure3-8 for examples CALL, CALLW, RETURN, RETLW and of accessing the stack. RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1 Stack Reset Disabled TOSH:TOSL 0x0F STKPTR = 0x1F (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 Initial Stack Configuration: 0x08 After Reset, the stack is empty. The empty stack is initialized so the Stack 0x07 Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the 0x06 TOSH/TOSL registers will return ‘0’. If 0x05 the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will 0x04 return the contents of stack address 0x0F. 0x03 0x02 0x01 0x00 Stack Reset Enabled TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F (STVREN = 1)  2011 Microchip Technology Inc. DS41391D-page 37

PIC16(L)F1826/27 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A This figure shows the stack configuration 0x09 after the first CALL or a single interrupt. If a RETURN instruction is executed, the 0x08 return address will be placed in the Program Counter and the Stack Pointer 0x07 decremented to the empty state (0x1F). 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL 0x00 Return Address STKPTR = 0x00 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs, or six CALLs and an interrupt, the stack looks like the figure 0x0B on the left. A series of RETURN instructions 0x0A will repeatedly place the return addresses into the Program Counter and pop the stack. 0x09 0x08 0x07 TOSH:TOSL 0x06 Return Address STKPTR = 0x06 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address DS41391D-page 38  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address When the stack is full, the next CALL or interrupt will set the Stack Pointer to 0x09 Return Address 0x10. This is identical to address 0x00 0x08 Return Address so the stack will wrap and overwrite the return address at 0x00. If the Stack 0x07 Return Address Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will 0x06 Return Address not be overwritten. 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address TOSH:TOSL 0x00 Return Address STKPTR = 0x10 3.4.2 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Word 2 is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.5 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2011 Microchip Technology Inc. DS41391D-page 39

PIC16(L)F1826/27 FIGURE 3-9: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Reserved 0x7FFF Address Range 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41391D-page 40  2011 Microchip Technology Inc.

PIC16(L)F1826/27 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing Indirect Addressing 4 BSR 0 6 From Opcode 0 7 FSRxH 0 7 FSRxL 0 0 0 0 0 Bank Select Location Select Bank Select Location Select 0000 0001 0010 1111 0x00 0x7F Bank 0 Bank 1 Bank 2 Bank 31  2011 Microchip Technology Inc. DS41391D-page 41

PIC16(L)F1826/27 3.5.2 LINEAR DATA MEMORY 3.5.3 PROGRAM FLASH MEMORY The linear data memory is the region from FSR To make constant data access easier, the entire address 0x2000 to FSR address 0x29AF. This region is program Flash memory is mapped to the upper half of a virtual region that points back to the 80-byte blocks of the FSR address space. When the MSB of FSRnH is GPR memory in all the banks. set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the Unimplemented memory reads as 0x00. Use of the lower 8 bits of each memory location is accessible via linear data memory region allows buffers to be larger INDF. Writing to the program Flash memory cannot be than 80 bytes because incrementing the FSR beyond accomplished via the FSR/INDF interface. All one bank will go directly to the GPR memory of the next instructions that access program Flash memory via the bank. FSR/INDF interface will require one additional The 16 bytes of common memory are not included in instruction cycle to complete. the linear data memory region. FIGURE 3-12: PROGRAM FLASH FIGURE 3-11: LINEAR DATA MEMORY MEMORY MAP MAP 7 FSRnH 0 7 FSRnL 0 7 FSRnH 0 7 FSRnL 0 1 0 0 1 Location Select 0x8000 0x0000 Location Select 0x2000 0x020 Bank 0 0x06F 0x0A0 Bank 1 Program 0x0EF Flash 0x120 Memory (low 8 Bank 2 bits) 0x16F 0xF20 Bank 30 0xFFFF 0x7FFF 0x29AF 0xF6F DS41391D-page 42  2011 Microchip Technology Inc.

PIC16(L)F1826/27 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'.  2011 Microchip Technology Inc. DS41391D-page 43

PIC16(L)F1826/27 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1/1 FCMEN IESO CLKOUTEN BOREN<1:0> CPD bit 13 bit 8 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit If FOSC configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin. All other FOSC modes: 1 =CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 =CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 7 CP: Code Protection bit 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 =MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 =MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit. bit 5 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 =WDT enabled 10 =WDT enabled while running and disabled in Sleep 01 =WDT controlled by the SWDTEN bit in the WDTCON register 00 =WDT disabled DS41391D-page 44  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 4-1: CONFIGURATION WORD 1 (CONTINUED) bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins  2011 Microchip Technology Inc. DS41391D-page 45

PIC16(L)F1826/27 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1/1 LVP(1) DEBUG(2) — BORV STVREN PLLEN bit 13 bit 8 U-1 U-1 U-1 R/P-1/1 U-1 U-1 R/P-1 R/P-1 — — — Reserved — — WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 Unimplemented: Read as ‘1’ bit 10 BORV: Brown-out Reset Voltage Selection bit 1 = Brown-out Reset voltage set to 1.9V (typical) 0 = Brown-out Reset voltage set to 2.5V (typical) bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7-5 Unimplemented: Read as ‘1’ bit 4 Reserved: This location should be programmed to a ‘1’. bit 3-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 2 kW Flash memory (PIC16(L)F1826 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control 00 = 000h to 7FFh write-protected, no addresses may be modified by EECON control 4 kW Flash memory (PIC16(L)F1827 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write-protected, no addresses may be modified by EECON control Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. 2: The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. DS41391D-page 46  2011 Microchip Technology Inc.

PIC16(L)F1826/27 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word 1. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section4.3 “Write Protection” for more information. 4.2.2 DATA EEPROM PROTECTION The entire data EEPROM is protected from external reads and writes by the CPD bit. When CPD = 0, exter- nal reads and writes of data EEPROM are inhibited. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 4.3 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot- loader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Word 2 define the size of the program memory block that is protected. 4.4 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F/LF1826/27 Memory Programming Specification” (DS41390).  2011 Microchip Technology Inc. DS41391D-page 47

PIC16(L)F1826/27 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. DS41391D-page 48  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 4-3: DEVICEID: DEVICE ID REGISTER(1) R R R R R R DEV<8:3> bit 13 bit 8 R R R R R R R R DEV<2:0> REV<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bit bit 13-5 DEV<8:0>: Device ID bits DEVICEID<13:0> Values Device DEV<8:0> REV<4:0> PIC16F1826 10 0111 100 x xxxx PIC16F1827 10 0111 101 x xxxx PIC16LF1826 10 1000 100 x xxxx PIC16LF1827 10 1000 101 x xxxx bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. Note 1: This location cannot be written.  2011 Microchip Technology Inc. DS41391D-page 49

PIC16(L)F1826/27 NOTES: DS41391D-page 50  2011 Microchip Technology Inc.

PIC16(L)F1826/27 5.0OSCILLATOR MODULE (WITH The oscillator module can be configured in one of eight FAIL-SAFE CLOCK MONITOR) clock modes. 1. ECL – External Clock Low-Power mode 5.1 Overview (0MHz to 0.5MHz) 2. ECM – External Clock Medium-Power mode The oscillator module has a wide variety of clock (0.5MHz to 4MHz) sources and selection features that allow it to be used 3. ECH – External Clock High-Power mode in a wide range of applications while maximizing perfor- (4MHz to 32MHz) mance and minimizing power consumption. Figure5-1 4. LP – 32kHz Low-Power Crystal mode. illustrates a block diagram of the oscillator module. 5. XT – Medium Gain Crystal or Ceramic Resonator Clock sources can be supplied from external oscillators, Oscillator mode (up to 4 MHz) quartz crystal resonators, ceramic resonators and 6. HS – High Gain Crystal or Ceramic Resonator Resistor-Capacitor (RC) circuits. In addition, the system mode (4 MHz to 20 MHz) clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds 7. RC – External Resistor-Capacitor (RC). selectable via software. Additional clock features 8. INTOSC – Internal oscillator (31kHz to 32 MHz). include: Clock Source modes are selected by the FOSC<2:0> • Selectable system clock source between external bits in the Configuration Word 1. The FOSC bits or internal sources via software. determine the type of oscillator that will be used when • Two-Speed Start-up mode, which minimizes the device is first powered. latency between external oscillator start-up and The EC clock mode relies on an external logic level code execution. signal as the device clock source. The LP, XT, and HS • Fail-Safe Clock Monitor (FSCM) designed to clock modes require an external crystal or resonator to detect a failure of the external clock source (LP, be connected to the device. Each mode is optimized for XT, HS, EC or RC modes) and switch a different frequency range. The RC clock mode automatically to the internal oscillator. requires an external resistor and capacitor to set the • Oscillator Start-up Timer (OST) ensures stability oscillator frequency. of crystal oscillator sources The INTOSC internal oscillator block produces low, medium, and high frequency clock sources, designated LFINTOSC, MFINTOSC, and HFINTOSC. (see Internal Oscillator Block, Figure5-1). A wide selection of device clock frequencies may be derived from these three clock sources.  2011 Microchip Technology Inc. DS41391D-page 51

PIC16(L)F1826/27 FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM External Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL Sleep OSC1 Oscillator Timer1 FOSC<2:0> = 100 T1OSC X CPU and T1OSO U Peripherals M T1OSCEN Enable T1OSI Oscillator IRCF<3:0> Internal Oscillator 16 MHz 8 MHz Internal Oscillator 4 MHz Block 2 MHz er 1 MHz Clock HFPLL 16 MHz scal 500 kHz UX Control (HFINTOSC) ost 250 kHz M P 125 kHz FOSC<2:0> SCS<1:0> 500 kHz Source 500 kHz 62.5 kHz (MFINTOSC) 31.25 kHz Clock Source Option for other modules 31 kHz 31 kHz Source 31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules DS41391D-page 52  2011 Microchip Technology Inc.

PIC16(L)F1826/27 5.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully clock source to function. Examples are: oscillator mod- static, stopping the external clock input will have the ules (EC mode), quartz crystal resonators or ceramic effect of halting the device while leaving all data intact. resonators (LP, XT and HS modes) and Resis- Upon restarting the external clock, the device will tor-Capacitor (RC) mode circuits. resume operation as if no time had elapsed. Internal clock sources are contained internally within FIGURE 5-2: EXTERNAL CLOCK (EC) the oscillator module. The internal oscillator block has MODE OPERATION two internal oscillators and a dedicated Phase-Lock Loop (HFPLL) that are used to generate three internal system clock sources: the 16MHz High-Frequency Clock from OSC1/CLKIN Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) Ext. System and the 31kHz Low-Frequency Internal Oscillator PIC® MCU (LFINTOSC). OSC2/CLKOUT The system clock can be selected between external or FOSC/4 or I/O(1) internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section5.3 Note 1: Output depends upon CLKOUTEN bit of the “Clock Switching” for additional information. Configuration Word 1. 5.2.1 EXTERNAL CLOCK SOURCES 5.2.1.2 LP, XT, HS Modes An external clock source can be used as the device system clock by performing one of the following The LP, XT and HS modes support the use of quartz actions: crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure5-3). The three modes select • Program the FOSC<2:0> bits in the Configuration a low, medium or high gain setting of the internal Word 1 to select an external clock source that will inverter-amplifier to support various resonator types be used as the default system clock upon a and speed. device Reset. • Write the SCS<1:0> bits in the OSCCON register LP Oscillator mode selects the lowest gain setting of the to switch the system clock source to: internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to - Timer1 Oscillator during run-time, or drive only 32.768 kHz tuning-fork type crystals (watch - An external clock source determined by the crystals). value of the FOSC bits. XT Oscillator mode selects the intermediate gain See Section5.3 “Clock Switching”for more informa- setting of the internal inverter-amplifier. XT mode tion. current consumption is the medium of the three modes. This mode is best suited to drive resonators with a 5.2.1.1 EC Mode medium drive level specification. The External Clock (EC) mode allows an externally HS Oscillator mode selects the highest gain setting of the generated logic level signal to be the system clock internal inverter-amplifier. HS mode current consumption source. When operating in this mode, an external clock is the highest of the three modes. This mode is best source is connected to the OSC1 input. suited for resonators that require a high drive setting. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure5-2 shows the pin connections for EC Figure5-3 and Figure5-4 show typical circuits for mode. quartz crystal and ceramic resonators, respectively. EC mode has 3 power modes to select from through Configuration Word 1: • High-power, 4-32MHz (FOSC = 111) • Medium power, 0.5-4MHz (FOSC = 110) • Low-power, 0-0.5MHz (FOSC = 101)  2011 Microchip Technology Inc. DS41391D-page 53

PIC16(L)F1826/27 FIGURE 5-3: QUARTZ CRYSTAL FIGURE 5-4: CERAMIC RESONATOR OPERATION (LP, XT OR OPERATION HS MODE) (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN OSC1/CLKIN C1 To Internal C1 To Internal Logic Logic QCruyasrttazl RF(2) Sleep RP(3) RF(2) Sleep C2 RS(1) OSC2/CLKOUT C2 Ceramic RS(1) OSC2/CLKOUT Resonator Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 3: An additional parallel feedback resistor (RP) Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator according to type, package and operation. manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 5.2.1.3 Oscillator Start-up Timer (OST) 2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts expected for the application. 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer 3: For oscillator design assistance, reference (PWRT) has expired (if configured), or a wake-up from the following Microchip Applications Notes: Sleep. During this time, the program counter does not • AN826, “Crystal Oscillator Basics and increment and program execution is suspended. The Crystal Selection for rfPIC® and PIC® OST ensures that the oscillator circuit, using a quartz Devices” (DS00826) crystal resonator or ceramic resonator, has started and • AN849, “Basic PIC® Oscillator Design” is providing a stable system clock to the oscillator (DS00849) module. • AN943, “Practical PIC® Oscillator In order to minimize latency between external oscillator Analysis and Design” (DS00943) start-up and code execution, the Two-Speed Clock • AN949, “Making Your Oscillator Work” Start-up mode can be selected (see Section5.4 (DS00949) “Two-Speed Clock Start-up Mode”). 5.2.1.4 4X PLL The oscillator module contains a 4X PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4X PLL must fall within specifications. See the PLL Clock Timing Specifications in Section30.0 “Electrical Specifications”. The 4X PLL may be enabled for use by one of two methods: 1. Program the PLLEN bit in Configuration Word 2 to a ‘1’. 2. Write the SPLLEN bit in the OSCCON register to a ‘1’. If the PLLEN bit in Configuration Word 2 is programmed to a ‘1’, then the value of SPLLEN is ignored. DS41391D-page 54  2011 Microchip Technology Inc.

PIC16(L)F1826/27 5.2.1.5 TIMER1 Oscillator 5.2.1.6 External RC Mode The Timer1 Oscillator is a separate crystal oscillator The external Resistor-Capacitor (RC) modes support that is associated with the Timer1 peripheral. It is opti- the use of an external RC circuit. This allows the mized for timekeeping operations with a 32.768 kHz designer maximum flexibility in frequency choice while crystal connected between the T1OSO and T1OSI keeping costs to a minimum when clock accuracy is not device pins. required. The Timer1 Oscillator can be used as an alternate sys- The RC circuit connects to OSC1. OSC2/CLKOUT is tem clock source and can be selected during run-time available for general purpose I/O or CLKOUT. The using clock switching. Refer to Section5.3 “Clock function of the OSC2/CLKOUT pin is determined by the Switching” for more information. state of the CLKOUTEN bit in Configuration Word 1. Figure5-6 shows the external RC mode connections. FIGURE 5-5: QUARTZ CRYSTAL OPERATION (TIMER1 FIGURE 5-6: EXTERNAL RC MODES OSCILLATOR) VDD PIC® MCU PIC® MCU REXT T1OSI OSC1/CLKIN Internal Clock C1 To Internal CEXT Logic 32.768 kHz VSS Quartz Crystal FOSC/4 or I/O(1) OSC2/CLKOUT C2 T1OSO Recommended values: 10 k  REXT  100 k, <3V 3 k  REXT  100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: Quartz crystal characteristics vary Note 1: Output depends upon CLKOUTEN bit of the according to type, package and Configuration Word 1. manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values 2: Always verify oscillator performance over and the operating temperature. Other factors affecting the VDD and temperature range that is the oscillator frequency are: expected for the application. • threshold voltage variation 3: For oscillator design assistance, reference • component tolerances the following Microchip Applications Notes: • packaging variations in capacitance • AN826, “Crystal Oscillator Basics and The user also needs to take into account variation due Crystal Selection for rfPIC® and PIC® to tolerance of external RC components used. Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) • TB097, “Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288)  2011 Microchip Technology Inc. DS41391D-page 55

PIC16(L)F1826/27 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.1 HFINTOSC The device may be configured to use the internal oscil- The High-Frequency Internal Oscillator (HFINTOSC) is lator block as the system clock by performing one of the a factory calibrated 16MHz internal clock source. The following actions: frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register5-3). • Program the FOSC<2:0> bits in Configuration Word 1 to select the INTOSC clock source, which The output of the HFINTOSC connects to a postscaler will be used as the default system clock upon a and multiplexer (see Figure5-1). One of nine device Reset. frequencies derived from the HFINTOSC can be • Write the SCS<1:0> bits in the OSCCON register selected via software using the IRCF<3:0> bits of the to switch the system clock source to the internal OSCCON register. See Section5.2.2.7 “Internal oscillator during run-time. See Section5.3 Oscillator Clock Switch Timing” for more information. “Clock Switching”for more information. The HFINTOSC is enabled by: In INTOSC mode, OSC1/CLKIN is available for general • Configure the IRCF<3:0> bits of the OSCCON purpose I/O. OSC2/CLKOUT is available for general register for the desired HF frequency, and purpose I/O or CLKOUT. • FOSC<2:0> = 100, or The function of the OSC2/CLKOUT pin is determined • Set the System Clock Source (SCS) bits of the by the state of the CLKOUTEN bit in Configuration OSCCON register to ‘1x’. Word 1. The High Frequency Internal Oscillator Ready bit The internal oscillator block has two independent (HFIOFR) of the OSCSTAT register indicates when the oscillators and a dedicated Phase-Lock Loop, HFPLL HFINTOSC is running and can be utilized. that can produce one of three internal system clock The High Frequency Internal Oscillator Status Locked sources. bit (HFIOFL) of the OSCSTAT register indicates when 1. The HFINTOSC (High-Frequency Internal the HFINTOSC is running within 2% of its final value. Oscillator) is factory calibrated and operates at The High Frequency Internal Oscillator Status Stable 16MHz. The HFINTOSC source is generated bit (HFIOFS) of the OSCSTAT register indicates when from the 500 kHz MFINTOSC source and the the HFINTOSC is running within 0.5% of its final value. dedicated Phase-Lock Loop, HFPLL. The frequency of the HFINTOSC can be 5.2.2.2 MFINTOSC user-adjusted via software using the OSCTUNE register (Register5-3). The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500kHz internal 2. The MFINTOSC (Medium-Frequency Internal clock source. The frequency of the MFINTOSC can be Oscillator) is factory calibrated and operates at altered via software using the OSCTUNE register 500kHz. The frequency of the MFINTOSC can (Register5-3). be user-adjusted via software using the OSCTUNE register (Register5-3). The output of the MFINTOSC connects to a postscaler 3. The LFINTOSC (Low-Frequency Internal and multiplexer (see Figure5-1). One of nine Oscillator) is uncalibrated and operates at frequencies derived from the MFINTOSC can be 31kHz. selected via software using the IRCF<3:0> bits of the OSCCON register. See Section5.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The MFINTOSC is enabled by: • Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running and can be utilized. DS41391D-page 56  2011 Microchip Technology Inc.

PIC16(L)F1826/27 5.2.2.3 Internal Oscillator Frequency 5.2.2.5 Internal Oscillator Frequency Adjustment Selection The 500 kHz internal oscillator is factory calibrated. The system clock speed can be selected via software This internal oscillator can be adjusted in software by using the Internal Oscillator Frequency Select bits writing to the OSCTUNE register (Register5-3). Since IRCF<3:0> of the OSCCON register. the HFINTOSC and MFINTOSC clock sources are The output of the 16MHz HFINTOSC and 31kHz derived from the 500 kHz internal oscillator a change in LFINTOSC connects to a postscaler and multiplexer the OSCTUNE register value will apply to both. (see Figure5-1). The Internal Oscillator Frequency The default value of the OSCTUNE register is ‘0’. The Select bits IRCF<3:0> of the OSCCON register select value is a 6-bit two’s complement number. A value of the frequency output of the internal oscillators. One of 1Fh will provide an adjustment to the maximum the following frequencies can be selected via software: frequency. A value of 20h will provide an adjustment to • 32 MHz (requires 4X PLL) the minimum frequency. • 16 MHz When the OSCTUNE register is modified, the oscillator • 8 MHz frequency will begin shifting to the new frequency. Code • 4 MHz execution continues during this shift. There is no • 2 MHz indication that the shift has occurred. • 1 MHz OSCTUNE does not affect the LFINTOSC frequency. • 500 kHz (Default after Reset) Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer • 250 kHz (PWRT), Watchdog Timer (WDT), Fail-Safe Clock • 125 kHz Monitor (FSCM) and peripherals, are not affected by the • 62.5 kHz change in frequency. • 31.25 kHz 5.2.2.4 LFINTOSC • 31 kHz (LFINTOSC) The Low-Frequency Internal Oscillator (LFINTOSC) is Note: Following any Reset, the IRCF<3:0> bits an uncalibrated 31kHz internal clock source. of the OSCCON register are set to ‘0111’ and the frequency selection is set to The output of the LFINTOSC connects to a postscaler 500kHz. The user can modify the IRCF and multiplexer (see Figure5-1). Select 31kHz, via bits to select a different frequency. software, using the IRCF<3:0> bits of the OSCCON register. See Section5.2.2.7 “Internal Oscillator The IRCF<3:0> bits of the OSCCON register allow Clock Switch Timing” for more information. The duplicate selections for some frequencies. These dupli- LFINTOSC is also the frequency for the Power-up Timer cate choices can offer system design trade-offs. Lower (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock power consumption can be obtained when changing Monitor (FSCM). oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes The LFINTOSC is enabled by selecting 31kHz that use the same oscillator source. (IRCF<3:0> bits of the OSCCON register=000) as the system clock source (SCS bits of the OSCCON register= 1x), or when any of the following are enabled: • Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ Peripherals that use the LFINTOSC are: • Power-up Timer (PWRT) • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized.  2011 Microchip Technology Inc. DS41391D-page 57

PIC16(L)F1826/27 5.2.2.6 32 MHz Internal Oscillator 5.2.2.7 Internal Oscillator Clock Switch Frequency Selection Timing The Internal Oscillator Block can be used with the 4X When switching between the HFINTOSC, MFINTOSC PLL associated with the External Oscillator Block to and the LFINTOSC, the new oscillator may already be produce a 32 MHz internal system clock source. The shut down to save power (see Figure5-7). If this is the following settings are required to use the 32 MHz inter- case, there is a delay after the IRCF<3:0> bits of the nal clock source: OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will • The FOSC bits in Configuration Word 1 must be reflect the current active status of the HFINTOSC, set to use the INTOSC source as the device sys- MFINTOSC and LFINTOSC oscillators. The sequence tem clock (FOSC<2:0> = 100). of a frequency selection is as follows: • The SCS bits in the OSCCON register must be cleared to use the clock determined by 1. IRCF<3:0> bits of the OSCCON register are FOSC<2:0> in Configuration Word 1 modified. (SCS<1:0>=00). 2. If the new clock is shut down, a clock start-up • The IRCF bits in the OSCCON register must be delay is started. set to the 8 MHz HFINTOSC set to use 3. Clock switch circuitry waits for a falling edge of (IRCF<3:0>=1110). the current clock. • The SPLLEN bit in the OSCCON register must be 4. The current clock is held low and the clock set to enable the 4xPLL, or the PLLEN bit of the switch circuitry waits for a rising edge in the new Configuration Word 2 must be programmed to a clock. ‘1’. 5. The new clock is now active. Note: When using the PLLEN bit of the 6. The OSCSTAT register is updated as required. Configuration Word 2, the 4xPLL cannot 7. Clock switch is complete. be disabled by software and the 8 MHz See Figure5-7 for more details. HFINTOSC option will no longer be available. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay The 4xPLL is not available for use with the internal before the new frequency is selected. Clock switching oscillator when the SCS bits of the OSCCON register time delays are shown in Table5-1. are set to ‘1x’. The SCS bits must be set to ‘00’ to use Start-up delay specifications are located in the the 4xPLL with the internal oscillator. oscillator tables of Section30.0 “Electrical Specifications”. DS41391D-page 58  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ LFINTOSC (FSCM and WDT disabled) MFINTOSC HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled) MFINTOSC HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC   IRCF <3:0> 0 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> = 0  0 System Clock  2011 Microchip Technology Inc. DS41391D-page 59

PIC16(L)F1826/27 5.3 Clock Switching 5.3.3 TIMER1 OSCILLATOR The system clock source can be switched between The Timer1 Oscillator is a separate crystal oscillator external and internal clock sources via software using associated with the Timer1 peripheral. It is optimized the System Clock Select (SCS) bits of the OSCCON for timekeeping operations with a 32.768 kHz crystal register. The following clock sources can be selected connected between the T1OSO and T1OSI device using the SCS bits: pins. • Default system oscillator determined by FOSC The Timer1 oscillator is enabled using the T1OSCEN bits in Configuration Word 1 control bit in the T1CON register. See Section21.0 “Timer1 Module with Gate Control” for more • Timer1 32 kHz crystal oscillator information about the Timer1 peripheral. • Internal Oscillator Block (INTOSC) 5.3.4 TIMER1 OSCILLATOR READY 5.3.1 SYSTEM CLOCK SELECT (SCS) (T1OSCR) BIT BITS The user must ensure that the Timer1 Oscillator is The System Clock Select (SCS) bits of the OSCCON ready to be used before it is selected as a system clock register selects the system clock source that is used for source. The Timer1 Oscillator Ready (T1OSCR) bit of the CPU and peripherals. the OSCSTAT register indicates whether the Timer1 • When the SCS bits of the OSCCON register = 00, oscillator is ready to be used. After the T1OSCR bit is the system clock source is determined by value of set, the SCS bits can be configured to select the Timer1 the FOSC<2:0> bits in the Configuration Word 1. oscillator. • When the SCS bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscil- lator delays are shown in Table5-1. 5.3.2 OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the Timer1 Oscillator. DS41391D-page 60  2011 Microchip Technology Inc.

PIC16(L)F1826/27 5.4 Two-Speed Clock Start-up Mode 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode provides additional power savings by minimizing the latency between external Two-Speed Start-up mode is configured by the oscillator start-up and code execution. In applications following settings: that make heavy use of the Sleep mode, Two-Speed • IESO (of the Configuration Word 1) = 1; Inter- Start-up will remove the external oscillator start-up nal/External Switchover bit (Two-Speed Start-up time from the time spent awake and can reduce the mode enabled). overall power consumption of the device. This mode • SCS (of the OSCCON register) = 00. allows the application to wake-up from Sleep, perform • FOSC<2:0> bits in the Configuration Word 1 a few instructions using the INTOSC internal oscillator configured for LP, XT or HS mode. block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up mode is entered after: Two-Speed Start-up provides benefits when the oscil- • Power-on Reset (POR) and, if enabled, after lator module is configured for LP, XT, or HS modes. Power-up Timer (PWRT) has expired, or The Oscillator Start-up Timer (OST) is enabled for • Wake-up from Sleep. these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT reg- ister is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 5-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) 31kHz Sleep/POR MFINTOSC(1) 31.25kHz-500 kHz Oscillator Warm-up Delay (TWARM) HFINTOSC(1) 31.25kHz-16MHz Sleep/POR EC, RC(1) DC – 32MHz 2 cycles LFINTOSC EC, RC(1) DC – 32MHz 1 cycle of each Timer1 Oscillator Sleep/POR 32kHz-20MHz 1024 Clock Cycles (OST) LP, XT, HS(1) MFINTOSC(1) 31.25kHz-500kHz Any clock source 2s (approx.) HFINTOSC(1) 31.25kHz-16MHz Any clock source LFINTOSC(1) 31kHz 1 cycle of each Any clock source Timer1 Oscillator 32kHz 1024 Clock Cycles (OST) PLL inactive PLL active 16-32MHz 2ms (approx.) Note 1: PLL inactive.  2011 Microchip Technology Inc. DS41391D-page 61

PIC16(L)F1826/27 5.4.2 TWO-SPEED START-UP 5.4.3 CHECKING TWO-SPEED CLOCK SEQUENCE STATUS 1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCSTAT 2. Instructions begin execution by the internal register will confirm if the microcontroller is running oscillator at the frequency set in the IRCF<3:0> from the external clock source, as defined by the bits of the OSCCON register. FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. 5. OSTS is set. 6. System clock held low until the next falling edge of new clock (LP, XT or HS mode). 7. System clock is switched to external clock source. FIGURE 5-8: TWO-SPEED START-UP INTOSC TTOST OSC1 0 1 1022 1023 OSC2 Program Counter P C - N PC PC + 1 System Clock DS41391D-page 62  2011 Microchip Technology Inc.

PIC16(L)F1826/27 5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset, to continue operating should the external oscillator fail. executing a SLEEP instruction or changing the SCS bits The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bits are the Oscillator Start-up Timer (OST) has expired. The changed, the OST is restarted. While the OST is FSCM is enabled by setting the FCMEN bit in the running, the device continues to operate from the Configuration Word 1. The FSCM is applicable to all INTOSC selected in OSCCON. When the OST times external Oscillator modes (LP, XT, HS, EC, Timer1 out, the Fail-Safe condition is cleared and the device Oscillator and RC). will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. FIGURE 5-9: FSCM BLOCK DIAGRAM 5.5.4 RESET OR WAKE-UP FROM SLEEP Clock Monitor Latch The FSCM is designed to detect an oscillator failure External S Q after the Oscillator Start-up Timer (OST) has expired. Clock The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or LFINTOSC RC Clock modes so that the FSCM will be active as Oscillator ÷ 64 R Q soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also 31 kHz 488 Hz enabled. Therefore, the device will always be executing (~32 s) (~2 ms) code while the OST is operating. Sample Clock Clock Note: Due to the wide range of oscillator start-up Failure times, the Fail-Safe circuit is not active Detected during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the 5.5.1 FAIL-SAFE DETECTION Status bits in the OSCSTAT register to The FSCM module detects a failed oscillator by verify the oscillator start-up and that the comparing the external oscillator to the FSCM sample system clock switchover has successfully clock. The sample clock is generated by dividing the completed. LFINTOSC by 64. See Figure5-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2011 Microchip Technology Inc. DS41391D-page 63

PIC16(L)F1826/27 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS41391D-page 64  2011 Microchip Technology Inc.

PIC16(L)F1826/27 5.6 Oscillator Control Registers REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0 SPLLEN IRCF<3:0> — SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Word 1 = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Word 1 = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 000x =31kHz LF 0010 =31.25kHz MF 0011 =31.25kHz HF(1) 0100 =62.5kHz MF 0101 =125kHz MF 0110 =250kHz MF 0111 =500kHz MF (default upon Reset) 1000 =125kHz HF(1) 1001 =250kHz HF(1) 1010 =500kHz HF(1) 1011 =1MHz HF 1100 =2MHz HF 1101 =4MHz HF 1110 =8MHz or 32 MHz HF(see Section5.2.2.1 “HFINTOSC”) 1111 =16MHz HF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Note 1: Duplicate frequency derived from HFINTOSC.  2011 Microchip Technology Inc. DS41391D-page 65

PIC16(L)F1826/27 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator is ready 0 = Timer1 oscillator is not ready If T1OSCEN = 0: 1 = Timer1 clock source is always ready bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Time-out Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Word 1 0 = Running from an internal oscillator (FOSC<2:0> = 100) bit 4 HFIOFR: High Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS41391D-page 66  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = • • • 000001 = 000000 = Oscillator module is running at the factory-calibrated frequency. 111111 = • • • 100000 = Minimum frequency TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0 — SCS1 SCS0 65 OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 66 OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 67 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE(1) 94 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF(1) 97 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 187 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources. Note 1: PIC16(L)F1827 only. TABLE 5-3: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD CONFIG1 50 7:0 CP MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources.  2011 Microchip Technology Inc. DS41391D-page 67

PIC16(L)F1826/27 NOTES: DS41391D-page 68  2011 Microchip Technology Inc.

PIC16(L)F1826/27 6.0 REFERENCE CLOCK MODULE 6.3 Conflicts with the CLKR Pin The reference clock module provides the ability to send There are two cases when the reference clock output a divided clock to the clock output pin of the device signal cannot be output to the CLKR pin, if: (CLKR) and provide a secondary internal clock source • LP, XT or HS Oscillator mode is selected. to the modulator module. This module is available in all • CLKOUT function is enabled. oscillator configurations and allows the user to select a greater range of clock submultiples to drive external Even if either of these cases are true, the module can devices in the application. The reference clock module still be enabled and the reference clock signal may be includes the following features: used in conjunction with the modulator module. • System clock is the source 6.3.1 OSCILLATOR MODES • Available in all oscillator configurations If LP, XT or HS oscillator modes are selected, the • Programmable clock divider OSC2/CLKR pin must be used as an oscillator input pin • Output enable to a port pin and the CLKR output cannot be enabled. See • Selectable duty cycle Section5.2 “Clock Source Types” for more informa- • Slew rate control tion on different oscillator modes. The reference clock module is controlled by the 6.3.2 CLKOUT FUNCTION CLKRCON register (Register6-1) and is enabled when setting the CLKREN bit. To output the divided clock sig- The CLKOUT function has a higher priority than the nal to the CLKR port pin, the CLKROE bit must be set. reference clock module. Therefore, if the CLKOUT function is enabled by the CLKOUTEN bit in Configura- The CLKRDIV<2:0> bits enable the selection of 8 dif- ferent clock divider options. The CLKRDC<1:0> bits tion Word 1, FOSC/4 will always be output on the port pin. Reference Section4.0 “Device Configuration” can be used to modify the duty cycle of the output clock(1). The CLKRSLR bit controls slew rate limiting. for more information. Note1: If the base clock rate is selected without 6.4 Operation During Sleep a divider, the output clock will always have a duty cycle equal to that of the As the reference clock module relies on the system source clock, unless a 0% duty cycle is clock as its source, and the system clock is disabled in selected. If the clock divider is set to base Sleep, the module does not function in Sleep, even if clock/2, then 25% and 75% duty cycle an external clock source or the Timer1 clock source is accuracy will be dependent upon the configured as the system clock. The module outputs source clock. will remain in their current state until the device exits Sleep. For information on using the reference clock output with the modulator module, see Section23.0 “Data Signal Modulator”. 6.1 Slew Rate The slew rate limitation on the output port pin can be disabled. The slew rate limitation can be removed by clearing the CLKRSLR bit in the CLKRCON register. 6.2 Effects of a Reset Upon any device Reset, the reference clock module is disabled. The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values.  2011 Microchip Technology Inc. DS41391D-page 69

PIC16(L)F1826/27 6.5 Reference Clock Control Register REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 = Reference Clock module is enabled 0 = Reference Clock module is disabled bit 6 CLKROE: Reference Clock Output Enable bit(3) 1 = Reference Clock output is enabled on CLKR pin 0 = Reference Clock output disabled on CLKR pin bit 5 CLKRSLR: Reference Clock Slew Rate Control limiting enable bit 1 = Slew Rate limiting is enabled 0 = Slew Rate limiting is disabled bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits 11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0% bit 2-0 CLKRDIV<2:0> Reference Clock Divider bits 111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2(1) 000 = Base clock value(2) Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle. 2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0% is selected. 3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration Word 1 = 0 will result in FOSC/4. See Section6.3 “Conflicts with the CLKR Pin” for details. DS41391D-page 70  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CLKRCON CLKREN CLKROE CLKRSLR CLKRDC1 CLKRDC0 CLKRDIV2 CLKRDIV1 CLKRDIV0 70 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. TABLE 6-2: SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD CONFIG1 44 7:0 CP MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.  2011 Microchip Technology Inc. DS41391D-page 71

PIC16(L)F1826/27 NOTES: DS41391D-page 72  2011 Microchip Technology Inc.

PIC16(L)F1826/27 7.0 RESETS There are multiple ways to reset this device: • Power-on Reset (POR) • Brown-out Reset (BOR) • MCLR Reset • WDT Reset • RESET instruction • Stack Overflow • Stack Underflow • Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure7-1. FIGURE 7-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Stack Overflow/Underflow Reset Pointer External Reset MCLRE MCLR Sleep WDT Time-out Device Power-on Reset Reset VDD Brown-out Reset BOR Enable PWRT Zero 64 ms LFINTOSC PWRTEN  2011 Microchip Technology Inc. DS41391D-page 73

PIC16(L)F1826/27 7.1 Power-on Reset (POR) 7.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when Vdd reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for performance may require greater than minimum VDD. execution protection can be implemented. The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in Configu- conditions have been met. ration Word 1. The four operating modes are: 7.1.1 POWER-UP TIMER (PWRT) • BOR is always on • BOR is off when in Sleep The Power-up Timer provides a nominal 64ms time- out on POR or Brown-out Reset. • BOR is controlled by software • BOR is always off The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to Refer to Table7-1 for more information. rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by enabled by clearing the PWRTE bit in Configuration configuring the BORV bit in Configuration Word 2. Word 1. A VDD noise rejection filter prevents the BOR from trig- The Power-up Timer starts after the release of the POR gering on small events. If VDD falls below VBOR for a and BOR. duration greater than parameter TBORDC, the device For additional information, refer to Application Note will reset. See Figure7-2 for more information. AN607, “Power-up Trouble Shooting” (DS00607). TABLE 7-1: BOR OPERATING MODES Device Operation Device Operation BOREN<1:0> SBOREN Device Mode BOR Mode upon wake- up from upon release of POR Sleep 11 X X Active Waits for BOR ready(1) Awake Active 10 X Waits for BOR ready Sleep Disabled 1 Active Begins immediately 01 X 0 Disabled Begins immediately 00 X X Disabled Begins immediately Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in start-up. 7.2.1 BOR IS ALWAYS ON 7.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Word 1 are set When the BOREN bits of Configuration Word 1 are set to ‘11’, the BOR is always on. The device start-up will to ‘01’, the BOR is controlled by the SBOREN bit of the be delayed until the BOR is ready and VDD is higher BORCON register. The device start-up is not delayed than the BOR threshold. by the BOR ready condition or the VDD level. BOR protection is active during Sleep. The BOR does BOR protection begins as soon as the BOR circuit is not delay wake-up from Sleep. ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. 7.2.2 BOR IS OFF IN SLEEP BOR protection is unchanged by Sleep. When the BOREN bits of Configuration Word 1 are set to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. DS41391D-page 74  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 7-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal < TPWRT Reset TPWRT(1) VDD VBOR Internal Reset TPWRT(1) Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’. REGISTER 7-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN — — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Word 1  01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Word 1 = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive  2011 Microchip Technology Inc. DS41391D-page 75

PIC16(L)F1826/27 7.3 MCLR 7.7 Programming Mode Exit The MCLR is an optional external input that can reset Upon exit of Programming mode, the device will the device. The MCLR function is controlled by the behave as if a POR had just occurred. MCLRE bit of Configuration Word 1 and the LVP bit of Configuration Word 2 (Table7-2). 7.8 Power-Up Timer The Power-up Timer optionally delays device execution TABLE 7-2: MCLR CONFIGURATION after a BOR or POR event. This timer is typically used to MCLRE LVP MCLR allow VDD to stabilize before allowing the device to start running. 0 0 Disabled The Power-up Timer is controlled by the PWRTE bit of 1 0 Enabled Configuration Word 1. x 1 Enabled 7.9 Start-up Sequence 7.3.1 MCLR ENABLED Upon the release of a POR or BOR, the following must When MCLR is enabled and the pin is held low, the occur before the device will begin executing: device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. 1. Power-up Timer runs to completion (if enabled). 2. Oscillator start-up timer runs to completion (if The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. required for oscillator source). 3. MCLR must be released (if enabled). Note: A Reset does not drive the MCLR pin low. The total time-out will vary based on oscillator configu- 7.3.2 MCLR DISABLED ration and Power-up Timer configuration. See Section5.0 “Oscillator Module (With Fail-Safe When MCLR is disabled, the pin functions as a general Clock Monitor)” for more information. purpose input and the internal weak pull-up is under The Power-up Timer and oscillator start-up timer run software control. See Section12.2 “PORTA Regis- independently of MCLR Reset. If MCLR is kept low ters” for more information. long enough, the Power-up Timer and oscillator start- up timer will expire. Upon bringing MCLR high, the 7.4 Watchdog Timer (WDT) Reset device will begin execution immediately (see Figure7- The Watchdog Timer generates a Reset if the firmware 3). This is useful for testing purposes or to synchronize does not issue a CLRWDT instruction within the time-out more than one device operating in parallel. period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section10.0 “Watchdog Timer” for more information. 7.5 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Table7-4 for default conditions after a RESET instruction has occurred. 7.6 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Word 2. See Section3.4.2 “Overflow/Underflow Reset”for more information. DS41391D-page 76  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 7-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC  2011 Microchip Technology Inc. DS41391D-page 77

PIC16(L)F1826/27 7.10 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table7-3 and Table7-4 show the Reset condi- tions of these registers. TABLE 7-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RMCLR RI POR BOR TO PD Condition 0 0 1 1 0 x 1 1 Power-on Reset 0 0 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 0 x x 0 Illegal, PD is set on POR 0 0 1 1 u 0 1 1 Brown-out Reset u u u u u u 0 u WDT Reset u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u 1 0 Interrupt Wake-up from Sleep u u 0 u u u u u MCLR Reset during normal operation u u 0 u u u 1 0 MCLR Reset during Sleep u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 7-4: RESET CONDITION FOR SPECIAL REGISTERS(2) Program STATUS PCON Condition Counter Register Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-- uuuu RESET Instruction Executed 0000h ---u uuuu uu-- u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as ‘0’. DS41391D-page 78  2011 Microchip Technology Inc.

PIC16(L)F1826/27 7.11 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Reset Instruction Reset (RI) • MCLR Reset (RMCLR) • Stack Underflow Reset (STKUNF) • Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register7-2. REGISTER 7-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u STKOVF STKUNF — — RMCLR RI POR BOR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or set to ‘0’ by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or set to ‘0’ by firmware bit 5-4 Unimplemented: Read as ‘0’ bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)  2011 Microchip Technology Inc. DS41391D-page 79

PIC16(L)F1826/27 TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BORCON SBOREN — — — — — — BORRDY 75 PCON STKOVF STKUNF — — RMCLR RI POR BOR 79 STATUS — — — TO PD Z DC C 21 WDTCON — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN 99 Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS41391D-page 80  2011 Microchip Technology Inc.

PIC16(L)F1826/27 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • Operation • Interrupt Latency • Interrupts During Sleep • INT Pin • Automatic Context Saving Many peripherals produce Interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure8-1. FIGURE 8-1: INTERRUPT LOGIC IOCBNx D Q Q4Q1 CK Edge Detect R RBx Data bus = S To data bus IOCBPx D Q 0 or 1 D Q IOCBFx CK Write IOCBFx CK IOCIE R Q2 From all other IOCBFx individual IOC interrupt pin detectors to CPU core Q1 Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q3 Q4 Q4 Q4 Q4 Q4Q1 Q4Q1 Q4Q1 Q4Q1  2011 Microchip Technology Inc. DS41391D-page 81

PIC16(L)F1826/27 8.1 Operation 8.2 Interrupt Latency Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the are enabled by setting the following bits: interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous • GIE bit of the INTCON register interrupts is 3 or 4 instruction cycles. For asynchronous • Interrupt Enable bit(s) for the specific interrupt interrupts, the latency is 3 to 5 instruction cycles, events) depending on when the interrupt occurs. See Figure8-2 • PEIE bit of the INTCON register (if the Interrupt and Figure8.3 for more details. Enable bit of the interrupt event is contained in the PIEx registers) The INTCON, PIRx registers record individual inter- rupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See “Section8.5 “Automatic Context Saving”.”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. DS41391D-page 82  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 8-2: INTERRUPT LATENCY OSC1 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC PC-1 PC PC+1 0004h 0005h Execute 1 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC+1/FSR New PC/ PC PC-1 PC 0004h 0005h ADDR PC+1 Execute 2 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h)  2011 Microchip Technology Inc. DS41391D-page 83

PIC16(L)F1826/27 FIGURE 8-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 (3) CLKOUT (4) INT pin (1) (1) (2) INTF (5) Interrupt Latency GIE INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section30.0 “Electrical Specifications””. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS41391D-page 84  2011 Microchip Technology Inc.

PIC16(L)F1826/27 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section9.0 “Power- Down Mode (Sleep)” for more details. 8.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 8.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the Shadow registers: • W register • STATUS register (except for TO and PD) • BSR register • FSR registers • PCLATH register Upon exiting the Interrupt Service Routine, these regis- ters are automatically restored. Any modifications to these registers during the ISR will be lost. If modifica- tions to any of these registers are desired, the corre- sponding Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved.  2011 Microchip Technology Inc. DS41391D-page 85

PIC16(L)F1826/27 8.6 Interrupt Control Registers Note: Interrupt flag bits are set when an interrupt 8.6.1 INTCON REGISTER condition occurs, regardless of the state of its corresponding enable bit or the Global The INTCON register is a readable and writable Enable bit, GIE, of the INTCON register. register, that contains the various enable and flag bits User software should ensure the appropri- for TMR0 register overflow, interrupt-on-change and ate interrupt flag bits are clear prior to external INT pin interrupts. enabling an interrupt. REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register have been cleared by software. DS41391D-page 86  2011 Microchip Technology Inc.

PIC16(L)F1826/27 8.6.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register8-2. set to enable any peripheral interrupt. REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 Gate Acquisition interrupt 0 = Disables the Timer1 Gate Acquisition interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port 1 (MSSP1) Interrupt Enable bit 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt  2011 Microchip Technology Inc. DS41391D-page 87

PIC16(L)F1826/27 8.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register8-3. set to enable any peripheral interrupt. REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit 1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt bit 3 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit 1 = Enables the MSSP1 Bus Collision Interrupt 0 = Disables the MSSP1 Bus Collision Interrupt bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Note 1: PIC16(L)F1827 only. DS41391D-page 88  2011 Microchip Technology Inc.

PIC16(L)F1826/27 8.6.4 PIE3 REGISTER The PIE3 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register8-4. set to enable any peripheral interrupt. REGISTER 8-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3(1) U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 — — CCP4IE CCP3IE TMR6IE — TMR4IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 CCP4IE: CCP4 Interrupt Enable bit 1 = Enables the CCP4 interrupt 0 = Disables the CCP4 interrupt bit 4 CCP3IE: CCP3 Interrupt Enable bit 1 = Enables the CCP3 interrupt 0 = Disables the CCP3 interrupt bit 3 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the TMR6 to PR6 Match interrupt 0 = Disables the TMR6 to PR6 Match interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 Match interrupt 0 = Disables the TMR4 to PR4 Match interrupt bit 0 Unimplemented: Read as ‘0’ Note 1: This register is only available on PIC16(L)F1827.  2011 Microchip Technology Inc. DS41391D-page 89

PIC16(L)F1826/27 8.6.5 PIE4 REGISTER(1) The PIE4 register contains the interrupt enable bits, as Note1: The PIE4 register is available only on the shown in Register8-5. PIC16(L)F1827 device. 2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. REGISTER 8-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — BCL2IE SSP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 BCL2IE: MSSP2 Bus Collision Interrupt Enable bit 1 = Enables the MSSP2 Bus Collision Interrupt 0 = Disables the MSSP2 Bus Collision Interrupt bit 0 SSP2IE: Master Synchronous Serial Port 2 (MSSP2) Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt Note 1: This register is only available on PIC16(L)F1827. DS41391D-page 90  2011 Microchip Technology Inc.

PIC16(L)F1826/27 8.6.6 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register8-6. condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 8-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port 1 (MSSP1) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending  2011 Microchip Technology Inc. DS41391D-page 91

PIC16(L)F1826/27 8.6.7 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register8-7. condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 8-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 C2IF: Comparator C2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Interrupt is not pending Note 1: PIC16(L)F1827 only. DS41391D-page 92  2011 Microchip Technology Inc.

PIC16(L)F1826/27 8.6.8 PIR3 REGISTER The PIR3 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register8-8. condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 8-8: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3(1) U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 — — CCP4IF CCP3IF TMR6IF — TMR4IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 CCP4IF: CCP4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 CCP3IF: CCP3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 Unimplemented: Read as ‘0’ bit 1 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 Unimplemented: Read as ‘0’ Note 1: This register is only available on PIC16(L)F1827.  2011 Microchip Technology Inc. DS41391D-page 93

PIC16(L)F1826/27 8.6.9 PIR4 REGISTER(1) The PIR4 register contains the interrupt flag bits, as Note1: The PIR4 register is available only on the shown in Register8-9. PIC16(L)F1827 device. 2: Interrupt flag bits are set when an inter- rupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 8-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 — — — — — — BCL2IF SSP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware bit 7-2 Unimplemented: Read as ‘0’ bit 1 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = A Bus Collision was detected (must be cleared in software) 0 = No Bus collision was detected bit 0 SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit 1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software) 0 = Waiting to Transmit/Receive/Bus Condition in progress Note 1: This register is only available on PIC16(L)F1827. TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 177 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE(1) 88 PIE3(1) — — CCP4IE CCP3IE TMR6IE — TMR4IE — 89 PIE4(1) — — — — — — BCL2IE SSP2IE 90 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 91 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF(1) 92 PIR3(1) — — CCP4IF CCP3IF TMR6IF — TMR4IF — 93 PIR4(1) — — — — — — BCL2IF SSP2IF 94 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts. Note 1: PIC16(L)F1827 only. DS41391D-page 94  2011 Microchip Technology Inc.

PIC16(L)F1826/27 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-Down mode is entered by executing a The device can wake-up from Sleep through one of the SLEEP instruction. following events: Upon entering Sleep mode, the following conditions 1. External Reset input on MCLR pin, if enabled exist: 2. BOR Reset, if enabled 1. WDT will be cleared but keeps running, if 3. POR Reset enabled for operation during Sleep. 4. Watchdog Timer, if enabled 2. PD bit of the STATUS register is cleared. 5. Any external interrupt 3. TO bit of the STATUS register is set. 6. Interrupts by peripherals capable of running dur- 4. CPU clock is disabled. ing Sleep (see individual peripheral for more 5. 31 kHz LFINTOSC is unaffected and peripherals information) that operate from it may continue operation in The first three events will cause a device Reset. The Sleep. last three events are considered a continuation of pro- 6. Timer1 oscillator is unaffected and peripherals gram execution. To determine whether a device Reset that operate from it may continue operation in or wake-up event occurred, refer to Section7.10 Sleep. “Determining the Cause of a Reset”. 7. ADC is unaffected, if the dedicated FRC clock is When the SLEEP instruction is being executed, the next selected. instruction (PC + 1) is prefetched. For the device to 8. Capacitive Sensing oscillator is unaffected. wake-up through an interrupt event, the corresponding 9. I/O ports maintain the status they had before interrupt enable bit must be enabled. Wake-up will SLEEP was executed (driving high, low or high- occur regardless of the state of the GIE bit. If the GIE impedance). bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is 10. Resets other than WDT are not affected by enabled, the device executes the instruction after the Sleep mode. SLEEP instruction, the device will then call the Interrupt Refer to individual chapters for more details on Service Routine. In cases where the execution of the peripheral operation during Sleep. instruction following SLEEP is not desirable, the user To minimize current consumption, the following condi- should have a NOP after the SLEEP instruction. tions should be considered: The WDT is cleared when the device wakes up from • I/O pins should not be floating Sleep, regardless of the source of wake-up. • External circuitry sinking current from I/O pins • Internal circuitry sourcing current from I/O pins • Current draw from pins with internal weak pull-ups • Modules using 31 kHz LFINTOSC • Modules using Timer1 oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching cur- rents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section17.0 “Digital-to-Analog Con- verter (DAC) Module” and Section14.0 “Fixed Volt- age Reference (FVR)” for more information on these modules.  2011 Microchip Technology Inc. DS41391D-page 95

PIC16(L)F1826/27 9.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the execu- tion of a SLEEP instruction When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit - SLEEP instruction will be completely exe- and interrupt flag bit set, one of the following will occur: cuted - Device will immediately wake-up from Sleep • If the interrupt occurs before the execution of a SLEEP instruction - WDT and WDT prescaler will be cleared - SLEEP instruction will execute as a NOP. - TO bit of the STATUS register will be set - WDT and WDT prescaler will not be cleared - PD bit of the STATUS register will be cleared. - TO bit of the STATUS register will not be set Even if the flag bits were checked before executing a - PD bit of the STATUS register will not be SLEEP instruction, it may be possible for flag bits to cleared. become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) CLKOUT(2) TOST(3) Interrupt flag Interrupt Latency(4) GIE bit Processor in (INTCON reg.) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC - 1) Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. 3: TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes. 4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 91 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 134 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 134 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 134 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 92 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE(1) 93 PIE4(1) — — — — — — BCL2IE SSP2IE 95 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 96 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF(1) 97 PIR4(1) — — — — — — BCL2IF SSP2IF 99 STATUS — — — TO PD Z DC C 23 WDTCON — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN 105 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode. Note 1: PIC16(L)F1827 only. DS41391D-page 96  2011 Microchip Technology Inc.

PIC16(L)F1826/27 10.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0>=01 SWDTEN 23-bit Programmable WDTE<1:0>=11 LFINTOSC WDT Time-out Prescaler WDT WDTE<1:0>=10 Sleep WDTPS<4:0>  2011 Microchip Technology Inc. DS41391D-page 97

PIC16(L)F1826/27 10.1 Independent Clock Source 10.3 Time-Out Period The WDT derives its time base from the 31kHz The WDTPS bits of the WDTCON register set the LFINTOSC internal oscillator. Time intervals in this time-out period from 1 ms to 256 seconds (nominal). chapter are based on a nominal interval of 1ms. See After a Reset, the default time-out period is 2 seconds. Section30.0 “Electrical Specifications” for the LFINTOSC tolerances. 10.4 Clearing the WDT 10.2 WDT Operating Modes The WDT is cleared when any of the following condi- tions occur: The Watchdog Timer module has four operating modes • Any Reset controlled by the WDTE<1:0> bits in Configuration • CLRWDT instruction is executed Word 1. See Table10-1. • Device enters Sleep 10.2.1 WDT IS ALWAYS ON • Device wakes up from Sleep When the WDTE bits of Configuration Word 1 are set to • Oscillator fail event ‘11’, the WDT is always on. • WDT is disabled WDT protection is active during Sleep. • Oscillator Start-up TImer (OST) is running See Table10-2 for more information. 10.2.2 WDT IS OFF IN SLEEP When the WDTE bits of Configuration Word 1 are set to 10.5 Operation During Sleep ‘10’, the WDT is on, except in Sleep. When the device enters Sleep, the WDT is cleared. If WDT protection is not active during Sleep. the WDT is enabled during Sleep, the WDT resumes counting. 10.2.3 WDT CONTROLLED BY SOFTWARE When the device exits Sleep, the WDT is cleared When the WDTE bits of Configuration Word 1 are set to again. The WDT remains clear until the OST, if ‘01’, the WDT is controlled by the SWDTEN bit of the enabled, completes. See Section5.0 “Oscillator WDTCON register. Module (With Fail-Safe Clock Monitor)” for more WDT protection is unchanged by Sleep. See information on the OST. Table10-1 for more details. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device TABLE 10-1: WDT OPERATING MODES wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the Device WDT WDTE<1:0> SWDTEN event. See Register3-1 for more information. Mode Mode 11 X X Active Awake Active 10 X Sleep Disabled 1 Active 01 X 0 Disabled 00 X X Disabled TABLE 10-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0>=00 WDTE<1:0>=01 and SWDTEN = 0 WDTE<1:0>=10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) Unaffected DS41391D-page 98  2011 Microchip Technology Inc.

PIC16(L)F1826/27 10.6 Watchdog Control Register REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 — — WDTPS<4:0> SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 00000 = 1:32 (Interval 1ms nominal) 00001 = 1:64 (Interval 2ms nominal) 00010 = 1:128 (Interval 4ms nominal) 00011 = 1:256 (Interval 8ms nominal) 00100 = 1:512 (Interval 16ms nominal) 00101 = 1:1024 (Interval 32ms nominal) 00110 = 1:2048 (Interval 64ms nominal) 00111 = 1:4096 (Interval 128ms nominal) 01000 = 1:8192 (Interval 256ms nominal) 01001 = 1:16384 (Interval 512ms nominal) 01010 = 1:32768 (Interval 1s nominal) 01011 = 1:65536 (Interval 2s nominal) (Reset value) 01100 = 1:131072 (217) (Interval 4s nominal) 01101 = 1:262144 (218) (Interval 8s nominal) 01110 = 1:524288 (219) (Interval 16s nominal) 01111 = 1:1048576 (220) (Interval 32s nominal) 10000 = 1:2097152 (221) (Interval 64s nominal) 10001 = 1:4194304 (222) (Interval 128s nominal) 10010 = 1:8388608 (223) (Interval 256s nominal) 10011 = Reserved. Results in minimum interval (1:32) • • • 11111 = Reserved. Results in minimum interval (1:32) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.  2011 Microchip Technology Inc. DS41391D-page 99

PIC16(L)F1826/27 TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON — IRCF<3:0> — SCS<1:0> 69 STATUS — — — TO PD Z DC C 21 WDTCON — — WDTPS<4:0> SWDTEN 99 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer. TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 44 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer. DS41391D-page 100  2011 Microchip Technology Inc.

PIC16(L)F1826/27 11.0 DATA EEPROM AND FLASH 11.1 EEADRL and EEADRH Registers PROGRAM MEMORY The EEADRH:EEADRL register pair can address up to CONTROL a maximum of 256bytes of data EEPROM or up to a maximum of 32K words of program memory. The Data EEPROM and Flash program memory are readable and writable during normal operation (full VDD When selecting a program address value, the MSB of range). These memories are not directly mapped in the the address is written to the EEADRH register and the register file space. Instead, they are indirectly LSB is written to the EEADRL register. When selecting addressed through the Special Function Registers a EEPROM address value, only the LSB of the address (SFRs). There are six SFRs used to access these is written to the EEADRL register. memories: 11.1.1 EECON1 AND EECON2 REGISTERS • EECON1 EECON1 is the control register for EE memory • EECON2 accesses. • EEDATL Control bit EEPGD determines if the access will be a • EEDATH program or data memory access. When clear, any • EEADRL subsequent operations will operate on the EEPROM • EEADRH memory. When set, any subsequent operations will When interfacing the data memory block, EEDATL operate on the program memory. On Reset, EEPROM is holds the 8-bit data for read/write, and EEADRL holds selected by default. the address of the EEDATL location being accessed. Control bits RD and WR initiate read and write, These devices have 256 bytes of data EEPROM with respectively. These bits cannot be cleared, only set, in an address range from 0h to 0FFh. software. They are cleared in hardware at completion When accessing the program memory block, the EED- of the read or write operation. The inability to clear the ATH:EEDATL register pair forms a 2-byte word that WR bit in software prevents the accidental, premature holds the 14-bit data for read/write, and the EEADRL termination of a write operation. and EEADRH registers form a 2-byte word that holds The WREN bit, when set, will allow a write operation to the 15-bit address of the program memory location occur. On power-up, the WREN bit is clear. The being read. WRERR bit is set when a write operation is interrupted The EEPROM data memory allows byte read and write. by a Reset during normal operation. In these situations, An EEPROM byte write automatically erases the loca- following Reset, the user can check the WRERR bit tion and writes the new data (erase before write). and execute the appropriate error handling routine. The write time is controlled by an on-chip timer. The Interrupt flag bit EEIF of the PIR2 register is set when write/erase voltages are generated by an on-chip write is complete. It must be cleared in the software. charge pump rated to operate over the voltage range of Reading EECON2 will read all ‘0’s. The EECON2 reg- the device for byte or word operations. ister is used exclusively in the data EEPROM write Depending on the setting of the Flash Program sequence. To enable writes, a specific pattern must be Memory Self Write Enable bits WRT<1:0> of the written to EECON2. Configuration Word 2, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are always allowed. When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory.  2011 Microchip Technology Inc. DS41391D-page 101

PIC16(L)F1826/27 11.2 Using the Data EEPROM 11.2.2 WRITING TO THE DATA EEPROM MEMORY The data EEPROM is a high-endurance, byte address- able array that has been optimized for the storage of To write an EEPROM data location, the user must first frequently changing information (e.g., program vari- write the address to the EEADRL register and the data ables or other data that are updated often). When vari- to the EEDATL register. Then the user must follow a ables in one section change frequently, while variables specific sequence to initiate the write for each byte. in another section do not change, it is possible to The write will not initiate if the above sequence is not exceed the total number of write cycles to the followed exactly (write 55h to EECON2, write AAh to EEPROM without exceeding the total number of write EECON2, then set the WR bit) for each byte. Interrupts cycles to a single byte. Refer to Section30.0 “Electri- should be disabled during this codesegment. cal Specifications”. If this is the case, then a refresh Additionally, the WREN bit in EECON1 must be set to of the array must be performed. For this reason, vari- enable write. This mechanism prevents accidental ables that change infrequently (such as constants, IDs, writes to data EEPROM due to errant (unexpected) calibration, etc.) should be stored in Flash program code execution (i.e., lost programs). The user should memory. keep the WREN bit clear at all times, except when 11.2.1 READING THE DATA EEPROM updating EEPROM. The WREN bit is not cleared byhardware. MEMORY After a write sequence has been initiated, clearing the To read a data memory location, the user must write the WREN bit will not affect this write cycle. The WR bit will address to the EEADRL register, clear the EEPGD and be inhibited from being set unless the WREN bit is set. CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next At the completion of the write cycle, the WR bit is cycle, in the EEDATL register; therefore, it can be read cleared in hardware and the EE Write Complete in the next instruction. EEDATL will hold this value until Interrupt Flag bit (EEIF) is set. The user can either another read or until it is written to by the user (during enable this interrupt or poll this bit. EEIF must be a write operation). cleared by software. 11.2.3 PROTECTION AGAINST SPURIOUS EXAMPLE 11-1: DATA EEPROM READ WRITE BANKSELEEADRL ; MOVLW DATA_EE_ADDR ; There are conditions when the user may not want to MOVWF EEADRL ;Data Memory write to the data EEPROM memory. To protect against ;Address to read spurious EEPROM writes, various mechanisms have BCF EECON1, CFGS ;Deselect Config space been built-in. On power-up, WREN is cleared. Also, the BCF EECON1, EEPGD;Point to DATA memory Power-up Timer (64ms duration) prevents EEPROM BSF EECON1, RD ;EE Read write. MOVF EEDATL, W ;W = EEDATL The write initiate sequence and the WREN bit together help prevent an accidental write during: • Brown-out Note: Data EEPROM can be read regardless of • Power Glitch the setting of the CPD bit. • Software Malfunction 11.2.4 DATA EEPROM OPERATION DURING CODE-PROTECT Data memory can be code-protected by programming the CPD bit in the Configuration Word 1 (Register4-1) to ‘0’. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. DS41391D-page 102  2011 Microchip Technology Inc.

PIC16(L)F1826/27 EXAMPLE 11-2: DATA EEPROM WRITE BANKSEL EEADRL ; MOVLW DATA_EE_ADDR ; MOVWF EEADRL ;Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATL ;Data Memory Value to write BCF EECON1, CFGS ;Deselect Configuration space BCF EECON1, EEPGD ;Point to DATA memory BSF EECON1, WREN ;Enable writes BCF INTCON, GIE ;Disable INTs. MOVLW 55h ; RequiredSequence MMMBOOOSVVVFWLWFWF E0EEEAEECACCOhOONNN221, WR ;;;;WWSerriit ttWeeR 5Ab5Aihht to begin write BSF INTCON, GIE ;Enable Interrupts BCF EECON1, WREN ;Disable writes BTFSC EECON1, WR ;Wait for write to complete GOTO $-2 ;Done  2011 Microchip Technology Inc. DS41391D-page 103

PIC16(L)F1826/27 FIGURE 11-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR PC PC + 1 EEADRH,EEADRL PPCC ++ 33 PC + 4 PC + 5 Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4) INSTR(PC - 1) BSF PMCON1,RD INSTR(PC + 1) Forced NOP INSTR(PC + 3) INSTR(PC + 4) executed here executed here executed here executed here executed here executed here RD bit EEDATH EEDATL Register DS41391D-page 104  2011 Microchip Technology Inc.

PIC16(L)F1826/27 11.3 Flash Program Memory Overview 11.3.1 READING THE FLASH PROGRAM MEMORY It is important to understand the Flash program mem- ory structure for erase and programming operations. To read a program memory location, the user must: Flash Program memory is arranged in rows. A row con- 1. Write the Least and Most Significant address sists of a fixed number of 14-bit program memory bits to the EEADRH:EEADRL register pair. words. A row is the minimum block size that can be 2. Clear the CFGS bit of the EECON1 register. erased by user software. 3. Set the EEPGD control bit of the EECON1 Flash program memory may only be written or erased register. if the destination address is in a segment of memory 4. Then, set control bit RD of the EECON1 register. that is not write-protected, as defined in bits WRT<1:0> Once the read control bit is set, the program memory of Configuration Word 2. Flash controller will use the second instruction cycle to After a row has been erased, the user can reprogram read the data. This causes the second instruction all or a portion of this row. Data to be written into the immediately following the “BSF EECON1,RD” instruction program memory row is written to 14-bit wide data write to be ignored. The data is available in the very next cycle, latches. These write latches are not directly accessible in the EEDATH:EEDATL register pair; therefore, it can to the user, but may be loaded via sequential writes to be read as two bytes in the following instructions. the EEDATH:EEDATL register pair. EEDATH:EEDATL register pair will hold this value until Note: If the user wants to modify only a portion another read or until it is written to by the user. of a previously programmed row, then the Note1: The two instructions following a program contents of the entire row must be read and saved in RAM prior to the erase. memory read are required to be NOPs. This prevents the user from executing a The number of data write latches may not be equivalent two-cycle instruction on the next to the number of row locations. During programming, instruction after the RD bit is set. user software may need to fill the set of write latches 2: Flash program memory can be read and initiate a programming operation multiple times in regardless of the setting of the CP bit. order to fully reprogram an erased row. For example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times. The size of a program memory row and the number of program memory write latches may vary by device. See Table11-1 for details. TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Erase Block Number of Device (Row) Size/ Write Latches/ Boundary Boundary PIC16(L)F1826/27 32 words, 32 words, EEADRL<4:0> EEADRL<4:0> = 00000 = 00000  2011 Microchip Technology Inc. DS41391D-page 105

PIC16(L)F1826/27 EXAMPLE 11-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL EEADRL ; Select Bank for EEPROM registers MOVLW PROG_ADDR_LO ; MOVWF EEADRL ; Store LSB of address MOVLW PROG_ADDR_HI ; MOVWL EEADRH ; Store MSB of address BCF EECON1,CFGS ; Do not select Configuration Space BSF EECON1,EEPGD ; Select Program Memory BCF INTCON,GIE ; Disable interrupts BSF EECON1,RD ; Initiate read NOP ; Ignored (Figure 11-1) NOP ; Ignored (Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS41391D-page 106  2011 Microchip Technology Inc.

PIC16(L)F1826/27 11.3.2 ERASING FLASH PROGRAM The following steps should be completed to load the MEMORY write latches and program a block of program memory. These steps are divided into two parts. First, all write While executing code, program memory can only be latches are loaded with data except for the last program erased by rows. To erase a row: memory location. Then, the last write latch is loaded 1. Load the EEADRH:EEADRL register pair with and the programming sequence is initiated. A special the address of new row to be erased. unlock sequence is required to load a write latch with 2. Clear the CFGS bit of the EECON1 register. data or initiate a Flash programming operation. This 3. Set the EEPGD, FREE, and WREN bits of the unlock sequence should not be interrupted. EECON1 register. 1. Set the EEPGD and WREN bits of the EECON1 4. Write 55h, then AAh, to EECON2 (Flash register. programming unlock sequence). 2. Clear the CFGS bit of the EECON1 register. 5. Set control bit WR of the EECON1 register to 3. Set the LWLO bit of the EECON1 register. When begin the erase operation. the LWLO bit of the EECON1 register is ‘1’, the 6. Poll the FREE bit in the EECON1 register to write sequence will only load the write latches determine when the row erase has completed. and will not initiate the write to Flash program memory. See Example11-4. 4. Load the EEADRH:EEADRL register pair with After the “BSF EECON1,WR” instruction, the processor the address of the location to be written. requires two cycles to set up the erase operation. The 5. Load the EEDATH:EEDATL register pair with user must place two NOP instructions after the WR bit is the program memory data to be written. set. The processor will halt internal operations for the 6. Write 55h, then AAh, to EECON2, then set the typical 2ms erase time. This is not Sleep mode as the WR bit of the EECON1 register (Flash clocks and peripherals will continue to run. After the programming unlock sequence). The write latch erase cycle, the processor will resume operation with is now loaded. the third instruction after the EECON1 write instruction. 7. Increment the EEADRH:EEADRL register pair 11.3.3 WRITING TO FLASH PROGRAM to point to the next location. MEMORY 8. Repeat steps 5 through 7 until all but the last Program memory is programmed using the following write latch has been loaded. steps: 9. Clear the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is 1. Load the starting address of the word(s) to be ‘0’, the write sequence will initiate the write to programmed. Flash program memory. 2. Load the write latches with data. 10. Load the EEDATH:EEDATL register pair with 3. Initiate a programming operation. the program memory data to be written. 4. Repeat steps 1 through 3 until all data is written. 11. Write 55h, then AAh, to EECON2, then set the Before writing to program memory, the word(s) to be WR bit of the EECON1 register (Flash written must be erased or previously unwritten. Pro- programming unlock sequence). The entire gram memory can only be erased one row at a time. No latch block is now written to Flash program automatic erase occurs upon the initiation of the write. memory. Program memory can be written one or more words at It is not necessary to load the entire write latch block a time. The maximum number of words written at one with user program data. However, the entire write latch time is equal to the number of write latches. See block will be written to program memory. Figure11-2 (block writes to program memory with 32 An example of the complete write sequence for eight write latches) for more details. The write latches are words is shown in Example11-5. The initial address is aligned to the address boundary defined by EEADRL loaded into the EEADRH:EEADRL register pair; the as shown in Table11-1. Write operations do not cross eight words of data are loaded using indirect addressing. these boundaries. At the completion of a program memory write operation, the write latches are reset to contain 0x3FFF.  2011 Microchip Technology Inc. DS41391D-page 107

PIC16(L)F1826/27 After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the write operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. FIGURE 11-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 7 5 0 7 0 EEDATH EEDATA 6 8 First word of block Last word of block to be written to be written 14 14 14 14 EEADRL<4:0> = 00000 EEADRL<4:0> = 00001 EEADRL<4:0> = 00010 EEADRL<4:0> = 11111 Buffer Register Buffer Register Buffer Register Buffer Register Program Memory DS41391D-page 108  2011 Microchip Technology Inc.

PIC16(L)F1826/27 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY - ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL EEADRL MOVF ADDRL,W ; Load lower 8 bits of erase address boundary MOVWF EEADRL MOVF ADDRH,W ; Load upper 6 bits of erase address boundary MOVWF EEADRH BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space BSF EECON1,FREE ; Specify an erase operation BSF EECON1,WREN ; Enable writes MOVLW 55h ; Start of required sequence to initiate erase MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne reer aasree ignored as processor ; halts to begin erase sequence NOP ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts  2011 Microchip Technology Inc. DS41391D-page 109

PIC16(L)F1826/27 EXAMPLE 11-5: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL ; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) ; BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL EEADRH ; Bank 3 MOVF ADDRH,W ; Load initial address MOVWF EEADRH ; MOVF ADDRL,W ; MOVWF EEADRL ; MOVLW LOW DATA_ADDR ; Load initial data address MOVWF FSR0L ; MOVLW HIGH DATA_ADDR ; Load initial data address MOVWF FSR0H ; BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space BSF EECON1,WREN ; Enable writes BSF EECON1,LWLO ; Only Load Write Latches LOOP MOVIW FSR0++ ; Load first data byte into lower MOVWF EEDATL ; MOVIW FSR0++ ; Load second data byte into upper MOVWF EEDATH ; MOVF EEADRL,W ; Check if lower bits of address are '000' XORLW 0x07 ; Check if we're on the last of 8 addresses ANDLW 0x07 ; BTFSC STATUS,Z ; Exit if last of eight words, GOTO START_WRITE ; MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne rwer iatree ignored as processor ; halts to begin write sequence NOP ; Processor will stop here and wait for write to complete. ; After write processor continues with 3rd instruction. INCF EEADRL,F ; Still loading latches Increment address GOTO LOOP ; Write next latches START_WRITE BCF EECON1,LWLO ; No more loading latches - Actually start Flash program ; memory write MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne rwer iatree ignored as processor ; halts to begin write sequence NOP ; Processor will stop here and wait for write complete. ; after write processor continues with 3rd instruction BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts DS41391D-page 110  2011 Microchip Technology Inc.

PIC16(L)F1826/27 11.4 Modifying Flash Program Memory 11.5 User ID, Device ID and Configuration Word Access When modifying existing data in a program memory row, and data within that row must be preserved, it must Instead of accessing program memory or EEPROM first be read and saved in a RAM image. Program data memory, the User ID’s, Device ID/Revision ID and memory is modified using the following steps: Configuration Words can be accessed when CFGS=1 1. Load the starting address of the row to be mod- in the EECON1 register. This is the region that would ified. be pointed to by PC<15>=1, but not all addresses are accessible. Different access may exist for reads and 2. Read the existing data from the row into a RAM writes. Refer to Table11-2. image. 3. Modify the RAM image to contain the new data When read access is initiated on an address outside to be written into program memory. the parameters listed in Table11-2, the EEDATH:EED- ATL register pair is cleared. 4. Load the starting address of the row to be rewrit- ten. 5. Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. 8. Repeat steps 6 and 7 as many times as required to reprogram the erased row. TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS=1) Address Function Read Access Write Access 8000h-8003h User IDs Yes Yes 8006h Device ID/Revision ID Yes No 8007h-8008h Configuration Words 1 and 2 Yes No EXAMPLE 11-3: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL EEADRL ; Select correct Bank MOVLW PROG_ADDR_LO ; MOVWF EEADRL ; Store LSB of address CLRF EEADRH ; Clear MSB of address BSF EECON1,CFGS ; Select Configuration Space BCF INTCON,GIE ; Disable interrupts BSF EECON1,RD ; Initiate read NOP ; Executed (See Figure 11-1) NOP ; Ignored (See Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2011 Microchip Technology Inc. DS41391D-page 111

PIC16(L)F1826/27 11.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example11-6) to the desired value to be written. Example11-6 shows how to verify a write to EEPROM. EXAMPLE 11-6: EEPROM WRITE VERIFY BANKSELEEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL, W ; BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue DS41391D-page 112  2011 Microchip Technology Inc.

PIC16(L)F1826/27 11.7 EEPROM and Flash Control Registers REGISTER 11-1: EEDATL: EEPROM LOW BYTE DATA REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 11-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — EEDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 EEDAT<13:8>: Read/write value for Most Significant bits of program memory REGISTER 11-3: EEADRL: EEPROM ADDRESS REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address  2011 Microchip Technology Inc. DS41391D-page 113

PIC16(L)F1826/27 REGISTER 11-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — EEADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address DS41391D-page 114  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Accesses program space Flash memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, User ID and Device ID Registers 0 = Accesses Flash Program or data EEPROM Memory bit 5 LWLO: Load Write Latches Only bit If CFGS=1 (Configuration space) OR CFGS=0 and EEPGD=1 (program Flash): 1 = The next WR command does not initiate a write; only the program memory latches are updated. 0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write of all the data stored in the program memory latches. If CFGS=0 and EEPGD=0: (Accessing data EEPROM) LWLO is ignored. The next WR command initiates a write to the data EEPROM. bit 4 FREE: Program Flash Erase Enable bit If CFGS=1 (Configuration space) OR CFGS=0 and EEPGD=1 (program Flash): 1 = Performs an erase operation on the next WR command (cleared by hardware after comple- tion of erase). 0 = Performs a write operation on the next WR command. If EEPGD=0 and CFGS=0: (Accessing data EEPROM) FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle. bit 3 WRERR: EEPROM Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit). 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash and data EEPROM bit 1 WR: Write Control bit 1 = Initiates a program Flash or data EEPROM program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash or data EEPROM is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash or data EEPROM data read.  2011 Microchip Technology Inc. DS41391D-page 115

PIC16(L)F1826/27 REGISTER 11-6: EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. Refer to Section11.2.2 “Writing to the Data EEPROM Memory” for more information. TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 115 EECON2 EEPROM Control Register 2 (not a physical register) 101* EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 113 EEADRH — EEADRH6 EEADRH5 EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 114 EEDATL EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDALT1 EEDATL0 113 EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 113 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 91 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE 93 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF 97 Legend: — = unimplemented read as ‘0’. Shaded cells are not used by data EEPROM module. * Page provides register information. DS41391D-page 116  2011 Microchip Technology Inc.

PIC16(L)F1826/27 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION Depending on the device selected and peripherals enabled, there are two ports available. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Read LATx TRISx Each port has three registers for its operation. These registers are: D Q • TRISx registers (data direction register) Write LATx • PORTx registers (reads the levels on the pins of Write PORTx CK VDD the device) Data Register • LATx registers (output latch) Some ports may have one or more of the following Data Bus additional registers. These registers are: I/O pin Read PORTx • ANSELx (analog select) • WPUx (weak pull-up) To peripherals VSS ANSELx TABLE 12-1: PORT AVAILABILITY PER DEVICE EXAMPLE 12-1: INITIALIZING PORTA TA TB TC ; This code example illustrates Device R R R ; initializing the PORTA register. The O O O P P P ; other ports are initialized in the same ; manner. PIC16(L)F1826 ● ● PIC16(L)F1827 ● ● ● BANKSEL PORTA ; CLRF PORTA ;Init PORTA The Data Latch (LATx registers) is useful for BANKSEL LATA ;Data Latch read-modify-write operations on the value that the I/O CLRF LATA ; pins are driving. BANKSEL ANSELA ; CLRF ANSELA ;digital I/O A write operation to the LATx register has the same BANKSEL TRISA ; effect as a write to the corresponding PORTx register. MOVLW B'00111000' ;Set RA<5:3> as inputs A read of the LATx register reads of the values held in MOVWF TRISA ;and set RA<2:0> as the I/O PORT latches, while a read of the PORTx ;outputs register reads the actual I/O pin value. Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure12-1.  2011 Microchip Technology Inc. DS41391D-page 117

PIC16(L)F1826/27 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON0 and APFCON1) registers are used to steer specific peripheral input and output functions between different pins. The APFCON0 and APFCON1 registers are shown in Register12-1 and Register12-2. For this device family, the following functions can be moved between different pins. • RX/DT • SDO1 • SS1 (Slave Select 1) • P2B • CCP2/P2A • P1D • P1C • CCP1/P1A • TX/CK These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. DS41391D-page 118  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 12-1: APFCON0: ALTERNATE PIN FUNCTION CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RXDTSEL SDO1SEL SS1SEL P2BSEL(1) CCP2SEL(1) P1DSEL P1CSEL CCP1SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RXDTSEL: Pin Selection bit 0 = RX/DT function is on RB1 1 = RX/DT function is on RB2 bit 6 SDO1SEL: Pin Selection bit 0 = SDO1 function is on RB2 1 = SDO1 function is on RA6 bit 5 SS1SEL: Pin Selection bit 0 = SS1 function is on RB5 1 = SS1 function is on RA5 bit 4 P2BSEL: Pin Selection bit 0 = P2B function is on RB7 1 = P2B function is on RA6 bit 3 CCP2SEL: Pin Selection bit 0 = CCP2/P2A function is on RB6 1 = CCP2/P2A function is on RA7 bit 2 P1DSEL: Pin Selection bit 0 = P1D function is on RB7 1 = P1D function is on RA6 bit 1 P1CSEL: Pin Selection bit 0 = P1C function is on RB6 1 = P1C function is on RA7 bit 0 CCP1SEL: Pin Selection bit 0 = CCP1/P1A function is on RB3 1 = CCP1/P1A function is on RB0 Note 1: PIC16(L)F1827 only. REGISTER 12-2: APFCON1: ALTERNATE PIN FUNCTION CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 — — — — — — — TXCKSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 TXCKSEL: Pin Selection bit 0 = TX/CK function is on RB2 1 = TX/CK function is on RB5  2011 Microchip Technology Inc. DS41391D-page 119

PIC16(L)F1826/27 12.2 PORTA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register12-4). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA5, which is input only and its TRIS bit will always read as ‘1’. Example12-1 shows how to initialize an I/O port. Reading the PORTA register (Register12-3) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). The TRISA register (Register12-4) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. 12.2.1 WEAK PULL-UPS Each of the PORTA pins has an individually configurable internal weak pull-up. Control bit WPUA<5> enables or disables the pull-up (see Register12-6). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-up is disabled on a Power-on Reset by the WPUEN bit of the OPTION register. 12.2.2 ANSELA REGISTER The ANSELA register (Register12-7) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. DS41391D-page 120  2011 Microchip Technology Inc.

PIC16(L)F1826/27 12.2.3 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table12-2. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input functions, such as ADC, comparator and CapSense inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown in Table12-2. TABLE 12-2: PORTA OUTPUT PRIORITY Pin Name Function Priority(1) RA0 SDO2 (PIC16(L)F1827 only) RA0 RA1 SS2 (PIC16(L)F1827 only) RA1 RA2 DACOUT (DAC) RA2 RA3 SRQ (SR latch) CCP3 (PIC16(L)F1827 only) C1OUT (Comparator) RA3 RA4 SRNQ (SR latch) CCP4 (PIC16(L)F1827 only) T0CKI C2OUT (Comparator) RA4 RA5 Input only pin RA6 OSC2 (enabled by Configura- tion Word) CLKOUT CLKR SDO1 P1D P2B (PIC16(L)F1827 only) RA6 RA7 OSC1/CLKIN (enabled by Configuration Word) P1C CCP2 (PIC16(L)F1827 only) P2A (PIC16(L)F1827 only) RA7 Note 1: Priority listed from highest to lowest. Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists.  2011 Microchip Technology Inc. DS41391D-page 121

PIC16(L)F1826/27 REGISTER 12-3: PORTA: PORTA REGISTER R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RA<7:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-4: TRISA: PORTA TRI-STATE REGISTER R/W-1/1 R/W-1/1 R-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TRISA<7:6>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 5 TRISA5: RA5 Port Tri-State Control bit This bit is always ‘1’ as RA5 is an input only bit 4-0 TRISA<4:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output REGISTER 12-5: LATA: PORTA DATA LATCH REGISTER R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATA7 LATA6 — LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 LATA<7:6>: RA<7:6> Output Latch Value bits(1) bit 5 Unimplemented: Read as ‘0 bit 4-0 LATA<4:0>: RA<4:0> Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. DS41391D-page 122  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 12-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 U-0 U-0 U-0 U-0 U-0 — — WPUA5 — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 WPUA5: Weak Pull-up RA5 Control bit If MCLRE in Configuration Word 1 = 0, MCLR is disabled): 1 = Weak Pull-up enabled(1) 0 = Weak Pull-up disabled If MCLRE in Configuration Word 1 = 1, MCLR is enabled): Weak Pull-up is always enabled. bit 4-0 Unimplemented: Read as ‘0’ Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. REGISTER 12-7: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 ANSA<4:0>: Analog Select between Analog or Digital Function on pins RA<4:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.  2011 Microchip Technology Inc. DS41391D-page 123

PIC16(L)F1826/27 TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 123 LATA LATA7 LATA6 — LATA4 LATA3 LATA2 LATA1 LATA0 122 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 176 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 122 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122 WPUA — — WPUA5 — — — — — 123 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. TABLE 12-4: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH PORTA Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD CONFIG1 44 7:0 CP MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. DS41391D-page 124  2011 Microchip Technology Inc.

PIC16(L)F1826/27 12.3 PORTB and TRISB Registers 12.3.3 ANSELB REGISTER PORTB is an 8-bit wide, bidirectional port. The The ANSELB register (Register12-12) is used to corresponding data direction register is TRISB configure the Input mode of an I/O pin to analog. (Register12-9). Setting a TRISB bit (= 1) will make the Setting the appropriate ANSELB bit high will cause all corresponding PORTB pin an input (i.e., put the digital reads on the pin to be read as ‘0’ and allow corresponding output driver in a High-Impedance mode). analog functions on the pin to operate correctly. Clearing a TRISB bit (= 0) will make the corresponding The state of the ANSELB bits has no affect on digital PORTB pin an output (i.e., enable the output driver and output functions. A pin with TRIS clear and ANSELB set put the contents of the output latch on the selected pin). will still operate as a digital output, but the Input mode Example12-1 shows how to initialize an I/O port. will be analog. This can cause unexpected behavior Reading the PORTB register (Register12-8) reads the when executing read-modify-write instructions on the status of the pins, whereas writing to it will write to the affected port. PORT latch. All write operations are read-modify-write The TRISB register (Register12-9) controls the PORTB operations. Therefore, a write to a port implies that the pin output drivers, even when they are being used as port pins are read, this value is modified and then written analog inputs. The user should ensure the bits in the to the PORT data latch. TRISB register are maintained set when using them as The TRISB register (Register12-9) controls the PORTB analog inputs. I/O pins configured as analog input always pin output drivers, even when they are being used as read ‘0’. analog inputs. The user should ensure the bits in the Note: The ANSELB register must be initialized TRISB register are maintained set when using them as to configure an analog channel as a digital analog inputs. I/O pins configured as analog input always input. Pins configured as analog inputs read ‘0’. will read ‘0’. 12.3.1 INTERRUPT-ON-CHANGE All of the PORTB pins are individually configurable as an interrupt-on-change pin. Control bits IOCB<7:0> enable or disable the interrupt function for each pin. The interrupt-on-change feature is disabled on a Power-on Reset. Reference Section13.0 “Interrupt-On-Change” for more information. 12.3.2 WEAK PULL-UPS Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:0> enable or disable each pull-up (see Register12-11). Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the WPUEN bit of the OPTION register.  2011 Microchip Technology Inc. DS41391D-page 125

PIC16(L)F1826/27 12.3.4 PORTB FUNCTIONS AND OUTPUT PRIORITIES TABLE 12-5: PORTB OUTPUT PRIORITY Each PORTB pin is multiplexed with other functions. The Pin Name Function Priority(1) pins, their combined functions and their output priorities RB0 P1A are shown in Table12-5. RB0 When multiple outputs are enabled, the actual pin RB1 SDA1 control goes to the peripheral with the highest priority. RX/DT Analog input and some digital input functions are not RB1 included in the list below. These input functions can RB2 SDA2 (PIC16(L)F1827 only) remain active when the pin is configured as an output. TX/CK Certain digital input functions, such as the EUSART RX RX/DT signal, override other port functions and are included in SDO1 the priority list. RB2 RB3 MDOUT CCP1/P1A RB3 RB4 SCL1 SCK1 RB4 RB5 SCL2 (PIC16(L)F1827 only) TX/CK SCK2 (PIC16(L)F1827 only) P1B RB5 RB6 ICSPCLK (Programming) T1OSI P1C CCP2 (PIC16(L)F1827 only) P2A (PIC16(L)F1827 only) RB6 RB7 ICSPDAT (Programming) T1OSO P1D P2B (PIC16(L)F1827 only) RB7 Note 1: Priority listed from highest to lowest. DS41391D-page 126  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 12-8: PORTB: PORTB REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RB<7:0>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 12-9: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output REGISTER 12-10: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 LATB<7:0>: PORTB Output Latch Value bits(1) Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values.  2011 Microchip Technology Inc. DS41391D-page 127

PIC16(L)F1826/27 REGISTER 12-11: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. REGISTER 12-12: ANSELB: PORTB ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 ANSB<7:1>: Analog Select between Analog or Digital Function on Pins RB<7:1>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 0 Unimplemented: Read as ‘0’ Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS41391D-page 128  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — 128 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 127 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 176 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 127 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 128 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.  2011 Microchip Technology Inc. DS41391D-page 129

PIC16(L)F1826/27 NOTES: DS41391D-page 130  2011 Microchip Technology Inc.

PIC16(L)F1826/27 13.0 INTERRUPT-ON-CHANGE 13.3 Interrupt Flags The PORTB pins can be configured to operate as The IOCBFx bits located in the IOCBF register are Interrupt-On-Change (IOC) pins. An interrupt can be status flags that correspond to the Interrupt-on-change generated by detecting a signal that has either a rising pins of the port. If an expected edge is detected on an edge or a falling edge. Any individual PORTB pin can appropriately enabled pin, then the status flag for that pin be configured to generate an interrupt. The will be set, and an interrupt will be generated if the IOCIE interrupt-on-change module has the following features: bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCBFx bits. • Interrupt-on-Change enable (Master Switch) • Individual pin configuration 13.4 Clearing Interrupt Flags • Rising and falling edge detection • Individual pin interrupt flags The individual status flags, (IOCBFx bits), can be cleared by resetting them to zero. If another edge is Figure13-1 is a block diagram of the IOC module. detected during this clearing operation, the associated status flag will be set at the end of the sequence, 13.1 Enabling the Module regardless of the value actually being written. To allow individual port pins to generate an interrupt, the In order to ensure that no detected edge is lost while IOCIE bit of the INTCON register must be set. If the clearing flags, only AND operations masking out known IOCIE bit is disabled, the edge detection on the pin will changed bits should be performed. The following still occur, but an interrupt will not be generated. sequence is an example of what should be performed. 13.2 Individual Pin Configuration EXAMPLE 13-1: For each port pin, a rising edge detector and a falling MOVLW 0xff edge detector are present. To enable a pin to detect a XORWF IOCBF, W ANDWF IOCBF, F rising edge, the associated IOCBPx bit of the IOCBP register is set. To enable a pin to detect a falling edge, the associated IOCBNx bit of the IOCBN register is set. 13.5 Operation in Sleep A pin can be configured to detect rising and falling The interrupt-on-change interrupt sequence will wake edges simultaneously by setting both the IOCBPx bit the device from Sleep mode, if the IOCIE bit is set. and the IOCBNx bit of the IOCBP and IOCBN registers, respectively. If an edge is detected while in Sleep mode, the IOCBF register will be updated prior to the first instruction executed out of Sleep. FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCIE IOCBNx D Q IOCBFx CK From all other IOCBFx individual pin detectors R IOC Interrupt to RBx CPU Core IOCBPx D Q CK R Q2 Clock Cycle  2011 Microchip Technology Inc. DS41391D-page 131

PIC16(L)F1826/27 13.6 Interrupt-On-Change Registers REGISTER 13-1: IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits 1 = Interrupt-on-change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-change disabled for the associated pin. REGISTER 13-2: IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBN<7:0>: Interrupt-on-Change Negative Edge Enable bits 1 = Interrupt-on-change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-change disabled for the associated pin. REGISTER 13-3: IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-0 IOCBF<7:0>: Interrupt-on-Change Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx=1 and a rising edge was detected on RBx, or when IOCBNx=1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. DS41391D-page 132  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — 128 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 132 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 132 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 132 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by interrupt-on-change.  2011 Microchip Technology Inc. DS41391D-page 133

PIC16(L)F1826/27 NOTES: DS41391D-page 134  2011 Microchip Technology Inc.

PIC16(L)F1826/27 14.0 FIXED VOLTAGE REFERENCE 14.1 Independent Gain Amplifiers (FVR) The output of the FVR supplied to the ADC, Comparators, and DAC and CPS is routed through two The Fixed Voltage Reference, or FVR, is a stable independent programmable gain amplifiers. Each voltage reference, independent of VDD, with 1.024V, amplifier can be configured to amplify the reference 2.048V or 4.096V selectable output levels. The output voltage by 1x, 2x or 4x, to produce the three possible of the FVR can be configured to supply a reference voltage levels. voltage to the following: The ADFVR<1:0> bits of the FVRCON register are • ADC input channel used to enable and configure the gain amplifier settings • ADC positive reference for the reference supplied to the ADC module. Refer- • Comparator positive input ence Section16.0 “Analog-to-Digital Converter • Digital-to-Analog Converter (DAC) (ADC) Module” for additional information. • Capacitive Sensing (CPS) module The CDAFVR<1:0> bits of the FVRCON register are The FVR can be enabled by setting the FVREN bit of used to enable and configure the gain amplifier settings the FVRCON register. for the reference supplied to the DAC and comparator module. Reference Section16.0 “Digital-to-Analog Converter (DAC) Module” and Section18.0 “Com- parator Module” and Section27.0 “Capacitive Sensing Module” for additional information. 14.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section30.0 “Electrical Specifications” for the minimum delay requirement. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 X1 X2 FVR BUFFER1 X4 (To ADC Module) CDAFVR<1:0> 2 X1 X2 FVR BUFFER2 X4 (To Comparators, DAC, CPS) 1.024V Fixed Reference + FVREN _ FVRRDY Any peripheral requiring the Fixed Reference (See Table14-1)  2011 Microchip Technology Inc. DS41391D-page 135

PIC16(L)F1826/27 14.3 FVR Control Registers REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FVREN FVRRDY(1) Reserved Reserved CDAFVR<1:0> ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 0 = Fixed Voltage Reference output is not ready or not enabled 1 = Fixed Voltage Reference output is ready for use bit 5-4 Reserved: Read as ‘0’. Maintain these bits clear. bit 3-2 CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bit 00 =Comparator and DAC Fixed Voltage Reference Peripheral output is off. 01 =Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 =Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 =Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit 00 =ADC Fixed Voltage Reference Peripheral output is off. 01 =ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 =ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 =ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) Note 1: FVRRDY is always ‘1’ on devices with LDO (PIC16F1826/27). 2: Fixed Voltage Reference output cannot exceed VDD. TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE FVR MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 136 Legend: Shaded cells are unused by the FVR module. DS41391D-page 136  2011 Microchip Technology Inc.

PIC16(L)F1826/27 15.0 TEMPERATURE INDICATOR FIGURE 15-1: TEMPERATURE CIRCUIT MODULE DIAGRAM This family of devices is equipped with a temperature VDD circuit designed to measure the operating temperature of the silicon die. The circuit's range of operating TSEN temperature falls between of -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is TSRNG internally connected to the device ADC. The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A one- point calibration allows the circuit to indicate a VOUT ADC temperature closely surrounding that point. A two-point MUX ADC calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal n Temperature Indicator” (DS01333) for more details CHS bits regarding the calibration process. (ADCON0 register) 15.1 Circuit Operation Figure15-1 shows a simplified block diagram of the 15.2 Minimum Operating VDD vs. temperature circuit. The proportional voltage output is Minimum Sensing Temperature achieved by measuring the forward voltage drop across When the temperature circuit is operated in low range, multiple silicon junctions. the device may be operated at any operating voltage Equation15-1 describes the output characteristics of that is within specifications. the temperature indicator. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high EQUATION 15-1: VOUT RANGES enough to ensure that the temperature circuit is cor- rectly biased. High Range: VOUT = VDD - 4VT Table15-1 shows the recommended minimum VDD vs. range setting. Low Range: VOUT = VDD - 2VT TABLE 15-1: RECOMMENDED VDD VS. RANGE The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 Section14.0 “Fixed Voltage Reference (FVR)” for 3.6V 1.8V more information. The circuit is enabled by setting the TSEN bit of the 15.3 Temperature Output FVRCON register. When disabled, the circuit draws no current. The output of the circuit is measured using the internal analog to digital converter. Channel 29 is reserved for The circuit operates in either high or low range. The high the temperature circuit output. Refer to Section16.0 range, selected by setting the TSRNG bit of the “Analog-to-Digital Converter (ADC) Module” for FVRCON register, provides a wider output voltage. This detailed information. provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.  2011 Microchip Technology Inc. DS41391D-page 137

PIC16(L)F1826/27 NOTES: DS41391D-page 138  2011 Microchip Technology Inc.

PIC16(L)F1826/27 16.0 ANALOG-TO-DIGITAL The ADC can generate an interrupt upon completion of CONVERTER (ADC) MODULE a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure16-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 16-1: ADC BLOCK DIAGRAM VREF- ADNREF = 1 ADNREF = 0 VSS VDD ADPREF = 00 ADPREF = 11 VREF+ ADPREF = 10 AN0 00000 AN1 00001 AN2 00010 AN3 00011 AN4 00100 AN5 00101 AN6 00110 AN7 00111 AN8 01000 ADC AN9 01001 GO/DONE 10 AN10 01010 AN11 01011 ADFM 0 = Left Justify 1 = Right Justify ADON 16 Temp Indicator 11101 VSS ADRESH ADRESL DAC 11110 FVR Buffer1 11111 CHS<4:0>(2) Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: See ADCON0 register (Register16-1) for detailed analog channel selection per device.  2011 Microchip Technology Inc. DS41391D-page 139

PIC16(L)F1826/27 16.1 ADC Configuration 16.1.4 CONVERSION CLOCK When configuring and using the ADC the following The source of the conversion clock is software select- functions must be considered: able via the ADCS bits of the ADCON1 register. There are seven possible clock options: • Port configuration • FOSC/2 • Channel selection • FOSC/4 • ADC voltage reference selection • FOSC/8 • ADC conversion clock source • FOSC/16 • Interrupt control • FOSC/32 • Result formatting • FOSC/64 16.1.1 PORT CONFIGURATION • FRC (dedicated internal oscillator) The ADC can be used to convert both analog and The time to complete one bit conversion is defined as digital signals. When converting analog signals, the I/O TAD. One full 10-bit conversion requires 11.5 TAD peri- pin should be configured for analog by setting the ods as shown in Figure16-2. associated TRIS and ANSEL bits. Refer to For correct conversion, the appropriate TAD specifica- Section12.0 “I/O Ports” for more information. tion must be met. Refer to the A/D conversion require- Note: Analog voltages on any pin that is defined ments in Section30.0 “Electrical Specifications”for as a digital input may cause the input buf- more information. Table16-1 gives examples of appro- fer to conduct excess current. priate ADC clock selections. Note: Unless using the FRC, any changes in the 16.1.2 CHANNEL SELECTION system clock frequency will change the There are up to 15 channel selections available: ADC clock frequency, which may adversely affect the ADC result. • AN<11:0> pins • Temperature Indicator • DAC Output • FVR (Fixed Voltage Reference) Output Refer to Section14.0 “Fixed Voltage Reference (FVR)”and Section15.0 “Temperature Indicator Module” for more information on these channel selec- tions. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section16.2 “ADC Operation” for more information. 16.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: • VREF+ pin • VDD • FVR 2.048V • FVR 4.096V (Not available on LF devices) The ADNREF bits of the ADCON1 register provides control of the negative voltage reference. The negative voltage reference can be: • VREF- pin • VSS See Section14.0 “Fixed Voltage Reference (FVR)” for more details on the fixed voltage reference. DS41391D-page 140  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Clock Source FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3) FOSC/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3) FOSC/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.0 s(3) FOSC/64 110 2.0 s 3.2 s 4.0 s 8.0 s(3) 16.0 s(3) 64.0 s(3) FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 1.6 s for VDD. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.  2011 Microchip Technology Inc. DS41391D-page 141

PIC16(L)F1826/27 16.1.5 INTERRUPTS 16.1.6 RESULT FORMATTING The ADC module allows for the ability to generate an The 10-bit A/D conversion result can be supplied in two interrupt upon completion of an Analog-to-Digital formats, left justified or right justified. The ADFM bit of conversion. The ADC Interrupt Flag is the ADIF bit in the ADCON1 register controls the output format. the PIR1 register. The ADC Interrupt Enable is the Figure16-3 shows the two output formats. ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruc- tion is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execu- tion, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. FIGURE 16-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result DS41391D-page 142  2011 Microchip Technology Inc.

PIC16(L)F1826/27 16.2 ADC Operation 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This 16.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC To enable the ADC module, the ADON bit of the option. When the FRC clock source is selected, the ADCON0 register must be set to a ‘1’. Setting the GO/ ADC waits one additional instruction before starting the DONE bit of the ADCON0 register to a ‘1’ will start the conversion. This allows the SLEEP instruction to be Analog-to-Digital conversion. executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device Note: The GO/DONE bit should not be set in the will wake-up from Sleep when the conversion same instruction that turns on the ADC. completes. If the ADC interrupt is disabled, the ADC Refer to Section16.2.6 “A/D Conver- module is turned off after the conversion completes, sion Procedure”. although the ADON bit remains set. 16.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conver- When the conversion is complete, the ADC module will: sion to be aborted and the ADC module is turned off, • Clear the GO/DONE bit although the ADON bit remains set. • Set the ADIF Interrupt Flag bit 16.2.5 SPECIAL EVENT TRIGGER • Update the ADRESH and ADRESL registers with new conversion result The Special Event Trigger of the CCPx/ECCPx module allows periodic ADC measurements without software 16.2.3 TERMINATING A CONVERSION intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to If a conversion must be terminated before completion, zero. the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with TABLE 16-2: SPECIAL EVENT TRIGGER the partially complete Analog-to-Digital conversion Device CCPx/ECCPx sample. Incomplete bits will match the last bit converted. PIC16(L)F1826 ECCP1 PIC16(L)F1827 CCP4 Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is Using the Special Event Trigger does not assure proper turned off and any pending conversion is ADC timing. It is the user’s responsibility to ensure that terminated. the ADC timing requirements are met. Refer to Section24.0 “Capture/Compare/PWM Mod- ules” for more information.  2011 Microchip Technology Inc. DS41391D-page 143

PIC16(L)F1826/27 16.2.6 A/D CONVERSION PROCEDURE EXAMPLE 16-1: A/D CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. 1. Configure Port: ; • Disable pin output driver (Refer to the TRIS ;Conversion start & polling for completion register) ; are included. • Configure pin as analog (Refer to the ANSEL ; register) BANKSEL ADCON1 ; MOVLW B’11110000’ ;Right justify, Frc 2. Configure the ADC module: ;clock • Select ADC conversion clock MOVWF ADCON1 ;Vdd and Vss Vref • Configure voltage reference BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input • Select ADC input channel BANKSEL ANSEL ; • Turn on ADC module BSF ANSEL,0 ;Set RA0 to analog 3. Configure ADC interrupt (optional): BANKSEL ADCON0 ; • Clear ADC interrupt flag MOVLW B’00000001’ ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On • Enable ADC interrupt CALL SampleTime ;Acquisiton delay • Enable peripheral interrupt BSF ADCON0,ADGO ;Start conversion • Enable global interrupt(1) BTFSC ADCON0,ADGO ;Is conversion done? 4. Wait the required acquisition time(2). GOTO $-1 ;No, test again BANKSEL ADRESH ; 5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits 6. Wait for ADC conversion to complete by one of MOVWF RESULTHI ;store in GPR space the following: BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits • Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result. 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section16.4 “A/D Acquisition Requirements”. DS41391D-page 144  2011 Microchip Technology Inc.

PIC16(L)F1826/27 16.3 ADC Register Definitions The following registers are used to control the operation of the ADC. REGISTER 16-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CHS<4:0> GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 =AN0 00001 =AN1 00010 =AN2 00011 =AN3 00100 =AN4 00101 =AN5 00110 =AN6 00111 =AN7 01000 =AN8 01001 =AN9 01010 =AN10 01011 =AN11 01100 =Reserved. No channel connected. • • • 11101 =Temperature Indicator(3) 11110 =DAC output(1) 11111 =FVR (Fixed Voltage Reference) Buffer 1 Output(2) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: See Section17.0 “Digital-to-Analog Converter (DAC) Module” for more information. 2: See Section14.0 “Fixed Voltage Reference (FVR)” for more information. 3: See Section15.0 “Temperature Indicator Module” for more information.  2011 Microchip Technology Inc. DS41391D-page 145

PIC16(L)F1826/27 REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded. bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 =FOSC/2 001 =FOSC/8 010 =FOSC/32 011 =FRC (clock supplied from a dedicated RC oscillator) 100 =FOSC/4 101 =FOSC/16 110 =FOSC/64 111 =FRC (clock supplied from a dedicated RC oscillator) bit 3 Unimplemented: Read as ‘0’ bit 2 ADNREF: A/D Negative Voltage Reference Configuration bit 0 = VREF- is connected to VSS 1 = VREF- is connected to external VREF- pin(1) bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits 00 = VREF+ is connected to VDD 01 = Reserved 10 = VREF+ is connected to external VREF+ pin(1) 11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1) Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section30.0 “Electrical Specifications” for details. DS41391D-page 146  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 16-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 16-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<1:0> — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use.  2011 Microchip Technology Inc. DS41391D-page 147

PIC16(L)F1826/27 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result REGISTER 16-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result DS41391D-page 148  2011 Microchip Technology Inc.

PIC16(L)F1826/27 16.4 A/D Acquisition Requirements source impedance is decreased, the acquisition time may be decreased. After the analog input channel is For the ADC to meet its specified accuracy, the charge selected (or changed), an A/D acquisition must be holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate charge to the input channel voltage level. The Analog the minimum acquisition time, Equation16-1 may be Input model is shown in Figure16-4. The source used. This equation assumes that 1/2 LSb error is used impedance (RS) and the internal sampling switch (RSS) (1,024 steps for the ADC). The 1/2 LSb error is the impedance directly affect the time required to charge maximum error allowed for the ADC to meet its the capacitor CHOLD. The sampling switch (RSS) specified resolution. impedance varies over the device voltage (VDD), refer to Figure16-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 16-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– ------n----+----1------------ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb 2 –1 –TC  ---------- RC VAPPLIED1–e  = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– ------n---+-----1------------ ;combining [1] and [2]   2  –1 Note: Where n = number of bits of the ADC. Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/511) = –10pF1k+7k+10k ln(0.001957) = 1.12µs Therefore: TACQ = 2µs+1.12µs+50°C- 25°C0.05µs/°C = 4.42µs Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification.  2011 Microchip Technology Inc. DS41391D-page 149

PIC16(L)F1826/27 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Sampling Input Switch VT  0.6V Rs pin RIC  1k SS Rss VA C5 PpIFN VT  0.6V I LEAKAGE(1) CHOLD = 10 pF VSS/VREF- 6V 5V RSS Legend: CHOLD = Sample/Hold Capacitance VDD4V 3V CPIN = Input Capacitance 2V I LEAKAGE = Leakage current at the pin due to various junctions 5 6 7 891011 RIC = Interconnect Resistance Sampling Switch RSS = Resistance of Sampling Switch (k) SS = Sampling Switch VT = Threshold Voltage Note 1: Refer to Section30.0 “Electrical Specifications”. FIGURE 16-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh 3FCh e od 3FBh C ut p ut O C D 03h A 02h 01h 00h Analog Input Voltage 0.5 LSB 1.5 LSB Zero-Scale VREF- Transition Full-Scale Transition VREF+ DS41391D-page 150  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 145 ADCON1 ADFM ADCS2 ADCS1 ADCS0 — ADNREF ADPREF1 ADPREF0 146 ADRESH A/D Result Register High 147, 148 ADRESL A/D Result Register Low 147, 148 ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 123 ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — 123 CCPxCON PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 226 INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 91 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 123 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 123 FVRCON FVREN FVRRDY Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 136 DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — DACNSS 156 DACCON1 — — — DACR4 DACR3 DACR2 DACR1 DACR0 156 Legend: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.  2011 Microchip Technology Inc. DS41391D-page 151

PIC16(L)F1826/27 NOTES: DS41391D-page 152  2011 Microchip Technology Inc.

PIC16(L)F1826/27 17.0 DIGITAL-TO-ANALOG 17.1 Output Voltage Selection CONVERTER (DAC) MODULE The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 The Digital-to-Analog Converter supplies a variable register. voltage reference, ratiometric with the input source, with 32 selectable output levels. The DAC output voltage is determined by the equations in Equation17-1. The input of the DAC can be connected to: • External VREF pins • VDD supply voltage • FVR (Fixed Voltage Reference) The output of the DAC can be configured to supply a reference voltage to the following: • Comparator positive input • ADC input channel • DACOUT pin • Capacitive Sensing module (CSM) The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register. EQUATION 17-1: DAC OUTPUT VOLTAGE IF DACEN = 1  DACR4:0 VOUT = VSOURCE+–VSOURCE------------------------------ +VSOURCE-  5  2 IF DACEN = 0 and DACLPS = 1 and DACR[4:0] = 11111 VOUT = VSOURCE+ IF DACEN = 0 and DACLPS = 0 and DACR[4:0] = 00000 VOUT = VSOURCE– VSOURCE+ = VDD, VREF, or FVR BUFFER 2 VSOURCE- = VSS 17.2 Ratiometric Output Level 17.3 DAC Voltage Reference Output The DAC output value is derived using a resistor ladder The DAC can be output to the DACOUT pin by setting with each end of the ladder tied to a positive and the DACOE bit of the DACCON0 register to ‘1’. negative voltage reference input source. If the voltage Selecting the DAC reference voltage for output on the of either input source fluctuates, a similar fluctuation will DACOUT pin automatically overrides the digital output result in the DAC output value. buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been The value of the individual resistors within the ladder configured for DAC reference voltage output will can be found in Section29.0 “Electrical always return a ‘0’. Specifications”. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to DACOUT. Figure17-2 shows an example buffering technique.  2011 Microchip Technology Inc. DS41391D-page 153

PIC16(L)F1826/27 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSOURCE+ VDD DACR<4:0> 5 VREF+ R R DACPSS<1:0> 2 R DACEN DACLPS R R X 32 U Steps 1 M DAC o- (To Comparator and 2-t ADC Modules) R 3 R DACOUT R DACOE DACNSS VREF- VSOURCE- VSS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC R Module + Voltage DACOUT – Buffered DAC Output Reference Output Impedance DS41391D-page 154  2011 Microchip Technology Inc.

PIC16(L)F1826/27 17.4 Low-Power Voltage State This is also the method used to output the voltage level from the FVR to an output pin. See Section17.5 In order for the DAC module to consume the least “Operation During Sleep” for more information. amount of power, one of the two voltage reference input Reference Figure17-3 for output clamping examples. sources to the resistor ladder must be disconnected. Either the positive voltage source, (VSOURCE+), or the 17.4.2 OUTPUT CLAMPED TO NEGATIVE negative voltage source, (VSOURCE-) can be disabled. VOLTAGE SOURCE The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the The DAC output voltage can be set to VSOURCE- with the least amount of power consumption by performing DACLPS bit in the DACCON0 register disables the the following: positive voltage source. • Clearing the DACEN bit in the DACCON0 register. 17.4.1 OUTPUT CLAMPED TO POSITIVE • Clearing the DACLPS bit in the DACCON0 register. VOLTAGE SOURCE • Configuring the DACNSS bits to the proper The DAC output voltage can be set to VSOURCE+ with negative source. the least amount of power consumption by performing • Configuring the DACR<4:0> bits to ‘00000’ in the the following: DACCON1 register. • Clearing the DACEN bit in the DACCON0 register. This allows the comparator to detect a zero-crossing • Setting the DACLPS bit in the DACCON0 register. while not consuming additional current through the DAC • Configuring the DACPSS bits to the proper module. positive source. Reference Figure17-3 for output clamping examples. • Configuring the DACR<4:0> bits to ‘11111’ in the DACCON1 register. FIGURE 17-3: OUTPUT VOLTAGE CLAMPING EXAMPLES Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source VSOURCE+ VSOURCE+ R R DACR<4:0> = 11111 R R DACEN = 0 DACEN = 0 DACLPS = 1 DAC Voltage Ladder DACLPS = 0 DAC Voltage Ladder (see Figure17-1) (see Figure17-1) R R DACR<4:0> = 00000 VSOURCE- VSOURCE- 17.5 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 17.6 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared.  2011 Microchip Technology Inc. DS41391D-page 155

PIC16(L)F1826/27 17.7 DAC Control Registers REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 DACLPS: DAC Low-Power Voltage State Select bit 1 = DAC Positive reference source selected 0 = DAC Negative reference source selected bit 5 DACOE: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin bit 4 Unimplemented: Read as ‘0’ bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits 00 = VDD 01 = VREF+ pin 10 = FVR Buffer2 output 11 = Reserved, do not use bit 1 Unimplemented: Read as ‘0’ bit 0 DACNSS: DAC Negative Source Select bits 1 = VREF- 0 = VSS REGISTER 17-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — DACR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR<4:0>: DAC Voltage Output Select bits TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 138 DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — DACNSS 156 DACCON1 — — — DACR4 DACR3 DACR2 DACR1 DACR0 156 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused with the DAC module. DS41391D-page 156  2011 Microchip Technology Inc.

PIC16(L)F1826/27 18.0 SR LATCH 18.2 Latch Output The module consists of a single SR Latch with multiple The SRQEN and SRNQEN bits of the SRCON0 regis- Set and Reset inputs as well as separate latch outputs. ter control the Q and Q latch outputs. Both of the SR The SR Latch module includes the following features: Latch outputs may be directly output to an I/O pin at the same time. • Programmable input selection • SR Latch output is available externally The applicable TRIS bit of the corresponding port must be cleared to enable the port pin output driver. • Separate Q and Q outputs • Firmware Set and Reset 18.3 Effects of a Reset The SR Latch can be used in a variety of analog appli- cations, including oscillator circuits, one-shot circuit, Upon any device Reset, the SR Latch output is not ini- hysteretic controllers, and analog timing applications. tialized to a known state. The user’s firmware is responsible for initializing the latch output before 18.1 Latch Operation enabling the output pins. The latch is a Set-Reset Latch that does not depend on a clock source. Each of the Set and Reset inputs are active-high. The latch can be Set or Reset by: • Software control (SRPS and SRPR bits) • Comparator C1 output (SYNCC1OUT) • Comparator C2 output (SYNCC2OUT) • SRI pin • Programmable clock (SRCLK) The SRPS and the SRPR bits of the SRCON0 register may be used to set or reset the SR Latch, respectively. The latch is Reset-dominant. Therefore, if both Set and Reset inputs are high, the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset oper- ation. The output from Comparator C1 or C2 can be used as the Set or Reset inputs of the SR Latch. The output of either comparator can be synchronized to the Timer1 clock source. See Section19.0 “Comparator Mod- ule” and Section21.0 “Timer1 Module with Gate Control” for more information. An external source on the SRI pin can be used as the Set or Reset inputs of the SR Latch. An internal clock source is available that can periodically set or reset the SR Latch. The SRCLK<2:0> bits in the SRCON0 register are used to select the clock source period. The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to set or reset the SR Latch, respectively. Note: Enabling both the Set and Reset inputs from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured.  2011 Microchip Technology Inc. DS41391D-page 157

PIC16(L)F1826/27 FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRLEN SRPS Pulse SRQEN Gen(2) SRI SRSPE S Q SRCLK SRQ SRSCKE SYNCC2OUT(3) SRSC2E SYNCC1OUT(3) SR SRSC1E Latch(1) SRPR Pulse Gen(2) SRI SRRPE R Q SRCLK SRNQ SRRCKE SRLEN SYNCC2OUT(3) SRNQEN SRRC2E SYNCC1OUT(3) SRRC1E Note 1: If R=1 and S=1 simultaneously, Q=0, Q=1 2: Pulse generator causes a 1 Q-state pulse width. 3: Name denotes the connection point at the comparator output. DS41391D-page 158  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 18-1: SRCLK FREQUENCY TABLE SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 62.5kHz 39.0kHz 31.3kHz 7.81kHz 1.95kHz 110 256 125kHz 78.1kHz 62.5kHz 15.6kHz 3.90kHz 101 128 250kHz 156kHz 125kHz 31.25kHz 7.81kHz 100 64 500kHz 313kHz 250kHz 62.5kHz 15.6kHz 011 32 1MHz 625kHz 500kHz 125kHz 31.3 kHz 010 16 2MHz 1.25MHz 1MHz 250kHz 62.5kHz 001 8 4MHz 2.5MHz 2MHz 500kHz 125kHz 000 4 8MHz 5MHz 4MHz 1MHz 250kHz REGISTER 18-1: SRCON0: SR LATCH CONTROL 0 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/S-0/0 R/S-0/0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared S = Bit is set only bit 7 SRLEN: SR Latch Enable bit 1 = SR Latch is enabled 0 = SR Latch is disabled bit 6-4 SRCLK<2:0>: SR Latch Clock Divider bits 000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock 001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock 010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock 011 = Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock 100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock 101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock 110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock 111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock bit 3 SRQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRQ pin 0 = External Q output is disabled If SRLEN = 0: SR Latch is disabled bit 2 SRNQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRnQ pin 0 = External Q output is disabled If SRLEN = 0: SR Latch is disabled bit 1 SRPS: Pulse Set Input of the SR Latch bit(1) 1 = Pulse set input for 1 Q-clock period 0 = No effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit(1) 1 = Pulse reset input for 1 Q-clock period 0 = No effect on reset input. Note 1: Set only, always reads back ‘0’.  2011 Microchip Technology Inc. DS41391D-page 159

PIC16(L)F1826/27 REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SR Latch is set when the SRI pin is high. 0 = SRI pin has no effect on the set input of the SR Latch bit 6 SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR Latch is pulsed with SRCLK 0 = SRCLK has no effect on the set input of the SR Latch bit 5 SRSC2E: SR Latch C2 Set Enable bit 1 = SR Latch is set when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the set input of the SR Latch bit 4 SRSC1E: SR Latch C1 Set Enable bit 1 = SR Latch is set when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the set input of the SR Latch bit 3 SRRPE: SR Latch Peripheral Reset Enable bit 1 = SR Latch is reset when the SRI pin is high. 0 = SRI pin has no effect on the reset input of the SR Latch bit 2 SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR Latch is pulsed with SRCLK 0 = SRCLK has no effect on the reset input of the SR Latch bit 1 SRRC2E: SR Latch C2 Reset Enable bit 1 = SR Latch is reset when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the reset input of the SR Latch bit 0 SRRC1E: SR Latch C1 Reset Enable bit 1 = SR Latch is reset when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the reset input of the SR Latch DS41391D-page 160  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 123 SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 159 SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 160 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR latch module.  2011 Microchip Technology Inc. DS41391D-page 161

PIC16(L)F1826/27 NOTES: DS41391D-page 162  2011 Microchip Technology Inc.

PIC16(L)F1826/27 19.0 COMPARATOR MODULE FIGURE 19-1: SINGLE COMPARATOR Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and VIN+ + providing a digital indication of their relative magnitudes. Output Comparators are very useful mixed signal building VIN- – blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: • Independent comparator control VIN- • Programmable input selection VIN+ • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change Output • Wake-up from Sleep • Programmable Speed/Power optimization • PWM shutdown Note: The black areas of the output of the • Programmable and fixed voltage reference comparator represents the uncertainty 19.1 Comparator Overview due to input offsets and response time. A single comparator is shown in Figure19-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level.  2011 Microchip Technology Inc. DS41391D-page 163

PIC16(L)F1826/27 FIGURE 19-2: COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<1:0> CxON(1) 2 Interrupt CxINTP det C12IN0- 0 Set CxIF C12IN1- 1 MUX Interrupt CxINTN C12IN2- 2 (2) det CXPOL C12IN3- 3 CxVN - Cx(3) D Q CMXCOXUOTUT To Data Bus + CxVP Q1 EN C1IN+ 0 MUX CxHYS DAC 1 (2) CxSP To ECCP PWM Logic FVR Buffer2 2 C12IN+ 3 CXSYNC CxON CXOE TRIS bit CXPCH<1:0> 0 CXOUT 2 D Q 1 (from Timer1) T1CLK To Timer1 or SR Latch SYNCCXOUT Note 1: When CxON = 0, the Comparator will produce a ‘0’ at the output 2: When CxON = 0, all multiplexer inputs are disconnected. 3: Output of comparator can be frozen during debugging. DS41391D-page 164  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 19-3: COMPARATOR 2 MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<1:0> CxON(1) 2 Interrupt CxINTP det C12IN0- 0 Set CxIF C12IN1- 1 MUX Interrupt CxINTN C12IN2- 2 (2) det CXPOL C12IN3- 3 CxVN - Cx(3) D Q CMXCOXUOTUT To Data Bus + CxVP Q1 EN C12IN+ 0 MUX CxHYS DAC 1 (2) CxSP To ECCP PWM Logic FVR Buffer2 2 3 CXSYNC VSS CxON CXOE TRIS bit CXPCH<1:0> 0 CXOUT 2 D Q 1 (from Timer1) T1CLK To Timer1 or SR Latch SYNCCXOUT Note 1: When CxON = 0, the Comparator will produce a ‘0’ at the output 2: When CxON = 0, all multiplexer inputs are disconnected. 3: Output of comparator can be frozen during debugging.  2011 Microchip Technology Inc. DS41391D-page 165

PIC16(L)F1826/27 19.2 Comparator Control 19.2.3 COMPARATOR OUTPUT POLARITY Each comparator has 2 control registers: CMxCON0 and Inverting the output of the comparator is functionally CMxCON1. equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by The CMxCON0 registers (see Register19-1) contain setting the CxPOL bit of the CMxCON0 register. Control and Status bits for the following: Clearing the CxPOL bit results in a non-inverted output. • Enable Table19-1 shows the output state versus input • Output selection conditions, including polarity control. • Output polarity TABLE 19-1: COMPARATOR OUTPUT • Speed/Power selection STATE VS. INPUT • Hysteresis enable CONDITIONS • Output synchronization Input Condition CxPOL CxOUT The CMxCON1 registers (see Register19-2) contain CxVN > CxVP 0 0 Control bits for the following: CxVN < CxVP 0 1 • Interrupt enable CxVN > CxVP 1 1 • Interrupt edge polarity CxVN < CxVP 1 0 • Positive input channel selection • Negative input channel selection 19.2.4 COMPARATOR SPEED/POWER SELECTION 19.2.1 COMPARATOR ENABLE The trade-off between speed or power can be opti- Setting the CxON bit of the CMxCON0 register enables mized during program execution with the CxSP control the comparator for operation. Clearing the CxON bit bit. The default state for this bit is ‘1’ which selects the disables the comparator resulting in minimum current normal speed mode. Device power consumption can consumption. be optimized at the cost of slower comparator propaga- 19.2.2 COMPARATOR OUTPUT tion delay by clearing the CxSP bit to ‘0’. SELECTION The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set Note1: The CxOE bit of the CMxCON0 register overrides the PORT data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. DS41391D-page 166  2011 Microchip Technology Inc.

PIC16(L)F1826/27 19.3 Comparator Hysteresis 19.5 Comparator Interrupt A selectable amount of separation voltage can be An interrupt can be generated upon a change in the added to the input pins of each comparator to provide a output value of the comparator for each comparator, a hysteresis function to the overall operation. Hysteresis rising edge detector and a Falling edge detector are is enabled by setting the CxHYS bit of the CMxCON0 present. register. When either edge detector is triggered and its associ- See Section29.0 “Electrical Specifications” for ated enable bit is set (CxINTP and/or CxINTN bits of more information. the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. 19.4 Timer1 Gate Operation To enable the interrupt, you must set the following bits: The output resulting from a comparator operation can • CxON, CxPOL and CxSP bits of the CMxCON0 be used as a source for gate control of Timer1. See register Section21.6 “Timer1 Gate” for more information. • CxIE bit of the PIE2 register This feature is useful for timing the duration or interval • CxINTP bit of the CMxCON1 register (for a rising of an analog event. edge detection) It is recommended that the comparator output be syn- • CxINTN bit of the CMxCON1 register (for a falling chronized to Timer1. This ensures that Timer1 does not edge detection) increment while a change in the comparator is occur- • PEIE and GIE bits of the INTCON register ring. The associated interrupt flag bit, CxIF bit of the PIR2 19.4.1 COMPARATOR OUTPUT register, must be cleared in software. If another edge is SYNCHRONIZATION detected while this flag is being cleared, the flag will still be set at the end of the sequence. The output from either comparator, C1 or C2, can be synchronized with Timer1 by setting the CxSYNC bit of Note: Although a comparator is disabled, an the CMxCON0 register. interrupt can be generated by changing the output polarity with the CxPOL bit of Once enabled, the comparator output is latched on the the CMxCON0 register, or by switching falling edge of the Timer1 source clock. If a prescaler is the comparator on or off with the CxON bit used with Timer1, the comparator output is latched after of the CMxCON0 register. the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the 19.6 Comparator Positive Input Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Selection Block Diagrams (Figure19-2 and Figure19-3) and the Configuring the CxPCH<1:0> bits of the CMxCON1 Timer1 Block Diagram (Figure21-1) for more register directs an internal voltage reference or an information. analog pin to the non-inverting input of the comparator: • C1IN+ or C2IN+ analog pin • DAC • FVR (Fixed Voltage Reference) • VSS (Ground) See Section14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section17.0 “Digital-to-Analog Converter (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled.  2011 Microchip Technology Inc. DS41391D-page 167

PIC16(L)F1826/27 19.7 Comparator Negative Input 19.10 Analog Input Connection Selection Considerations The CxNCH<1:0> bits of the CMxCON0 register direct A simplified circuit for an analog input is shown in one of four analog pins to the comparator inverting Figure19-4. Since the analog input pins share their input. connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The Note: To use CxIN+ and CxINx- pins as analog analog input, therefore, must be between VSS and VDD. input, the appropriate bits must be set in If the input voltage deviates from this range by more the ANSEL register and the correspond- than 0.6V in either direction, one of the diodes is for- ing TRIS bits must also be set to disable ward biased and a latch-up may occur. the output drivers. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component 19.8 Comparator Response Time connected to an analog input pin, such as a capacitor or The comparator output is indeterminate for a period of a Zener diode, should have very little leakage current to time after the change of an input source or the selection minimize inaccuracies introduced. of a new reference voltage. This period is referred to as the response time. The response time of the comparator Note1: When reading a PORT register, all pins differs from the settling time of the voltage reference. configured as analog inputs will read as a Therefore, both of these times must be considered when ‘0’. Pins configured as digital inputs will determining the total response time to a comparator convert as an analog input, according to input change. See the Comparator and Voltage Refer- the input specification. ence Specifications in Section29.0 “Electrical Specifi- cations” for more details. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to 19.9 Interaction with ECCP Logic consume more current than is specified. The C1 and C2 comparators can be used as general purpose comparators. Their outputs can be brought out to the C1OUT and C2OUT pins. When the ECCP Auto-Shutdown is active it can use one or both comparator signals. If auto-restart is also enabled, the comparators can be configured as a closed loop analog feedback to the ECCP, thereby, creating an analog controlled PWM. Note: When the comparator module is first initialized the output state is unknown. Upon initialization, the user should verify the output state of the comparator prior to relying on the result, primarily when using the result in connection with other peripheral features, such as the ECCP Auto-Shutdown mode. DS41391D-page 168  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 19-4: ANALOG INPUT MODEL VDD Analog Input Rs < 10K pin VT  0.6V RIC To Comparator VA C5 PpIFN VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage Note 1: See Section29.0 “Electrical Specifications”  2011 Microchip Technology Inc. DS41391D-page 169

PIC16(L)F1826/27 REGISTER 19-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled and consumes no active power 0 = Comparator is disabled bit 6 CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous. DS41391D-page 170  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 19-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 CxINTP CxINTN CxPCH<1:0> — — CxNCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits 00 = CxVP connects to CxIN+ pin 01 = CxVP connects to DAC Voltage Reference 10 = CxVP connects to FVR Voltage Reference For C1: 11 = CxVP connects to C12IN+ pin For C2: 11 = CxVP connects to VSS bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CxNCH<1:0>: Comparator Negative Input Channel Select bits 00 = CxVN connects to C12IN0- pin 01 = CxVN connects to C12IN1- pin 10 = CxVN connects to C12IN2- pin 11 = CxVN connects to C12IN3- pin REGISTER 19-3: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0 — — — — — — MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit  2011 Microchip Technology Inc. DS41391D-page 171

PIC16(L)F1826/27 TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 123 CMxCON0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC 170 CMxCON1 CxNTP CxINTN CxPCH1 CxPCH0 — — CxNCH1 CxNCH0 171 CMOUT — — — — — — MC2OUT MC1OUT 171 DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — DACNSS 156 DACCON1 — — — DACR4 DACR3 DACR2 DACR1 DACR0 156 FVRCON FVREN FVRRDY Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 136 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 LATA LATA7 LATA6 — LATA4 LATA3 LATA2 LATA1 LATA0 122 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE(1) 88 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF(1) 92 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 122 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: PIC16(L)F1827 only. DS41391D-page 172  2011 Microchip Technology Inc.

PIC16(L)F1826/27 20.0 TIMER0 MODULE 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment The Timer0 module is an 8-bit timer/counter with the on every rising or falling edge of the T0CKI pin or the following features: Capacitive Sensing Oscillator (CPSCLK) signal. • 8-bit timer/counter register (TMR0) 8-Bit Counter mode using the T0CKI pin is selected by • 8-bit prescaler (independent of Watchdog Timer) setting the TMR0CS bit in the OPTION_REG register to • Programmable internal or external clock source ‘1’ and resetting the T0XCS bit in the CPSCON0 register • Programmable external clock edge selection to ‘0’. • Interrupt on overflow 8-Bit Counter mode using the Capacitive Sensing • TMR0 can be used to gate Timer1 Oscillator (CPSCLK) signal is selected by setting the Figure20-1 is a block diagram of the Timer0 module. TMR0CS bit in the OPTION_REG register to ‘1’ and setting the T0XCS bit in the CPSCON0 register to ‘1’. 20.1 Timer0 Operation The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit The Timer0 module can be used as either an 8-bit timer in the OPTION_REG register. or an 8-bit counter. 20.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 20-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 Sync 0 1 2 TCY TMR0 0 From CPSCLK 1 TMR0SE TMR0CS 8-bit Set Flag bit TMR0IF on Overflow Prescaler PSA T0XCS Overflow to Timer1 8 PS<2:0>  2011 Microchip Technology Inc. DS41391D-page 173

PIC16(L)F1826/27 FIGURE 20-2: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 Sync 1 2 TCY TMR0 0 TMR0SE TMR0CS 8-bit Set Flag bit TMR0IF on Overflow Prescaler PSA Overflow to Timer1 8 PS<2:0> DS41391D-page 174  2011 Microchip Technology Inc.

PIC16(L)F1826/27 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by set- ting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 20.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 20.1.5 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section29.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode.  2011 Microchip Technology Inc. DS41391D-page 175

PIC16(L)F1826/27 20.2 Option and Timer0 Control Register REGISTER 20-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate 000 1 : 2 001 1 : 4 010 1 : 8 011 1 : 16 100 1 : 32 101 1 : 64 110 1 : 128 111 1 : 256 TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CPSCON0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 318 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 177 TMR0 Timer0 Module Register 173* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. DS41391D-page 176  2011 Microchip Technology Inc.

PIC16(L)F1826/27 21.0 TIMER1 MODULE WITH GATE • Gate Toggle mode CONTROL • Gate Single-pulse mode • Gate Value Status The Timer1 module is a 16-bit timer/counter with the • Gate Event Interrupt following features: Figure21-1 is a block diagram of the Timer1 module. • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 2-bit prescaler • Dedicated 32 kHz oscillator circuit • Optionally synchronized comparator out • Multiple Timer1 gate (count enable) sources • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with CCP/ECCP) • Selectable Gate Source Polarity FIGURE 21-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 T1GSPM FrOomve Trfilmower0 01 T1G_IN 0 0 T1GVAL D Q Data Bus SCYomNCpaCr1aOtoUr T1 10 SAicnqg.l eC Ponutlrsoel 1 Q1 EN T1GRCDON D Q 1 SCYomNCpaCr2aOtoUr T2 11 CK Q T1GGO/DONE Interrupt Set TMR1ON R det TMR1GIF T1GPOL T1GTM TMR1GE Set flag bit TMR1ON TMR1IF on To Comparator Module Overflow TMR1(2) EN Synchronized TMR1H TMR1L T1CLK 0 clock input Q D 1 TMR1CS<1:0> T1SYNC T1OSO OUT Cap. Sensing T1OSC Oscillator 11 Prescaler Synchronize(3) 1 1, 2, 4, 8 det T1OSI EN 10 2 0 FOSC T1CKPS<1:0> Internal 01 T1OSCEN Clock IFnOteSrCn/a2l Sleep input FOSC/4 Clock Internal 00 (1) Clock T1CKI To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2011 Microchip Technology Inc. DS41391D-page 177

PIC16(L)F1826/27 21.1 Timer1 Operation 21.2 Clock Source Selection The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> and T1OSCEN bits of the T1CON which is accessed through the TMR1H:TMR1L register register are used to select the clock source for Timer1. pair. Writes to TMR1H or TMR1L directly update the Table21-2 displays the clock source selections. counter. 21.2.1 INTERNAL CLOCK SOURCE When used with an internal clock source, the module is a timer and increments on every instruction cycle. When the internal clock source is selected the When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples can be used as either a timer or counter and incre- of FOSC as determined by the Timer1 prescaler. ments on every selected edge of the external source. When the FOSC internal clock source is selected, the Timer1 is enabled by configuring the TMR1ON and Timer1 register value will increment by four counts every TMR1GE bits in the T1CON and T1GCON registers, instruction clock cycle. Due to this condition, a 2LSB respectively. Table21-1 displays the Timer1 enable error in resolution will occur when reading the Timer1 selections. value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. TABLE 21-1: TIMER1 ENABLE The following asynchronous sources may be used: SELECTIONS • Asynchronous event on the T1G pin to Timer1 Timer1 TMR1ON TMR1GE gate Operation • C1 or C2 comparator input to Timer1 gate 0 0 Off 21.2.2 EXTERNAL CLOCK SOURCE 0 1 Off 1 0 Always On When the external clock source is selected, the Timer1 module may work as a timer or a counter. 1 1 Count Enabled When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external 32.768kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • Timer1 enabled after POR • Write to TMR1H or TMR1L • Timer1 is disabled • Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. TABLE 21-2: CLOCK SOURCE SELECTIONS TMR1CS1 TMR1CS0 T1OSCEN Clock Source 0 0 x Instruction Clock (FOSC/4) 0 1 x System Clock (FOSC) 1 0 0 External Clocking on T1CKI Pin 1 0 0 External Clocking on T1CKI Pin 1 1 x Capacitive Sensing Oscillator DS41391D-page 178  2011 Microchip Technology Inc.

PIC16(L)F1826/27 21.3 Timer1 Prescaler 21.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER Timer1 has four prescaler options allowing 1, 2, 4 or 8 MODE divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The Reading TMR1H or TMR1L while the timer is running prescale counter is not directly readable or writable; from an external asynchronous clock will ensure a valid however, the prescaler counter is cleared upon a write to read (taken care of in hardware). However, the user TMR1H or TMR1L. should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the 21.4 Timer1 Oscillator timer may overflow between the reads. For writes, it is recommended that the user simply stop A dedicated low-power 32.768kHz oscillator circuit is the timer and write the desired values. A write built-in between pins T1OSI (input) and T1OSO contention may occur by writing to the timer registers, (amplifier output). This internal circuit is to be used in while the register is incrementing. This may produce an conjunction with an external 32.768kHz crystal. unpredictable value in the TMR1H:TMR1L register pair. The oscillator circuit is enabled by setting the T1OSCEN bit of the T1CON register. The oscillator will 21.6 Timer1 Gate continue to run during Sleep. Timer1 can be configured to count freely or the count Note: The oscillator requires a start-up and can be enabled and disabled using Timer1 gate stabilization time before use. Thus, circuitry. This is also referred to as Timer1 gate enable. T1OSCEN should be set and a suitable Timer1 gate can also be driven by multiple selectable delay observed prior to using Timer1. A sources. suitable delay similar to the OST delay can be implemented in software by 21.6.1 TIMER1 GATE ENABLE clearing the TMR1IF bit then presetting the TMR1H:TMR1L register pair to The Timer1 Gate Enable mode is enabled by setting FC00h. The TMR1IF flag will be set when the TMR1GE bit of the T1GCON register. The polarity 1024 clock cycles have elapsed, thereby of the Timer1 Gate Enable mode is configured using indicating that the oscillator is running and the T1GPOL bit of the T1GCON register. reasonably stable. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock 21.5 Timer1 Operation in source. When Timer1 Gate Enable mode is disabled, Asynchronous Counter Mode no incrementing will occur and Timer1 will hold the current count. See Figure21-3 for timing details. If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer TABLE 21-3: TIMER1 GATE ENABLE increments asynchronously to the internal phase clocks. If the external clock source is selected then the SELECTIONS timer will continue to run during Sleep and can T1CLK T1GPOL T1G Timer1 Operation generate an interrupt on overflow, which will wake-up the processor. However, special precautions in  0 0 Counts software are needed to read/write the timer (see  0 1 Holds Count Section21.5.1 “Reading and Writing Timer1 in  1 0 Holds Count Asynchronous Counter Mode”).  1 1 Counts Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.  2011 Microchip Technology Inc. DS41391D-page 179

PIC16(L)F1826/27 21.6.2 TIMER1 GATE SOURCE 21.6.3 TIMER1 GATE TOGGLE MODE SELECTION When Timer1 Gate Toggle mode is enabled, it is possi- The Timer1 gate source can be selected from one of ble to measure the full-cycle length of a Timer1 gate four different sources. Source selection is controlled by signal, as opposed to the duration of a single level the T1GSS bits of the T1GCON register. The polarity pulse. for each available source is also selectable. Polarity The Timer1 gate source is routed through a flip-flop that selection is controlled by the T1GPOL bit of the changes state on every incrementing edge of the T1GCON register. signal. See Figure21-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the TABLE 21-4: TIMER1 GATE SOURCES T1GTM bit of the T1GCON register. When the T1GTM T1GSS Timer1 Gate Source bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is 00 Timer1 Gate Pin measured. 01 Overflow of Timer0 (TMR0 increments from FFh to 00h) Note: Enabling Toggle mode at the same time as changing the gate polarity may result in 10 Comparator 1 Output SYNCC1OUT indeterminate operation. (optionally Timer1 synchronized output) 11 Comparator 2 Output SYNCC2OUT 21.6.4 TIMER1 GATE SINGLE-PULSE (optionally Timer1 synchronized output) MODE 21.6.2.1 T1G Pin Gate Operation When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 The T1G pin is one source for Timer1 gate control. It Gate Single-Pulse mode is first enabled by setting the can be used to supply an external source to the Timer1 T1GSPM bit in the T1GCON register. Next, the gate circuitry. T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing 21.6.2.2 Timer0 Overflow Gate Operation edge. On the next trailing edge of the pulse, the When Timer0 increments from FFh to 00h, a T1GGO/DONE bit will automatically be cleared. No other low-to-high pulse will automatically be generated and gate events will be allowed to increment Timer1 until the internally supplied to the Timer1 gate circuitry. T1GGO/DONE bit is once again set in software. See Figure21-5 for timing details. 21.6.2.3 Comparator C1 Gate Operation If the Single Pulse Gate mode is disabled by clearing the The output resulting from a Comparator 1 operation can T1GSPM bit in the T1GCON register, the T1GGO/DONE be selected as a source for Timer1 gate control. The bit should also be cleared. Comparator 1 output (SYNCC1OUT) can be Enabling the Toggle mode and the Single-Pulse mode synchronized to the Timer1 clock or left asynchronous. simultaneously will permit both sections to work For more information see Section19.4.1 “Comparator together. This allows the cycle times on the Timer1 gate Output Synchronization”. source to be measured. See Figure21-6 for timing 21.6.2.4 Comparator C2 Gate Operation details. The output resulting from a Comparator 2 operation 21.6.5 TIMER1 GATE VALUE STATUS can be selected as a source for Timer1 gate control. When Timer1 Gate Value Status is utilized, it is possible The Comparator 2 output (SYNCC2OUT) can be to read the most current level of the gate control value. synchronized to the Timer1 clock or left asynchronous. The value is stored in the T1GVAL bit in the T1GCON For more information see Section19.4.1 “Comparator register. The T1GVAL bit is valid even when the Timer1 Output Synchronization”. gate is not enabled (TMR1GE bit is cleared). 21.6.6 TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is pos- sible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). DS41391D-page 180  2011 Microchip Technology Inc.

PIC16(L)F1826/27 21.7 Timer1 Interrupt 21.9 ECCP/CCP Capture/Compare Time Base The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls The CCP modules use the TMR1H:TMR1L register over, the Timer1 interrupt flag bit of the PIR1 register is pair as the time base when operating in Capture or set. To enable the interrupt on rollover, you must set Compare mode. these bits: In Capture mode, the value in the TMR1H:TMR1L • TMR1ON bit of the T1CON register register pair is copied into the CCPR1H:CCPR1L • TMR1IE bit of the PIE1 register register pair on a configured event. • PEIE bit of the INTCON register In Compare mode, an event is triggered when the value • GIE bit of the INTCON register CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a The interrupt is cleared by clearing the TMR1IF bit in Special Event Trigger. the Interrupt Service Routine. For more information, see Section24.0 Note: The TMR1H:TMR1L register pair and the “Capture/Compare/PWM Modules”. TMR1IF bit should be cleared before enabling interrupts. 21.10 ECCP/CCP Special Event Trigger 21.8 Timer1 Operation During Sleep When any of the CCP’s are configured to trigger a spe- cial event, the trigger will clear the TMR1H:TMR1L reg- Timer1 can only operate during Sleep when setup in ister pair. This special event does not cause a Timer1 Asynchronous Counter mode. In this mode, an external interrupt. The CCP module may still be configured to crystal or clock source can be used to increment the generate a CCP interrupt. counter. To set up the timer to wake the device: In this mode of operation, the CCPR1H:CCPR1L • TMR1ON bit of the T1CON register must be set register pair becomes the period register for Timer1. • TMR1IE bit of the PIE1 register must be set Timer1 should be synchronized and FOSC/4 should be • PEIE bit of the INTCON register must be set selected as the clock source in order to utilize the Spe- • T1SYNC bit of the T1CON register must be set cial Event Trigger. Asynchronous operation of Timer1 • TMR1CS bits of the T1CON register must be can cause a Special Event Trigger to be missed. configured In the event that a write to TMR1H or TMR1L coincides • T1OSCEN bit of the T1CON register must be with a Special Event Trigger from the CCP, the write will configured take precedence. The device will wake-up on an overflow and execute For more information, see Section16.2.5 “Special the next instructions. If the GIE bit of the INTCON Event Trigger”. register is set, the device will call the Interrupt Service Routine. Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 21-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2011 Microchip Technology Inc. DS41391D-page 181

PIC16(L)F1826/27 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 DS41391D-page 182  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 Cleared by TMR1GIF Cleared by software Set by hardware on software falling edge of T1GVAL  2011 Microchip Technology Inc. DS41391D-page 183

PIC16(L)F1826/27 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 Set by hardware on Cleared by TMR1GIF Cleared by software falling edge of T1GVAL software DS41391D-page 184  2011 Microchip Technology Inc.

PIC16(L)F1826/27 21.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register21-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 21-1: T1CON: TIMER1 CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 =Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC) 10 =Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 =Timer1 clock source is system clock (FOSC) 00 =Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS<1:0> = 1X: 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMR1CS<1:0> = 0X: This bit is ignored. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop  2011 Microchip Technology Inc. DS41391D-page 185

PIC16(L)F1826/27 21.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register21-2, is used to control Timer1 gate. REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> DONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 gate pin 01 = Timer0 overflow output 10 = Comparator 1 optionally synchronized output (SYNCC1OUT) 11 = Comparator 2 optionally synchronized output (SYNCC2OUT) DS41391D-page 186  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 21-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — 128 CCP1CON PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 226 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 91 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 127 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 177* TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 177* TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 185 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 186 DONE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information.  2011 Microchip Technology Inc. DS41391D-page 187

PIC16(L)F1826/27 NOTES: DS41391D-page 188  2011 Microchip Technology Inc.

PIC16(L)F1826/27 22.0 TIMER2/4/6 MODULES There are up to three identical Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also Timer2/4/6). Note: The ‘x’ variable used in this section is used to designate Timer2, Timer4, or Timer6. For example, TxCON references T2CON, T4CON, or T6CON. PRx refer- ences PR2, PR4, or PR6. The Timer2/4/6 modules incorporate the following features: • 8-bit Timer and Period registers (TMRx and PRx, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMRx match with PRx, respectively • Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure22-1 for a block diagram of Timer2/4/6. FIGURE 22-1: TIMER2/4/6 BLOCK DIAGRAM Prescaler Reset FOSC/4 TMRx TMRx Output 1:1, 1:4, 1:16, 1:64 2 Comparator Postscaler Sets Flag bit TMRxIF EQ 1:1 to 1:16 TxCKPS<1:0> PRx 4 TxOUTPS<3:0>  2011 Microchip Technology Inc. DS41391D-page 189

PIC16(L)F1826/27 22.1 Timer2/4/6 Operation 22.3 Timer2/4/6 Output The clock input to the Timer2/4/6 modules is the The unscaled output of TMRx is available primarily to system instruction clock (FOSC/4). the CCP modules, where it is used as a time base for operations in PWM mode. TMRx increments from 00h on each clock edge. Timer2 can be optionally used as the shift clock source A 4-bit counter/prescaler on the clock input allows direct for the MSSPx modules operating in SPI mode. input, divide-by-4 and divide-by-16 prescale options. Additional information is provided in Section25.1 These options are selected by the prescaler control bits, “Master SSPx (MSSPx) Module Overview” TxCKPS<1:0> of the TxCON register. The value of Timer2/4/6 Operation During Sleep TMRx is compared to that of the Period register, PRx, on each clock cycle. When the two values match, the The Timer2/4/6 timers cannot be operated while the comparator generates a match signal as the timer processor is in Sleep mode. The contents of the TMRx output. This signal also resets the value of TMRx to 00h and PRx registers will remain unchanged while the on the next cycle and drives the output processor is in Sleep mode. counter/postscaler (see Section22.2 “Timer2/4/6 Interrupt”). The TMRx and PRx registers are both directly readable and writable. The TMRx register is cleared on any device Reset, whereas the PRx register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • a write to the TMRx register • a write to the TxCON register • Power-on Reset (POR) • Brown-out Reset (BOR) • MCLR Reset • Watchdog Timer (WDT) Reset • Stack Overflow Reset • Stack Underflow Reset • RESET Instruction Note: TMRx is not cleared when TxCON is written. 22.2 Timer2/4/6 Interrupt Timer2/4/6 can also generate an optional device interrupt. The Timer2/4/6 output signal (TMRx-to-PRx match) provides the input for the 4-bit counter/postscaler. This counter generates the TMRx match interrupt flag which is latched in TMRxIF of the PIRx register. The interrupt is enabled by setting the TMRx Match Interrupt Enable bit, TMRxIE of the PIEx register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, TxOUTPS<3:0>, of the TxCON register. DS41391D-page 190  2011 Microchip Technology Inc.

PIC16(L)F1826/27 22.4 Timer2 Control Register REGISTER 22-1: TXCON: TIMER2/TIMER4/TIMER6 CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — TxOUTPS<3:0> TMRxON TxCKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TxOUTPS<3:0>: Timerx Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler bit 2 TMRxON: Timerx On bit 1 = Timerx is on 0 = Timerx is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 =Prescaler is 1 01 =Prescaler is 4 10 =Prescaler is 16 11 =Prescaler is 64  2011 Microchip Technology Inc. DS41391D-page 191

PIC16(L)F1826/27 TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 91 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 92 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 96 PIE3(1) — — CCP4IE CCP3IE TMR6IE — TMR4IE — 94 PIR3(1) — — CCP4IF CCP3IF TMR6IF — TMR4IF — 98 PR2 Timer2 Module Period Register 189* PR4 Timer4 Module Period Register 189* PR6 Timer6 Module Period Register 189* T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 191 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 191 T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 191 TMR2 Holding Register for the 8-bit TMR2 Time Base 189* TMR4 Holding Register for the 8-bit TMR4 Time Base(1) 189* TMR6 Holding Register for the 8-bit TMR6 Time Base(1) 189* Legend: — = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information. Note 1: PIC16(L)F1827 only. DS41391D-page 192  2011 Microchip Technology Inc.

PIC16(L)F1826/27 23.0 DATA SIGNAL MODULATOR Using this method, the DSM can generate the following types of Key Modulation schemes: The Data Signal Modulator (DSM) is a peripheral which • Frequency-Shift Keying (FSK) allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a • Phase-Shift Keying (PSK) modulated output. • On-Off Keying (OOK) Both the carrier and the modulator signals are supplied Additionally, the following features are provided within to the DSM module either internally, from the output of the DSM module: a peripheral, or externally through an input pin. • Carrier Synchronization The modulated output signal is generated by perform- • Carrier Source Polarity Select ing a logical “AND” operation of both the carrier and • Carrier Source Pin Disable modulator signals and then provided to the MDOUT pin. • Programmable Modulator Data The carrier signal is comprised of two distinct and sep- • Modulator Source Pin Disable arate signals. A carrier high (CARH) signal and a car- • Modulated Output Polarity Select rier low (CARL) signal. During the time in which the • Slew Rate Control modulator (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator Figure23-1 shows a Simplified Block Diagram of the signal. When the modulator signal is in a logic low Data Signal Modulator peripheral. state, the DSM mixes the carrier low signal with the modulator signal. FIGURE 23-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR MDCH<3:0> MDEN VSS 0000 MDCIN1 0001 EN MDCIN2 0010 Data Signal CLKR 0011 Modulator CCP1 0100 CCP2 0101 CARH CCP3 0110 CCP4 0111 Reserved 1000 MDCHPOL No Channel * * Selected 1111 D SYNC MDMS<3:0> Q 1 MDBIT 0000 MDMIN 0001 CCP1 0010 CCP2 0011 0 CCP3 0100 CCP4 0101 Comparator C1 0110 MOD MDCHSYNC Comparator C2 0111 MSSP1 SDO1 1000 MDOUT MSSP2 SDO2 1001 EUSART 1010 MDOPOL MDOE Reserved 0011 No Channel * * Selected 1111 D MDCL<3:0> SYNC Q 1 VSS 0000 MDCIN1 0001 MDCIN2 0010 CLKR 0011 0 CCP1 0100 CCP2 0101 CARL MDCLSYNC CCP3 0110 CCP4 0111 1000 Reserved No Channel * MDCLPOL * Selected 1111  2011 Microchip Technology Inc. DS41391D-page 193

PIC16(L)F1826/27 23.1 DSM Operation 23.3 Carrier Signal Sources The DSM module can be enabled by setting the MDEN The carrier high signal and carrier low signal can be bit in the MDCON register. Clearing the MDEN bit in the supplied from the following sources: MDCON register, disables the DSM module by auto- • CCP1 Signal matically switching the carrier high and carrier low sig- • CCP2 Signal nals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON • CCP3 Signal register. This not only assures that the DSM module is • CCP4 Signal inactive, but that it is also consuming the least amount • Reference Clock Module Signal of current. • External Signal on MDCIN1 pin The values used to select the carrier high, carrier low, • External Signal on MDCIN2 pin and modulator sources held by the Modulation Source, • VSS Modulation High Carrier, and Modulation Low Carrier The carrier high signal is selected by configuring the control registers are not affected when the MDEN bit is MDCH <3:0> bits in the MDCARH register. The carrier cleared and the DSM module is disabled. The values low signal is selected by configuring the MDCL <3:0> inside these registers remain unchanged while the bits in the MDCARL register. DSM is inactive. The sources for the carrier high, car- rier low and modulator signals will once again be 23.4 Carrier Synchronization selected when the MDEN bit is set and the DSM mod- ule is again enabled and active. During the time when the DSM switches between car- The modulated output signal can be disabled without rier high and carrier low signal sources, the carrier data shutting down the DSM module. The DSM module will in the modulated output signal can become truncated. remain active and continue to mix signals, but the out- To prevent this, the carrier signal can be synchronized put value will not be sent to the MDOUT pin. During the to the modulator signal. When synchronization is time that the output is disabled, the MDOUT pin will enabled, the carrier pulse that is being mixed at the remain low. The modulated output can be disabled by time of the transition is allowed to transition low before clearing the MDOE bit in the MDCON register. the DSM switches over to the next carrier source. Synchronization is enabled separately for the carrier 23.2 Modulator Signal Sources high and carrier low signal sources. Synchronization for the carrier high signal can be enabled by setting the The modulator signal can be supplied from the follow- MDCHSYNC bit in the MDCARH register. Synchroniza- ing sources: tion for the carrier low signal can be enabled by setting • CCP1 Signal the MDCLSYNC bit in the MDCARL register. • CCP2 Signal Figure23-1 through Figure23-5 show timing diagrams • CCP3 Signal of using various synchronization methods. • CCP4 Signal • MSSP1 SDO1 Signal (SPI Mode Only) • MSSP2 SDO2 Signal (SPI Mode Only) • Comparator C1 Signal • Comparator C2 Signal • EUSART TX Signal • External Signal on MDMIN1 pin • MDBIT bit in the MDCON register The modulator signal is selected by configuring the MDMS <3:0> bits in the MDSRC register. DS41391D-page 194  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 23-2: ON OFF KEYING (OOK) SYNCHRONIZATION Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 EXAMPLE 23-1: NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier CARH CARL CARH CARL State FIGURE 23-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 Active Carrier CARH both CARL CARH both CARL State  2011 Microchip Technology Inc. DS41391D-page 195

PIC16(L)F1826/27 FIGURE 23-4: CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier CARH CARL CARH CARL State FIGURE 23-5: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier CARH CARL CARH CARL State DS41391D-page 196  2011 Microchip Technology Inc.

PIC16(L)F1826/27 23.5 Carrier Source Polarity Select 23.11 Operation in Sleep Mode The signal provided from any selected input source for The DSM module is not affected by Sleep mode. The the carrier high and carrier low signals can be inverted. DSM can still operate during Sleep, if the Carrier and Inverting the signal for the carrier high source is Modulator input sources are also still operable during enabled by setting the MDCHPOL bit of the MDCARH Sleep. register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCARL 23.12 Effects of a Reset register. Upon any device Reset, the data signal modulator 23.6 Carrier Source Pin Disable module is disabled. The user's firmware is responsible for initializing the module before enabling the output. Some peripherals assert control over their correspond- The registers are reset to their default values. ing output pin when they are enabled. For example, when the CCP1 module is enabled, the output of CCP1 is connected to the CCP1 pin. This default connection to a pin can be disabled by set- ting the MDCHODIS bit in the MDCARH register for the carrier high source and the MDCLODIS bit in the MDCARL register for the carrier low source. 23.7 Programmable Modulator Data The MDBIT of the MDCON register can be selected as the source for the modulator signal. This gives the user the ability to program the value used for modulation. 23.8 Modulator Source Pin Disable The modulator source default connection to a pin can be disabled by setting the MDMSODIS bit in the MDSRC register. 23.9 Modulated Output Polarity The modulated output signal provided on the MDOUT pin can also be inverted. Inverting the modulated out- put signal is enabled by setting the MDOPOL bit of the MDCON register. 23.10 Slew Rate Control The slew rate limitation on the output port pin can be disabled. The slew rate limitation can be removed by clearing the MDSLR bit in the MDCON register.  2011 Microchip Technology Inc. DS41391D-page 197

PIC16(L)F1826/27 REGISTER 23-1: MDCON: MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R-0/0 U-0 U-0 R/W-0/0 MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output bit 6 MDOE: Modulator Module Pin Output Enable bit 1 = Modulator pin output enabled 0 = Modulator pin output disabled bit 5 MDSLR: MDOUT Pin Slew Rate Limiting bit 1 = MDOUT pin slew rate limiting enabled 0 = MDOUT pin slew rate limiting disabled bit 4 MDOPOL: Modulator Output Polarity Select bit 1 = Modulator output signal is inverted 0 = Modulator output signal is not inverted bit 3 MDOUT: Modulator Output bit Displays the current output value of the modulator module.(1) bit 2-1 Unimplemented: Read as ‘0’ bit 0 MDBIT: Allows software to manually set modulation source input to module(2) 1 = Modulator uses High Carrier source 0 = Modulator uses Low Carrier source Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. 2: MDBIT must be selected as the modulation source in the MDSRC register for this operation. DS41391D-page 198  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 23-2: MDSRC: MODULATION SOURCE CONTROL REGISTER R/W-x/u U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDMSODIS — — — MDMS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDMSODIS: Modulation Source Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3-0 MDMS<3:0> Modulation Source Selection bits 1111 = Reserved. No channel connected. 1110 = Reserved. No channel connected. 1101 = Reserved. No channel connected. 1100 = Reserved. No channel connected. 1011 = Reserved. No channel connected. 1010 = EUSART TX output 1001 = MSSP2 SDOx output 1000 = MSSP1 SDOx output 0111 = Comparator2 output 0110 = Comparator1 output 0101 = CCP4 output (PWM Output mode only) 0100 = CCP3 output (PWM Output mode only) 0011 = CCP2 output (PWM Output mode only) 0010 = CCP1 output (PWM Output mode only) 0001 = MDMIN port pin 0000 = MDBIT bit of MDCON register is modulation source Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.  2011 Microchip Technology Inc. DS41391D-page 199

PIC16(L)F1826/27 REGISTER 23-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCHODIS MDCHPOL MDCHSYNC — MDCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCHODIS: Modulator High Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is enabled bit 6 MDCHPOL: Modulator High Carrier Polarity Select bit 1 = Selected high carrier signal is inverted 0 = Selected high carrier signal is not inverted bit 5 MDCHSYNC: Modulator High Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 = Modulator Output is not synchronized to the high time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 MDCH<3:0> Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. • • • 1000 = Reserved. No channel connected. 0111 = CCP4 output (PWM Output mode only) 0110 = CCP3 output (PWM Output mode only) 0101 = CCP2 output (PWM Output mode only) 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal 0010 = MDCIN2 port pin 0001 = MDCIN1 port pin 0000 = VSS Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. DS41391D-page 200  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 23-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCLODIS MDCLPOL MDCLSYNC — MDCL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is enabled bit 6 MDCLPOL: Modulator Low Carrier Polarity Select bit 1 = Selected low carrier signal is inverted 0 = Selected low carrier signal is not inverted bit 5 MDCLSYNC: Modulator Low Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 = Modulator Output is not synchronized to the low time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 MDCL<3:0> Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. • • • 1000 = Reserved. No channel connected. 0111 = CCP4 output (PWM Output mode only) 0110 = CCP3 output (PWM Output mode only) 0101 = CCP2 output (PWM Output mode only) 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal 0010 = MDCIN2 port pin 0001 = MDCIN1 port pin 0000 = VSS Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page MDCARH MDCHODIS MDCHPOL MDCHSYNC — MDCH<3:0> 200 MDCARL MDCLODIS MDCLPOL MDCLSYNC — MDCL<3:0> 201 MDCON MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT 198 MDSRC MDMSODIS — — — MDMS<3:0> 199 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode.  2011 Microchip Technology Inc. DS41391D-page 201

PIC16(L)F1826/27 NOTES: DS41391D-page 202  2011 Microchip Technology Inc.

PIC16(L)F1826/27 24.0 CAPTURE/COMPARE/PWM MODULES Note1: In devices with more than one CCP The Capture/Compare/PWM module is a peripheral module, it is very important to pay close which allows the user to time and control different attention to the register names used. A events, and to generate Pulse-Width Modulation number placed after the module acronym (PWM) signals. In Capture mode, the peripheral allows is used to distinguish between separate the timing of the duration of an event. The Compare modules. For example, the CCP1CON mode allows the user to trigger an external event when and CCP2CON control the same a predetermined amount of time has expired. The operational aspects of two completely PWM mode can generate Pulse-Width Modulated different CCP modules. signals of varying frequency and duty cycle. 2: Throughout this section, generic This family of devices contains two Enhanced references to a CCP module in any of its Capture/Compare/PWM modules (ECCP1 and operating modes may be interpreted as ECCP2) and two standard Capture/Compare/PWM being equally applicable to ECCP1, modules (CCP3 and CCP4). ECCP2, CCP3 and CCP4. Register names, module signals, I/O pins, and bit The Capture and Compare functions are identical for all names may use the generic designator 'x' four CCP modules (ECCP1, ECCP2, CCP3 and to indicate the use of a numeral to CCP4). The only differences between CCP modules distinguish a particular module, when are in the Pulse-Width Modulation (PWM) function. The required. standard PWM function is identical in modules, CCP3 and CCP4. In CCP modules ECCP1 and ECCP2, the Enhanced PWM function has slight variations from one another. Full-Bridge ECCP modules have four available I/O pins while Half-Bridge ECCP modules only have two available I/O pins. See Table24-1 for more information. TABLE 24-1: PWM RESOURCES Device Name ECCP1 ECCP2 CCP3 CCP4 Enhanced PWM PIC16(L)F1826 Not Available Not Available Not Available Full-Bridge Enhanced PWM Enhanced PWM PIC16(L)F1827 Standard PWM Standard PWM Full-Bridge Half-Bridge  2011 Microchip Technology Inc. DS41391D-page 203

PIC16(L)F1826/27 24.1 Capture Mode 24.1.2 TIMER1 MODE RESOURCE The Capture mode function described in this section is Timer1 must be running in Timer mode or Synchronized available and identical for CCP modules ECCP1, Counter mode for the CCP module to use the capture ECCP2, CCP3 and CCP4. feature. In Asynchronous Counter mode, the capture operation may not work. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the See Section21.0 “Timer1 Module with Gate Control” 16-bit CCPRxH:CCPRxL register pair captures and for more information on configuring Timer1. stores the 16-bit value of the TMR1H:TMR1L register 24.1.3 SOFTWARE INTERRUPT MODE pair, respectively. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of When the Capture mode is changed, a false capture the CCPxCON register: interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to • Every falling edge avoid false interrupts. Additionally, the user should • Every rising edge clear the CCPxIF interrupt flag bit of the PIRx register • Every 4th rising edge following any change in Operating mode. • Every 16th rising edge 24.1.4 CCP PRESCALER When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag There are four prescaler settings specified by the must be cleared in software. If another capture occurs CCPxM<3:0> bits of the CCPxCON register. Whenever before the value in the CCPRxH, CCPRxL register pair the CCP module is turned off, or the CCP module is not is read, the old captured value is overwritten by the new in Capture mode, the prescaler counter is cleared. Any captured value. Reset will clear the prescaler counter. Figure24-1 shows a simplified diagram of the Capture Switching from one capture prescaler to another does not operation. clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by 24.1.1 CCP PIN CONFIGURATION clearing the CCPxCON register before changing the In Capture mode, the CCPx pin should be configured prescaler. Equation24-1 demonstrates the code to as an input by setting the associated TRIS control bit. perform this function. Also, the CCPx pin function can be moved to EXAMPLE 24-1: CHANGING BETWEEN alternative pins using the APFCON0 register. Refer to CAPTURE PRESCALERS Section12.1 “Alternate Pin Function” for more details. BANKSELCCPxCON ;Set Bank bits to point ;to CCPxCON Note: If the CCPx pin is configured as an output, CLRF CCPxCON ;Turn CCP module off a write to the port can cause a capture MOVLW NEW_CAPT_PS;Load the W reg with condition. ;the new prescaler ;move value and CCP ON FIGURE 24-1: CAPTURE MODE MOVWF CCPxCON ;Load CCPxCON with this ;value OPERATION BLOCK DIAGRAM Set Flag bit CCPxIF (PIRx register) Prescaler  1, 4, 16 CCPx CCPRxH CCPRxL pin and Capture Edge Detect Enable TMR1H TMR1L CCPxM<3:0> System Clock (FOSC) DS41391D-page 204  2011 Microchip Technology Inc.

PIC16(L)F1826/27 24.1.5 CAPTURE DURING SLEEP 24.1.6 ALTERNATE PIN LOCATIONS Capture mode depends upon the Timer1 module for This module incorporates I/O pins that can be moved to proper operation. There are two options for driving the other locations with the use of the alternate pin function Timer1 module in Capture mode. It can be driven by the registers, APFCON0 and APFCON1. To determine instruction clock (FOSC/4), or by an external clock source. which pins can be moved and what their default loca- tions are upon a reset, see Section12.1 “Alternate When Timer1 is clocked by FOSC/4, Timer1 will not Pin Function” for more information. increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(2) CCP2SEL(2) P1DSEL P1CSEL CCP1SEL 119 CCPxCON PxM1(1) PxM0(1) DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 226 CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) 204* CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 204* CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 170 CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 — — C1NCH1 C1NCH0 171 CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 170 CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0 — — C2NCH1 C2NCH0 171 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE(2) 88 PIE3(2) — — CCP4IE CCP3IE TMR6IE — TMR4IE — 89 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 91 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF(2) 92 PIR3(2) — — CCP4IF CCP3IF TMR6IF — TMR4IF — 93 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 185 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS1 T1GSS0 186 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 177* TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 177* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by Capture mode. * Page provides register information. Note 1: Applies to ECCP modules only. 2: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 205

PIC16(L)F1826/27 24.2 Compare Mode 24.2.2 TIMER1 MODE RESOURCE The Compare mode function described in this section In Compare mode, Timer1 must be running in either Timer is available and identical for CCP modules ECCP1, mode or Synchronized Counter mode. The compare ECCP2, CCP3 and CCP4. operation may not work in Asynchronous Counter mode. Compare mode makes use of the 16-bit Timer1 See Section21.0 “Timer1 Module with Gate Control” resource. The 16-bit value of the CCPRxH:CCPRxL for more information on configuring Timer1. register pair is constantly compared against the 16-bit Note: Clocking Timer1 from the system clock value of the TMR1H:TMR1L register pair. When a (FOSC) should not be used in Compare match occurs, one of the following events can occur: mode. In order for Compare mode to • Toggle the CCPx output recognize the trigger event on the CCPx pin, TImer1 must be clocked from the • Set the CCPx output instruction clock (FOSC/4) or from an • Clear the CCPx output external clock source. • Generate a Special Event Trigger • Generate a Software Interrupt 24.2.3 SOFTWARE INTERRUPT MODE The action on the pin is based on the value of the When Generate Software Interrupt mode is chosen CCPxM<3:0> control bits of the CCPxCON register. At (CCPxM<3:0>=1010), the CCPx module does not the same time, the interrupt flag CCPxIF bit is set. assert control of the CCPx pin (see the CCPxCON All Compare modes can generate an interrupt. register). Figure24-2 shows a simplified diagram of the 24.2.4 SPECIAL EVENT TRIGGER Compare operation. When Special Event Trigger mode is chosen FIGURE 24-2: COMPARE MODE (CCPxM<3:0>=1011), the CCPx module does the following: OPERATION BLOCK DIAGRAM • Resets Timer1 • Starts an ADC conversion if ADC is enabled CCPxM<3:0> Mode Select The CCPx module does not assert control of the CCPx pin in this mode. Set CCPxIF Interrupt Flag The Special Event Trigger output of the CCP occurs (PIRx) CCPx 4 immediately upon a match between the TMR1H, Pin CCPRxH CCPRxL TMR1L register pair and the CCPRxH, CCPRxL Q S Output Comparator register pair. The TMR1H, TMR1L register pair is not R Logic Match reset until the next rising edge of the Timer1 clock. The Special Event Trigger output starts an A/D conversion TMR1H TMR1L TRIS (if the A/D module is enabled). This allows the Output Enable CCPRxH, CCPRxL register pair to effectively provide a Special Event Trigger 16-bit programmable period register for Timer1. TABLE 24-3: SPECIAL EVENT TRIGGER 24.2.1 CCP PIN CONFIGURATION Device CCPx/ECCPx The user must configure the CCPx pin as an output by PIC16(L)F1826 ECCP1 clearing the associated TRIS bit. PIC16(L)F1827 CCP4 Also, the CCPx pin function can be moved to Refer to Section16.2.5 “Special Event Trigger” for alternative pins using the APFCON0 register. Refer to more information. Section12.1 “Alternate Pin Function” for more details. Note1: The Special Event Trigger from the CCP module does not set interrupt flag bit Note: Clearing the CCPxCON register will force TMR1IF of the PIR1 register. the CCPx compare output latch to the default low level. This is not the PORT I/O 2: Removing the match condition by data latch. changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. DS41391D-page 206  2011 Microchip Technology Inc.

PIC16(L)F1826/27 24.2.5 COMPARE DURING SLEEP 24.2.6 ALTERNATE PIN LOCATIONS The Compare mode is dependent upon the system This module incorporates I/O pins that can be moved to clock (FOSC) for proper operation. Since FOSC is shut other locations with the use of the alternate pin function down during Sleep mode, the Compare mode will not registers, APFCON0 and APFCON1. To determine function properly during Sleep. which pins can be moved and what their default loca- tions are upon a reset, see Section12.1 “Alternate Pin Function” for more information. TABLE 24-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(2) CCP2SEL(2) P1DSEL P1CSEL CCP1SEL 119 CCPxCON PxM1(1) PxM0(1) DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 226 CCPRxL Capture/Compare/PWM Register x Low Byte (LSB) 204* CCPRxH Capture/Compare/PWM Register x High Byte (MSB) 204* CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 170 CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 — — C1NCH1 C1NCH0 171 CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 170 CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0 — — C2NCH1 C2NCH0 171 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE(2) 88 PIE3(2) — — CCP4IE CCP3IE TMR6IE — TMR4IE — 89 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 91 PIR2 OSFIF C2IF C1IF EEIF BCLIF — — CCP2IF(2) 92 PIR3(2) — — CCP4IF CCP3IF TMR6IF — TMR4IF — 93 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 185 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS1 T1GSS0 186 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 177* TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 177* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by Compare mode. * Page provides register information. Note 1: Applies to ECCP modules only. 2: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 207

PIC16(L)F1826/27 24.3 PWM Overview FIGURE 24-3: CCP PWM OUTPUT SIGNAL Pulse-Width Modulation (PWM) is a scheme that Period provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles Pulse Width a square wave where the high portion of the signal is TMRx = PRx considered the on state and the low portion of the signal TMRx = CCPRxH:CCPxCON<5:4> is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in TMRx = 0 steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to FIGURE 24-4: SIMPLIFIED PWM BLOCK the load. Lowering the number of steps applied, which DIAGRAM shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete CCPxCON<5:4> cycle or the total amount of on and off time combined. Duty Cycle Registers PWM resolution defines the maximum number of steps CCPRxL that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. CCPRxH(2) (Slave) CCPx The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, Comparator R Q where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher S TMRx (1) duty cycle corresponds to more power applied. TRIS Figure24-3 shows a typical waveform of the PWM signal. Comparator Clear Timer, toggle CCPx pin and 24.3.1 STANDARD PWM OPERATION latch duty cycle PRx The standard PWM function described in this section is Note 1: The 8-bit timer TMRx register is concatenated available and identical for CCP modules ECCP1, with the 2-bit internal system clock (FOSC), or ECCP2, CCP3 and CCP4. 2 bits of the prescaler, to create the 10-bit time The standard PWM mode generates a Pulse-Width base. Modulation (PWM) signal on the CCPx pin with up to 10 2: In PWM mode, CCPRxH is a read-only register. bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • PRx registers • TxCON registers • CCPRxL registers • CCPxCON registers Figure24-4 shows a simplified block diagram of PWM operation. Note1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. DS41391D-page 208  2011 Microchip Technology Inc.

PIC16(L)F1826/27 24.3.2 SETUP FOR PWM OPERATION When TMRx is equal to PRx, the following three events occur on the next increment cycle: The following steps should be taken when configuring the CCP module for standard PWM operation: • TMRx is cleared 1. Disable the CCPx pin output driver by setting the • The CCPx pin is set. (Exception: If the PWM duty associated TRIS bit. cycle=0%, the pin will not be set.) 2. Load the PRx register with the PWM period • The PWM duty cycle is latched from CCPRxL into value. CCPRxH. 3. Configure the CCP module for the PWM mode Note: The Timer postscaler (see Section22.1 by loading the CCPxCON register with the “Timer2/4/6 Operation”) is not used in the appropriate values. determination of the PWM frequency. 4. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty 24.3.5 PWM DUTY CYCLE cycle value. The PWM duty cycle is specified by writing a 10-bit 5. Configure and start Timer2/4/6: value to multiple registers: CCPRxL register and •Select the Timer2/4/6 resource to be used DCxB<1:0> bits of the CCPxCON register. The for PWM generation by setting the CCPRxL contains the eight MSbs and the DCxB<1:0> CxTSEL<1:0> bits in the CCPTMRS bits of the CCPxCON register contain the two LSbs. register. CCPRxL and DCxB<1:0> bits of the CCPxCON •Clear the TMRxIF interrupt flag bit of the register can be written to at any time. The duty cycle PIRx register. See Note below. value is not latched into CCPRxH until after the period •Configure the TxCKPS bits of the TxCON completes (i.e., a match between PRx and TMRx register with the Timer prescale value. registers occurs). While using the PWM, the CCPRxH •Enable the Timer by setting the TMRxON bit register is read-only. of the TxCON register. Equation24-2 is used to calculate the PWM pulse 6. Enable PWM output pin: width. •Wait until the Timer overflows and the TMRxIF Equation24-3 is used to calculate the PWM duty cycle bit of the PIRx register is set. See Note ratio. below. •Enable the CCPx pin output driver by clearing EQUATION 24-2: PULSE WIDTH the associated TRIS bit. Note: In order to send a complete duty cycle and Pulse Width = CCPRxL:CCPxCON<5:4>  period on the first PWM output, the above TOSC  (TMRx Prescale Value) steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, EQUATION 24-3: DUTY CYCLE RATIO then step 6 may be ignored. 24.3.3 TIMER2/4/6 TIMER RESOURCE CCPRxL:CCPxCON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------- 4PRx+1 The PWM standard mode makes use of one of the 8-bit Timer2/4/6 timer resources to specify the PWM period. The CCPRxH register and a 2-bit internal latch are Configuring the CxTSEL<1:0> bits in the CCPTMRS used to double buffer the PWM duty cycle. This double register selects which Timer2/4/6 timer is used. buffering is essential for glitchless PWM operation. 24.3.4 PWM PERIOD The 8-bit timer TMRx register is concatenated with either The PWM period is specified by the PRx register of the 2-bit internal system clock (FOSC), or 2 bits of the Timer2/4/6. The PWM period can be calculated using prescaler, to create the 10-bit time base. The system the formula of Equation24-1. clock is used if the Timer2/4/6 prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and EQUATION 24-1: PWM PERIOD 2-bit latch, then the CCPx pin is cleared (see Figure24-4). PWM Period = PRx+14TOSC (TMRx Prescale Value) Note 1: TOSC = 1/FOSC  2011 Microchip Technology Inc. DS41391D-page 209

PIC16(L)F1826/27 24.3.6 PWM RESOLUTION EQUATION 24-4: PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution log4PRx+1 Resolution = ------------------------------------------ bits will result in 1024 discrete duty cycles, whereas an 8-bit log2 resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PRx is Note: If the pulse width value is greater than the 255. The resolution is a function of the PRx register period the assigned PWM pin(s) will value as shown by Equation24-4. remain unchanged. TABLE 24-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz) PWM Frequency 1.95 kHz 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 24-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 24-7: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PRx Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 DS41391D-page 210  2011 Microchip Technology Inc.

PIC16(L)F1826/27 24.3.7 OPERATION IN SLEEP MODE 24.3.10 ALTERNATE PIN LOCATIONS In Sleep mode, the TMRxregister will not increment This module incorporates I/O pins that can be moved to and the state of the module will not change. If the CCPx other locations with the use of the alternate pin function pin is driving a value, it will continue to drive that value. registers, APFCON0 and APFCON1. To determine When the device wakes up, TMRx will continue from its which pins can be moved and what their default loca- previous state. tions are upon a reset, see Section12.1 “Alternate Pin Function” for more information. 24.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. 24.3.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. TABLE 24-8: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(2) CCP2SEL(2) P1DSEL P1CSEL CCP1SEL 119 CCPxCON PxM1(1) PxM0(1) DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 226 CCPxAS CCPxASE CCPxAS2 CCPxAS1 CCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 228 CCPTMRS C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 227 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PR2 Timer2 Period Register 189* PR4 Timer4 Module Period Register 189* PR6 Timer6 Module Period Register 189* PSTRxCON — — — STRxSYNC STRxD STRxC STRxB STRxA 230 PWMxCON PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 229 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 191 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 191 T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 191 TMR2 Holding Register for the 8-bit TMR2 Time Base 189* TMR4 Holding Register for the 8-bit TMR4 Time Base(1) 189* TMR6 Holding Register for the 8-bit TMR6 Time Base(1) 189* TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. Note 1: Applies to ECCP modules only. 2: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 211

PIC16(L)F1826/27 24.4 PWM (Enhanced Mode) To select an Enhanced PWM Output mode, the PxM bits of the CCPxCON register must be configured The enhanced PWM function described in this section is appropriately. available for CCP modules ECCP1 and ECCP2, with The PWM outputs are multiplexed with I/O pins and are any differences between modules noted. designated PxA, PxB, PxC and PxD. The polarity of the The enhanced PWM mode generates a Pulse-Width PWM pins is configurable and is selected by setting the Modulation (PWM) signal on up to four different output CCPxM bits in the CCPxCON register appropriately. pins with up to 10 bits of resolution. The period, duty Figure24-5 shows an example of a simplified block cycle, and resolution are controlled by the following diagram of the Enhanced PWM module. registers: Figure24-9 shows the pin assignments for various • PRx registers Enhanced PWM modes. • TxCON registers • CCPRxL registers Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the • CCPxCON registers CCPx pin. The ECCP modules have the following additional PWM 2: Clearing the CCPxCON register will registers which control Auto-shutdown, Auto-restart, relinquish control of the CCPx pin. Dead-band Delay and PWM Steering modes: 3: Any pin not used in the enhanced PWM • CCPxAS registers mode is available for alternate pin • PSTRxCON registers functions, if applicable. • PWMxCON registers 4: To prevent the generation of an The enhanced PWM module can generate the following incomplete waveform when the PWM is five PWM Output modes: first enabled, the ECCP module waits • Single PWM until the start of a new PWM period before generating a PWM signal. • Half-Bridge PWM • Full-Bridge PWM, Forward Mode • Full-Bridge PWM, Reverse Mode • Single PWM with PWM Steering Mode FIGURE 24-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DCxB<1:0> PxM<1:0> CCPxM<3:0> Duty Cycle Registers 2 4 CCPRxL CCPx/PxA CCPx/PxA TRISx CCPRxH (Slave) PxB PxB Output TRISx Comparator R Q Controller PxC PxC TMRx (1) S TRISx PxD PxD Comparator Clear Timer, TRISx toggle PWM pin and latch duty cycle PRx PWMxCON Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. DS41391D-page 212  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 24-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> CCPx/PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: PWM Steering enables outputs in Single mode. FIGURE 24-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse PRX+1 PxM<1:0> Signal 0 Width Period 00 (Single Output) PxA Modulated Delay Delay PxA Modulated 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>)  2011 Microchip Technology Inc. DS41391D-page 213

PIC16(L)F1826/27 FIGURE 24-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal 0 Pulse PRx+1 Width Period 00 (Single Output) PxA Modulated PxA Modulated Delay Delay 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>) DS41391D-page 214  2011 Microchip Technology Inc.

PIC16(L)F1826/27 24.4.1 HALF-BRIDGE MODE Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be In Half-Bridge mode, two pins are used as outputs to cleared to configure PxA and PxB as outputs. drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM FIGURE 24-8: EXAMPLE OF output signal is output on the PxB pin (see HALF-BRIDGE PWM Figure24-9). This mode can be used for Half-Bridge applications, as shown in Figure24-9, or for Full-Bridge OUTPUT applications, where four power switches are being Period Period modulated with two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in PxA(2) Half-Bridge power devices. The value of the PDC<6:0> td bits of the PWMxCON register sets the number of td instruction cycles before the output is driven active. If the PxB(2) value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See (1) (1) (1) Section24.4.5 “Programmable Dead-Band Delay Mode” for more details of the dead-band delay td = Dead-Band Delay operations. Note 1: At this time, the TMRx register is equal to the PRx register. 2: Output signals are shown as active-high. FIGURE 24-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA - Load FET Driver + PxB - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver PxA Load FET FET Driver Driver PxB  2011 Microchip Technology Inc. DS41391D-page 215

PIC16(L)F1826/27 24.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure24-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure24-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure24-11. PxA, PxB, PxC and PxD outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs. FIGURE 24-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver PxA Load PxB FET FET Driver Driver PxC QB QD V- PxD DS41391D-page 216  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 24-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA(2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) (1) Note 1: At this time, the TMRx register is equal to the PRx register. 2: Output signal is shown as active-high.  2011 Microchip Technology Inc. DS41391D-page 217

PIC16(L)F1826/27 24.4.2.1 Direction Change in Full-Bridge The Full-Bridge mode does not provide dead-band Mode delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation In the Full-Bridge mode, the PxM1 bit in the CCPxCON where dead-band delay is required. This situation register allows users to control the forward/reverse occurs when both of the following conditions are true: direction. When the application firmware changes this direction control bit, the module will change to the new 1. The direction of the PWM output changes when direction on the next PWM cycle. the duty cycle of the output is at or near 100%. 2. The turn off time of the power switch, including A direction change is initiated in software by changing the power device and driver circuit, is greater the PxM1 bit of the CCPxCON register. The following than the turn on time. sequence occurs four Timer cycles prior to the end of the current PWM period: Figure24-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty • The modulated outputs (PxB and PxD) are placed cycle. In this example, at time t1, the output PxA and in their inactive state. PxD become inactive, while output PxC becomes • The associated unmodulated outputs (PxA and active. Since the turn off time of the power devices is PxC) are switched to drive in the opposite longer than the turn on time, a shoot-through current direction. will flow through power devices QC and QD (see • PWM modulation resumes at the beginning of the Figure24-10) for the duration of ‘t’. The same next period. phenomenon will occur to power devices QA and QB See Figure24-12 for an illustration of this sequence. for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 24-12: EXAMPLE OF PWM DIRECTION CHANGE Signal Period(1) Period PxA (Active-High) PxB (Active-High) Pulse Width PxC (Active-High) (2) PxD (Active-High) Pulse Width Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle. 2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts. DS41391D-page 218  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 24-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential T = TOFF – TON Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver.  2011 Microchip Technology Inc. DS41391D-page 219

PIC16(L)F1826/27 24.4.3 ENHANCED PWM AUTO-SHUTDOWN MODE Note1: The auto-shutdown condition is a The PWM mode supports an Auto-Shutdown mode that level-based signal, not an edge-based will disable the PWM outputs when an external signal. As long as the level is present, the shutdown event occurs. Auto-Shutdown mode places auto-shutdown will persist. the PWM output pins into a predetermined state. This 2: Writing to the CCPxASE bit of the mode is used to help prevent the PWM from damaging CCPxAS register is disabled while an the application. auto-shutdown condition persists. The auto-shutdown sources are selected using the 3: Once the auto-shutdown condition has CCPxAS<2:0> bits of the CCPxAS register. A shutdown been removed and the PWM restarted event may be generated by: (either through firmware or auto-restart) • A logic ‘0’ on the INT pin the PWM signal will always restart at the • A logic ‘1’ on a Comparator (Cx) output beginning of the next PWM period. A shutdown condition is indicated by the CCPxASE 4: Prior to an auto-shutdown event caused (Auto-Shutdown Event Status) bit of the CCPxAS by a comparator output or INT pin event, register. If the bit is a ‘0’, the PWM pins are operating a software shutdown can be triggered in normally. If the bit is a ‘1’, the PWM outputs are in the firmware by setting the CCPxASE bit of shutdown state. the CCPxAS register to ‘1’. The Auto-Restart feature tracks the active When a shutdown event occurs, two things happen: status of a shutdown caused by a The CCPxASE bit is set to ‘1’. The CCPxASE will comparator output or INT pin event only. remain set until cleared in firmware or an auto-restart If it is enabled at this time, it will occurs (see Section24.4.4 “Auto-Restart Mode”). immediately clear this bit and restart the ECCP module at the beginning of the The enabled PWM pins are asynchronously placed in next PWM period. their shutdown states. The PWM output pins are grouped into pairs [PxA/PxC] and [PxB/PxD]. The state of each pin pair is determined by the PSSxAC and PSSxBD bits of the CCPxAS register. Each pin pair may be placed into one of three states: • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) FIGURE 24-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0) Missing Pulse Missing Pulse (Auto-Shutdown) (CCPxASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent CCPxASE bit PWM Shutdown Shutdown Resumes Event Occurs Event Clears CCPxASE Cleared by Firmware DS41391D-page 220  2011 Microchip Technology Inc.

PIC16(L)F1826/27 24.4.4 AUTO-RESTART MODE If auto-restart is enabled, the CCPxASE bit will remain set as long as the auto-shutdown condition is active. The Enhanced PWM can be configured to automati- When the auto-shutdown condition is removed, the cally restart the PWM signal once the auto-shutdown CCPxASE bit will be cleared via hardware and normal condition has been removed. Auto-restart is enabled by operation will resume. setting the PxRSEN bit in the PWMxCON register. FIGURE 24-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1) Missing Pulse Missing Pulse (Auto-Shutdown) (CCPxASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent CCPxASE bit PWM Shutdown Resumes Event Occurs Shutdown CCPxASE Event Clears Cleared by Hardware  2011 Microchip Technology Inc. DS41391D-page 221

PIC16(L)F1826/27 24.4.5 PROGRAMMABLE DEAD-BAND FIGURE 24-16: EXAMPLE OF DELAY MODE HALF-BRIDGE PWM OUTPUT In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power Period Period switches normally require more time to turn off than to turn on. If both the upper and lower power switches are Pulse Width switched at the same time (one turned on, and the PxA(2) other turned off), both switches may be on for a short td period of time until one switch completely turns off. td During this brief interval, a very high current PxB(2) (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this (1) (1) (1) potentially destructive shoot-through current from flowing during switching, turning on either of the power td = Dead-Band Delay switches is normally delayed to allow the other switch to completely turn off. Note 1: At this time, the TMRx register is equal to the In Half-Bridge mode, a digitally programmable PRx register. dead-band delay is available to avoid shoot-through 2: Output signals are shown as active-high. current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure24-16 for illustration. The lower seven bits of the associated PWMxCON register (Register24-4) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 24-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA V - Load FET Driver + PxB V - V- DS41391D-page 222  2011 Microchip Technology Inc.

PIC16(L)F1826/27 24.4.6 PWM STEERING MODE In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCPxM<3:2>=11 and PxM<1:0>=00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STRx<D:A> bits of the PSTRxCON register, as shown in Register24-5. Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. While the PWM Steering mode is active, CCPxM<1:0> bits of the CCPxCON register select the PWM output polarity for the Px<D:A> pins. The PWM auto-shutdown operation also applies to PWM Steering mode as described in Section24.4.3 “Enhanced PWM Auto-shutdown mode”. An auto-shutdown event will only affect pins that have PWM outputs enabled. FIGURE 24-18: SIMPLIFIED STEERING BLOCK DIAGRAM STRxA PxA Signal PxA pin CCPxM1 1 PORT Data 0 TRIS STRxB PxB pin CCPxM0 1 PORT Data 0 TRIS STRxC PxC pin CCPxM1 1 PORT Data 0 TRIS STRxD PxD pin CCPxM0 1 PORT Data 0 TRIS Note 1: Port outputs are configured as shown when the CCPxCON register bits PxM<1:0>=00 and CCPxM<3:2>=11. 2: Single PWM output requires setting at least one of the STRx bits.  2011 Microchip Technology Inc. DS41391D-page 223

PIC16(L)F1826/27 24.4.6.1 Steering Synchronization configuration while the PWM pin output drivers are enable is not recommended since it may result in The STRxSYNC bit of the PSTRxCON register gives damage to the application circuits. the user two selections of when the steering event will happen. When the STRxSYNC bit is ‘0’, the steering The PxA, PxB, PxC and PxD output latches may not be event will happen at the end of the instruction that in the proper states when the PWM module is writes to the PSTRxCON register. In this case, the initialized. Enabling the PWM pin output drivers at the output signal at the Px<D:A> pins may be an same time as the Enhanced PWM modes may cause incomplete PWM waveform. This operation is useful damage to the application circuit. The Enhanced PWM when the user firmware needs to immediately remove modes must be enabled in the proper Output mode and a PWM signal from the pin. complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle When the STRxSYNC bit is ‘1’, the effective steering is indicated by the TMRxIF bit of the PIRx register update will happen at the beginning of the next PWM being set as the second PWM period begins. period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. Note: When the microcontroller is released from Reset, all of the I/O pins are in the Figures 24-19 and24-20 illustrate the timing diagrams high-impedance state. The external cir- of the PWM steering depending on the STRxSYNC cuits must keep the power switch devices setting. in the Off state until the microcontroller 24.4.7 START-UP CONSIDERATIONS drives the I/O pins with the proper signal levels or activates the PWM output(s). When any PWM mode is used, the application hardware must use the proper external pull-up and/or 24.4.8 ALTERNATE PIN LOCATIONS pull-down resistors on the PWM output pins. This module incorporates I/O pins that can be moved to The CCPxM<1:0> bits of the CCPxCON register allow other locations with the use of the alternate pin function the user to choose whether the PWM output signals are registers, APFCON0 and APFCON1. To determine active-high or active-low for each pair of PWM output which pins can be moved and what their default loca- pins (PxA/PxC and PxB/PxD). The PWM output tions are upon a reset, see Section12.1 “Alternate polarities must be selected before the PWM pin output Pin Function” for more information. drivers are enabled. Changing the polarity FIGURE 24-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0) PWM Period PWM STRx P1<D:A> PORT Data PORT Data P1n = PWM FIGURE 24-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRxSYNC = 1) PWM STRx P1<D:A> PORT Data PORT Data P1n = PWM DS41391D-page 224  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 24-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(2) CCP2SEL(2) P1DSEL P1CSEL CCP1SEL 119 CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 226 CCPxAS CCPxASE CCPxAS<2:0> PSSxAC<1:0> PSSxBD<1:0> 228 CCPTMRS C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 227 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE C1IE EEIE BCLIE — — CCP2IE 88 PIE3(2) — — CCP4IE CCP3IE TMR6IE — TMR4IE — 89 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 91 PIR2 OSFIF C2IF C1IF EEIF BCLIF — — CCP2IF 92 PIR3(2) — — CCP4IF CCP3IF TMR6IF — TMR4IF — 93 PR2 Timer2 Period Register 189* PR4 Timer4 Module Period Register 189* PR6 Timer6 Module Period Register 189* PSTRxCON — — — STRxSYNC STRxD STRxC STRxB STRxA 230 PWMxCON PxRSEN PxDC<6:0> 229 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 191 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 191 T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 191 TMR2 Holding Register for the 8-bit TMR2 Time Base 189* TMR4 Holding Register for the 8-bit TMR4 Time Base(1) 189* TMR6 Holding Register for the 8-bit TMR6 Time Base(1) 189* TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. Note 1: Applies to ECCP modules only. 2: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 225

PIC16(L)F1826/27 24.5 CCP Control Registers REGISTER 24-1: CCPxCON: CCPx CONTROL REGISTER R/W-00 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits(1) Capture mode: Unused Compare mode: Unused If CCPxM<3:2> = 00, 01, 10: xx =PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins If CCPxM<3:2> = 11: 00 =Single output; PxA modulated; PxB, PxC, PxD assigned as port pins 01 =Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive 10 =Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins 11 =Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits 0000 =Capture/Compare/PWM off (resets ECCPx module) 0001 =Reserved 0010 =Compare mode: toggle output on match 0011 =Reserved 0100 =Capture mode: every falling edge 0101 =Capture mode: every rising edge 0110 =Capture mode: every 4th rising edge 0111 =Capture mode: every 16th rising edge 1000 =Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF) 1001 =Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF) 1010 =Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state 1011 =Compare mode: Special Event Trigger (ECCPx resets Timer, sets CCPxIF bit, starts A/D conversion if A/D module is enabled)(1) CCP Modules only: 11xx =PWM mode ECCP Modules only: 1100 =PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 =PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 =PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 =PWM mode: PxA, PxC active-low; PxB, PxD active-low Note 1: These bits are not implemented on CCP<4:3>. DS41391D-page 226  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 24-2: CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection 00 =CCP4 is based off Timer 2 in PWM Mode 01 =CCP4 is based off Timer 4 in PWM Mode 10 =CCP4 is based off Timer 6 in PWM Mode 11 =Reserved bit 5-4 C3TSEL<1:0>: CCP3 Timer Selection 00 =CCP3 is based off Timer 2 in PWM Mode 01 =CCP3 is based off Timer 4 in PWM Mode 10 =CCP3 is based off Timer 6 in PWM Mode 11 =Reserved bit 3-2 C2TSEL<1:0>: CCP2 Timer Selection 00 =CCP2 is based off Timer 2 in PWM Mode 01 =CCP2 is based off Timer 4 in PWM Mode 10 =CCP2 is based off Timer 6 in PWM Mode 11 =Reserved bit 1-0 C1TSEL<1:0>: CCP1 Timer Selection 00 =CCP1 is based off Timer 2 in PWM Mode 01 =CCP1 is based off Timer 4 in PWM Mode 10 =CCP1 is based off Timer 6 in PWM Mode 11 =Reserved  2011 Microchip Technology Inc. DS41391D-page 227

PIC16(L)F1826/27 REGISTER 24-3: CCPxAS: CCPx AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCPxASE CCPxAS<2:0> PSSxAC<1:0> PSSxBD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCPxASE: CCPx Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; CCPx outputs are in shutdown state 0 = CCPx outputs are operating bit 6-4 CCxPAS<2:0>: CCPx Auto-Shutdown Source Select bits 000 =Auto-shutdown is disabled 001 =Comparator C1 output high(1) 010 =Comparator C2 output high(1) 011 =Either Comparator C1 or C2 high(1) 100 =VIL on INT pin 101 =VIL on INT pin or Comparator C1 high(1) 110 =VIL on INT pin or Comparator C2 high(1) 111 =VIL on INT pin or Comparator C1 or Comparator C2 high(1) bit 3-2 PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits 00 = Drive pins PxA and PxC to ‘0’ 01 = Drive pins PxA and PxC to ‘1’ 1x = Pins PxA and PxC tri-state bit 1-0 PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits 00 = Drive pins PxB and PxD to ‘0’ 01 = Drive pins PxB and PxD to ‘1’ 1x = Pins PxB and PxD tri-state Note 1: If CxSYNC is enabled, the shutdown will be delayed by Timer1. DS41391D-page 228  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 24-4: PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxRSEN PxDC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM bit 6-0 PxDC<6:0>: PWM Delay Count bits PxDCx =Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled.  2011 Microchip Technology Inc. DS41391D-page 229

PIC16(L)F1826/27 REGISTER 24-5: PSTRxCON: PWM STEERING CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 — — — STRxSYNC STRxD STRxC STRxB STRxA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRxSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRxD: Steering Enable bit D 1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxD pin is assigned to port pin bit 2 STRxC: Steering Enable bit C 1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxC pin is assigned to port pin bit 1 STRxB: Steering Enable bit B 1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxB pin is assigned to port pin bit 0 STRxA: Steering Enable bit A 1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = PxA pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2>=11 and PxM<1:0>=00. DS41391D-page 230  2011 Microchip Technology Inc.

PIC16(L)F1826/27 25.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP1 AND MSSP2) MODULE 25.1 Master SSPx (MSSPx) Module Overview The Master Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc. The MSSPx module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) The SPI interface supports the following modes and features: • Master mode • Slave mode • Clock Parity • Slave Select Synchronization (Slave mode only) • Daisy-chain connection of slave devices Figure25-1 is a block diagram of the SPI interface module. FIGURE 25-1: MSSPX BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SDIx SSPxSR Reg SDOx bit 0 Shift Clock SSx SSxControl 2 (CKP, CKE) Enable Clock Select Edge Select SSPxM<3:0> 4 ( T M R 2 O u tp u t ) 2 SCKx Edge Prescaler TOSC Select 4, 16, 64 Baud Rate Generator TRIS bit (SSPxADD)  2011 Microchip Technology Inc. DS41391D-page 231

PIC16(L)F1826/27 The I2C interface supports the following modes and The PIC16F1827 has two MSSP modules, MSSP1 and features: MSSP2, each module operating independently from the other. • Master mode • Slave mode • Byte NACKing (Slave mode) Note1: In devices with more than one MSSP • Limited Multi-master support module, it is very important to pay close • 7-bit and 10-bit addressing attention to SSPxCONx register names. SSP1CON1 and SSP1CON2 registers • Start and Stop interrupts control different operational aspects of • Interrupt masking the same module, while SSP1CON1 and • Clock stretching SSP2CON1 control the same features for • Bus collision detection two different modules. • General call address matching 2: Throughout this section, generic refer- • Address masking ences to an MSSP module in any of its • Address Hold and Data Hold modes operating modes may be interpreted as • Selectable SDAx hold times being equally applicable to MSSP1 or MSSP2. Register names, module I/O sig- Figure25-2 is a block diagram of the I2C interface nals, and bit names may use the generic module in Master mode. Figure25-3 is a diagram of the designator ‘x’ to indicate the use of a I2C interface module in Slave mode. numeral to distinguish a particular module when required. FIGURE 25-2: MSSPX BLOCK DIAGRAM (I2C™ MASTER MODE) Internal data bus [SSPxM 3:0] Read Write SSPxBUF Baud rate generator (SSPxADD) SDAx Shift SDAx in Clock SSPxSR ct e Enable (RCEN) GMeSnSbetAararcttk ebn i(otS,w SSletPodxpgC ebOitL,NS2b) Clock Cntl arbitrate/BCOL det d off clock source) SCLx ceive Clock (Hol e R Start bit detect, Stop bit detect SCLx in Write collision detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV Clock arbitration Reset SEN, PEN (SSPxCON2) Bus Collision State counter for Set SSPxIF, BCLxIF end of XMIT/RCV Address Match detect DS41391D-page 232  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-3: MSSPX BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCLx Shift Clock SSPxSR Reg SDAx MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Set, Reset Stop bit Detect S, P bits (SSPxSTAT Reg)  2011 Microchip Technology Inc. DS41391D-page 233

PIC16(L)F1826/27 25.2 SPI Mode Overview During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master The Serial Peripheral Interface (SPI) bus is a device is sending out the MSb from its shift register (on synchronous serial data communication bus that its SDOx pin) and the slave device is reading this bit operates in Full-Duplex mode. Devices communicate and saving it as the LSb of its shift register, that the in a master/slave environment where the master device slave device is also sending out the MSb from its shift initiates the communication. A slave device is register (on its SDOx pin) and the master device is controlled through a Chip Select known as Slave reading this bit and saving it as the LSb of its shift Select. register. The SPI bus specifies four signal connections: After 8 bits have been shifted out, the master and slave • Serial Clock (SCKx) have exchanged register values. • Serial Data Out (SDOx) If there is more data to exchange, the shift registers are • Serial Data In (SDIx) loaded with new data and the process repeats itself. • Slave Select (SSx) Whether the data is meaningful or not (dummy data), Figure25-1 shows the block diagram of the MSSPx depends on the application software. This leads to module when operating in SPI Mode. three scenarios for data transmission: The SPI bus operates with a single master device and • Master sends useful data and slave sends dummy one or more slave devices. When multiple slave data. devices are used, an independent Slave Select con- • Master sends useful data and slave sends useful nection is required from the master device to each data. slave device. • Master sends dummy data and slave sends useful Figure25-4 shows a typical connection between a data. master device and multiple slave devices. Transmissions may involve any number of clock The master selects only one slave at a time. Most slave cycles. When there is no more data to be transmitted, devices have tri-state outputs so their output signal the master stops sending the clock signal and it dese- appears disconnected from the bus when they are not lects the slave. selected. Every slave device connected to the bus that has not Transmissions involve two shift registers, eight bits in been selected through its slave select line must disre- size, one in the master and one in the slave. With either gard the clock and transmission signals and must not the master or the slave device, data is always shifted transmit out any data of its own. out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure25-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the pro- grammed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDOx output pin which is connected to, and received by, the slave's SDIx input pin. The slave device trans- mits information out on its SDOx output pin, which is connected to, and received by, the master's SDIx input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polar- ity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. DS41391D-page 234  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SCKx SCKx SPI Master SDOx SDIx SPI Slave SDIx SDOx #1 General I/O SSx General I/O General I/O SCKx SDIx SPI Slave SDOx #2 SSx SCKx SDIx SPI Slave SDOx #3 SSx 25.2.1 SPI MODE REGISTERS The MSSPx module has five registers for SPI mode operation. These are: • MSSPx STATUS register (SSPxSTAT) • MSSPx Control Register 1 (SSPxCON1) • MSSPx Control Register 3 (SSPxCON3) • MSSPx Data Buffer register (SSPxBUF) • MSSPx Address register (SSPxADD) • MSSPx Shift register (SSPxSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control and STA- TUS registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. In one SPI master mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section25.7 “Baud Rate Generator”. SSPxSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPxSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPxSR and SSPxBUF together create a buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR.  2011 Microchip Technology Inc. DS41391D-page 235

PIC16(L)F1826/27 25.2.2 SPI MODE OPERATION Any serial port function that is not desired may be overridden by programming the corresponding data When initializing the SPI, several options need to be direction (TRIS) register to the opposite value. specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). The MSSPx consists of a transmit/receive shift register These control bits allow the following to be specified: (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb • Master mode (SCKx is the clock output) first. The SSPxBUF holds the data that was written to • Slave mode (SCKx is the clock input) the SSPxSR until the received data is ready. Once the • Clock Polarity (Idle state of SCKx) 8 bits of data have been received, that byte is moved to • Data Input Sample Phase (middle or end of data the SSPxBUF register. Then, the Buffer Full Detect bit, output time) BF of the SSPxSTAT register, and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received • Clock Edge (output data on rising/falling edge of data (SSPxBUF) allows the next byte to start reception SCKx) before reading the data that was just received. Any • Clock Rate (Master mode only) write to the SSPxBUF register during • Slave Select mode (Slave mode only) transmission/reception of data will be ignored and the To enable the serial port, SSPx Enable bit, SSPxEN of write collision detect bit WCOL of the SSPxCON1 the SSPxCON1 register, must be set. To reset or recon- register, will be set. User software must clear the figure SPI mode, clear the SSPxEN bit, re-initialize the WCOL bit to allow the following write(s) to the SSPxCONx registers and then set the SSPxEN bit. SSPxBUF register to complete successfully. This configures the SDIx, SDOx, SCKx and SSx pins When the application software is expecting to receive as serial port pins. For the pins to behave as the serial valid data, the SSPxBUF should be read before the port function, some must have their data direction bits next byte of data to transfer is written to the SSPxBUF. (in the TRIS register) appropriately programmed as fol- The Buffer Full bit, BF of the SSPxSTAT register, lows: indicates when SSPxBUF has been loaded with the • SDIx must have corresponding TRIS bit set received data (transmission is complete). When the • SDOx must have corresponding TRIS bit cleared SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, • SCKx (Master mode) must have corresponding the MSSPx interrupt is used to determine when the TRIS bit cleared transmission/reception has completed. If the interrupt • SCKx (Slave mode) must have corresponding method is not going to be used, then software polling TRIS bit set can be done to ensure that a write collision does not • SSx must have corresponding TRIS bit set occur. FIGURE 25-5: SPI MASTER/SLAVE CONNECTION SPI Master SSPxM<3:0> = 00xx SPI Slave SSPxM<3:0> = 010x = 1010 SDOx SDIx Serial Input Buffer Serial Input Buffer (BUF) (SSPxBUF) SDIx SDOx Shift Register Shift Register (SSPxSR) (SSPxSR) MSb LSb MSb LSb Serial Clock SCKx SCKx Slave Select General I/O SSx Processor 1 (optional) Processor 2 DS41391D-page 236  2011 Microchip Technology Inc.

PIC16(L)F1826/27 25.2.3 SPI MASTER MODE The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register The master can initiate the data transfer at any time and the CKE bit of the SSPxSTAT register. This then, because it controls the SCKx line. The master would give waveforms for SPI communication as determines when the slave (Processor 2, Figure25-5) shown in Figure25-6, Figure25-8 and Figure25-9, is to broadcast data by the software protocol. where the MSB is transmitted first. In Master mode, the In Master mode, the data is transmitted/received as SPI clock rate (bit rate) is user programmable to be one soon as the SSPxBUF register is written to. If the SPI of the following: is only going to receive, the SDOx output could be dis- • FOSC/4 (or TCY) abled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDIx • FOSC/16 (or 4 * TCY) pin at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY) received, it will be loaded into the SSPxBUF register as • Timer2 output/2 if a normal received byte (interrupts and Status bits • Fosc/(4 * (SSPxADD + 1)) appropriately set). Figure25-6 shows the waveforms for Master mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. FIGURE 25-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDIx (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF  2011 Microchip Technology Inc. DS41391D-page 237

PIC16(L)F1826/27 25.2.4 SPI SLAVE MODE 25.2.5 SLAVE SELECT SYNCHRONIZATION In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last The Slave Select can also be used to synchronize com- bit is latched, the SSPxIF interrupt flag bit is set. munication. The Slave Select line is held high until the Before enabling the module in SPI Slave mode, the clock master device is ready to communicate. When the line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a be observed by reading the SCKx pin. The Idle state is new transmission is starting. determined by the CKP bit of the SSPxCON1 register. If the slave fails to receive the communication properly, While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the the external clock source on the SCKx pin. This exter- Slave Select line returns to a high state. The slave is nal clock must meet the minimum high and low times then ready to receive a new transmission when the as specified in the electrical specifications. Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will even- While in Sleep mode, the slave can transmit/receive tually become out of sync with the master. If the slave data. The shift register is clocked from the SCKx pin misses a bit, it will always be one bit off in future trans- input and when a byte is received, the device will gen- missions. Use of the Slave Select line allows the slave erate an interrupt. If enabled, the device will wake-up and master to align themselves at the beginning of from Sleep. each transmission. 25.2.4.1 Daisy-Chain Configuration The SSx pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SSx pin control The SPI bus can sometimes be connected in a enabled (SSPxCON1<3:0> = 0100). daisy-chain configuration. The first slave output is con- nected to the second slave input, the second slave When the SSx pin is low, transmission and reception output is connected to the third slave input, and so on. are enabled and the SDOx pin is driven. The final slave output is connected to the master input. When the SSx pin goes high, the SDOx pin is no longer Each slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down first group of clock pulses. The whole chain acts as resistors may be desirable depending on the applica- one large communication shift register. The tion. daisy-chain feature only requires a single Slave Select line from the master device. Note 1: When the SPI is in Slave mode with SSx pin control enabled (SSPxCON1<3:0> = Figure25-7 shows the block diagram of a typical 0100), the SPI module will reset if the SSx daisy-chain connection when operating in SPI Mode. pin is set to VDD. In a daisy-chain configuration, only the most recent 2: When the SPI is used in Slave mode with byte on the bus is required by the slave. Setting the CKE set; the user must enable SSx pin BOEN bit of the SSPxCON3 register will enable writes control. to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data 3: While operated in SPI Slave mode the that may not apply to it. SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SSx pin to a high level or clearing the SSPxEN bit. DS41391D-page 238  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-7: SPI DAISY-CHAIN CONNECTION SCK SCK SPI Master SDOx SDIx SPI Slave SDIx SDOx #1 General I/O SSx SCK SDIx SPI Slave SDOx #2 SSx SCK SDIx SPI Slave SDOx #3 SSx FIGURE 25-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDOx bit 7 bit 6 bit 7 bit 6 bit 0 SDIx bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF  2011 Microchip Technology Inc. DS41391D-page 239

PIC16(L)F1826/27 FIGURE 25-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE=0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 7 bit 0 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 25-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 7 bit 0 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active DS41391D-page 240  2011 Microchip Technology Inc.

PIC16(L)F1826/27 25.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmis- In SPI Master mode, module clocks may be operating sion/reception will remain in that state until the device at a different speed than when in full power mode; in wakes. After the device returns to Run mode, the mod- the case of the Sleep mode, all clocks are halted. ule will resume transmitting and receiving data. Special care must be taken by the user when the In SPI Slave mode, the SPI Transmit/Receive Shift MSSPx clock is much faster than the system clock. register operates asynchronously to the device. This In Slave mode, when MSSPx interrupts are enabled, allows the device to be placed in Sleep mode and data after the master completes sending data, an MSSPx to be shifted into the SPI Transmit/Receive Shift interrupt will wake the controller from Sleep. register. When all 8 bits have been received, the MSSPx interrupt flag bit will be set and if enabled, will If an exit from Sleep mode is not desired, MSSPx inter- wake the device. rupts should be disabled. TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(1) CCP2SEL(1) P1DSEL P1CSEL CCP1SEL 119 ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 123 ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — 128 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 91 SSPxBUF Synchronous Serial Port Receive Buffer/Transmit Register 235* SSPxCON1 WCOL SSPxOV SSPxEN CKP SSPxM3 SSPxM2 SSPxM1 SSPxM0 280 SSPxCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 282 SSPxSTAT SMP CKE D/A P S R/W UA BF 279 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode. * Page provides register information. Note 1: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 241

PIC16(L)F1826/27 25.3 I2C MODE OVERVIEW FIGURE 25-11: I2C MASTER/ SLAVE CONNECTION The Inter-Integrated Circuit Bus (I²C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master VDD devices initiate the communication. A Slave device is controlled through addressing. SCLx SCLx The I2C bus specifies two signal connections: VDD • Serial Clock (SCLx) Master Slave • Serial Data (SDAx) SDAx SDAx Figure25-11 shows the block diagram of the MSSPx module when operating in I2C Mode. Both the SCLx and SDAx connections are bidirectional open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal, supply voltage. Pulling the line to ground is considered which holds the SDAx line low to indicate to the trans- a logical zero and letting the line float is considered a mitter that the slave device has received the transmit- logical one. ted data and is ready to receive more. Figure25-11 shows a typical connection between two The transition of a data bit is always performed while processors configured as master and slave devices. the SCLx line is held low. Transitions that occur while The I2C bus can operate with one or more master the SCLx line is held high are used to indicate Start and devices and one or more slave devices. Stop bits. There are four potential modes of operation for a given If the master intends to write to the slave, then it repeat- device: edly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the • Master Transmit mode master device is in Master Transmit mode and the (master is transmitting data to a slave) slave is in Slave Receive mode. • Master Receive mode If the master intends to read from the slave, then it (master is receiving data from a slave) repeatedly receives a byte of data from the slave, and • Slave Transmit mode responds after each byte with an ACK bit. In this exam- (slave is transmitting data to a master) ple, the master device is in Master Receive mode and • Slave Receive mode the slave is Slave Transmit mode. (slave is receiving data from the master) On the last byte of data communicated, the master To begin communication, a master device starts out in device may end the transmission by sending a Stop bit. Master Transmit mode. The master device sends out a If the master device is in Receive mode, it sends the Start bit followed by the address byte of the slave it Stop bit in place of the last ACK bit. A Stop bit is indi- intends to communicate with. This is followed by a sin- cated by a low-to-high transition of the SDAx line while gle Read/Write bit, which determines whether the mas- the SCLx line is held high. ter intends to transmit to or receive data from the slave In some cases, the master may want to maintain con- device. trol of the bus and re-initiate another transmission. If If the requested slave exists on the bus, it will respond so, the master device may send another Start bit in with an Acknowledge bit, otherwise known as an ACK. place of the Stop bit or last ACK bit when it is in receive The master then continues in either Transmit mode or mode. Receive mode and the slave continues in the comple- The I2C bus specifies three message protocols; ment, either in Receive mode or Transmit mode, respectively. • Single message where a master writes data to a slave. A Start bit is indicated by a high-to-low transition of the SDAx line while the SCLx line is held high. Address and • Single message where a master reads data from data bytes are sent out, Most Significant bit (MSb) first. a slave. The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a out as a logical zero when it intends to write data to the combination of writes and reads, to one or more slave. slaves. DS41391D-page 242  2011 Microchip Technology Inc.

PIC16(L)F1826/27 When one device is transmitting a logical one, or letting 25.3.2 ARBITRATION the line float, and a second device is transmitting a log- Each master device must monitor the bus for Start and ical zero, or holding the line low, the first device can Stop bits. If the device detects that the bus is busy, it detect that the line is not a logical one. This detection, cannot begin a new message until the bus returns to an when used on the SCLx line, is called clock stretching. Idle state. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on However, two master devices may try to initiate a trans- the SDAx line, it is called arbitration. Arbitration mission on or about the same time. When this occurs, ensures that there is only one master device communi- the process of arbitration begins. Each transmitter cating at any single time. checks the level of the SDAx data line and compares it to the level that it expects to find. The first transmitter to 25.3.1 CLOCK STRETCHING observe that the two levels don't match, loses arbitra- tion, and must stop transmitting on the SDAx line. When a slave device has not completed processing data, it can delay the transfer of more data through the For example, if one transmitter holds the SDAx line to process of Clock Stretching. An addressed slave a logical one (lets it float) and a second transmitter device may hold the SCLx clock line low after receiving holds it to a logical zero (pulls it low), the result is that or sending a bit, indicating that it is not yet ready to con- the SDAx line will be low. The first transmitter then tinue. The master that is communicating with the slave observes that the level of the line is different than will attempt to raise the SCLx line in order to transfer expected and concludes that another transmitter is the next bit, but will detect that the clock line has not yet communicating. been released. Because the SCLx connection is The first transmitter to notice this difference is the one open-drain, the slave has the ability to hold that line low that loses arbitration and must stop driving the SDAx until it is ready to continue communicating. line. If this transmitter is also a master device, it also Clock stretching allows receivers that cannot keep up must stop driving the SCLx line. It then can monitor the with a transmitter to control the flow of incoming data. lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDAx line continues with it's original transmission. It can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less com- mon. If two master devices are sending a message to two dif- ferent slave devices at the address stage, the master sending the lower slave address always wins arbitra- tion. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a neces- sary process for proper multi-master support.  2011 Microchip Technology Inc. DS41391D-page 243

PIC16(L)F1826/27 25.4 I2C MODE OPERATION TABLE 25-2: I2C BUS TERMS All MSSPx I2C communication is byte oriented and TERM Description shifted out MSb first. Six SFR registers and 2 interrupt Transmitter The device which shifts data out flags interface the module with the PIC® microcon- onto the bus. troller and user software. Two pins, SDAx and SCLx, Receiver The device which shifts data in are exercised by the module to communicate with from the bus. other external I2C devices. Master The device that initiates a transfer, generates clock signals and termi- 25.4.1 BYTE FORMAT nates a transfer. All communication in I2C is done in 9-bit segments. A Slave The device addressed by the mas- byte is sent from a Master to a Slave or vice-versa, fol- ter. lowed by an Acknowledge bit sent back. After the 8th Multi-master A bus with more than one device falling edge of the SCLx line, the device outputting that can initiate data transfers. data on the SDAx changes that pin to an input and Arbitration Procedure to ensure that only one reads in an acknowledge value on the next clock master at a time controls the bus. pulse. Winning arbitration ensures that The clock signal, SCLx, is provided by the master. the message is not corrupted. Data is valid to change while the SCLx signal is low, Synchronization Procedure to synchronize the and sampled on the rising edge of the clock. Changes clocks of two or more devices on on the SDAx line while the SCLx line is high define the bus. special conditions on the bus, explained below. Idle No master is controlling the bus, 25.4.2 DEFINITION OF I2C TERMINOLOGY and both SDAx and SCLx lines are high. There is language and terminology in the description Active Any time one or more master of I2C communication that have definitions specific to devices are controlling the bus. I2C. That word usage is defined below and may be Addressed Slave device that has received a used in the rest of this document without explanation. This table was adapted from the Philips I2C Slave matching address and is actively being clocked by a master. specification. Matching Address byte that is clocked into a 25.4.3 SDAX AND SCLX PINS Address slave that matches the value Selection of any I2C mode with the SSPxEN bit set, stored in SSPxADD. forces the SCLx and SDAx pins to be open-drain. Write Request Slave receives a matching These pins should be set by the user to inputs by set- address with R/W bit clear, and is ready to clock in data. ting the appropriate TRIS bits. Read Request Master sends an address byte with Note: Data is tied to output zero when an I2C the R/W bit set, indicating that it mode is enabled. wishes to clock data out of the Slave. This data is the next and all 25.4.4 SDAX HOLD TIME following bytes until a Restart or The hold time of the SDAx pin is selected by the Stop. SDAHT bit of the SSPxCON3 register. Hold time is the Clock Stretching When a device on the bus hold time SDAx is held valid after the falling edge of SCLx. SCLx low to stall communication. Setting the SDAHT bit selects a longer 300ns mini- Bus Collision Any time the SDAx line is sampled mum hold time and may help on buses with large low by the module while it is out- capacitance. putting and expected high state. DS41391D-page 244  2011 Microchip Technology Inc.

PIC16(L)F1826/27 25.4.5 START CONDITION 25.4.7 RESTART CONDITION The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid. transition of SDAx from a high to a low state while A master can issue a Restart if it wishes to hold the SCLx line is high. A Start condition is always gener- bus after terminating the current transfer. A Restart ated by the master and signifies the transition of the has the same effect on the slave that a Start would, bus from an Idle to an Active state. Figure25-10 resetting all slave logic and preparing it to clock in an shows wave forms for Start and Stop conditions. address. The master may want to address the same or another slave. A bus collision can occur on a Start condition if the module samples the SDAx line low before asserting it In 10-bit Addressing Slave mode a Restart is required low. This does not conform to the I2C Specification that for the master to clock data out of the addressed states no bus collision can occur on a Start. slave. Once a slave has been fully addressed, match- ing both high and low address bytes, the master can 25.4.6 STOP CONDITION issue a Restart and the high address byte with the A Stop condition is a transition of the SDAx line from R/W bit set. The slave logic will then hold the clock low-to-high state while the SCLx line is high. and prepare to clock out data. After a full match with R/W clear in 10-bit mode, a prior Note: At least one SCLx low time must appear match flag is set and maintained. Until a Stop condi- before a Stop is valid, therefore, if the SDAx tion, a high address with R/W clear, or high address line goes low then high again while the SCLx match fails. line stays high, only the Start condition is detected. 25.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 25-12: I2C START AND STOP CONDITIONS SDAx SCLx S P Change of Change of Data Allowed Data Allowed Start Stop Condition Condition FIGURE 25-13: I2C RESTART CONDITION Sr Change of Change of Data Allowed Data Allowed Restart Condition  2011 Microchip Technology Inc. DS41391D-page 245

PIC16(L)F1826/27 25.4.9 ACKNOWLEDGE SEQUENCE 25.5 I2C SLAVE MODE OPERATION The 9th SCLx pulse for any transferred byte in I2C is The MSSPx Slave mode operates in one of four dedicated as an Acknowledge. It allows receiving modes selected in the SSPxM bits of SSPxCON1 reg- devices to respond back to the transmitter by pulling ister. The modes can be divided into 7-bit and 10-bit the SDAx line low. The transmitter must release con- Addressing mode. 10-bit Addressing modes operate trol of the line during this time to shift in the response. the same as 7-bit with some additional overhead for The Acknowledge (ACK) is an active-low signal, pull- handling the larger addresses. ing the SDAx line low indicated to the transmitter that Modes with Start and Stop bit interrupts operated the the device has received the transmitted data and is same as the other modes with SSPxIF additionally ready to receive more. getting set upon detection of a Start, Restart, or Stop The result of an ACK is placed in the ACKSTAT bit of condition. the SSPxCON2 register. 25.5.1 SLAVE MODE ADDRESSES Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to The SSPxADD register (Register25-6) contains the the transmitter. The ACKDT bit of the SSPxCON2 reg- Slave mode address. The first byte received after a ister is set/cleared to determine the response. Start or Restart condition is compared against the Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the AHEN and DHEN bits of the SSPxCON3 register are value is loaded into the SSPxBUF register and an clear. interrupt is generated. If the value does not match, the module goes Idle and no indication is given to the soft- There are certain conditions where an ACK will not be ware that anything happened. sent by the slave. If the BF bit of the SSPxSTAT regis- ter or the SSPxOV bit of the SSPxCON1 register are The SSPx Mask register (Register25-5) affects the set when a byte is received. address matching process. See Section25.5.9 “SSPx Mask Register” for more information. When the module is addressed, after the 8th falling edge of SCLx on the bus, the ACKTIM bit of the 25.5.1.1 I2C Slave 7-bit Addressing Mode SSPxCON3 register is set. The ACKTIM bit indicates In 7-bit Addressing mode, the LSb of the received data the acknowledge time of the active bus. The ACKTIM byte is ignored when determining if there is an address Status bit is only active when the AHEN bit or DHEN match. bit is enabled. 25.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCLx is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all 8 bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCLx is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communi- cation. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hard- ware will then acknowledge the read request and pre- pare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS41391D-page 246  2011 Microchip Technology Inc.

PIC16(L)F1826/27 25.5.2 SLAVE RECEPTION 25.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte Slave device reception with AHEN and DHEN set is clear, the R/W bit of the SSPxSTAT register is operate the same as without these options with extra cleared. The received address is loaded into the SSPx- interrupts and clock stretching added after the 8th fall- BUF register and acknowledged. ing edge of SCLx. These additional interrupts allow the slave software to decide whether it wants to ACK the When the overflow condition exists for a received receive address or data byte, rather than the hard- address, then not Acknowledge is given. An overflow ware. This functionality adds support for PMBus™ that condition is defined as either bit BF of the SSPxSTAT was not present on previous versions of this module. register is set, or bit SSPxOV of the SSPxCON1 regis- ter is set. The BOEN bit of the SSPxCON3 register This list describes the steps that need to be taken by modifies this operation. For more information see slave software to use these options for I2C commun- Register25-4. cation. Figure25-15 displays a module using both address and data holding. Figure25-16 includes the An MSSPx interrupt is generated for each transferred operation with the SEN bit of the SSPxCON2 register data byte. Flag bit, SSPxIF, must be cleared by soft- set. ware. 1. S bit of SSPxSTAT is set; SSPxIF is set if inter- When the SEN bit of the SSPxCON2 register is set, rupt on Start detect is enabled. SCLx will be held low (clock stretch) following each received byte. The clock must be released by setting 2. Matching address with R/W bit clear is clocked the CKP bit of the SSPxCON1 register, except in. SSPxIF is set and CKP cleared after the 8th sometimes in 10-bit mode. See Section25.2.3 “SPI falling edge of SCLx. Master Mode” for more detail. 3. Slave clears the SSPxIF. 4. Slave can look at the ACKTIM bit of the 25.5.2.1 7-bit Addressing Reception SSPxCON3 register to determine if the SSPxIF This section describes a standard sequence of events was after or before the ACK. for the MSSPx module configured as an I2C Slave in 5. Slave reads the address value from SSPxBUF, 7-bit Addressing mode. All decisions made by hard- clearing the BF flag. ware or software and their effect on reception. 6. Slave sets ACK value clocked out to the master Figure25-13 and Figure25-14 is used as a visual by setting ACKDT. reference for this description. 7. Slave releases the clock by setting CKP. This is a step by step process of what typically must 8. SSPxIF is set after an ACK, not after a NACK. be done to accomplish I2C communication. 9. If SEN=1 the slave hardware will stretch the 1. Start bit detected. clock after the ACK. 2. S bit of SSPxSTAT is set; SSPxIF is set if inter- 10. Slave clears SSPxIF. rupt on Start detect is enabled. Note: SSPxIF is still set after the 9th falling edge of 3. Matching address with R/W bit clear is received. SCLx even if there is no clock stretching and 4. The slave pulls SDAx low sending an ACK to the BF has been cleared. Only if NACK is sent master, and sets SSPxIF bit. to Master is SSPxIF not set 5. Software clears the SSPxIF bit. 11. SSPxIF set and CKP cleared after 8th falling 6. Software reads received address from SSPx- edge of SCLx for a received data byte. BUF clearing the BF flag. 12. Slave looks at ACKTIM bit of SSPxCON3 to 7. If SEN=1; Slave software sets CKP bit to determine the source of the interrupt. release the SCLx line. 13. Slave reads the received data from SSPxBUF 8. The master clocks out a data byte. clearing BF. 9. Slave drives SDAx low sending an ACK to the 14. Steps 7-14 are the same for each received data master, and sets SSPxIF bit. byte. 10. Software clears SSPxIF. 15. Communication is ended by either the slave 11. Software reads the received byte from SSPx- sending an ACK=1, or the master sending a BUF clearing BF. Stop condition. If a Stop is sent and Interrupt on 12. Steps 8-12 are repeated for all received bytes Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. from the Master. 13. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes Idle.  2011 Microchip Technology Inc. DS41391D-page 247

PIC16(L)F1826/27 FIGURE 25-14: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=0, DHEN=0) s endn 9th Bus Master sStop conditio 1 P SSPxIF set on falling edge of SCLx = K 9 C A D0 8 e Master eceiving Data D4D3D2D1 4567 eared by software SSPxOV set becausSSPxBUF is still full. ACK is not sent. e to R D5 3 Cl From Slav D7D6K 12 First byte of data is available in SSPxBUF C 9 A D0 8 D1 7 ad e a D2 6 ware F is r Receiving Dat D5D4D3 345 Cleared by soft SSPxBU D6 2 D7 1 K 9 C A 8 A1 7 2 6 A s s dre A3 5 d A ng A4 4 vi ecei A5 3 R A6 2 A7 1 S V F O x x xI x DA CL SP BF SP S S S S DS41391D-page 248  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-15: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) Bus Master sends Stop condition P SSPxIF set on 9thfalling edge of SCLx SCLx is not heldlow becauseACK=1 K C 9 A D0 8 e Receive Data D7D6D5D4D3D2D1 1234567 Cleared by software First byte of data is available in SSPxBUF SSPxOV set becausSSPxBUF is still full. ACK is not sent. CKP is written to 1 in software, releasing SCLx N E S K AC 9 D0 8 ’1 o ‘ Data D2D1 67 KP is set t oftware, Receive D7D6D5D4D3 12345 Clock is held low until C Cleared by software SSPxBUF is read CKP is written to ‘’ in s1releasing SCLx N E S K C A 9 0 = W R/ 8 A1 7 2 6 A s s dre A3 5 d e A A4 4 v ei ec A5 3 R 6 2 A A7 1 S V F O P SDAx SCLx SSPxI BF SSPx CK  2011 Microchip Technology Inc. DS41391D-page 249

PIC16(L)F1826/27 FIGURE 25-16: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=1) Master sendsStop condition =1 P No interruptafter not ACKfrom Slave CK 9 A are T to Received DataCKD7D6D5D4D3D2D1D0 912345678 Cleared by software a is read from SSPxBUF Slave softwsets ACKDnot ACK CKP set by software, SCLx is released ACKTIM set by hardwareon 8th falling edge of SCLx A at D D0 8 g Receiving Data D6D5D4D3D2D1 234567 SPxIF is set on h falling edge of CLx, after ACK When DHEN=1:CKP is cleared byhardware on 8th fallinedge of SCLx KTIM cleared bydware in 9th ng edge of SCLx D7 1 S9tS ACharrisi K 9 ce C n A e Axqu De es SCK s sA Master Releato slave for Receiving Address A7A6A5A4A3A2A1 12345678 If AHEN=:1SSPxIF is set Address isread from SSBUF Slave softwareclears ACKDT to ACK the receivedbyte When AHEN=1:CKP is cleared by hardwareand SCLx is stretched ACKTIM set by hardwareon 8th falling edge of SCLx S M SDAx SCLx SSPxIF BF ACKDT CKP ACKTI S P DS41391D-page 250  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-17: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN= 1, AHEN=1, DHEN=1) Master sendsStop condition P No interrupt afterif not ACKfrom Slave CKP is not clearedif not ACK K 9 C A D0 8 s d D1 7 enK Receive Data D6D5D4D3D2 23456 SSPxBUF can beread any time beforenext byte is loaded Slave snot AC Set by software,release SCLx D7 1 K C 9 A D0 8 F e CK sequence Receive Data D7D6D5D4D3D2D1 1245673 Cleared by software Received data isavailable on SSPxBU When DHEN = ;1on the 8th falling edgeof SCLx of a receiveddata byte, CKP is cleared ACKTIM is cleared by hardwaron 9th rising edge of SCLx A er releasesx to slave for ACK 9 stA aD MS 8 s R/W = 0 Receiving Address A6A5A4A3A2A1 342567 Received address is loaded into SSPxBUF Slave software clearACKDT to ACKthe received byte When AHEN=;1on the 8th falling edgeof SCLx of an addressbyte, CKP is cleared KTIM is set by hardware8th falling edge of SCLx A7 1 ACon S M TI SDAx SCLx SSPxIF BF ACKDT CKP ACK S P  2011 Microchip Technology Inc. DS41391D-page 251

PIC16(L)F1826/27 25.5.3 SLAVE TRANSMISSION 25.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set A master device can transmit a read request to a and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list SSPxSTAT register is set. The received address is below outlines what software for a slave will need to loaded into the SSPxBUF register, and an ACK pulse is do to accomplish a standard transmission. sent by the slave on the ninth bit. Figure25-17 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDAx and and the SCLx pin is held low (see Section25.5.6 SCLx. “Clock Stretching” for more detail). By stretching the 2. S bit of SSPxSTAT is set; SSPxIF is set if inter- clock, the master will be unable to assert another clock rupt on Start detect is enabled. pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by data. the Slave setting SSPxIF bit. The transmit data must be loaded into the SSPxBUF 4. Slave hardware generates an ACK and sets register which also loads the SSPxSR register. Then SSPxIF. the SCLx pin should be released by setting the CKP bit 5. SSPxIF bit is cleared by user. of the SSPxCON1 register. The eight data bits are 6. Software reads the received address from shifted out on the falling edge of the SCLx input. This SSPxBUF, clearing BF. ensures that the SDAx signal is valid during the SCLx 7. R/W is set so CKP was automatically cleared high time. after the ACK. The ACK pulse from the master-receiver is latched on 8. The slave software loads the transmit data into the rising edge of the ninth SCLx input pulse. This ACK SSPxBUF. value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data 9. CKP bit is set releasing SCLx, allowing the mas- transfer is complete. In this case, when the not ACK is ter to clock the data out of the slave. latched by the slave, the slave goes Idle and waits for 10. SSPxIF is set after the ACK response from the another occurrence of the Start bit. If the SDAx line was master is loaded into the ACKSTAT register. low (ACK), the next transmit data must be loaded into 11. SSPxIF bit is cleared. the SSPxBUF register. Again, the SCLx pin must be 12. The slave software checks the ACKSTAT bit to released by setting bit CKP. see if the master wants to clock out more data. An MSSPx interrupt is generated for each data transfer Note 1: If the master ACKs the clock will be byte. The SSPxIF bit must be cleared by software and stretched. the SSPxSTAT register is used to determine the status 2: ACKSTAT is the only bit updated on the of the byte. The SSPxIF bit is set on the falling edge of rising edge of SCLx (9th) rather than the the ninth clock pulse. falling. 25.5.3.1 Slave Mode Bus Collision 13. Steps 9-13 are repeated for each transmitted A slave receives a Read request and begins shifting byte. data out on the SDAx line. If a bus collision is detected 14. If the master sends a not ACK; the clock is not and the SBCDE bit of the SSPxCON3 register is set, held, but SSPxIF is still set. the BCLxIF bit of the PIRx register is set. Once a bus 15. The master sends a Restart condition or a Stop. collision is detected, the slave goes Idle and waits to be 16. The slave is no longer addressed. addressed again. User software can use the BCLxIF bit to handle a slave bus collision. DS41391D-page 252  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-18: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=0) sn do enditi er scon P stp ao MSt K C 9 A Transmitting Data D7D6D5D4D3D2D1D0 12345678 BF is automatically cleared after 8th fallingedge of SCLx CKP is not held for not ACK Masters not ACKis copied to ACKSTAT c ati m o ut A K AC 9 D0 8 1 D 7 a Dat D2 6 F Transmitting D7D6D5D4D3 12345 Cleared by software Data to transmit isloaded into SSPxBU Set by software c ati m o ut A 1CK =A 9 W eceiving AddressR/A5A4A3A2A1 345678 Received addressis read from SSPxBUF When R/W is setSCLx is alwaysheld low after 9th SCLxfalling edge R/W is copied from the matching address byte Indicates an address has been received R 6 A 2 7 A 1 S T F TA SDAx SCLx SSPxI BF CKP ACKS R/W D/A S P  2011 Microchip Technology Inc. DS41391D-page 253

PIC16(L)F1826/27 25.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt gen- eration after the 8th falling edge of a received match- ing address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure25-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. Bus starts Idle. 2. Master sends Start condition; the S bit of SSPx- STAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCLx line the CKP bit is cleared and SSPxIF interrupt is gen- erated. 4. Slave software clears SSPxIF. 5. Slave software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPx- BUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSPxCON2 register accordingly. 8. Slave sets the CKP bit releasing SCLx. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Slave software clears SSPxIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCLx pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmit- ted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCLx line to receive a Stop. DS41391D-page 254  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-19: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=1) endsdition sn aster op co P MSt K C A 9 0 D 8 Transmitting Data D5D4D3D2D1 34567 F is automatically eared after 8th fallingge of SCLx Master’s ACKresponse is copiedto SSPxSTAT CKP not cleared after not ACK D6 2 Bcled 7 D 1 c ati m o AutK C A 9 D0 8 1 a D 7 at D 2 DAxequence AutomaticTransmitting D7D6D5D4D3D 123456 Cleared by software Data to transmit isloaded into SSPxBUF Set by software,releases SCLx ACKTIM is clearedon 9th rising edge of SCLx Ss K Master releases to slave for ACK W=1AC 9 When R/W = ;1CKP is alwayscleared after ACK R/ 8 F U K Receiving Address A7A6A5A4A3A2A1 1234567 Received addressis read from SSPxB Slave clearsACKDT to ACaddress When AHEN = ;1CKP is cleared by hardwareafter receiving matchingaddress. ACKTIM is set on 8th fallingedge of SCLx S SDAx SCLx SPxIF BF CKDT STAT CKP KTIM R/W D/A S A K C C A A  2011 Microchip Technology Inc. DS41391D-page 255

PIC16(L)F1826/27 25.5.4 SLAVE MODE 10-BIT ADDRESS 25.5.5 10-BIT ADDRESSING WITH ADDRESS OR RECEPTION DATA HOLD This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or for the MSSPx module configured as an I2C Slave in DHEN set is the same as with 7-bit modes. The only 10-bit Addressing mode. difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the Figure25-19 is used as a visual reference for this CKP bit is cleared and SCLx line is held low are the description. same. Figure25-20 can be used as a reference of a This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set. slave software to accomplish I2C communication. Figure25-21 shows a standard waveform for a slave 1. Bus starts Idle. transmitter in 10-bit Addressing mode. 2. Master sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. 4. Slave sends ACK and SSPxIF is set. 5. Software clears the SSPxIF bit. 6. Software reads received address from SSPx- BUF clearing the BF flag. 7. Slave loads low address into SSPxADD, releasing SCLx. 8. Master sends matching low address byte to the Slave; UA bit is set. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPxIF is set. Note: If the low address does not match, SSPxIF and UA are still set so that the slave soft- ware can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPxIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCLx pulse; SSPxIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPxIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCLx. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS41391D-page 256  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-20: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) endsdition er scon P stp ao MSt K C 9 A 0 8 D ata D1 7 dBUF Receive D D6D5D4D3D2 23456 SCLx is held lowwhile CKP = 0 Data is reafrom SSPx Set by software,releasing SCLxyte D7 1 d b e v K cei Receive Data D6D5D4D3D2D1D0AC 92345678 Cleared by software Receive address isread from SSPxBUF When SEN = ;1CKP is cleared after9th falling edge of re D7 1 K C e A 9 Byt A0 8 DD s A es A1 7 Px Receive Second Addr A6A5A4A3A2 23456 Software updates SSand releases SCLx A7 1 K C 9 ve First Address Byte A0A9A811 345678 Set by hardwareon 9th falling edge If address matchesSSPxADD it is loaded into SSPxBUF When UA = ;1SCLx is held low ei 1 2 c e R 1 1 S SDAx SCLx SPxIF BF UA CKP S  2011 Microchip Technology Inc. DS41391D-page 257

PIC16(L)F1826/27 FIGURE 25-21: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=0) a Receive Data D7D6D5 12 Received datis read from SSPxBUF K C 9 A D0 8 D1 7 s D,se Receive Data D6D5D4D3D2 23456 eared by software Update of SSPxADclears UA and releaSCLx CKP with software ases SCLx D7 1 Cl Set rele A U K C 9 A 0 A 8 Receive Second Address Byte A6A5A4A3A2A1 345672 ed by software SSPxBUF can beread anytime beforethe next received byte ate to SSPxADD isallowed until 9thng edge of SCLx A7 1 Clear Updnot falli A U K C 9 A 0 = W 8 eive First Address ByteR/ A9A8110 34567 Set by hardwareon 9th falling edge Slave software clearsACKDT to ACKthe received byte If when AHEN=;1on the 8th falling edgeof SCLx of an addressbyte, CKP is cleared ACKTIM is set by hardwareon 8th falling edge of SCLx ec 1 2 R 1 1 S F T M SDAx SCLx SSPxI BF ACKD UA CKP ACKTI DS41391D-page 258  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN=0, AHEN=0, DHEN=0) ends dition er scon P MastStop K = 1 ds AC 9 en D0 8 K Master snot ACK Transmitting Data Byte D7D6D5D4D3D2D1 1723456 Data to transmit isloaded into SSPxBUF Set by softwarereleases SCLx Masters not ACis copied K C A 9 aster sends estart event Receive First Address Byte A9A811110 16782345Sr Set by hardware Received address isread from SSPxBUF High address is loadedback into SSPxADD When R/W = ;1CKP is cleared on9th falling edge of SCLx R/W is copied from thematching address byte MR K yte AC 9 eiving Second Address B A6A5A4A3A2A1A0 6782345 Cleared by software After SSPxADD isupdated, UA is clearedand SCLx is released c Re A7 1 K = 0 AC 9 W 8 Receiving AddressR/ A9A811110 1672345 Set by hardware SSPxBUF loadedwith received address UA indicates SSPxADDmust be updated Indicates an addresshas been received S AT T S SDAx SCLx SPxIF BF UA CKP ACK R/W D/A S  2011 Microchip Technology Inc. DS41391D-page 259

PIC16(L)F1826/27 25.5.6 CLOCK STRETCHING 25.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set, the holds the SCLx line low effectively pausing communi- clock is always stretched. This is the only time the cation. The slave may stretch the clock to allow more SCLx is stretched without CKP being cleared. SCLx is time to handle data or prepare a response for the mas- released immediately after a write to SSPxADD. ter device. A master device is not concerned with Note: Previous versions of the module did not stretching as anytime it is active on the bus and not stretch the clock if the second address byte transferring data it is stretching. Any stretching done did not match. by a slave is invisible to the master software and han- dled by the hardware that generates SCLx. 25.5.6.3 Byte NACKing The CKP bit of the SSPxCON1 register is used to con- When AHEN bit of SSPxCON3 is set; CKP is cleared trol stretching in software. Any time the CKP bit is by hardware after the 8th falling edge of SCLx for a cleared, the module will wait for the SCLx line to go received matching address byte. When DHEN bit of low and then hold it. Setting CKP will release SCLx SSPxCON3 is set; CKP is cleared after the 8th falling and allow more communication. edge of SCLx for received data. 25.5.6.1 Normal Clock Stretching Stretching after the 8th falling edge of SCLx allows the Following an ACK if the R/W bit of SSPxSTAT is set, a slave to look at the received address or data and read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data. allows the slave time to update SSPxBUF with data to 25.5.7 CLOCK SYNCHRONIZATION AND transfer to the master. If the SEN bit of SSPxCON2 is THE CKP BIT set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait is set by software and communication resumes. for the SCLx line to go low and then hold it. However, clearing the CKP bit will not assert the SCLx output Note 1: The BF bit has no effect on if the clock will low until the SCLx output is already sampled low. be stretched or not. This is different than Therefore, the CKP bit will not assert the SCLx line previous versions of the module that until an external I2C master device has already would not stretch the clock, clear CKP, if asserted the SCLx line. The SCLx output will remain SSPxBUF was read before the 9th falling low until the CKP bit is set and all other devices on the edge of SCLx. I2C bus have released SCLx. This ensures that a write 2: Previous versions of the module did not to the CKP bit will not violate the minimum high time stretch the clock for a transmission if requirement for SCLx (see Figure25-22). SSPxBUF was loaded before the 9th fall- ing edge of SCLx. It is now always cleared for read requests. FIGURE 25-23: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX DX ‚ – 1 SCLx Master device CKP asserts clock Master device releases clock WR SSPxCON1 DS41391D-page 260  2011 Microchip Technology Inc.

PIC16(L)F1826/27 25.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave The addressing procedure for the I2C bus is such that will prepare to receive the second byte as data, just as the first byte after the Start condition usually deter- it would in 7-bit mode. mines which device will be the slave addressed by the master device. The exception is the general call If the AHEN bit of the SSPxCON3 register is set, just address which can address all devices. When this as with any other address reception, the slave hard- address is used, all devices should, in theory, respond ware will stretch the clock after the 8th falling edge of with an acknowledge. SCLx. The slave must then set its ACKDT value and release the clock with communication progressing as it The general call address is a reserved address in the would normally. I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. Figure25-23 shows a general call reception sequence. FIGURE 25-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDAx General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPxIF BF (SSPxSTAT<0>) Cleared by software SSPxBUF is read GCEN (SSPxCON2<7>) ’1’ 25.5.9 SSPX MASK REGISTER An SSPx Mask (SSPxMSK) register (Register25-5) is available in I2C Slave mode as a mask for the value held in the SSPxSR register during an address comparison operation. A zero (‘0’) bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSPx operation until written with a mask value. The SSPx Mask register is active during: • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSPx mask has no effect during the reception of the first (high) byte of the address.  2011 Microchip Technology Inc. DS41391D-page 261

PIC16(L)F1826/27 25.6 I2C MASTER MODE 25.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the The master device generates all of the serial clock appropriate SSPxM bits in the SSPxCON1 register and pulses and the Start and Stop conditions. A transfer is by setting the SSPxEN bit. In Master mode, the SDAx ended with a Stop condition or with a Repeated Start and SCKx pins must be configured as inputs. The condition. Since the Repeated Start condition is also MSSP peripheral hardware will override the output the beginning of the next serial transfer, the I2C bus will not be released. driver TRIS controls when necessary to drive the pins low. In Master Transmitter mode, serial data is output through SDAx, while SCLx outputs the serial clock. The Master mode of operation is supported by interrupt first byte transmitted contains the slave address of the generation on the detection of the Start and Stop con- receiving device (7 bits) and the Read/Write (R/W) bit. ditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSPx module is disabled. Con- In this case, the R/W bit will be logic ‘0’. Serial data is trol of the I2C bus may be taken when the P bit is set, transmitted 8 bits at a time. After each byte is transmit- or the bus is Idle. ted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the In Firmware Controlled Master mode, user code end of a serial transfer. conducts all I2C bus operations based on Start and Stop bit condition detection. Start and Stop condition In Master Receive mode, the first byte transmitted con- detection is the only active circuitry in this mode. All tains the slave address of the transmitting device other communication is done by the user software (7bits) and the R/W bit. In this case, the R/W bit will be directly manipulating the SDAx and SCLx lines. logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. The following events will cause the SSPx Interrupt Flag Serial data is received via SDAx, while SCLx outputs bit, SSPxIF, to be set (SSPx interrupt, if enabled): the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is • Start condition detected transmitted. Start and Stop conditions indicate the • Stop condition detected beginning and end of transmission. • Data transfer byte transmitted/received A Baud Rate Generator is used to set the clock fre- • Acknowledge transmitted/received quency output on SCLx. See Section25.7 “Baud • Repeated Start generated Rate Generator” for more detail. Note 1: The MSSPx module, when configured in I2C Master mode, does not allow queue- ing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur 2: When in Master mode, Start/Stop detec- tion is masked and an interrupt is gener- ated when the SEN/PEN bit is cleared and the generation is complete. DS41391D-page 262  2011 Microchip Technology Inc.

PIC16(L)F1826/27 25.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure25-25). FIGURE 25-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX DX ‚ – 1 SCLx deasserted but slave holds SCLx allowed to transition high SCLx low (clock arbitration) SCLx BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCLx is sampled high, reload takes place and BRG starts its count BRG Reload 25.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not Idle. Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPxCON2 is disabled until the Start condition is complete.  2011 Microchip Technology Inc. DS41391D-page 263

PIC16(L)F1826/27 25.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended, CONDITION TIMING leaving the SDAx line held low and the Start condition is complete. To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the Note 1: If at the beginning of the Start condition, SDAx and SCLx pins are sampled high, the Baud Rate the SDAx and SCLx pins are already sam- Generator is reloaded with the contents of pled low, or if during the Start condition, SSPxADD<7:0> and starts its count. If SCLx and the SCLx line is sampled low before the SDAx are both sampled high when the Baud Rate SDAx line is driven low, a bus collision Generator times out (TBRG), the SDAx pin is driven occurs, the Bus Collision Interrupt Flag, low. The action of the SDAx being driven low while BCLxIF, is set, the Start condition is SCLx is high is the Start condition and causes the S bit aborted and the I2C module is reset into of the SSPxSTAT1 register to be set. Following this, its Idle state. the Baud Rate Generator is reloaded with the contents 2: The Philips I2C Specification states that a of SSPxADD<7:0> and resumes its count. When the bus collision cannot occur on a Start. Baud Rate Generator times out (TBRG), the SEN bit of the SSPxCON2 register will be automatically cleared FIGURE 25-26: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPxSTAT<3>) At completion of Start bit, SDAx = 1, hardware clears SEN bit SCLx = 1 and sets SSPxIF bit TBRG TBRG Write to SSPxBUF occurs here SDAx 1st bit 2nd bit TBRG SCLx S TBRG DS41391D-page 264  2011 Microchip Technology Inc.

PIC16(L)F1826/27 25.6.5 I2C MASTER MODE REPEATED SSPxCON2 register will be automatically cleared and START CONDITION TIMING the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is A Repeated Start condition occurs when the RSEN bit detected on the SDAx and SCLx pins, the S bit of the of the SSPxCON2 register is programmed high and the SSPxSTAT register will be set. The SSPxIF bit will not Master state machine is no longer active. When the be set until the Baud Rate Generator has timed out. RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is Note1: If RSEN is programmed while any other loaded and begins counting. The SDAx pin is released event is in progress, it will not take effect. (brought high) for one Baud Rate Generator count 2: A bus collision during the Repeated Start (TBRG). When the Baud Rate Generator times out, if condition occurs if: SDAx is sampled high, the SCLx pin will be deasserted • SDAx is sampled low when SCLx (brought high). When SCLx is sampled high, the Baud goes from low-to-high. Rate Generator is reloaded and begins counting. SDAx and SCLx must be sampled high for one TBRG. This • SCLx goes low before SDAx is action is then followed by assertion of the SDAx pin asserted low. This may indicate (SDAx=0) for one TBRG while SCLx is high. SCLx is that another master is attempting to asserted low. Following this, the RSEN bit of the transmit a data ‘1’. FIGURE 25-27: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here At completion of Start bit, SDAx = 1, SDAx = 1, hardware clears RSEN bit SCLx (no change) SCLx = 1 and sets SSPxIF TBRG TBRG TBRG SDAx 1st bit Write to SSPxBUF occurs here TBRG SCLx Sr TBRG Repeated Start  2011 Microchip Technology Inc. DS41391D-page 265

PIC16(L)F1826/27 25.6.6 I2C MASTER MODE TRANSMISSION 25.6.6.3 ACKSTAT Status Flag Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit of the SSPxCON2 other half of a 10-bit address is accomplished by simply register is cleared when the slave has sent an Acknowl- writing a value to the SSPxBUF register. This action will edge (ACK=0) and is set when the slave does not set the Buffer Full flag bit, BF and allow the Baud Rate Acknowledge (ACK=1). A slave sends an Acknowl- Generator to begin counting and start the next trans- edge when it has recognized its address (including a mission. Each bit of address/data will be shifted out general call), or when the slave has properly received onto the SDAx pin after the falling edge of SCLx is its data. asserted. SCLx is held low for one Baud Rate Genera- 25.6.6.4 Typical transmit sequence: tor rollover count (TBRG). Data should be valid before SCLx is released high. When the SCLx pin is released 1. The user generates a Start condition by setting high, it is held that way for TBRG. The data on the SDAx the SEN bit of the SSPxCON2 register. pin must remain stable for that duration and some hold 2. SSPxIF is set by hardware on completion of the time after the next falling edge of SCLx. After the eighth Start. bit is shifted out (the falling edge of the eighth clock), 3. SSPxIF is cleared by software. the BF flag is cleared and the master releases SDAx. 4. The MSSPx module will wait the required start This allows the slave device being addressed to time before any other operation takes place. respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received prop- 5. The user loads the SSPxBUF with the slave erly. The status of ACK is written into the ACKSTAT bit address to transmit. on the rising edge of the ninth clock. If the master 6. Address is shifted out the SDAx pin until all 8 bits receives an Acknowledge, the Acknowledge Status bit, are transmitted. Transmission begins as soon ACKSTAT, is cleared. If not, the bit is set. After the ninth as SSPxBUF is written to. clock, the SSPxIF bit is set and the master clock (Baud 7. The MSSPx module shifts in the ACK bit from Rate Generator) is suspended until the next data byte the slave device and writes its value into the is loaded into the SSPxBUF, leaving SCLx low and ACKSTAT bit of the SSPxCON2 register. SDAx unchanged (Figure25-27). 8. The MSSPx module generates an interrupt at After the write to the SSPxBUF, each bit of the address the end of the ninth clock cycle by setting the will be shifted out on the falling edge of SCLx until all SSPxIF bit. seven address bits and the R/W bit are completed. On 9. The user loads the SSPxBUF with eight bits of the falling edge of the eighth clock, the master will data. release the SDAx pin, allowing the slave to respond 10. Data is shifted out the SDAx pin until all 8 bits with an Acknowledge. On the falling edge of the ninth are transmitted. clock, the master will sample the SDAx pin to see if the 11. The MSSPx module shifts in the ACK bit from address was recognized by a slave. The status of the the slave device and writes its value into the ACK bit is loaded into the ACKSTAT Status bit of the ACKSTAT bit of the SSPxCON2 register. SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is 12. Steps 8-11 are repeated for all transmitted data set, the BF flag is cleared and the Baud Rate Generator bytes. is turned off until another write to the SSPxBUF takes 13. The user generates a Stop or Restart condition place, holding SCLx low and allowing SDAx to float. by setting the PEN or RSEN bits of the SSPxCON2 register. Interrupt is generated once 25.6.6.1 BF Status Flag the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all 8 bits are shifted out. 25.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL is set and the contents of the buf- fer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. DS41391D-page 266  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-28: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e ACKSTAT in SSPxCON2 = P ared by softwar K e C 9 Cl A > 6 2< D0 8 e N n slave, clear ACKSTAT bit SSPxCO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared by software service routifrom SSPx interrupt SSPxBUF is written by software om D7 1 xIF Fr ow SP = 0 SCLx held lwhile CPUsponds to S CK re = 0 A W 9 are R/W A1 ess and R/ 78 d by hardw ave A2 addr 6 eare PxCON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPxBUF written with 7-bit start transmit 12345 Cleared by software SSPxBUF written After Start condition, SEN cl Sn Write SStart co S T<0>) A T S x F SP SDAx SCLx SSPxI BF (S SEN PEN R/W  2011 Microchip Technology Inc. DS41391D-page 267

PIC16(L)F1826/27 25.6.7 I2C MASTER MODE RECEPTION 25.6.7.4 Typical Receive Sequence: Master mode reception is enabled by programming the 1. The user generates a Start condition by setting Receive Enable bit, RCEN bit of the SSPxCON2 the SEN bit of the SSPxCON2 register. register. 2. SSPxIF is set by hardware on completion of the Note: The MSSPx module must be in an Idle Start. state before the RCEN bit is set or the 3. SSPxIF is cleared by software. RCEN bit will be disregarded. 4. User writes SSPxBUF with the slave address to transmit and the R/W bit set. The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes 5. Address is shifted out the SDAx pin until all 8 bits (high-to-low/low-to-high) and data is shifted into the are transmitted. Transmission begins as soon SSPxSR. After the falling edge of the eighth clock, the as SSPxBUF is written to. receive enable flag is automatically cleared, the con- 6. The MSSPx module shifts in the ACK bit from tents of the SSPxSR are loaded into the SSPxBUF, the the slave device and writes its value into the BF flag bit is set, the SSPxIF flag bit is set and the Baud ACKSTAT bit of the SSPxCON2 register. Rate Generator is suspended from counting, holding 7. The MSSPx module generates an interrupt at SCLx low. The MSSPx is now in Idle state awaiting the the end of the ninth clock cycle by setting the next command. When the buffer is read by the CPU, SSPxIF bit. the BF flag bit is automatically cleared. The user can 8. User sets the RCEN bit of the SSPxCON2 regis- then send an Acknowledge bit at the end of reception ter and the Master clocks in a byte from the slave. by setting the Acknowledge Sequence Enable, ACKEN 9. After the 8th falling edge of SCLx, SSPxIF and bit of the SSPxCON2 register. BF are set. 25.6.7.1 BF Status Flag 10. Master clears SSPxIF and reads the received byte from SSPxUF, clears BF. In receive operation, the BF bit is set when an address 11. Master sets ACK value sent to slave in ACKDT or data byte is loaded into SSPxBUF from SSPxSR. It bit of the SSPxCON2 register and initiates the is cleared when the SSPxBUF register is read. ACK by setting the ACKEN bit. 25.6.7.2 SSPxOV Status Flag 12. Masters ACK is clocked out to the Slave and SSPxIF is set. In receive operation, the SSPxOV bit is set when 8 bits are received into the SSPxSR and the BF flag bit is 13. User clears SSPxIF. already set from a previous reception. 14. Steps 8-13 are repeated for each received byte from the slave. 25.6.7.3 WCOL Status Flag 15. Master sends a not ACK or Stop to end If the user writes the SSPxBUF when a receive is communication. already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). DS41391D-page 268  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-29: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) pt Write to SSPxCON2<4>to start Acknowledge sequenceSDAx = ACKDT (SSPxCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from MasterMaster configured as a receiverSDAx = ACKDT = SDAx = ACKDT = 10by programming SSPxCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten hereom Slavenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1ACKD0W ACK Bus masterACK is not sentterminatestransfer9967895876512343124PSet SSPxIF at endData shifted in on falling edge of CLKof receiveSet SSPxIF interruat end of Acknow-Set SSPxIF interruptSet SSPxIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared by softwareCleared by softwareCleared by software(SSPxSTAT<4>)Cleared insoftwareand SSPxIF Last bit is shifted into SSPxSR andcontents are unloaded into SSPxBUF SSPxOV is set becauseSSPxBUF is still full Master configured as a receiverRCEN clearedACK from MasterRCEN clearedSDAx = ACKDT = automatically0by programming SSPxCON2<3> (RCEN = )automatically1 K fr R/ 8 AC A1 7 e, Write to SSPxCON2<0>(SEN = ),1begin Start condition SEN = 0Write to SSPxBUF occurs herstart XMIT Transmit Address to Slave A7A6A5A4A3A2SDAx 631245SCLxS SSPxIF Cleared by softwareSDAx = , SCLx = 01while CPU responds to SSPxIF BF (SSPxSTAT<0>) SSPxOV ACKEN RCEN  2011 Microchip Technology Inc. DS41391D-page 269

PIC16(L)F1826/27 25.6.8 ACKNOWLEDGE SEQUENCE 25.6.9 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDAx pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPxCON2 register. At the end of a SSPxCON2 register. When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDAx pin. If the user wishes to the master will assert the SDAx line low. When the generate an Acknowledge, then the ACKDT bit should SDAx line is sampled low, the Baud Rate Generator is be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate before starting an Acknowledge sequence. The Baud Generator times out, the SCLx pin will be brought high Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count) (TBRG) and the SCLx pin is deasserted (pulled high). later, the SDAx pin will be deasserted. When the SDAx When the SCLx pin is sampled high (clock arbitration), pin is sampled high while SCLx is high, the P bit of the the Baud Rate Generator counts for TBRG. The SCLx pin SSPxSTAT register is set. A TBRG later, the PEN bit is is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure25-30). matically cleared, the Baud Rate Generator is turned off 25.6.9.1 WCOL Status Flag and the MSSPx module then goes into Idle mode (Figure25-29). If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the 25.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does If the user writes the SSPxBUF when an Acknowledge not occur). sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 25-30: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPxCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDAx D0 ACK SCLx 8 9 SSPxIF Cleared in SSPxIF set at Cleared in software the end of receive software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. DS41391D-page 270  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 25-31: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPxCON2, SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG set PEN after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Falling edge of PEN bit (SSPxCON2<2>) is cleared by 9th clock hardware and the SSPxIF bit is set TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 25.6.10 SLEEP OPERATION 25.6.13 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C slave module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSPx interrupt is enabled). tion. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master 25.6.11 EFFECTS OF A RESET outputs a ‘1’ on SDAx, by letting SDAx float high and A Reset disables the MSSPx module and terminates another master asserts a ‘0’. When the SCLx pin floats the current transfer. high, data should be stable. If the expected data on SDAx is a ‘1’ and the data sampled on the SDAx pin is 25.6.12 MULTI-MASTER MODE ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF and reset In Multi-Master mode, the interrupt generation on the the I2C port to its Idle state (Figure25-31). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSPx module is disabled. Control of the I2C bus may cleared, the SDAx and SCLx lines are deasserted and be taken when the P bit of the SSPxSTAT register is the SSPxBUF can be written to. When the user ser- set, or the bus is Idle, with both the S and P bits clear. vices the bus collision Interrupt Service Routine and if When the bus is busy, enabling the SSPx interrupt will the I2C bus is free, the user can resume communica- generate the interrupt when the Stop condition occurs. tion by asserting a Start condition. In multi-master operation, the SDAx line must be If a Start, Repeated Start, Stop or Acknowledge condi- monitored for arbitration to see if the signal level is the tion was in progress when the bus collision occurred, the expected output level. This check is performed by condition is aborted, the SDAx and SCLx lines are deas- hardware with the result placed in the BCLxIF bit. serted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus col- The states where arbitration can be lost are: lision Interrupt Service Routine and if the I2C bus is free, • Address Transfer the user can resume communication by asserting a Start • Data Transfer condition. • A Start Condition The master will continue to monitor the SDAx and SCLx • A Repeated Start Condition pins. If a Stop condition occurs, the SSPxIF bit will be set. • An Acknowledge Condition A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared.  2011 Microchip Technology Inc. DS41391D-page 271

PIC16(L)F1826/27 FIGURE 25-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDAx. While SCLx is high, Data changes SDAx line pulled low data does not match what is driven while SCLx = 0 by another source by the master. Bus collision has occurred. SDAx released by master SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF DS41391D-page 272  2011 Microchip Technology Inc.

PIC16(L)F1826/27 25.6.13.1 Bus Collision During a Start If the SDAx pin is sampled low during this count, the Condition BRG is reset and the SDAx line is asserted early (Figure25-34). If, however, a ‘1’ is sampled on the During a Start condition, a bus collision occurs if: SDAx pin, the SDAx pin is asserted low at the end of a) SDAx or SCLx are sampled low at the beginning the BRG count. The Baud Rate Generator is then of the Start condition (Figure25-32). reloaded and counts down to zero; if the SCLx pin is b) SCLx is sampled low before SDAx is asserted sampled as ‘0’ during this time, a bus collision does not low (Figure25-33). occur. At the end of the BRG count, the SCLx pin is asserted low. During a Start condition, both the SDAx and the SCLx pins are monitored. Note: The reason that bus collision is not a fac- tor during a Start condition is that no two If the SDAx pin is already low, or the SCLx pin is bus masters can assert a Start condition already low, then all of the following occur: at the exact same time. Therefore, one • the Start condition is aborted, master will always assert SDAx before the • the BCLxIF flag is set and other. This condition does not cause a bus • the MSSPx module is reset to its Idle state collision because the two masters must be (Figure25-32). allowed to arbitrate the first address fol- The Start condition begins with the SDAx and SCLx lowing the Start condition. If the address is pins deasserted. When the SDAx pin is sampled high, the same, arbitration must be allowed to the Baud Rate Generator is loaded and counts down. If continue into the data portion, Repeated the SCLx pin is sampled low while SDAx is high, a bus Start or Stop conditions. collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 25-33: BUS COLLISION DURING START CONDITION (SDAX ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDAx = 1, SCLx = 1 SSPx module reset into Idle state. SEN SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because BCLxIF SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared by software S SSPxIF SSPxIF and BCLxIF are cleared by software  2011 Microchip Technology Inc. DS41391D-page 273

PIC16(L)F1826/27 FIGURE 25-34: BUS COLLISION DURING START CONDITION (SCLX=0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start SCLx sequence if SDAx = 1, SCLx = 1 SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared by software S ’0’ ’0’ SSPxIF ’0’ ’0’ FIGURE 25-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Set SSPxIF Less than TBRG TBRG SDAx SDAx pulled low by other master. Reset BRG and assert SDAx. SCLx S SCLx pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 BCLxIF ’0’ S SSPxIF SDAx = 0, SCLx = 1, Interrupts cleared set SSPxIF by software DS41391D-page 274  2011 Microchip Technology Inc.

PIC16(L)F1826/27 25.6.13.2 Bus Collision During a Repeated If SDAx is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure25-35). If SDAx is sampled high, the BRG is reloaded and During a Repeated Start condition, a bus collision begins counting. If SDAx goes from high-to-low before occurs if: the BRG times out, no bus collision occurs because no a) A low level is sampled on SDAx when SCLx two masters can assert SDAx at exactly the same time. goes from low level to high level. If SCLx goes from high-to-low before the BRG times b) SCLx goes low before SDAx is asserted low, out and SDAx has not already been asserted, a bus indicating that another master is attempting to collision occurs. In this case, another master is transmit a data ‘1’. attempting to transmit a data ‘1’ during the Repeated When the user releases SDAx and the pin is allowed to Start condition, see Figure25-36. float high, the BRG is loaded with SSPxADD and If, at the end of the BRG time-out, both SCLx and SDAx counts down to zero. The SCLx pin is then deasserted are still high, the SDAx pin is driven low and the BRG and when sampled high, the SDAx pin is sampled. is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. FIGURE 25-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared by software S ’0’ SSPxIF ’0’ FIGURE 25-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx SCLx goes low before SDAx, BCLxIF set BCLxIF. Release SDAx and SCLx. Interrupt cleared by software RSEN ’0’ S SSPxIF  2011 Microchip Technology Inc. DS41391D-page 275

PIC16(L)F1826/27 25.6.13.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low. Condition When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPxADD and a) After the SDAx pin has been deasserted and counts down to 0. After the BRG times out, SDAx is allowed to float high, SDAx is sampled low after sampled. If SDAx is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCLx pin is deasserted, SCLx is drive a data ‘0’ (Figure25-37). If the SCLx pin is sampled low before SDAx goes high. sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure25-38). FIGURE 25-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDAx sampled low after TBRG, set BCLxIF SDAx SDAx asserted low SCLx PEN BCLxIF P ’0’ SSPxIF ’0’ FIGURE 25-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes low before SDAx goes high, Assert SDAx set BCLxIF SCLx PEN BCLxIF P ’0’ SSPxIF ’0’ DS41391D-page 276  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 25-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE(1) 88 PIE4(1) — — — — — — BCL2IE SSP2IE 90 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 91 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF(1) 92 PIR4(1) — — — — — — BCL2IF SSP2IF 94 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 SSPxADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 283 SSPxBUF MSSPx Receive Buffer/Transmit Register 235* SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 280 SSPxCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 281 SSPxCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 282 SSPxMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 283 SSPxSTAT SMP CKE D/A P S R/W UA BF 279 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode. * Page provides register information. Note 1: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 277

PIC16(L)F1826/27 25.7 BAUD RATE GENERATOR module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSPx is The MSSPx module has a Baud Rate Generator avail- being operated in. able for clock generation in both I2C and SPI Master Table25-4 demonstrates clock rates based on modes. The Baud Rate Generator (BRG) reload value instruction cycles and the BRG value loaded into is placed in the SSPxADD register (Register25-6). SSPxADD. When a write occurs to SSPxBUF, the Baud Rate Gen- erator will automatically begin counting down. EQUATION 25-1: Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will FOSC remain in its last state. FCLOCK = ------------------------------------------------- SSPxADD+14 An internal signal “Reload” in Figure25-39 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the FIGURE 25-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPxM<3:0> SSPxADD<7:0> SSPxM<3:0> Reload Reload SCLx Control SSPxCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 25-4: MSSPX CLOCK RATE W/BRG FCLOCK FOSC FCY BRG Value (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz(1) 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. DS41391D-page 278  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 25-1: SSPxSTAT: SSPx STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I 2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I 2 C™ mode only: 1 = Enable input logic so that thresholds are compliant with SM bus™ specification 0 = Disable SM bus™ specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I 2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty  2011 Microchip Technology Inc. DS41391D-page 279

PIC16(L)F1826/27 REGISTER 25-2: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 WCOL SSPxOV SSPxEN CKP SSPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPxOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software). 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPxEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I 2 C Slave mode: SCLx release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C Master mode: Unused in this mode bit 3-0 SSPxM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))(5) 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: When enabled, the SDAx and SCLx pins must be configured as inputs. 4: SSPxADD values of 0, 1 or 2 are not supported for I2C Mode. 5: SSPxADD value of ‘0’ is not supported. Use SSPxM = 0000 instead. DS41391D-page 280  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 25-3: SSPxCON2: SSPx CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKx Release Control: 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).  2011 Microchip Technology Inc. DS41391D-page 281

PIC16(L)F1826/27 REGISTER 25-4: SSPxCON3: SSPx CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCLx clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCLx clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPxOV bit of the SSPxCON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPxOV bit only if the BF bit = 0. 0 = SSPxBUF is only updated when SSPxOV is clear bit 3 SDAHT: SDAx Hold Time Selection bit (I2C mode only) 1 = Minimum of 300ns hold time on SDAx after the falling edge of SCLx 0 = Minimum of 100ns hold time on SDAx after the falling edge of SCLx bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the BCLxIF bit of the PIR2 register is set, and bus goes Idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the SSPxCON1 register will be cleared and the SCLx will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCLx is held low. 0 = Data holding is disabled Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still set when a new byte is received and BF=1, but hardware continues to write the most recent byte to SSPxBUF. 2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. 3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. DS41391D-page 282  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 25-5: SSPxMSK: SSPx MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPxM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 25-6: SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCLx pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pat- tern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode — Least Significant Address byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.  2011 Microchip Technology Inc. DS41391D-page 283

PIC16(L)F1826/27 NOTES: DS41391D-page 284  2011 Microchip Technology Inc.

PIC16(L)F1826/27 26.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer • Half-duplex synchronous master independent of device program execution. The • Half-duplex synchronous slave EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous Interface (SCI), can be configured as a full-duplex modes asynchronous system or half-duplex synchronous • Sleep operation system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT The EUSART module implements the following terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems: with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate circuits, serial EEPROMs or other microcontrollers. • Wake-up on Break reception These devices typically do not have internal clocks for • 13-bit Break character transmit baud rate generation and require the external clock signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and receiver are shown in Figure26-1 and Figure26-2. FIGURE 26-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREG Register TXIF 8 MSb LSb TX/CK pin (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT SPEN Baud Rate Generator FOSC ÷ n TX9 BRG16 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 X 0 0 0 SPBRGH SPBRGL BRGH X 1 1 0 0 BRG16 X 1 0 1 0  2011 Microchip Technology Inc. DS41391D-page 285

PIC16(L)F1826/27 FIGURE 26-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN OERR RCIDL RX/DT pin MSb RSR Register LSb Panind BCuoffnetrrol DReactaovery Stop (8) 7 • • • 1 0 START Baud Rate Generator FOSC RX9 ÷ n BRG16 n + 1 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 FIFO SPBRGH SPBRGL BRGH X 1 1 0 0 FERR RX9D RCREG Register BRG16 X 1 0 1 0 8 Data Bus RCIF Interrupt RCIE The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These registers are detailed in Register26-1, Register26-2 and Register26-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output. DS41391D-page 286  2011 Microchip Technology Inc.

PIC16(L)F1826/27 26.1 EUSART Asynchronous Mode 26.1.1.2 Transmitting Data The EUSART transmits and receives data using the A transmission is initiated by writing a character to the standard non-return-to-zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the implemented with two levels: a VOH mark state which previous character has been completely flushed from represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXREG is immediately represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains consecutively transmitted data bits of the same value all or part of a previous character, the new character stay at the output level of that bit without returning to a data is held in the TXREG until the Stop bit of the neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending transmission port idles in the mark state. Each character character in the TXREG is then transferred to the TSR transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits or nine data bits and is always terminated by one or and Stop bit sequence commences immediately more Stop bits. The Start bit is always a space and the following the transfer of the data to the TSR from the Stop bits are always marks. The most common data TXREG. format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud 26.1.1.3 Transmit Data Polarity Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table26-5 The polarity of the transmit data can be controlled with for examples of baud rate configurations. the SCKP bit of the BAUDCON register. The default state of this bit is ‘0’ which selects high true transmit idle The EUSART transmits and receives the LSb first. The and data bits. Setting the SCKP bit to ‘1’ will invert the EUSART’s transmitter and receiver are functionally transmit data resulting in low true idle and data bits. The independent, but share the same data format and baud SCKP bit controls transmit data polarity in rate. Parity is not supported by the hardware, but can Asynchronous mode only. In Synchronous mode, the be implemented in software and stored as the ninth SCKP bit has a different function. See Section26.4.1.2 data bit. “Clock Polarity”. 26.1.1 EUSART ASYNCHRONOUS 26.1.1.4 Transmit Interrupt Flag TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set The EUSART transmitter block diagram is shown in whenever the EUSART transmitter is enabled and no Figure26-1. The heart of the transmitter is the serial character is being held for transmission in the TXREG. Transmit Shift Register (TSR), which is not directly In other words, the TXIF bit is only clear when the TSR accessible by software. The TSR obtains its data from is busy with a character and a new character has been the transmit buffer, which is the TXREG register. queued for transmission in the TXREG. The TXIF flag bit 26.1.1.1 Enabling the Transmitter is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following The EUSART transmitter is enabled for asynchronous the write execution. Polling TXIF immediately following operations by configuring the following three control the TXREG write will return invalid results. The TXIF bit bits: is read-only, it cannot be set or cleared by software. • TXEN = 1 The TXIF interrupt can be enabled by setting the TXIE • SYNC = 0 interrupt enable bit of the PIE1 register. However, the • SPEN = 1 TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. All other EUSART control bits are assumed to be in their default state. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the Setting the TXEN bit of the TXSTA register enables the TXIE interrupt enable bit upon writing the last character transmitter circuitry of the EUSART. Clearing the SYNC of the transmission to the TXREG. bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set.  2011 Microchip Technology Inc. DS41391D-page 287

PIC16(L)F1826/27 26.1.1.5 TSR Status 26.1.1.7 Asynchronous Transmission Set-up: The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRGL register pair and status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired TRMT bit is set when the TSR register is empty and is baud rate (see Section26.3 “EUSART Baud cleared when a character is transferred to the TSR Rate Generator (BRG)”). register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit. No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 con- poll this bit to determine the TSR status. trol bit. A set ninth data bit will indicate that the 8 Note: The TSR register is not mapped in data Least Significant data bits are an address when memory, so it is not available to the user. the receiver is set for address detection. 4. Set SCKP bit if inverted transmit is desired. 26.1.1.6 Transmitting 9-Bit Characters 5. Enable the transmission by setting the TXEN The EUSART supports 9-bit character transmissions. control bit. This will cause the TXIF interrupt bit When the TX9 bit of the TXSTA register is set, the to be set. EUSART will shift 9 bits out for each character transmit- 6. If interrupts are desired, set the TXIE interrupt ted. The TX9D bit of the TXSTA register is the ninth, enable bit of the PIE1 register. An interrupt will and Most Significant, data bit. When transmitting 9-bit occur immediately provided that the GIE and data, the TX9D data bit must be written before writing PEIE bits of the INTCON register are also set. the 8 Least Significant bits into the TXREG. All nine bits 7. If 9-bit transmission is selected, the ninth bit of data will be transferred to the TSR shift register should be loaded into the TX9D data bit. immediately after the TXREG is written. 8. Load 8-bit data into the TXREG register. This A special 9-bit Address mode is available for use with will start the transmission. multiple receivers. See Section26.1.2.7 “Address Detection” for more information on the address mode. FIGURE 26-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) FIGURE 26-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Transmit Buffer Reg. Empty Flag) 1 TCY TRMT bit Word 1 Word 2 (Transmit Shift Transmit Shift Reg. Transmit Shift Reg. Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. DS41391D-page 288  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(1) CCP2SEL(1) P1DSEL P1CSEL CCP1SEL 119 APFCON1 — — — — — — — TXCKSEL 119 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 296 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 91 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 295 SPBRGL BRG<7:0> 297* SPBRGH BRG<15:8> 297* TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 TXREG EUSART Transmit Data Register 287* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 294 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission. * Page provides register information. Note 1: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 289

PIC16(L)F1826/27 26.1.2 EUSART ASYNCHRONOUS 26.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit, systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data Figure26-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts the baud rate, whereas the serial Receive Shift character reception, without generating an error, and Register (RSR) operates at the bit rate. When all 8 or 9 resumes looking for the falling edge of the Start bit. If bits of the character have been shifted in, they are the Start bit zero verification succeeds then the data immediately transferred to a two character recovery circuit counts a full bit time to the center of the First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. start of a third character before software must start This repeats until all data bits have been sampled and servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always Access to the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this 26.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this character. See Section26.1.2.4 “Receive Framing The EUSART receiver is enabled for asynchronous Error” for more information on framing errors. operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have • CREN = 1 been received, the character in the RSR is transferred • SYNC = 0 to the EUSART receive FIFO and the RCIF interrupt • SPEN = 1 flag bit of the PIR1 register is set. The top character in All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the their default state. RCREG register. Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun of the TXSTA register configures the EUSART for condition is cleared. See Section26.1.2.5 asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more RCSTA register enables the EUSART. The programmer information on overrun errors. must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. 26.1.2.3 Receive Interrupts Note: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is cleared for the receiver to function. an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: • RCIE interrupt enable bit of the PIE1 register • PEIE peripheral interrupt enable bit of the INTCON register • GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS41391D-page 290  2011 Microchip Technology Inc.

PIC16(L)F1826/27 26.1.2.4 Receive Framing Error 26.1.2.7 Address Detection Each character in the receive FIFO buffer has a A special Address Detection mode is available for use corresponding framing error Status bit. A framing error when multiple receivers share the same transmission indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA FERR bit of the RCSTA register. The FERR bit register. represents the status of the top unread character in the Address detection requires 9-bit character reception. receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters before reading the RCREG. with the ninth data bit set will be transferred to the The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt unread character in the receive FIFO. A framing error bit. All other characters will be ignored. (FERR = 1) does not preclude reception of additional Upon receiving an address character, user software characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon Reading the next character from the FIFO buffer will address match, user software must disable address advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next corresponding framing error. Stop bit occurs. When user software detects the end of The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit. affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. 26.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 26.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG.  2011 Microchip Technology Inc. DS41391D-page 291

PIC16(L)F1826/27 26.1.2.8 Asynchronous Reception Set-up: 26.1.2.9 9-bit Address Detection Mode Set-up 1. Initialize the SPBRGH, SPBRGL register pair This mode would typically be used in RS-485 systems. and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section26.3 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRGL register pair 2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the 3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section26.3 “EUSART The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”). operation. 2. Clear the ANSEL bit for the RX pin (if applicable). 4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit. PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous INTCON register. operation. 5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the 6. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the 7. The RCIF interrupt flag bit will be set when a INTCON register. character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit. receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN the RCIE interrupt enable bit was also set. bit. 8. Read the RCSTA register to get the error flags 7. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 9. Get the received 8 Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit register. was also set. 10. If an overrun occurred, clear the OERR flag by 9. Read the RCSTA register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 10. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. FIGURE 26-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg. Word 1 Word 2 RCREG RCREG RCIDL Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS41391D-page 292  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 26-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(1) CCP2SEL(1) P1DSEL P1CSEL CCP1SEL 119 APFCON1 — — — — — — — TXCKSEL 119 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 296 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 91 RCREG EUSART Receive Data Register 290* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 295 SPBRGL BRG<7:0> 297* SPBRGH BRG<15:8> 297* TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 294 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Reception. * Page provides register information. Note 1: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 293

PIC16(L)F1826/27 26.2 Clock Accuracy with The first (preferred) method uses the OSCTUNE Asynchronous Operation register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution The factory calibrates the internal oscillator block out- changes to the system clock source. See Section5.2.2 put (INTOSC). However, the INTOSC frequency may “Internal Clock Sources” for more information. drift as VDD or temperature changes, and this directly The other method adjusts the value in the Baud Rate affects the asynchronous baud rate. Two methods may Generator. This can be done automatically with the be used to adjust the baud rate clock, but both require Auto-Baud Detect feature (see Section26.3.1 a reference clock source of some kind. “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. REGISTER 26-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS41391D-page 294  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 26-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.  2011 Microchip Technology Inc. DS41391D-page 295

PIC16(L)F1826/27 REGISTER 26-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS41391D-page 296  2011 Microchip Technology Inc.

PIC16(L)F1826/27 26.3 EUSART Baud Rate Generator EXAMPLE 26-1: CALCULATING BAUD (BRG) RATE ERROR The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. FOSC Desired Baud Rate = ------------------------------------------------------------------------ By default, the BRG operates in 8-bit mode. Setting the 64[SPBRGH:SPBRGL]+1 BRG16 bit of the BAUDCON register selects 16-bit Solving for SPBRGH:SPBRGL: mode. FOSC The SPBRGH, SPBRGL register pair determines the --------------------------------------------- Desired Baud Rate period of the free running baud rate timer. In X = ---------------------------------------------–1 64 Asynchronous mode the multiplier of the baud rate 16000000 period is determined by both the BRGH bit of the TXSTA ------------------------ 9600 register and the BRG16 bit of the BAUDCON register. In = ------------------------–1 64 Synchronous mode, the BRGH bit is ignored. = 25.042 = 25 Table26-3 contains the formulas for determining the baud rate. Example26-1 provides a sample calculation 16000000 Calculated Baud Rate = --------------------------- for determining the baud rate and baud rate error. 6425+1 Typical baud rates and error values for various = 9615 asynchronous modes have been computed for your convenience and are shown in Table26-3. It may be Calc. Baud Rate–Desired Baud Rate Error = -------------------------------------------------------------------------------------------- advantageous to use the high baud rate (BRGH = 1), Desired Baud Rate or the 16-bit BRG (BRG16 = 1) to reduce the baud rate 9615–9600 error. The 16-bit BRG mode is used to achieve slow = ---------------------------------- = 0.16% 9600 baud rates for fast oscillator frequencies. Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock.  2011 Microchip Technology Inc. DS41391D-page 297

PIC16(L)F1826/27 TABLE 26-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair TABLE 26-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 296 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 295 SPBRGL BRG<7:0> 297* SPBRGH BRG<15:8> 297* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 294 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator. * Page provides register information. DS41391D-page 298  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5  2011 Microchip Technology Inc. DS41391D-page 299

PIC16(L)F1826/27 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — DS41391D-page 300  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —  2011 Microchip Technology Inc. DS41391D-page 301

PIC16(L)F1826/27 26.3.1 AUTO-BAUD DETECT and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. Note1: If the WUE bit is set with the ABDEN bit, In the Auto-Baud Detect (ABD) mode, the clock to the auto-baud detection will occur on the byte BRG is reversed. Rather than the BRG clocking the following the Break character (see incoming RX signal, the RX signal is timing the BRG. Section26.3.3 “Auto-Wake-up on The Baud Rate Generator is used to time the period of Break”). a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the that it has five rising edges including the Stop bit edge. incoming character baud rate is within the range of the selected BRG clock source. Setting the ABDEN bit of the BAUDCON register starts Some combinations of oscillator frequency the auto-baud calibration sequence (Figure26-6). and EUSART baud rates are not possible. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of 3: During the auto-baud process, the the receive line, after the Start bit, the SPBRG begins auto-baud counter starts counting at 1. counting up using the BRG counter clock as shown in Upon completion of the auto-baud Table26-6. The fifth rising edge will occur on the RX pin sequence, to achieve maximum accuracy, at the end of the eighth bit period. At that time, an subtract 1 from the SPBRGH:SPBRGL accumulated value totaling the proper BRG period is register pair. left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag TABLE 26-6: BRG COUNTER CLOCK RATES is set. The value in the RCREG needs to be read to BRG Base BRG ABD clear the RCIF interrupt. RCREG content should be BRG16 BRGH Clock Clock discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the 0 0 FOSC/64 FOSC/512 SPBRGL register did not overflow by checking for 00h 0 1 FOSC/16 FOSC/128 in the SPBRGH register. 1 0 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table26-6. During ABD, 1 1 FOSC/4 FOSC/32 both the SPBRGH and SPBRGL registers are used as Note: During the ABD sequence, SPBRGL and a 16-bit counter, independent of the BRG16 bit setting. SPBRGH registers are both used as a 16-bit While calibrating the baud rate period, the SPBRGH counter, independent of BRG16 setting. FIGURE 26-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL XXh 1Ch SPBRGH XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. DS41391D-page 302  2011 Microchip Technology Inc.

PIC16(L)F1826/27 26.3.2 AUTO-BAUD OVERFLOW 26.3.3.1 Special Considerations During the course of automatic baud detection, the Break Character ABDOVF bit of the BAUDCON register will be set if the To avoid character errors or character fragments during baud rate counter overflows before the fifth rising edge a wake-up event, the wake-up character must be all is detected on the RX pin. The ABDOVF bit indicates zeros. that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register When the wake-up is enabled the function works pair. After the ABDOVF has been set, the counter con- independent of the low time on the data stream. If the tinues to count until the fifth rising edge is detected on WUE bit is set and a valid non-zero character is the RX pin. Upon detecting the fifth RX edge, the hard- received, the low time from the Start bit to the first rising ware will set the RCIF interrupt flag and clear the edge will be interpreted as the wake-up event. The ABDEN bit of the BAUDCON register. The RCIF flag remaining bits in the character will be received as a can be subsequently cleared by reading the RCREG fragmented character and subsequent characters can register. The ABDOVF flag of the BAUDCON register result in framing or overrun errors. can be cleared by software directly. Therefore, the initial character in the transmission must To terminate the auto-baud process before the RCIF be all ‘0’s. This must be 10 or more bit times, 13-bit flag is set, clear the ABDEN bit then clear the ABDOVF times recommended for LIN bus, or any number of bit bit of the BAUDCON register. The ABDOVF bit will times for standard RS-232 devices. remain set if the ABDEN bit is not cleared first. Oscillator Start-up Time Oscillator start-up time must be considered, especially 26.3.3 AUTO-WAKE-UP ON BREAK in applications using oscillators with longer start-up During Sleep mode, all clocks to the EUSART are intervals (i.e., LP, XT or HS/PLL mode). The Sync suspended. Because of this, the Baud Rate Generator Break (or wake-up signal) character must be of is inactive and a proper character reception cannot be sufficient length, and be followed by a sufficient performed. The Auto-Wake-up feature allows the interval, to allow enough time for the selected oscillator controller to wake-up due to activity on the RX/DT line. to start and provide proper initialization of the EUSART. This feature is available only in Asynchronous mode. WUE Bit The Auto-Wake-up feature is enabled by setting the The wake-up event causes a receive interrupt by WUE bit of the BAUDCON register. Once set, the normal setting the RCIF bit. The WUE bit is cleared in receive sequence on RX/DT is disabled, and the hardware by a rising edge on RX/DT. The interrupt EUSART remains in an Idle state, monitoring for a condition is then cleared in software by reading the wake-up event independent of the CPU mode. A RCREG register and discarding its contents. wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break To ensure that no actual data is lost, check the RCIDL or a wake-up signal character for the LIN protocol.) bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not The EUSART module generates an RCIF interrupt occurring, the WUE bit may then be set just prior to coincident with the wake-up event. The interrupt is entering the Sleep mode. generated synchronously to the Q clocks in normal CPU operating modes (Figure26-7), and asynchronously if the device is in Sleep mode (Figure26-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.  2011 Microchip Technology Inc. DS41391D-page 303

PIC16(L)F1826/27 FIGURE 26-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 26-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RX/DT Line Note 1 RCIF Cleared due to User Read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. DS41391D-page 304  2011 Microchip Technology Inc.

PIC16(L)F1826/27 26.3.4 BREAK CHARACTER SEQUENCE 26.3.5 RECEIVING A BREAK CHARACTER The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break special Break character sequences that are required by character in two ways. the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the Received data To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is bits of the TXSTA register. The Break character trans- assumed to have been initialized to the expected baud mission is then initiated by a write to the TXREG. The rate. value of data written to TXREG will be ignored and all A Break character has been received when; ‘0’s will be transmitted. • RCIF bit is set The SENDB bit is automatically reset by hardware after • FERR bit is set the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte • RCREG = 00h following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature character in the LIN specification). described in Section26.3.3 “Auto-Wake-up on The TRMT bit of the TXSTA register indicates when the Break”. By enabling this feature, the EUSART will transmit operation is active or Idle, just as it does during sample the next two transitions on RX/DT, cause an normal transmission. See Figure26-9 for the timing of RCIF interrupt, and receive the next data byte followed the Break character sequence. by another interrupt. Note that following a Break character, the user will 26.3.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature. The following sequence will start a message frame For both methods, the user can set the ABDEN bit of header made up of a Break, followed by an auto-baud the BAUDCON register before placing the EUSART in Sync byte. This sequence is typical of a LIN bus Sleep mode. master. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to enable the Break sequence. 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. FIGURE 26-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit)  2011 Microchip Technology Inc. DS41391D-page 305

PIC16(L)F1826/27 26.4 EUSART Synchronous Mode Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising Synchronous serial communications are typically used edge of each clock. in systems with a single master and one or more slaves. The master device contains the necessary cir- 26.4.1.3 Synchronous Master Transmission cuitry for baud rate generation and supplies the clock Data is transferred out of the device on the RX/DT pin. for all devices in the system. Slave devices can take The RX/DT and TX/CK pin output drivers are automat- advantage of the master clock by eliminating the inter- ically enabled when the EUSART is configured for syn- nal clock generation circuitry. chronous master transmit operation. There are two signal lines in Synchronous mode: a bidi- A transmission is initiated by writing a character to the rectional data line and a clock line. Slaves use the TXREG register. If the TSR still contains all or part of a external clock supplied by the master to shift the serial previous character the new character data is held in the data into and out of their respective receive and trans- TXREG until the last bit of the previous character has mit shift registers. Since the data line is bidirectional, been transmitted. If this is the first character, or the pre- synchronous operation is half-duplex only. Half-duplex vious character has been completely flushed from the refers to the fact that master and slave devices can TSR, the data in the TXREG is immediately transferred receive and transmit data but not both simultaneously. to the TSR. The transmission of the character com- The EUSART can operate as either a master or slave mences immediately following the transfer of the data device. to the TSR from the TXREG. Start and Stop bits are not used in synchronous trans- Each data bit changes on the leading edge of the mas- missions. ter clock and remains valid until the subsequent leading clock edge. 26.4.1 SYNCHRONOUS MASTER MODE The following bits are used to configure the EUSART Note: The TSR register is not mapped in data for Synchronous Master operation: memory, so it is not available to the user. • SYNC = 1 26.4.1.4 Synchronous Master Transmission • CSRC = 1 Set-up: • SREN = 0 (for transmit); SREN = 1 (for receive) 1. Initialize the SPBRGH, SPBRGL register pair • CREN = 0 (for transmit); CREN = 1 (for receive) and the BRGH and BRG16 bits to achieve the • SPEN = 1 desired baud rate (see Section26.3 “EUSART Baud Rate Generator (BRG)”). Setting the SYNC bit of the TXSTA register configures 2. Enable the synchronous master serial port by the device for synchronous operation. Setting the CSRC setting bits SYNC, SPEN and CSRC. bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA 3. Disable Receive mode by clearing bits SREN register ensures that the device is in the Transmit mode, and CREN. otherwise the device will be configured to receive. Setting 4. Enable Transmit mode by setting the TXEN bit. the SPEN bit of the RCSTA register enables the 5. If 9-bit transmission is desired, set the TX9 bit. EUSART. 6. If interrupts are desired, set the TXIE bit of the 26.4.1.1 Master Clock PIE1 register and the GIE and PEIE bits of the INTCON register. Synchronous data transfers use a separate clock line, 7. If 9-bit transmission is selected, the ninth bit which is synchronous with the data. A device config- should be loaded in the TX9D bit. ured as a master transmits the clock on the TX/CK line. 8. Start transmission by loading data to the TXREG The TX/CK pin output driver is automatically enabled register. when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trail- ing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are gener- ated as there are data bits. 26.4.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. DS41391D-page 306  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 26-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 26-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit  2011 Microchip Technology Inc. DS41391D-page 307

PIC16(L)F1826/27 TABLE 26-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(1) CCP2SEL(1) P1DSEL P1CSEL CCP1SEL 119 APFCON1 — — — — — — — TXCKSEL 119 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 296 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 91 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 295 SPBRGL BRG<7:0> 297* SPBRGH BRG<15:8> 297* TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 TXREG EUSART Transmit Data Register 287* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 294 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Transmission. * Page provides register information. Note 1: PIC16(L)F1827 only. DS41391D-page 308  2011 Microchip Technology Inc.

PIC16(L)F1826/27 26.4.1.5 Synchronous Master Reception buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit Data is received at the RX/DT pin. The RX/DT pin can only be cleared by clearing the overrun condition. output driver is automatically disabled when the If the overrun error occurred when the SREN bit is set EUSART is configured for synchronous master receive and CREN is clear then the error is cleared by reading operation. RCREG. If the overrun occurred when the CREN bit is In Synchronous mode, reception is enabled by setting set then the error condition is cleared by either clearing either the Single Receive Enable bit (SREN of the the CREN bit of the RCSTA register or by clearing the RCSTA register) or the Continuous Receive Enable bit SPEN bit which resets the EUSART. (CREN of the RCSTA register). 26.4.1.8 Receiving 9-bit Characters When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a The EUSART supports 9-bit character reception. When single character. The SREN bit is automatically cleared the RX9 bit of the RCSTA register is set the EUSART at the completion of one character. When CREN is set, will shift 9-bits into the RSR for each character clocks are continuously generated until CREN is received. The RX9D bit of the RCSTA register is the cleared. If CREN is cleared in the middle of a character ninth, and Most Significant, data bit of the top unread the CK clock stops immediately and the partial charac- character in the receive FIFO. When reading 9-bit data ter is discarded. If SREN and CREN are both set, then from the receive FIFO buffer, the RX9D data bit must SREN is cleared at the completion of the first character be read before reading the 8 Least Significant bits from and CREN takes precedence. the RCREG. To initiate reception, set either SREN or CREN. Data is 26.4.1.9 Synchronous Master Reception sampled at the RX/DT pin on the trailing edge of the Set-up: TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is 1. Initialize the SPBRGH, SPBRGL register pair for received into the RSR, the RCIF bit is set and the char- the appropriate baud rate. Set or clear the acter is automatically transferred to the two character BRGH and BRG16 bits, as required, to achieve receive FIFO. The Least Significant eight bits of the top the desired baud rate. character in the receive FIFO are available in RCREG. 2. Clear the ANSEL bit for the RX pin (if applicable). The RCIF bit remains set as long as there are unread 3. Enable the synchronous master serial port by characters in the receive FIFO. setting bits SYNC, SPEN and CSRC. Note: If the RX/DT function is on an analog pin, 4. Ensure bits CREN and SREN are clear. the corresponding ANSEL bit must be 5. If interrupts are desired, set the RCIE bit of the cleared for the receiver to function. PIE1 register and the GIE and PEIE bits of the INTCON register. 26.4.1.6 Slave Clock 6. If 9-bit reception is desired, set bit RX9. Synchronous data transfers use a separate clock line, 7. Start reception by setting the SREN bit or for which is synchronous with the data. A device configured continuous reception, set the CREN bit. as a slave receives the clock on the TX/CK line. The 8. Interrupt flag bit RCIF will be set when reception TX/CK pin output driver is automatically disabled when of a character is complete. An interrupt will be the device is configured for synchronous slave transmit generated if the enable bit RCIE was set. or receive operation. Serial data bits change on the 9. Read the RCSTA register to get the ninth bit (if leading edge to ensure they are valid at the trailing edge enabled) and determine if any error occurred of each clock. One data bit is transferred for each clock during reception. cycle. Only as many clock cycles should be received as there are data bits. 10. Read the 8-bit received data by reading the RCREG register. Note: If the device is configured as a slave and 11. If an overrun error occurs, clear the error by the TX/CK function is on an analog pin, the either clearing the CREN bit of the RCSTA corresponding ANSEL bit must be register or by clearing the SPEN bit which resets cleared. the EUSART. 26.4.1.7 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO  2011 Microchip Technology Inc. DS41391D-page 309

PIC16(L)F1826/27 FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 26-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(1) CCP2SEL(1) P1DSEL P1CSEL CCP1SEL 119 APFCON1 — — — — — — — TXCKSEL 119 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 296 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 91 RCREG EUSART Receive Data Register 290* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 295 SPBRGL BRG<7:0> 297* SPBRGH BRG<15:8> 297* TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 294 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception. * Page provides register information. Note 1: PIC16(L)F1827 only. DS41391D-page 310  2011 Microchip Technology Inc.

PIC16(L)F1826/27 26.4.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the EUSART for Synchronous slave operation: 1. The first character will immediately transfer to the TSR register and transmit. • SYNC = 1 2. The second word will remain in TXREG register. • CSRC = 0 3. The TXIF bit will not be set. • SREN = 0 (for transmit); SREN = 1 (for receive) 4. After the first character has been shifted out of • CREN = 0 (for transmit); CREN = 1 (for receive) TSR, the TXREG register will transfer the second • SPEN = 1 character to the TSR and the TXIF bit will now be Setting the SYNC bit of the TXSTA register configures the set. device for synchronous operation. Clearing the CSRC bit 5. If the PEIE and TXIE bits are set, the interrupt of the TXSTA register configures the device as a slave. will wake the device from Sleep and execute the Clearing the SREN and CREN bits of the RCSTA register next instruction. If the GIE bit is also set, the ensures that the device is in the Transmit mode, program will call the Interrupt Service Routine. otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the 26.4.2.2 Synchronous Slave Transmission EUSART. Set-up: 26.4.2.1 EUSART Synchronous Slave 1. Set the SYNC and SPEN bits and clear the CSRC bit. Transmit 2. Clear the ANSEL bit for the CK pin (if applicable). The operation of the Synchronous Master and Slave 3. Clear the CREN and SREN bits. modes are identical (see Section26.4.1.3 4. If interrupts are desired, set the TXIE bit of the “Synchronous Master Transmission”), except in the PIE1 register and the GIE and PEIE bits of the case of the Sleep mode. INTCON register. 5. If 9-bit transmission is desired, set the TX9 bit. 6. Enable transmission by setting the TXEN bit. 7. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 8. Start transmission by writing the Least Significant 8 bits to the TXREG register. TABLE 26-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(1) CCP2SEL(1) P1DSEL P1CSEL CCP1SEL 119 APFCON1 — — — — — — — TXCKSEL 119 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 296 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 91 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 295 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 TXREG EUSART Transmit Data Register 287* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 294 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. * Page provides register information. Note 1: PIC16(L)F1827 only.  2011 Microchip Technology Inc. DS41391D-page 311

PIC16(L)F1826/27 26.4.2.3 EUSART Synchronous Slave 26.4.2.4 Synchronous Slave Reception Reception Set-up: The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the modes is identical (Section26.4.1.5 “Synchronous CSRC bit. Master Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins • Sleep (if applicable). • CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RCIE bit of the never Idle PIE1 register and the GIE and PEIE bits of the INTCON register. • SREN bit, which is a “don’t care” in Slave mode 4. If 9-bit reception is desired, set the RX9 bit. A character may be received while in Sleep mode by 5. Set the CREN bit to enable reception. setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data 6. The RCIF bit will be set when reception is to the RCREG register. If the RCIE enable bit is set, the complete. An interrupt will be generated if the interrupt generated will wake the device from Sleep RCIE bit was set. and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTA register. 8. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 26-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(1) CCP2SEL(1) P1DSEL P1CSEL CCP1SEL 119 APFCON1 — — — — — — — TXCKSEL 119 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 296 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 91 RCREG EUSART Receive Data Register 290* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 295 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 294 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception. * Page provides register information. Note 1: PIC16(L)F1827 only. DS41391D-page 312  2011 Microchip Technology Inc.

PIC16(L)F1826/27 26.5 EUSART Operation During Sleep 26.5.2 SYNCHRONOUS TRANSMIT DURING SLEEP The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the To transmit during Sleep, all the following conditions system clock and therefore cannot generate the neces- must be met before entering Sleep mode: sary signals to run the Transmit or Receive Shift regis- • RCSTA and TXSTA Control registers must be ters during Sleep. configured for Synchronous Slave Transmission Synchronous Slave mode uses an externally generated (see Section26.4.2.2 “Synchronous Slave clock to run the Transmit and Receive Shift registers. Transmission Set-up:”). • The TXIF interrupt flag must be cleared by writing 26.5.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the SLEEP TSR and transmit buffer. To receive during Sleep, all the following conditions • If interrupts are desired, set the TXIE bit of the must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON reg- ister. • RCSTA and TXSTA Control registers must be • Interrupt enable bits TXIE of the PIE1 register and configured for Synchronous Slave Reception (see PEIE of the INTCON register must set. Section26.4.2.4 “Synchronous Slave Reception Set-up:”). Upon entering Sleep mode, the device will be ready to • If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the PIE1 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been INTCON register. completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and • The RCIF interrupt flag must be cleared by read- the TXIF flag will be set. Thereby, waking the processor ing RCREG to unload any pending characters in from Sleep. At this point, the TXREG is available to the receive buffer. accept another character for transmission, which will Upon entering Sleep mode, the device will be ready to clear the TXIF flag. accept data and clocks on the RX/DT and TX/CK pins, Upon waking from Sleep, the instruction following the respectively. When the data word has been completely SLEEP instruction will be executed. If the Global clocked in by the external device, the RCIF interrupt Interrupt Enable (GIE) bit is also set then the Interrupt flag bit of the PIR1 register will be set. Thereby, waking Service Routine at address 0004h will be called. the processor from Sleep. Upon waking from Sleep, the instruction following the 26.5.3 ALTERNATE PIN LOCATIONS SLEEP instruction will be executed. If the GIE global This module incorporates I/O pins that can be moved to interrupt enable bit of the INTCON register is also set, other locations with the use of the alternate pin function then the Interrupt Service Routine at address 004h will registers, APFCON0 and APFCON1. To determine be called. which pins can be moved and what their default loca- tions are upon a reset, see Section12.1 “Alternate Pin Function” for more information.  2011 Microchip Technology Inc. DS41391D-page 313

PIC16(L)F1826/27 NOTES: DS41391D-page 314  2011 Microchip Technology Inc.

PIC16(L)F1826/27 27.0 CAPACITIVE SENSING MODULE The capacitive sensing module allows for an interaction with an end user without a mechanical interface. In a typical application, the capacitive sensing module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the capacitive sensing module. The capacitive sensing module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: • Analog MUX for monitoring multiple inputs • Capacitive sensing oscillator • Multiple timer resources • Software control • Operation during Sleep FIGURE 27-1: CAPACITIVE SENSING BLOCK DIAGRAM Timer0 Module Set TMR0CS T0XCS TMR0IF FOSC/4 0 Overflow T0CKI 0 TMR0 1 1 CPSCH<3:0> CPSON(1) CPS0 CPS1 CPS2 Timer1 Module CPS3 CPSON T1CS<1:0> CPS4 FOSC Capacitive CPS5 Sensing FOSC/4 CPSCLK Oscillator TMR1H:TMR1L CPS6 T1OSC/ EN CPSOSC T1CKI CPS7 CPSOUT CPS8 CPSRNG<1:0> T1GSEL<1:0> CPS9 T1G CPS10 Timer1 Gate Control Logic SYNCC1OUT CPS11 SYNCC2OUT Note 1: If CPSON=0, disabling capacitive sensing, no channel is selected.  2011 Microchip Technology Inc. DS41391D-page 315

PIC16(L)F1826/27 27.1 Analog MUX 27.4.1 TIMER0 The capacitive sensing module can monitor up to 12 To select Timer0 as the timer resource for the capacitive inputs. The capacitive sensing inputs are defined as sensing module: CPS<11:0>. To determine if a frequency change has • Set the T0XCS bit of the CPSCON0 register occurred the user must: • Clear the TMR0CS bit of the OPTION register • Select the appropriate CPS pin by setting the When Timer0 is chosen as the timer resource, the CPSCH<3:0> bits of the CPSCON1 register capacitive sensing oscillator will be the clock source for • Set the corresponding ANSEL bit Timer0. Refer to Section20.0 “Timer0 Module” for • Set the corresponding TRIS bit additional information. • Run the software algorithm 27.4.2 TIMER1 Selection of the CPSx pin while the module is enabled To select Timer1 as the timer resource for the will cause the capacitive sensing oscillator to be on the capacitive sensing module, set the TMR1CS<1:0> of CPSx pin. Failure to set the corresponding ANSEL and the T1CON register to ‘11’. When Timer1 is chosen as TRIS bits can cause the capacitive sensing oscillator to the timer resource, the capacitive sensing oscillator will stop, leading to false frequency readings. be the clock source for Timer1. Because the Timer1 module has a gate control, developing a time base for 27.2 Capacitive Sensing Oscillator the frequency measurement can be simplified by using The capacitive sensing oscillator consists of a constant the Timer0 overflow flag. current source and a constant current sink, to produce It is recommend that the Timer0 overflow flag, in con- a triangle waveform. The CPSOUT bit of the junction with the Toggle mode of the Timer1 gate, be CPSCON0 register shows the status of the capacitive used to develop the fixed time base required by the sensing oscillator, whether it is a sinking or sourcing software portion of the capacitive sensing module. current. The oscillator is designed to drive a capacitive Refer to Section21.6.3 “Timer1 Gate Toggle Mode” load (single PCB pad) and at the same time, be a clock for additional information. source to either Timer0 or Timer1. The oscillator has three different current settings as defined by TABLE 27-1: TIMER1 ENABLE FUNCTION CPSRNG<1:0> of the CPSCON0 register. The different current settings for the oscillator serve two purposes: TMR1ON TMR1GE Timer1 Operation • Maximize the number of counts in a timer for a 0 0 Off fixed time base 0 1 Off • Maximize the count differential in the timer during 1 0 On a change in frequency 1 1 Count Enabled by input 27.3 Timer resources To measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. For the period of the fixed time base, the capacitive sensing oscillator is used to clock either Timer0 or Timer1. The frequency of the capacitive sensing oscillator is equal to the number of counts in the timer divided by the period of the fixed time base. 27.4 Fixed Time Base To measure the frequency of the capacitive sensing oscillator, a fixed time base is required. Any timer resource or software loop can be used to establish the fixed time base. It is up to the end user to determine the method in which the fixed time base is generated. Note: The fixed time base can not be generated by the timer resource that the capacitive sensing oscillator is clocking. DS41391D-page 316  2011 Microchip Technology Inc.

PIC16(L)F1826/27 27.5 Software Control 27.5.3 FREQUENCY THRESHOLD The software portion of the capacitive sensing module The frequency threshold should be placed midway is required to determine the change in frequency of the between the value of nominal frequency and the capacitive sensing oscillator. This is accomplished by reduced frequency of the capacitive sensing oscillator. the following: Refer to Application Note AN1103, “Software Handling for Capacitive Sensing” (DS01103) for more detailed • Setting a fixed time base to acquire counts on information on the software required for capacitive Timer0 or Timer1 sensing module. • Establishing the nominal frequency for the Note: For more information on general capacitive capacitive sensing oscillator sensing refer to Application Notes: • Establishing the reduced frequency for the capacitive sensing oscillator due to an additional • AN1101, “Introduction to Capacitive capacitive load Sensing” (DS01101) • Set the frequency threshold • AN1102, “Layout and Physical Design Guidelines for Capacitive 27.5.1 NOMINAL FREQUENCY Sensing” (DS01102) (NO CAPACITIVE LOAD) To determine the nominal frequency of the capacitive 27.6 Operation during Sleep sensing oscillator: The capacitive sensing oscillator will continue to run as • Remove any extra capacitive load on the selected long as the module is enabled, independent of the part CPSx pin being in Sleep. In order for the software to determine if • At the start of the fixed time base, clear the timer a frequency change has occurred, the part must be resource awake. However, the part does not have to be awake • At the end of the fixed time base save the value in when the timer resource is acquiring counts. the timer resource Note: Timer0 does not operate when in Sleep, The value of the timer resource is the number of and therefore cannot be used for oscillations of the capacitive sensing oscillator for the capacitive sense measurements in Sleep. given time base. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base. 27.5.2 REDUCED FREQUENCY (ADDITIONAL CAPACITIVE LOAD) The extra capacitive load will cause the frequency of the capacitive sensing oscillator to decrease. To determine the reduced frequency of the capacitive sensing oscillator: • Add a typical capacitive load on the selected CPSx pin • Use the same fixed time base as the nominal frequency measurement • At the start of the fixed time base, clear the timer resource • At the end of the fixed time base save the value in the timer resource The value of the timer resource is the number of oscil- lations of the capacitive sensing oscillator with an addi- tional capacitive load. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base. This frequency should be less than the value obtained during the nominal frequency measurement.  2011 Microchip Technology Inc. DS41391D-page 317

PIC16(L)F1826/27 REGISTER 27-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPSON: Capacitive Sensing Module Enable bit 1 = Capacitive sensing module is enabled 0 = Capacitive sensing module is disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3-2 CPSRNG<1:0>: Capacitive Sensing Oscillator Range bits 00 = Oscillator is off 01 = Oscillator is in low range. Charge/discharge current is nominally 0.1µA. 10 = Oscillator is in medium range. Charge/discharge current is nominally 1.2µA. 11 = Oscillator is in high range. Charge/discharge current is nominally 18µA. bit 1 CPSOUT: Capacitive Sensing Oscillator Status bit 1 = Oscillator is sourcing current (Current flowing out the pin) 0 = Oscillator is sinking current (Current flowing into the pin) bit 0 T0XCS: Timer0 External Clock Source Select bit If TMR0CS = 1 The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0: 1 = Timer0 clock source is the capacitive sensing oscillator 0 = Timer0 clock source is the T0CKI pin If TMR0CS = 0 Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4 DS41391D-page 318  2011 Microchip Technology Inc.

PIC16(L)F1826/27 REGISTER 27-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CPSCH<3:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected. If CPSON = 1: 0000 = channel 0, (CPS0) 0001 = channel 1, (CPS1) 0010 = channel 2, (CPS2) 0011 = channel 3, (CPS3) 0100 = channel 4, (CPS4) 0101 = channel 5, (CPS5) 0110 = channel 6, (CPS6) 0111 = channel 7, (CPS7) 1000 = channel 8, (CPS8) 1001 = channel 9, (CPS9) 1010 = channel 10, (CPS10) 1011 = channel 11, (CPS11) 1100 = Reserved. Do not use. 1101 = Reserved. Do not use. 1110 = Reserved. Do not use. 1111 = Reserved. Do not use. TABLE 27-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 123 ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 — 128 CPSCON0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 318 CPSCON1 — — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 319 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 176 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 91 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 185 TxCON — TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 TMRxON TxCKPS1 TxCKPS0 185 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 127 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the capacitive sensing module.  2011 Microchip Technology Inc. DS41391D-page 319

PIC16(L)F1826/27 NOTES: DS41391D-page 320  2011 Microchip Technology Inc.

PIC16(L)F1826/27 28.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirec- tional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16(L)F182X/PIC12(L)F1822 Memory Programming Specification” (DS41390). 28.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. Some programmers produce VPP greater than VIHH (9.0V), an external circuit is required to limit the VPP voltage. See Figure28-1 for example circuit. FIGURE 28-1: VPP LIMITER EXAMPLE CIRCUIT RJ11-6PIN 1 6 VPP 2 5 VDD 3 4 VSS 4 3 ICSP_DATA 5 2 ICSP_CLOCK 6 1 NC RJ11-6PIN To MPLAB® ICD 2 R1 To Target Board 270 Ohm LM431BCMX 23 AA U1 K1 6 A NC4 7 A NC5 VREF 8 R2 R3 10k 1% 24k 1% Note: The ICD 2 produces a VPP voltage greater than the maximum VPP specification of the PIC16(L)F1826/27.  2011 Microchip Technology Inc. DS41391D-page 321

PIC16(L)F1826/27 28.2 Low-Voltage Programming Entry FIGURE 28-2: ICD RJ-11 STYLE Mode CONNECTOR INTERFACE The Low-Voltage Programming Entry mode allows the PIC16(L)F1826/27 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word 2 is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the ICSPDAT Low-Voltage ICSP mode, the LVP bit must be 2 4 6 NC VDD programmed to ‘0’. ICSPCLK 1 3 5 Target Entry into the Low-Voltage Programming Entry mode requires the following steps: VPP/MCLR VSS PC Board Bottom Side 1. MCLR is brought to VIL. 2. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Pin Description* Once the key sequence is complete, MCLR must be 1 = VPP/MCLR held at VIL for as long as Program/Verify mode is to be 2 = VDD Target maintained. 3 = VSS (ground) If low-voltage programming is enabled (LVP = 1), the 4 = ICSPDAT MCLR Reset function is automatically enabled and 5 = ICSPCLK cannot be disabled. See Section7.3 “MCLR” for more 6 = No Connect information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1inch 28.3 Common Programming Interfaces spacing. Refer to Figure28-3. Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6 pin, 6 connector) configuration. See Figure28-2. FIGURE 28-3: PICkit™ STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 1 = VPP/MCLR 2 2 = VDD Target 3 4 3 = VSS (ground) 5 4 = ICSPDAT 6 5 = ICSPCLK 6 = No Connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins. DS41391D-page 322  2011 Microchip Technology Inc.

PIC16(L)F1826/27 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure28-4 for more information. FIGURE 28-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming VDD Device to be Signals Programmed VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required).  2011 Microchip Technology Inc. DS41391D-page 323

PIC16(L)F1826/27 NOTES: DS41391D-page 324  2011 Microchip Technology Inc.

PIC16(L)F1826/27 29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations Each PIC16 instruction is a 14-bit word containing the Any instruction that specifies a file register as part of operation code (opcode) and all required operands. the instruction performs a Read-Modify-Write (R-M-W) The op codes are broken into three broad categories. operation. The register is read, the data is modified, and the result is stored according to either the instruc- • Byte Oriented tion, or the destination designator ‘d’. A read operation • Bit Oriented is performed on a register even if the instruction writes • Literal and Control to that register. The literal and control category contains the most var- ied instruction word format. TABLE 29-1: OPCODE FIELD DESCRIPTIONS Table29-3 lists the instructions recognized by the MPASMTM assembler. Field Description All instructions are executed within a single instruction f Register file address (0x00 to 0x7F) cycle, with the following exceptions, which may take W Working register (accumulator) two or three cycles: b Bit address within an 8-bit file register • Subroutine takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two k Literal field, constant data or label cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1). • Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0. BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for • One additional instruction cycle will be used when compatibility with all Microchip software tools. any instruction references an indirect file register d Destination select; d = 0: store result in W, and the file select register is pointing to program d = 1: store result in file register f. memory. Default is d = 1. One instruction cycle consists of 4 oscillator cycles; for n FSR or INDF number. (0-1) an oscillator frequency of 4 MHz, this gives a nominal mm Pre-post increment-decrement mode instruction execution rate of 1 MHz. selection All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a TABLE 29-2: ABBREVIATION hexadecimal digit. DESCRIPTIONS Field Description PC Program Counter TO Time-out bit C Carry bit DC Digit carry bit Z Zero bit PD Power-down bit  2011 Microchip Technology Inc. DS41391D-page 325

PIC16(L)F1826/27 FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value MOVLP instruction only 13 7 6 0 OPCODE k (literal) k = 7-bit immediate value MOVLB instruction only 13 5 4 0 OPCODE k (literal) k = 5-bit immediate value BRA instruction only 13 9 8 0 OPCODE k (literal) k = 9-bit immediate value FSR Offset instructions 13 7 6 5 0 OPCODE n k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 3 2 1 0 OPCODE n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE DS41391D-page 326  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 29-3: PIC16(L)F1826/27 ENHANCED INSTRUCTION SET Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2 ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2 ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2 LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2 LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0000 00xx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 2 INCF f, d Increment f 1 00 1010 dfff ffff Z 2 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 2 MOVWF f Move W to f 1 00 0000 1fff ffff 2 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2 SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 2 BIT-ORIENTED SKIP OPERATIONS BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2 LITERAL OPERATIONS ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLB k Move literal to BSR 1 00 0000 001k kkkk MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk MOVLW k Move literal to W 1 11 0000 kkkk kkkk SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.  2011 Microchip Technology Inc. DS41391D-page 327

PIC16(L)F1826/27 TABLE 29-3: PIC16(L)F1826/27 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected CONTROL OPERATIONS BRA k Relative Branch 2 11 001k kkkk kkkk BRW – Relative Branch with W 2 00 0000 0000 1011 CALL k Call Subroutine 2 10 0kkk kkkk kkkk CALLW – Call Subroutine with W 2 00 0000 0000 1010 GOTO k Go to address 2 10 1kkk kkkk kkkk RETFIE k Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 0100 kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 INHERENT OPERATIONS CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD NOP – No Operation 1 00 0000 0000 0000 OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010 RESET – Software device Reset 1 00 0000 0000 0001 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD TRIS f Load TRIS register with W 1 00 0000 0110 0fff C-COMPILER OPTIMIZED ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3 modifier, mm k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2 MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3 modifier, mm k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2 Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions. DS41391D-page 328  2011 Microchip Technology Inc.

PIC16(L)F1826/27 29.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k Operands: -32  k  31 Operands: 0  k  255 n  [ 0, 1] Operation: (W) .AND. (k)  (W) Operation: FSR(n) + k  FSR(n) Status Affected: Z Status Affected: None Description: The contents of W register are Description: The signed 6-bit literal ‘k’ is added to AND’ed with the eight-bit literal ‘k’. the contents of the FSRnH:FSRnL The result is placed in the W register. register pair. FSRn is limited to the range 0000h - FFFFh. Moving beyond these bounds will cause the FSR to wrap around. ADDLW Add literal and W ANDWF AND W with f Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d Operands: 0  k  255 Operands: 0  f  127 d 0,1 Operation: (W) + k  (W) Operation: (W) .AND. (f)  (destination) Status Affected: C, DC, Z Status Affected: Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the Description: AND the W register with register ‘f’. If result is placed in the W register. ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWF Add W and f ASRF Arithmetic Right Shift Syntax: [ label ] ADDWF f,d Syntax: [ label ] ASRF f {,d} Operands: 0  f  127 Operands: 0  f  127 d 0,1 d [0,1] Operation: (W) + (f)  (destination) Operation: (f<7>) dest<7> (f<7:1>)  dest<6:0>, Status Affected: C, DC, Z (f<0>)  C, Description: Add the contents of the W register Status Affected: C, Z with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the Description: The contents of register ‘f’ are shifted result is stored back in register ‘f’. one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in reg- ister ‘f’. ADDWFC ADD W and CARRY bit to f register f C Syntax: [ label ] ADDWFC f {,d} Operands: 0  f  127 d [0,1] Operation: (W) + (f) + (C)  dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data mem- ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.  2011 Microchip Technology Inc. DS41391D-page 329

PIC16(L)F1826/27 BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 0  b  7 0  b  7 Operation: 0  (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b [ label ] BRA $+k Operands: 0  f  127 Operands: -256label-PC+1255 0  b < 7 -256  k  255 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k  PC Status Affected: None Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Description: Add the signed 9-bit literal ‘k’ to the instruction is executed. PC. Since the PC will have incre- If bit ‘b’ is ‘1’, then the next mented to fetch the next instruction, instruction is discarded and a NOP is the new address will be PC+1+k. executed instead, making this a This instruction is a two-cycle instruc- 2-cycle instruction. tion. This branch has a limited range. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W)  PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incre- mented to fetch the next instruction, the new address will be PC+1+(W). This instruction is a two-cycle instruc- tion. BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0  f  127 0  b  7 Operation: 1  (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. DS41391D-page 330  2011 Microchip Technology Inc.

PIC16(L)F1826/27 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<6:3>)  PC<14:11> 1  TO Status Affected: None 1  PD Description: Call Subroutine. First, return address Status Affected: TO, PD (PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch- The eleven-bit immediate address is dog Timer. It also resets the prescaler loaded into PC bits <10:0>. The upper of the WDT. bits of the PC are loaded from Status bits TO and PD are set. PCLATH. CALL is a two-cycle instruc- tion. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: (PC) +1  TOS, (W)  PC<7:0>, Operation: (f)  (destination) (PCLATH<6:0>) PC<14:8> Status Affected: Z Description: The contents of register ‘f’ are com- Status Affected: None plemented. If ‘d’ is ‘0’, the result is Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is return address (PC + 1) is pushed stored back in register ‘f’. onto the return stack. Then, the con- tents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a two-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the and the Z bit is set. result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h  (W) 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set.  2011 Microchip Technology Inc. DS41391D-page 331

PIC16(L)F1826/27 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre- mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. is placed back in register ‘f’. If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is NOP is executed instead, making it a executed instead, making it a 2-cycle 2-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<6:3>  PC<14:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. The OR’ed with the eight-bit literal ‘k’. The eleven-bit immediate value is loaded result is placed in the W register. into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis- mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is is placed back in register ‘f’. placed back in register ‘f’. DS41391D-page 332  2011 Microchip Technology Inc.

PIC16(L)F1826/27 LSLF Logical Left Shift MOVF Move f Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d Operands: 0  f  127 Operands: 0  f  127 d [0,1] d  [0,1] Operation: (f<7>)  C Operation: (f)  (dest) (f<6:0>)  dest<7:1> Status Affected: Z 0  dest<0> Description: The contents of register f is moved to Status Affected: C, Z a destination dependent upon the Description: The contents of register ‘f’ are shifted status of d. If d = 0, one bit to the left through the Carry flag. destination is W register. If d = 1, the A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, destination is file register f itself. d = 1 the result is placed in W. If ‘d’ is ‘1’, the is useful to test a file register since result is stored back in register ‘f’. status flag Z is affected. Words: 1 C register f 0 Cycles: 1 Example: MOVF FSR, 0 After Instruction LSRF Logical Right Shift W = value in FSR register Syntax: [ label ] LSLF f {,d} Z = 1 Operands: 0  f  127 d [0,1] Operation: 0  dest<7> (f<7:1>)  dest<6:0>, (f<0>)  C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘0’ is shifted into the MSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 0 register f C  2011 Microchip Technology Inc. DS41391D-page 333

PIC16(L)F1826/27 MOVIW Move INDFn to W MOVLP Move literal to PCLATH Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k [ label ] MOVIW --FSRn Operands: 0  k  127 [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-- Operation: k  PCLATH [ label ] MOVIW k[FSRn] Status Affected: None Operands: n  [0,1] Description: The seven-bit literal ‘k’ is loaded into the mm  [00,01, 10, 11] PCLATH register. -32  k  31 Operation: INDFn  W Effective address is determined by MOVLW Move literal to W • FSR + 1 (preincrement) Syntax: [ label ] MOVLW k • FSR - 1 (predecrement) • FSR + k (relative offset) Operands: 0  k  255 After the Move, the FSR value will be Operation: k  (W) either: • FSR + 1 (all increments) Status Affected: None • FSR - 1 (all decrements) Description: The eight-bit literal ‘k’ is loaded into W • Unchanged register. The “don’t cares” will assem- Status Affected: Z ble as ‘0’s. Words: 1 Mode Syntax mm Cycles: 1 Preincrement ++FSRn 00 Example: MOVLW 0x5A Predecrement --FSRn 01 After Instruction W = 0x5A Postincrement FSRn++ 10 Postdecrement FSRn-- 11 MOVWF Move W to f Syntax: [ label ] MOVWF f Description: This instruction is used to move data between W and one of the indirect Operands: 0  f  127 registers (INDFn). Before/after this Operation: (W)  (f) move, the pointer (FSRn) is updated by Status Affected: None pre/post incrementing/decrementing it. Description: Move data from W register to register Note: The INDFn registers are not ‘f’. physical registers. Any instruction that Words: 1 accesses an INDFn register actually accesses the register at the address Cycles: 1 specified by the FSRn. Example: MOVWF OPTION_REG Before Instruction FSRn is limited to the range 0000h - OPTION_REG = 0xFF FFFFh. Incrementing/decrementing it W = 0x4F beyond these bounds will cause it to wrap After Instruction around. OPTION_REG = 0x4F W = 0x4F MOVLB Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0  k  15 Operation: k  BSR Status Affected: None Description: The five-bit literal ‘k’ is loaded into the Bank Select Register (BSR). DS41391D-page 334  2011 Microchip Technology Inc.

PIC16(L)F1826/27 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] NOP Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn Operands: None [ label ] MOVWI FSRn++ Operation: No operation [ label ] MOVWI FSRn-- [ label ] MOVWI k[FSRn] Status Affected: None Operands: n  [0,1] Description: No operation. mm  [00,01, 10, 11] Words: 1 -32  k  31 Cycles: 1 Operation: W  INDFn Example: NOP Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be Load OPTION_REG Register either: OPTION with W • FSR + 1 (all increments) • FSR - 1 (all decrements) Syntax: [ label ] OPTION Unchanged Operands: None Status Affected: None Operation: (W)  OPTION_REG Status Affected: None Mode Syntax mm Description: Move data from W register to Preincrement ++FSRn 00 OPTION_REG register. Predecrement --FSRn 01 Postincrement FSRn++ 10 Words: 1 Postdecrement FSRn-- 11 Cycles: 1 Example: OPTION Description: This instruction is used to move data Before Instruction between W and one of the indirect OPTION_REG = 0xFF registers (INDFn). Before/after this W = 0x4F move, the pointer (FSRn) is updated by After Instruction pre/post incrementing/decrementing it. OPTION_REG = 0x4F W = 0x4F Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually RESET Software Reset accesses the register at the address specified by the FSRn. Syntax: [ label ] RESET Operands: None FSRn is limited to the range 0000h - FFFFh. Incrementing/decrementing it Operation: Execute a device Reset. Resets the beyond these bounds will cause it to wrap nRI flag of the PCON register. around. Status Affected: None Description: This instruction provides a way to The increment/decrement operation on execute a hardware Reset by soft- FSRn WILL NOT affect any Status bits. ware.  2011 Microchip Technology Inc. DS41391D-page 335

PIC16(L)F1826/27 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] RETFIE Syntax: [ label ] RETURN Operands: None Operands: None Operation: TOS  PC, Operation: TOS  PC 1  GIE Status Affected: None Status Affected: None Description: Return from subroutine. The stack is Description: Return from Interrupt. Stack is POPed POPed and the top of the stack (TOS) and Top-of-Stack (TOS) is loaded in is loaded into the program counter. the PC. Interrupts are enabled by This is a two-cycle instruction. setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 RETLW Return with literal in W RLF Rotate Left f through Carry Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d Operands: 0  k  255 Operands: 0  f  127 d  [0,1] Operation: k  (W); TOS  PC Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the eight Description: The contents of register ‘f’ are rotated bit literal ‘k’. The program counter is one bit to the left through the Carry loaded from the top of the stack (the flag. If ‘d’ is ‘0’, the result is placed in return address). This is a two-cycle the W register. If ‘d’ is ‘1’, the result is instruction. stored back in register ‘f’. Words: 1 C Register f Cycles: 2 Words: 1 Example: CALL TABLE;W contains table Cycles: 1 ;offset value • ;W now has table value Example: RLF REG1,0 TABLE • Before Instruction • REG1 = 1110 0110 ADDWF PC ;W = offset C = 0 RETLW k1 ;Begin table After Instruction RETLW k2 ; REG1 = 1110 0110 • W = 1100 1100 • C = 1 • RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 DS41391D-page 336  2011 Microchip Technology Inc.

PIC16(L)F1826/27 SUBLW Subtract W from literal RRF Rotate Right f through Carry Syntax: [ label ] SUBLW k Syntax: [ label ] RRF f,d Operands: 0 k 255 Operands: 0  f  127 d  [0,1] Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s com- plement method) from the eight-bit Description: The contents of register ‘f’ are rotated literal ‘k’. The result is placed in the W one bit to the right through the Carry register. flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is C = 0 W  k placed back in register ‘f’. C = 1 W  k C Register f DC = 0 W<3:0>  k<3:0> DC = 1 W<3:0>  k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] SLEEP Syntax: [ label ] SUBWF f,d Operands: None Operands: 0 f 127 d  [0,1] Operation: 00h  WDT, 0  WDT prescaler, Operation: (f) - (W) destination) 1  TO, Status Affected: C, DC, Z 0  PD Description: Subtract (2’s complement method) W Status Affected: TO, PD register from register ‘f’. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is result is stored in the W cleared. Time-out Status bit, TO is register. If ‘d’ is ‘1’, the result is stored set. Watchdog Timer and its pres- back in register ‘f. caler are cleared. The processor is put into Sleep mode C = 0 W  f with the oscillator stopped. C = 1 W  f DC = 0 W<3:0>  f<3:0> DC = 1 W<3:0>  f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB f {,d} Operands: 0  f  127 d  [0,1] Operation: (f) – (W) – (B) dest Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s comple- ment method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.  2011 Microchip Technology Inc. DS41391D-page 337

PIC16(L)F1826/27 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k Operands: 0  f  127 Operands: 0 k 255 d  [0,1] Operation: (W) .XOR. k W) Operation: (f<3:0>)  (destination<7:4>), Status Affected: Z (f<7:4>)  (destination<3:0>) Description: The contents of the W register are Status Affected: None XOR’ed with the eight-bit Description: The upper and lower nibbles of regis- literal ‘k’. The result is placed in the ter ‘f’ are exchanged. If ‘d’ is ‘0’, the W register. result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. TRIS Load TRIS Register with W XORWF Exclusive OR W with f Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d Operands: 5  f  7 Operands: 0  f  127 d  [0,1] Operation: (W)  TRIS register ‘f’ Operation: (W) .XOR. (f) destination) Status Affected: None Status Affected: Z Description: Move data from W register to TRIS register. Description: Exclusive OR the contents of the W When ‘f’ = 5, TRISA is loaded. register with register ‘f’. If ‘d’ is ‘0’, the When ‘f’ = 6, TRISB is loaded. result is stored in the W register. If ‘d’ When ‘f’ = 7, TRISC is loaded. is ‘1’, the result is stored back in regis- ter ‘f’. DS41391D-page 338  2011 Microchip Technology Inc.

PIC16(L)F1826/27 30.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias.......................................................................................................-40°C to +125°C Storage temperature.........................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS, PIC16F1826/27 .........................................................................-0.3V to +6.5V Voltage on VDD with respect to VSS, PIC16LF1826/27 .......................................................................-0.3V to +4.0V Voltage on MCLR with respect to Vss .................................................................................................-0.3V to +9.0V Voltage on all other pins with respect to VSS ...........................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)...............................................................................................................................800 mW Maximum current out of VSS pin, -40°C  TA  +85°C for industrial................................................................396 mA Maximum current out of VSS pin, -40°C  TA  +125°C for extended.............................................................114 mA Maximum current into VDD pin, -40°C  TA  +85°C for industrial.................................................................. 292 mA Maximum current into VDD pin, -40°C  TA  +125°C for extended................................................................107 mA Clamp current, IK (VPIN < 0 or VPIN > VDD).......................................................................................................20 mA Maximum output current sunk by any I/O pin....................................................................................................25 mA Maximum output current sourced by any I/O pin..............................................................................................25 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating condi- tions for extended periods may affect device reliability.  2011 Microchip Technology Inc. DS41391D-page 339

PIC16(L)F1826/27 FIGURE 30-1: PIC16F1826/27 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C 5.5 ) V ( d d V 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-1 for each Oscillator mode’s supported frequencies. FIGURE 30-2: PIC16LF1826/27 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C V) 3.6 ( d d V 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-1 for each Oscillator mode’s supported frequencies. DS41391D-page 340  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 30-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 ± 3% C) ° 60 ( e r u at r e p 25 ± 2% m e T 0 -20 ± 5% -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2011 Microchip Technology Inc. DS41391D-page 341

PIC16(L)F1826/27 30.1 DC Characteristics: PIC16(L)F1826/27-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) PIC16LF1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. D001 VDD Supply Voltage PIC16LF1826/27 1.8 — 3.6 V FOSC  16MHz: 2.5 — 3.6 V FOSC  32MHz (NOTE 2) D001 PIC16F1826/27 1.8 — 5.5 V FOSC  16MHz: 2.5 — 5.5 V FOSC  32MHz (NOTE 2) D002* VDR RAM Data Retention Voltage(1) PIC16LF1826/27 1.5 — — V Device in Sleep mode D002* PIC16F1826/27 1.7 — — V Device in Sleep mode VPOR* Power-on Reset Release Voltage — 1.6 — V VPORR* Power-on Reset Rearm Voltage PIC16LF1826/27 — 0.8 — V Device in Sleep mode PIC16F1826/27 — 1.7 — V Device in Sleep mode D003 VADFVR Fixed Voltage Reference Voltage for -8 — 6 % 1.024V, VDD  2.5V ADC -8 — 6 2.048V, VDD  2.5V -8 — 6 4.096V, VDD  4.75 D003A VCDAFVR Fixed Voltage Reference Voltage for -11 — 7 % 1.024V, VDD  2.5V Comparator and DAC -11 — 7 2.048V, VDD  2.5V -11 — 7 4.096V, VDD  4.75 D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See Section7.1 “Power-on Reset Power-on Reset signal (POR)” for details. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation. DS41391D-page 342  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 30-4: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) TPOR(3) Note 1: When NPOR is low, the device is held in Reset. 2: TPOR 1s typical. 3: TVLOW 2.7s typical.  2011 Microchip Technology Inc. DS41391D-page 343

PIC16(L)F1826/27 30.2 DC Characteristics: PIC16(L)F1826/27-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) PIC16LF1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D010 — 7.0 13 A 1.8 FOSC = 32kHz — 9.0 16 A 3.0 LP Oscillator mode, -40°C  TA  +85°C — 7.0 17 A 1.8 FOSC = 32kHz — 9.0 18 A 3.0 LP Oscillator mode, -40°C  TA  +125°C D010 — 24 40 A 1.8 FOSC = 32kHz — 30 48 A 3.0 LP Oscillator mode -40°C  TA  +85°C — 32 55 A 5.0 — 24 43 A 1.8 FOSC = 32kHz — 30 50 A 3.0 LP Oscillator mode -40°C  TA  +125°C — 32 60 A 5.0 D011 — 110 200 A 1.8 FOSC = 1MHz XT Oscillator mode — 200 400 A 3.0 D011 — 160 210 A 1.8 FOSC = 1MHz XT Oscillator mode — 210 400 A 3.0 — 250 450 A 5.0 D012 — 290 475 A 1.8 FOSC = 4MHz XT Oscillator mode — 600 900 A 3.0 D012 — 380 570 A 1.8 FOSC = 4MHz XT Oscillator mode — 650 880 A 3.0 — 680 1100 A 5.0 D013 — 40 80 A 1.8 FOSC = 500kHz EC Oscillator mode, Low-power mode — 70 120 A 3.0 D013 — 60 120 A 1.8 FOSC = 500kHz EC Oscillator mode — 80 180 A 3.0 Low-power mode — 93 200 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins as inputs, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 MHz internal RC oscillator with 4x PLL enabled. 4: 8MHz crystal oscillator with 4x PLL enabled. 5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. DS41391D-page 344  2011 Microchip Technology Inc.

PIC16(L)F1826/27 30.2 DC Characteristics: PIC16(L)F1826/27-I/E (Industrial, Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D014 — 260 475 A 1.8 FOSC = 4MHz EC Oscillator mode, — 550 800 A 3.0 Medium-power mode D014 — 375 655 A 1.8 FOSC = 4MHz EC Oscillator mode — 600 800 A 3.0 Medium-power mode — 650 930 A 5.0 D015 — 3.6 10 A 1.8 FOSC = 31kHz LFINTOSC mode — 7.0 15 A 3.0 D015 — 21 42 A 1.8 FOSC = 31kHz LFINTOSC mode — 27 55 A 3.0 — 28 60 A 5.0 D016 — 110 210 A 1.8 FOSC = 500kHz MFINTOSC mode — 150 250 A 3.0 D016 — 150 250 A 1.8 FOSC = 500kHz MFINTOSC mode — 210 345 A 3.0 — 270 425 A 5.0 D017* — 0.8 1.5 mA 1.8 FOSC = 8MHz HFINTOSC mode — 1.3 2.4 mA 3.0 D017* — 1.0 2.0 mA 1.8 FOSC = 8MHz HFINTOSC mode — 1.5 2.6 mA 3.0 — 1.7 2.8 mA 5.0 D018 — 1.2 2.5 mA 1.8 FOSC = 16MHz HFINTOSC mode — 2.5 3.75 mA 3.0 D018 — 1.7 2.23 mA 1.8 FOSC = 16MHz HFINTOSC mode — 2.7 4.3 mA 3.0 — 3.0 4.6 mA 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins as inputs, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 MHz internal RC oscillator with 4x PLL enabled. 4: 8MHz crystal oscillator with 4x PLL enabled. 5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.  2011 Microchip Technology Inc. DS41391D-page 345

PIC16(L)F1826/27 30.2 DC Characteristics: PIC16(L)F1826/27-I/E (Industrial, Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D019 — 4.0 7.3 mA 3.0 FOSC = 32MHz HFINTOSC mode (Note 3) — 4.4 7.5 mA 3.6 D019 — 4.2 7.3 mA 3.0 FOSC = 32MHz HFINTOSC mode (Note 3) — 4.6 7.5 mA 5.0 D020 — 4.0 6.0 mA 3.0 FOSC = 32MHz HS Oscillator mode (Note 4) — 4.7 7.0 mA 3.6 D020 — 4.2 6.8 mA 3.0 FOSC = 32MHz HS Oscillator mode (Note 4) — 4.9 7.6 mA 5.0 D021 — 410 0.65 mA 1.8 FOSC = 4MHz EXTRC mode (Note 5) — 710 1.25 mA 3.0 D021 — 430 0.695 mA 1.8 FOSC = 4MHz EXTRC mode (Note 5) — 730 1.3 mA 3.0 — 860 1.35 mA 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins as inputs, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 MHz internal RC oscillator with 4x PLL enabled. 4: 8MHz crystal oscillator with 4x PLL enabled. 5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. DS41391D-page 346  2011 Microchip Technology Inc.

PIC16(L)F1826/27 30.3 DC Characteristics: PIC16(L)F1826/27-I/E (Power-Down) Standard Operating Conditions (unless otherwise stated) PIC16LF1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D022 — 0.02 1.0 4.0 A 1.8 WDT, BOR, FVR, and T1OSC — 0.03 1.1 7.0 A 3.0 disabled, all Peripherals Inactive D022 — 15 35 50 A 1.8 WDT, BOR, FVR, and T1OSC — 18 40 60 A 3.0 disabled, all Peripherals Inactive — 19 45 70 A 5.0 D023 — 0.5 1.1 5.0 A 1.8 LPWDT Current (Note 1) — 0.8 2.0 8.0 A 3.0 D023 — 16 35 50 A 1.8 LPWDT Current (Note 1) — 19 40 60 A 3.0 — 20 45 70 A 5.0 D023A — 8.5 23 32 A 1.8 FVR current (Note 1) — 8.5 26 40 A 3.0 D023A — 32 62 66 A 1.8 FVR current (Note 1) — 39 70 80 A 3.0 — 70 110 120 A 5.0 D024 — 8.1 14 20 A 3.0 BOR Current (Note 1) D024 — 34 57 70 A 3.0 BOR Current (Note 1) — 67 100 115 A 5.0 D025 — 0.6 1.5 5.0 A 1.8 T1OSC Current (Note 1) — 0.8 2.5 8.0 A 3.0 D025 — 16 35 50 A 1.8 T1OSC Current (Note 1) — 21 40 60 A 3.0 — 25 45 70 A 5.0 D026 — 0.1 1.1 5.0 A 1.8 A/D Current (Note 1, Note 3), no — 0.1 2.0 8.0 A 3.0 conversion in progress D026 — 16 35 50 A 1.8 A/D Current (Note 1, Note 3), no — 21 40 60 A 3.0 conversion in progress — 25 45 70 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins set to inputs state and tied to VDD. 3: A/D oscillator source is FRC.  2011 Microchip Technology Inc. DS41391D-page 347

PIC16(L)F1826/27 30.3 DC Characteristics: PIC16(L)F1826/27-I/E (Power-Down) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D026A* — 250 — — A 1.8 A/D Current (Note 1, Note 3), — 250 — — A 3.0 conversion in progress D026A* — 280 — — A 1.8 A/D Current (Note 1, Note 3), — 280 — — A 3.0 conversion in progress — 280 — — A 5.0 D027 — 3.5 6 8 A 1.8 Cap Sense Low Power — 7 10 14 A 3.0 Oscillator mode (Note 1) D027 — 4.3 36 38 A 1.8 Cap Sense Low Power — 5.8 39 42 A 3.0 Oscillator mode (Note 1) — 6.3 42 45 A 5.0 D027A — 4.2 8 10 A 1.8 Cap Sense Medium Power — 6 12 15 A 3.0 Oscillator mode (Note 1) D027A — 7.4 38 40 A 1.8 Cap Sense Medium Power — 9.7 42 43 A 3.0 Oscillator mode (Note 1) — 10.4 46 48 A 5.0 D027B — 6 10 15 A 1.8 Cap Sense High Power — 10 14 20 A 3.0 Oscillator mode (Note 1) D027B — 17 44 50 A 1.8 Cap Sense High Power — 41 68 80 A 3.0 Oscillator mode (Note 1) — 50 78 90 A 5.0 D028 — 6.9 11 15 A 1.8 Comparator Current, Low Power — 7.0 13 16 A 3.0 mode, one comparator enabled (Note 1) D028 — 24 45 60 A 1.8 Comparator Current, Low Power — 24.5 60 70 A 3.0 mode, one comparator enabled (Note 1) — 25 65 75 A 5.0 D028A — 7.0 12 16 A 1.8 Comparator Current, Low Power — 7.2 14 17 A 3.0 mode, two comparators enabled (Note 1) D028A — 24 45 60 A 1.8 Comparator Current, Low Power — 24.5 60 70 A 3.0 mode, two comparators enabled (Note 1) — 25 65 75 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins set to inputs state and tied to VDD. 3: A/D oscillator source is FRC. DS41391D-page 348  2011 Microchip Technology Inc.

PIC16(L)F1826/27 30.3 DC Characteristics: PIC16(L)F1826/27-I/E (Power-Down) (Continued) Standard Operating Conditions (unless otherwise stated) PIC16LF1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC16F1826/27 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D028B — 24 32 40 A 1.8 Comparator Current, High Power — 25 35 45 A 3.0 mode, one comparator enabled (Note 1) D028B — 36 60 80 A 1.8 Comparator Current, High Power — 37 63 87 A 3.0 mode, one comparator enabled (Note 1) — 38 65 90 A 5.0 D028C — 40 80 90 A 1.8 Comparator Current, High Power — 41 83 95 A 3.0 mode, two comparators enabled D028C — 43 86 100 A 1.8 Comparator Current, High Power — 44 90 105 A 3.0 mode, two comparators enabled (Note 1) — 45 95 110 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins set to inputs state and tied to VDD. 3: A/D oscillator source is FRC.  2011 Microchip Technology Inc. DS41391D-page 349

PIC16(L)F1826/27 30.4 DC Characteristics: PIC16(L)F1826/27-I/E Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature-40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage I/O PORT: D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V D030A — — 0.15VDD V 1.8V  VDD  4.5V D031 with Schmitt Trigger buffer — — 0.2VDD V 2.0V  VDD  5.5V with I2C™ levels — — 0.3VDD V with SMBus™ levels — — 0.8 V 2.7V  VDD  5.5V D032 MCLR, OSC1 (RC mode)(1) — — 0.2VDD V D033 OSC1 (HS mode) — — 0.3VDD V VIH Input High Voltage I/O ports: — — D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V D040A 0.25VDD + — — V 1.8V  VDD  4.5V 0.8 D041 with Schmitt Trigger buffer 0.8VDD — — V 2.0V  VDD  5.5V with I2C™ levels 0.7VDD — — V with SMBus™ levels 2.1 — — V 2.7V  VDD  5.5V D042 MCLR 0.8VDD — — V D043A OSC1 (HS mode) 0.7VDD — — V D043B OSC1 (RC mode) 0.9VDD — — V (Note 1) IIL Input Leakage Current(2) D060 I/O ports — ± 5 ± 100 nA VSS  VPIN  VDD, Pin at high- impedance at 85°C ± 5 ± 1000 nA 125°C D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD at 85°C IPUR Weak Pull-up Current D070* 25 100 200 VDD = 3.3V, VPIN = VSS 25 140 300 A VDD = 5.0V, VPIN = VSS VOL Output Low Voltage(4) D080 I/O ports IOL = 8mA, VDD = 5V — — 0.6 V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V VOH Output High Voltage(4) D090 I/O ports IOH = 3.5mA, VDD = 5V VDD - 0.7 — — V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode. DS41391D-page 350  2011 Microchip Technology Inc.

PIC16(L)F1826/27 30.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP/RA5 pin 8.0 — 9.0 V (Note 3, Note 4) D111 IDDP Supply Current during — — 10 mA Programming D112 VDD for Bulk Erase 2.7 — VDD V max. D113 VPEW VDD for Write or Row Erase VDD — VDD V min. max. D114 IPPPGM Current on MCLR/VPP during Erase/ — — 1.0 mA Write D115 IDDPGM Current on VDD during Erase/Write — 5.0 mA Data EEPROM Memory D116 ED Byte Endurance 100K — — E/W -40C to +85C D117 VDRW VDD for Read/Write VDD — VDD V min. max. D118 TDEW Erase/Write Cycle Time — 4.0 5.0 ms D119 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D120 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +85°C Cycles before Refresh(2) Program Flash Memory D121 EP Cell Endurance 10K — — E/W -40C to +85C (Note 1) D122 VPR VDD for Read VDD — VDD V min. max. D123 TIW Self-timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Refer to Section11.2 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2.  2011 Microchip Technology Inc. DS41391D-page 351

PIC16(L)F1826/27 30.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance Junction to Ambient 65.5 C/W 18-pin PDIP package 76 C/W 18-pin SOIC package 89.3 C/W 20-pin SSOP package TBD C/W 28-pin UQFN 4x4mm package 31.1 C/W 28-pin QFN 6x6mm package TH02 JC Thermal Resistance Junction to Case 29.5 C/W 18-pin PDIP package 23.5 C/W 18-pin SOIC package 31.1 C/W 20-pin SSOP package TBD C/W 28-pin UQFN 4x4mm package 5 C/W 28-pin QFN 6x6mm package TH03 TJMAX Maximum Junction Temperature 150 C TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Legend: TBD = To Be Determined Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature 3: TJ = Junction Temperature DS41391D-page 352  2011 Microchip Technology Inc.

PIC16(L)F1826/27 30.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDIx sc SCKx do SDO ss SS dt Data in t0 T0CKI io I/O PORT t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 30-5: LOAD CONDITIONS Load Condition Pin Cl Vss Legend: CL = 50 pF for all pins, 15 pF for OSC2 output  2011 Microchip Technology Inc. DS41391D-page 353

PIC16(L)F1826/27 30.8 AC Characteristics: PIC16(L)F1826/27-I/E FIGURE 30-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 30-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz EC Oscillator mode (low) DC — 4 MHz EC Oscillator mode (medium) DC — 20 MHz EC Oscillator mode (high) Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 4 MHz HS Oscillator mode 1 — 20 MHz HS Oscillator mode, VDD > 2.7V DC — 4 MHz RC Oscillator mode, VDD > 2.0V OS02 TOSC External CLKIN Period(1) 27 —  s LP Oscillator mode 250 —  ns XT Oscillator mode 50 —  ns HS Oscillator mode 50 —  ns EC Oscillator mode Oscillator Period(1) — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY — DC ns TCY = FOSC/4 OS04* TosH, External CLKIN High, 2 — — s LP oscillator TosL External CLKIN Low 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TosR, External CLKIN Rise, 0 —  ns LP oscillator TosF External CLKIN Fall 0 —  ns XT oscillator 0 —  ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. DS41391D-page 354  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 30-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Freq. Sym. Characteristic Min. Typ† Max. Units Conditions No. Tolerance OS08 HFOSC Internal Calibrated HFINTOSC 2% — 16.0 — MHz 0°C  TA  +60°C, VDD  2.5V Frequency(2) 3% — 16.0 — MHz 60°C  TA  +85°C, VDD  2.5V 5% — 16.0 — MHz -40°C  TA  +125°C OS08A MFOSC Internal Calibrated MFINTOSC 2% — 500 — kHz 0°C  TA  +60°C, VDD  2.5V Frequency(2) 3% — 500 — kHz 60°C  TA  +85°C, VDD  2.5V 5% — 500 — kHz -40°C  TA  +125°C OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz -40°C  TA  +125°C OS10* TIOSC ST HFINTOSC — — 3.2 8 s Wake-up from Sleep Start-up Time MFINTOSC Wake-up from Sleep Start-up Time — — 24 35 s * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. 3: By design. TABLE 30-3: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 8 MHz F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz F12 TRC PLL Start-up Time (Lock Time) — — 2 ms F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% % * These parameters are characterized but not tested. † Data in “Typ” column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.  2011 Microchip Technology Inc. DS41391D-page 355

PIC16(L)F1826/27 FIGURE 30-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19 DS41391D-page 356  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 30-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS11 TosH2ckL FOSC to CLKOUT (1) — — 70 ns VDD = 3.3-5.0V OS12 TosH2ckH FOSC to CLKOUT (1) — — 72 ns VDD = 3.3-5.0V OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3-5.0V OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns VDD = 3.3-5.0V (I/O in hold time) OS17 TioV2osH Port input valid to Fosc(Q2 cycle) 20 — — ns (I/O in setup time) OS18 TioR Port output rise time(2) — 40 72 ns VDD = 1.8V — 15 32 VDD = 3.3-5.0V OS19 TioF Port output fall time(2) — 28 55 ns VDD = 1.8V — 15 30 VDD = 3.3-5.0V OS20* Tinp INT pin input high or low time 25 — — ns OS21* Tioc Interrupt-on-change new input level 25 — — ns time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode. FIGURE 30-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING Vdd MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low.  2011 Microchip Technology Inc. DS41391D-page 357

PIC16(L)F1826/27 FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS Vdd VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Rese 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to ‘0’. 2ms delay if PWRTE = 0 and VREGEN=1. DS41391D-page 358  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDTLP Low-Power Watchdog Timer 10 16 27 ms VDD = 3.3V-5V Time-out Period (No Prescaler) 1:16 Prescaler used 32 TOST Oscillator Start-up Timer Period(1), (2) — 1024 — Tosc (Note 3) 33* TPWRT Power-up Timer Period, PWRTE=0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low — — 2.0 s or Watchdog Timer Reset 35 VBOR Brown-out Reset Voltage 2.38 2.5 2.73 V BORV=2.5V 1.80 1.9 2.11 BORV=1.9V 36* VHYST Brown-out Reset Hysteresis 0 25 50 mV -40°C to +85°C 37* TBORDC Brown-out Reset DC Response 0 3 35 s VDD  VBOR Time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. FIGURE 30-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1  2011 Microchip Technology Inc. DS41391D-page 359

PIC16(L)F1826/27 TABLE 30-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns Period 30 or TCY + 40 N Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range 32.4 32.768 33.1 kHz (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync Increment mode * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure30.5 for load conditions. TABLE 30-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. CC01* TccL CCPx Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCPx Input Period 3TCY + 40 — — ns N = prescale value (1, 4 or 16) N * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41391D-page 360  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 30-8: PIC16(L)F1826/27 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature Tested at +25°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — — ±1.7 LSb VREF = 3.0V AD03 EDL Differential Error — — ±1 LSb No missing codes VREF = 3.0V AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V AD05 EGN Gain Error — — ±2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage(3) — — VDD V VREF = (VREF+ minus VREF-) (NOTE 5) AD07 VAIN Full-Scale Range — — VREF V AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01F capacitor is Analog Voltage Source present on input pin. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input. 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. 5: FVR voltage selected must be 2.048V or 4.096V. TABLE 30-9: PIC16(L)F1826/27 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD130* TAD A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal RC Oscillator 1.0 2.5 6.0 s ADCS<1:0> = 11 (ADRC mode) Period AD131 TCNV Conversion Time (not including — 11 — TAD Set GO/DONE bit to conversion Acquisition Time)(1) complete AD132* TACQ Acquisition Time — 5.0 — s * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle.  2011 Microchip Technology Inc. DS41391D-page 361

PIC16(L)F1826/27 FIGURE 30-12: PIC16(L)F1826/27 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 1 Tcy AD134 (TOSC/2(1)) AD131 Q4 AD130 A/D CLK A/D Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 Tcy GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. FIGURE 30-13: PIC16(L)F1826/27 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 Tcy AD131 Q4 AD130 A/D CLK A/D Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 Tcy GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. DS41391D-page 362  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 30-10: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param Sym. Characteristics Min. Typ. Max. Units Comments No. CM01 Vioff Input Offset Voltage — ±7.5 ±60 mV High Power Mode CM02 Vicm Input Common Mode Voltage 0 — VDD V CM03* CMRR Common Mode Rejection Ratio — 50 — dB CM04A Response Time Rising Edge — 400 800 ns High Power Mode CM04B Response Time Falling Edge — 200 400 ns High Power Mode Tresp CM04C Response Time Rising Edge — 1200 — ns Low Power Mode CM04D Response Time Falling Edge — 550 — ns CM05* Tmc2ov Comparator Mode Change to — — 10 s Output Valid CM06 Chyster Comparator Hysteresis — 65 — mV Hysteresis ON * These parameters are characterized but not tested. TABLE 30-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param Sym. Characteristics Min. Typ. Max. Units Comments No. DAC01* CLSB Step Size — VDD/32 — V DAC02* CACC Absolute Accuracy — —  1/2 LSb DAC03* CR Unit Resistor Value (R) — 5000 —  DAC04* CST Settling Time(1) — — 10 s * These parameters are characterized but not tested. Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.  2011 Microchip Technology Inc. DS41391D-page 363

PIC16(L)F1826/27 FIGURE 30-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US120 US122 Note: Refer to Figure30-5 for load conditions. TABLE 30-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. US120 TCKH2DTV SYNC XMIT (Master and Slave) 3.0-5.5V — 80 ns Clock high to data-out valid 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time 3.0-5.5V — 45 ns (Master mode) 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns FIGURE 30-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure30-5 for load conditions. TABLE 30-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK  (DT hold time) 10 — ns US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns DS41391D-page 364  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 30-16: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SCKx (CKP = 1) SP79 SP78 SP80 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure30-5 for load conditions. FIGURE 30-17: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SSx SP81 SCKx (CKP = 0) SP71 SP72 SP79 SP73 SCKx (CKP = 1) SP80 SP78 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure30-5 for load conditions.  2011 Microchip Technology Inc. DS41391D-page 365

PIC16(L)F1826/27 FIGURE 30-18: SPI SLAVE MODE TIMING (CKE=0) SSx SP70 SCKx SP83 (CKP = 0) SP71 SP72 SP78 SP79 SCKx (CKP = 1) SP79 SP78 SP80 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SP77 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure30-5 for load conditions. FIGURE 30-19: SPI SLAVE MODE TIMING (CKE=1) SP82 SSx SP70 SCKx SP83 (CKP = 0) SP71 SP72 SCKx (CKP = 1) SP80 SDOx MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure30-5 for load conditions. DS41391D-page 366  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 30-14: SPI MODE REQUIREMENTS Param Symbol Characteristic Min. Typ† Max. Units Conditions No. SP70* TSSL2SCH, SSx to SCKx or SCKx input TCY — — ns TSSL2SCL SP71* TSCH SCKx input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCKx input low time (Slave mode) TCY + 20 — — ns SP73* TDIV2SCH, Setup time of SDIx data input to SCKx edge 100 — — ns TDIV2SCL SP74* TSCH2DIL, Hold time of SDIx data input to SCKx edge 100 — — ns TSCL2DIL SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns 1.8-5.5V — 25 50 ns SP76* TDOF SDOx data output fall time — 10 25 ns SP77* TSSH2DOZ SSx to SDOx output high-impedance 10 — 50 ns SP78* TSCR SCKx output rise time 3.0-5.5V — 10 25 ns (Master mode) 1.8-5.5V — 25 50 ns SP79* TSCF SCKx output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, SDOx data output valid after 3.0-5.5V — — 50 ns TSCL2DOV SCKx edge 1.8-5.5V — — 145 ns SP81* TDOV2SCH, SDOx data output setup to SCKx edge Tcy — — ns TDOV2SCL SP82* TSSL2DOV SDOx data output valid after SS edge — — 50 ns SP83* TSCH2SSH, SSx after SCKx edge 1.5TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-20: I2C™ BUS START/STOP BITS TIMING SCLx SP91 SP93 SP90 SP92 SDAx Start Stop Condition Condition Note: Refer to Figure30-5 for load conditions.  2011 Microchip Technology Inc. DS41391D-page 367

PIC16(L)F1826/27 FIGURE 30-21: I2C™ BUS DATA TIMING SP103 SP100 SP102 SP101 SCLx SP90 SP106 SP107 SP91 SP92 SDAx In SP110 SP109 SP109 SDAx Out Note: Refer to Figure30-5 for load conditions. TABLE 30-15: I2C™ BUS START/STOP BITS REQUIREMENTS Param Symbol Characteristic Min. Typ Max. Units Conditions No. SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — Start condition SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first Hold time 400 kHz mode 600 — — clock pulse is generated SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. DS41391D-page 368  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TABLE 30-16: I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSPx module 1.5TCY — — SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSPx module 1.5TCY — — SP102* TR SDAx and SCLx 100 kHz mode — 1000 ns rise time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF SP103* TF SDAx and SCLx fall 100 kHz mode — 250 ns time 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from 10-400 pF SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s SP107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2) time 400 kHz mode 100 — ns SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free before a new transmission 400 kHz mode 1.3 — s can start SP111 CB Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx sig- nal, it must output the next data bit to the SDAx line TR max. + TSU:DAT=1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released.  2011 Microchip Technology Inc. DS41391D-page 369

PIC16(L)F1826/27 TABLE 30-17: CAP SENSE OSCILLATOR SPECIFICATIONS Param. Symbol Characteristic Min. Typ† Max. Units Conditions No. CS01 ISRC Current Source High -3 -8 -15 A Medium -0.8 -1.5 -3 A Low -0.1 -0.3 -0.4 A CS02 ISNK Current Sink High 2.5 7.5 14 A Medium 0.6 1.5 2.9 A Low 0.1 0.25 0.6 A CS03 VCTH Cap Threshold — 0.8 — mV CS04 VCTL Cap Threshold — 0.4 — mV CS05 VCHYST CAP HYSTERESIS High 350 525 725 mV (VCTH - VCTL) Medium 250 375 500 mV Low 175 300 425 mV * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-22: CAP SENSE OSCILLATOR VCTH VCTL ISRC ISNK Enabled Enabled DS41391D-page 370  2011 Microchip Technology Inc.

PIC16(L)F1826/27 31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean+3) or (mean-3) respectively, where  is a standard deviation, over each temperature range. FIGURE 31-1: VOH VS. IOH OVER TEMPERATURE (VDD = 5.0V) 6 Max: Maximum + 3 Min: Minimum - 3 5 4 V) (H 3 O V Min. 125°C Typ. 25°C Max. -40°C 2 1 0 0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 -22.5 -25 -27.5 -30 IOH(mA) FIGURE 31-2: VOL VS. IOL OVER TEMPERATURE (VDD = 5.0V) 5 Max. 125°C Typ. 25°C Min. -40°C 4 3 )V ( L 2 O V 1 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 IOL(mA)  2011 Microchip Technology Inc. DS41391D-page 371

PIC16(L)F1826/27 FIGURE 31-3: VOH VS. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 Max: Maximum + 3 Min: Minimum -3 3 V) m )V 2.52 Hysterisis ( ( H Min 125°C Typ 25°C Max -40°C O V 1.5 1 0.5 0 0 -2.5 -5 -7.5 -10 -12.5 -15 IOH(mA) FIGURE 31-4: VOL VS. IOL OVER TEMPERATURE (VDD = 3.0V) 3 Max: Maximum + 3 Min: Minimum -3 2.5 2 Max 125°C Typ 25°C Min -40°C V) ( L 1.5 O V 1 0.5 0 0 5 10 15 20 25 30 IOL(mA) DS41391D-page 372  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 31-5: VOH VS. IOH OVER TEMPERATURE (VDD = 1.8V) 2 Max: Maximum + 3 1.8 Min: Minimum -3 1.6 Max -40°C 1.4 1.2 Typ 25°C )V ( HO 1 Min 125°C V 0.8 0.6 0.4 0.2 0 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 IOH(mA) FIGURE 31-6: VOL VS. IOL OVER TEMPERATURE (VDD = 1.8V) 1.8 Max: Maximum + 3 1.6 Min: Minimum -3 Max 125°C Typ 25°C Min -40°C 1.4 1.2 )V 1 ( LO 0.8 V 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 8 9 10 IOL(mA)  2011 Microchip Technology Inc. DS41391D-page 373

PIC16(L)F1826/27 FIGURE 31-7: PIC16(L)F1826/27 RESET VOLTAGE (BOR = 1.9V) 2.100 Max: High Power + 3 Min: Low Power -3 2.050 2.000 Max )V ( e 1.950 g a otl V 1.900 Min 1.850 1.800 -40°C 25°C 85°C 125°C Temperature FIGURE 31-8: PIC16(L)F1826/27 RESET VOLTAGE (BOR = 1.9V) 2.650 Max: High Power + 3 Min: Low Power -3 Max 2.600 2.550 V) e( 2.500 g toal Min V 2.450 2.400 2.350 -40°C 25°C 85°C 125°C Temperature DS41391D-page 374  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 31-9: PIC16(L)F1826/27 POR RELEASE 1.7 Max: High Power + 3 1.68 MMianx:: LMoawx Pimouwmer + - 33s 1.66 Max 1.64 V) e( 1.62 g Voatl 1.6 Typical e s a 1.58 e el R 1.56 Min 1.54 1.52 1.5 -40°C 25°C 85°C 125°C Temperature (Celsius) FIGURE 31-10: PIC16(L)F1826/27 COMPARATOR HYSTERISIS, HIGH-POWER MODE 90 Max: Maximum + 3 Min: Minimum -3 80 Max 125°C 70 60 V) m erisis ( 50 Typical 25°C st y 40 H 30 20 10 Min -40°C 0 1.8 3 3.6 5.5 VDD (Volts)  2011 Microchip Technology Inc. DS41391D-page 375

PIC16(L)F1826/27 FIGURE 31-11: PIC16(L)F1826/27 COMPARATOR HYSTERISIS, LOW-POWER MODE 16 Max: Maximum + 3 Min: Minimum -3 Max 125°C 14 12 V) m s ( 10 si steri Typical 25°C Hy 8 6 4 Min -40°C 2 0 1.8 5.5 VDD(Volts) FIGURE 31-12: PIC16(L)F1826/27 COMPARATOR OFFSET, HIGH-POWER MODE (VDD = 5.5V) 60 Max: Maximum + 3 Min: Minimum -3 40 20 Max V) m et ( 0 s Typical Off -20 Min -40 -60 0.2 1 1.8 2.6 3.4 4.2 5 Common Mode Voltage (Volts) DS41391D-page 376  2011 Microchip Technology Inc.

PIC16(L)F1826/27 FIGURE 31-13: PIC16(L)F1826/27 COMPARATOR RESPONSE TIME, HIGH-POWER MODE 350 Max: High Power + 3 MMina:x L: oMwa xPimowuemr +- 33s 300 Max 250 s) nd 200 o c e S n e ( 150 m Typ Ti 100 50 0 1.8 2 2.5 3 3.6 5.5 VDD(Volts) FIGURE 31-14: TYPICAL COMPARATOR RESPONSE TIME OVER TEMP, HIGH-POWER MODE 170 -40°C 165 160 s) 25°C nd155 o c e S n 85°C e (150 m Ti 125°C 145 140 135 1.8 2 2.5 3 3.6 5.5 VDD (Volts)  2011 Microchip Technology Inc. DS41391D-page 377

PIC16(L)F1826/27 NOTES: DS41391D-page 378  2011 Microchip Technology Inc.

PIC16(L)F1826/27 32.0 DEVELOPMENT SUPPORT 32.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2011 Microchip Technology Inc. DS41391D-page 379

PIC16(L)F1826/27 32.2 MPLAB C Compilers for Various 32.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 32.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 32.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 32.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS41391D-page 380  2011 Microchip Technology Inc.

PIC16(L)F1826/27 32.7 MPLAB SIM Software Simulator 32.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 32.10 PICkit 3 In-Circuit Debugger/ Programmer and 32.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2011 Microchip Technology Inc. DS41391D-page 381

PIC16(L)F1826/27 32.11 PICkit 2 Development 32.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 32.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS41391D-page 382  2011 Microchip Technology Inc.

PIC16(L)F1826/27 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX PIC16F1826-I/P XXXXXXXXXXXXXXXXX 1110017 YYWWNNN 18-Lead SOIC (.300”) Example XXXXXXXXXXXX PIC16C1826-I XXXXXXXXXXXX /SO XXXXXXXXXXXX 1110017 YYWWNNN 20-Lead SSOP Example XXXXXXXXXXX PIC16F1827 XXXXXXXXXXX -I/SS YYWWNNN 1110017 28-Lead QFN/UQFN Example XXXXXXXX 16F1827 XXXXXXXX /ML YYWWNNN 1110017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PICmicro® device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2011 Microchip Technology Inc. DS41391D-page 383

PIC16(L)F1826/27 33.2 Package Details The following sections give the technical details of the packages. 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(cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:30)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)-(cid:4)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)<<(cid:4) (cid:20)(cid:24)(cid:4)(cid:4) (cid:20)(cid:24)(cid:3)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:23) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:29) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:4)(cid:5)1 DS41391D-page 384  2011 Microchip Technology Inc.

PIC16(L)F1826/27 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc. DS41391D-page 385

PIC16(L)F1826/27 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41391D-page 386  2011 Microchip Technology Inc.

PIC16(L)F1826/27 !(cid:24)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)"#$(cid:14)(cid:19)%(cid:9)"(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)&(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)""(cid:21)(cid:9)(cid:22)(cid:9)’((cid:23)(cid:24)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)""&(cid:10)(cid:30)(cid:9) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 e b c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:24)(cid:4) (cid:5)(cid:20)(cid:3)(cid:4) (cid:5)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:3)1  2011 Microchip Technology Inc. DS41391D-page 387

PIC16(L)F1826/27 !(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9))(cid:17)(cid:7)(cid:8)(cid:9)*(cid:11)(cid:7)(cid:13)+(cid:9)(cid:31)(cid:27)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)%(cid:7),(cid:6)(cid:9)(cid:20)-(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)./.(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29))*(cid:31)(cid:30) 0(cid:14)(cid:13)#(cid:9)(cid:24)(’’(cid:9)(cid:25)(cid:25)(cid:9)1(cid:27)(cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19),(cid:13)# (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)- (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# A (cid:4)(cid:20)(cid:3)(cid:4) = = (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)(cid:29)1 DS41391D-page 388  2011 Microchip Technology Inc.

PIC16(L)F1826/27 !(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9))(cid:17)(cid:7)(cid:8)(cid:9)*(cid:11)(cid:7)(cid:13)+(cid:9)(cid:31)(cid:27)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)%(cid:7),(cid:6)(cid:9)(cid:20)-(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)./.(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29))*(cid:31)(cid:30) 0(cid:14)(cid:13)#(cid:9)(cid:24)(’’(cid:9)(cid:25)(cid:25)(cid:9)1(cid:27)(cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19),(cid:13)# (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2011 Microchip Technology Inc. DS41391D-page 389

PIC16(L)F1826/27 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41391D-page 390  2011 Microchip Technology Inc.

PIC16(L)F1826/27 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc. DS41391D-page 391

PIC16(L)F1826/27 NOTES: DS41391D-page 392  2011 Microchip Technology Inc.

PIC16(L)F1826/27 APPENDIX A: DATA SHEET APPENDIX B: MIGRATING FROM REVISION HISTORY OTHER PIC® DEVICES Revision A This section provides comparisons when migrating Original release (06/2009) from other similar PIC® devices to the PIC16(L)F1826/27 family of devices. Revision B (08/09) B.1 PIC16F648A to PIC16(L)F1827 Revised Tables 5-3, 6-2, 12-2, 12-3; Updated Electrical Specifications; Added UQFN Package; Added SOIC TABLE B-1: FEATURE COMPARISON and QFN Land Patterns; Updated Product ID section. Feature PIC16F648A PIC16(L)F1827 Revision C (06/10) Max. Operating 20MHz 32MHz Speed Updated Electrical Specification and included Max. Program 4K 4K Enhanced Core Golden Chapters. Memory (Words) Max. SRAM (Bytes) 256 384 Revision D (04/11) Max. EEPROM 256 256 Added Char Data to release Final data sheet. (Bytes) A/D Resolution 10-bit 10-bit Timers (8/16-bit) 2/1 4/1 Brown-out Reset Y Y Internal Pull-ups RB<7:0> RB<7:0>, RA5 Interrupt-on-Change RB<7:4> RB<7:0>, Edge Selectable Comparator 2 2 AUSART/EUSART 1/0 0/2 Extended WDT N Y Software Control N Y Option of WDT/BOR INTOSC 48 kHz or 31kHz - Frequencies 4 MHz 32MHz Clock Switching Y Y Capacitive Sensing N Y CCP/ECCP 2/0 2/2 Enhanced PIC16 N Y CPU MSSPx/SSPx 0 2/0 Reference Clock N Y Data Signal N Y Modulator SR Latch N Y Voltage Reference N Y DAC Y Y  2011 Microchip Technology Inc. DS41391D-page 393

PIC16(L)F1826/27 NOTES: DS41391D-page 394  2011 Microchip Technology Inc.

PIC16(L)F1826/27 INDEX A Bank 6................................................................................31 Bank 7................................................................................31 A/D Bank 8................................................................................32 Specifications............................................................361 Bank 9................................................................................33 Absolute Maximum Ratings..............................................339 BAUDCON Register.........................................................296 AC Characteristics BF.............................................................................266, 268 Industrial and Extended............................................354 BF Status Flag..........................................................266, 268 Load Conditions........................................................353 Block Diagram ACKSTAT.........................................................................266 Capacitive Sensing...................................................315 ACKSTAT Status Flag......................................................266 Block Diagrams ADC..................................................................................139 (CCP) Capture Mode Operation...............................204 Acquisition Requirements.........................................149 ADC..........................................................................139 Associated registers..................................................151 ADC Transfer Function.............................................150 Block Diagram...........................................................139 Analog Input Model...........................................150, 169 Calculating Acquisition Time.....................................149 CCP PWM................................................................208 Channel Selection.....................................................140 Clock Source..............................................................52 Configuration.............................................................140 Comparator...............................................................164 Configuring Interrupt.................................................144 Compare...................................................................206 Conversion Clock......................................................140 Crystal Operation..................................................54, 55 Conversion Procedure..............................................144 Digital-to-Analog Converter (DAC)...........................154 Internal Sampling Switch (RSS) IMPEDANCE..............149 EUSART Receive.....................................................286 Interrupts...................................................................142 EUSART Transmit....................................................285 Operation..................................................................143 External RC Mode......................................................55 Operation During Sleep............................................143 Fail-Safe Clock Monitor (FSCM).................................63 Port Configuration.....................................................140 Generic I/O Port........................................................117 Reference Voltage (VREF).........................................140 Interrupt Logic.............................................................81 Source Impedance....................................................149 On-Chip Reset Circuit.................................................73 Special Event Trigger................................................143 PIC16F/LF1826/27.....................................................10 Starting an A/D Conversion......................................142 PIC16F193X/LF193X.................................................16 ADCON0 Register.......................................................28, 145 PWM (Enhanced).....................................................212 ADCON1 Register.......................................................28, 146 Resonator Operation..................................................54 ADDFSR...........................................................................329 Timer0..............................................................173, 174 ADDWFC..........................................................................329 Timer1......................................................................177 ADRESH Register...............................................................28 Timer1 Gate..............................................182, 183, 184 ADRESH Register (ADFM = 0).........................................147 Timer2/4/6................................................................189 ADRESH Register (ADFM = 1).........................................148 Voltage Reference....................................................135 ADRESL Register (ADFM = 0)..........................................147 Voltage Reference Output Buffer Example..............154 ADRESL Register (ADFM = 1)..........................................148 BORCON Register..............................................................75 Alternate Pin Function.......................................................118 BRA..................................................................................330 Analog-to-Digital Converter. See ADC Break Character (12-bit) Transmit and Receive...............305 ANSELA Register.............................................................123 Brown-out Reset (BOR)......................................................75 ANSELB Register.............................................................128 Specifications...........................................................359 APFCON0 Register...........................................................119 Timing and Characteristics.......................................358 APFCON1 Register...........................................................119 Assembler C MPASM Assembler...................................................380 C Compilers Automatic Context Saving...................................................85 MPLAB C18..............................................................380 B CALL.................................................................................331 CALLW.............................................................................331 Bank 10...............................................................................33 Capacitive Sensing...........................................................315 Bank 11...............................................................................33 Associated registers w/ Capacitive Sensing.............319 Bank 12.........................................................................33, 34 Specifications...........................................................370 Bank 13.........................................................................33, 34 Capture Module. See Enhanced Capture/Compare/PWM Bank 14...............................................................................33 (ECCP) Bank 15...............................................................................33 Capture/Compare/PWM...................................................203 Bank 16...............................................................................33 Capture/Compare/PWM (CCP) Bank 17...............................................................................33 Associated Registers w/ Capture.............................205 Bank 18...............................................................................33 Associated Registers w/ Compare...........................207 Bank 19...............................................................................33 Associated Registers w/ PWM.........................211, 225 Bank 20...............................................................................33 Capture Mode...........................................................204 Bank 21...............................................................................33 CCPx Pin Configuration............................................204 Bank 22...............................................................................33 Compare Mode.........................................................206 Bank 23...............................................................................34 CCPx Pin Configuration....................................206 Bank 31...............................................................................35 Software Interrupt Mode...........................204, 206  2011 Microchip Technology Inc. DS41391D-page 395

PIC16(L)F1826/27 Special Event Trigger........................................206 Customer Change Notification Service.............................403 Timer1 Mode Resource............................204, 206 Customer Notification Service..........................................403 Prescaler...................................................................204 Customer Support.............................................................403 PWM Mode D Duty Cycle.........................................................209 Effects of Reset.................................................211 DACCON0 (Digital-to-Analog Converter Control 0) Example PWM Frequencies and Register....................................................................156 Resolutions, 20 MHZ................................210 DACCON1 (Digital-to-Analog Converter Control 1) Example PWM Frequencies and Register....................................................................156 Resolutions, 32 MHZ................................210 Data EEPROM Memory....................................................101 Example PWM Frequencies and Associated Registers................................................116 Resolutions, 8 MHz...................................210 Code Protection........................................................102 Operation in Sleep Mode..................................211 Reading....................................................................102 Resolution.........................................................210 Writing......................................................................102 System Clock Frequency Changes...................211 Data Memory......................................................................20 PWM Operation........................................................208 DC and AC Characteristics...............................................371 PWM Overview.........................................................208 Graphs and Tables...................................................371 PWM Period..............................................................209 DC Characteristics PWM Setup...............................................................209 Extended and Industrial............................................350 CCP1CON Register......................................................30, 31 Industrial and Extended............................................342 CCPR1H Register.........................................................30, 31 Development Support.......................................................379 CCPR1L Register..........................................................30, 31 Device Configuration..........................................................43 CCPTMRS Register..........................................................227 Code Protection..........................................................47 CCPxAS Register..............................................................228 Configuration Word.....................................................43 CCPxCON (ECCPx) Register...........................................226 User ID.................................................................47, 48 CLKRCON Register............................................................70 Device ID Register..............................................................49 Clock Accuracy with Asynchronous Operation.................294 Device Overview.............................................................9, 97 Clock Sources Digital-to-Analog Converter (DAC)...................................153 External Modes...........................................................53 Associated Registers................................................156 EC.......................................................................53 Effects of a Reset.....................................................154 HS.......................................................................53 Specifications...........................................................363 LP........................................................................53 E OST.....................................................................54 RC.......................................................................55 ECCP/CCP. See Enhanced Capture/Compare/PWM XT.......................................................................53 EEADR Registers.............................................................101 Internal Modes............................................................56 EEADRH Registers...........................................................101 HFINTOSC..........................................................56 EEADRL Register.............................................................113 Internal Oscillator Clock Switch Timing...............58 EEADRL Registers...........................................................101 LFINTOSC..........................................................57 EECON1 Register.....................................................101, 115 MFINTOSC.........................................................56 EECON2 Register.....................................................101, 116 Clock Switching...................................................................60 EEDATH Register.....................................................113, 114 CMOUT Register...............................................................171 EEDATL Register.............................................................113 CMxCON0 Register..........................................................170 EEPROM Data Memory CMxCON1 Register..........................................................171 Avoiding Spurious Write...........................................102 Code Examples Write Verify...............................................................112 A/D Conversion.........................................................144 Effects of Reset Changing Between Capture Prescalers....................204 PWM mode...............................................................211 Initializing PORTA.....................................................117 Electrical Specifications....................................................339 Write Verify...............................................................112 Enhanced Capture/Compare/PWM (ECCP).....................203 Writing to Flash Program Memory............................110 Enhanced PWM Mode..............................................212 Comparator Auto-Restart.....................................................221 Associated Registers................................................172 Auto-shutdown..................................................220 Operation..................................................................163 Direction Change in Full-Bridge Output Mode..218 Comparator Module..........................................................163 Full-Bridge Application......................................216 Cx Output State Versus Input Conditions.................166 Full-Bridge Mode..............................................216 Comparator Specifications................................................363 Half-Bridge Application.....................................215 Comparators Half-Bridge Application Examples....................222 C2OUT as T1 Gate...................................................179 Half-Bridge Mode..............................................215 Compare Module. See Enhanced Capture/Compare/ Output Relationships (Active-High and PWM (ECCP) Active-Low)...............................................213 CONFIG1 Register..............................................................44 Output Relationships Diagram..........................214 CONFIG2 Register..............................................................46 Programmable Dead Band Delay.....................222 Core Function Register.......................................................27 Shoot-through Current......................................222 CPSCON0 Register..........................................................318 Start-up Considerations....................................224 CPSCON1 Register..........................................................319 Specifications...........................................................360 Enhanced Mid-Range CPU................................................15 DS41391D-page 396  2011 Microchip Technology Inc.

PIC16(L)F1826/27 Enhanced Universal Synchronous Asynchronous Transmission....................................................266 Receiver Transmitter (EUSART)...............................285 Multi-Master Communication, Bus Collision and Errata....................................................................................8 Arbitration.........................................................271 EUSART...........................................................................285 Multi-Master Mode....................................................271 Associated Registers Read/Write Bit Information (R/W Bit)........................247 Baud Rate Generator........................................298 Slave Mode Asynchronous Mode.................................................287 Transmission....................................................252 12-bit Break Transmit and Receive..................305 Sleep Operation........................................................271 Associated Registers Stop Condition Timing..............................................270 Receive.....................................................293 INDF Register.....................................................................27 Transmit....................................................289 Indirect Addressing.............................................................39 Auto-Wake-up on Break...................................303 Instruction Format.............................................................326 Baud Rate Generator (BRG)............................297 Instruction Set...................................................................325 Clock Accuracy.................................................294 ADDLW.....................................................................329 Receiver............................................................290 ADDWF....................................................................329 Setting up 9-bit Mode with Address Detect.......292 ADDWFC..................................................................329 Transmitter........................................................287 ANDLW.....................................................................329 Baud Rate Generator (BRG) ANDWF....................................................................329 Auto Baud Rate Detect.....................................302 BRA..........................................................................330 Baud Rate Error, Calculating............................297 CALL.........................................................................331 Baud Rates, Asynchronous Modes..................299 CALLW.....................................................................331 Formulas...........................................................298 LSLF.........................................................................333 High Baud Rate Select (BRGH Bit)..................297 LSRF........................................................................333 Synchronous Master Mode...............................306, 311 MOVF.......................................................................333 Associated Registers MOVIW.....................................................................334 Receive.....................................................310 MOVLB.....................................................................334 Transmit....................................................308 MOVWI.....................................................................335 Reception..........................................................309 OPTION....................................................................335 Transmission....................................................306 RESET......................................................................335 Synchronous Slave Mode SUBWFB..................................................................337 Associated Registers TRIS.........................................................................338 Receive.....................................................312 BCF..........................................................................330 Transmit....................................................311 BSF...........................................................................330 Reception..........................................................312 BTFSC......................................................................330 Transmission....................................................311 BTFSS......................................................................330 Extended Instruction Set CALL.........................................................................331 ADDFSR...................................................................329 CLRF........................................................................331 CLRW.......................................................................331 F CLRWDT..................................................................331 Fail-Safe Clock Monitor.......................................................63 COMF.......................................................................331 Fail-Safe Condition Clearing.......................................63 DECF........................................................................331 Fail-Safe Detection.....................................................63 DECFSZ...................................................................332 Fail-Safe Operation.....................................................63 GOTO.......................................................................332 Reset or Wake-up from Sleep.....................................63 INCF.........................................................................332 Firmware Instructions........................................................325 INCFSZ.....................................................................332 Fixed Voltage Reference (FVR) IORLW......................................................................332 Associated Registers................................................136 IORWF......................................................................332 Flash Program Memory....................................................101 MOVLW....................................................................334 Erasing......................................................................107 MOVWF....................................................................334 Modifying...................................................................111 NOP..........................................................................335 Writing.......................................................................107 RETFIE.....................................................................336 FSR Register......................................................................27 RETLW.....................................................................336 FVRCON (Fixed Voltage Reference Control) Register.....136 RETURN...................................................................336 RLF...........................................................................336 I RRF..........................................................................337 I2C Mode (MSSPx) SLEEP......................................................................337 Acknowledge Sequence Timing................................270 SUBLW.....................................................................337 Bus Collision SUBWF.....................................................................337 During a Repeated Start Condition...................275 SWAPF.....................................................................338 During a Stop Condition....................................276 XORLW....................................................................338 Effects of a Reset......................................................271 XORWF....................................................................338 I2C Clock Rate w/BRG..............................................278 INTCON Register................................................................86 Master Mode Internal Oscillator Block Operation..........................................................262 INTOSC Reception..........................................................268 Specifications...................................................355 Start Condition Timing..............................264, 265  2011 Microchip Technology Inc. DS41391D-page 397

PIC16(L)F1826/27 Internal Sampling Switch (RSS) IMPEDANCE......................149 XT...............................................................................51 Internet Address................................................................403 Oscillator Parameters.......................................................355 Interrupt-On-Change.........................................................131 Oscillator Specifications....................................................354 Associated Registers................................................133 Oscillator Start-up Timer (OST) Interrupts.............................................................................81 Specifications...........................................................359 ADC..........................................................................144 Oscillator Switching Associated registers w/ Interrupts...............................94 Fail-Safe Clock Monitor..............................................63 Configuration Word w/ Clock Sources........................67 Two-Speed Clock Start-up..........................................61 Configuration Word w/ PORTA.................................124 OSCSTAT Register............................................................66 Configuration Word w/ Reference Clock Sources.......71 OSCTUNE Register............................................................67 TMR1........................................................................181 P INTOSC Specifications.....................................................355 IOCBF Register.................................................................132 P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/ IOCBN Register................................................................132 PWM (ECCP)............................................................212 IOCBP Register.................................................................132 Packaging.........................................................................383 Marking.....................................................................383 L PDIP Details.............................................................384 LATA Register...................................................................122 PCL and PCLATH...............................................................16 LATB Register...................................................................127 PCL Register......................................................................27 Load Conditions................................................................353 PCLATH Register...............................................................27 LSLF..................................................................................333 PCON Register.............................................................28, 79 LSRF.................................................................................333 PIE1 Register................................................................28, 87 PIE2 Register......................................................................88 M PIE3 Register......................................................................89 Master Synchronous Serial Port. See MSSPx PIE4 Register......................................................................90 MCLR..................................................................................76 Pin Diagram Internal........................................................................76 PIC16F/LF1826/27, 18-pin PDIP/SOIC........................4 MDCARH Register............................................................200 PIC16F/LF1826/27, 28-pin QFN/UQFN........................5 MDCARL Register.............................................................201 Pinout Descriptions MDCON Register..............................................................198 PIC16F/LF1826/27.....................................................11 MDSRC Register...............................................................199 PIR1 Register...............................................................28, 91 Memory Organization..........................................................17 PIR2 Register...............................................................28, 92 Data............................................................................20 PIR3 Register.....................................................................93 Program......................................................................17 PIR4 Register.....................................................................94 Microchip Internet Web Site..............................................403 PORTA.............................................................................120 Migrating from other PIC Microcontroller Devices.............393 ANSELA Register.....................................................120 MOVIW..............................................................................334 Associated Registers................................................124 MOVLB..............................................................................334 PORTA Register...................................................28, 29 MOVWI..............................................................................335 Specifications...........................................................357 MPLAB ASM30 Assembler, Linker, Librarian...................380 PORTA Register...............................................................122 MPLAB Integrated Development Environment Software..379 PORTB.............................................................................125 MPLAB PM3 Device Programmer.....................................382 Additional Pin Functions MPLAB REAL ICE In-Circuit Emulator System.................381 Weak Pull-up....................................................127 MPLINK Object Linker/MPLIB Object Librarian................380 ANSELB Register.....................................................125 MSSPx..............................................................................231 Associated Registers................................................129 I2C Mode...................................................................242 Interrupt-on-Change.................................................125 I2C Mode Operation..................................................244 P1B/P1C/P1D.See Enhanced Capture/Compare/ SPI Mode..................................................................234 PWM+ (ECCP+)...............................................125 SSPxBUF Register...................................................237 Pin Descriptions and Diagrams................................129 SSPxSR Register......................................................237 PORTB Register...................................................28, 29 PORTB Register...............................................................127 O Power-Down Mode (Sleep).................................................95 OPCODE Field Descriptions.............................................325 Associated Registers..........................................96, 201 OPTION............................................................................335 Power-on Reset..................................................................74 OPTION_REG Register....................................................176 Power-up Time-out Sequence............................................76 OSCCON Register..............................................................65 Power-up Timer (PWRT)....................................................74 Oscillator Specifications...........................................................359 Associated Registers..................................................67 PR2 Register................................................................28, 32 Oscillator Module................................................................51 Precision Internal Oscillator Parameters..........................355 ECH............................................................................51 Program Memory................................................................17 ECL.............................................................................51 Map and Stack (PIC16F/LF1826)...............................18 ECM............................................................................51 Map and Stack (PIC16F/LF1826/27)....................17, 18 HS...............................................................................51 Programming, Device Instructions....................................325 INTOSC......................................................................51 PSTRxCON Register........................................................230 LP................................................................................51 PWM (ECCP Module) RC...............................................................................51 PWM Steering...........................................................223 DS41391D-page 398  2011 Microchip Technology Inc.

PIC16(L)F1826/27 Steering Synchronization..........................................224 PIE3 (Peripheral Interrupt Enable 3)..........................89 PWM Mode. See Enhanced Capture/Compare/PWM......212 PIE4 (Peripheral Interrupt Enable 4)..........................90 PWM Steering...................................................................223 PIR1 (Peripheral Interrupt Register 1)........................91 PWMxCON Register.........................................................229 PIR2 (Peripheral Interrupt Request 2)........................92 PIR3 (Peripheral Interrupt Request 3)........................93 R PIR4 (Peripheral Interrupt Request 4)........................94 RCREG.............................................................................292 PORTA.....................................................................122 RCREG Register.................................................................29 PORTB.....................................................................127 RCSTA Register.........................................................29, 295 PSTRxCON (PWM Steering Control).......................230 Reader Response.............................................................404 PWMxCON (Enhanced PWM Control).....................229 Read-Modify-Write Operations.........................................325 RCREG.....................................................................302 Reference Clock.................................................................69 RCSTA (Receive Status and Control)......................295 Associated Registers..................................................71 SPBRGH..................................................................297 Registers SPBRGL...................................................................297 ADCON0 (ADC Control 0)........................................145 Special Function, Summary........................................28 ADCON1 (ADC Control 1)........................................146 SRCON0 (SR Latch Control 0).................................159 ADRESH (ADC Result High) with ADFM = 0)...........147 SRCON1 (SR Latch Control 1).................................160 ADRESH (ADC Result High) with ADFM = 1)...........148 SSPxADD (MSSPx Address and Baud Rate, ADRESL (ADC Result Low) with ADFM = 0)............147 I2C Mode).........................................................283 ADRESL (ADC Result Low) with ADFM = 1)............148 SSPxCON1 (MSSPx Control 1)................................280 ANSELA (PORTA Analog Select).............................123 SSPxCON2 (SSPx Control 2)...................................281 ANSELB (PORTB Analog Select).............................128 SSPxCON3 (SSPx Control 3)...................................282 APFCON0 (Alternate Pin Function Control 0)...........119 SSPxMSK (SSPx Mask)...........................................283 APFCON1 (Alternate Pin Function Control 1)...........119 SSPxSTAT (SSPx Status)........................................279 BAUDCON (Baud Rate Control)...............................296 STATUS.....................................................................21 BORCON Brown-out Reset Control)...........................75 T1CON (Timer1 Control)..........................................185 CCPTMRS (PWM Timer Selection Control).............227 T1GCON (Timer1 Gate Control)...............................186 CCPxAS (CCPx Auto-Shutdown Control).................228 TRISA (Tri-State PORTA)........................................122 CCPxCON (ECCPx Control).....................................226 TRISB (Tri-State PORTB)........................................127 CLKRCON (Reference Clock Control)........................70 TXCON.....................................................................191 CMOUT (Comparator Output)...................................171 TXSTA (Transmit Status and Control)......................294 CMxCON0 (Cx Control)............................................170 WDTCON (Watchdog Timer Control).........................99 CMxCON1 (Cx Control 1).........................................171 WPUB (Weak Pull-up PORTB).........................123, 128 Configuration Word 1..................................................44 RESET..............................................................................335 Configuration Word 2..................................................46 Reset..................................................................................73 Core Function, Summary............................................27 Reset Instruction.................................................................76 CPSCON0 (Capacitive Sensing Control Register 0) 318 Resets................................................................................73 CPSCON1 (Capacitive Sensing Control Register 1) 319 Associated Registers..................................................80 DACCON0................................................................156 Revision History................................................................393 DACCON1................................................................156 S Device ID....................................................................49 EEADRL (EEPROM Address)..................................113 Shoot-through Current......................................................222 EECON1 (EEPROM Control 1).................................115 Software Simulator (MPLAB SIM)....................................381 EECON2 (EEPROM Control 2).................................116 SPBRG Register.................................................................29 EEDATH (EEPROM Data)................................113, 114 SPBRGH Register............................................................297 EEDATL (EEPROM Data)........................................113 SPBRGL Register.............................................................297 FVRCON...................................................................136 Special Event Trigger.......................................................143 INTCON (Interrupt Control).........................................86 Special Function Registers (SFRs).....................................28 IOCBF (Interrupt-on-Change Flag)...........................132 SPI Mode (MSSPx) IOCBN (Interrupt-on-Change Negative Edge)..........132 Associated Registers................................................241 IOCBP (Interrupt-on-Change Positive Edge)............132 SPI Clock..................................................................237 LATA (Data Latch PORTA).......................................122 SR Latch...........................................................................157 LATB (Data Latch PORTB).......................................127 Associated registers w/ SR Latch.............................161 MDCARH (Modulation High Carrier Control SRCON0 Register............................................................159 Register)...........................................................200 SRCON1 Register............................................................160 MDCARL (Modulation Low Carrier Control Register)201 SSP1ADD Register.............................................................30 MDCON (Modulation Control Register)....................198 SSP1BUF Register.............................................................30 MDSRC (Modulation Source Control Register)........199 SSP1CON Register............................................................30 OPTION_REG (OPTION).........................................176 SSP1CON2 Register..........................................................30 OSCCON (Oscillator Control).....................................65 SSP1CON3 Register..........................................................30 OSCSTAT (Oscillator Status).....................................66 SSP1MSK Register............................................................30 OSCTUNE (Oscillator Tuning)....................................67 SSP1STAT Register...........................................................30 PCON (Power Control Register).................................79 SSP2ADD Register.............................................................30 PCON (Power Control)...............................................79 SSP2BUF Register.............................................................30 PIE1 (Peripheral Interrupt Enable 1)...........................87 SSP2CON1 Register..........................................................30 PIE2 (Peripheral Interrupt Enable 2)...........................88 SSP2CON2 Register..........................................................30  2011 Microchip Technology Inc. DS41391D-page 399

PIC16(L)F1826/27 SSP2CON3 Register...........................................................30 BRG Reset Due to SDA Arbitration During Start SSP2MSK Register.............................................................30 Condition..........................................................274 SSP2STAT Register...........................................................30 Brown-out Reset (BOR)............................................358 SSPxADD Register...........................................................283 Brown-out Reset Situations........................................75 SSPxCON1 Register.........................................................280 Bus Collision During a Repeated Start Condition SSPxCON2 Register.........................................................281 (Case 1)............................................................275 SSPxCON3 Register.........................................................282 Bus Collision During a Repeated Start Condition SSPxMSK Register...........................................................283 (Case 2)............................................................275 SSPxOV............................................................................268 Bus Collision During a Start Condition (SCL = 0).....274 SSPxOV Status Flag.........................................................268 Bus Collision During a Stop Condition (Case 1).......276 SSPxSTAT Register..........................................................279 Bus Collision During a Stop Condition (Case 2).......276 R/W Bit......................................................................247 Bus Collision During Start Condition (SDA only)......273 Stack...................................................................................37 Bus Collision for Transmit and Acknowledge...........272 Accessing....................................................................37 CLKOUT and I/O......................................................356 Reset...........................................................................39 Clock Synchronization..............................................260 Stack Overflow/Underflow...................................................76 Clock Timing.............................................................354 STATUS Register................................................................21 Comparator Output...................................................163 SUBWFB...........................................................................337 Enhanced Capture/Compare/PWM (ECCP).............360 Fail-Safe Clock Monitor (FSCM).................................64 T First Start Bit Timing.................................................264 T1CON Register..........................................................28, 185 Full-Bridge PWM Output...........................................217 T1GCON Register.............................................................186 Half-Bridge PWM Output..................................215, 222 T2CON Register............................................................28, 32 I2C Bus Data.............................................................368 Temperature Indicator Module..........................................137 I2C Bus Start/Stop Bits.............................................367 Thermal Considerations....................................................352 I2C Master Mode (7 or 10-Bit Transmission)............267 Timer0.......................................................................173, 192 I2C Master Mode (7-Bit Reception)...........................269 Associated Registers................................................176 I2C Stop Condition Receive or Transmit Mode.........271 Operation..................................................................173 INT Pin Interrupt.........................................................84 Specifications............................................................360 Internal Oscillator Switch Timing................................59 Timer1...............................................................................177 PWM Auto-shutdown................................................221 Associated registers..................................................187 Firmware Restart..............................................220 Asynchronous Counter Mode...................................179 PWM Direction Change............................................218 Reading and Writing.........................................179 PWM Direction Change at Near 100% Duty Cycle...219 Clock Source Selection.............................................178 PWM Output (Active-High).......................................213 Interrupt.....................................................................181 PWM Output (Active-Low)........................................214 Operation..................................................................178 Repeat Start Condition.............................................265 Operation During Sleep............................................181 Reset Start-up Sequence...........................................77 Oscillator...................................................................179 Reset, WDT, OST and Power-up Timer...................357 Prescaler...................................................................179 Send Break Character Sequence.............................305 Specifications............................................................360 SPI Master Mode (CKE = 1, SMP = 1).....................365 Timer1 Gate SPI Mode (Master Mode)..........................................237 Selecting Source...............................................179 SPI Slave Mode (CKE = 0).......................................366 TMR1H Register.......................................................177 SPI Slave Mode (CKE = 1).......................................366 TMR1L Register........................................................177 Synchronous Reception (Master Mode, SREN).......310 Timer2 Synchronous Transmission......................................307 Associated registers..................................................192 Synchronous Transmission (Through TXEN)...........307 Timer2/4/6.........................................................................189 Timer0 and Timer1 External Clock...........................359 Associated registers..................................................192 Timer1 Incrementing Edge.......................................181 Timers Two Speed Start-up....................................................62 Timer1 USART Synchronous Receive (Master/Slave).........364 T1CON..............................................................185 USART Synchronous Transmission (Master/Slave).364 T1GCON...........................................................186 Wake-up from Interrupt...............................................96 Timer2/4/6 Timing Diagrams and Specifications TXCON.............................................................191 PLL Clock.................................................................355 Timing Diagrams Timing Parameter Symbology..........................................353 A/D Conversion.........................................................362 Timing Requirements A/D Conversion (Sleep Mode)..................................362 I2C Bus Data.............................................................369 Acknowledge Sequence...........................................270 I2C Bus Start/Stop Bits.............................................368 Asynchronous Reception..........................................292 SPI Mode..................................................................367 Asynchronous Transmission.....................................288 TMR0 Register....................................................................28 Asynchronous Transmission (Back to Back)............288 TMR1H Register.................................................................28 Auto Wake-up Bit (WUE) During Normal Operation.304 TMR1L Register..................................................................28 Auto Wake-up Bit (WUE) During Sleep....................304 TMR2 Register..............................................................28, 32 Automatic Baud Rate Calibration..............................302 TRIS..................................................................................338 Baud Rate Generator with Clock Arbitration.............263 TRISA Register...........................................................28, 122 DS41391D-page 400  2011 Microchip Technology Inc.

PIC16(L)F1826/27 TRISB...............................................................................125 TRISB Register...........................................................28, 127 Two-Speed Clock Start-up Mode........................................61 TXCON (Timer2/4/6) Register..........................................191 TXREG..............................................................................287 TXREG Register.................................................................29 TXSTA Register..........................................................29, 294 BRGH Bit..................................................................297 U USART Synchronous Master Mode Requirements, Synchronous Receive..............364 Requirements, Synchronous Transmission......364 Timing Diagram, Synchronous Receive...........364 Timing Diagram, Synchronous Transmission...364 V VREF. SEE ADC Reference Voltage W Wake-up on Break............................................................303 Wake-up Using Interrupts...................................................96 Watchdog Timer (WDT)......................................................76 Associated Registers................................................100 Configuration Word w/ Watchdog Timer...................100 Modes.........................................................................98 Specifications............................................................359 WCOL.......................................................263, 266, 268, 270 WCOL Status Flag....................................263, 266, 268, 270 WDTCON Register.............................................................99 WPUB Register.........................................................123, 128 Write Protection..................................................................47 WWW Address..................................................................403 WWW, On-Line Support.......................................................8  2011 Microchip Technology Inc. DS41391D-page 401

PIC16(L)F1826/27 NOTES: DS41391D-page 402  2011 Microchip Technology Inc.

PIC16(L)F1826/27 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011 Microchip Technology Inc. DS41391D-page 403

PIC16(L)F1826/27 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16(L)F1826/27 Literature Number: DS41391D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41391D-page 404  2011 Microchip Technology Inc.

PIC16(L)F1826/27 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F1826 - I/ML 301 = Industrial temp., QFN Range package, Extended VDD limits, QTP pattern #301. b) PIC16F1826 - I/P = Industrial temp., PDIP package, Extended VDD limits. Device: PIC16F1826(1), PIC16F1827(1), PIC16F1826T(2), c) PIC16F1827 - E/SS= Extended temp., SSOP PIC16F1827T(2); package, normal VDD limits. VDD range 1.8V to 5.5V PIC16LF1826(1), PIC16LF1827(1), PIC16LF1826T(2), PIC16LF1827T(2); VDD range 1.8V to 3.6V Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Package: ML = Micro Lead Frame (QFN) 6x6 MV = Micro Lead Frame (UQFN) 4x4 Note1: F = Wide Voltage Range P = Plastic DIP LF = Standard Voltage Range SO = SOIC 2: T = in tape and reel SOIC, SSOP, and SS = SSOP QFN/UQFN packages only. Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise)  2011 Microchip Technology Inc. DS41391D-page 405

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