PIC12(L)F1822/16(L)F1823 8/14-Pin Flash Microcontrollers with XLP Technology High-Performance RISC CPU Extreme Low-Power Management PIC12LF1822/16LF1823 with XLP • Only 49 Instructions to Learn: - All single-cycle instructions except branches • Sleep mode: 20nA @ 1.8V, typical • Operating Speed: • Watchdog Timer: 300nA @ 1.8V, typical - DC – 32MHz oscillator/clock input • Timer1 Oscillator: 650nA @ 32 kHz, typical - DC – 125ns instruction cycle • Operating Current: 30µA/MHz @ 1.8V, typical • Interrupt Capability with Automatic Context Saving Analog Features • 16-Level Deep Hardware Stack with Optional • Analog-to-Digital Converter (ADC) module: Overflow/Underflow Reset - 10-bit resolution, up to 8 channels • Direct, Indirect and Relative Addressing modes: - Conversion available during Sleep - Two full 16-bit File Select Registers (FSRs) • Analog Comparator module: - FSRs can read program and data memory - Up to two rail-to-rail analog comparators Flexible Oscillator Structure - Power mode control - Software controllable hysteresis • Precision 32MHz internal Oscillator Block: • Voltage Reference module: - Factory calibrated to ± 1%, typical - Fixed Voltage Reference (FVR) with 1.024V, - Software selectable frequencies range of 2.048V and 4.096V output levels 31kHz to 32MHz - 5-bit rail-to-rail resistive DAC with positive • 31 kHz Low-Power Internal Oscillator and negative reference selection • Four Crystal modes up to 32MHz • Three External Clock modes up to 32MHz Peripheral Highlights • 4X Phase Lock Loop (PLL) • Up to 11 I/O Pins and 1 Input-Only Pin: • Fail-Safe Clock Monitor: - High current sink/source 25mA/25mA - Allows for safe shutdown if peripheral clock - Programmable weak pull-ups stops - Programmable interrupt-on-change pins • Two-Speed Oscillator Start-up • Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler • Reference Clock module: • Enhanced Timer1: - Programmable clock output frequency and - 16-bit timer/counter with prescaler duty-cycle - External Gate Input mode Special Microcontroller Features - Dedicated, low-power 32 kHz oscillator driver • Timer2: 8-Bit Timer/Counter with 8-Bit Period • Full 5.5V Operation – PIC12F1822/16F1823 Register, Prescaler and Postscaler • 1.8V-3.6V Operation – PIC12LF1822/16LF1823 • Enhanced CCP (ECCP) modules: • Self-Reprogrammable under Software Control - Software selectable time bases • Power-on Reset (POR), Power-up Timer (PWRT) - Auto-shutdown and auto-restart and Oscillator Start-up Timer (OST) - PWM steering • Programmable Brown-out Reset (BOR) • Master Synchronous Serial Port (MSSP) with SPI • Extended Watchdog Timer (WDT) and I2CTM with: • In-Circuit Serial Programming™ (ICSP™) via - 7-bit address masking Two Pins - SMBus/PMBusTM compatibility • In-Circuit Debug (ICD) via Two Pins • Enhanced Universal Synchronous Asynchronous • Enhanced Low-Voltage Programming (LVP) Receiver Transmitter (EUSART) module: • Operating Voltage Range: - RS-232, RS-485 and LIN compatible - 1.8V-5.5V (PIC12F1822/16F1823) - Auto-Baud Detect - 1.8V-3.6V (PIC12LF1822/16LF1823) • Capacitive Sensing (CPS) module (mTouch™): • Programmable Code Protection - Up to 8 input channels • Self-Programmable under Software Control  2010-2015 Microchip Technology Inc. DS40001413E-page 1

PIC12(L)F1822/16(L)F1823 Peripheral Features (Continued) • Data Signal Modulator module - Selectable modulator and carrier sources • SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications TABLE 1: PIC12(L)F1822/1840/PIC16(L)F182X/1847 FAMILY TYPES Device Data Sheet Index Program MemoryFlash (words) Data EEPROM(bytes) Data SRAM(bytes) (2)I/O’s 10-bit ADC (ch) CapSense (ch) Comparators Timers(8/16-bit) EUSART 2MSSP (IC™/SPI) CCP (Full-Bridge)CCP (Half-Bridge)CCP SR Latch (1)Debug XLP EE PIC12(L)F1822 (1) 2K 256 128 6 4 4 1 2/1 1 1 0/1/0 Y I/H Y PIC12(L)F1840 (2) 4K 256 256 6 4 4 1 2/1 1 1 0/1/0 Y I/H Y PIC16(L)F1823 (1) 2K 256 128 12 8 8 2 2/1 1 1 1/0/0 Y I/H Y PIC16(L)F1824 (3) 4K 256 256 12 8 8 2 4/1 1 1 1/1/2 Y I/H Y PIC16(L)F1825 (4) 8K 256 1024 12 8 8 2 4/1 1 1 1/1/2 Y I/H Y PIC16(L)F1826 (5) 2K 256 256 16 12 12 2 2/1 1 1 1/0/0 Y I/H Y PIC16(L)F1827 (5) 4K 256 384 16 12 12 2 4/1 1 2 1/1/2 Y I/H Y PIC16(L)F1828 (3) 4K 256 256 18 12 12 2 4/1 1 1 1/1/2 Y I/H Y PIC16(L)F1829 (4) 8K 256 1024 18 12 12 2 4/1 1 2 1/1/2 Y I/H Y PIC16(L)F1847 (6) 8K 256 1024 16 12 12 2 4/1 1 2 1/1/2 Y I/H Y Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header. 2: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS41413 PIC12(L)F1822/PIC16(L)F1823 Data Sheet, 8/14-Pin Flash Microcontrollers. 2: DS41441 PIC12(L)F1840 Data Sheet, 8-Pin Flash Microcontrollers. 3: DS41419 PIC16(L)F1824/1828 Data Sheet, 28/40/44-Pin Flash Microcontrollers. 4: DS41440 PIC16(L)F1825/1829 Data Sheet, 14/20-Pin Flash Microcontrollers. 5: DS41391 PIC16(L)F1826/1827 Data Sheet, 18/20/28-Pin Flash Microcontrollers. 6: DS41453 PIC16(L)F1847 Data Sheet, 18/20/28-Pin Flash Microcontrollers. Note: For other small form-factor package availability and marking information, please visit www.microchip.com/packaging or contact your local sales office. DS40001413E-page 2  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 1: 8-PIN DIAGRAM FOR PIC12(L)F1822 PDIP, SOIC, DFN, UDFN VDD 1 2 8 VSS 2 RA5 2 18 7 RA0/ICSPDAT F RA4 3 2(L) 6 RA1/ICSPCLK 1 MCLR/VPP/RA3 4 C 5 RA2 PI TABLE 2: 8-PIN ALLOCATION TABLE (PIC12(L)F1822) N F D U N/ I/O DIP/SOIC/DF A/D Reference Cap Sense Comparator SR Latch Timers ECCP EUSART MSSP Interrupt Modulator Pull-up Basic P n Pi 8- RA0 7 AN0 DACOUT CPS0 C1IN+ — — P1B(1) TX(1) SDO(1) IOC MDOUT Y ICSPDAT CK(1) SS(1) ICDDAT RA1 6 AN1 VREF+ CPS1 C1IN0- SRI — — RX(1) SCL IOC MDMIN Y ICSPCLK DT(1) SCK ICPCLK RA2 5 AN2 — CPS2 C1OUT SRQ T0CKI CCP1(1) — SDA INT/ MDCIN1 Y — P1A(1) SDI IOC FLT0 RA3 4 — — — — — T1G(1) — — SS(1) IOC — Y MCLR VPP RA4 3 AN3 — CPS3 C1IN1- — T1G(1) P1B(1) TX(1) SDO(1) IOC MDCIN2 Y OSC2 T1OSO CK(1) CLKOUT CLKR RA5 2 — — — — SRNQ T1CKI CCP1(1) RX(1) — IOC — Y OSC1 T1OSI P1A(1) DT(1) CLKIN VDD 1 — — — — — — — — — — — — VDD VSS 8 — — — — — — — — — — — — VSS Note 1: Pin function is selectable via the APFCON register.  2010-2015 Microchip Technology Inc. DS40001413E-page 3

PIC12(L)F1822/16(L)F1823 FIGURE 2: 14-PIN DIAGRAM FOR PIC16(L)F1823 PDIP, SOIC, TSSOP VDD 1 14 VSS RA5 2 13 RA0/ICSPDAT 3 RA4 3 2 12 RA1/ICSPCLK 8 1 MCLR/VPP/RA3 4 F 11 RA2 ) L RC5 5 6( 10 RC0 1 C RC4 6 PI 9 RC1 RC3 7 8 RC2 FIGURE 3: 16-PIN DIAGRAM FOR PIC16(L)F1823 QFN, UQFN DD C C SS V N N V 6 5 4 3 1 1 1 1 RA5 1 12 RA0/ICSPDAT RA4 2 11 RA1/ICSPCLK PIC16(L)F1823 MCLR/VPP/RA3 3 10 RA2 RC5 4 9 RC0 5 6 7 8 4 3 2 1 C C C C R R R R DS40001413E-page 4  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 3: 14-PIN ALLOCATION TABLE (PIC16(L)F1823) P O I/O PDIP/SOIC/TSS Pin QFN/UQFN A/D Reference Cap Sense Comparator SR Latch Timers ECCP EUSART MSSP Interrupt Modulator Pull-up Basic n 6- Pi 1 4- 1 RA0 13 12 AN0 DACOUT CPS0 C1IN+ — — — TX(1) — IOC — Y ICSPDAT CK(1) ICDDAT RA1 12 11 AN1 VREF+ CPS1 C12IN0- SRI — — RX(1) — IOC — Y ICSPCLK DT(1) ICDCLK RA2 11 10 AN2 — CPS2 C1OUT SRQ T0CKI FLT0 — — INT/ — Y — IOC RA3 4 3 — — — — — T1G(1) — — SS(1) IOC — Y MCLR VPP RA4 3 2 AN3 — CPS3 — — T1G(1) — SDO(1) IOC — Y OSC2 T1OSO CLKOUT CLKR RA5 2 1 — — — — — T1CKI — — — IOC — Y OSC1 T1OSI CLKIN RC0 10 9 AN4 — CPS4 C2IN+ — — — — SCL — — Y — SCK RC1 9 8 AN5 — CPS5 C12IN1- — — — — SDA — — Y — SDI RC2 8 7 AN6 — CPS6 C12IN2- — — P1D — SDO(1) — MDCIN1 Y — RC3 7 6 AN7 — CPS7 C12IN3- — — P1C — SS(1) — MDMIN Y — RC4 6 5 — — — C2OUT SRNQ — P1B TX(1) — — MDOUT Y — CK(1) RC5 5 4 — — — — — — CCP1 RX(1) — — MDCIN2 Y — P1A DT(1) VDD 1 16 — — — — — — — — — — — — VDD VSS 14 13 — — — — — — — — — — — — VSS Note 1: Pin function is selectable via the APFCON register.  2010-2015 Microchip Technology Inc. DS40001413E-page 5

PIC12(L)F1822/16(L)F1823 Table of Contents 1.0 Device Overview..........................................................................................................................................................................8 2.0 Enhanced Mid-Range CPU........................................................................................................................................................15 3.0 Memory Organization.................................................................................................................................................................17 4.0 Device Configuration..................................................................................................................................................................45 5.0 Oscillator Module (With Fail-Safe Clock Monitor).......................................................................................................................51 6.0 Reference Clock Module............................................................................................................................................................68 7.0 Resets........................................................................................................................................................................................71 8.0 Interrupts....................................................................................................................................................................................80 9.0 Power-Down Mode (Sleep)........................................................................................................................................................92 10.0 Watchdog Timer.........................................................................................................................................................................95 11.0 Data EEPROM and Flash Program Memory Control.................................................................................................................98 12.0 I/O Ports...................................................................................................................................................................................112 13.0 Interrupt-On-Change................................................................................................................................................................123 14.0 Fixed Voltage Reference (FVR)...............................................................................................................................................127 15.0 Temperature Indicator Module.................................................................................................................................................129 16.0 Analog-to-Digital Converter (ADC) Module..............................................................................................................................130 17.0 Digital-to-Analog Converter (DAC) Module..............................................................................................................................143 18.0 SR Latch...................................................................................................................................................................................147 19.0 Comparator Module..................................................................................................................................................................152 20.0 Timer0 Module.........................................................................................................................................................................162 21.0 Timer1 Module with Gate Control.............................................................................................................................................165 22.0 Timer2 Module.........................................................................................................................................................................176 23.0 Data Signal Modulator..............................................................................................................................................................180 24.0 Capture/Compare/PWM Modules............................................................................................................................................190 25.0 Master Synchronous Serial Port Module..................................................................................................................................217 26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................268 27.0 Capacitive Sensing (CPS) Module...........................................................................................................................................296 28.0 In-Circuit Serial Programming™ (ICSP™)...............................................................................................................................305 29.0 Instruction Set Summary..........................................................................................................................................................308 30.0 Electrical Specifications............................................................................................................................................................322 31.0 DC and AC Characteristics Graphs and Charts.......................................................................................................................359 32.0 Development Support...............................................................................................................................................................387 33.0 Packaging Information..............................................................................................................................................................391 Appendix A: Data Sheet Revision History..........................................................................................................................................418 Appendix B: Migrating From Other PIC® Devices.............................................................................................................................418 The Microchip Web Site.....................................................................................................................................................................419 Customer Change Notification Service..............................................................................................................................................419 Customer Support..............................................................................................................................................................................419 Product Identification System.............................................................................................................................................................420 DS40001413E-page 6  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2010-2015 Microchip Technology Inc. DS40001413E-page 7

PIC12(L)F1822/16(L)F1823 1.0 DEVICE OVERVIEW The PIC12(L)F1822/16(L)F1823 are described within this data sheet. They are available in 8/14 pin packages. Figure1-1 shows a block diagram of the PIC12(L)F1822/16(L)F1823 devices. Tables1-2 and1-3 show the pinout descriptions. Reference Table1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY 2 3 2 2 8 8 1 1 F F Peripheral L) L) 2( 6( 1 1 C C PI PI ADC ● ● Capacitive Sensing (CPS) Module ● ● Data EEPROM ● ● Digital-to-Analog Converter (DAC) ● ● Digital Signal Modulator (DSM) ● ● EUSART ● ● Fixed Voltage Reference (FVR) ● ● SR Latch ● ● Capture/Compare/PWM Modules ECCP1 ● ● Comparators C1 ● ● C2 ● Master Synchronous Serial Ports MSSP ● ● Timers Timer0 ● ● Timer1 ● ● Timer2 ● ● DS40001413E-page 8  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 1-1: PIC12(L)F1822/16(L)F1823 BLOCK DIAGRAM Program Flash Memory RAM EEPROM CLKR Clock Reference OSC2/CLKOUT Timing Generation PORTA OSC1/CLKIN CPU INTRC Oscillator (Figure2-1) PORTC(3) MCLR SR ADC Timer0 Timer1 DAC Comparators Latch 10-Bit ECCP1 MSSP Modulator EUSART FVR CapSense Note 1: See applicable chapters for more information on peripherals. 2: See Table1-1 for peripherals available on specific devices. 3: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 9

PIC12(L)F1822/16(L)F1823 TABLE 1-2: PIC12(L)F1822 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/CPS0/C1IN+/ RA0 TTL CMOS General purpose I/O. DACOUT/TX(1)/CK(1)/SDO(1)/ AN0 AN — A/D Channel 0 input. SS(1)/P1B(1)/MDOUT/ICSPDAT/ CPS0 AN — Capacitive sensing input 0. ICDDAT C1IN+ AN — Comparator C1 positive input. DACOUT — AN Digital-to-Analog Converter output. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. SDO — CMOS SPI data output. SS ST — Slave Select input. P1B — CMOS PWM output. MDOUT — CMOS Modulator output. ICSPDAT ST CMOS ICSP™ Data I/O. RA1/AN1/CPS1/VREF+/C1IN0-/ RA1 TTL CMOS General purpose I/O. SRI/RX(1)/DT(1)/SCL/SCK/ AN1 AN — A/D Channel 1 input. MDMIN/ICSPCLK/ICDCLK CPS1 AN — Capacitive sensing input 1. VREF+ AN — A/D and DAC Positive Voltage Reference input. C1IN0- AN — Comparator C1 or C2 negative input. SRI ST — SR latch input. RX ST — USART asynchronous input. DT ST CMOS USART synchronous data. SCL I2C™ OD I2C™ clock. SCK ST CMOS SPI clock. MDMIN ST — Modulator source input. ICSPCLK ST — Serial Programming Clock. RA2/AN2/CPS2/C1OUT/SRQ/ RA2 ST CMOS General purpose I/O. T0CKI/CCP1(1)/P1A(1)/FLT0/ AN2 AN — A/D Channel 2 input. SDA/SDI/INT/MDCIN1 CPS2 AN — Capacitive sensing input 2. C1OUT — CMOS Comparator C1 output. SRQ — CMOS SR latch non-inverting output. T0CKI ST — Timer0 clock input. CCP1 ST CMOS Capture/Compare/PWM 1. P1A — CMOS PWM output. FLT0 ST — ECCP Auto-Shutdown Fault input. SDA I2C™ OD I2C™ data input/output. SDI CMOS — SPI data input. INT ST — External interrupt. MDCIN1 ST — Modulator Carrier Input 1. RA3/SS(1)/T1G(1)/VPP/MCLR RA3 TTL — General purpose input. SS ST — Slave Select input. T1G ST — Timer1 Gate input. VPP HV — Programming voltage. MCLR ST — Master Clear with internal pull-up. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register12-1). DS40001413E-page 10  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 1-2: PIC12(L)F1822 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RA4/AN3/CPS3/OSC2/ RA4 TTL CMOS General purpose I/O. CLKOUT/T1OSO/C1IN1-/CLKR/ AN3 AN — A/D Channel 3 input. SDO(1)/CK(1)/TX(1)/P1B(1)/ T1G(1)/MDCIN2 CPS3 AN — Capacitive sensing input 3. OSC2 XTAL XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. T1OSO XTAL XTAL Timer1 oscillator connection. C1IN1- AN — Comparator C1 negative input. CLKR — CMOS Clock Reference output. SDO — CMOS SPI data output. CK ST CMOS USART synchronous clock. TX — CMOS USART asynchronous transmit. P1B — CMOS PWM output. T1G ST — Timer1 Gate input. MDCIN2 ST — Modulator Carrier Input 2. RA5/CLKIN/OSC1/T1OSI/ RA5 TTL CMOS General purpose I/O. T1CKI/SRNQ/P1A(1)/CCP1(1)/ CLKIN CMOS — External clock input (EC mode). DT(1)/RX(1) OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes). T1OSI XTAL XTAL Timer1 oscillator connection. T1CKI ST — Timer1 clock input. SRNQ — CMOS SR latch inverting output. P1A — CMOS PWM output. CCP1 ST CMOS Capture/Compare/PWM 1. DT ST CMOS USART synchronous data. RX ST — USART asynchronous input. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register12-1).  2010-2015 Microchip Technology Inc. DS40001413E-page 11

PIC12(L)F1822/16(L)F1823 TABLE 1-3: PIC16(L)F1823 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/CPS0/C1IN+/ RA0 TTL CMOS General purpose I/O. DACOUT/TX(1)/CK(1)/ICSPDAT/ AN0 AN — A/D Channel 0 input. ICDDAT CPS0 AN — Capacitive sensing input 0. C1IN+ AN — Comparator C1 positive input. DACOUT — AN Digital-to-Analog Converter output. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. ICSPDAT ST CMOS ICSP™ Data I/O. RA1/AN1/CPS1/C12IN0-/VREF+/ RA1 TTL CMOS General purpose I/O. SRI/RX(1)/DT(1)/ICSPCLK/ AN1 AN — A/D Channel 1 input. ICDCLK CPS1 AN — Capacitive sensing input 1. C12IN0- AN — Comparator C1 or C2 negative input. VREF+ AN — A/D and DAC Positive Voltage Reference input. SRI ST — SR latch input. RX ST — USART asynchronous input. DT ST CMOS USART synchronous data. ICSPCLK ST — Serial Programming Clock. RA2/AN2/CPS2/T0CKI/INT/ RA2 ST CMOS General purpose I/O. C1OUT/SRQ/FLT0 AN2 AN — A/D Channel 2 input. CPS2 AN — Capacitive sensing input 2. T0CKI ST — Timer0 clock input. INT ST — External interrupt. C1OUT — CMOS Comparator C1 output. SRQ — CMOS SR latch non-inverting output. FLT0 ST — ECCP Auto-Shutdown Fault input. RA3/SS(1)/T1G(1)/VPP/MCLR RA3 TTL — General purpose input. SS ST — Slave Select input. T1G ST — Timer1 Gate input. VPP HV — Programming voltage. MCLR ST — Master Clear with internal pull-up. RA4/AN3/CPS3/OSC2/ RA4 TTL CMOS General purpose I/O. CLKOUT/T1OSO/CLKR/SDO(1)/ AN3 AN — A/D Channel 3 input. T1G(1) CPS3 AN — Capacitive sensing input 3. OSC2 XTAL XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. T1OSO XTAL XTAL Timer1 oscillator connection. CLKR — CMOS Clock Reference output. SDO — CMOS SPI data output. T1G ST — Timer1 Gate input. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register12-1). DS40001413E-page 12  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 1-3: PIC16(L)F1823 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RA5/CLKIN/OSC1/T1OSI/T1CKI RA5 TTL CMOS General purpose I/O. CLKIN CMOS — External clock input (EC mode). OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes). T1OSI XTAL XTAL Timer1 oscillator connection. T1CKI ST — Timer1 clock input. RC0/AN4/CPS4/C2IN+/SCL/ RC0 TTL CMOS General purpose I/O. SCK AN4 AN — A/D Channel 4 input. CPS4 AN — Capacitive sensing input 4. C2IN+ AN — Comparator C2 positive input. SCL I2C™ OD I2C™ clock. SCK ST CMOS SPI clock. RC1/AN5/CPS5/C12IN1-/SDA/ RC1 TTL CMOS General purpose I/O. SDI AN5 AN — A/D Channel 5 input. CPS5 AN — Capacitive sensing input 5. C12IN1- AN — Comparator C1 or C2 negative input. SDA I2C™ OD I2C™ data input/output. SDI CMOS — SPI data input. RC2/AN6/CPS6/C12IN2-/P1D/ RC2 TTL CMOS General purpose I/O. SDO(1)/MDCIN1 AN6 AN — A/D Channel 6 input. CPS6 AN — Capacitive sensing input 6. C12IN2- AN — Comparator C1 or C2 negative input. P1D — CMOS PWM output. SDO — CMOS SPI data output. MDCIN1 ST — Modulator Carrier Input 1. RC3/AN7/CPS7/C12IN3-/P1C/ RC6 TTL CMOS General purpose I/O. SS(1)/MDMIN AN7 AN — A/D Channel 6 input. CPS7 AN — Capacitive sensing input 6. C12IN3- AN — Comparator C1 or C2 negative input. P1C — CMOS PWM output. SS ST — Slave Select input. MDMIN ST — Modulator source input. RC4/C2OUT/SRNQ/P1B/CK(1)/ RC4 TTL CMOS General purpose I/O. TX(1)/MDOUT C2OUT — CMOS Comparator C2 output. SRNQ — CMOS SR latch inverting output. P1B — CMOS PWM output. CK ST CMOS USART synchronous clock. TX — CMOS USART asynchronous transmit. MDOUT — CMOS Modulator output. RC5/P1A/CCP1/DT(1)/RX(1)/ RC5 TTL CMOS General purpose I/O. MDCIN2 P1A — CMOS PWM output. CCP1 ST CMOS Capture/Compare/PWM 1. DT ST CMOS USART synchronous data. RX ST — USART asynchronous input. MDCIN2 ST — Modulator Carrier Input 2. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register12-1).  2010-2015 Microchip Technology Inc. DS40001413E-page 13

PIC12(L)F1822/16(L)F1823 TABLE 1-3: PIC16(L)F1823 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register12-1). DS40001413E-page 14  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. • Automatic Interrupt Context Saving • 16-level Stack with Overflow and Underflow • File Select Registers • Instruction Set 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section8.5 “Automatic Context Saving”, for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Under- flow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a soft- ware Reset. See section Section3.4 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one data pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section3.5 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section29.0 “Instruction Set Summary” for more details.  2010-2015 Microchip Technology Inc. DS40001413E-page 15

PIC12(L)F1822/16(L)F1823 FIGURE 2-1: CORE BLOCK DIAGRAM 15 CCCooonnnfffiiiggguuurrraaatttiiiooonnn 15 888 DDDaaatttaaa BBBuuusss PPPrrrooogggrrraaammm CCCooouuunnnttteeerrr Flash X U Program M Memory 1886 -LLLeeevvveeell lSS Sttaataccckkk RAM (((111335---bbbiiittt))) PPPrrrooogggrrraaammm 111444 Program Memory 12 RAM Addr BBBuuusss Read (PMR) AAAddddddrrr MMMUUUXXX IIInnnssstttrrruuuccctttiiiooonnn Rrreeeggg Indirect DDDiiirrreeecccttt AAAddddddrrr 777 Addr 5 12 12 15 BFFSSSRRR Rrreeeggg FFFSSSRRR 0rr eeRggeg FFFSSSRRR1 rrReeeggg 15 SSSTTTAAATTTUUUSSS Rrreeeggg 888 333 MMMUUUXXX Power-up Timer IIInnnssstttrrruuuccctttiiiooonnn Oscillator DDDeeecccooodddeee a &&nd Start-up Timer AAALLLUUU CCCooonnntttrrrooolll Power-on OSC1/CLKIN Reset 888 TTTiiimmmiiinnnggg Watchdog OSC2/CLKOUT GGGeeennneeerrraaatttiiiooonnn Timer W Reg Brown-out Reset Internal Oscillator Block VVVDDDDDD VVVSSSSSS DS40001413E-page 16  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 3.0 MEMORY ORGANIZATION The following features are associated with access and control of program memory and data memory: These devices contain the following types of memory: • PCL and PCLATH • Program Memory • Stack • Data Memory • Indirect Addressing - Core Registers - Special Function Registers 3.1 Program Memory Organization - General Purpose RAM The enhanced mid-range core has a 15-bit program - Common RAM counter capable of addressing a 32K x 14 program - Device Memory Maps memory space. Table3-1 shows the memory sizes - Special Function Registers Summary implemented for the PIC12(L)F1822/16(L)F1823 family. • Data EEPROM memory(1) Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. Note1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) Last Program Memory Address PIC12(L)F1822 2,048 07FFh PIC16(L)F1823  2010-2015 Microchip Technology Inc. DS40001413E-page 17

PIC12(L)F1822/16(L)F1823 FIGURE 3-1: PROGRAM MEMORY MAP 3.1.1 READING PROGRAM MEMORY AS AND STACK FOR DATA PIC12(L)F1822/16(L)F1823 There are two methods of accessing constants in program memory. The first method is to use tables of PC<14:0> RETLW instructions. The second method is to set an FSR to point to the program memory. CALL, CALLW 15 RETURN, RETLW 3.1.1.1 RETLW Instruction Interrupt, RETFIE Stack Level 0 The RETLW instruction can be used to provide access Stack Level 1 to tables of constants. The recommended way to create such a table is shown in Example3-1. Stack Level 15 EXAMPLE 3-1: RETLW INSTRUCTION constants Reset Vector 0000h BRW ;Add Index in W to ;program counter to ;select data Interrupt Vector 0004h RETLW DATA0 ;Index0 data On-chip 0005h RETLW DATA1 ;Index1 data Program Page 0 RETLW DATA2 Memory 07FFh RETLW DATA3 0800h Rollover to Page 0 Wraps to Page 0 my_function ;… LOTS OF CODE… MOVLW DATA_INDEX Wraps to Page 0 CALL constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable Wraps to Page 0 with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. Rollover to Page 0 7FFFh DS40001413E-page 18  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 3.1.1.2 Indirect Read with FSR 3.2.1 CORE REGISTERS The program memory can be accessed as data by The core registers contain the registers that directly setting bit 7 of the FSRxH register and reading the affect the basic operation of the matching INDFx register. The MOVIW instruction will PIC12(L)F1822/16(L)F1823. These registers are listed place the lower eight bits of the addressed word in the below: W register. Writes to the program memory cannot be • INDF0 performed via the INDF registers. Instructions that • INDF1 access the program memory via the FSR require one • PCL extra instruction cycle to complete. Example3-2 demonstrates accessing the program memory via an • STATUS FSR. • FSR0 Low The High directive will set bit<7> if a label points to a • FSR0 High location in program memory. • FSR1 Low • FSR1 High EXAMPLE 3-2: ACCESSING PROGRAM • BSR MEMORY VIA FSR • WREG constants • PCLATH RETLW DATA0 ;Index0 data • INTCON RETLW DATA1 ;Index1 data RETLW DATA2 Note: The core registers are the first 12 RETLW DATA3 addresses of every data memory bank. my_function ;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure3-2): • 12 core registers • 20 Special Function Registers (SFR) • Up to 80 bytes of General Purpose RAM (GPR) • 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section3.5 “Indirect Addressing” for more information.  2010-2015 Microchip Technology Inc. DS40001413E-page 19

PIC12(L)F1822/16(L)F1823 3.2.1.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register3-1, contains: as ‘000u u1uu’ (where u = unchanged). • the arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, • the Reset status SWAPF and MOVWF instructions are used to alter the The STATUS register can be the destination for any STATUS register, because these instructions do not instruction, like any other register. If the STATUS affect any Status bits. For other instructions not register is the destination for an instruction that affects affecting any Status bits (Refer to Section29.0 the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”). disabled. These bits are set or cleared according to the Note1: The C and DC bits operate as Borrow device logic. Furthermore, the TO and PD bits are not and Digit Borrow out bits, respectively, in writable. Therefore, the result of an instruction with the subtraction. STATUS register as destination may be different than intended. REGISTER 3-1: STATUS: STATUS REGISTER U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — — — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. DS40001413E-page 20  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 3.2.2 SPECIAL FUNCTION REGISTER 3.2.5 DEVICE MEMORY MAPS The Special Function Registers are registers used by The memory maps for the device family are as shown the application to control the desired operation of in Table3-2. peripheral functions in the device. The registers associated with the operation of the peripherals are TABLE 3-2: MEMORY MAP TABLES described in the appropriate peripheral chapter of this data sheet. Device Banks Table No. 3.2.3 GENERAL PURPOSE RAM 0-7 Table3-3 8-15 Table3-4 There are up to 80bytes of GPR in each data memory bank. PIC12(L)F1822/16(L)F1823 16-23 Table3-5 24-31 Table3-6 3.2.3.1 Linear Access to GPR 31 Table3-7 The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section3.5.2 “Linear Data Memory” for more information. 3.2.4 COMMON RAM There are 16 bytes of common RAM accessible from all banks. FIGURE 3-2: BANKED MEMORY PARTITIONING 7-bit Bank Offset Memory Region 00h Core Registers (12 bytes) 0Bh 0Ch Special Function Registers (20 bytes maximum) 1Fh 20h General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh  2010-2015 Microchip Technology Inc. DS40001413E-page 21

D TABLE 3-3: PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANKS 0-7 P S 4 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 0 I 00 000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0 C 14 001h INDF1 081h INDF1 101h INDF1 181h INDF1 201h INDF1 281h INDF1 301h INDF1 381h INDF1 1 002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL 1 3 E 003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS 2 -page 000045hh FFSSRR00HL 008854hh FFSSRR00HL 110045hh FFSSRR00HL 118854hh FFSSRR00HL 220054hh FFSSRR00HL 228854hh FFSSRR00HL 330045hh FFSSRR00HL 338845hh FFSSRR00HL (L 2 006h FSR1L 086h FSR1L 106h FSR1L 186h FSR1L 206h FSR1L 286h FSR1L 306h FSR1L 386h FSR1L 2 007h FSR1H 087h FSR1H 107h FSR1H 187h FSR1H 207h FSR1H 287h FSR1H 307h FSR1H 387h FSR1H ) 008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR F 009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG 1 00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH 00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON 8 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch — 30Ch — 38Ch — 2 00Dh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh — 2 00Eh PORTC(1) 08Eh TRISC(1) 10Eh LATC(1) 18Eh ANSELC(1) 20Eh WPUC(1) 28Eh — 30Eh — 38Eh — 00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh — / 1 010h — 090h — 110h — 190h — 210h — 290h — 310h — 390h — 011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP 6 012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN ( 013h — 093h — 113h CM2CON0(1) 193h EEDATL 213h SSP1MASK 293h CCP1CON 313h — 393h IOCAF L 014h — 094h — 114h CM2CON1(1) 194h EEDATH 214h SSP1STAT 294h PWM1CON 314h — 394h — ) 015h TMR0 095h OPTION 115h CMOUT 195h EECON1 215h SSP1CON1 295h CCP1AS 315h — 395h — F 016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSP1CON2 296h PSTR1CON 316h — 396h — 017h TMR1H 097h WDTCON 117h FVRCON 197h — 217h SSP1CON3 297h — 317h — 397h — 1 018h T1CON 098h OSCTUNE 118h DACCON0 198h — 218h — 298h — 318h — 398h — 8 019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h — 299h — 319h — 399h — 2 01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah — 29Ah — 31Ah — 39Ah CLKRCON 01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh — 29Bh — 31Bh — 39Bh — 3 01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch MDCON 01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh MDSRC 01Eh CPSCON0 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh — 31Eh — 39Eh MDCARL 01Fh CPSCON1 09Fh — 11Fh — 19Fh BAUDCON 21Fh — 29Fh — 31Fh — 39Fh MDCARH 020h 0A0h General 120h 1A0h 220h 2A0h 320h 3A0h Purpose General Register  Purpose 0BFh 32 Bytes Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented 2 Register 0CFh Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 0 80 Bytes Unimplemented 1 0 Read as ‘0’ -2 06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh 01 070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h 5 M Common RAM Accesses Accesses Accesses Accesses Accesses Accesses Accesses ic 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh ro 07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh c h ip T Legend: = Unimplemented data memory locations, read as ‘0’. e Note 1: Available only on PIC16(L)F1823. c h n o lo g y In c .

 TABLE 3-4: PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANKS 8-15 20 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 1 0 -2 400h INDF0 480h INDF0 500h INDF0 580h INDF0 600h INDF0 680h INDF0 700h INDF0 780h INDF0 01 401h INDF1 481h INDF1 501h INDF1 581h INDF1 601h INDF1 681h INDF1 701h INDF1 781h INDF1 5 M 402h PCL 482h PCL 502h PCL 582h PCL 602h PCL 682h PCL 702h PCL 782h PCL ic 403h STATUS 483h STATUS 503h STATUS 583h STATUS 603h STATUS 683h STATUS 703h STATUS 783h STATUS roc 404h FSR0L 484h FSR0L 504h FSR0L 584h FSR0L 604h FSR0L 684h FSR0L 704h FSR0L 784h FSR0L hip 405h FSR0H 485h FSR0H 505h FSR0H 585h FSR0H 605h FSR0H 685h FSR0H 705h FSR0H 785h FSR0H T 406h FSR1L 486h FSR1L 506h FSR1L 586h FSR1L 606h FSR1L 686h FSR1L 706h FSR1L 786h FSR1L e ch 407h FSR1H 487h FSR1H 507h FSR1H 587h FSR1H 607h FSR1H 687h FSR1H 707h FSR1H 787h FSR1H no 408h BSR 488h BSR 508h BSR 588h BSR 608h BSR 688h BSR 708h BSR 788h BSR log 409h WREG 489h WREG 509h WREG 589h WREG 609h WREG 689h WREG 709h WREG 789h WREG y Inc 4400ABhh PINCTLCAOTNH 4488ABhh PINCTLCAOTNH 5500ABhh PINCTLCAOTNH 5588ABhh PINCTLCAOTNH 6600ABhh PINCTLCAOTNH 6688ABhh PINCTLCAOTNH 7700ABhh PINCTLCAOTNH 7788ABhh PINCTLCAOTNH . 40Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch — 40Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh — 40Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70Eh — 78Eh — 40Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh — 78Fh — 410h — 490h — 510h — 590h — 610h — 690h — 710h — 790h — 411h — 491h — 511h — 591h — 611h — 691h — 711h — 791h — P 412h — 492h — 512h — 592h — 612h — 692h — 712h — 792h — 413h — 493h — 513h — 593h — 613h — 693h — 713h — 793h — IC 414h — 494h — 514h — 594h — 614h — 694h — 714h — 794h — 415h — 495h — 515h — 595h — 615h — 695h — 715h — 795h — 1 416h — 496h — 516h — 596h — 616h — 696h — 716h — 796h — 2 417h — 497h — 517h — 597h — 617h — 697h — 717h — 797h — ( 418h — 498h — 518h — 598h — 618h — 698h — 718h — 798h — L 419h — 499h — 519h — 599h — 619h — 699h — 719h — 799h — ) 41Ah — 49Ah — 51Ah — 59Ah — 61Ah — 69Ah — 71Ah — 79Ah — F 41Bh — 49Bh — 51Bh — 59Bh — 61Bh — 69Bh — 71Bh — 79Bh — 41Ch — 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch — 1 41Dh — 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh — 8 41Eh — 49Eh — 51Eh — 59Eh — 61Eh — 69Eh — 71Eh — 79Eh — 2 41Fh — 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh — 2 420h 4A0h 520h 5A0h 620h 6A0h 720h 7A0h / 1 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented 6 Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ ( D L S 4 46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh 0 ) 00 470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h F 141 7A0chc e–s 7seFsh 7A0chc e–s 7seFsh 7A0chc e–s 7seFsh 7A0chc e–s 7sFesh 7A0chc e–s 7sFesh 7A0chc e–s 7sFesh 7A0chc e–s 7sFesh 7A0chc e–s 7sFesh 1 3 E 8 -p 47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh a 2 ge Legend: = Unimplemented data memory locations, read as ‘0’. 2 3 3

D TABLE 3-5: PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANKS 16-23 P S 40 BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23 I 0 C 0 800h INDF0 880h INDF0 900h INDF0 980h INDF0 A00h INDF0 A80h INDF0 B00h INDF0 B80h INDF0 1 41 801h INDF1 881h INDF1 901h INDF1 981h INDF1 A01h INDF1 A81h INDF1 B01h INDF1 B81h INDF1 1 3E 802h PCL 882h PCL 902h PCL 982h PCL A02h PCL A82h PCL B02h PCL B82h PCL 2 -p 803h STATUS 883h STATUS 903h STATUS 983h STATUS A03h STATUS A83h STATUS B03h STATUS B83h STATUS ag 804h FSR0L 884h FSR0L 904h FSR0L 984h FSR0L A04h FSR0L A84h FSR0L B04h FSR0L B84h FSR0L ( e L 2 805h FSR0H 885h FSR0H 905h FSR0H 985h FSR0H A05h FSR0H A85h FSR0H B05h FSR0H B85h FSR0H 4 806h FSR1L 886h FSR1L 906h FSR1L 986h FSR1L A06h FSR1L A86h FSR1L B06h FSR1L B86h FSR1L ) F 807h FSR1H 887h FSR1H 907h FSR1H 987h FSR1H A07h FSR1H A87h FSR1H B07h FSR1H B87h FSR1H 808h BSR 888h BSR 908h BSR 988h BSR A08h BSR A88h BSR B08h BSR B88h BSR 1 809h WREG 889h WREG 909h WREG 989h WREG A09h WREG A89h WREG B09h WREG B89h WREG 8 80Ah PCLATH 88Ah PCLATH 90Ah PCLATH 98Ah PCLATH A0Ah PCLATH A8Ah PCLATH B0Ah PCLATH B8Ah PCLATH 2 80Bh INTCON 88Bh INTCON 90Bh INTCON 98Bh INTCON A0Bh INTCON A8Bh INTCON B0Bh INTCON B8Bh INTCON 2 80Ch — 88Ch — 90Ch — 98Ch — A0Ch — A8Ch — B0Ch — B8Ch — 80Dh — 88Dh — 90Dh — 98Dh — A0Dh — A8Dh — B0Dh — B8Dh — / 1 80Eh — 88Eh — 90Eh — 98Eh — A0Eh — A8Eh — B0Eh — B8Eh — 80Fh — 88Fh — 90Fh — 98Fh — A0Fh — A8Fh — B0Fh — B8Fh — 6 810h — 890h — 910h — 990h — A10h — A90h — B10h — B90h — ( 811h — 891h — 911h — 991h — A11h — A91h — B11h — B91h — L 812h — 892h — 912h — 992h — A12h — A92h — B12h — B92h — ) 813h — 893h — 913h — 993h — A13h — A93h — B13h — B93h — F 814h — 894h — 914h — 994h — A14h — A94h — B14h — B94h — 1 815h — 895h — 915h — 995h — A15h — A95h — B15h — B95h — 8 816h — 896h — 916h — 996h — A16h — A96h — B16h — B96h — 817h — 897h — 917h — 997h — A17h — A97h — B17h — B97h — 2 818h — 898h — 918h — 998h — A18h — A98h — B18h — B98h — 3 819h — 899h — 919h — 999h — A19h — A99h — B19h — B99h — 81Ah — 89Ah — 91Ah — 99Ah — A1Ah — A9Ah — B1Ah — B9Ah — 81Bh — 89Bh — 91Bh — 99Bh — A1Bh — A9Bh — B1Bh — B9Bh — 81Ch — 89Ch — 91Ch — 99Ch — A1Ch — A9Ch — B1Ch — B9Ch — 81Dh — 89Dh — 91Dh — 99Dh — A1Dh — A9Dh — B1Dh — B9Dh — 81Eh — 89Eh — 91Eh — 99Eh — A1Eh — A9Eh — B1Eh — B9Eh —  81Fh — 89Fh — 91Fh — 99Fh — A1Fh — A9Fh — B1Fh — B9Fh — 20 820h 8A0h 920h 9A0h A20h AA0h B20h BA0h 1 0 -20 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented 15 Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ M icro 86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh ch 870h 8F0h 970h 9F0h A70h AF0h B70h BF0h ip Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses T 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh e c h 87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh n o log Legend: = Unimplemented data memory locations, read as ‘0’. y In c .

 TABLE 3-6: PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANKS 24-31 20 BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31 1 0 -2 C00h INDF0 C80h INDF0 D00h INDF0 D80h INDF0 E00h INDF0 E80h INDF0 F00h INDF0 F80h INDF0 01 C01h INDF1 C81h INDF1 D01h INDF1 D81h INDF1 E01h INDF1 E81h INDF1 F01h INDF1 F81h INDF1 5 M C02h PCL C82h PCL D02h PCL D82h PCL E02h PCL E82h PCL F02h PCL F82h PCL ic C03h STATUS C83h STATUS D03h STATUS D83h STATUS E03h STATUS E83h STATUS F03h STATUS F83h STATUS roc C04h FSR0L C84h FSR0L D04h FSR0L D84h FSR0L E04h FSR0L E84h FSR0L F04h FSR0L F84h FSR0L hip C05h FSR0H C85h FSR0H D05h FSR0H D85h FSR0H E05h FSR0H E85h FSR0H F05h FSR0H F85h FSR0H T C06h FSR1L C86h FSR1L D06h FSR1L D86h FSR1L E06h FSR1L E86h FSR1L F06h FSR1L F86h FSR1L e c C07h FSR1H C87h FSR1H D07h FSR1H D87h FSR1H E07h FSR1H E87h FSR1H F07h FSR1H F87h FSR1H h no C08h BSR C88h BSR D08h BSR D88h BSR E08h BSR E88h BSR F08h BSR F88h BSR lo C09h WREG C89h WREG D09h WREG D89h WREG E09h WREG E89h WREG F09h WREG F89h WREG g y Inc CC00BAhh PINCTLCAOTNH CC88BAhh PINCTLCAOTNH DD00BAhh PINCTLCAOTNH DD88BAhh PINCTLCAOTNH EE00BAhh PINCTLCAOTNH EE88BAhh PINCTLCAOTNH FF00BAhh PINCTLCAOTNH FF88BAhh PINCTLCAOTNH . C0Ch — C8Ch — D0Ch — D8Ch — E0Ch — E8Ch — F0Ch — F8Ch C0Dh — C8Dh — D0Dh — D8Dh — E0Dh — E8Dh — F0Dh — F8Dh C0Eh — C8Eh — D0Eh — D8Eh — E0Eh — E8Eh — F0Eh — F8Eh C0Fh — C8Fh — D0Fh — D8Fh — E0Fh — E8Fh — F0Fh — F8Fh C10h — C90h — D10h — D90h — E10h — E90h — F10h — F90h C11h — C91h — D11h — D91h — E11h — E91h — F11h — F91h P C12h — C92h — D12h — D92h — E12h — E92h — F12h — F92h C13h — C93h — D13h — D93h — E13h — E93h — F13h — F93h I C C14h — C94h — D14h — D94h — E14h — E94h — F14h — F94h C15h — C95h — D15h — D95h — E15h — E95h — F15h — F95h 1 C16h — C96h — D16h — D96h — E16h — E96h — F16h — F96h 2 C17h — C97h — D17h — D97h — E17h — E97h — F17h — F97h See Table3-7 for ( C18h — C98h — D18h — D98h — E18h — E98h — F18h — F98h register mapping L C19h — C99h — D19h — D99h — E19h — E99h — F19h — F99h details ) C1Ah — C9Ah — D1Ah — D9Ah — E1Ah — E9Ah — F1Ah — F9Ah F C1Bh — C9Bh — D1Bh — D9Bh — E1Bh — E9Bh — F1Bh — F9Bh C1Ch — C9Ch — D1Ch — D9Ch — E1Ch — E9Ch — F1Ch — F9Ch 1 C1Dh — C9Dh — D1Dh — D9Dh — E1Dh — E9Dh — F1Dh — F9Dh 8 C1Eh — C9Eh — D1Eh — D9Eh — E1Eh — E9Eh — F1Eh — F9Eh 2 C1Fh — C9Fh — D1Fh — D9Fh — E1Fh — E9Fh — F1Fh — F9Fh 2 C20h CA0h D20h DA0h E20h EA0h F20h FA0h / 1 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 6 ( D L S C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh 40 C70h CF0h D70h DF0h E70h EF0h F70h FF0h ) 00 Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses F 141 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 1 3 CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh E 8 -pa Legend: = Unimplemented data memory locations, read as ‘0’. 2 g e 2 3 5

PIC12(L)F1822/16(L)F1823 TABLE 3-7: PIC12(L)F1822/16(L)F1823 3.2.6 SPECIAL FUNCTION REGISTERS MEMORY MAP, BANK 31 SUMMARY Bank 31 The Special Function Register Summary for the device family are as follows: FA0h Unimplemented Device Bank(s) Page No. Read as ‘0’ 0 27 FE3h 1 28 FE4h STATUS_SHAD FE5h WREG_SHAD 2 29 FE6h BSR_SHAD 3 30 FE7h PCLATH_SHAD FE8h FSR0L_SHAD 4 31 PIC12(L)F1822 FE9h FSR0H_SHAD 5 32 PIC16(L)F1823 FEAh FSR1L_SHAD 6 33 FEBh FSR1H_SHAD FECh — 7 34 FEDh STKPTR 8 35 FEEh TOSL 9-30 36 FEFh TOSH Legend: = Unimplemented data memory locations, 31 37 read as ‘0’. DS40001413E-page 26  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 0 000h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 001h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 002h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 003h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 004h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 005h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 006h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 007h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 008h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000 009h(1) WREG Working Register 0000 0000 uuuu uuuu 00Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 00Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx 00Dh — Unimplemented — — 00Eh PORTC(2) — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --xx xxxx 00Fh — Unimplemented — — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 012h PIR2 OSFIF C2IF(2) C1IF EEIF BCL1IF — — — 0000 0--- 0000 0--- 013h — Unimplemented — — 014h — Unimplemented — — 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 018h T1CON TMR1CS1 TMR1CS0 T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 0000 00-0 uuuu uu-u 019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu DONE 01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000 01Bh PR2 Timer2 Period Register 1111 1111 1111 1111 01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000 01Dh — Unimplemented — — 01Eh CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 00-- 0000 00-- 0000 01Fh CPSCON1 — — — — CPSCH<3:2>(2) CPSCH<1:0> ---- 0000 ---- 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as ‘1’. 4: PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 27

PIC12(L)F1822/16(L)F1823 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 1 080h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 081h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 082h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 083h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 084h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 085h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 086h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 087h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 088h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000 089h(1) WREG Working Register 0000 0000 uuuu uuuu 08Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 08Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 08Ch TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 08Dh — Unimplemented — — 08Eh TRISC(2) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 08Fh — Unimplemented — — 090h — Unimplemented — — 091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 092h PIE2 OSFIE C2IE(2) C1IE EEIE BCL1IE — — — 0000 0--- 0000 0--- 093h — Unimplemented — — 094h — Unimplemented — — 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111 096h PCON STKOVF STKUNF — — RMCLR RI POR BOR 00-- 11qq qq-- qquu 097h WDTCON — — WDTPS<4:0> SWDTEN --01 0110 --01 0110 098h OSCTUNE — — TUN<5:0> --00 0000 --00 0000 099h OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 0011 1-00 0011 1-00 09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q 09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu 09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu 09Dh ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000 09Eh ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 0000 --00 0000 --00 09Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as ‘1’. 4: PIC12(L)F1822 only. DS40001413E-page 28  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 2 100h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 101h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 102h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 103h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 104h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 105h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 106h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 107h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 108h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000 109h(1) WREG Working Register 0000 0000 uuuu uuuu 10Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 10Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 10Ch LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu 10Dh — Unimplemented — — 10Eh LATC(2) — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 --xx xxxx --uu uuuu 10Fh — Unimplemented — — 110h — Unimplemented — — 111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100 112h CM1CON1 C1INTP C1INTN C1PCH<1:0> — — C1NCH1(2) C1NCH0 0000 ---0 0000 ---0 113h CM2CON0(2) C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 0000 -100 0000 -100 114h CM2CON1(2) C2INTP C2INTN C2PCH<1:0> — — C2NCH<1:0> 0000 --00 0000 --00 115h CMOUT — — — — — — MC2OUT(2) MC1OUT ---- --00 ---- --00 116h BORCON SBOREN — — — — — — BORRDY 1--- ---q u--- ---u 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000 118h DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — — 000- 00-- 000- 00-- 119h DACCON1 — — — DACR<4:0> ---0 0000 ---0 0000 11Ah SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000 11Bh SRCON1 SRSPE SRSCKE SRSC2E(2) SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000 (2) 11Ch — Unimplemented — — 11Dh APFCON RXDTSEL SDOSEL SSSEL --- T1GSEL TXCKSEL P1BSEL(4) CCP1SEL 000- 0000 000- 0000 (4) 11Eh — Unimplemented — — 11Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as ‘1’. 4: PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 29

PIC12(L)F1822/16(L)F1823 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 3 180h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 181h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 182h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 183h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 184h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 185h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 186h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 187h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 188h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000 189h(1) WREG Working Register 0000 0000 uuuu uuuu 18Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 18Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111 18Dh — Unimplemented — — 18Eh ANSELC(2) — — — — ANSC3 ANSC2 ANSC1 ANSC0 ---- 1111 ---- 1111 18Fh — Unimplemented — — 190h — Unimplemented — — 191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000 192h EEADRH —(3) EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000 193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu 194h EEDATH — — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu 195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000 196h EECON2 EEPROM control register 2 0000 0000 0000 0000 197h — Unimplemented — — 198h — Unimplemented — — 199h RCREG USART Receive Data Register 0000 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000 19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as ‘1’. 4: PIC12(L)F1822 only. DS40001413E-page 30  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 4 200h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 201h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 202h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 203h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 204h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 205h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 206h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 207h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 208h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000 209h(1) WREG Working Register 0000 0000 uuuu uuuu 20Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 20Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111 20Dh — Unimplemented — — 20Eh WPUC(2) — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 --11 1111 --11 1111 20Fh — Unimplemented — — 210h — Unimplemented — — 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD ADD<7:0> 0000 0000 0000 0000 213h SSP1MSK MSK<7:0> 1111 1111 1111 1111 214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h — Unimplemented — — 219h — Unimplemented — — 21Ah — Unimplemented — — 21Bh — Unimplemented — — 21Ch — Unimplemented — — 21Dh — Unimplemented — — 21Eh — Unimplemented — — 21Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as ‘1’. 4: PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 31

PIC12(L)F1822/16(L)F1823 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 5 280h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 281h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 282h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 283h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 284h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 285h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 286h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 287h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 288h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000 289h(1) WREG Working Register 0000 0000 uuuu uuuu 28Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 28Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 28Ch — Unimplemented — — 28Dh — Unimplemented — — 28Eh — Unimplemented — — 28Fh — Unimplemented — — 290h — Unimplemented — — 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000 294h PWM1CON P1RSEN P1DC<6:0> 0000 0000 0000 0000 295h CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 0000 0000 296h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001 297h — Unimplemented — — 298h — Unimplemented — — 299h — Unimplemented — — 29Ah — Unimplemented — — 29Bh — Unimplemented — — 29Ch — Unimplemented — — 29Dh — Unimplemented — — 29Eh — Unimplemented — — 29Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as ‘1’. 4: PIC12(L)F1822 only. DS40001413E-page 32  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 6 300h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 301h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 302h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 303h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 304h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 305h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 306h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 307h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 308h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000 309h(1) WREG Working Register 0000 0000 uuuu uuuu 30Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 30Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 30Ch — Unimplemented — — 30Dh — Unimplemented — — 30Eh — Unimplemented — — 30Fh — Unimplemented — — 310h — Unimplemented — — 311h — Unimplemented — — 312h — Unimplemented — — 313h — Unimplemented — — 314h — Unimplemented — — 315h — Unimplemented — — 316h — Unimplemented — — 317h — Unimplemented — — 318h — Unimplemented — — 319h — Unimplemented — — 31Ah — Unimplemented — — 31Bh — Unimplemented — — 31Ch — Unimplemented — — 31Dh — Unimplemented — — 31Eh — Unimplemented — — 31Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as ‘1’. 4: PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 33

PIC12(L)F1822/16(L)F1823 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 7 380h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 381h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 382h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 383h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 384h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 385h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 386h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 387h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 388h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000 389h(1) WREG Working Register 0000 0000 uuuu uuuu 38Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 38Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 38Ch — Unimplemented — — 38Dh — Unimplemented — — 38Eh — Unimplemented — — 38Fh — Unimplemented — — 390h — Unimplemented — — 391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000 392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 394h — Unimplemented — — 395h — Unimplemented — — 396h — Unimplemented — — 397h — Unimplemented — — 398h — Unimplemented — — 399h — Unimplemented — — 39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> 0011 0000 0011 0000 39Bh — Unimplemented — — 39Ch MDCON MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT 0010 ---0 0010 ---0 39Dh MDSRC MDMSODIS — — — MDMS<3:0> x--- xxxx u--- uuuu 39Eh MDCARL MDCLODIS MDCLPOL MDCLSYNC — MDCL<3:0> xxx- xxxx uuu- uuuu 39Fh MDCARH MDCHODIS MDCHPOL MDCHSYNC — MDCH<3:0> xxx- xxxx uuu- uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as ‘1’. 4: PIC12(L)F1822 only. DS40001413E-page 34  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 8 400h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 401h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) 402h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 403h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu 404h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 405h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 406h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 407h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 408h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000 409h(1) WREG Working Register 0000 0000 uuuu uuuu 40Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 40Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 40Ch — Unimplemented — — 40Dh — Unimplemented — — 40Eh — Unimplemented — — 40Fh — Unimplemented — — 410h — Unimplemented — — 411h — Unimplemented — — 412h — Unimplemented — — 413h — Unimplemented — — 414h — Unimplemented — — 415h — Unimplemented — — 416h — Unimplemented — — 417h — Unimplemented — — 418h — Unimplemented — — 419h — Unimplemented — — 41Ah — Unimplemented — — 41Bh — Unimplemented — — 41Ch — Unimplemented — — 41Dh — Unimplemented — — 41Eh — Unimplemented — — 41Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as ‘1’. 4: PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 35

PIC12(L)F1822/16(L)F1823 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Banks 9-30 x00h/ INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx x80h(1) (not a physical register) x00h/ INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx x81h(1) (not a physical register) x02h/ PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x82h(1) x03h/ STATUS — — — TO PD Z DC C ---1 1000 ---q quuu x83h(1) x04h/ FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x84h(1) x05h/ FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x85h(1) x06h/ FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x86h(1) x07h/ FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x87h(1) x08h/ BSR — — — BSR<4:0> ---0 0000 ---0 0000 x88h(1) x09h/ WREG Working Register 0000 0000 uuuu uuuu x89h(1) x0Ah/ PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 x8Ah(1) x0Bh/ INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u x8Bh(1) x0Ch/ — Unimplemented — — x8Ch — x1Fh/ x9Fh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as ‘1’. 4: PIC12(L)F1822 only. DS40001413E-page 36  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 31 F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx (not a physical register) F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx (not a physical register) F82h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 F83h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu F84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu F85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 F86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu F87h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 F88h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000 F89h(1) WREG Working Register 0000 0000 uuuu uuuu F8Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 F8Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u F8Ch — Unimplemented — — — FE3h FE4h STATUS_ — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow 0000 0000 uuuu uuuu SHAD FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu SHAD FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu SHAD FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FECh — Unimplemented — — FEDh STKPTR — — — Current Stack pointer ---1 1111 ---1 1111 FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu uuuu FEFh TOSH — Top-of-Stack High byte -xxx xxxx -uuu uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC16(L)F1823 only. 3: Unimplemented. Read as ‘1’. 4: PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 37

PIC12(L)F1822/16(L)F1823 3.3 PCL and PCLATH 3.3.3 COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte A computed function CALL allows programs to maintain comes from the PCL register, which is a readable and tables of functions and provide another way to execute writable register. The high byte (PC<14:8>) is not directly state machines or look-up tables. When performing a readable or writable and comes from PCLATH. On any table read using a computed function CALL, care Reset, the PC is cleared. Figure3-3 shows the five should be exercised if the table location crosses a PCL situations for the loading of the PC. memory boundary (each 256-byte block). If using the CALL instruction, the PCH<2:0> and PCL FIGURE 3-3: LOADING OF PC IN registers are loaded with the operand of the CALL DIFFERENT SITUATIONS instruction. PCH<6:3> is loaded with PCLATH<6:3>. The CALLW instruction enables computed calls by com- 14 PCH PCL 0 Instruction with PC PCL as bining PCLATH and W to form the destination address. Destination A computed CALLW is accomplished by loading the W 6 7 0 8 register with the desired address and executing CALLW. PCLATH ALU Result The PCL register is loaded with the value of W and PCH is loaded with PCLATH. 14 PCH PCL 0 3.3.4 BRANCHING PC GOTO, CALL The branching instructions add an offset to the PC. 6 4 0 11 This allows relocatable code and code that crosses PCLATH OPCODE <10:0> page boundaries. There are two forms of branching, 14 PCH PCL 0 BRW and BRA. The PC will have incremented to fetch PC CALLW the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be 6 7 0 8 crossed. PCLATH W If using BRW, load the W register with the desired 14 PCH PCL 0 unsigned address and execute BRW. The entire PC will PC BRW be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC+1+, 15 PC + W the signed value of the operand of the BRA instruction. 14 PCH PCL 0 PC BRA 15 PC + OPCODE <8:0> 3.3.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writ- ing the desired upper seven bits to the PCLATH regis- ter. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 3.3.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). DS40001413E-page 38  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 3.4 Stack 3.4.1 ACCESSING THE STACK All devices have a 16-levelx15-bit wide hardware The stack is available through the TOSH, TOSL and stack (refer to Figures3-4through3-7). The stack STKPTR registers. STKPTR is the current value of the space is not part of either program or data space. The Stack Pointer. TOSH:TOSL register pair points to the PC is PUSHed onto the stack when CALL or CALLW TOP of the stack. Both registers are read/writable. TOS instructions are executed or an interrupt causes a is split into TOSH and TOSL due to the 15-bit size of the branch. The stack is POPed in the event of a RETURN, PC. To access the stack, adjust the value of STKPTR, RETLW or a RETFIE instruction execution. PCLATH is which will position TOSH:TOSL, then read/write to not affected by a PUSH or POP operation. TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Word 2). This Note: Care should be taken when modifying the means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled. times, the seventeenth PUSH overwrites the value that During normal program operation, CALL, CALLW and was stored from the first PUSH. The eighteenth PUSH Interrupts will increment STKPTR while RETLW, overwrites the second PUSH (and so on). The RETURN, and RETFIE will decrement STKPTR. At any STKOVF and STKUNF flag bits will be set on an Over- time STKPTR can be inspected to see how much stack flow/Underflow, regardless of whether the Reset is is left. The STKPTR always points at the currently used enabled. place on the stack. Therefore, a CALL or CALLW will Note1: There are no instructions/mnemonics increment the STKPTR and then write the PC, and a called PUSH or POP. These are actions return will unload the PC and then decrement STKPTR. that occur from the execution of the Reference Figure3-4 through Figure3-7 for examples CALL, CALLW, RETURN, RETLW and of accessing the stack. RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 Stack Reset Disabled TOSH:TOSL 0x0F STKPTR = 0x1F (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The 0x08 empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack 0x07 Overflow/Underflow Reset is enabled, the 0x06 TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is 0x05 disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x04 0x03 0x02 0x01 0x00 Stack Reset Enabled TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F (STVREN = 1)  2010-2015 Microchip Technology Inc. DS40001413E-page 39

PIC12(L)F1822/16(L)F1823 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the return address will be placed in the 0x07 Program Counter and the Stack Pointer 0x06 decremented to the empty state (0x1F). 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL 0x00 Return Address STKPTR = 0x00 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an 0x0B interrupt, the stack looks like the figure on the left. A series of RETURN instructions 0x0A will repeatedly place the return addresses into the Program Counter and pop the stack. 0x09 0x08 0x07 TOSH:TOSL 0x06 Return Address STKPTR = 0x06 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address DS40001413E-page 40  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address When the stack is full, the next CALL or 0x09 Return Address an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 0x08 Return Address so the stack will wrap and overwrite the return address at 0x00. If the Stack 0x07 Return Address Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will 0x06 Return Address not be overwritten. 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address TOSH:TOSL 0x00 Return Address STKPTR = 0x10 3.4.2 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Word 2 is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.5 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2010-2015 Microchip Technology Inc. DS40001413E-page 41

PIC12(L)F1822/16(L)F1823 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Reserved 0x7FFF Address Range 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS40001413E-page 42  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing Indirect Addressing 4 BSR 0 6 From Opcode 0 7 FSRxH 0 7 FSRxL 0 0 0 0 0 Bank Select Location Select Bank Select Location Select 00000 00001 00010 11111 0x00 0x7F Bank 0 Bank 1 Bank 2 Bank 31  2010-2015 Microchip Technology Inc. DS40001413E-page 43

PIC12(L)F1822/16(L)F1823 3.5.2 LINEAR DATA MEMORY 3.5.3 PROGRAM FLASH MEMORY The linear data memory is the region from FSR To make constant data access easier, the entire address 0x2000 to FSR address 0x29AF. This region is program Flash memory is mapped to the upper half of a virtual region that points back to the 80-byte blocks of the FSR address space. When the MSB of FSRnH is GPR memory in all the banks. set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the Unimplemented memory reads as 0x00. Use of the lower eight bits of each memory location is accessible linear data memory region allows buffers to be larger via INDF. Writing to the program Flash memory cannot than 80 bytes because incrementing the FSR beyond be accomplished via the FSR/INDF interface. All one bank will go directly to the GPR memory of the next instructions that access program Flash memory via the bank. FSR/INDF interface will require one additional The 16 bytes of common memory are not included in instruction cycle to complete. the linear data memory region. FIGURE 3-11: PROGRAM FLASH FIGURE 3-10: LINEAR DATA MEMORY MEMORY MAP MAP 7 FSRnH 0 7 FSRnL 0 7 FSRnH 0 7 FSRnL 0 1 0 0 1 Location Select 0x8000 0x0000 Location Select 0x2000 0x020 Bank 0 0x06F 0x0A0 Bank 1 Program 0x0EF Flash 0x120 Memory (low 8 Bank 2 bits) 0x16F 0xF20 Bank 30 0xFFFF 0x7FFF 0x29AF 0xF6F DS40001413E-page 44  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 register at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2010-2015 Microchip Technology Inc. DS40001413E-page 45

PIC12(L)F1822/16(L)F1823 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 FCMEN IESO CLKOUTEN BOREN<1:0> CPD bit 13 bit 8 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit If FOSC configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin All other FOSC modes: 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin 0 = CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 7 CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of the WPUA register. bit 5 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off. DS40001413E-page 46  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 4-1: CONFIGURATION WORD 1 (CONTINUED) bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-32MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off.  2010-2015 Microchip Technology Inc. DS40001413E-page 47

PIC12(L)F1822/16(L)F1823 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1/1 R/P-1/1 U-1 R/P-1/1 R/P-1/1 R/P-1/1 LVP(1) DEBUG(2) — BORV STVREN PLLEN bit 13 bit 8 U-1 U-1 U-1 R-1 U-1 U-1 R/P-1/1 R/P-1/1 — — — Reserved — — WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(2) 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 Unimplemented: Read as ‘1’ bit 10 BORV: Brown-out Reset Voltage Selection bit(3) 1 = Brown-out Reset voltage (Vbor), low trip point selected 0 = Brown-out Reset voltage (Vbor), high trip point selected bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7-5 Unimplemented: Read as ‘1’ bit 4 Reserved: This location should be programmed to a ‘1’. bit 3-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 11 =Write protection off 10 =000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control 01 =000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control 00 =000h to 7FFh write-protected, no addresses may be modified by EECON control Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. 2: The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 3: See Vbor parameter for specific trip point voltages. DS40001413E-page 48  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word 1. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section4.3 “Write Protection” for more information. 4.2.2 DATA EEPROM PROTECTION The entire data EEPROM is protected from external reads and writes by the CPD bit. When CPD = 0, external reads and writes of data EEPROM are inhibited. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 4.3 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Word 2 define the size of the program memory block that is protected. 4.4 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F/LF1826/27/PIC12F/LF1822 Memory Programming Specification” (DS41390).  2010-2015 Microchip Technology Inc. DS40001413E-page 49

PIC12(L)F1822/16(L)F1823 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. REGISTER 4-3: DEVICEID: DEVICE ID REGISTER(1) R R R R R R DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 13 bit 8 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit ‘0’ = Bit is cleared ‘1’ = Bit is set bit 13-5 DEV<8:0>: Device ID bits 100111000 = PIC12F1822 100111001 = PIC16F1823 101000000 = PIC12LF1822 101000001 = PIC16LF1823 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. Note 1: This location cannot be written. DS40001413E-page 50  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 5.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of eight FAIL-SAFE CLOCK MONITOR) clock modes. 1. ECL – External Clock Low-Power mode 5.1 Overview (0MHz to 0.5MHz) 2. ECM – External Clock Medium-Power mode The oscillator module has a wide variety of clock (0.5MHz to 4MHz) sources and selection features that allow it to be used 3. ECH – External Clock High-Power mode in a wide range of applications while maximizing perfor- (4MHz to 32MHz) mance and minimizing power consumption. Figure5-1 4. LP – 32kHz Low-Power Crystal mode. illustrates a block diagram of the oscillator module. 5. XT – Medium Gain Crystal or Ceramic Resonator Clock sources can be supplied from external oscillators, Oscillator mode (up to 4 MHz) quartz crystal resonators, ceramic resonators and 6. HS – High Gain Crystal or Ceramic Resonator Resistor-Capacitor (RC) circuits. In addition, the system mode (4 MHz to 20 MHz) clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds 7. RC – External Resistor-Capacitor (RC). selectable via software. Additional clock features 8. INTOSC – Internal oscillator (31kHz to 32 MHz). include: Clock Source modes are selected by the FOSC<2:0> • Selectable system clock source between external bits in the Configuration Word 1. The FOSC bits or internal sources via software. determine the type of oscillator that will be used when • Two-Speed Start-up mode, which minimizes the device is first powered. latency between external oscillator start-up and The EC clock mode relies on an external logic level code execution. signal as the device clock source. The LP, XT and HS • Fail-Safe Clock Monitor (FSCM) designed to clock modes require an external crystal or resonator to detect a failure of the external clock source (LP, be connected to the device. Each mode is optimized for XT, HS, EC or RC modes) and switch a different frequency range. The RC clock mode automatically to the internal oscillator. requires an external resistor and capacitor to set the • Oscillator Start-up Timer (OST) ensures stability oscillator frequency. of crystal oscillator sources The INTOSC internal oscillator block produces low, medium, and high frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure5-1). A wide selection of device clock frequencies may be derived from these three clock sources.  2010-2015 Microchip Technology Inc. DS40001413E-page 51

PIC12(L)F1822/16(L)F1823 FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM External Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL Sleep OSC1 Oscillator Timer1 FOSC<2:0> = 100 T1OSC X CPU and T1OSO U Peripherals M T1OSCEN Enable T1OSI Oscillator IRCF<3:0> Internal Oscillator 16 MHz 8 MHz Internal Oscillator 4 MHz Block 2 MHz er 1 MHz Clock HFPLL 16 MHz scal 500 kHz UX Control (HFINTOSC) ost 250 kHz M P 125 kHz FOSC<2:0> SCS<1:0> 500 kHz Source 500 kHz 62.5 kHz (MFINTOSC) 31.25 kHz Clock Source Option for other modules 31 kHz 31 kHz Source 31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules DS40001413E-page 52  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 5.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully clock source to function. Examples are: oscillator mod- static, stopping the external clock input will have the ules (EC mode), quartz crystal resonators or ceramic effect of halting the device while leaving all data intact. resonators (LP, XT and HS modes) and Upon restarting the external clock, the device will Resistor-Capacitor (RC) mode circuits. resume operation as if no time had elapsed. Internal clock sources are contained internally within FIGURE 5-2: EXTERNAL CLOCK (EC) the oscillator module. The internal oscillator block has MODE OPERATION two internal oscillators and a dedicated Phase-Locked Loop (HFPLL) that are used to generate three internal system clock sources: the 16MHz High-Frequency Clock from OSC1/CLKIN Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) Ext. System and the 31kHz Low-Frequency Internal Oscillator PIC® MCU (LFINTOSC). OSC2/CLKOUT The system clock can be selected between external or FOSC/4 or I/O(1) internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section5.3 Note 1: Output depends upon CLKOUTEN bit of the “Clock Switching” for additional information. Configuration Word 1. 5.2.1 EXTERNAL CLOCK SOURCES 5.2.1.2 LP, XT, HS Modes An external clock source can be used as the device system clock by performing one of the following The LP, XT and HS modes support the use of quartz actions: crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure5-3). The three modes select • Program the FOSC<2:0> bits in the Configuration a low, medium or high gain setting of the internal Word 1 to select an external clock source that will inverter-amplifier to support various resonator types be used as the default system clock upon a and speed. device Reset. • Write the SCS<1:0> bits in the OSCCON register LP Oscillator mode selects the lowest gain setting of the to switch the system clock source to: internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to - Timer1 Oscillator during run-time, or drive only 32.768 kHz tuning-fork type crystals (watch - An external clock source determined by the crystals). value of the FOSC bits. XT Oscillator mode selects the intermediate gain See Section5.3 “Clock Switching”for more informa- setting of the internal inverter-amplifier. XT mode tion. current consumption is the medium of the three modes. This mode is best suited to drive resonators with a 5.2.1.1 EC Mode medium drive level specification. The External Clock (EC) mode allows an externally HS Oscillator mode selects the highest gain setting of the generated logic level signal to be the system clock internal inverter-amplifier. HS mode current consumption source. When operating in this mode, an external clock is the highest of the three modes. This mode is best source is connected to the OSC1 input. suited for resonators that require a high drive setting. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure5-2 shows the pin connections for EC Figure5-3 and Figure5-4 show typical circuits for mode. quartz crystal and ceramic resonators, respectively. EC mode has three power modes to select from through Configuration Word 1: • High power, 4-32MHz (FOSC = 111) • Medium power, 0.5-4MHz (FOSC = 110) • Low power, 0-0.5MHz (FOSC = 101)  2010-2015 Microchip Technology Inc. DS40001413E-page 53

PIC12(L)F1822/16(L)F1823 FIGURE 5-3: QUARTZ CRYSTAL FIGURE 5-4: CERAMIC RESONATOR OPERATION (LP, XT OR OPERATION HS MODE) (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN OSC1/CLKIN C1 To Internal C1 To Internal Logic Logic QCruyasrttazl RF(2) Sleep RP(3) RF(2) Sleep C2 RS(1) OSC2/CLKOUT C2 Ceramic RS(1) OSC2/CLKOUT Resonator Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 3: An additional parallel feedback resistor (RP) Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator according to type, package and operation. manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 5.2.1.3 Oscillator Start-up Timer (OST) 2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts expected for the application. 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer 3: For oscillator design assistance, reference (PWRT) has expired (if configured), or a wake-up from the following Microchip Applications Notes: Sleep. During this time, the program counter does not • AN826, “Crystal Oscillator Basics and increment and program execution is suspended. The Crystal Selection for rfPIC® and PIC® OST ensures that the oscillator circuit, using a quartz Devices” (DS00826) crystal resonator or ceramic resonator, has started and • AN849, “Basic PIC® Oscillator Design” is providing a stable system clock to the oscillator (DS00849) module. • AN943, “Practical PIC® Oscillator In order to minimize latency between external oscillator Analysis and Design” (DS00943) start-up and code execution, the Two-Speed Clock • AN949, “Making Your Oscillator Work” Start-up mode can be selected (see Section5.4 (DS00949) “Two-Speed Clock Start-up Mode”). 5.2.1.4 4X PLL The oscillator module contains a 4X PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4X PLL must fall within specifications. See the PLL Clock Timing Specifications in Section30.0 “Electrical Specifications”. The 4X PLL may be enabled for use by one of two methods: 1. Program the PLLEN bit in Configuration Word 2 to a ‘1’. 2. Write the SPLLEN bit in the OSCCON register to a ‘1’. If the PLLEN bit in Configuration Word 2 is programmed to a ‘1’, then the value of SPLLEN is ignored. DS40001413E-page 54  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 5.2.1.5 TIMER1 Oscillator 5.2.1.6 External RC Mode The Timer1 Oscillator is a separate crystal oscillator The external Resistor-Capacitor (RC) modes support that is associated with the Timer1 peripheral. It is opti- the use of an external RC circuit. This allows the mized for timekeeping operations with a 32.768 kHz designer maximum flexibility in frequency choice while crystal connected between the T1OSO and T1OSI keeping costs to a minimum when clock accuracy is not device pins. required. The Timer1 Oscillator can be used as an alternate The RC circuit connects to OSC1. OSC2/CLKOUT is system clock source and can be selected during available for general purpose I/O or CLKOUT. The run-time using clock switching. Refer to Section5.3 function of the OSC2/CLKOUT pin is determined by the “Clock Switching” for more information. state of the CLKOUTEN bit in Configuration Word 1. Figure5-6 shows the external RC mode connections. FIGURE 5-5: QUARTZ CRYSTAL OPERATION (TIMER1 FIGURE 5-6: EXTERNAL RC MODES OSCILLATOR) VDD PIC® MCU PIC® MCU REXT T1OSI OSC1/CLKIN Internal Clock C1 To Internal CEXT Logic 32.768 kHz VSS Quartz Crystal FOSC/4 or I/O(1) OSC2/CLKOUT C2 T1OSO Recommended values: 10 k  REXT  100 k, <3V 3 k  REXT  100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: Quartz crystal characteristics vary Note 1: Output depends upon CLKOUTEN bit of the according to type, package and Configuration Word 1. manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values 2: Always verify oscillator performance over and the operating temperature. Other factors affecting the VDD and temperature range that is the oscillator frequency are: expected for the application. • threshold voltage variation 3: For oscillator design assistance, reference • component tolerances the following Microchip Applications Notes: • packaging variations in capacitance • AN826, “Crystal Oscillator Basics and The user also needs to take into account variation due Crystal Selection for rfPIC® and PIC® to tolerance of external RC components used. Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) • TB097, “Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288)  2010-2015 Microchip Technology Inc. DS40001413E-page 55

PIC12(L)F1822/16(L)F1823 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.1 HFINTOSC The device may be configured to use the internal oscil- The High-Frequency Internal Oscillator (HFINTOSC) is lator block as the system clock by performing one of the a factory calibrated 16MHz internal clock source. The following actions: frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register5-3). • Program the FOSC<2:0> bits in Configuration Word 1 to select the INTOSC clock source, which The output of the HFINTOSC connects to a postscaler will be used as the default system clock upon a and multiplexer (see Figure5-1). One of nine device Reset. frequencies derived from the HFINTOSC can be • Write the SCS<1:0> bits in the OSCCON register selected via software using the IRCF<3:0> bits of the to switch the system clock source to the internal OSCCON register. See Section5.2.2.7 “Internal oscillator during run-time. See Section5.3 Oscillator Clock Switch Timing” for more information. “Clock Switching”for more information. The HFINTOSC is enabled by: In INTOSC mode, OSC1/CLKIN is available for general • Configure the IRCF<3:0> bits of the OSCCON purpose I/O. OSC2/CLKOUT is available for general register for the desired HF frequency, and purpose I/O or CLKOUT. • FOSC<2:0> = 100, or The function of the OSC2/CLKOUT pin is determined • Set the System Clock Source (SCS) bits of the by the state of the CLKOUTEN bit in Configuration OSCCON register to ‘1x’. Word 1. The High Frequency Internal Oscillator Ready bit The internal oscillator block has two independent (HFIOFR) of the OSCSTAT register indicates when the oscillators and a dedicated Phase-Locked Loop, HFINTOSC is running and can be utilized. HFPLL that can produce one of three internal system The High Frequency Internal Oscillator Status Locked clock sources. bit (HFIOFL) of the OSCSTAT register indicates when 1. The HFINTOSC (High-Frequency Internal the HFINTOSC is running within 2% of its final value. Oscillator) is factory calibrated and operates at The High Frequency Internal Oscillator Status Stable 16MHz. The HFINTOSC source is generated bit (HFIOFS) of the OSCSTAT register indicates when from the 500 kHz MFINTOSC source and the the HFINTOSC is running within 0.5% of its final value. dedicated Phase-Locked Loop, HFPLL. The frequency of the HFINTOSC can be 5.2.2.2 MFINTOSC user-adjusted via software using the OSCTUNE register (Register5-3). The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500kHz internal 2. The MFINTOSC (Medium-Frequency Internal clock source. The frequency of the MFINTOSC can be Oscillator) is factory calibrated and operates at altered via software using the OSCTUNE register 500kHz. The frequency of the MFINTOSC can (Register5-3). be user-adjusted via software using the OSCTUNE register (Register5-3). The output of the MFINTOSC connects to a postscaler 3. The LFINTOSC (Low-Frequency Internal and multiplexer (see Figure5-1). One of nine Oscillator) is uncalibrated and operates at frequencies derived from the MFINTOSC can be 31kHz. selected via software using the IRCF<3:0> bits of the OSCCON register. See Section5.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The MFINTOSC is enabled by: • Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running and can be utilized. DS40001413E-page 56  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 5.2.2.3 Internal Oscillator Frequency 5.2.2.5 Internal Oscillator Frequency Adjustment Selection The 500 kHz internal oscillator is factory calibrated. The system clock speed can be selected via software This internal oscillator can be adjusted in software by using the Internal Oscillator Frequency Select bits writing to the OSCTUNE register (Register5-3). Since IRCF<3:0> of the OSCCON register. the HFINTOSC and MFINTOSC clock sources are The outputs of the 16MHz HFINTOSC postscaler and derived from the 500 kHz internal oscillator a change in the LFINTOSC connect to a multiplexer (see the OSCTUNE register value will apply to both. Figure5-1). The Internal Oscillator Frequency Select The default value of the OSCTUNE register is ‘0’. The bits IRCF<3:0> of the OSCCON register select the value is a 6-bit two’s complement number. A value of frequency output of the internal oscillators. One of the 1Fh will provide an adjustment to the maximum following frequencies can be selected via software: frequency. A value of 20h will provide an adjustment to • 32 MHz (requires 4X PLL) the minimum frequency. • 16 MHz When the OSCTUNE register is modified, the oscillator • 8 MHz frequency will begin shifting to the new frequency. Code • 4 MHz execution continues during this shift. There is no • 2 MHz indication that the shift has occurred. • 1 MHz OSCTUNE does not affect the LFINTOSC frequency. • 500 kHz (Default after Reset) Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer • 250 kHz (PWRT), Watchdog Timer (WDT), Fail-Safe Clock • 125 kHz Monitor (FSCM) and peripherals, are not affected by the • 62.5 kHz change in frequency. • 31.25 kHz 5.2.2.4 LFINTOSC • 31 kHz (LFINTOSC) The Low-Frequency Internal Oscillator (LFINTOSC) is Note: Following any Reset, the IRCF<3:0> bits an uncalibrated 31kHz internal clock source. of the OSCCON register are set to ‘0111’ and the frequency selection is set to The output of the LFINTOSC connects to a multiplexer 500kHz. The user can modify the IRCF (see Figure5-1). Select 31kHz, via software, using the bits to select a different frequency. IRCF<3:0> bits of the OSCCON register. See Section5.2.2.7 “Internal Oscillator Clock Switch The IRCF<3:0> bits of the OSCCON register allow Timing” for more information. The LFINTOSC is also duplicate selections for some frequencies. These dupli- the frequency for the Power-up Timer (PWRT), cate choices can offer system design trade-offs. Lower Watchdog Timer (WDT) and Fail-Safe Clock Monitor power consumption can be obtained when changing (FSCM). oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes The LFINTOSC is enabled by selecting 31kHz that use the same oscillator source. (IRCF<3:0> bits of the OSCCON register=000) as the system clock source (SCS bits of the OSCCON register= 1x), or when any of the following are enabled: • Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ Peripherals that use the LFINTOSC are: • Power-up Timer (PWRT) • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized.  2010-2015 Microchip Technology Inc. DS40001413E-page 57

PIC12(L)F1822/16(L)F1823 5.2.2.6 32 MHz Internal Oscillator 5.2.2.7 Internal Oscillator Clock Switch Frequency Selection Timing The Internal Oscillator Block can be used with the 4X When switching between the HFINTOSC, MFINTOSC PLL associated with the External Oscillator Block to and the LFINTOSC, the new oscillator may already be produce a 32 MHz internal system clock source. The shut down to save power (see Figure5-7). If this is the following settings are required to use the 32 MHz inter- case, there is a delay after the IRCF<3:0> bits of the nal clock source: OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will • The FOSC bits in Configuration Word 1 must be reflect the current active status of the HFINTOSC, set to use the INTOSC source as the device MFINTOSC and LFINTOSC oscillators. The sequence system clock (FOSC<2:0> = 100). of a frequency selection is as follows: • The SCS bits in the OSCCON register must be cleared to use the clock determined by 1. IRCF<3:0> bits of the OSCCON register are FOSC<2:0> in Configuration Word 1 modified. (SCS<1:0>=00). 2. If the new clock is shut down, a clock start-up • The IRCF bits in the OSCCON register must be delay is started. set to the 8 MHz HFINTOSC set to use 3. Clock switch circuitry waits for a falling edge of (IRCF<3:0>=1110). the current clock. • The SPLLEN bit in the OSCCON register must be 4. The current clock is held low and the clock set to enable the 4xPLL, or the PLLEN bit of the switch circuitry waits for a rising edge in the new Configuration Word 2 must be programmed to a clock. ‘1’. 5. The new clock is now active. Note: When using the PLLEN bit of the 6. The OSCSTAT register is updated as required. Configuration Word 2, the 4xPLL cannot 7. Clock switch is complete. be disabled by software and the 8 MHz See Figure5-7 for more details. HFINTOSC option will no longer be available. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay The 4xPLL is not available for use with the internal before the new frequency is selected. Clock switching oscillator when the SCS bits of the OSCCON register time delays are shown in Table5-1. are set to ‘1x’. The SCS bits must be set to ‘00’ to use Start-up delay specifications are located in the the 4xPLL with the internal oscillator. oscillator tables of Section30.0 “Electrical Specifications”. DS40001413E-page 58  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ LFINTOSC (FSCM and WDT disabled) MFINTOSC HFINTOSC/ MFINTOSC Oscillator Delay(1) 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled) MFINTOSC HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC   IRCF <3:0> 0 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Oscillator Delay(1) 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> = 0  0 System Clock Note 1: See Table5-1, Oscillator Switching Delays, for more information.  2010-2015 Microchip Technology Inc. DS40001413E-page 59

PIC12(L)F1822/16(L)F1823 5.3 Clock Switching 5.3.3 TIMER1 OSCILLATOR The system clock source can be switched between The Timer1 Oscillator is a separate crystal oscillator external and internal clock sources via software using associated with the Timer1 peripheral. It is optimized the System Clock Select (SCS) bits of the OSCCON for timekeeping operations with a 32.768 kHz crystal register. The following clock sources can be selected connected between the T1OSO and T1OSI device using the SCS bits: pins. • Default system oscillator determined by FOSC The Timer1 oscillator is enabled using the T1OSCEN bits in Configuration Word 1 control bit in the T1CON register. See Section21.0 “Timer1 Module with Gate Control” for more • Timer1 32 kHz crystal oscillator information about the Timer1 peripheral. • Internal Oscillator Block (INTOSC) 5.3.4 TIMER1 OSCILLATOR READY 5.3.1 SYSTEM CLOCK SELECT (SCS) (T1OSCR) BIT BITS The user must ensure that the Timer1 Oscillator is The System Clock Select (SCS) bits of the OSCCON ready to be used before it is selected as a system clock register selects the system clock source that is used for source. The Timer1 Oscillator Ready (T1OSCR) bit of the CPU and peripherals. the OSCSTAT register indicates whether the Timer1 • When the SCS bits of the OSCCON register = 00, oscillator is ready to be used. After the T1OSCR bit is the system clock source is determined by value of set, the SCS bits can be configured to select the Timer1 the FOSC<2:0> bits in the Configuration Word 1. oscillator. • When the SCS bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table5-1. 5.3.2 OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the Timer1 Oscillator. DS40001413E-page 60  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 5.4 Two-Speed Clock Start-up Mode 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode provides additional power savings by minimizing the latency between external Two-Speed Start-up mode is configured by the oscillator start-up and code execution. In applications following settings: that make heavy use of the Sleep mode, Two-Speed • IESO (of the Configuration Word 1) = 1; Inter- Start-up will remove the external oscillator start-up nal/External Switchover bit (Two-Speed Start-up time from the time spent awake and can reduce the mode enabled). overall power consumption of the device. This mode • SCS (of the OSCCON register) = 00. allows the application to wake-up from Sleep, perform • FOSC<2:0> bits in the Configuration Word 1 a few instructions using the INTOSC internal oscillator configured for LP, XT or HS mode. block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up mode is entered after: Two-Speed Start-up provides benefits when the oscil- • Power-on Reset (POR) and, if enabled, after lator module is configured for LP, XT or HS modes. Power-up Timer (PWRT) has expired, or The Oscillator Start-up Timer (OST) is enabled for • Wake-up from Sleep. these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT reg- ister is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 5-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) 31kHz Sleep/POR MFINTOSC(1) 31.25kHz-500 kHz Oscillator Warm-up Delay HFINTOSC(1) 31.25kHz-16MHz Sleep/POR EC, RC(1) DC – 32MHz 2 cycles LFINTOSC EC, RC(1) DC – 32MHz 1 cycle of each Timer1 Oscillator Sleep/POR 32kHz-20MHz 1024 Clock Cycles (OST) LP, XT, HS(1) MFINTOSC(1) 31.25kHz-500kHz Any clock source 2s (approx.) HFINTOSC(1) 31.25kHz-16MHz Any clock source LFINTOSC(1) 31kHz 1 cycle of each Any clock source Timer1 Oscillator 32kHz 1024 Clock Cycles (OST) PLL inactive PLL active 16-32MHz 2ms (approx.) Note 1: PLL inactive.  2010-2015 Microchip Technology Inc. DS40001413E-page 61

PIC12(L)F1822/16(L)F1823 5.4.2 TWO-SPEED START-UP 5.4.3 CHECKING TWO-SPEED CLOCK SEQUENCE STATUS 1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCSTAT 2. Instructions begin execution by the internal register will confirm if the microcontroller is running oscillator at the frequency set in the IRCF<3:0> from the external clock source, as defined by the bits of the OSCCON register. FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. 5. OSTS is set. 6. System clock held low until the next falling edge of new clock (LP, XT or HS mode). 7. System clock is switched to external clock source. FIGURE 5-8: TWO-SPEED START-UP INTOSC TTOST OSC1 0 1 1022 1023 OSC2 Program Counter P C - N PC PC + 1 System Clock DS40001413E-page 62  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset, to continue operating should the external oscillator fail. executing a SLEEP instruction or changing the SCS The FSCM can detect oscillator failure any time after bits of the OSCCON register. When the SCS bits are the Oscillator Start-up Timer (OST) has expired. The changed, the OST is restarted. While the OST is FSCM is enabled by setting the FCMEN bit in the running, the device continues to operate from the Configuration Word 1. The FSCM is applicable to all INTOSC selected in OSCCON. When the OST times external Oscillator modes (LP, XT, HS, EC, Timer1 out, the Fail-Safe condition is cleared after Oscillator and RC). successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to FIGURE 5-9: FSCM BLOCK DIAGRAM the external clock source. If the Fail-Safe condition still Clock Monitor exists, the OSFIF flag will again become set by Latch hardware. External S Q Clock 5.5.4 RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure LFINTOSC after the Oscillator Start-up Timer (OST) has expired. ÷ 64 R Q Oscillator The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or 31 kHz 488 Hz RC Clock modes so that the FSCM will be active as (~32 s) (~2 ms) soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also Sample Clock Clock enabled. Therefore, the device will always be executing Failure code while the OST is operating. Detected Note: Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active 5.5.1 FAIL-SAFE DETECTION during oscillator start-up (i.e., after exiting The FSCM module detects a failed oscillator by Reset or Sleep). After an appropriate comparing the external oscillator to the FSCM sample amount of time, the user should check the clock. The sample clock is generated by dividing the Status bits in the OSCSTAT register to LFINTOSC by 64. See Figure5-9. Inside the fail verify the oscillator start-up and that the detector block is a latch. The external clock sets the system clock switchover has successfully latch on each falling edge of the external clock. The completed. sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2010-2015 Microchip Technology Inc. DS40001413E-page 63

PIC12(L)F1822/16(L)F1823 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS40001413E-page 64  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 5.6 Oscillator Control Registers REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0 SPLLEN IRCF<3:0> — SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Word 1 = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Word 1 = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 000x = 31kHz LF 0010 = 31.25kHz MF 0011 = 31.25kHz HF(1) 0100 = 62.5kHz MF 0101 = 125kHz MF 0110 = 250kHz MF 0111 = 500kHz MF (default upon Reset) 1000 = 125kHz HF(1) 1001 = 250kHz HF(1) 1010 = 500kHz HF(1) 1011 = 1MHz HF 1100 = 2MHz HF 1101 = 4MHz HF 1110 = 8MHz or 32 MHz HF(see Section5.2.2.1 “HFINTOSC”) 1111 = 16MHz HF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Note 1: Duplicate frequency derived from HFINTOSC.  2010-2015 Microchip Technology Inc. DS40001413E-page 65

PIC12(L)F1822/16(L)F1823 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator is ready 0 = Timer1 oscillator is not ready If T1OSCEN = 0: 1 = Timer1 clock source is always ready bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Time-out Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Word 1 0 = Running from an internal oscillator (FOSC<2:0> = 100) bit 4 HFIOFR: High Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS40001413E-page 66  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = • • • 000001 = 000000 = Oscillator module is running at the factory-calibrated frequency. 111111 = • • • 100000 = Minimum frequency TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 65 OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 66 OSCTUNE — — TUN<5:0> 67 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 173 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Note 1: PIC16(L)F1823 only. TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 46 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Note 1: PIC12F1822/16F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 67

PIC12(L)F1822/16(L)F1823 6.0 REFERENCE CLOCK MODULE 6.3 Conflicts with the CLKR pin The reference clock module provides the ability to send There are two cases when the reference clock output a divided clock to the clock output pin of the device signal cannot be output to the CLKR pin, if: (CLKR) and provide a secondary internal clock source • LP, XT or HS oscillator mode is selected. to the modulator module. This module is available in all • CLKOUT function is enabled. oscillator configurations and allows the user to select a greater range of clock sub-multiples to drive external Even if either of these cases are true, the module can devices in the application. The reference clock module still be enabled and the reference clock signal may be includes the following features: used in conjunction with the modulator module. • System clock is the source 6.3.1 OSCILLATOR MODES • Available in all oscillator configurations If LP, XT or HS oscillator modes are selected, the • Programmable clock divider OSC2/CLKR pin must be used as an oscillator input pin • Output enable to a port pin and the CLKR output cannot be enabled. See • Selectable duty cycle Section5.2 “Clock Source Types” for more informa- • Slew rate control tion on different oscillator modes. The reference clock module is controlled by the CLKRCON 6.3.2 CLKOUT FUNCTION register (Register6-1) and is enabled when setting the CLKREN bit. To output the divided clock signal to the CLKR The CLKOUT function has a higher priority than the port pin, the CLKROE bit must be set. The CLKRDIV<2:0> reference clock module. Therefore, if the CLKOUT function is enabled by the CLKOUTEN bit in Configura- bits enable the selection of eight different clock divider options. The CLKRDC<1:0> bits can be used to modify the duty cycle tion Word 1, FOSC/4 will always be output on the port of the output clock(1). The CLKRSLR bit controls slew rate pin. Reference Section4.0 “Device Configuration” limiting. for more information. Note1: If the base clock rate is selected without 6.4 Operation During Sleep a divider, the output clock will always have a duty cycle equal to that of the As the reference clock module relies on the system source clock, unless a 0% duty cycle is clock as its source, and the system clock is disabled in selected. If the clock divider is set to base Sleep, the module does not function in Sleep, even if clock/2, then 25% and 75% duty cycle an external clock source or the Timer1 clock source is accuracy will be dependent upon the configured as the system clock. The module outputs source clock. will remain in their current state until the device exits Sleep. For information on using the reference clock output with the modulator module, see Section23.0 “Data Signal Modulator”. 6.1 Slew Rate The slew rate limitation on the output port pin can be disabled. The Slew Rate limitation can be removed by clearing the CLKRSLR bit in the CLKRCON register. 6.2 Effects of a Reset Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. DS40001413E-page 68  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 = Reference clock module is enabled 0 = Reference clock module is disabled bit 6 CLKROE: Reference Clock Output Enable bit(3) 1 = Reference clock output is enabled on CLKR pin 0 = Reference clock output disabled on CLKR pin bit 5 CLKRSLR: Reference Clock Slew Rate Control limiting enable bit 1 = Slew rate limiting is enabled 0 = Slew rate limiting is disabled bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits 11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0% bit 2-0 CLKRDIV<2:0> Reference Clock Divider bits 111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2(1) 000 = Base clock value(2) Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle. 2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0% is selected. 3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration Word 1 = 0 will result in FOSC/4. See Section6.3 “Conflicts with the CLKR pin” for details.  2010-2015 Microchip Technology Inc. DS40001413E-page 69

PIC12(L)F1822/16(L)F1823 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CLKRCON CLKREN CLKROE CLKRSLR CLKRDC1 CLKRDC0 CLKRDIV2 CLKRDIV1 CLKRDIV0 69 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. TABLE 6-2: SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD CONFIG1 46 7:0 CP MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. DS40001413E-page 70  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 7.0 RESETS There are multiple ways to reset this device: • Power-on Reset (POR) • Brown-out Reset (BOR) • MCLR Reset • WDT Reset • RESET instruction • Stack Overflow • Stack Underflow • Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure7-1. FIGURE 7-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Stack Overflow/Underflow Reset Pointer External Reset MCLRE MCLR Sleep WDT Time-out Device Power-on Reset Reset VDD Brown-out Reset BOR Enable PWRT Zero 64 ms LFINTOSC PWRTEN  2010-2015 Microchip Technology Inc. DS40001413E-page 71

PIC12(L)F1822/16(L)F1823 7.1 Power-on Reset (POR) 7.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when VDD reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for performance may require greater than minimum VDD. execution protection can be implemented. The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in Configu- conditions have been met. ration Word 1. The four operating modes are: 7.1.1 POWER-UP TIMER (PWRT) • BOR is always on • BOR is off when in Sleep The Power-up Timer provides a nominal 64ms time- out on POR or Brown-out Reset. • BOR is controlled by software • BOR is always off The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to Refer to Table7-1 for more information. rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by enabled by clearing the PWRTE bit in Configuration configuring the BORV bit in Configuration Word 2. Word 1. A VDD noise rejection filter prevents the BOR from The Power-up Timer starts after the release of the POR triggering on small events. If VDD falls below VBOR for and BOR. a duration greater than parameter TBORDC, the device For additional information, refer to Application Note will reset. See Figure7-3 for more information. AN607, “Power-up Trouble Shooting” (DS00607). TABLE 7-1: BOR OPERATING MODES Device Device BOREN Operation upon SBOREN Device Mode BOR Mode Operation upon Config bits wake- up from release of POR Sleep BOR_ON(11) X X Active Waits for BOR ready(1) BOR_NSLEEP (10) X Awake Active Waits for BOR ready BOR_NSLEEP (10) X Sleep Disabled BOR_SBOREN (01) 1 X Active Begins immediately BOR_SBOREN (01) 0 X Disabled Begins immediately BOR_OFF (00) X X Disabled Begins immediately Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. 7.2.1 BOR IS ALWAYS ON 7.2.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Word 1 are set When the BOREN bits of Configuration Word 1 are set to ‘11’, the BOR is always on. The device start-up will to ‘10’, the BOR is on, except in Sleep. The device be delayed until the BOR is ready and VDD is higher start-up will be delayed until the BOR is ready and VDD than the BOR threshold. is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does BOR protection is not active during Sleep. The device not delay wake-up from Sleep. wake-up will be delayed until the BOR is ready. DS40001413E-page 72  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 7.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Word 1 are set to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep. FIGURE 7-2: BROWN-OUT READY SBOREN TBORRDY BORRDY BOR Protection Active FIGURE 7-3: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal < TPWRT Reset TPWRT(1) VDD VBOR Internal Reset TPWRT(1) Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.  2010-2015 Microchip Technology Inc. DS40001413E-page 73

PIC12(L)F1822/16(L)F1823 REGISTER 7-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN — — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Word 1  01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Word 1 = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive DS40001413E-page 74  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 7.3 MCLR 7.8 Power-Up Timer The MCLR is an optional external input that can reset The Power-up Timer optionally delays device execution the device. The MCLR function is controlled by the after a BOR or POR event. This timer is typically used to MCLRE bit of Configuration Word 1 and the LVP bit of allow VDD to stabilize before allowing the device to start Configuration Word 2 (Table7-2). running. The Power-up Timer is controlled by the PWRTE bit of TABLE 7-2: MCLR CONFIGURATION Configuration Word 1. MCLRE LVP MCLR 7.9 Start-up Sequence 0 0 Disabled Upon the release of a POR or BOR, the following must 1 0 Enabled occur before the device will begin executing: x 1 Enabled 1. Power-up Timer runs to completion (if enabled). 7.3.1 MCLR ENABLED 2. Oscillator start-up timer runs to completion (if required for oscillator source). When MCLR is enabled and the pin is held low, the 3. MCLR must be released (if enabled). device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The total time-out will vary based on oscillator configu- ration and Power-up Timer configuration. See The device has a noise filter in the MCLR Reset path. Section5.0 “Oscillator Module (With Fail-Safe The filter will detect and ignore small pulses. Clock Monitor)” for more information. Note: A Reset does not drive the MCLR pin low. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long 7.3.2 MCLR DISABLED enough, the Power-up Timer and oscillator start-up When MCLR is disabled, the pin functions as a general timer will expire. Upon bringing MCLR high, the device purpose input and the internal weak pull-up is under will begin execution immediately (see Figure7-4). This software control. See Section12.2 “PORTA Registers” is useful for testing purposes or to synchronize more for more information. than one device operating in parallel. 7.4 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section10.0 “Watchdog Timer” for more information. 7.5 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Table7-4 for default conditions after a RESET instruction has occurred. 7.6 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Word2. See Section3.4.2 “Overflow/Underflow Reset” for more information. 7.7 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred.  2010-2015 Microchip Technology Inc. DS40001413E-page 75

PIC12(L)F1822/16(L)F1823 FIGURE 7-4: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC DS40001413E-page 76  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 7.10 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table7-3 and Table7-4 show the Reset condi- tions of these registers. TABLE 7-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RMCLR RI POR BOR TO PD Condition 0 0 1 1 0 x 1 1 Power-on Reset 0 0 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 0 x x 0 Illegal, PD is set on POR 0 0 1 1 u 0 1 1 Brown-out Reset u u u u u u 0 u WDT Reset u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u 1 0 Interrupt Wake-up from Sleep u u 0 u u u u u MCLR Reset during normal operation u u 0 u u u 1 0 MCLR Reset during Sleep u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 7-4: RESET CONDITION FOR SPECIAL REGISTERS(2) Program STATUS PCON Condition Counter Register Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-- uuuu RESET Instruction Executed 0000h ---u uuuu uu-- u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as ‘0’.  2010-2015 Microchip Technology Inc. DS40001413E-page 77

PIC12(L)F1822/16(L)F1823 7.11 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Reset Instruction Reset (RI) • Stack Overflow Reset (STKOVF) • Stack Underflow Reset (STKUNF) • MCLR Reset (RMCLR) The PCON register bits are shown in Register7-2. REGISTER 7-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u STKOVF STKUNF — — RMCLR RI POR BOR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or set to ‘0’ by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or set to ‘0’ by firmware bit 5-4 Unimplemented: Read as ‘0’ bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) DS40001413E-page 78  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BORCON SBOREN — — — — — — BORRDY 74 PCON STKOVF STKUNF — — RMCLR RI POR BOR 78 STATUS — — — TO PD Z DC C 20 WDTCON — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN 97 Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.  2010-2015 Microchip Technology Inc. DS40001413E-page 79

PIC12(L)F1822/16(L)F1823 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • Operation • Interrupt Latency • Interrupts During Sleep • INT Pin • Automatic Context Saving Many peripherals produce Interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure8-1 and Figure8-2. FIGURE 8-1: INTERRUPT LOGIC Wake-up (If in Sleep mode) TMR0IF TMR0IE INTF Interrupt to CPU INTE IOCIF IOCIE From Peripheral Interrupt Logic (Figure8-2) PEIE GIE DS40001413E-page 80  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 8-2: PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF To Interrupt Logic TMR1IE (Figure8-1) TMR2IF TMR2IE EEIF EEIE OSFIF OSFIE C1IF C1IE C2IF(1) C2IE(1) BCLIF BCLIE Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 81

PIC12(L)F1822/16(L)F1823 8.1 Operation 8.2 Interrupt Latency Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the are enabled by setting the following bits: interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous • GIE bit of the INTCON register interrupts is three or four instruction cycles. For • Interrupt Enable bit(s) for the specific interrupt asynchronous interrupts, the latency is three to five event(s) instruction cycles, depending on when the interrupt • PEIE bit of the INTCON register (if the Interrupt occurs. See Figure8-3 and Figure8.3 for more details. Enable bit of the interrupt event is contained in the PIE1 or PIE2 registers) The INTCON, PIR1 and PIR2 registers record individ- ual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See “Section8.5 “Automatic Context Saving”.”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. DS40001413E-page 82  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 8-3: INTERRUPT LATENCY OSC1 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC PC-1 PC PC+1 0004h 0005h Execute 1 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC+1/FSR New PC/ PC PC-1 PC 0004h 0005h ADDR PC+1 Execute 2 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h)  2010-2015 Microchip Technology Inc. DS40001413E-page 83

PIC12(L)F1822/16(L)F1823 FIGURE 8-4: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 (3) CLKOUT (4) INT pin (1) (1) (2) INTF (5) Interrupt Latency GIE INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section30.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS40001413E-page 84  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section9.0 “Power- Down Mode (Sleep)” for more details. 8.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 8.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • W register • STATUS register (except for TO and PD) • BSR register • FSR registers • PCLATH register Upon exiting the Interrupt Service Routine, these regis- ters are automatically restored. Any modifications to these registers during the ISR will be lost. If modifica- tions to any of these registers are desired, the corre- sponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved.  2010-2015 Microchip Technology Inc. DS40001413E-page 85

PIC12(L)F1822/16(L)F1823 8.5.1 INTCON REGISTER Note: Interrupt flag bits are set when an interrupt The INTCON register is a readable and writable condition occurs, regardless of the state of register, which contains the various enable and flag bits its corresponding enable bit or the Global for TMR0 register overflow, interrupt-on-change and Enable bit, GIE, of the INTCON register. external INT pin interrupts. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register have been cleared by software. DS40001413E-page 86  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 8.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register8-2. set to enable any peripheral interrupt. REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 Gate Acquisition interrupt 0 = Disables the Timer1 Gate Acquisition interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt  2010-2015 Microchip Technology Inc. DS40001413E-page 87

PIC12(L)F1822/16(L)F1823 8.5.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register8-3. set to enable any peripheral interrupt. REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 OSFIE C2IE(1) C1IE EEIE BCLIE — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit(1) 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit 1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2-0 Unimplemented: Read as ‘0’ Note 1: PIC16(L)F1823 only. DS40001413E-page 88  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 8.5.4 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register8-4. condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending  2010-2015 Microchip Technology Inc. DS40001413E-page 89

PIC12(L)F1822/16(L)F1823 8.5.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register8-5. condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 OSFIF C2IF(1) C1IF EEIF BCLIF — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 C2IF: Comparator C2 Interrupt Flag(1) 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 C1IF: Comparator C1 Interrupt Flag 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2-0 Unimplemented: Read as ‘0’ Note 1: PIC16(L)F1823 only. DS40001413E-page 90  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 164 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts. Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 91

PIC12(L)F1822/16(L)F1823 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-Down mode is entered by executing a The device can wake-up from Sleep through one of the SLEEP instruction. following events: Upon entering Sleep mode, the following conditions 1. External Reset input on MCLR pin, if enabled exist: 2. BOR Reset, if enabled 1. WDT will be cleared but keeps running, if 3. POR Reset enabled for operation during Sleep. 4. Watchdog Timer, if enabled 2. PD bit of the STATUS register is cleared. 5. Any external interrupt 3. TO bit of the STATUS register is set. 6. Interrupts by peripherals capable of running 4. CPU clock is disabled. during Sleep (see individual peripheral for more 5. 31 kHz LFINTOSC is unaffected and peripherals information) that operate from it may continue operation in The first three events will cause a device Reset. The Sleep. last three events are considered a continuation of pro- 6. Timer1 oscillator is unaffected and peripherals gram execution. To determine whether a device Reset that operate from it may continue operation in or wake-up event occurred, refer to Section7.10 Sleep. “Determining the Cause of a Reset”. 7. ADC is unaffected, if the dedicated FRC clock is When the SLEEP instruction is being executed, the next selected. instruction (PC + 1) is prefetched. For the device to 8. Capacitive Sensing oscillator is unaffected. wake-up through an interrupt event, the corresponding 9. I/O ports maintain the status they had before interrupt enable bit must be enabled. Wake-up will SLEEP was executed (driving high, low or high- occur regardless of the state of the GIE bit. If the GIE impedance). bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is 10. Resets other than WDT are not affected by enabled, the device executes the instruction after the Sleep mode. SLEEP instruction, the device will call the Interrupt Ser- Refer to individual chapters for more details on vice Routine. In cases where the execution of the peripheral operation during Sleep. instruction following SLEEP is not desirable, the user To minimize current consumption, the following condi- should have a NOP after the SLEEP instruction. tions should be considered: The WDT is cleared when the device wakes up from • I/O pins should not be floating Sleep, regardless of the source of wake-up. • External circuitry sinking current from I/O pins • Internal circuitry sourcing current from I/O pins • Current draw from pins with internal weak pull-ups • Modules using 31 kHz LFINTOSC • Modules using Timer1 oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section17.0 “Digital-to-Analog Converter (DAC) Module” and Section14.0 “Fixed Voltage Reference (FVR)” for more information on these modules. DS40001413E-page 92  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 9.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the execu- tion of a SLEEP instruction When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit - SLEEP instruction will be completely and interrupt flag bit set, one of the following will occur: executed - Device will immediately wake-up from Sleep • If the interrupt occurs before the execution of a SLEEP instruction - WDT and WDT prescaler will be cleared - SLEEP instruction will execute as a NOP. - TO bit of the STATUS register will be set - WDT and WDT prescaler will not be cleared - PD bit of the STATUS register will be cleared. - TO bit of the STATUS register will not be set Even if the flag bits were checked before executing a - PD bit of the STATUS register will not be SLEEP instruction, it may be possible for flag bits to cleared. become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) CLKOUT(2) TOST(3) Interrupt flag Interrupt Latency(4) GIE bit Processor in (INTCON reg.) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC - 1) Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. 3: TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes. 4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.  2010-2015 Microchip Technology Inc. DS40001413E-page 93

PIC12(L)F1822/16(L)F1823 TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 125 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 125 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 125 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 STATUS — — — TO PD Z DC C 20 WDTCON — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN 97 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode. Note 1: PIC16(L)F1823 only. DS40001413E-page 94  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 10.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0>=01 SWDTEN 23-bit Programmable WDTE<1:0>=11 LFINTOSC WDT Time-out Prescaler WDT WDTE<1:0>=10 Sleep WDTPS<4:0>  2010-2015 Microchip Technology Inc. DS40001413E-page 95

PIC12(L)F1822/16(L)F1823 10.1 Independent Clock Source 10.3 Time-Out Period The WDT derives its time base from the 31kHz The WDTPS bits of the WDTCON register set the LFINTOSC internal oscillator. time-out period from 1ms to 256 seconds. After a Reset, the default time-out period is two seconds. 10.2 WDT Operating Modes 10.4 Clearing the WDT The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration The WDT is cleared when any of the following condi- Word 1. See Table10-1. tions occur: • Any Reset 10.2.1 WDT IS ALWAYS ON • CLRWDT instruction is executed When the WDTE bits of Configuration Word 1 are set to • Device enters Sleep ‘11’, the WDT is always on. • Device wakes up from Sleep WDT protection is active during Sleep. • Oscillator fail event 10.2.2 WDT IS OFF IN SLEEP • WDT is disabled • OST is running When the WDTE bits of Configuration Word 1 are set to ‘10’, the WDT is on, except in Sleep. See Table10-2 for more information. WDT protection is not active during Sleep. 10.5 Operation During Sleep 10.2.3 WDT CONTROLLED BY SOFTWARE When the device enters Sleep, the WDT is cleared. If When the WDTE bits of Configuration Word 1 are set to the WDT is enabled during Sleep, the WDT resumes ‘01’, the WDT is controlled by the SWDTEN bit of the counting. WDTCON register. When the device exits Sleep, the WDT is cleared WDT protection is unchanged by Sleep. See again. The WDT remains clear until the OST, if Table10-1 for more details. enabled, completes. See Section5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for more TABLE 10-1: WDT OPERATING MODES information on the OST. When a WDT time-out occurs while the device is in WDTE Device WDT SWDTEN Sleep, no Reset is generated. Instead, the device Config bits Mode Mode wakes up and resumes operation. The TO and PD bits WDT_ON(11) X X Active in the STATUS register are changed to indicate the event. See Section3.0 “Memory Organization” and WDT_NSLEEP (10) X Awake Active The STATUS register (Register3-1) for more WDT_NSLEEP (10) X Sleep Disabled information. WDT_SWDTEN (01) 1 X Active WDT_SWDTEN (01) 0 X Disabled WDT_OFF (00) X X Disabled TABLE 10-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0>=00 WDTE<1:0>=01 and SWDTEN = 0 WDTE<1:0>=10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) Unaffected DS40001413E-page 96  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 — — WDTPS<4:0> SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 00000 = 1:32 (Interval 1ms typ) 00001 = 1:64 (Interval 2ms typ) 00010 = 1:128 (Interval 4ms typ) 00011 = 1:256 (Interval 8ms typ) 00100 = 1:512 (Interval 16ms typ) 00101 = 1:1024 (Interval 32ms typ) 00110 = 1:2048 (Interval 64ms typ) 00111 = 1:4096 (Interval 128ms typ) 01000 = 1:8192 (Interval 256ms typ) 01001 = 1:16384 (Interval 512ms typ) 01010 = 1:32768 (Interval 1s typ) 01011 = 1:65536 (Interval 2s typ) (Reset value) 01100 = 1:131072 (217) (Interval 4s typ) 01101 = 1:262144 (218) (Interval 8s typ) 01110 = 1:524288 (219) (Interval 16s typ) 01111 = 1:1048576 (220) (Interval 32s typ) 10000 = 1:2097152 (221) (Interval 64s typ) 10001 = 1:4194304 (222) (Interval 128s typ) 10010 = 1:8388608 (223) (Interval 256s typ) 10011 = Reserved. Results in minimum interval (1:32) • • • 11111 = Reserved. Results in minimum interval (1:32) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored.  2010-2015 Microchip Technology Inc. DS40001413E-page 97

PIC12(L)F1822/16(L)F1823 11.0 DATA EEPROM AND FLASH 11.1 EEADRL and EEADRH Registers PROGRAM MEMORY The EEADRH:EEADRL register pair can address up to CONTROL a maximum of 256bytes of data EEPROM or up to a maximum of 32K words of program memory. The data EEPROM and Flash program memory are readable and writable during normal operation (full VDD When selecting a program address value, the MSB of range). These memories are not directly mapped in the the address is written to the EEADRH register and the register file space. Instead, they are indirectly LSB is written to the EEADRL register. When selecting addressed through the Special Function Registers a EEPROM address value, only the LSB of the address (SFRs). There are six SFRs used to access these is written to the EEADRL register. memories: 11.1.1 EECON1 AND EECON2 REGISTERS • EECON1 EECON1 is the control register for EE memory • EECON2 accesses. • EEDATL Control bit EEPGD determines if the access will be a • EEDATH program or data memory access. When clear, any • EEADRL subsequent operations will operate on the EEPROM • EEADRH memory. When set, any subsequent operations will When interfacing the data memory block, EEDATL operate on the program memory. On Reset, EEPROM is holds the 8-bit data for read/write, and EEADRL holds selected by default. the address of the EEDATL location being accessed. Control bits RD and WR initiate read and write, These devices have 256 bytes of data EEPROM with respectively. These bits cannot be cleared, only set, in an address range from 0h to 0FFh. software. They are cleared in hardware at completion When accessing the program memory block, the of the read or write operation. The inability to clear the EEDATH:EEDATL register pair forms a 2-byte word WR bit in software prevents the accidental, premature that holds the 14-bit data for read/write, and the termination of a write operation. EEADRL and EEADRH registers form a 2-byte word The WREN bit, when set, will allow a write operation to that holds the 15-bit address of the program memory occur. On power-up, the WREN bit is clear. The location being read. WRERR bit is set when a write operation is interrupted The EEPROM data memory allows byte read and write. by a Reset during normal operation. In these situations, An EEPROM byte write automatically erases the loca- following Reset, the user can check the WRERR bit tion and writes the new data (erase before write). and execute the appropriate error handling routine. The write time is controlled by an on-chip timer. The Interrupt flag bit EEIF of the PIR2 register is set when write/erase voltages are generated by an on-chip write is complete. It must be cleared in the software. charge pump rated to operate over the voltage range of Reading EECON2 will read all ‘0’s. The EECON2 reg- the device for byte or word operations. ister is used exclusively in the data EEPROM write Depending on the setting of the Flash Program sequence. To enable writes, a specific pattern must be Memory Self Write Enable bits WRT<1:0> of the written to EECON2. Configuration Word 2, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are always allowed. When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. DS40001413E-page 98  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 11.2 Using the Data EEPROM 11.2.2 WRITING TO THE DATA EEPROM MEMORY The data EEPROM is a high-endurance, byte address- able array that has been optimized for the storage of To write an EEPROM data location, the user must first frequently changing information (e.g., program vari- write the address to the EEADRL register and the data ables or other data that are updated often). When vari- to the EEDATL register. Then the user must follow a ables in one section change frequently, while variables specific sequence to initiate the write for each byte. in another section do not change, it is possible to The write will not initiate if the above sequence is not exceed the total number of write cycles to the followed exactly (write 55h to EECON2, write AAh to EEPROM without exceeding the total number of write EECON2, then set WR bit) for each byte. Interrupts cycles to a single byte. Refer to Section30.0 “Electri- should be disabled during this codesegment. cal Specifications”. If this is the case, then a refresh Additionally, the WREN bit in EECON1 must be set to of the array must be performed. For this reason, vari- enable write. This mechanism prevents accidental ables that change infrequently (such as constants, IDs, writes to data EEPROM due to errant (unexpected) calibration, etc.) should be stored in Flash program code execution (i.e., lost programs). The user should memory. keep the WREN bit clear at all times, except when 11.2.1 READING THE DATA EEPROM updating EEPROM. The WREN bit is not cleared byhardware. MEMORY After a write sequence has been initiated, clearing the To read a data memory location, the user must write the WREN bit will not affect this write cycle. The WR bit will address to the EEADRL register, clear the EEPGD and be inhibited from being set unless the WREN bit is set. CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next At the completion of the write cycle, the WR bit is cycle, in the EEDATL register; therefore, it can be read cleared in hardware and the EE Write Complete in the next instruction. EEDATL will hold this value until Interrupt Flag bit (EEIF) is set. The user can either another read or until it is written to by the user (during enable this interrupt or poll this bit. EEIF must be a write operation). cleared by software. 11.2.3 PROTECTION AGAINST SPURIOUS EXAMPLE 11-1: DATA EEPROM READ WRITE BANKSELEEADRL ; MOVLW DATA_EE_ADDR ; There are conditions when the user may not want to MOVWF EEADRL ;Data Memory write to the data EEPROM memory. To protect against ;Address to read spurious EEPROM writes, various mechanisms have BCF EECON1, CFGS ;Deselect Config space been built-in. On power-up, WREN is cleared. Also, the BCF EECON1, EEPGD;Point to DATA memory Power-up Timer (64ms duration) prevents EEPROM BSF EECON1, RD ;EE Read write. MOVF EEDATL, W ;W = EEDATL The write initiate sequence and the WREN bit together help prevent an accidental write during: • Brown-out Note: Data EEPROM can be read regardless of • Power Glitch the setting of the CPD bit. • Software Malfunction 11.2.4 DATA EEPROM OPERATION DURING CODE-PROTECT Data memory can be code-protected by programming the CPD bit in the Configuration Word 1 (Register5-1) to ‘0’. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM.  2010-2015 Microchip Technology Inc. DS40001413E-page 99

PIC12(L)F1822/16(L)F1823 EXAMPLE 11-2: DATA EEPROM WRITE BANKSEL EEADRL ; MOVLW DATA_EE_ADDR ; MOVWF EEADRL ;Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATL ;Data Memory Value to write BCF EECON1, CFGS ;Deselect Configuration space BCF EECON1, EEPGD ;Point to DATA memory BSF EECON1, WREN ;Enable writes BCF INTCON, GIE ;Disable INTs. MOVLW 55h ; RequiredSequence MMMBOOOSVVVFWLWFWF E0EEEAEECACCOhOONNN221, WR ;;;;WWSerriit ttWeeR 5Ab5Aihht to begin write BSF INTCON, GIE ;Enable Interrupts BCF EECON1, WREN ;Disable writes BTFSC EECON1, WR ;Wait for write to complete GOTO $-2 ;Done FIGURE 11-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR PC PC + 1 EEADRH,EEADRL PPCC ++ 33 PC + 4 PC + 5 Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4) INSTR(PC - 1) BSF EECON1,RD INSTR(PC + 1) Forced NOP INSTR(PC + 3) INSTR(PC + 4) executed here executed here executed here executed here executed here executed here RD bit EEDATH EEDATL Register EERHLT DS40001413E-page 100  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 11.3 Flash Program Memory Overview 11.3.1 READING THE FLASH PROGRAM MEMORY It is important to understand the Flash program mem- ory structure for erase and programming operations. To read a program memory location, the user must: Flash Program memory is arranged in rows. A row con- 1. Write the Least and Most Significant address sists of a fixed number of 14-bit program memory bits to the EEADRH:EEADRL register pair. words. A row is the minimum block size that can be 2. Clear the CFGS bit of the EECON1 register. erased by user software. 3. Set the EEPGD control bit of the EECON1 Flash program memory may only be written or erased register. if the destination address is in a segment of memory 4. Then, set control bit RD of the EECON1 register. that is not write-protected, as defined in bits WRT<1:0> Once the read control bit is set, the program memory of Configuration Word 2. Flash controller will use the second instruction cycle to After a row has been erased, the user can reprogram read the data. This causes the second instruction all or a portion of this row. Data to be written into the immediately following the “BSF EECON1,RD” instruction program memory row is written to 14-bit wide data write to be ignored. The data is available in the very next cycle, latches. These write latches are not directly accessible in the EEDATH:EEDATL register pair; therefore, it can to the user, but may be loaded via sequential writes to be read as two bytes in the following instructions. the EEDATH:EEDATL register pair. EEDATH:EEDATL register pair will hold this value until Note: If the user wants to modify only a portion another read or until it is written to by the user. of a previously programmed row, then the Note1: The two instructions following a program contents of the entire row must be read and saved in RAM prior to the erase. memory read are required to be NOPs. This prevents the user from executing a The number of data write latches may not be equivalent two-cycle instruction on the next to the number of row locations. During programming, instruction after the RD bit is set. user software may need to fill the set of write latches 2: Flash program memory can be read and initiate a programming operation multiple times in regardless of the setting of the CP bit. order to fully reprogram an erased row. For example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times. The size of a program memory row and the number of program memory write latches may vary by device. See Table11-1 for details. TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Erase Block Number of Device (Row) Size/ Write Latches/ Boundary Boundary PIC12(L)F1822 16 words, 16 words, PIC16(L)F1823 EEADRL<3:0> EEADRL<3:0> = 0000 = 0000  2010-2015 Microchip Technology Inc. DS40001413E-page 101

PIC12(L)F1822/16(L)F1823 EXAMPLE 11-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL EEADRL ; Select Bank for EEPROM registers MOVLW PROG_ADDR_LO ; MOVWF EEADRL ; Store LSB of address MOVLW PROG_ADDR_HI ; MOVWL EEADRH ; Store MSB of address BCF EECON1,CFGS ; Do not select Configuration Space BSF EECON1,EEPGD ; Select Program Memory BCF INTCON,GIE ; Disable interrupts BSF EECON1,RD ; Initiate read NOP ; Executed (Figure 11-1) NOP ; Ignored (Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS40001413E-page 102  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 11.3.2 ERASING FLASH PROGRAM The following steps should be completed to load the MEMORY write latches and program a block of program memory. These steps are divided into two parts. First, all write While executing code, program memory can only be latches are loaded with data except for the last program erased by rows. To erase a row: memory location. Then, the last write latch is loaded 1. Load the EEADRH:EEADRL register pair with and the programming sequence is initiated. A special the address of new row to be erased. unlock sequence is required to load a write latch with 2. Clear the CFGS bit of the EECON1 register. data or initiate a Flash programming operation. This 3. Set the EEPGD, FREE, and WREN bits of the unlock sequence should not be interrupted. EECON1 register. 1. Set the EEPGD and WREN bits of the EECON1 4. Write 55h, then AAh, to EECON2 (Flash register. programming unlock sequence). 2. Clear the CFGS bit of the EECON1 register. 5. Set control bit WR of the EECON1 register to 3. Set the LWLO bit of the EECON1 register. When begin the erase operation. the LWLO bit of the EECON1 register is ‘1’, the 6. Poll the WR bit in the EECON1 register to deter- write sequence will only load the write latches mine when the row erase has completed. and will not initiate the write to Flash program memory. See Example11-4. 4. Load the EEADRH:EEADRL register pair with After the “BSF EECON1,WR” instruction, the processor the address of the location to be written. requires two cycles to set up the erase operation. The 5. Load the EEDATH:EEDATL register pair with user must place two NOP instructions after the WR bit is the program memory data to be written. set. The processor will halt internal operations for the 6. Write 55h, then AAh, to EECON2, then set the typical 2ms erase time. This is not Sleep mode as the WR bit of the EECON1 register (Flash clocks and peripherals will continue to run. After the programming unlock sequence). The write latch erase cycle, the processor will resume operation with is now loaded. the third instruction after the EECON1 write instruction. 7. Increment the EEADRH:EEADRL register pair 11.3.3 WRITING TO FLASH PROGRAM to point to the next location. MEMORY 8. Repeat steps 5 through 7 until all but the last Program memory is programmed using the following write latch has been loaded. steps: 9. Clear the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is 1. Load the starting address of the word(s) to be ‘0’, the write sequence will initiate the write to programmed. Flash program memory. 2. Load the write latches with data. 10. Load the EEDATH:EEDATL register pair with 3. Initiate a programming operation. the program memory data to be written. 4. Repeat steps 1 through 3 until all data is written. 11. Write 55h, then AAh, to EECON2, then set the Before writing to program memory, the word(s) to be WR bit of the EECON1 register (Flash written must be erased or previously unwritten. Pro- programming unlock sequence). The entire gram memory can only be erased one row at a time. No latch block is now written to Flash program automatic erase occurs upon the initiation of the write. memory. Program memory can be written one or more words at It is not necessary to load the entire write latch block a time. The maximum number of words written at one with user program data. However, the entire write latch time is equal to the number of write latches. See block will be written to program memory. Figure11-2 (block writes to program memory with 16 An example of the complete write sequence for eight write latches) for more details. The write latches are words is shown in Example11-5. The initial address is aligned to the address boundary defined by EEADRL loaded into the EEADRH:EEADRL register pair; the as shown in Table11-1. Write operations do not cross eight words of data are loaded using indirect addressing. these boundaries. At the completion of a program memory write operation, the write latches are reset to contain 0x3FFF.  2010-2015 Microchip Technology Inc. DS40001413E-page 103

PIC12(L)F1822/16(L)F1823 After the “BSF EECON1,WR” instruction, the processor continue to run. The processor does not stall when requires two cycles to set up the write operation. The LWLO = 1, loading the write latches. After the write user must place two NOP instructions after the WR bit is cycle, the processor will resume operation with the third set. The processor will halt internal operations for the instruction after the EECON1 write instruction. typical 2ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will FIGURE 11-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES 7 5 0 7 0 EEDATH EEDATA 6 8 First word of block Last word of block to be written to be written 14 14 14 14 EEADRL<3:0> = 0000 EEADRL<3:0> = 0001 EEADRL<3:0> = 0010 EEADRL<3:0> = 1111 Buffer Register Buffer Register Buffer Register Buffer Register Program Memory DS40001413E-page 104  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL EEADRL MOVF ADDRL,W ; Load lower 8 bits of erase address boundary MOVWF EEADRL MOVF ADDRH,W ; Load upper 6 bits of erase address boundary MOVWF EEADRH BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space BSF EECON1,FREE ; Specify an erase operation BSF EECON1,WREN ; Enable writes MOVLW 55h ; Start of required sequence to initiate erase MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne reer aasree ignored as processor ; halts to begin erase sequence NOP ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts  2010-2015 Microchip Technology Inc. DS40001413E-page 105

PIC12(L)F1822/16(L)F1823 EXAMPLE 11-5: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL ; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F ; BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL EEADRH ; Bank 3 MOVF ADDRH,W ; Load initial address MOVWF EEADRH ; MOVF ADDRL,W ; MOVWF EEADRL ; MOVLW LOW DATA_ADDR ; Load initial data address MOVWF FSR0L ; MOVLW HIGH DATA_ADDR ; Load initial data address MOVWF FSR0H ; BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space BSF EECON1,WREN ; Enable writes BSF EECON1,LWLO ; Only Load Write Latches LOOP MOVIW FSR0++ ; Load first data byte into lower MOVWF EEDATL ; MOVIW FSR0++ ; Load second data byte into upper MOVWF EEDATH ; MOVF EEADRL,W ; Check if lower bits of address are '000' XORLW 0x07 ; Check if we're on the last of 8 addresses ANDLW 0x07 ; BTFSC STATUS,Z ; Exit if last of eight words, GOTO START_WRITE ; MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne rwer iatree ignored as processor ; halts to begin write sequence NOP ; Processor will stop here and wait for write to complete. ; After write processor continues with 3rd instruction. INCF EEADRL,F ; Still loading latches Increment address GOTO LOOP ; Write next latches START_WRITE BCF EECON1,LWLO ; No more loading latches - Actually start Flash program ; memory write MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne rwer iatree ignored as processor ; halts to begin write sequence NOP ; Processor will stop here and wait for write complete. ; after write processor continues with 3rd instruction BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts DS40001413E-page 106  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 11.4 Modifying Flash Program Memory 11.5 User ID, Device ID and Configuration Word Access When modifying existing data in a program memory row, and data within that row must be preserved, it must Instead of accessing program memory or EEPROM first be read and saved in a RAM image. Program data memory, the User ID’s, Device ID/Revision ID and memory is modified using the following steps: Configuration Words can be accessed when CFGS=1 1. Load the starting address of the row to be in the EECON1 register. This is the region that would modified. be pointed to by PC<15>=1, but not all addresses are accessible. Different access may exist for reads and 2. Read the existing data from the row into a RAM writes. Refer to Table11-2. image. 3. Modify the RAM image to contain the new data When read access is initiated on an address outside the to be written into program memory. parameters listed in Table11-2, the EEDATH:EEDATL register pair is cleared. 4. Load the starting address of the row to be rewrit- ten. 5. Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. 8. Repeat steps 6 and 7 as many times as required to reprogram the erased row. TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS=1) Address Function Read Access Write Access 8000h-8003h User IDs Yes Yes 8006h Device ID/Revision ID Yes No 8007h-8008h Configuration Words 1 and 2 Yes No EXAMPLE 11-3: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL EEADRL ; Select correct Bank MOVLW PROG_ADDR_LO ; MOVWF EEADRL ; Store LSB of address CLRF EEADRH ; Clear MSB of address BSF EECON1,CFGS ; Select Configuration Space BCF INTCON,GIE ; Disable interrupts BSF EECON1,RD ; Initiate read NOP ; Executed (See Figure 11-1) NOP ; Ignored (See Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2010-2015 Microchip Technology Inc. DS40001413E-page 107

PIC12(L)F1822/16(L)F1823 11.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example11-6) to the desired value to be written. Example11-6 shows how to verify a write to EEPROM. EXAMPLE 11-6: EEPROM WRITE VERIFY BANKSELEEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL, W ; BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue DS40001413E-page 108  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 11-1: EEDATL: EEPROM DATA REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 11-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — EEDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 EEDAT<13:8>: Read/write value for Most Significant bits of program memory REGISTER 11-3: EEADRL: EEPROM ADDRESS REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address REGISTER 11-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 —(1) EEADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address Note 1: Unimplemented, read as ‘1’.  2010-2015 Microchip Technology Inc. DS40001413E-page 109

PIC12(L)F1822/16(L)F1823 REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Accesses program space Flash memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, User ID and Device ID Registers 0 = Accesses Flash Program or data EEPROM Memory bit 5 LWLO: Load Write Latches Only bit If CFGS=1 (Configuration space) OR CFGS=0 and EEPGD=1 (program Flash): 1 = The next WR command does not initiate a write; only the program memory latches are updated. 0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write of all the data stored in the program memory latches. If CFGS=0 and EEPGD=0: (Accessing data EEPROM) LWLO is ignored. The next WR command initiates a write to the data EEPROM. bit 4 FREE: Program Flash Erase Enable bit If CFGS=1 (Configuration space) OR CFGS=0 and EEPGD=1 (program Flash): 1 = Performs an erase operation on the next WR command (cleared by hardware after comple- tion of erase). 0 = Performs a write operation on the next WR command. If EEPGD=0 and CFGS=0: (Accessing data EEPROM) FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle. bit 3 WRERR: EEPROM Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit). 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash and data EEPROM bit 1 WR: Write Control bit 1 = Initiates a program Flash or data EEPROM program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash or data EEPROM is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash or data EEPROM data read. DS40001413E-page 110  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 11-6: EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. Refer to Section11.2.2 “Writing to the Data EEPROM Memory” for more information. TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 110 EECON2 EEPROM Control Register 2 (not a physical register) 111* EEADRL EEADRL<7:0> 109 EEADRH —(2) EEADRH<6:0> 109 EEDATL EEDATL<7:0> 109 EEDATH — — EEDATH<5:0> 109 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Data EEPROM module. * Page provides register information. Note 1: PIC16(L)F1823 only. 2: Unimplemented. Read as ‘1’.  2010-2015 Microchip Technology Inc. DS40001413E-page 111

PIC12(L)F1822/16(L)F1823 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION Depending on the device selected and peripherals enabled, there are up to two ports available. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Read LATx TRISx Each port has three standard registers for its operation. These registers are: D Q • TRISx registers (data direction) Write LATx • PORTx registers (reads the levels on the pins of Write PORTx CK VDD the device) Data Register • LATx registers (output latch) Some ports may have one or more of the following Data Bus additional registers. These registers are: I/O pin Read PORTx • ANSELx (analog select) • WPUx (weak pull-up) To peripherals VSS • INLVLx (input level control) ANSELx TABLE 12-1: PORT AVAILABILITY PER DEVICE A C T T Device R R O O P P PIC12(L)F1822 ● PIC16(L)F1823 ● ● The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same affect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure12-1. DS40001413E-page 112  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) registers are used to steer specific peripheral input and output functions between different pins. The APFCON registers are shown in Register12-1. For this device family, the following functions can be moved between different pins. • RX/DT • TX/CK • SDO • SS (Slave Select) • T1G • P1B • CCP1/P1A These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.  2010-2015 Microchip Technology Inc. DS40001413E-page 113

PIC12(L)F1822/16(L)F1823 REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(1) CCP1SEL(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RXDTSEL: Pin Selection bit For 8-Pin Devices (PIC12(L)F1822): 0 = RX/DT function is on RA1 1 = RX/DT function is on RA5 For 14-Pin Devices (PIC16(L)F1823): 0 = RX/DT function is on RC5 1 = RX/DT function is on RA1 bit 6 SDOSEL: Pin Selection bit For 8-Pin Devices (PIC12(L)F1822): 0 = SDO function is on RA0 1 = SDO function is on RA4 For 14-Pin Devices (PIC16(L)F1823): 0 = SDO function is on RC2 1 = SDO function is on RA4 bit 5 SSSEL: Pin Selection bit For 8-Pin Devices (PIC12(L)F1822): 0 = SS function is on RA3 1 = SS function is on RA0 For 14-Pin Devices (PIC16(L)F1823): 0 = SS function is on RC3 1 = SS function is on RA3 bit 4 Unimplemented: Read as ‘0’ bit 3 T1GSEL: Pin Selection bit 0 = T1G function is on RA4 1 = T1G function is on RA3 bit 2 TXCKSEL: Pin Selection bit For 8-Pin Devices (PIC12(L)F1822): 0 = TX/CK function is on RA0 1 = TX/CK function is on RA4 For 14-Pin Devices (PIC16(L)F1823): 0 = TX/CK function is on RC4 1 = TX/CK function is on RA0 bit 1 P1BSEL: Pin Selection bit(1) For 8-Pin Devices (PIC12(L)F1822): 0 = P1B function is on RA0 1 = P1B function is on RA4 For 14-Pin Devices (PIC16(L)F1823): P1B function is always on RC4 bit 0 CCP1SEL: Pin Selection bit(1) For 8-Pin Devices (PIC12(L)F1822): 0 = CCP1/P1A function is on RA2 1 = CCP1/P1A function is on RA5 For 14-Pin Devices (PIC16(L)F1823): CCP1/P1A function is always on RC5 Note 1: PIC12(L)F1822 only. DS40001413E-page 114  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 12.2 PORTA Registers PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register12-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as ‘1’. Example12-1 shows how to initialize PORTA. Reading the PORTA register (Register12-2) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). The TRISA register (Register12-3) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. 12.2.1 ANSELA REGISTER The ANSELA register (Register12-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. EXAMPLE 12-1: INITIALIZING PORTA BANKSEL PORTA ; CLRF PORTA ;Init PORTA BANKSEL LATA ;Data Latch CLRF LATA ; BANKSEL ANSELA ; CLRF ANSELA ;digital I/O BANKSEL TRISA ; MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs  2010-2015 Microchip Technology Inc. DS40001413E-page 115

PIC12(L)F1822/16(L)F1823 12.2.2 PORTA FUNCTIONS AND OUTPUT RA3 PRIORITIES No output priorities. Input only pin. Each PORTA pin is multiplexed with other functions. The RA4 pins, their combined functions and their output priorities 1. OSC2 are briefly described here. For additional information, refer to the appropriate section in this data sheet. 2. CLKOUT 3. T1OSO (Timer1 Oscillator) When multiple outputs are enabled, the actual pin 4. CLKR control goes to the peripheral with the lowest number in the following lists. 5. TX/CK (PIC12(L)F1822 only) 6. SDO Analog input functions, such as ADC, comparator and CapSense inputs, are not shown in the priority lists. 7. P1B (PIC12(L)F1822 only) These inputs are active when the I/O pin is set for RA5 Analog mode using the ANSELx registers. Digital 1. OSC1 output functions may control the pin when it is in Analog mode with the priority shown below. 2. T1OSI (Timer1 Oscillator) 3. SRNQ (PIC12(L)F1822 only) RA0 4. RX/DT (PIC12(L)F1822 only) 1. ICSPDAT 5. CCP1/P1A (PIC12(L)F1822 only) 2. ICDDAT 3. DACOUT (DAC) 4. MDOUT (PIC12(L)F1822 only) 5. TX/CK (EUSART) 6. SDO (PIC12(L)F1822 only) 7. P1B (PIC12(L)F1822 only) RA1 1. ICSPCLK 2. ICDCLK 3. SCL (PIC12(L)F1822 only) 4. RX/DT (EUSART) 5. SCK (PIC12(L)F1822 only) RA2 1. SRQ 2. C1OUT (Comparator) 3. SDA (PIC12(L)F1822 only) 4. CCP1/P1A (PIC12(L)F1822 only) DS40001413E-page 116  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 12-2: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-3: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-4 TRISA<5:4>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 3 TRISA3: RA3 Port Tri-State Control bit This bit is always ‘1’ as RA3 is an input only bit 2-0 TRISA<2:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output  2010-2015 Microchip Technology Inc. DS40001413E-page 117

PIC12(L)F1822/16(L)F1823 REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemented: Read as ‘0 bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — — ANSA4 — ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 3 Unimplemented: Read as ‘0’ bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS40001413E-page 118  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 12-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(1, 2) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(1) CCP1SEL(1) 114 LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 118 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 164 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 117 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 119 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: PIC12F1822 only. TABLE 12-3: SUMMARY OF CONFIGURATION WORD WITH PORTA Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 46 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.  2010-2015 Microchip Technology Inc. DS40001413E-page 119

PIC12(L)F1822/16(L)F1823 12.3 PORTC Registers 12.3.2 PORTC FUNCTIONS AND OUTPUT (PIC16(L)F1823 only) PRIORITIES Each PORTC pin is multiplexed with other functions. The PORTC is a 6-bit wide, bidirectional port. The pins, their combined functions and their output priorities corresponding data direction register is TRISC are briefly described here. For additional information, (Register12-8). Setting a TRISC bit (= 1) will make the refer to the appropriate section in this data sheet. corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). When multiple outputs are enabled, the actual pin Clearing a TRISC bit (= 0) will make the corresponding control goes to the peripheral with the lowest number in PORTC pin an output (i.e., enable the output driver and the following lists. put the contents of the output latch on the selected pin). Analog input and some digital input functions are not Example12-2 shows how to initialize PORTC. included in the list below. These input functions can remain active when the pin is configured as an output. Reading the PORTC register (Register12-7) reads the Certain digital input functions override other port status of the pins, whereas writing to it will write to the functions and are included in the priority list. PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the RC0 port pins are read, this value is modified and then written 1. SCL (MSSP) to the PORT data latch (LATC). 2. SCK (MSSP) The TRISC register (Register12-8) controls the PORTC RC1 pin output drivers, even when they are being used as 1. SDA (MSSP) analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as RC2 analog inputs. I/O pins configured as analog input always 1. SDO (MSSP) read ‘0’. 2. P1D 12.3.1 ANSELC REGISTER RC3 The ANSELC register (Register12-10) is used to 1. P1C configure the Input mode of an I/O pin to analog. RC4 Setting the appropriate ANSELC bit high will cause all 1. MDOUT digital reads on the pin to be read as ‘0’ and allow 2. SRNQ analog functions on the pin to operate correctly. 3. C2OUT The state of the ANSELC bits has no affect on digital out- 4. TX/CK put functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be 5. P1B analog. This can cause unexpected behavior when RC5 executing read-modify-write instructions on the affected 1. RX/DT port. 2. CCP1/P1A Note: The ANSELC register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. EXAMPLE 12-2: INITIALIZING PORTC BANKSEL PORTC ; CLRF PORTC ;Init PORTC BANKSEL LATC ;Data Latch CLRF LATC ; BANKSEL ANSELC CLRF ANSELC ;Make RC<5:0> digital BANKSEL TRISB ; MOVLW B’00110000’;Set RC<5:4> as inputs ;and RC<3:0> as outputs MOVWF TRISC ; DS40001413E-page 120  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 12-7: PORTC: PORTC REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RC<5:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 12-8: TRISC: PORTC TRI-STATE REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISC<5:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output REGISTER 12-9: LATC: PORTC DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LATC<5:0>: PORTC Output Latch Value bits(1) Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values.  2010-2015 Microchip Technology Inc. DS40001413E-page 121

PIC12(L)F1822/16(L)F1823 REGISTER 12-10: ANSELC: PORTC ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — — — ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 12-11: WPUC: WEAK PULL-UP PORTC REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUC<5:0>: Weak Pull-up Register bits(1, 2) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC(1) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELC — — — — ANSC3 ANSC2 ANSC1 ANSC0 122 LATC — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 121 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 164 PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 121 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 WPUC — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 122 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Note 1: PIC16(L)F1823 only. DS40001413E-page 122  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 13.0 INTERRUPT-ON-CHANGE 13.3 Interrupt Flags The PORTA pins can be configured to operate as The IOCAFx bits located in the IOCAF register are Interrupt-On-Change (IOC) pins. An interrupt can be status flags that correspond to the Interrupt-on-change generated by detecting a signal that has either a rising pins of PORTA. If an expected edge is detected on an edge or a falling edge. Any individual PORTA pin, or appropriately enabled pin, then the status flag for that pin combination of PORTA pins, can be configured to will be set, and an interrupt will be generated if the IOCIE generate an interrupt. The interrupt-on-change module bit is set. The IOCIF bit of the INTCON register reflects has the following features: the status of all IOCAFx bits. • Interrupt-on-Change enable (Master Switch) 13.4 Clearing Interrupt Flags • Individual pin configuration • Rising and falling edge detection The individual status flags, (IOCAFx bits), can be • Individual pin interrupt flags cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated Figure13-1 is a block diagram of the IOC module. status flag will be set at the end of the sequence, regardless of the value actually being written. 13.1 Enabling the Module In order to ensure that no detected edge is lost while To allow individual PORTA pins to generate an interrupt, clearing flags, only AND operations masking out known the IOCIE bit of the INTCON register must be set. If the changed bits should be performed. The following IOCIE bit is disabled, the edge detection on the pin will sequence is an example of what should be performed. still occur, but an interrupt will not be generated. EXAMPLE 13-1: CLEARING 13.2 Individual Pin Configuration INTERRUPT FLAGS (PORTA EXAMPLE) For each PORTA pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a MOVLW 0xff rising edge, the associated IOCAPx bit of the IOCAP XORWF IOCAF, W register is set. To enable a pin to detect a falling edge, ANDWF IOCAF, F the associated IOCANx bit of the IOCAN register is set. A pin can be configured to detect rising and falling 13.5 Operation in Sleep edges simultaneously by setting both the IOCAPx bit and the IOCANx bit of the IOCAP and IOCAN registers, The interrupt-on-change interrupt sequence will wake respectively. the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCAF register will be updated prior to the first instruction executed out of Sleep.  2010-2015 Microchip Technology Inc. DS40001413E-page 123

PIC12(L)F1822/16(L)F1823 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q Q4Q1 CK edge detect R RBx data bus = S to data bus IOCBPx D Q 0 or 1 D Q IOCBFx CK write IOCBFx CK IOCIE R Q2 from all other IOCBFx individual IOC interrupt pin detectors to CPU core Q1 Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q3 Q4 Q4 Q4 Q4 Q4Q1 Q4Q1 Q4Q1 Q4Q1 DS40001413E-page 124  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCAPx=1 and a rising edge was detected on RAx, or when IOCANx=1 and a falling edge was detected on RAx. 0 = No change was detected, or the user cleared the detected change.  2010-2015 Microchip Technology Inc. DS40001413E-page 125

PIC12(L)F1822/16(L)F1823 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 125 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 125 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 125 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. DS40001413E-page 126  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 14.0 FIXED VOLTAGE REFERENCE 14.1 Independent Gain Amplifiers (FVR) The output of the FVR supplied to the ADC, Comparators, DAC and CPS module is routed through The Fixed Voltage Reference, or FVR, is a stable two independent programmable gain amplifiers. Each voltage reference, independent of VDD, with 1.024V, amplifier can be configured to amplify the reference 2.048V or 4.096V selectable output levels. The output voltage by 1x, 2x or 4x, to produce the three possible of the FVR can be configured to supply a reference voltage levels. voltage to the following: The ADFVR<1:0> bits of the FVRCON register are • ADC input channel used to enable and configure the gain amplifier settings • ADC positive reference for the reference supplied to the ADC module. Refer- • Comparator positive input ence Section16.0 “Analog-to-Digital Converter • Digital-to-Analog Converter (DAC) (ADC) Module” for additional information. • Capacitive Sensing (CPS) module The CDAFVR<1:0> bits of the FVRCON register are The FVR can be enabled by setting the FVREN bit of used to enable and configure the gain amplifier settings the FVRCON register. for the reference supplied to Comparators, DAC and CPS module. Reference Section17.0 “Digital-to- Analog Converter (DAC) Module”, Section19.0 “Comparator Module” and Section27.0 “Capacitive Sensing (CPS) Module” for additional information. 14.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section30.0 “Electrical Specifications” for the minimum delay requirement. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 X1 X2 FVR BUFFER1 X4 (To ADC Module) CDAFVR<1:0> 2 X1 X2 FVR BUFFER2 X4 (To Comparators, DAC, CPS) + FVREN 1.024V Fixed FVRRDY _ Reference  2010-2015 Microchip Technology Inc. DS40001413E-page 127

PIC12(L)F1822/16(L)F1823 REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FVREN FVRRDY(1) TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 0 = Fixed Voltage Reference output is not ready or not enabled 1 = Fixed Voltage Reference output is ready for use bit 5 TSEN: Temperature Indicator Enable bit 0 = Temperature Indicator is disabled 1 = Temperature Indicator is enabled bit 4 TSRNG: Temperature Indicator Range Selection bit 0 = VOUT = VDD - 2VT (Low Range) 1 = VOUT = VDD - 4VT (High Range) bit 3-2 CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bits 00 =Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is off 01 =Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 =Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 =Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bits 00 =ADC Fixed Voltage Reference Peripheral output is off 01 =ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 =ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 =ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) Note 1: FVRRDY is always ‘1’ on PIC12F1822/16F1823 only. 2: Fixed Voltage Reference output cannot exceed VDD. TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 128 Legend: Shaded cells are unused by the Fixed Voltage Reference module. DS40001413E-page 128  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 15.0 TEMPERATURE INDICATOR FIGURE 15-1: TEMPERATURE CIRCUIT MODULE DIAGRAM This family of devices is equipped with a temperature VDD circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating TSEN temperature falls between of -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is TSRNG internally connected to the device ADC. The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A one- point calibration allows the circuit to indicate a VOUT ADC temperature closely surrounding that point. A two-point MUX ADC calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal n Temperature Indicator” (DS01333) for more details CHS bits regarding the calibration process. (ADCON0 register) 15.1 Circuit Operation Figure15-1 shows a simplified block diagram of the 15.2 Minimum Operating VDD vs. temperature circuit. The proportional voltage output is Minimum Sensing Temperature achieved by measuring the forward voltage drop across When the temperature circuit is operated in low range, multiple silicon junctions. the device may be operated at any operating voltage Equation15-1 describes the output characteristics of that is within specifications. the temperature indicator. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high EQUATION 15-1: VOUT RANGES enough to ensure that the temperature circuit is correctly biased. High Range: VOUT = VDD - 4VT Table15-1 shows the recommended minimum VDD vs. range setting. Low Range: VOUT = VDD - 2VT TABLE 15-1: RECOMMENDED VDD VS. RANGE The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 Section14.0 “Fixed Voltage Reference (FVR)” for 3.6V 1.8V more information. The circuit is enabled by setting the TSEN bit of the 15.3 Temperature Output FVRCON register. When disabled, the circuit draws no current. The output of the circuit is measured using the internal analog to digital converter. A channel is reserved for the The circuit operates in either high or low range. The high temperature circuit output. Refer to Section16.0 range, selected by setting the TSRNG bit of the “Analog-to-Digital Converter (ADC) Module” for FVRCON register, provides a wider output voltage. This detailed information. provides more resolution over the temperature range, but may be less consistent from part to part. This range 15.3.1 ADC ACQUISITION TIME requires a higher bias voltage to operate and thus, a higher VDD is needed. To ensure accurate temperature measurements, the user must wait at least 200 usec after the ADC input The low range is selected by clearing the TSRNG bit of multiplexer is connected to the temperature indicator the FVRCON register. The low range generates a lower output before the conversion is performed. In addition, voltage drop and thus, a lower bias voltage is needed to the user must wait 200 usec between sequential operate the circuit. The low range is provided for low conversions of the temperature indicator output. voltage operation.  2010-2015 Microchip Technology Inc. DS40001413E-page 129

PIC12(L)F1822/16(L)F1823 16.0 ANALOG-TO-DIGITAL The ADC can generate an interrupt upon completion of CONVERTER (ADC) MODULE a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure16-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 16-1: ADC BLOCK DIAGRAM VDD ADPREF = 00 ADPREF = 11 VREF+ ADPREF = 10 AN0 00000 AN1 00001 AN2 00010 AN3 00011 AN4(2) 00100 AN5(2) 00101 AN6(2) 00110 AN7(2) 00111 ADC GO/DONE 10 Temp Indicator 11101 0 = Left Justify DAC_output 11110 ADFM 1 = Right Justify FVR Buffer1 11111 ADON(1) 16 VSS ADRESH ADRESL CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: Not available on PIC12(L)F1822. DS40001413E-page 130  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 16.1 ADC Configuration 16.1.4 CONVERSION CLOCK When configuring and using the ADC the following The source of the conversion clock is software select- functions must be considered: able via the ADCS bits of the ADCON1 register. There are seven possible clock options: • Port configuration • FOSC/2 • Channel selection • FOSC/4 • ADC voltage reference selection • FOSC/8 • ADC conversion clock source • FOSC/16 • Interrupt control • FOSC/32 • Result formatting • FOSC/64 16.1.1 PORT CONFIGURATION • FRC (dedicated internal oscillator) The ADC can be used to convert both analog and The time to complete one bit conversion is defined as digital signals. When converting analog signals, the I/O TAD. One full 10-bit conversion requires 11.5 TAD pin should be configured for analog by setting the periods as shown in Figure16-2. associated TRIS and ANSEL bits. Refer to For correct conversion, the appropriate TAD specifica- Section12.0 “I/O Ports” for more information. tion must be met. Refer to the A/D conversion require- Note: Analog voltages on any pin that is defined ments in Section30.0 “Electrical Specifications” for as a digital input may cause the input buf- more information. Table16-1 gives examples of appro- fer to conduct excess current. priate ADC clock selections. Note: Unless using the FRC, any changes in the 16.1.2 CHANNEL SELECTION system clock frequency will change the There are up to 11 channel selections available: ADC clock frequency, which may adversely affect the ADC result. • AN<3:0> pins (PIC12(L)F1822 only) • AN<7:0> pins (PIC16(L)F1823 only) • Temperature Indicator • DAC_output • FVR Buffer1 Output Refer to Section17.0 “Digital-to-Analog Converter (DAC) Module”, Section14.0 “Fixed Voltage Refer- ence (FVR)” and Section15.0 “Temperature Indica- tor Module” for more information on these channel selections. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section16.2 “ADC Operation” for more information. 16.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: • VREF+ pin • VDD • FVR 2.048V • FVR 4.096V (Not available on LF devices) See Section14.0 “Fixed Voltage Reference (FVR)” for more details on the Fixed Voltage Reference.  2010-2015 Microchip Technology Inc. DS40001413E-page 131

PIC12(L)F1822/16(L)F1823 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Clock Source Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3) Fosc/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3) Fosc/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.0 s(3) Fosc/64 110 2.0 s 3.2 s 4.0 s 8.0 s(3) 16.0 s(3) 64.0 s(3) FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 1.6 s for VDD. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS40001413E-page 132  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 16.1.5 INTERRUPTS 16.1.6 RESULT FORMATTING The ADC module allows for the ability to generate an The 10-bit A/D conversion result can be supplied in two interrupt upon completion of an Analog-to-Digital formats, left justified or right justified. The ADFM bit of conversion. The ADC Interrupt Flag is the ADIF bit in the ADCON1 register controls the output format. the PIR1 register. The ADC Interrupt Enable is the Figure16-3 shows the two output formats. ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruc- tion is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execu- tion, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. FIGURE 16-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result  2010-2015 Microchip Technology Inc. DS40001413E-page 133

PIC12(L)F1822/16(L)F1823 16.2 ADC Operation 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This 16.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC To enable the ADC module, the ADON bit of the option. When the FRC clock source is selected, the ADCON0 register must be set to a ‘1’. Setting the GO/ ADC waits one additional instruction before starting the DONE bit of the ADCON0 register to a ‘1’ will start the conversion. This allows the SLEEP instruction to be Analog-to-Digital conversion. executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device Note: The GO/DONE bit should not be set in the will wake-up from Sleep when the conversion same instruction that turns on the ADC. completes. If the ADC interrupt is disabled, the ADC Refer to Section16.2.6 “A/D Conver- module is turned off after the conversion completes, sion Procedure”. although the ADON bit remains set. 16.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conver- When the conversion is complete, the ADC module will: sion to be aborted and the ADC module is turned off, • Clear the GO/DONE bit although the ADON bit remains set. • Set the ADIF Interrupt Flag bit 16.2.5 SPECIAL EVENT TRIGGER • Update the ADRESH and ADRESL registers with new conversion result The Special Event Trigger of the CCPx/ECCPX module allows periodic ADC measurements without software 16.2.3 TERMINATING A CONVERSION intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to If a conversion must be terminated before completion, zero. the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with TABLE 16-2: SPECIAL EVENT TRIGGER the partially complete Analog-to-Digital conversion Device CCP1/ECCP1 sample. Incomplete bits will match the last bit converted. PIC12(L)F1822/16(L)F1823 CCP1 Note: A device Reset forces all registers to their Using the Special Event Trigger does not assure proper Reset state. Thus, the ADC module is ADC timing. It is the user’s responsibility to ensure that turned off and any pending conversion is the ADC timing requirements are met. terminated. Refer to Section24.0 “Capture/Compare/PWM Mod- ules” for more information. DS40001413E-page 134  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 16.2.6 A/D CONVERSION PROCEDURE EXAMPLE 16-1: A/D CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. 1. Configure Port: ; • Disable pin output driver (Refer to the TRIS ;Conversion start & polling for completion register) ; are included. • Configure pin as analog (Refer to the ANSEL ; register) BANKSEL ADCON1 ; MOVLW B’11110000’ ;Right justify, Frc 2. Configure the ADC module: ;clock • Select ADC conversion clock MOVWF ADCON1 ;Vdd and Vss Vref • Configure voltage reference BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input • Select ADC input channel BANKSEL ANSEL ; • Turn on ADC module BSF ANSEL,0 ;Set RA0 to analog 3. Configure ADC interrupt (optional): BANKSEL ADCON0 ; • Clear ADC interrupt flag MOVLW B’00000001’ ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On • Enable ADC interrupt CALL SampleTime ;Acquisiton delay • Enable peripheral interrupt BSF ADCON0,ADGO ;Start conversion • Enable global interrupt(1) BTFSC ADCON0,ADGO ;Is conversion done? 4. Wait the required acquisition time(2). GOTO $-1 ;No, test again BANKSEL ADRESH ; 5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits 6. Wait for ADC conversion to complete by one of MOVWF RESULTHI ;store in GPR space the following: BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits • Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result. 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section16.3 “A/D Acquisition Requirements”.  2010-2015 Microchip Technology Inc. DS40001413E-page 135

PIC12(L)F1822/16(L)F1823 16.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 16-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CHS<4:0> GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 =AN0 00001 =AN1 00010 =AN2 00011 =AN3 00100 =AN4(1) 00101 =AN5(1) 00110 =AN6(1) 00111 =AN7(1) 01001 =Reserved. No channel connected. • • • 11100 =Reserved. No channel connected. 11101 =Temperature Indicator(4) 11110 =DAC output(2) 11111 =FVR (Fixed Voltage Reference) Buffer 1 Output(3) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: PIC16(L)F1823 only. For PIC12(L)F1822 it is “Reserved. No channel connected”. 2: See Section17.0 “Digital-to-Analog Converter (DAC) Module” for more information. 3: See Section14.0 “Fixed Voltage Reference (FVR)” for more information. 4: See Section15.0 “Temperature Indicator Module” for more information. DS40001413E-page 136  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> — — ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded. bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 =FOSC/2 001 =FOSC/8 010 =FOSC/32 011 =FRC (clock supplied from a dedicated RC oscillator) 100 =FOSC/4 101 =FOSC/16 110 =FOSC/64 111 =FRC (clock supplied from a dedicated RC oscillator) bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits 00 = VREF+ is connected to AVDD 01 = Reserved 10 = VREF+ is connected to external VREF+(1) 11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1) Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section30.0 “Electrical Specifications” for details.  2010-2015 Microchip Technology Inc. DS40001413E-page 137

PIC12(L)F1822/16(L)F1823 REGISTER 16-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 16-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<1:0> — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. DS40001413E-page 138  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 16-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result  2010-2015 Microchip Technology Inc. DS40001413E-page 139

PIC12(L)F1822/16(L)F1823 16.3 A/D Acquisition Requirements source impedance is decreased, the acquisition time may be decreased. After the analog input channel is For the ADC to meet its specified accuracy, the charge selected (or changed), an A/D acquisition must be holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate charge to the input channel voltage level. The Analog the minimum acquisition time, Equation16-1 may be Input model is shown in Figure16-4. The source used. This equation assumes that 1/2 LSb error is used impedance (RS) and the internal sampling switch (RSS) (1,024 steps for the ADC). The 1/2 LSb error is the impedance directly affect the time required to charge maximum error allowed for the ADC to meet its the capacitor CHOLD. The sampling switch (RSS) specified resolution. impedance varies over the device voltage (VDD), refer to Figure16-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 16-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– ------n----+----1------------ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb 2 –1 –TC  ---------- RC VAPPLIED1–e  = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– ------n---+-----1------------ ;combining [1] and [2]   2  –1 Note: Where n = number of bits of the ADC. Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/2047) = –12.5pF1k+7k+10k ln(0.0004885) = 1.72µs Therefore: TACQ = 2µs+1.72µs+50°C- 25°C0.05µs/°C = 4.97µs Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification. DS40001413E-page 140  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Sampling Input Switch VT  0.6V Rs pin RIC  1k SS Rss VA C5 PpIFN VT  0.6V I LEAKAGE(1) CHOLD = 12.5 pF VSS/VREF- 6V 5V RSS Legend: CHOLD = Sample/Hold Capacitance VDD4V 3V CPIN = Input Capacitance 2V I LEAKAGE = Leakage current at the pin due to various junctions 5 6 7 891011 RIC = Interconnect Resistance Sampling Switch RSS = Resistance of Sampling Switch (k) SS = Sampling Switch VT = Threshold Voltage Note1: Refer to Section30.0 “Electrical Specifications”. FIGURE 16-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh 3FCh e od 3FBh C ut p ut O C D 03h A 02h 01h 00h Analog Input Voltage 0.5 LSB 1.5 LSB Zero-Scale VSS/VREF- Transition Full-Scale Transition VREF+  2010-2015 Microchip Technology Inc. DS40001413E-page 141

PIC12(L)F1822/16(L)F1823 TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 136 ADCON1 ADFM ADCS2 ADCS1 ADCS0 — — ADPREF1 ADPREF0 137 ADRESH A/D Result Register High 130* ADRESL A/D Result Register Low 130* ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 ANSELC(1) — — — — ANSC3 ANSC2 ANSC1 ANSC0 122 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 213 DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — — 146 DACCON1 — — — DACR4 DACR3 DACR2 DACR1 DACR0 146 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 128 INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. * Page provides register information. Note 1: PIC16(L)F1823 only. DS40001413E-page 142  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 17.0 DIGITAL-TO-ANALOG 17.1 Output Voltage Selection CONVERTER (DAC) MODULE The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 The Digital-to-Analog Converter supplies a variable register. voltage reference, ratiometric with the input source, with 32 selectable output levels. The DAC output voltage is determined by the following equations: The input of the DAC can be connected to: • External VREF pins • VDD supply voltage • FVR Buffer2 The output of the DAC can be configured to supply a reference voltage to the following: • Comparator positive input • ADC input channel • DACOUT pin The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register. EQUATION 17-1: DAC OUTPUT VOLTAGE IF DACEN = 1  DACR4:0 VOUT = VSOURCE+–VSOURCE------------------------------ +VSOURCE-  5  2 IF DACEN = 0 & DACLPS = 1 & DACR[4:0] = 11111 VOUT = VSOURCE+ IF DACEN = 0 & DACLPS = 0 & DACR[4:0] = 00000 VOUT = VSOURCE– VSOURCE+ = VDD or FVR BUFFER 2 VSOURCE- = VSS 17.2 Ratiometric Output Level 17.3 DAC Voltage Reference Output The DAC output value is derived using a resistor ladder The DAC can be output to the DACOUT pin by setting with each end of the ladder tied to a positive and the DACOE bit of the DACCON0 register to ‘1’. negative voltage reference input source. If the voltage Selecting the DAC reference voltage for output on the of either input source fluctuates, a similar fluctuation will DACOUT pin automatically overrides the digital output result in the DAC output value. buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been The value of the individual resistors within the ladder configured for DAC reference voltage output will can be found in Section30.0 “Electrical always return a ‘0’. Specifications”. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to DACOUT. Figure17-2 shows an example buffering technique.  2010-2015 Microchip Technology Inc. DS40001413E-page 143

PIC12(L)F1822/16(L)F1823 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSOURCE+ VDD DACR<4:0> 5 VREF+ R R DACPSS<1:0> 2 R DACEN DACLPS R R X 32 U Steps 1 M DAC_output o- (To Comparator, CPS and 2-t ADC Modules) R 3 R DACOUT R DACOE VSOURCE- FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC R Module + Voltage DACOUT – Buffered DAC Output Reference Output Impedance DS40001413E-page 144  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 17.4 Low-Power Voltage State This is also the method used to output the voltage level from the FVR to an output pin. See Section17.5 In order for the DAC module to consume the least “Operation During Sleep” for more information. amount of power, one of the two voltage reference input Reference Figure17-3 for output clamping examples. sources to the resistor ladder must be disconnected. Either the positive voltage source, (VSOURCE+), or the 17.4.2 OUTPUT CLAMPED TO NEGATIVE negative voltage source, (VSOURCE-) can be disabled. VOLTAGE SOURCE The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the The DAC output voltage can be set to VSOURCE- with the least amount of power consumption by performing DACLPS bit in the DACCON0 register disables the the following: positive voltage source. • Clearing the DACEN bit in the DACCON0 register. 17.4.1 OUTPUT CLAMPED TO POSITIVE • Clearing the DACLPS bit in the DACCON0 register. VOLTAGE SOURCE • Configuring the DACR<4:0> bits to ‘00000’ in the The DAC output voltage can be set to VSOURCE+ with DACCON1 register. the least amount of power consumption by performing This allows the comparator to detect a zero-crossing the following: while not consuming additional current through the DAC • Clearing the DACEN bit in the DACCON0 register. module. • Setting the DACLPS bit in the DACCON0 register. Reference Figure17-3 for output clamping examples. • Configuring the DACPSS bits to the proper positive source. • Configuring the DACR<4:0> bits to ‘11111’ in the DACCON1 register. FIGURE 17-3: OUTPUT VOLTAGE CLAMPING EXAMPLES Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source VSOURCE+ VSOURCE+ R R DACR<4:0> = 11111 R R DACEN = 0 DACEN = 0 DACLPS = 1 DAC Voltage Ladder DACLPS = 0 DAC Voltage Ladder (see Figure17-1) (see Figure17-1) R R DACR<4:0> = 00000 VSOURCE- VSOURCE- 17.5 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 17.6 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared.  2010-2015 Microchip Technology Inc. DS40001413E-page 145

PIC12(L)F1822/16(L)F1823 REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 DACEN DACLPS DACOE — DACPSS<1:0> — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 DACLPS: DAC Low-Power Voltage State Select bit 1 = DAC Positive reference source selected 0 = DAC Negative reference source selected bit 5 DACOE: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin bit 4 Unimplemented: Read as ‘0’ bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits 00 = VDD 01 = VREF+ pin 10 = FVR Buffer2 output 11 = Reserved, do not use bit 1-0 Unimplemented: Read as ‘0’ REGISTER 17-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — DACR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR<4:0>: DAC Voltage Output Select bits TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 128 DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — — 146 DACCON1 — — — DACR4 DACR3 DACR2 DACR1 DACR0 146 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the DAC module. DS40001413E-page 146  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 18.0 SR LATCH The module consists of a single SR latch with multiple 18.2 Latch Output Set and Reset inputs as well as separate latch outputs. The SR latch module includes the following features: The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs. Both of the SR • Programmable input selection latch outputs may be directly output to an I/O pin at the • SR latch output is available externally same time. • Separate Q and Q outputs The applicable TRIS bit of the corresponding port must • Firmware Set and Reset be cleared to enable the port pin output driver. The SR latch can be used in a variety of analog appli- cations, including oscillator circuits, one-shot circuit, 18.3 Effects of a Reset hysteretic controllers, and analog timing applications. Upon any device Reset, the SR latch output is not 18.1 Latch Operation initialized to a known state. The user’s firmware is responsible for initializing the latch output before The latch is a Set-Reset Latch that does not depend on enabling the output pins. a clock source. Each of the Set and Reset inputs are active-high. The latch can be Set or Reset by: • Software control (SRPS and SRPR bits) • Comparator C1 output (sync_C1OUT) • Comparator C2 output (sync_C2OUT) (PIC16(L)F1823 only) • SRI pin • Programmable clock (SRCLK) The SRPS and the SRPR bits of the SRCON0 register may be used to Set or Reset the SR latch, respectively. The latch is Reset-dominant. Therefore, if both Set and Reset inputs are high, the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset oper- ation. The output from Comparator C1 or C2 can be used as the Set or Reset inputs of the SR latch. The output of either Comparator can be synchronized to the Timer1 clock source. See Section19.0 “Comparator Module” and Section21.0 “Timer1 Module with Gate Control” for more information. An external source on the SRI pin can be used as the Set or Reset inputs of the SR latch. An internal clock source is available that can periodically set or reset the SR latch. The SRCLK<2:0> bits in the SRCON0 register are used to select the clock source period. The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to Set or Reset the SR latch, respectively.  2010-2015 Microchip Technology Inc. DS40001413E-page 147

PIC12(L)F1822/16(L)F1823 FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRLEN SRPS Pulse SRQEN Gen(2) SRI SRSPE S Q SRCLK SRQ SRSCKE SYNC_C2OUT(3, 4) SRSC2E(4) SYNC_C1OUT(3) SR SRSC1E Latch(1) SRPR Pulse Gen(2) SRI SRRPE R Q SRCLK SRNQ SRRCKE SRLEN SYNC_C2OUT(3, 4) SRNQEN SRRC2E(4) SYNC_C1OUT(3) SRRC1E Note 1: If R=1 and S=1 simultaneously, Q=0, Q=1 2: Pulse generator causes a 1 Q-state pulse width. 3: Name denotes the connection point at the comparator output. 4: PIC16(L)F1823 only. DS40001413E-page 148  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 18-1: SRCLK FREQUENCY TABLE SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 62.5kHz 39.0kHz 31.3kHz 7.81kHz 1.95kHz 110 256 125kHz 78.1kHz 62.5kHz 15.6kHz 3.90kHz 101 128 250kHz 156kHz 125kHz 31.25kHz 7.81kHz 100 64 500kHz 313kHz 250kHz 62.5kHz 15.6kHz 011 32 1MHz 625kHz 500kHz 125kHz 31.3 kHz 010 16 2MHz 1.25MHz 1MHz 250kHz 62.5kHz 001 8 4MHz 2.5MHz 2MHz 500kHz 125kHz 000 4 8MHz 5MHz 4MHz 1MHz 250kHz REGISTER 18-1: SRCON0: SR LATCH CONTROL 0 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/S-0/0 R/S-0/0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared S = Bit is set only bit 7 SRLEN: SR Latch Enable bit 1 = SR latch is enabled 0 = SR latch is disabled bit 6-4 SRCLK<2:0>: SR Latch Clock Divider bits 000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock 001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock 010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock 011 = Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock 100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock 101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock 110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock 111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock bit 3 SRQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRQ pin 0 = External Q output is disabled If SRLEN = 0: SR latch is disabled bit 2 SRNQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRnQ pin 0 = External Q output is disabled If SRLEN = 0: SR latch is disabled bit 1 SRPS: Pulse Set Input of the SR Latch bit(1) 1 = Pulse set input for 1 Q-clock period 0 = No effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit(1) 1 = Pulse reset input for 1 Q-clock period 0 = No effect on reset input. Note 1: Set only, always reads back ‘0’.  2010-2015 Microchip Technology Inc. DS40001413E-page 149

PIC12(L)F1822/16(L)F1823 REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE SRSC2E(1) SRSC1E SRRPE SRRCKE SRRC2E(1) SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SR latch is set when the SRI pin is high 0 = SRI pin has no effect on the set input of the SR latch bit 6 SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR latch is pulsed with SRCLK 0 = SRCLK has no effect on the set input of the SR latch bit 5 SRSC2E: SR Latch C2 Set Enable bit(1) 1 = SR latch is set when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the set input of the SR latch bit 4 SRSC1E: SR Latch C1 Set Enable bit 1 = SR latch is set when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the set input of the SR latch bit 3 SRRPE: SR Latch Peripheral Reset Enable bit 1 = SR latch is reset when the SRI pin is high 0 = SRI pin has no effect on the reset input of the SR latch bit 2 SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR latch is pulsed with SRCLK 0 = SRCLK has no effect on the reset input of the SR latch bit 1 SRRC2E: SR Latch C2 Reset Enable bit(1) 1 = SR latch is reset when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the reset input of the SR latch bit 0 SRRC1E: SR Latch C1 Reset Enable bit 1 = SR latch is reset when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the reset input of the SR latch Note 1: PIC16(L)F1823 only. DS40001413E-page 150  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 149 SRCON1 SRSPE SRSCKE SRSC2E(1) SRSC1E SRRPE SRRCKE SRRC2E(1) SRRC1E 150 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR latch module. Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 151

PIC12(L)F1822/16(L)F1823 19.0 COMPARATOR MODULE FIGURE 19-1: SINGLE COMPARATOR Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and VIN+ + providing a digital indication of their relative magnitudes. Output Comparators are very useful mixed signal building VIN- – blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: • Independent comparator control VIN- • Programmable input selection VIN+ • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change Output • Wake-up from Sleep • Programmable Speed/Power optimization • PWM shutdown Note: The black areas of the output of the • Programmable and Fixed Voltage Reference comparator represents the uncertainty 19.1 Comparator Overview due to input offsets and response time. A single comparator is shown in Figure19-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. DS40001413E-page 152  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 19-2: COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM (PIC12(L)F1822) CxNCH<1:0> C1ON(1) 2 Interrupt C1INTP det Set C1IF C1IN0- 0 MUX Interrupt C1INTN (2) det C1IN1- 1 C1POL C1VN - C1OUT Cx(3) D Q MC1OUT To Data Bus + C1VP Q1 EN C1IN+ 0 MUX C1HYS DAC_output 1 (2) C1SP To ECCP PWM Logic FVR Buffer2 2 3 C1SYNC VSS C1ON C1OE TRIS bit C1OUT C1PCH<1:0> 0 2 D Q 1 (from Timer1) T1CLK To Timer1 or SR Latch sync_C1OUT Note 1: When C1ON = 0, the Comparator will produce a ‘0’ at the output. 2: When C1ON = 0, all multiplexer inputs are disconnected. 3: Output of comparator can be frozen during debugging.  2010-2015 Microchip Technology Inc. DS40001413E-page 153

PIC12(L)F1822/16(L)F1823 FIGURE 19-3: COMPARATOR 1 AND 2 MODULES SIMPLIFIED BLOCK DIAGRAM (PIC16(L)F1823) CxNCH<1:0> CxON(1) 2 Interrupt CxINTP det C12IN0- 0 Set CxIF C12IN1- 1 MUX Interrupt CxINTN C12IN2- 2 (2) det CXPOL C12IN3- 3 CxVN - Cx(3) D Q CMXCOXUOTUT To Data Bus + CxVP Q1 EN CXIN+ 0 MUX CxHYS DAC_output 1 (2) CxSP To ECCP PWM Logic FVR Buffer2 2 3 CXSYNC VSS CxON CXOE TRIS bit CXPCH<1:0> 0 CXOUT 2 D Q 1 (from Timer1) T1CLK To Timer1 or SR Latch sync_CxOUT Note 1: When CxON = 0, the Comparator will produce a ‘0’ at the output. 2: When CxON = 0, all multiplexer inputs are disconnected. 3: Output of comparator can be frozen during debugging. DS40001413E-page 154  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 19.2 Comparator Control 19.2.3 COMPARATOR OUTPUT POLARITY Each comparator has two control registers: CMxCON0 Inverting the output of the comparator is functionally and CMxCON1. equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by The CMxCON0 registers (see Register18-1) contain setting the CxPOL bit of the CMxCON0 register. Control and Status bits for the following: Clearing the CxPOL bit results in a non-inverted output. • Enable Table19-1 shows the output state versus input • Output selection conditions, including polarity control. • Output polarity TABLE 19-1: COMPARATOR OUTPUT • Speed/Power selection STATE VS. INPUT • Hysteresis enable CONDITIONS • Output synchronization Input Condition CxPOL CxOUT The CMxCON1 registers (see Register18-2) contain CxVN > CxVP 0 0 Control bits for the following: CxVN < CxVP 0 1 • Interrupt enable CxVN > CxVP 1 1 • Interrupt edge polarity CxVN < CxVP 1 0 • Positive input channel selection • Negative input channel selection 19.2.4 COMPARATOR SPEED/POWER SELECTION 19.2.1 COMPARATOR ENABLE The trade-off between speed or power can be opti- Setting the CxON bit of the CMxCON0 register enables mized during program execution with the CxSP control the comparator for operation. Clearing the CxON bit bit. The default state for this bit is ‘1’ which selects the disables the comparator resulting in minimum current normal speed mode. Device power consumption can consumption. be optimized at the cost of slower comparator propaga- 19.2.2 COMPARATOR OUTPUT tion delay by clearing the CxSP bit to ‘0’. SELECTION The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set Note1: The CxOE bit of the CMxCON0 register overrides the PORT data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched.  2010-2015 Microchip Technology Inc. DS40001413E-page 155

PIC12(L)F1822/16(L)F1823 19.3 Comparator Hysteresis 19.5 Comparator Interrupt A selectable amount of separation voltage can be An interrupt can be generated upon a change in the added to the input pins of each comparator to provide a output value of the comparator for each comparator, a hysteresis function to the overall operation. Hysteresis rising edge detector and a Falling edge detector are is enabled by setting the CxHYS bit of the CMxCON0 present. register. When either edge detector is triggered and its associ- See Section30.0 “Electrical Specifications” for ated enable bit is set (CxINTP and/or CxINTN bits of more information. the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. 19.4 Timer1 Gate Operation To enable the interrupt, you must set the following bits: The output resulting from a comparator operation can • CxON, CxPOL and CxSP bits of the CMxCON0 be used as a source for gate control of Timer1. See register Section21.6 “Timer1 Gate” for more information. • CxIE bit of the PIE2 register This feature is useful for timing the duration or interval • CxINTP bit of the CMxCON1 register (for a rising of an analog event. edge detection) It is recommended that the comparator output be • CxINTN bit of the CMxCON1 register (for a falling synchronized to Timer1. This ensures that Timer1 does edge detection) not increment while a change in the comparator is • PEIE and GIE bits of the INTCON register occurring. The associated interrupt flag bit, CxIF bit of the PIR2 19.4.1 COMPARATOR OUTPUT register, must be cleared in software. If another edge is SYNCHRONIZATION detected while this flag is being cleared, the flag will still be set at the end of the sequence. The output from either comparator, C1 or C2, can be synchronized with Timer1 by setting the CxSYNC bit of Note: Although a comparator is disabled, an the CMxCON0 register. interrupt can be generated by changing the output polarity with the CxPOL bit of Once enabled, the comparator output is latched on the the CMxCON0 register, or by switching falling edge of the Timer1 source clock. If a prescaler is the comparator on or off with the CxON bit used with Timer1, the comparator output is latched after of the CMxCON0 register. the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the 19.6 Comparator Positive Input Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Selection Block Diagrams (Figures19-2and19-3) and the Configuring the CxPCH<1:0> bits of the CMxCON1 Timer1 Block Diagram (Figure21-1) for more register directs an internal voltage reference or an information. analog pin to the non-inverting input of the comparator: • C1IN+ or C2IN+ analog pin • DAC_output • FVR Buffer2 • VSS (Ground) See Section14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section17.0 “Digital-to-Analog Converter (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. DS40001413E-page 156  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 19.7 Comparator Negative Input 19.10 Analog Input Connection Selection Considerations The CxNCH<1:0> bits of the CMxCON0 register direct A simplified circuit for an analog input is shown in one of four analog pins to the comparator inverting Figure19-4. Since the analog input pins share their input. connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The Note: To use CxIN+ and CxINx- pins as analog analog input, therefore, must be between VSS and VDD. input, the appropriate bits must be set in If the input voltage deviates from this range by more the ANSEL register and the correspond- than 0.6V in either direction, one of the diodes is ing TRIS bits must also be set to disable forward biased and a latch-up may occur. the output drivers. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component 19.8 Comparator Response Time connected to an analog input pin, such as a capacitor or The comparator output is indeterminate for a period of a Zener diode, should have very little leakage current to time after the change of an input source or the selection minimize inaccuracies introduced. of a new reference voltage. This period is referred to as the response time. The response time of the comparator Note1: When reading a PORT register, all pins differs from the settling time of the voltage reference. configured as analog inputs will read as a Therefore, both of these times must be considered when ‘0’. Pins configured as digital inputs will determining the total response time to a comparator convert as an analog input, according to input change. See the Comparator and Voltage Refer- the input specification. ence Specifications in Section30.0 “Electrical Specifi- cations” for more details. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to 19.9 Interaction with ECCP Logic consume more current than is specified. The C1 and C2 comparators can be used as general purpose comparators. Their outputs can be brought out to the C1OUT and C2OUT pins. When the ECCP Auto-Shutdown is active it can use one or both comparator signals. If auto-restart is also enabled, the comparators can be configured as a closed loop analog feedback to the ECCP, thereby, creating an analog controlled PWM. Note: When the Comparator module is first initialized the output state is unknown. Upon initialization, the user should verify the output state of the comparator prior to relying on the result, primarily when using the result in connection with other peripheral features, such as the ECCP Auto-Shutdown mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 157

PIC12(L)F1822/16(L)F1823 FIGURE 19-4: ANALOG INPUT MODEL VDD Analog Input Rs < 10K pin VT  0.6V RIC To Comparator VA C5 PpIFN VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage Note 1: See Section30.0 “Electrical Specifications” DS40001413E-page 158  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 19-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and consumes no power bit 6 CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous.  2010-2015 Microchip Technology Inc. DS40001413E-page 159

PIC12(L)F1822/16(L)F1823 REGISTER 19-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 CxINTP CxINTN CxPCH<1:0> — — CxNCH1(1) CxNCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits 00 = CxVP connects to CxIN+ pin 01 = CxVP connects to DAC Voltage Reference 10 = CxVP connects to FVR Voltage Reference 11 = CxVP connects to VSS bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CxNCH<1:0>: Comparator Negative Input Channel Select bits PIC12(L)F1822: 0 = C1VN connects to C1IN0- pin 1 = C1VN connects to C1IN1- pin PIC16(L)F1823: 00 = CxVN connects to C12IN0- pin 01 = CxVN connects to C12IN1- pin 10 = CxVN connects to C12IN2- pin 11 = CxVN connects to C12IN3- pin Note 1: PIC16(L)F1823 only. REGISTER 19-3: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0 — — — — — — MC2OUT(1) MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit(1) bit 0 MC1OUT: Mirror Copy of C1OUT bit Note 1: PIC16(L)F1823 only. DS40001413E-page 160  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 159 CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 — — C1NCH1(1) C1NCH0 160 CM2CON0(1) C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 159 CM2CON1(1) C2INTP C2INTN C2PCH1 C2PCH0 — — C2NCH1 C2NCH0 160 CMOUT — — — — — — MC2OUT(1) MC1OUT 160 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 87 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 161

PIC12(L)F1822/16(L)F1823 20.0 TIMER0 MODULE 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment The Timer0 module is an 8-bit timer/counter with the on every rising or falling edge of the T0CKI pin or the following features: Capacitive Sensing Oscillator (CPSCLK) signal. • 8-bit timer/counter register (TMR0) 8-Bit Counter mode using the T0CKI pin is selected by • 8-bit prescaler (independent of Watchdog Timer) setting the TMR0CS bit in the OPTION register to ‘1’ • Programmable internal or external clock source and resetting the T0XCS bit in the CPSCON0 register to • Programmable external clock edge selection ‘0’. • Interrupt on overflow 8-Bit Counter mode using the Capacitive Sensing • TMR0 can be used to gate Timer1 Oscillator (CPSCLK) signal is selected by setting the Figure20-1 is a block diagram of the Timer0 module. TMR0CS bit in the OPTION register to ‘1’ and setting the T0XCS bit in the CPSCON0 register to ‘1’. 20.1 Timer0 Operation The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit The Timer0 module can be used as either an 8-bit timer in the OPTION register. or an 8-bit counter. 20.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the OPTION register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 20-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 Sync 0 1 2 TCY TMR0 0 From CPSCLK 1 TMR0SE TMR0CS 8-bit Set Flag bit TMR0IF on Overflow Prescaler PSA T0XCS Overflow to Timer1 8 PS<2:0> DS40001413E-page 162  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 mod- ule ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 20.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 20.1.5 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section30.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 163

PIC12(L)F1822/16(L)F1823 REGISTER 20-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate 000 1 : 2 001 1 : 4 010 1 : 8 011 1 : 16 100 1 : 32 101 1 : 64 110 1 : 128 111 1 : 256 TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CPSCON0 CPSON CPSRM — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 302 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 164 TMR0 Timer0 Module Register 162* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. DS40001413E-page 164  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 21.0 TIMER1 MODULE WITH GATE • Gate Toggle mode CONTROL • Gate Single-pulse mode • Gate Value Status The Timer1 module is a 16-bit timer/counter with the • Gate Event Interrupt following features: Figure21-1 is a block diagram of the Timer1 module. • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 2-bit prescaler • Dedicated 32 kHz oscillator circuit • Optionally synchronized comparator out • Multiple Timer1 gate (count enable) sources • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with CCP/ECCP) • Selectable Gate Source Polarity FIGURE 21-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 T1GSPM FrOomve Trfilmower0 01 T1G_IN 0 0 T1GVAL D Q Data Bus Csyonmcp_aCr1aOtoUr T1 10 SAicnqg.l eC Ponutlrsoel 1 Q1 EN T1GRCDON D Q 1 Csyonmcp_aCr2aOtoUr T2 11 CK Q T1GGO/DONE Interrupt Set TMR1ON R det TMR1GIF T1GPOL T1GTM TMR1GE Set flag bit TMR1ON TMR1IF on To Comparator Module Overflow TMR1(2) EN Synchronized TMR1H TMR1L T1CLK 0 clock input Q D 1 TMR1CS<1:0> T1SYNC T1OSO OUT Cap. Sensing T1OSC Oscillator 11 Prescaler Synchronize(3) 1 1, 2, 4, 8 det T1OSI EN 10 2 0 FOSC T1CKPS<1:0> Internal 01 T1OSCEN Clock IFnOteSrCn/a2l Sleep input FOSC/4 Clock Internal 00 (1) Clock T1CKI To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2010-2015 Microchip Technology Inc. DS40001413E-page 165

PIC12(L)F1822/16(L)F1823 21.1 Timer1 Operation 21.2 Clock Source Selection The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> and T1OSCEN bits of the T1CON which is accessed through the TMR1H:TMR1L register register are used to select the clock source for Timer1. pair. Writes to TMR1H or TMR1L directly update the Table21-2 displays the clock source selections. counter. 21.2.1 INTERNAL CLOCK SOURCE When used with an internal clock source, the module is a timer and increments on every instruction cycle. When the internal clock source is selected the When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples can be used as either a timer or counter and incre- of FOSC as determined by the Timer1 prescaler. ments on every selected edge of the external source. When the FOSC internal clock source is selected, the Timer1 is enabled by configuring the TMR1ON and Timer1 register value will increment by four counts every TMR1GE bits in the T1CON and T1GCON registers, instruction clock cycle. Due to this condition, a 2LSB respectively. Table21-1 displays the Timer1 enable error in resolution will occur when reading the Timer1 selections. value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. TABLE 21-1: TIMER1 ENABLE The following asynchronous sources may be used: SELECTIONS • Asynchronous event on the T1G pin to Timer1 Timer1 TMR1ON TMR1GE Gate Operation • C1 or C2 comparator input to Timer1 Gate 0 0 Off 21.2.2 EXTERNAL CLOCK SOURCE 0 1 Off 1 0 Always On When the external clock source is selected, the Timer1 module may work as a timer or a counter. 1 1 Count Enabled When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external 32.768kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • Timer1 enabled after POR • Write to TMR1H or TMR1L • Timer1 is disabled • Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. TABLE 21-2: CLOCK SOURCE SELECTIONS TMR1CS1 TMR1CS0 T1OSCEN Clock Source 0 1 x System Clock (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 1 x Capacitive Sensing Oscillator 1 0 0 External Clocking on T1CKI Pin 1 0 1 Osc.Circuit On T1OSI/T1OSO Pins DS40001413E-page 166  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 21.3 Timer1 Prescaler 21.6 Timer1 Gate Timer1 has four prescaler options allowing 1, 2, 4 or 8 Timer1 can be configured to count freely or the count divisions of the clock input. The T1CKPS bits of the can be enabled and disabled using Timer1 Gate T1CON register control the prescale counter. The circuitry. This is also referred to as Timer1 Gate Enable. prescale counter is not directly readable or writable; Timer1 Gate can also be driven by multiple selectable however, the prescaler counter is cleared upon a write to sources. TMR1H or TMR1L. 21.6.1 TIMER1 GATE ENABLE 21.4 Timer1 Oscillator The Timer1 Gate Enable mode is enabled by setting A dedicated low-power 32.768kHz oscillator circuit is the TMR1GE bit of the T1GCON register. The polarity built-in between pins T1OSI (input) and T1OSO of the Timer1 Gate Enable mode is configured using (amplifier output). This internal circuit is to be used in the T1GPOL bit of the T1GCON register. conjunction with an external 32.768kHz crystal. When Timer1 Gate Enable mode is enabled, Timer1 The oscillator circuit is enabled by setting the will increment on the rising edge of the Timer1 clock T1OSCEN bit of the T1CON register. The oscillator will source. When Timer1 Gate Enable mode is disabled, continue to run during Sleep. no incrementing will occur and Timer1 will hold the current count. See Figure21-3 for timing details. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable TABLE 21-3: TIMER1 GATE ENABLE delay observed prior to enabling Timer1. SELECTIONS T1CLK T1GPOL T1G Timer1 Operation 21.5 Timer1 Operation in  0 0 Counts Asynchronous Counter Mode  0 1 Holds Count If control bit T1SYNC of the T1CON register is set, the  1 0 Holds Count external clock input is not synchronized. The timer  1 1 Counts increments asynchronously to the internal phase clocks. If external clock source is selected then the 21.6.2 TIMER1 GATE SOURCE timer will continue to run during Sleep and can SELECTION generate an interrupt on overflow, which will wake-up the processor. However, special precautions in The Timer1 Gate source can be selected from one of software are needed to read/write the timer (see four different sources. Source selection is controlled by Section21.5.1 “Reading and Writing Timer1 in the T1GSS bits of the T1GCON register. The polarity Asynchronous Counter Mode”). for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the Note: When switching from synchronous to T1GCON register. asynchronous operation, it is possible to skip an increment. When switching from TABLE 21-4: TIMER1 GATE SOURCES asynchronous to synchronous operation, it is possible to produce an additional T1GSS Timer1 Gate Source increment. 00 Timer1 Gate Pin 21.5.1 READING AND WRITING TIMER1 IN 01 Overflow of Timer0 ASYNCHRONOUS COUNTER (TMR0 increments from FFh to 00h) MODE 10 Comparator 1 Output sync_C1OUT (optionally Timer1 synchronized output) Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid 11 Comparator 2 Output sync_C2OUT read (taken care of in hardware). However, the user (optionally Timer1 synchronized output) should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.  2010-2015 Microchip Technology Inc. DS40001413E-page 167

PIC12(L)F1822/16(L)F1823 21.6.2.1 T1G Pin Gate Operation 21.6.4 TIMER1 GATE SINGLE-PULSE MODE The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 When Timer1 Gate Single-Pulse mode is enabled, it is Gate circuitry. possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the 21.6.2.2 Timer0 Overflow Gate Operation T1GSPM bit in the T1GCON register. Next, the When Timer0 increments from FFh to 00h, a T1GGO/DONE bit in the T1GCON register must be set. low-to-high pulse will automatically be generated and The Timer1 will be fully enabled on the next incrementing internally supplied to the Timer1 Gate circuitry. edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other 21.6.2.3 Comparator C1 Gate Operation gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. See The output resulting from a Comparator 1 operation can Figure21-5 for timing details. be selected as a source for Timer1 Gate Control. The Comparator 1 output (sync_C1OUT) can be If the Single Pulse Gate mode is disabled by clearing the synchronized to the Timer1 clock or left asynchronous. T1GSPM bit in the T1GCON register, the T1GGO/DONE For more information see Section19.4.1 “Comparator bit should also be cleared. Output Synchronization”. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work 21.6.2.4 Comparator C2 Gate Operation together. This allows the cycle times on the Timer1 The output resulting from a Comparator 2 operation Gate source to be measured. See Figure21-6 for can be selected as a source for Timer1 Gate Control. timing details. The Comparator 2 output (sync_C2OUT) can be synchronized to the Timer1 clock or left asynchronous. 21.6.5 TIMER1 GATE VALUE STATUS For more information see Section19.4.1 “Comparator When Timer1 Gate Value Status is utilized, it is possible Output Synchronization”. to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON 21.6.3 TIMER1 GATE TOGGLE MODE register. The T1GVAL bit is valid even when the Timer1 When Timer1 Gate Toggle mode is enabled, it is possi- Gate is not enabled (TMR1GE bit is cleared). ble to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level 21.6.6 TIMER1 GATE EVENT INTERRUPT pulse. When Timer1 Gate Event Interrupt is enabled, it is pos- The Timer1 Gate source is routed through a flip-flop sible to generate an interrupt upon the completion of a that changes state on every incrementing edge of the gate event. When the falling edge of T1GVAL occurs, signal. See Figure21-4 for timing details. the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an Timer1 Gate Toggle mode is enabled by setting the interrupt will be recognized. T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This The TMR1GIF flag bit operates even when the Timer1 is necessary in order to control which edge is Gate is not enabled (TMR1GE bit is cleared). measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. DS40001413E-page 168  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 21.7 Timer1 Interrupt 21.9 ECCP/CCP Capture/Compare Time Base The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls The CCP1 module uses the TMR1H:TMR1L register over, the Timer1 interrupt flag bit of the PIR1 register is pair as the time base when operating in Capture or set. To enable the interrupt on rollover, you must set Compare mode. these bits: In Capture mode, the value in the TMR1H:TMR1L • TMR1ON bit of the T1CON register register pair is copied into the CCPR1H:CCPR1L • TMR1IE bit of the PIE1 register register pair on a configured event. • PEIE bit of the INTCON register In Compare mode, an event is triggered when the value • GIE bit of the INTCON register CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a The interrupt is cleared by clearing the TMR1IF bit in Special Event Trigger. the Interrupt Service Routine. For more information, see Section24.0 Note: The TMR1H:TMR1L register pair and the “Capture/Compare/PWM Modules”. TMR1IF bit should be cleared before enabling interrupts. 21.10 ECCP/CCP Special Event Trigger 21.8 Timer1 Operation During Sleep When any of the CCP’s are configured to trigger a special event, the trigger will clear the TMR1H:TMR1L Timer1 can only operate during Sleep when setup in register pair. This special event does not cause a Asynchronous Counter mode. In this mode, an external Timer1 interrupt. The CCP module may still be crystal or clock source can be used to increment the configured to generate a CCP interrupt. counter. To set up the timer to wake the device: In this mode of operation, the CCPR1H:CCPR1L • TMR1ON bit of the T1CON register must be set register pair becomes the period register for Timer1. • TMR1IE bit of the PIE1 register must be set Timer1 should be synchronized and FOSC/4 should be • PEIE bit of the INTCON register must be set selected as the clock source in order to utilize the • T1SYNC bit of the T1CON register must be set Special Event Trigger. Asynchronous operation of • TMR1CS bits of the T1CON register must be Timer1 can cause a Special Event Trigger to be configured missed. • T1OSCEN bit of the T1CON register must be In the event that a write to TMR1H or TMR1L coincides configured with a Special Event Trigger from the CCP, the write will take precedence. The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON For more information, see Section16.2.5 “Special register is set, the device will call the Interrupt Service Event Trigger”. Routine. Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 21-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2010-2015 Microchip Technology Inc. DS40001413E-page 169

PIC12(L)F1822/16(L)F1823 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 DS40001413E-page 170  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 Cleared by TMR1GIF Cleared by software Set by hardware on software falling edge of T1GVAL  2010-2015 Microchip Technology Inc. DS40001413E-page 171

PIC12(L)F1822/16(L)F1823 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 Set by hardware on Cleared by TMR1GIF Cleared by software falling edge of T1GVAL software DS40001413E-page 172  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 21.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register21-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 21-1: T1CON: TIMER1 CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 =Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC) 10 =Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 =Timer1 clock source is system clock (FOSC) 00 =Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS<1:0> = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMR1CS<1:0> = 0X This bit is ignored. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop  2010-2015 Microchip Technology Inc. DS40001413E-page 173

PIC12(L)F1822/16(L)F1823 21.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register21-2, is used to control Timer1 Gate. REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> DONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 Gate pin 01 = Timer0 overflow output 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 11 = Comparator 2 optionally synchronized output (sync_C2OUT) DS40001413E-page 174  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 21-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 213 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 169* TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 169* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 173 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 174 DONE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 175

PIC12(L)F1822/16(L)F1823 22.0 TIMER2 MODULE The Timer2 module incorporate the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP1 modules (Timer2 only) See Figure22-1 for a block diagram of Timer2. FIGURE 22-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 bit TMR2IF Output Prescaler Reset FOSC/4 TMR2 1:1, 1:4, 1:16, 1:64 2 Comparator Postscaler EQ 1:1 to 1:16 T2CKPS<1:0> PR2 4 T2OUTPS<3:0> DS40001413E-page 176  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 22.1 Timer2 Operation 22.3 Timer2 Output The clock input to the Timer2 modules is the system The unscaled output of TMR2 is available primarily to instruction clock (FOSC/4). the CCP1 module, where it is used as a time base for operations in PWM mode. TMR2 increments from 00h on each clock edge. Timer2 can be optionally used as the shift clock source A 4-bit counter/prescaler on the clock input allows direct for the MSSP1 module operating in SPI mode. input, divide-by-4 and divide-by-16 prescale options. Additional information is provided in Section25.1 These options are selected by the prescaler control bits, “Master SSP (MSSP1) Module Overview” T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on 22.4 Timer2 Operation During Sleep each clock cycle. When the two values match, the comparator generates a match signal as the timer The Timer2 timers cannot be operated while the output. This signal also resets the value of TMR2 to 00h processor is in Sleep mode. The contents of the TMR2 on the next cycle and drives the output and PR2 registers will remain unchanged while the counter/postscaler (see Section22.2 “Timer2 processor is in Sleep mode. Interrupt”). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • a write to the TMR2 register • a write to the T2CON register • Power-on Reset (POR) • Brown-out Reset (BOR) • MCLR Reset • Watchdog Timer (WDT) Reset • Stack Overflow Reset • Stack Underflow Reset • RESET Instruction Note: TMR2 is not cleared when T2CON is written. 22.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register.  2010-2015 Microchip Technology Inc. DS40001413E-page 177

PIC12(L)F1822/16(L)F1823 REGISTER 22-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 =Prescaler is 1 01 =Prescaler is 4 10 =Prescaler is 16 11 =Prescaler is 64 DS40001413E-page 178  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 89 PR2 Timer2 Module Period Register 176* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS1 T2CKPS0 178 TMR2 Holding Register for the 8-bit TMR2 Register 176* Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information.  2010-2015 Microchip Technology Inc. DS40001413E-page 179

PIC12(L)F1822/16(L)F1823 23.0 DATA SIGNAL MODULATOR Using this method, the DSM can generate the following types of Key Modulation schemes: The Data Signal Modulator (DSM) is a peripheral which • Frequency-Shift Keying (FSK) allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a • Phase-Shift Keying (PSK) modulated output. • On-Off Keying (OOK) Both the carrier and the modulator signals are supplied Additionally, the following features are provided within to the DSM module either internally, from the output of the DSM module: a peripheral, or externally through an input pin. • Carrier Synchronization The modulated output signal is generated by perform- • Carrier Source Polarity Select ing a logical “AND” operation of both the carrier and • Carrier Source Pin Disable modulator signals and then provided to the MDOUT pin. • Programmable Modulator Data The carrier signal is comprised of two distinct and • Modulator Source Pin Disable separate signals. A carrier high (CARH) signal and a • Modulated Output Polarity Select carrier low (CARL) signal. During the time in which the • Slew Rate Control modulator (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator Figure23-1 shows a Simplified Block Diagram of the signal. When the modulator signal is in a logic low Data Signal Modulator peripheral. state, the DSM mixes the carrier low signal with the modulator signal. FIGURE 23-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR MDCH<3:0> MDEN VSS 0000 MDCIN1 0001 EN MDCIN2 0010 Data Signal CLKR 0011 Modulator CCP1 0100 CCP2 0101 CARH CCP3 0110 CCP4 0111 Reserved 1000 MDCHPOL No Channel * * Selected 1111 D SYNC MDMS<3:0> Q 1 MDBIT 0000 MDMIN 0001 CCP1 0010 CCP2 0011 0 CCP3 0100 CCP4 0101 Comparator C1 0110 MOD MDCHSYNC Comparator C2 0111 MSSP1 SDO1 1000 MDOUT MSSP2 SDO2 1001 EUSART 1010 MDOPOL MDOE Reserved 0011 No Channel * * Selected 1111 D MDCL<3:0> SYNC Q 1 VSS 0000 MDCIN1 0001 MDCIN2 0010 CLKR 0011 0 CCP1 0100 CCP2 0101 CARL MDCLSYNC CCP3 0110 CCP4 0111 1000 Reserved No Channel * MDCLPOL * Selected 1111 DS40001413E-page 180  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 23.1 DSM Operation 23.3 Carrier Signal Sources The DSM module can be enabled by setting the MDEN The carrier high signal and carrier low signal can be bit in the MDCON register. Clearing the MDEN bit in the supplied from the following sources: MDCON register, disables the DSM module by auto- • CCP1 Signal matically switching the carrier high and carrier low sig- • Reference Clock Module Signal nals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON • External Signal on MDCIN1 pin register. This not only assures that the DSM module is • External Signal on MDCIN2 pin inactive, but that it is also consuming the least amount • VSS of current. The carrier high signal is selected by configuring the The values used to select the carrier high, carrier low, MDCH <3:0> bits in the MDCARH register. The carrier and modulator sources held by the Modulation Source, low signal is selected by configuring the MDCL <3:0> Modulation High Carrier, and Modulation Low Carrier bits in the MDCARL register. control registers are not affected when the MDEN bit is cleared and the DSM module is disabled. The values 23.4 Carrier Synchronization inside these registers remain unchanged while the DSM is inactive. The sources for the carrier high, During the time when the DSM switches between car- carrier low and modulator signals will once again be rier high and carrier low signal sources, the carrier data selected when the MDEN bit is set and the DSM in the modulated output signal can become truncated. module is again enabled and active. To prevent this, the carrier signal can be synchronized to the modulator signal. When synchronization is The modulated output signal can be disabled without enabled, the carrier pulse that is being mixed at the shutting down the DSM module. The DSM module will time of the transition is allowed to transition low before remain active and continue to mix signals, but the out- the DSM switches over to the next carrier source. put value will not be sent to the MDOUT pin. During the time that the output is disabled, the MDOUT pin will Synchronization is enabled separately for the carrier remain low. The modulated output can be disabled by high and carrier low signal sources. Synchronization for clearing the MDOE bit in the MDCON register. the carrier high signal can be enabled by setting the MDCHSYNC bit in the MDCARH register. Synchroniza- 23.2 Modulator Signal Sources tion for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. The modulator signal can be supplied from the Figure23-1 through Figure23-5 show timing diagrams following sources: of using various synchronization methods. • CCP1 Signal • MSSP1 SDO1 Signal (SPI mode Only) • Comparator C1 Signal • Comparator C2 Signal (PIC16(L)F1823 only) • EUSART TX Signal • External Signal on MDMIN pin • MDBIT bit in the MDCON register The modulator signal is selected by configuring the MDMS <3:0> bits in the MDSRC register.  2010-2015 Microchip Technology Inc. DS40001413E-page 181

PIC12(L)F1822/16(L)F1823 FIGURE 23-2: ON OFF KEYING (OOK) SYNCHRONIZATION Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 EXAMPLE 23-1: NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier CARH CARL CARH CARL State FIGURE 23-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 Active Carrier CARH both CARL CARH both CARL State DS40001413E-page 182  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 23-4: CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier CARH CARL CARH CARL State FIGURE 23-5: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier CARH CARL CARH CARL State  2010-2015 Microchip Technology Inc. DS40001413E-page 183

PIC12(L)F1822/16(L)F1823 23.5 Carrier Source Polarity Select 23.9 Modulated Output Polarity The signal provided from any selected input source for The modulated output signal provided on the MDOUT the carrier high and carrier low signals can be inverted. pin can also be inverted. Inverting the modulated out- Inverting the signal for the carrier high source is put signal is enabled by setting the MDOPOL bit of the enabled by setting the MDCHPOL bit of the MDCARH MDCON register. register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCARL 23.10 Slew Rate Control register. The slew rate limitation on the output port pin can be 23.6 Carrier Source Pin Disable disabled. The slew rate limitation can be removed by clearing the MDSLR bit in the MDCON register. Some peripherals assert control over their correspond- ing output pin when they are enabled. For example, 23.11 Operation in Sleep Mode when the CCP1 module is enabled, the output of CCP1 is connected to the CCP1 pin. The DSM module is not affected by Sleep mode. The DSM can still operate during Sleep, if the Carrier and This default connection to a pin can be disabled by Modulator input sources are also still operable during setting the MDCHODIS bit in the MDCARH register for Sleep. the carrier high source and the MDCLODIS bit in the MDCARL register for the carrier low source. 23.12 Effects of a Reset 23.7 Programmable Modulator Data Upon any device Reset, the Data Signal Modulator module is disabled. The user’s firmware is responsible The MDBIT of the MDCON register can be selected as for initializing the module before enabling the output. the source for the modulator signal. This gives the user The registers are reset to their default values. the ability to program the value used for modulation. 23.8 Modulator Source Pin Disable The modulator source default connection to a pin can be disabled by setting the MDMSODIS bit in the MDSRC register. DS40001413E-page 184  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 23-1: MDCON: MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R-0/0 U-0 U-0 R/W-0/0 MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output bit 6 MDOE: Modulator Module Pin Output Enable bit 1 = Modulator pin output enabled 0 = Modulator pin output disabled bit 5 MDSLR: MDOUT Pin Slew Rate Limiting bit 1 = MDOUT pin slew rate limiting enabled 0 = MDOUT pin slew rate limiting disabled bit 4 MDOPOL: Modulator Output Polarity Select bit 1 = Modulator output signal is inverted 0 = Modulator output signal is not inverted bit 3 MDOUT: Modulator Output bit Displays the current output value of the Modulator module.(1) bit 2-1 Unimplemented: Read as ‘0’ bit 0 MDBIT: Allows software to manually set modulation source input to module(2) 1 = Modulator uses High Carrier source 0 = Modulator uses Low Carrier source Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. 2: MDBIT must be selected as the modulation source in the MDSRC register for this operation.  2010-2015 Microchip Technology Inc. DS40001413E-page 185

PIC12(L)F1822/16(L)F1823 REGISTER 23-2: MDSRC: MODULATION SOURCE CONTROL REGISTER R/W-x/u U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDMSODIS — — — MDMS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDMSODIS: Modulation Source Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3-0 MDMS<3:0> Modulation Source Selection bits 1111 = Reserved. No channel connected. 1110 = Reserved. No channel connected. 1101 = Reserved. No channel connected. 1100 = Reserved. No channel connected. 1011 = Reserved. No channel connected. 1010 = EUSART TX output 1001 = Reserved. No channel selected. 1000 = MSSP1 SDO1 output 0111 = Comparator 2 output (PIC16(L)F1823 only. PIC12(L)F1822; Reserved, no channel connected.) 0110 = Comparator 1 output 0101 = Reserved. No channel connected. 0100 = Reserved. No channel connected. 0011 = Reserved. No channel connected. 0010 = CCP1 output (PWM Output mode only) 0001 = MDMIN port pin 0000 = MDBIT bit of MDCON register is modulation source Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. DS40001413E-page 186  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 23-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCHODIS MDCHPOL MDCHSYNC — MDCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCHODIS: Modulator High Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is enabled bit 6 MDCHPOL: Modulator High Carrier Polarity Select bit 1 = Selected high carrier signal is inverted 0 = Selected high carrier signal is not inverted bit 5 MDCHSYNC: Modulator High Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 = Modulator Output is not synchronized to the high time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 MDCH<3:0> Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. • • • 0101 = Reserved. No channel connected. 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal (CLKR) 0010 = MDCIN2 port pin 0001 = MDCIN1 port pin 0000 = VSS Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.  2010-2015 Microchip Technology Inc. DS40001413E-page 187

PIC12(L)F1822/16(L)F1823 REGISTER 23-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCLODIS MDCLPOL MDCLSYNC — MDCL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is enabled bit 6 MDCLPOL: Modulator Low Carrier Polarity Select bit 1 = Selected low carrier signal is inverted 0 = Selected low carrier signal is not inverted bit 5 MDCLSYNC: Modulator Low Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 = Modulator Output is not synchronized to the low time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 MDCL<3:0> Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. • • • 0101 = Reserved. No channel connected. 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal 0010 = Reserved. No channel connected. 0001 = MDCIN1 port pin 0000 = VSS Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. DS40001413E-page 188  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 ANSELC(1) — — — — ANSC3 ANSC2 ANSC1 ANSC0 122 MDCARH MDCHODIS MDCHPOL MDCHSYNC — MDCH<3:0> 187 MDCARL MDCLODIS MDCLPOL MDCLSYNC — MDCL<3:0> 188 MDCON MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT 185 MDSRC MDMSODIS — — — MDMS<3:0> 186 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 119 WPUC(1) — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 122 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode. Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 189

PIC12(L)F1822/16(L)F1823 24.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains one Enhanced Capture/ Compare/PWM module (ECCP1). The Full-Bridge ECCP module has four available I/O pins, while the Half-Bridge ECCP module only has two. See Table24-1. TABLE 24-1: PWM RESOURCES Device Name ECCP1 PIC12(L)F1822 Enhanced PWM Half-Bridge PIC16(L)F1823 Enhanced PWM Full-Bridge DS40001413E-page 190  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 24.1 Capture Mode 24.1.2 TIMER1 MODE RESOURCE Capture mode makes use of the 16-bit Timer1 Timer1 must be running in Timer mode or Synchronized resource. When an event occurs on the CCP1 pin, the Counter mode for the CCP1 module to use the capture 16-bit CCPR1H:CCPR1L register pair captures and feature. In Asynchronous Counter mode, the capture stores the 16-bit value of the TMR1H:TMR1L register operation may not work. pair, respectively. An event is defined as one of the See Section21.0 “Timer1 Module with Gate Control” following and is configured by the CCP1M<3:0> bits of for more information on configuring Timer1. the CCP1CON register: 24.1.3 SOFTWARE INTERRUPT MODE • Every falling edge • Every rising edge When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the • Every 4th rising edge CCP1IE interrupt enable bit of the PIE1 register clear to • Every 16th rising edge avoid false interrupts. Additionally, the user should When a capture is made, the Interrupt Request Flag bit clear the CCP1IF interrupt flag bit of the PIR1 register CCP1IF of the PIR1 register is set. The interrupt flag following any change in Operating mode. must be cleared in software. If another capture occurs Note: Clocking Timer1 from the system clock before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new (FOSC) should not be used in Capture mode. In order for Capture mode to captured value. recognize the trigger event on the CCP1 Figure24-1 shows a simplified diagram of the Capture pin, Timer1 must be clocked from the operation. instruction clock (FOSC/4) or from an external clock source. 24.1.1 CCP1 PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured 24.1.4 CCP1 PRESCALER as an input by setting the associated TRIS control bit. There are four prescaler settings specified by the Also, the CCP1 pin function may be moved to CCP1M<3:0> bits of the CCP1CON register. alternative pins using the APFCON register. Refer to Whenever the CCP1 module is turned off, or the CCP1 Section12.1 “Alternate Pin Function” for more module is not in Capture mode, the prescaler counter details. is cleared. Any Reset will clear the prescaler counter. Note: If the CCP1 pin is configured as an output, Switching from one capture prescaler to another does not a write to the port can cause a capture clear the prescaler and may generate a false interrupt. To condition. avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the FIGURE 24-1: CAPTURE MODE prescaler. Example24-1 demonstrates the code to OPERATION BLOCK perform this function. DIAGRAM EXAMPLE 24-1: CHANGING BETWEEN Set Flag bit CCP1IF CAPTURE PRESCALERS (PIR1 register) Prescaler  1, 4, 16 BANKSELCCP1CON ;Set Bank bits to point CCP1 CCPR1H CCPR1L ;to CCP1CON pin CLRF CCP1CON ;Turn CCP1 module off MOVLW NEW_CAPT_PS;Load the W reg with and Capture Edge Detect Enable ;the new prescaler ;move value and CCP1 ON TMR1H TMR1L MOVWF CCP1CON ;Load CCP1CON with this CCP1M<3:0> ;value System Clock (FOSC)  2010-2015 Microchip Technology Inc. DS40001413E-page 191

PIC12(L)F1822/16(L)F1823 24.1.5 CAPTURE DURING SLEEP 24.1.6 ALTERNATE PIN LOCATIONS Capture mode depends upon the Timer1 module for This module incorporates I/O pins that can be moved to proper operation. There are two options for driving the other locations with the use of the alternate pin function Timer1 module in Capture mode. It can be driven by the register, APFCON. To determine which pins can be instruction clock (FOSC/4), or by an external clock source. moved and what their default locations are upon a Reset, see Section12.1 “Alternate Pin Function” for When Timer1 is clocked by FOSC/4, Timer1 will not more information. increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(2) CCP1SEL(2) 114 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 213 CCPR1L Capture/Compare/PWM Register x Low Byte (LSB) 191 CCPR1H Capture/Compare/PWM Register x High Byte (MSB) 191 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 173 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 174 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 169 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 169 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode. Note 1: PIC16(L)F1823 only. 2: PIC12(L)F1822 only. DS40001413E-page 192  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 24.2 Compare Mode 24.2.2 TIMER1 MODE RESOURCE Compare mode makes use of the 16-bit Timer1 In Compare mode, Timer1 must be running in either resource. The 16-bit value of the CCPR1H:CCPR1L Timer mode or Synchronized Counter mode. The register pair is constantly compared against the 16-bit compare operation may not work in Asynchronous value of the TMR1H:TMR1L register pair. When a Counter mode. match occurs, one of the following events can occur: See Section21.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. • Toggle the CCP1 output • Set the CCP1 output Note: Clocking Timer1 from the system clock • Clear the CCP1 output (FOSC) should not be used in Compare mode. In order for Compare mode to • Generate a Special Event Trigger recognize the trigger event on the CCP1 • Generate a Software Interrupt pin, TImer1 must be clocked from the The action on the pin is based on the value of the instruction clock (FOSC/4) or from an CCP1M<3:0> control bits of the CCP1CON register. At external clock source. the same time, the interrupt flag CCP1IF bit is set. All Compare modes can generate an interrupt. 24.2.3 SOFTWARE INTERRUPT MODE Figure24-2 shows a simplified diagram of the When Generate Software Interrupt mode is chosen Compare operation. (CCP1M<3:0>=1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON FIGURE 24-2: COMPARE MODE register). OPERATION BLOCK 24.2.4 SPECIAL EVENT TRIGGER DIAGRAM When Special Event Trigger mode is chosen CCP1M<3:0> (CCP1M<3:0>=1011), the CCP1 module does the Mode Select following: Set CCP1IF Interrupt Flag • Resets Timer1 (PIR1) CCP1 4 • Starts an ADC conversion if ADC is enabled Pin CCPR1H CCPR1L The CCP1 module does not assert control of the CCP1 Q S Output Comparator pin in this mode. Logic Match R The Special Event Trigger output of the CCP1 occurs TMR1H TMR1L immediately upon a match between the TMR1H, TRIS TMR1L register pair and the CCPR1H, CCPR1L regis- Output Enable ter pair. The TMR1H, TMR1L register pair is not reset Special Event Trigger until the next rising edge of the Timer1 clock. The Spe- cial Event Trigger output starts an A/D conversion (if the A/D module is enabled). This allows the CCPR1H, 24.2.1 CCP1 PIN CONFIGURATION CCPR1L register pair to effectively provide a 16-bit The user must configure the CCP1 pin as an output by programmable period register for Timer1. clearing the associated TRIS bit. TABLE 24-3: SPECIAL EVENT TRIGGER Also, the CCP1 pin function may be moved to Device CCP1/ECCP1 alternative pins using the APFCON register. Refer to Section12.1 “Alternate Pin Function” for more PIC12(L)F1822/16(L)F1823 CCP1 details. Refer to Section16.0 “Analog-to-Digital Converter Note: Clearing the CCP1CON register will force (ADC) Module” for more information. the CCP1 compare output latch to the Note1: The Special Event Trigger from the CCP default low level. This is not the PORT I/O module does not set interrupt flag bit data latch. TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.  2010-2015 Microchip Technology Inc. DS40001413E-page 193

PIC12(L)F1822/16(L)F1823 24.2.5 COMPARE DURING SLEEP 24.2.6 ALTERNATE PIN LOCATIONS The Compare mode is dependent upon the system This module incorporates I/O pins that can be moved to clock (FOSC) for proper operation. Since FOSC is shut other locations with the use of the alternate pin function down during Sleep mode, the Compare mode will not register, APFCON. To determine which pins can be function properly during Sleep. moved and what their default locations are upon a Reset, see Section12.1 “Alternate Pin Function” for more information. TABLE 24-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(2) CCP1SEL(2) 114 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 213 CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) 191 CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) 191 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 173 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 174 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 169 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 169 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode. Note 1: PIC16(L)F1823 only. 2: PIC12(L)F1822 only. DS40001413E-page 194  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 24.3 PWM Overview FIGURE 24-3: CCP1 PWM OUTPUT SIGNAL Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between Period fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is Pulse Width considered the on state and the low portion of the signal TMR2 = PR2 is considered the off state. The high portion, also known TMR2 = CCPR1H:CCP1CON<5:4> as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which TMR2 = 0 lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which FIGURE 24-4: SIMPLIFIED PWM BLOCK shortens the pulse width, supplies less power. The DIAGRAM PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. CCP1CON<5:4> PWM resolution defines the maximum number of steps Duty Cycle Registers that can be present in a single PWM period. A higher CCPR1L resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. The term duty cycle describes the proportion of the on CCPR1H(2) (Slave) time to the off time and is expressed in percentages, CCP1 where 0% is fully off and 100% is fully on. A lower duty Comparator R Q cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. S TMR2 (1) Figure24-3 shows a typical waveform of the PWM TRIS signal. Comparator 24.3.1 STANDARD PWM OPERATION Clear Timer, toggle CCP1 pin and latch duty cycle The standard PWM mode generates a Pulse-Width PR2 modulation (PWM) signal on the CCP1 pin with up to 10 Note 1: The 8-bit timer TMR2 register is concatenated bits of resolution. The period, duty cycle, and resolution with the 2-bit internal system clock (FOSC), or are controlled by the following registers: two bits of the prescaler, to create the 10-bit • PR2 registers time base. • T2CON registers 2: In PWM mode, CCPR1H is a read-only register. • CCPR1L registers • CCP1CON registers Figure24-4 shows a simplified block diagram of PWM operation. Note1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCP1 pin. 2: Clearing the CCP1CON register will relinquish control of the CCP1 pin.  2010-2015 Microchip Technology Inc. DS40001413E-page 195

PIC12(L)F1822/16(L)F1823 24.3.2 SETUP FOR PWM OPERATION When TMR2 is equal to PR2, the following three events occur on the next increment cycle: The following steps should be taken when configuring the CCP1 module for standard PWM operation: • TMR2 is cleared • The CCP1 pin is set. (Exception: If the PWM duty 1. Disable the CCP1 pin output driver by setting cycle=0%, the pin will not be set.) the associated TRIS bit. 2. Load the PR2 register with the PWM period • The PWM duty cycle is latched from CCPR1L into value. CCPR1H. 3. Configure the CCP1 module for the PWM mode by loading the CCP1CON register with the Note: The Timer postscaler (see Section22.1 “Timer2 Operation”) is not used in the appropriate values. determination of the PWM frequency. 4. Load the CCPR1L register and the DC1B1 bits of the CCP1CON register, with the PWM duty 24.3.4 PWM DUTY CYCLE cycle value. The PWM duty cycle is specified by writing a 10-bit 5. Configure and start Timer2: value to multiple registers: CCPR1L register and • Clear the TMR2IF interrupt flag bit of the DC1B<1:0> bits of the CCP1CON register. The PIR1 register. See Note below. CCPR1L contains the eight MSbs and the DC1B<1:0> • Configure the T2CKPS bits of the T2CON bits of the CCP1CON register contain the two LSbs. register with the Timer prescale value. CCPR1L and DC1B<1:0> bits of the CCP1CON • Enable the Timer by setting the TMR2ON register can be written to at any time. The duty cycle bit of the T2CON register. value is not latched into CCPR1H until after the period 6. Enable PWM output pin: completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H • Wait until the Timer overflows and the register is read-only. TMR2IF bit of the PIR1 register is set. See Note below. Equation24-2 is used to calculate the PWM pulse • Enable the CCP1 pin output driver by clear- width. ing the associated TRIS bit. Equation24-3 is used to calculate the PWM duty cycle Note: In order to send a complete duty cycle and ratio. period on the first PWM output, the above steps must be included in the setup EQUATION 24-2: PULSE WIDTH sequence. If it is not critical to start with a complete PWM signal on the first output, Pulse Width = CCPR1L:CCP1CON<5:4>  then step 6 may be ignored. TOSC  (TMR2 Prescale Value) 24.3.3 PWM PERIOD The PWM period is specified by the PR2 register of EQUATION 24-3: DUTY CYCLE RATIO Timer2. The PWM period can be calculated using the formula of Equation24-1. CCPRxL:CCPxCON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------- 4PRx+1 EQUATION 24-1: PWM PERIOD PWM Period = PR2+14TOSC The CCPR1H register and a 2-bit internal latch are (TMR2 Prescale Value) used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. Note 1: TOSC = 1/FOSC The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (see Figure24-4). DS40001413E-page 196  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 24.3.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation24-4. EQUATION 24-4: PWM RESOLUTION log4PR2+1 Resolution = ------------------------------------------ bits log2 Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. TABLE 24-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz) PWM Frequency 1.95 kHz 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 24-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 24-7: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5  2010-2015 Microchip Technology Inc. DS40001413E-page 197

PIC12(L)F1822/16(L)F1823 24.3.6 OPERATION IN SLEEP MODE 24.3.9 ALTERNATE PIN LOCATIONS In Sleep mode, the TMR2register will not increment This module incorporates I/O pins that can be moved to and the state of the module will not change. If the CCP1 other locations with the use of the alternate pin function pin is driving a value, it will continue to drive that value. register, APFCON. To determine which pins can be When the device wakes up, TMR2 will continue from its moved and what their default locations are upon a previous state. Reset, see Section12.1 “Alternate Pin Function” for more information. 24.3.7 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. 24.3.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. TABLE 24-8: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(2) CCP1SEL(2) 114 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 213 CCPR1L Capture/Compare/PWM Register x Low Byte (LSB) 191 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 PR2 Timer2 Period Register 176* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<:0>1 178 TMR2 Timer2 Module Register 176* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. Note 1: PIC16(L)F1823 only. 2: PIC12(L)F1822 only. DS40001413E-page 198  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 24.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the The enhanced PWM mode generates a Pulse-Width PWM pins is configurable and is selected by setting the Modulation (PWM) signal on up to four different output bits CCP1M<3:0> in the CCP1CON register pins with up to 10 bits of resolution. The period, duty appropriately. cycle, and resolution are controlled by the following Figure24-5 shows an example of a simplified block registers: diagram of the Enhanced PWM module. • PR2 registers Table24-9 shows the pin assignments for various • T2CON registers Enhanced PWM modes. • CCPR1L registers Note 1: The corresponding TRIS bit must be • CCP1CON registers cleared to enable the PWM output on the The ECCP modules have the following additional PWM CCP1 pin. registers which control Auto-shutdown, Auto-restart, 2: Clearing the CCP1CON register will Dead-band Delay and PWM Steering modes: relinquish control of the CCP1 pin. • CCP1AS registers 3: Any pin not used in the enhanced PWM • PSTR1CON registers mode is available for alternate pin • PWM1CON registers functions, if applicable. The enhanced PWM module can generate the following 4: To prevent the generation of an four PWM Output modes: incomplete waveform when the PWM is • Single PWM first enabled, the ECCP module waits until the start of a new PWM period • Half-Bridge PWM before generating a PWM signal. • Full-Bridge PWM (PIC16(L)F1823 only) • Single PWM with PWM Steering mode To select an Enhanced PWM Output mode, the P1M bits of the CCP1CON register must be configured appropriately. FIGURE 24-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DC1B<1:0> P1M<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L CCP1/P1A CCP1/P1A TRISx CCPR1H (Slave) P1B P1B Output TRISx Comparator R Q Controller P1C(2) P1C(2) TMR2 (1) S TRISx P1D(2) P1D(2) Comparator Clear Timer, TRISx toggle PWM pin and latch duty cycle PR2 PWM1CON Note 1: The 8-bit timer TMR1 register is concatenated with the 2-bit internal Q clock, or two bits of the prescaler to create the 10-bit time base. 2: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 199

PIC12(L)F1822/16(L)F1823 TABLE 24-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode P1M<1:0> CCP1/P1A P1B P1C(2) P1D(2) Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward(2) 01 Yes Yes Yes Yes Full-Bridge, Reverse(2) 11 Yes Yes Yes Yes Note 1: PWM Steering enables outputs in Single mode. 2: PIC16(L)F1823 only. FIGURE 24-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse PRX+1 PxM<1:0> Signal 0 Width Period 00 (Single Output) PxA Modulated Delay Delay PxA Modulated 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>) DS40001413E-page 200  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 24-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal 0 Pulse PRx+1 Width Period 00 (Single Output) PxA Modulated PxA Modulated Delay Delay 10 (Half-Bridge) PxB Modulated PxA Active (Full-Bridge, PxB Inactive 01 Forward) PxC Inactive PxD Modulated PxA Inactive (Full-Bridge, PxB Modulated 11 Reverse) PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON<6:0>)  2010-2015 Microchip Technology Inc. DS40001413E-page 201

PIC12(L)F1822/16(L)F1823 24.4.1 HALF-BRIDGE MODE Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must In Half-Bridge mode, two pins are used as outputs to be cleared to configure P1A and P1B as outputs. drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM FIGURE 24-8: EXAMPLE OF HALF- output signal is output on the P1B pin (see Figure24-9). BRIDGE PWM OUTPUT This mode can be used for Half-Bridge applications, as shown in Figure24-9, or for Full-Bridge applications, Period Period where four power switches are being modulated with two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay P1A(2) can be used to prevent shoot-through current in Half- td Bridge power devices. The value of the PDC<6:0> bits of td the PWM1CON register sets the number of instruction P1B(2) cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output (1) (1) (1) remains inactive during the entire cycle. See Section24.4.5 “Programmable Dead-Band Delay td = Dead-Band Delay Mode” for more details of the dead-band delay Note 1: At this time, the TMR2 register is equal to the operations. PR2 register. 2: Output signals are shown as active-high. FIGURE 24-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A - Load FET Driver + P1B - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver P1A Load FET FET Driver Driver P1B DS40001413E-page 202  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 24.4.2 FULL-BRIDGE MODE (PIC16(L)F1823 ONLY) In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure24-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure24-11. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure24-11. P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 24-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D  2010-2015 Microchip Technology Inc. DS40001413E-page 203

PIC12(L)F1822/16(L)F1823 FIGURE 24-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS40001413E-page 204  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 24.4.2.1 Direction Change in Full-Bridge The Full-Bridge mode does not provide dead-band Mode delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation In the Full-Bridge mode, the P1M1 bit in the CCP1CON where dead-band delay is required. This situation register allows users to control the forward/reverse occurs when both of the following conditions are true: direction. When the application firmware changes this direction control bit, the module will change to the new 1. The direction of the PWM output changes when direction on the next PWM cycle. the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including A direction change is initiated in software by changing the power device and driver circuit, is greater the P1M1 bit of the CCP1CON register. The following than the turn-on time. sequence occurs four Timer cycles prior to the end of the current PWM period: Figure24-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty • The modulated outputs (P1B and P1D) are placed cycle. In this example, at time t1, the output P1A and in their inactive state. P1D become inactive, while output P1C becomes • The associated unmodulated outputs (P1A and active. Since the turn off time of the power devices is P1C) are switched to drive in the opposite longer than the turn on time, a shoot-through current direction. will flow through power devices QC and QD (see • PWM modulation resumes at the beginning of the Figure24-10) for the duration of ‘t’. The same next period. phenomenon will occur to power devices QA and QB See Figure24-12 for an illustration of this sequence. for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 24-12: EXAMPLE OF PWM DIRECTION CHANGE Signal Period(1) Period P1A (Active-High) P1B (Active-High) Pulse Width P1C (Active-High) (2) P1D (Active-High) Pulse Width Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer counts.  2010-2015 Microchip Technology Inc. DS40001413E-page 205

PIC12(L)F1822/16(L)F1823 FIGURE 24-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential T = TOFF – TON Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver. DS40001413E-page 206  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 24.4.3 ENHANCED PWM AUTO- SHUTDOWN MODE Note1: The auto-shutdown condition is a level- The PWM mode supports an Auto-Shutdown mode that based signal, not an edge-based signal. will disable the PWM outputs when an external As long as the level is present, the auto- shutdown event occurs. Auto-Shutdown mode places shutdown will persist. the PWM output pins into a predetermined state. This 2: Writing to the CCP1ASE bit is disabled mode is used to help prevent the PWM from damaging while an auto-shutdown condition the application. persists. The auto-shutdown sources are selected using the 3: Once the auto-shutdown condition has CCP1AS<2:0> bits of the CCP1AS register. A shutdown been removed and the PWM restarted event may be generated by: (either through firmware or auto-restart) • A logic ‘0’ on the FLT0 pin the PWM signal will always restart at the • A logic ‘1’ on a Comparator (C1) output beginning of the next PWM period. A shutdown condition is indicated by the CCP1ASE 4: Prior to an auto-shutdown event caused (Auto-Shutdown Event Status) bit of the CCP1AS by a comparator output or FLT0 pin event, register. If the bit is a ‘0’, the PWM pins are operating a software shutdown can be triggered in normally. If the bit is a ‘1’, the PWM outputs are in the firmware by setting the CCP1ASE bit of shutdown state. the CCP1AS register to ‘1’. The auto- restart feature tracks the active status of When a shutdown event occurs, two things happen: a shutdown caused by a comparator out- The CCP1ASE bit is set to ‘1’. The CCP1ASE will put or FLT0 pin event only. If it is enabled remain set until cleared in firmware or an auto-restart at this time, it will immediately clear this occurs (see Section24.4.4 “Auto-Restart Mode”). bit and restart the ECCP module at the The enabled PWM pins are asynchronously placed in beginning of the next PWM period. their shutdown states. The PWM output pins are grouped into pairs [P1A/P1C] and [P1B/P1D]. The state of each pin pair is determined by the PSS1AC and PSS1BD bits of the CCP1AS register. Each pin pair may be placed into one of three states: • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) FIGURE 24-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (P1RSEN = 0) Missing Pulse Missing Pulse (Auto-Shutdown) (CCP1ASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent CCP1ASE bit PWM Shutdown Shutdown Resumes Event Occurs Event Clears CCP1ASE Cleared by Firmware  2010-2015 Microchip Technology Inc. DS40001413E-page 207

PIC12(L)F1822/16(L)F1823 24.4.4 AUTO-RESTART MODE The Enhanced PWM can be configured to automati- cally restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the P1RSEN bit in the PWM1CON register. If auto-restart is enabled, the CCP1ASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCP1ASE bit will be cleared via hardware and normal operation will resume. FIGURE 24-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART (P1RSEN = 1) Missing Pulse Missing Pulse (Auto-Shutdown) (CCP1ASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent CCP1ASE bit PWM Shutdown Resumes Event Occurs Shutdown CCP1ASE Event Clears Cleared by Hardware DS40001413E-page 208  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 24.4.5 PROGRAMMABLE DEAD-BAND FIGURE 24-16: EXAMPLE OF HALF- DELAY MODE BRIDGE PWM OUTPUT In Half-Bridge applications where all power switches Period Period are modulated at the PWM frequency, the power Pulse Width switches normally require more time to turn off than to turn on. If both the upper and lower power switches are P1A(2) switched at the same time (one turned on, and the td other turned off), both switches may be on for a short td period of time until one switch completely turns off. P1B(2) During this brief interval, a very high current (shoot- through current) will flow through both power switches, (1) (1) (1) shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during td = Dead-Band Delay switching, turning on either of the power switches is normally delayed to allow the other switch to Note 1: At this time, the TMR2 register is equal to the completely turn off. PR2 register. In Half-Bridge mode, a digitally programmable dead- 2: Output signals are shown as active-high. band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure24-16 for illustration. The lower seven bits of the associated PWM1CON register (Register24-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 24-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A V - Load FET Driver + P1B V - V-  2010-2015 Microchip Technology Inc. DS40001413E-page 209

PIC12(L)F1822/16(L)F1823 24.4.6 PWM STEERING MODE FIGURE 24-18: SIMPLIFIED STEERING BLOCK DIAGRAM In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the STR1A same PWM signal can be simultaneously available on multiple pins. P1A Signal P1A pin CCP1M1 1 Once the Single Output mode is selected (CCP1M<3:2>=11 and P1M<1:0>=00 of the PORT Data CCP1CON register), the user firmware can bring out 0 TRIS the same PWM signal to one, two, three or four output STR1B pins by setting the appropriate STR1 bits of the PSTR1CON register, as shown in Table24-9. CCP1M0 1 P1B pin Note: The associated TRIS bits must be set to PORT Data output (‘0’) to enable the pin output driver 0 TRIS in order to see the PWM signal on the pin. STR1C While the PWM Steering mode is active, the P1C pin(3) CCP1M<1:0> bits of the CCP1CON register determine CCP1M1 1 the polarity of the output pins. PORT Data 0 The PWM auto-shutdown operation also applies to TRIS PWM Steering mode as described in Section24.4.3 STR1D “Enhanced PWM Auto-shutdown mode”. An auto- shutdown event will only affect pins that have PWM P1D pin(3) CCP1M0 1 outputs enabled. PORT Data 0 TRIS Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0>=00 and CCP1M<3:2>=11. 2: Single PWM output requires setting at least one of the STR1 bits. 3: PIC16(L)F1823 only. DS40001413E-page 210  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 24.4.6.1 Steering Synchronization drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are The STR1SYNC bit of the PSTR1CON register gives enable is not recommended since it may result in the user two selections of when the steering event will damage to the application circuits. happen. When the STR1SYNC bit is ‘0’, the steering event will happen at the end of the instruction that The P1A, P1B, P1C and P1D output latches may not be writes to the PSTR1CON register. In this case, the in the proper states when the PWM module is output signal at the output pins may be an incomplete initialized. Enabling the PWM pin output drivers at the PWM waveform. This operation is useful when the user same time as the Enhanced PWM modes may cause firmware needs to immediately remove a PWM signal damage to the application circuit. The Enhanced PWM from the pin. modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM When the STR1SYNC bit is ‘1’, the effective steering pin output drivers. The completion of a full PWM cycle update will happen at the beginning of the next PWM is indicated by the TMR2IF bit of the PIR1 register period. In this case, steering on/off the PWM output will being set as the second PWM period begins. always produce a complete PWM waveform. Note: When the microcontroller is released from Figures24-19 and24-20 illustrate the timing diagrams Reset, all of the I/O pins are in the high- of the PWM steering depending on the STR1SYNC impedance state. The external circuits setting. must keep the power switch devices in the 24.4.7 START-UP CONSIDERATIONS Off state until the microcontroller drives the I/O pins with the proper signal levels or When any PWM mode is used, the application activates the PWM output(s). hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. The CCP1M<1:0> bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pin output FIGURE 24-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STR1SYNC = 0) PWM Period PWM STR1 P1<D:A> PORT Data PORT Data P1n = PWM FIGURE 24-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STR1SYNC = 1) PWM STR1 P1<D:A> PORT Data PORT Data P1n = PWM  2010-2015 Microchip Technology Inc. DS40001413E-page 211

PIC12(L)F1822/16(L)F1823 24.4.8 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a reset, see Section12.1 “Alternate Pin Function” for more information. TABLE 24-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(2) CCP1SEL(2) 114 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 213 CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 214 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 PR2 Timer2 Period Register 176* PSTR1CON — — — STR1SYNC STR1D(1) STR1C(1) STR1B STR1A 216 PWM1CON P1RSEN P1DC<6:0> 215 T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<:0>1 178 TMR2 Timer2 Module Register 176* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. Note 1: PIC16(L)F1823 only. 2: PIC12(L)F1822 only. DS40001413E-page 212  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 24-1: CCP1CON: CCP1 CONTROL REGISTER R/W-00 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 P1M<1:0>(1) DC1B<1:0> CCP1M<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 P1M<1:0>: Enhanced PWM Output Configuration bits(1) Capture mode: Unused Compare mode: Unused PWM mode: If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins(1) If CCP1M<3:2> = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive(1) 10 = Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive(1) bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: ECCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP1 module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize ECCP1 pin low; set output on compare match (set CCP1IF) 1001 = Compare mode: initialize ECCP1 pin high; clear output on compare match (set CCP1IF) 1010 = Compare mode: generate software interrupt only; ECCP1 pin reverts to I/O state 1011 = Compare mode: Special Event Trigger (CCP1 resets Timer, sets CCP1IF bit, and starts A/D conversion if A/D module is enabled) PWM mode: 1100 = PWM mode: P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode: P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode: P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode: P1A, P1C active-low; P1B, P1D active-low Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 213

PIC12(L)F1822/16(L)F1823 REGISTER 24-2: CCP1AS: CCP1 AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP1ASE: CCP1 Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; CCP1 outputs are in shutdown state 0 = CCP1 outputs are operating bit 6-4 CCP1AS<2:0>: CCP1 Auto-Shutdown Source Select bits 000 =Auto-shutdown is disabled 001 =Comparator C1 output high(1) 010 =Comparator C2 output high(1, 2) 011 =Either Comparator C1 or C2 high(1, 2) 100 =VIL on FLT0 pin 101 =VIL on FLT0 pin or Comparator C1 high(1) 110 =VIL on FLT0 pin or Comparator C2 high(1, 2) 111 =VIL on FLT0 pin or Comparator C1 or Comparator C2 high(1, 2) bit 3-2 PSS1AC<1:0>: Pins P1A and P1C Shutdown State Control bits(2) 00 = Drive pins P1A and P1C to ‘0’ 01 = Drive pins P1A and P1C to ‘1’ 1x = Pins P1A and P1C tri-state bit 1-0 PSS1BD<1:0>: Pins P1B and P1D Shutdown State Control bits(2) 00 = Drive pins P1B and P1D to ‘0’ 01 = Drive pins P1B and P1D to ‘1’ 1x = Pins P1B and P1D tri-state Note 1: If C1SYNC is enabled, the shutdown will be delayed by Timer1. 2: C2, P1C and P1D available on PIC16(L)F1823 only. DS40001413E-page 214  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 24-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 P1RSEN P1DC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 P1RSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCP1ASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, CCP1ASE must be cleared in software to restart the PWM bit 6-0 P1DC<6:0>: PWM Delay Count bits P1DC1 =Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled.  2010-2015 Microchip Technology Inc. DS40001413E-page 215

PIC12(L)F1822/16(L)F1823 REGISTER 24-4: PSTR1CON: PWM STEERING CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 — — — STR1SYNC STR1D STR1C STR1B STR1A bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STR1SYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STR1D: Steering Enable bit D(2) 1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1D pin is assigned to port pin bit 2 STR1C: Steering Enable bit C(2) 1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1C pin is assigned to port pin bit 1 STR1B: Steering Enable bit B 1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1B pin is assigned to port pin bit 0 STR1A: Steering Enable bit A 1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2>=11 and P1M<1:0>=00. 2: PIC16(L)F1823 only. DS40001413E-page 216  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 25.0 MASTER SYNCHRONOUS SERIAL PORT MODULE 25.1 Master SSP (MSSP1) Module Overview The Master Synchronous Serial Port (MSSP1) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc. The MSSP1 module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) The SPI interface supports the following modes and features: • Master mode • Slave mode • Clock Parity • Slave Select Synchronization (Slave mode only) • Daisy-chain connection of slave devices Figure25-1 is a block diagram of the SPI interface module. FIGURE 25-1: MSSP1 BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSP1BUF Reg SDI SSP1SR Reg SDO bit 0 Shift Clock SS SS Control 2 (CKP, CKE) Enable Clock Select Edge Select SSP1M<3:0> 4 ( T M R 2 O u tp u t ) 2 SCK Edge Prescaler TOSC Select 4, 16, 64 Baud rate generator TRIS bit (SSP1ADD)  2010-2015 Microchip Technology Inc. DS40001413E-page 217

PIC12(L)F1822/16(L)F1823 The I2C interface supports the following modes and features: • Master mode • Slave mode • Byte NACKing (Slave mode) • Limited Multi-master support • 7-bit and 10-bit addressing • Start and Stop interrupts • Interrupt masking • Clock stretching • Bus collision detection • General call address matching • Address masking • Address Hold and Data Hold modes • Selectable SDA hold times Figure25-2 is a block diagram of the I2C interface mod- ule in Master mode. Figure25-3 is a diagram of the I2C interface module in Slave mode. FIGURE 25-2: MSSP1 BLOCK DIAGRAM (I2C™ MASTER MODE) Internal data bus [SSP1M 3:0] Read Write SSP1BUF Baud rate generator (SSP1ADD) SDA Shift SDA in Clock SSP1SR ct e Enable (RCEN) GMeSnSbetAararcttk ebn i(otS,w SSletPod1pgC ebOitL,NS2b) Clock Cntl arbitrate/BCOL det d off clock source) SCL ceive Clock (Hol e R Start bit detect, Stop bit detect SCL in Write collision detect Set/Reset: S, P, SSP1STAT, WCOL, SSP1OV Clock arbitration Reset SEN, PEN (SSP1CON2) Bus Collision State counter for Set SSP1IF, BCL1IF end of XMIT/RCV Address Match detect DS40001413E-page 218  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 25-3: MSSP1 BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSP1BUF Reg SCL Shift Clock SSP1SR Reg SDA MSb LSb SSP1MSK Reg Match Detect Addr Match SSP1ADD Reg Start and Set, Reset Stop bit Detect S, P bits (SSP1STAT Reg)  2010-2015 Microchip Technology Inc. DS40001413E-page 219

PIC12(L)F1822/16(L)F1823 25.2 SPI Mode Overview saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register The Serial Peripheral Interface (SPI) bus is a (on its SDO pin) and the master device is reading this synchronous serial data communication bus that bit and saving it as the LSb of its shift register. operates in Full Duplex mode. Devices communicate in After eight bits have been shifted out, the master and a master/slave environment where the master device slave have exchanged register values. initiates the communication. A slave device is controlled through a chip select known as Slave Select. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. The SPI bus specifies four signal connections: Whether the data is meaningful or not (dummy data), • Serial Clock (SCK) depends on the application software. This leads to • Serial Data Out (SDO) three scenarios for data transmission: • Serial Data In (SDI) • Master sends useful data and slave sends dummy • Slave Select (SS) data. Figure25-1 shows the block diagram of the MSSP1 • Master sends useful data and slave sends useful module when operating in SPI mode. data. The SPI bus operates with a single master device and • Master sends dummy data and slave sends useful one or more slave devices. When multiple slave data. devices are used, an independent Slave Select con- Transmissions may involve any number of clock nection is required from the master device to each cycles. When there is no more data to be transmitted, slave device. the master stops sending the clock signal and it Figure25-4 shows a typical connection between a deselects the slave. master device and multiple slave devices. Every slave device connected to the bus that has not The master selects only one slave at a time. Most slave been selected through its slave select line must disre- devices have tri-state outputs so their output signal gard the clock and transmission signals and must not appears disconnected from the bus when they are not transmit out any data of its own. selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure25-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the pro- grammed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits infor- mation out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polar- ity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. During each SPI clock cycle, a full duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDO pin) and the slave device is reading this bit and DS40001413E-page 220  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 25-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SCK SCK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS General I/O General I/O SCK SDI SPI Slave SDO #2 SS SCK SDI SPI Slave SDO #3 SS 25.2.1 SPI MODE REGISTERS 25.2.2 SPI MODE OPERATION The MSSP1 module has five registers for SPI mode When initializing the SPI, several options need to be operation. These are: specified. This is done by programming the appropriate control bits (SSP1CON1<5:0> and SSP1STAT<7:6>). • MSSP1 STATUS register (SSP1STAT) These control bits allow the following to be specified: • MSSP1 Control Register 1 (SSP1CON1) • Master mode (SCK1 is the clock output) • MSSP1 Control Register 3 (SSP1CON3) • Slave mode (SCK1 is the clock input) • MSSP1 Data Buffer register (SSP1BUF) • Clock Polarity (Idle state of SCK1) • MSSP1 Address register (SSP1ADD) • Data Input Sample Phase (middle or end of data • MSSP1 Shift register (SSP1SR) output time) (Not directly accessible) • Clock Edge (output data on rising/falling edge of SSP1CON1 and SSP1STAT are the control and SCK1) STATUS registers in SPI mode operation. The • Clock Rate (Master mode only) SSP1CON1 register is readable and writable. The lower 6 bits of the SSP1STAT are read-only. The upper • Slave Select mode (Slave mode only) two bits of the SSP1STAT are read/write. To enable the serial port, SSP1 Enable bit, SSP1EN of In one SPI master mode, SSP1ADD can be loaded the SSP1CON1 register must be set. To reset or recon- with a value used in the Baud Rate Generator. More figure SPI mode, clear the SSP1EN bit, re-initialize the information on the Baud Rate Generator is available in SSP1CONx registers and then set the SSP1EN bit. Section25.7 “Baud Rate Generator”. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port SSP1SR is the shift register used for shifting data in function, some must have their data direction bits (in and out. SSP1BUF provides indirect access to the the TRIS register) appropriately programmed as SSP1SR register. SSP1BUF is the buffer register to follows: which data bytes are written, and from which data bytes are read. • SDI must have corresponding TRIS bit set • SDO must have corresponding TRIS bit cleared In receive operations, SSP1SR and SSP1BUF together create a buffered receiver. When SSP1SR • SCK (Master mode) must have corresponding receives a complete byte, it is transferred to SSP1BUF TRIS bit cleared and the SSP1IF interrupt is set. • SCK (Slave mode) must have corresponding TRIS bit set During transmission, the SSP1BUF is not buffered. A write to SSP1BUF will write to both SSP1BUF and • SS must have corresponding TRIS bit set SSP1SR. Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value.  2010-2015 Microchip Technology Inc. DS40001413E-page 221

PIC12(L)F1822/16(L)F1823 The MSSP1 consists of a transmit/receive shift register When the application software is expecting to receive (SSP1SR) and a buffer register (SSP1BUF). The valid data, the SSP1BUF should be read before the SSP1SR shifts the data in and out of the device, MSb next byte of data to transfer is written to the SSP1BUF. first. The SSP1BUF holds the data that was written to The Buffer Full bit, BF of the SSP1STAT register, the SSP1SR until the received data is ready. Once the indicates when SSP1BUF has been loaded with the eight bits of data have been received, that byte is received data (transmission is complete). When the moved to the SSP1BUF register. Then, the Buffer Full SSP1BUF is read, the BF bit is cleared. This data may Detect bit, BF of the SSP1STAT register, and the be irrelevant if the SPI is only a transmitter. Generally, interrupt flag bit, SSP1IF, are set. This double-buffering the MSSP1 interrupt is used to determine when the of the received data (SSP1BUF) allows the next byte to transmission/reception has completed. If the interrupt start reception before reading the data that was just method is not going to be used, then software polling received. Any write to the SSP1BUF register during can be done to ensure that a write collision does not transmission/reception of data will be ignored and the occur. write collision detect bit, WCOL, of the SSP1CON1 The SSP1SR is not directly readable or writable and register, will be set. User software must clear the can only be accessed by addressing the SSP1BUF WCOL bit to allow the following write(s) to the register. Additionally, the SSP1STAT register indicates SSP1BUF register to complete successfully. the various Status conditions. FIGURE 25-5: SPI MASTER/SLAVE CONNECTION SPI Master SSP1M<3:0> = 00xx SPI Slave SSP1M<3:0> = 010x = 1010 SDO SDI Serial Input Buffer Serial Input Buffer (BUF) (SSP1BUF) SDI SDO Shift Register Shift Register (SSP1SR) (SSP1SR) MSb LSb MSb LSb Serial Clock SCK SCK Slave Select General I/O SS Processor 1 (optional) Processor 2 DS40001413E-page 222  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 25.2.3 SPI MASTER MODE The clock polarity is selected by appropriately programming the CKP bit of the SSP1CON1 register The master can initiate the data transfer at any time and the CKE bit of the SSP1STAT register. This then, because it controls the SCK line. The master would give waveforms for SPI communication as determines when the slave (Processor 2, Figure25-5) shown in Figure25-6, Figure25-8, Figure25-9 and is to broadcast data by the software protocol. Figure25-10, where the MSB is transmitted first. In In Master mode, the data is transmitted/received as Master mode, the SPI clock rate (bit rate) is user soon as the SSP1BUF register is written to. If the SPI programmable to be one of the following: is only going to receive, the SDO output could be dis- • FOSC/4 (or TCY) abled (programmed as an input). The SSP1SR register will continue to shift in the signal present on the SDI pin • FOSC/16 (or 4 * TCY) at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY) received, it will be loaded into the SSP1BUF register as • Timer2 output/2 if a normal received byte (interrupts and Status bits • Fosc/(4 * (SSP1ADD + 1)) appropriately set). Figure25-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSP1BUF is loaded with the received data is shown. FIGURE 25-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSP1BUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSP1IF SSP1SR to SSP1BUF  2010-2015 Microchip Technology Inc. DS40001413E-page 223

PIC12(L)F1822/16(L)F1823 25.2.4 SPI SLAVE MODE 25.2.5 SLAVE SELECT SYNCHRONIZATION In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last The Slave Select can also be used to synchronize com- bit is latched, the SSP1IF interrupt flag bit is set. munication. The Slave Select line is held high until the master device is ready to communicate. When the Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a be observed by reading the SCK pin. The Idle state is new transmission is starting. determined by the CKP bit of the SSP1CON1 register. If the slave fails to receive the communication properly, While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the the external clock source on the SCK pin. This external Slave Select line returns to a high state. The slave is clock must meet the minimum high and low times as then ready to receive a new transmission when the specified in the electrical specifications. Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will even- While in Sleep mode, the slave can transmit/receive tually become out of sync with the master. If the slave data. The shift register is clocked from the SCK pin misses a bit, it will always be one bit off in future trans- input and when a byte is received, the device will gen- missions. Use of the Slave Select line allows the slave erate an interrupt. If enabled, the device will wake-up and master to align themselves at the beginning of from Sleep. each transmission. 25.2.4.1 Daisy-Chain Configuration The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled The SPI bus can sometimes be connected in a (SSP1CON1<3:0> = 0100). daisy-chain configuration. The first slave output is con- nected to the second slave input, the second slave When the SS pin is low, transmission and reception are output is connected to the third slave input, and so on. enabled and the SDO pin is driven. The final slave output is connected to the master input. When the SS pin goes high, the SDO pin is no longer Each slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down first group of clock pulses. The whole chain acts as resistors may be desirable depending on the applica- one large communication shift register. The tion. daisy-chain feature only requires a single Slave Select line from the master device. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSP1CON1<3:0> = Figure25-7 shows the block diagram of a typical 0100), the SPI module will reset if the SS daisy-chain connection when operating in SPI mode. pin is set to VDD. In a daisy-chain configuration, only the most recent 2: When the SPI is used in Slave mode with byte on the bus is required by the slave. Setting the CKE set; the user must enable SS pin BOEN bit of the SSP1CON3 register will enable writes control. to the SSP1BUF register, even if the previous byte has 3: While operated in SPI Slave mode the not been read. This allows the software to ignore data SMP bit of the SSP1STAT register must that may not apply to it. remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSP1EN bit. DS40001413E-page 224  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 25-7: SPI DAISY-CHAIN CONNECTION SCK SCK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS SCK SDI SPI Slave SDO #2 SS SCK SDI SPI Slave SDO #3 SS FIGURE 25-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Shift register SSP1SR and bit count are reset SSP1BUF to SSP1SR SDO bit 7 bit 6 bit 7 bit 6 bit 0 SDI bit 0 bit 7 bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF  2010-2015 Microchip Technology Inc. DS40001413E-page 225

PIC12(L)F1822/16(L)F1823 FIGURE 25-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE=0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active FIGURE 25-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active DS40001413E-page 226  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 25.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmis- In SPI Master mode, module clocks may be operating sion/reception will remain in that state until the device at a different speed than when in full power mode; in wakes. After the device returns to Run mode, the the case of the Sleep mode, all clocks are halted. module will resume transmitting and receiving data. Special care must be taken by the user when the In SPI Slave mode, the SPI Transmit/Receive Shift MSSP1 clock is much faster than the system clock. register operates asynchronously to the device. This In Slave mode, when MSSP1 interrupts are enabled, allows the device to be placed in Sleep mode and data after the master completes sending data, an MSSP1 to be shifted into the SPI Transmit/Receive Shift interrupt will wake the controller from Sleep. register. When all eight bits have been received, the If an exit from Sleep mode is not desired, MSSP1 MSSP1 interrupt flag bit will be set and if enabled, will interrupts should be disabled. wake the device. TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 ANSELC — — — — ANSC3 ANSC2 ANSC1 ANSC0 122 APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(2) CCP1SEL(2) 114 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 221* SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 264 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 266 SSP1STAT SMP CKE D/A P S R/W UA BF 263 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode. * Page provides register information. Note 1: PIC16(L)F1823 only. 2: PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 227

PIC12(L)F1822/16(L)F1823 25.3 I2C MODE OVERVIEW FIGURE 25-11: I2C MASTER/ SLAVE CONNECTION The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master VDD devices initiate the communication. A Slave device is controlled through addressing. SCL SCL The I2C bus specifies two signal connections: VDD • Serial Clock (SCL) Master Slave • Serial Data (SDA) SDA SDA Figure25-11 shows the block diagram of the MSSP1 module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal, supply voltage. Pulling the line to ground is considered which holds the SDA line low to indicate to the transmit- a logical zero and letting the line float is considered a ter that the slave device has received the transmitted logical one. data and is ready to receive more. Figure25-11 shows a typical connection between two The transition of a data bit is always performed while processors configured as master and slave devices. the SCL line is held low. Transitions that occur while the The I2C bus can operate with one or more master SCL line is held high are used to indicate Start and Stop devices and one or more slave devices. bits. There are four potential modes of operation for a given If the master intends to write to the slave, then it repeat- device: edly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the • Master Transmit mode master device is in Master Transmit mode and the (master is transmitting data to a slave) slave is in Slave Receive mode. • Master Receive mode If the master intends to read from the slave, then it (master is receiving data from a slave) repeatedly receives a byte of data from the slave, and • Slave Transmit mode responds after each byte with an ACK bit. In this exam- (slave is transmitting data to a master) ple, the master device is in Master Receive mode and • Slave Receive mode the slave is Slave Transmit mode. (slave is receiving data from the master) On the last byte of data communicated, the master To begin communication, a master device starts out in device may end the transmission by sending a Stop bit. Master Transmit mode. The master device sends out a If the master device is in Receive mode, it sends the Start bit followed by the address byte of the slave it Stop bit in place of the last ACK bit. A Stop bit is indi- intends to communicate with. This is followed by a cated by a low-to-high transition of the SDA line while single Read/Write bit, which determines whether the the SCL line is held high. master intends to transmit to or receive data from the In some cases, the master may want to maintain con- slave device. trol of the bus and re-initiate another transmission. If If the requested slave exists on the bus, it will respond so, the master device may send another Start bit in with an Acknowledge bit, otherwise known as an ACK. place of the Stop bit or last ACK bit when it is in receive The master then continues in either Transmit mode or mode. Receive mode and the slave continues in the comple- The I2C bus specifies three message protocols; ment, either in Receive mode or Transmit mode, respectively. • Single message where a master writes data to a slave. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and • Single message where a master reads data from data bytes are sent out, Most Significant bit (MSb) first. a slave. The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a out as a logical zero when it intends to write data to the combination of writes and reads, to one or more slave. slaves. DS40001413E-page 228  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 When one device is transmitting a logical one, or letting Slave Transmit mode can also be arbitrated, when a the line float, and a second device is transmitting a log- master addresses multiple slaves, but this is less ical zero, or holding the line low, the first device can common. detect that the line is not a logical one. This detection, If two master devices are sending a message to two dif- when used on the SCL line, is called clock stretching. ferent slave devices at the address stage, the master Clock stretching gives slave devices a mechanism to sending the lower slave address always wins arbitra- control the flow of data. When this detection is used on tion. When two master devices send messages to the the SDA line, it is called arbitration. Arbitration ensures same slave address, and addresses can sometimes that there is only one master device communicating at refer to multiple slaves, the arbitration process must any single time. continue into the data stage. 25.3.1 CLOCK STRETCHING Arbitration usually occurs very rarely, but it is a neces- sary process for proper multi-master support. When a slave device has not completed processing data, it can delay the transfer of more data through the 25.4 I2C Mode Operation process of Clock Stretching. An addressed slave device may hold the SCL clock line low after receiving All MSSP1 I2C communication is byte oriented and or sending a bit, indicating that it is not yet ready to con- shifted out MSb first. Six SFR registers and two inter- tinue. The master that is communicating with the slave rupt flags interface the module with the PIC® micro- will attempt to raise the SCL line in order to transfer the controller and user software. Two pins, SDA and SCL, next bit, but will detect that the clock line has not yet are exercised by the module to communicate with been released. Because the SCL connection is other external I2C devices. open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. 25.4.1 BYTE FORMAT Clock stretching allows receivers that cannot keep up All communication in I2C is done in 9-bit segments. A with a transmitter to control the flow of incoming data. byte is sent from a Master to a Slave or vice-versa, followed by an Acknowledge bit sent back. After the 25.3.2 ARBITRATION 8th falling edge of the SCL line, the device outputting Each master device must monitor the bus for Start and data on the SDA changes that pin to an input and Stop bits. If the device detects that the bus is busy, it reads in an acknowledge value on the next clock cannot begin a new message until the bus returns to an pulse. Idle state. The clock signal, SCL, is provided by the master. Data However, two master devices may try to initiate a trans- is valid to change while the SCL signal is low, and mission on or about the same time. When this occurs, sampled on the rising edge of the clock. Changes on the process of arbitration begins. Each transmitter the SDA line while the SCL line is high define special checks the level of the SDA data line and compares it conditions on the bus, explained below. to the level that it expects to find. The first transmitter to 25.4.2 DEFINITION OF I2C TERMINOLOGY observe that the two levels don’t match, loses arbitra- tion, and must stop transmitting on the SDA line. There is language and terminology in the description For example, if one transmitter holds the SDA line to a of I2C communication that have definitions specific to logical one (lets it float) and a second transmitter holds I2C. That word usage is defined below and may be it to a logical zero (pulls it low), the result is that the used in the rest of this document without explana- SDA line will be low. The first transmitter then observes tion. This table was adapted from the Philips I2C™ that the level of the line is different than expected and specification. concludes that another transmitter is communicating. 25.4.3 SDA AND SCL PINS The first transmitter to notice this difference is the one Selection of any I2C mode with the SSP1EN bit set, that loses arbitration and must stop driving the SDA forces the SCL and SDA pins to be open-drain. These line. If this transmitter is also a master device, it also pins should be set by the user to inputs by setting the must stop driving the SCL line. It then can monitor the appropriate TRIS bits. lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that Note: Data is tied to output zero when an I2C has not noticed any difference between the expected mode is enabled. and actual levels on the SDA line continues with its original transmission. It can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message.  2010-2015 Microchip Technology Inc. DS40001413E-page 229

PIC12(L)F1822/16(L)F1823 25.4.4 SDA HOLD TIME TABLE 25-2: I2C BUS TERMS The hold time of the SDA pin is selected by the SDAHT TERM Description bit of the SSP1CON3 register. Hold time is the time Transmitter The device which shifts data out SDA is held valid after the falling edge of SCL. Setting onto the bus. the SDAHT bit selects a longer 300ns minimum hold Receiver The device which shifts data in time and may help on buses with large capacitance. from the bus. Master The device that initiates a transfer, generates clock signals and termi- nates a transfer. Slave The device addressed by the mas- ter. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Addressed Slave device that has received a Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSP1ADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is out- putting and expected high state. DS40001413E-page 230  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 25.4.5 START CONDITION has the same effect on the slave that a Start would, The I2C specification defines a Start condition as a resetting all slave logic and preparing it to clock in an address. The master may want to address the same or transition of SDA from a high to a low state while SCL another slave. Figure25-13 shows wave forms for a line is high. A Start condition is always generated by Restart condition. the master and signifies the transition of the bus from an Idle to an Active state. Figure25-12 shows wave In 10-bit Addressing Slave mode a Restart is required forms for Start and Stop conditions. for the master to clock data out of the addressed slave. Once a slave has been fully addressed, match- A bus collision can occur on a Start condition if the ing both high and low address bytes, the master can module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock states no bus collision can occur on a Start. and prepare to clock out data. 25.4.6 STOP CONDITION After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condi- A Stop condition is a transition of the SDA line from tion, a high address with R/W clear, or high address low-to-high state while the SCL line is high. match fails. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA 25.4.8 START/STOP CONDITION line goes low then high again while the SCL INTERRUPT MASKING line stays high, only the Start condition is The SCIE and PCIE bits of the SSP1CON3 register detected. can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave 25.4.7 RESTART CONDITION modes where interrupt on Start and Stop detect are A Restart is valid any time that a Stop would be valid. already enabled, these bits will have no effect. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart FIGURE 25-12: I2C START AND STOP CONDITIONS SDA SCL S P Change of Change of Data Allowed Data Allowed Start Stop Condition Condition FIGURE 25-13: I2C RESTART CONDITION Sr Change of Change of Data Allowed Data Allowed Restart Condition  2010-2015 Microchip Technology Inc. DS40001413E-page 231

PIC12(L)F1822/16(L)F1823 25.4.9 ACKNOWLEDGE SEQUENCE 25.5 I2C SLAVE MODE OPERATION The 9th SCL pulse for any transferred byte in I2C is The MSSP1 Slave mode operates in one of four dedicated as an Acknowledge. It allows receiving modes selected in the SSP1M bits of SSP1CON1 reg- devices to respond back to the transmitter by pulling ister. The modes can be divided into 7-bit and 10-bit the SDA line low. The transmitter must release control Addressing mode. 10-bit Addressing modes operate of the line during this time to shift in the response. The the same as 7-bit with some additional overhead for Acknowledge (ACK) is an active-low signal, pulling the handling the larger addresses. SDA line low indicated to the transmitter that the device has received the transmitted data and is ready Modes with Start and Stop bit interrupts operated the to receive more. same as the other modes with SSP1IF additionally getting set upon detection of a Start, Restart, or Stop The result of an ACK is placed in the ACKSTAT bit of condition. the SSP1CON2 register. Slave software, when the AHEN and DHEN bits are 25.5.1 SLAVE MODE ADDRESSES set, allow the user to set the ACK value sent back to The SSP1ADD register (Register25-6) contains the the transmitter. The ACKDT bit of the SSP1CON2 reg- Slave mode address. The first byte received after a ister is set/cleared to determine the response. Start or Restart condition is compared against the Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the AHEN and DHEN bits of the SSP1CON3 register are value is loaded into the SSP1BUF register and an clear. interrupt is generated. If the value does not match, the module goes Idle and no indication is given to the soft- There are certain conditions where an ACK will not be ware that anything happened. sent by the slave. If the BF bit of the SSP1STAT regis- ter or the SSP1OV bit of the SSP1CON1 register are The SSP Mask register (Register25-5) affects the set when a byte is received. address matching process. See Section25.5.9 “SSP1 Mask Register” for more information. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit of the 25.5.1.1 I2C Slave 7-bit Addressing Mode SSP1CON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM In 7-bit Addressing mode, the LSb of the received data Status bit is only active when the AHEN bit or DHEN byte is ignored when determining if there is an address bit is enabled. match. 25.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSbs of the 10-bit address and stored in bits 2 and 1 of the SSP1ADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSP1ADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSP1ADD. Even if there is not an address match; SSP1IF and UA are set, and SCL is held low until SSP1ADD is updated to receive a high byte again. When SSP1ADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communi- cation. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hard- ware will then acknowledge the read request and pre- pare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS40001413E-page 232  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 25.5.2 SLAVE RECEPTION 25.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte is clear, the R/W bit of the SSP1STAT register is Slave device reception with AHEN and DHEN set cleared. The received address is loaded into the operate the same as without these options with extra SSP1BUF register and acknowledged. interrupts and clock stretching added after the eighth When the overflow condition exists for a received falling edge of SCL. These additional interrupts allow address, then not Acknowledge is given. An overflow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hard- condition is defined as either bit BF of the SSP1STAT register is set, or bit SSP1OV of the SSP1CON1 regis- ware. This functionality adds support for PMBus™ that ter is set. The BOEN bit of the SSP1CON3 register was not present on previous versions of this module. modifies this operation. For more information see This list describes the steps that need to be taken by Register25-4. slave software to use these options for I2C communi- cation. Figure25-16 displays a module using both An MSSP1 interrupt is generated for each transferred address and data holding. Figure25-17 includes the data byte. Flag bit, SSP1IF, must be cleared by soft- operation with the SEN bit of the SSP1CON2 register ware. set. When the SEN bit of the SSP1CON2 register is set, 1. S bit of SSP1STAT is set; SSP1IF is set if inter- SCL will be held low (clock stretch) following each rupt on Start detect is enabled. received byte. The clock must be released by setting the CKP bit of the SSP1CON1 register, except 2. Matching address with R/W bit clear is clocked sometimes in 10-bit mode. See Section25.2.3 “SPI in. SSP1IF is set and CKP cleared after the 8th Master Mode” for more detail. falling edge of SCL. 3. Slave clears the SSP1IF. 25.5.2.1 7-bit Addressing Reception 4. Slave can look at the ACKTIM bit of the This section describes a standard sequence of events SSP1CON3 register to determine if the SSP1IF for the MSSP1 module configured as an I2C Slave in was after or before the ACK. 7-bit Addressing mode. All decisions made by hard- 5. Slave reads the address value from SSP1BUF, ware or software and their effect on reception. clearing the BF flag. Figure25-14 and Figure25-15 is used as a visual 6. Slave sets ACK value clocked out to the master reference for this description. by setting ACKDT. This is a step by step process of what typically must 7. Slave releases the clock by setting CKP. be done to accomplish I2C communication. 8. SSP1IF is set after an ACK, not after a NACK. 1. Start bit detected. 9. If SEN=1 the slave hardware will stretch the 2. S bit of SSP1STAT is set; SSP1IF is set if inter- clock after the ACK. rupt on Start detect is enabled. 10. Slave clears SSP1IF. 3. Matching address with R/W bit clear is received. Note: SSP1IF is still set after the 9th falling edge 4. The slave pulls SDA low sending an ACK to the of SCL even if there is no clock stretching master, and sets SSP1IF bit. and BF has been cleared. Only if NACK is 5. Software clears the SSP1IF bit. sent to Master is SSP1IF not set 6. Software reads received address from 11. SSP1IF set and CKP cleared after eighth falling SSP1BUF clearing the BF flag. edge of SCL for a received data byte. 7. If SEN=1; Slave software sets CKP bit to 12. Slave looks at ACKTIM bit of SSP1CON3 to release the SCL line. determine the source of the interrupt. 8. The master clocks out a data byte. 13. Slave reads the received data from SSP1BUF 9. Slave drives SDA low sending an ACK to the clearing BF. master, and sets SSP1IF bit. 14. Steps 7-14 are the same for each received data 10. Software clears SSP1IF. byte. 11. Software reads the received byte from 15. Communication is ended by either the slave SSP1BUF clearing BF. sending an ACK=1, or the master sending a 12. Steps 8-12 are repeated for all received bytes Stop condition. If a Stop is sent and Interrupt on from the Master. Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. 13. Master sends Stop condition, setting P bit of SSP1STAT, and the bus goes Idle.  2010-2015 Microchip Technology Inc. DS40001413E-page 233

PIC12(L)F1822/16(L)F1823 FIGURE 25-14: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=0, DHEN=0) s Bus Master sendStop condition 1 P SSP1IF set on 9thfalling edge of SCL = K 9 C A D0 8 e Master eceiving Data D4D3D2D1 4567 eared by software SSP1OV set becausSSP1BUF is still full. ACK is not sent. e to R D5 3 Cl v F From Sla D7D6K 12 First byte of data is available in SSP1BU C 9 A D0 8 D1 7 ad e a D2 6 ware F is r Receiving Dat D5D4D3 345 Cleared by soft SSP1BU D6 2 D7 1 K 9 C A 8 A1 7 2 6 A s s dre A3 5 d A ng A4 4 vi ecei A5 3 R A6 2 A7 1 S V F O A L 1I 1 D C P F P S S S B S S S DS40001413E-page 234  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 25-15: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) Bus Master sends Stop condition P SSP1IF set on 9thfalling edge of SCL SCL is not heldlow becauseACK=1 K C 9 A D0 8 e Receive Data D7D6D5D4D3D2D1 1234567 Cleared by software First byte of data is available in SSP1BUF SSP1OV set becausSSP1BUF is still full. ACK is not sent. CKP is written to ‘’ in software,1releasing SCL N E S K AC 9 D0 8 ’1 o ‘ Data D2D1 67 KP is set t oftware, Receive D7D6D5D4D3 12345 Clock is held low until C Cleared by software SSP1BUF is read CKP is written to ‘’ in s1releasing SCL N E S K C A 9 0 = W R/ 8 A1 7 2 6 A s s dre A3 5 d e A A4 4 v ei ec A5 3 R 6 2 A A7 1 S V F O P SDA SCL SSP1I BF SSP1 CK  2010-2015 Microchip Technology Inc. DS40001413E-page 235

PIC12(L)F1822/16(L)F1823 FIGURE 25-16: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=1) Master sendsStop condition = 1 P No interruptafter not ACKfrom Slave CK 9 A are T to Received DataCKD7D6D5D4D3D2D1D0 912345678 Cleared by software a is read from SSP1BUF Slave softwsets ACKDnot ACK CKP set by software, SCL is released ACKTIM set by hardwareon 8th falling edge of SCL A at D D0 8 g Receiving Data D6D5D4D3D2D1 234567 SP1IF is set on h falling edge of CL, after ACK When DHEN = 1:CKP is cleared byhardware on 8th fallinedge of SCL KTIM cleared bydware in 9th ng edge of SCL D7 1 S9tS ACharrisi K 9 ce C n A e Au Dq ses SCK se aA eleor Master Rto slave f Receiving Address A6A5A4A3A2A1 2345678 If AHEN=:1SSP1IF is set Address isread from SSBUF Slave softwareclears ACKDT to ACK the receivedbyte When AHEN = 1:CKP is cleared by hardwareand SCL is stretched ACKTIM set by hardwareon 8th falling edge of SCL A7 1 S M SDA SCL SSP1IF BF ACKDT CKP ACKTI S P DS40001413E-page 236  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 25-17: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN= 1, AHEN=1, DHEN=1) Master sendsStop condition P No interrupt afterif not ACKfrom Slave CKP is not clearedif not ACK K 9 C A D0 8 s d D1 7 enK Receive Data D6D5D4D3D2 23456 SSP1BUF can beread any time beforenext byte is loaded Slave snot AC Set by software,release SCL D7 1 K C 9 A D0 8 F e K sequence Receive Data D7D6D5D4D3D2D1 1245673 Cleared by software Received data isavailable on SSP1BU When DHEN = ;1on the 8th falling edgeof SCL of a receiveddata byte, CKP is cleared ACKTIM is cleared by hardwaron 9th rising edge of SCL C A ster releasesA to slave for ACK 9 aD MS 8 s R/W = 0 Receiving Address A6A5A4A3A2A1 342567 Received address is loaded into SSP1BUF Slave software clearACKDT to ACKthe received byte When AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared KTIM is set by hardware8th falling edge of SCL A7 1 ACon S M TI SDA SCL P1IF BF CKDT CKP ACK S P S A S  2010-2015 Microchip Technology Inc. DS40001413E-page 237

PIC12(L)F1822/16(L)F1823 25.5.3 SLAVE TRANSMISSION 25.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set A master device can transmit a read request to a and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list SSP1STAT register is set. The received address is below outlines what software for a slave will need to loaded into the SSP1BUF register, and an ACK pulse do to accomplish a standard transmission. is sent by the slave on the ninth bit. Figure25-18 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and and the SCL pin is held low (see Section25.5.6 SCL. “Clock Stretching” for more detail). By stretching the 2. S bit of SSP1STAT is set; SSP1IF is set if inter- clock, the master will be unable to assert another clock rupt-on-Start detect is enabled. pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by data. the Slave setting SSP1IF bit. The transmit data must be loaded into the SSP1BUF 4. Slave hardware generates an ACK and sets register which also loads the SSP1SR register. Then SSP1IF. the SCL pin should be released by setting the CKP bit 5. SSP1IF bit is cleared by user. of the SSP1CON1 register. The eight data bits are 6. Software reads the received address from shifted out on the falling edge of the SCL input. This SSP1BUF, clearing BF. ensures that the SDA signal is valid during the SCL 7. R/W is set so CKP was automatically cleared high time. after the ACK. The ACK pulse from the master-receiver is latched on 8. The slave software loads the transmit data into the rising edge of the ninth SCL input pulse. This ACK SSP1BUF. value is copied to the ACKSTAT bit of the SSP1CON2 register. If ACKSTAT is set (not ACK), then the data 9. CKP bit is set releasing SCL, allowing the transfer is complete. In this case, when the not ACK is master to clock the data out of the slave. latched by the slave, the slave goes Idle and waits for 10. SSP1IF is set after the ACK response from the another occurrence of the Start bit. If the SDA line was master is loaded into the ACKSTAT register. low (ACK), the next transmit data must be loaded into 11. SSP1IF bit is cleared. the SSP1BUF register. Again, the SCL pin must be 12. The slave software checks the ACKSTAT bit to released by setting bit CKP. see if the master wants to clock out more data. An MSSP1 interrupt is generated for each data transfer Note 1: If the master ACKs the clock will be byte. The SSP1IF bit must be cleared by software and stretched. the SSP1STAT register is used to determine the status 2: ACKSTAT is the only bit updated on the of the byte. The SSP1IF bit is set on the falling edge of rising edge of SCL (9th) rather than the the ninth clock pulse. falling. 25.5.3.1 Slave Mode Bus Collision 13. Steps 9-13 are repeated for each transmitted A slave receives a Read request and begins shifting byte. data out on the SDA line. If a bus collision is detected 14. If the master sends a not ACK; the clock is not and the SBCDE bit of the SSP1CON3 register is set, held, but SSP1IF is still set. the BCL1IF bit of the PIRx register is set. Once a bus 15. The master sends a Restart condition or a Stop. collision is detected, the slave goes Idle and waits to be 16. The slave is no longer addressed. addressed again. User software can use the BCL1IF bit to handle a slave bus collision. DS40001413E-page 238  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 25-18: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=0) sn do enditi er scon P stp ao MSt K C 9 A Transmitting Data D7D6D5D4D3D2D1D0 12345678 BF is automatically cleared after 8th fallingedge of SCL CKP is not held for not ACK Masters not ACKis copied to ACKSTAT c ati m o ut A K AC 9 D0 8 1 D 7 a Dat D2 6 F Transmitting D7D6D5D4D3 12345 Cleared by software Data to transmit isloaded into SSP1BU Set by software c ati m o ut A 1CK =A 9 W eceiving AddressR/A5A4A3A2A1 345678 Received addressis read from SSP1BUF When R/W is setSCL is alwaysheld low after 9th SCLfalling edge R/W is copied from the matching address byte Indicates an address has been received R 6 A 2 7 A 1 S T F TA SDA SCL SSP1I BF CKP ACKS R/W D/A S P  2010-2015 Microchip Technology Inc. DS40001413E-page 239

PIC12(L)F1822/16(L)F1823 25.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSP1CON3 register enables additional clock stretching and interrupt gen- eration after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSP1IF interrupt is set. Figure25-19 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. Bus starts Idle. 2. Master sends Start condition; the S bit of SSP1STAT is set; SSP1IF is set if inter- rupt-on-Start detect is enabled. 3. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSP1IF interrupt is generated. 4. Slave software clears SSP1IF. 5. Slave software reads ACKTIM bit of SSP1CON3 register, and R/W and D/A of the SSP1STAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSP1BUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSP1CON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSP1IF after the ACK if the R/W bit is set. 11. Slave software clears SSP1IF. 12. Slave loads value to transmit to the master into SSP1BUF setting the BF bit. Note: SSP1BUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSP1CON2 register. 16. Steps 10-15 are repeated for each byte transmit- ted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus, allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS40001413E-page 240  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 25-19: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=1) endsdition sn aster op co P MSt K C A 9 0 D 8 Transmitting Data D6D5D4D3D2D1 234567 BF is automatically cleared after 8th fallingedge of SCL Master’s ACKresponse is copiedto SSP1STAT CKP not cleared after not ACK 7 D 1 c ati m o AutK C A 9 D0 8 1 a D 7 at D 2 ence omaticTransmitting D7D6D5D4D3D 123456 Cleared by software Data to transmit isloaded into SSP1BUF Set by software,releases SCL KTIM is cleared9th rising edge of SCL DAequ Aut ACon Ss K Master releases to slave for ACK W=1AC 9 When R/W = ;1CKP is alwayscleared after ACK R/ 8 F U K Receiving Address A7A6A5A4A3A2A1 1234567 Received addressis read from SSP1B Slave clearsACKDT to ACaddress When AHEN = ;1CKP is cleared by hardwareafter receiving matchingaddress. ACKTIM is set on 8th fallingedge of SCL S SDA SCL P1IF BF KDT TAT CKP TIM R/W D/A S C S K S A K C C A A  2010-2015 Microchip Technology Inc. DS40001413E-page 241

PIC12(L)F1822/16(L)F1823 25.5.4 SLAVE MODE 10-BIT ADDRESS 25.5.5 10-BIT ADDRESSING WITH RECEPTION ADDRESS OR DATA HOLD This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or for the MSSP1 module configured as an I2C Slave in DHEN set is the same as with 7-bit modes. The only 10-bit Addressing mode. difference is the need to update the SSP1ADD register using the UA bit. All functionality, specifically when the Figure25-20 is used as a visual reference for this CKP bit is cleared and SCL line is held low are the description. same. Figure25-21 can be used as a reference of a This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set. slave software to accomplish I2C communication. Figure25-22 shows a standard waveform for a slave 1. Bus starts Idle. transmitter in 10-bit Addressing mode. 2. Master sends Start condition; S bit of SSP1STAT is set; SSP1IF is set if inter- rupt-on-Start detect is enabled. 3. Master sends matching high address with R/W bit clear; UA bit of the SSP1STAT register is set. 4. Slave sends ACK and SSP1IF is set. 5. Software clears the SSP1IF bit. 6. Software reads received address from SSP1BUF clearing the BF flag. 7. Slave loads low address into SSP1ADD, releasing SCL. 8. Master sends matching low address byte to the Slave; UA bit is set. Note: Updates to the SSP1ADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSP1IF is set. Note: If the low address does not match, SSP1IF and UA are still set so that the slave soft- ware can set SSP1ADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSP1IF. 11. Slave reads the received matching address from SSP1BUF clearing BF. 12. Slave loads high address into SSP1ADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSP1IF is set. 14. If SEN bit of SSP1CON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSP1IF. 16. Slave reads the received byte from SSP1BUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS40001413E-page 242  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 25-20: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) endsdition er scon P stp ao MSt K C 9 A 0 8 D ata D1 7 dBUF D 2 6 a1 Receive D6D5D4D3D 2345 SCL is held lowwhile CKP = 0 Data is refrom SSP Set by software,releasing SCLyte D7 1 d b e v K cei Receive Data D6D5D4D3D2D1D0AC 92345678 Cleared by software Receive address isread from SSP1BUF When SEN = ;1CKP is cleared after9th falling edge of re D7 1 K C e A 9 Byt A0 8 DD ess A1 7 P1A Receive Second Addr A6A5A4A3A2 23456 Software updates SSand releases SCL A7 1 K C 9 A o ve First Address Byte 0A9A811 345678 Set by hardwareon 9th falling edge If address matchesSSP1ADD it is loaded intSSP1BUF When UA = ;1SCL is held low ei 1 2 c e R 1 1 S A L F F A P D C 1I B U K S S P C S S  2010-2015 Microchip Technology Inc. DS40001413E-page 243

PIC12(L)F1822/16(L)F1823 FIGURE 25-21: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=0) a Receive Data D7D6D5 12 Received datis read from SSP1BUF K C 9 A D0 8 D1 7 s D,se Receive Data D6D5D4D3D2 23456 eared by software Update of SSP1ADclears UA and releaSCL CKP with software ases SCL D7 1 Cl Set rele A U K C 9 A 0 A 8 Receive Second Address Byte A6A5A4A3A2A1 345672 ed by software SSP1BUF can beread anytime beforethe next received byte ate to SSP1ADD isallowed until 9thng edge of SCL A7 1 Clear Updnot falli A U K C 9 A 0 = W 8 R/ e eive First Address Byte A9A8110 34567 Set by hardwareon 9th falling edge Slave software clearsACKDT to ACKthe received byte If when AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared ACKTIM is set by hardwaron 8th falling edge of SCL ec 1 2 R 1 1 S F T M SDA SCL SSP1I BF ACKD UA CKP ACKTI DS40001413E-page 244  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 25-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN=0, AHEN=0, DHEN=0) ends dition er scon P MastStop K = 1 ds AC 9 en D0 8 K Master snot ACK Transmitting Data Byte D7D6D5D4D3D2D1 1723456 Data to transmit isloaded into SSP1BUF Set by softwarereleases SCL Masters not ACis copied K C A 9 e 8 aster sends estart event Receive First Address Byt A9A811110 1672345Sr Set by hardware Received address isread from SSP1BUF High address is loadedback into SSP1ADD When R/W = ;1CKP is cleared on9th falling edge of SCL R/W is copied from thematching address byte MR K yte AC 9 s B A0 8 ed eiving Second Addres A6A5A4A3A2A1 672345 Cleared by software After SSP1ADD isupdated, UA is clearand SCL is released c Re A7 1 K = 0 AC 9 W 8 Receiving AddressR/ A9A811110 1672345 Set by hardware SSP1BUF loadedwith received address UA indicates SSP1ADDmust be updated Indicates an addresshas been received S AT T S SDA SCL P1IF BF UA CKP ACK R/W D/A S S  2010-2015 Microchip Technology Inc. DS40001413E-page 245

PIC12(L)F1822/16(L)F1823 25.5.6 CLOCK STRETCHING 25.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set, the holds the SCL line low effectively pausing communica- clock is always stretched. This is the only time the SCL tion. The slave may stretch the clock to allow more is stretched without CKP being cleared. SCL is time to handle data or prepare a response for the mas- released immediately after a write to SSP1ADD. ter device. A master device is not concerned with Note: Previous versions of the module did not stretching as anytime it is active on the bus and not stretch the clock if the second address byte transferring data it is stretching. Any stretching done did not match. by a slave is invisible to the master software and han- dled by the hardware that generates SCL. 25.5.6.3 Byte NACKing The CKP bit of the SSP1CON1 register is used to con- When AHEN bit of SSP1CON3 is set; CKP is cleared trol stretching in software. Any time the CKP bit is by hardware after the eighth falling edge of SCL for a cleared, the module will wait for the SCL line to go low received matching address byte. When DHEN bit of and then hold it. Setting CKP will release SCL and SSP1CON3 is set; CKP is cleared after the eighth allow more communication. falling edge of SCL for received data. 25.5.6.1 Normal Clock Stretching Stretching after the eighth falling edge of SCL allows Following an ACK if the R/W bit of SSP1STAT is set, a the slave to look at the received address or data and read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data. allows the slave time to update SSP1BUF with data to 25.5.7 CLOCK SYNCHRONIZATION AND transfer to the master. If the SEN bit of SSP1CON2 is THE CKP BIT set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait is set by software and communication resumes. for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low Note 1: The BF bit has no effect on if the clock will until the SCL output is already sampled low. There- be stretched or not. This is different than fore, the CKP bit will not assert the SCL line until an previous versions of the module that external I2C master device has already asserted the would not stretch the clock, clear CKP, if SCL line. The SCL output will remain low until the CKP SSP1BUF was read before the ninth bit is set and all other devices on the I2C bus have falling edge of SCL. released SCL. This ensures that a write to the CKP bit 2: Previous versions of the module did not will not violate the minimum high time requirement for stretch the clock for a transmission if SCL (see Figure25-23). SSP1BUF was loaded before the ninth falling edge of SCL. It is now always cleared for read requests. FIGURE 25-23: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX ‚ – 1 SCL Master device CKP asserts clock Master device releases clock WR SSP1CON1 DS40001413E-page 246  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 25.5.8 GENERAL CALL ADDRESS software can read SSP1BUF and respond. SUPPORT Figure25-24 shows a general call reception sequence. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually deter- In 10-bit Address mode, the UA bit will not be set on mines which device will be the slave addressed by the the reception of the general call address. The slave master device. The exception is the general call will prepare to receive the second byte as data, just as address which can address all devices. When this it would in 7-bit mode. address is used, all devices should, in theory, respond If the AHEN bit of the SSP1CON3 register is set, just with an acknowledge. as with any other address reception, the slave hard- The general call address is a reserved address in the ware will stretch the clock after the 8th falling edge of I2C protocol, defined as address 0x00. When the SCL. The slave must then set its ACKDT value and GCEN bit of the SSP1CON2 register is set, the slave release the clock with communication progressing as it module will automatically ACK the reception of this would normally. address regardless of the value stored in SSP1ADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave FIGURE 25-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSP1IF BF (SSP1STAT<0>) Cleared by software SSP1BUF is read GCEN (SSP1CON2<7>) ’1’ 25.5.9 SSP1 MASK REGISTER An SSP1 Mask (SSP1MSK) register (Register25-5) is available in I2C Slave mode as a mask for the value held in the SSP1SR register during an address comparison operation. A zero (‘0’) bit in the SSP1MSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP1 operation until written with a mask value. The SSP1 Mask register is active during: • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSP1 mask has no effect during the reception of the first (high) byte of the address.  2010-2015 Microchip Technology Inc. DS40001413E-page 247

PIC12(L)F1822/16(L)F1823 25.6 I2C MASTER MODE 25.6.1 I2C MASTER MODE OPERATION The master device generates all of the serial clock Master mode is enabled by setting and clearing the pulses and the Start and Stop conditions. A transfer is appropriate SSP1M bits in the SSP1CON1 register and ended with a Stop condition or with a Repeated Start by setting the SSP1EN bit. In Master mode, the SCL condition. Since the Repeated Start condition is also and SDA lines are set as inputs and are manipulated by the beginning of the next serial transfer, the I2C bus will the MSSP1 hardware. not be released. Master mode of operation is supported by interrupt In Master Transmitter mode, serial data is output generation on the detection of the Start and Stop con- through SDA, while SCL outputs the serial clock. The ditions. The Stop (P) and Start (S) bits are cleared from first byte transmitted contains the slave address of the a Reset or when the MSSP1 module is disabled. Con- trol of the I2C bus may be taken when the P bit is set, receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic ‘0’. Serial data is or the bus is Idle. transmitted eight bits at a time. After each byte is trans- In Firmware Controlled Master mode, user code mitted, an Acknowledge bit is received. Start and Stop conducts all I2C bus operations based on Start and conditions are output to indicate the beginning and the Stop bit condition detection. Start and Stop condition end of a serial transfer. detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted con- other communication is done by the user software tains the slave address of the transmitting device directly manipulating the SDA and SCL lines. (7bits) and the R/W bit. In this case, the R/W bit will be The following events will cause the SSP1 Interrupt Flag logic ‘1’. Thus, the first byte transmitted is a 7-bit slave bit, SSP1IF, to be set (SSP1 interrupt, if enabled): address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the • Start condition detected serial clock. Serial data is received eight bits at a time. • Stop condition detected After each byte is received, an Acknowledge bit is • Data transfer byte transmitted/received transmitted. Start and Stop conditions indicate the • Acknowledge transmitted/received beginning and end of transmission. • Repeated Start generated A Baud Rate Generator is used to set the clock Note 1: The MSSP1 module, when configured in frequency output on SCL. See Section25.7 “Baud I2C Master mode, does not allow queuing Rate Generator” for more detail. of events. For instance, the user is not 25.6.2 CLOCK ARBITRATION allowed to initiate a Start condition and immediately write the SSP1BUF register Clock arbitration occurs when the master, during any to initiate transmission before the Start receive, transmit or Repeated Start/Stop condition, condition is complete. In this case, the releases the SCL pin (SCL allowed to float high). When SSP1BUF will not be written to and the the SCL pin is allowed to float high, the Baud Rate WCOL bit will be set, indicating that a Generator (BRG) is suspended from counting until the write to the SSP1BUF did not occur SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded 2: When in Master mode, Start/Stop detec- with the contents of SSP1ADD<7:0> and begins count- tion is masked and an interrupt is gener- ing. This ensures that the SCL high time will always be ated when the SEN/PEN bit is cleared and at least one BRG rollover count in the event that the the generation is complete. clock is held low by an external device (Figure25-25). DS40001413E-page 248  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 25-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX ‚ – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload 25.6.3 WCOL STATUS FLAG high is the Start condition and causes the S bit of the SSP1STAT1 register to be set. Following this, the If the user writes the SSP1BUF when a Start, Restart, Baud Rate Generator is reloaded with the contents of Stop, Receive or Transmit sequence is in progress, the SSP1ADD<7:0> and resumes its count. When the WCOL is set and the contents of the buffer are Baud Rate Generator times out (TBRG), the SEN bit of unchanged (the write does not occur). Any time the the SSP1CON2 register will be automatically cleared WCOL bit is set it indicates that an action on SSP1BUF by hardware; the Baud Rate Generator is suspended, was attempted while the module was not Idle. leaving the SDA line held low and the Start condition is Note: Because queuing of events is not allowed, complete. writing to the lower five bits of SSP1CON2 Note 1: If at the beginning of the Start condition, is disabled until the Start condition is the SDA and SCL pins are already sam- complete. pled low, or if during the Start condition, 25.6.4 I2C MASTER MODE START the SCL line is sampled low before the SDA line is driven low, a bus collision CONDITION TIMING occurs, the Bus Collision Interrupt Flag, To initiate a Start condition (Figure25-26), the user BCL1IF, is set, the Start condition is sets the Start Enable bit, SEN bit of the SSP1CON2 aborted and the I2C module is reset into register. If the SDA and SCL pins are sampled high, its Idle state. the Baud Rate Generator is reloaded with the contents 2: The Philips I2C™ Specification states that of SSP1ADD<7:0> and starts its count. If SCL and a bus collision cannot occur on a Start. SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is FIGURE 25-26: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSP1STAT<3>) At completion of Start bit, SDA = 1, hardware clears SEN bit SCL = 1 and sets SSP1IF bit TBRG TBRG Write to SSP1BUF occurs here SDA 1st bit 2nd bit TBRG SCL S TBRG  2010-2015 Microchip Technology Inc. DS40001413E-page 249

PIC12(L)F1822/16(L)F1823 25.6.5 I2C MASTER MODE REPEATED cally cleared and the Baud Rate Generator will not be START CONDITION TIMING reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, A Repeated Start condition (Figure25-27) occurs when the S bit of the SSP1STAT register will be set. The the RSEN bit of the SSP1CON2 register is pro- SSP1IF bit will not be set until the Baud Rate Generator grammed high and the Master state machine is no lon- has timed out. ger active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Note1: If RSEN is programmed while any other Baud Rate Generator is loaded and begins counting. event is in progress, it will not take effect. The SDA pin is released (brought high) for one Baud 2: A bus collision during the Repeated Start Rate Generator count (TBRG). When the Baud Rate condition occurs if: Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is • SDA is sampled low when SCL sampled high, the Baud Rate Generator is reloaded goes from low-to-high. and begins counting. SDA and SCL must be sampled • SCL goes low before SDA is high for one TBRG. This action is then followed by asserted low. This may indicate assertion of the SDA pin (SDA=0) for one TBRG while that another master is attempting to SCL is high. SCL is asserted low. Following this, the transmit a data ‘1’. RSEN bit of the SSP1CON2 register will be automati- FIGURE 25-27: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSP1CON2 occurs here At completion of Start bit, SDA = 1, SDA = 1, hardware clears RSEN bit SCL (no change) SCL = 1 and sets SSP1IF TBRG TBRG TBRG SDA 1st bit Write to SSP1BUF occurs here TBRG SCL Sr TBRG Repeated Start 25.6.6 I2C MASTER MODE on the rising edge of the ninth clock. If the master TRANSMISSION receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth Transmission of a data byte, a 7-bit address or the clock, the SSP1IF bit is set and the master clock (Baud other half of a 10-bit address is accomplished by simply Rate Generator) is suspended until the next data byte writing a value to the SSP1BUF register. This action will is loaded into the SSP1BUF, leaving SCL low and SDA set the Buffer Full flag bit, BF, and allow the Baud Rate unchanged (Figure25-28). Generator to begin counting and start the next trans- mission. Each bit of address/data will be shifted out After the write to the SSP1BUF, each bit of the address onto the SDA pin after the falling edge of SCL is will be shifted out on the falling edge of SCL until all asserted. SCL is held low for one Baud Rate Generator seven address bits and the R/W bit are completed. On rollover count (TBRG). Data should be valid before SCL the falling edge of the eighth clock, the master will is released high. When the SCL pin is released high, it release the SDA pin, allowing the slave to respond with is held that way for TBRG. The data on the SDA pin an Acknowledge. On the falling edge of the ninth clock, must remain stable for that duration and some hold the master will sample the SDA pin to see if the address time after the next falling edge of SCL. After the eighth was recognized by a slave. The status of the ACK bit is bit is shifted out (the falling edge of the eighth clock), loaded into the ACKSTAT Status bit of the SSP1CON2 the BF flag is cleared and the master releases SDA. register. Following the falling edge of the ninth clock This allows the slave device being addressed to transmission of the address, the SSP1IF is set, the BF respond with an ACK bit during the ninth bit time if an flag is cleared and the Baud Rate Generator is turned address match occurred, or if data was received prop- off until another write to the SSP1BUF takes place, erly. The status of ACK is written into the ACKSTAT bit holding SCL low and allowing SDA to float. DS40001413E-page 250  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 25.6.6.1 BF Status Flag In Transmit mode, the BF bit of the SSP1STAT register is set when the CPU writes to SSP1BUF and is cleared when all eight bits are shifted out. 25.6.6.2 WCOL Status Flag If the user writes the SSP1BUF when a transmit is already in progress (i.e., SSP1SR is still shifting out a data byte), the WCOL is set and the contents of the buf- fer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. 25.6.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSP1CON2 register is cleared when the slave has sent an Acknowl- edge (ACK=0) and is set when the slave does not Acknowledge (ACK=1). A slave sends an Acknowl- edge when it has recognized its address (including a general call), or when the slave has properly received its data. 25.6.6.4 Typical Transmit Sequence: 1. The user generates a Start condition by setting the SEN bit of the SSP1CON2 register. 2. SSP1IF is set by hardware on completion of the Start. 3. SSP1IF is cleared by software. 4. The MSSP1 module will wait the required start time before any other operation takes place. 5. The user loads the SSP1BUF with the slave address to transmit. 6. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSP1BUF is written to. 7. The MSSP1 module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. 8. The MSSP1 module generates an interrupt at the end of the ninth clock cycle by setting the SSP1IF bit. 9. The user loads the SSP1BUF with eight bits of data. 10. Data is shifted out the SDA pin until all eight bits are transmitted. 11. The MSSP1 module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. 12. Steps 8-11 are repeated for all transmitted data bytes. 13. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSP1CON2 register. Interrupt is generated once the Stop/Restart condition is complete.  2010-2015 Microchip Technology Inc. DS40001413E-page 251

PIC12(L)F1822/16(L)F1823 FIGURE 25-28: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) ACKSTAT in SSP1CON2 = 1 P ared by software K e C 9 Cl > A 6 2< D0 8 e N n slave, clear ACKSTAT bit SSP1CO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared by software service routifrom SSP1 interrupt SSP1BUF is written by software om D7 1 1IF Fr w SP o S = 0 SCL held lwhile CPUsponds to CK re = 0 A W 9 are R/W A1 ess and R/ 78 d by hardw ave A2 addr 6 eare P1CON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSP1BUF written with 7-bit start transmit 12345 Cleared by software SSP1BUF written After Start condition, SEN cl Sn Write SStart co S T<0>) A T S 1 1IF SSP SDA SCL SSP BF ( SEN PEN R/W DS40001413E-page 252  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 25.6.7 I2C MASTER MODE RECEPTION 8. User sets the RCEN bit of the SSP1CON2 regis- ter and the Master clocks in a byte from the slave. Master mode reception (Figure25-29) is enabled by programming the Receive Enable bit, RCEN bit of the 9. After the eighth falling edge of SCL, SSP1IF and SSP1CON2 register. BF are set. 10. Master clears SSP1IF and reads the received Note: The MSSP1 module must be in an Idle byte from SSP1UF, clears BF. state before the RCEN bit is set or the 11. Master sets ACK value sent to slave in ACKDT RCEN bit will be disregarded. bit of the SSP1CON2 register and initiates the The Baud Rate Generator begins counting and on each ACK by setting the ACKEN bit. rollover, the state of the SCL pin changes 12. Masters ACK is clocked out to the Slave and (high-to-low/low-to-high) and data is shifted into the SSP1IF is set. SSP1SR. After the falling edge of the eighth clock, the 13. User clears SSP1IF. receive enable flag is automatically cleared, the con- 14. Steps 8-13 are repeated for each received byte tents of the SSP1SR are loaded into the SSP1BUF, the from the slave. BF flag bit is set, the SSP1IF flag bit is set and the Baud Rate Generator is suspended from counting, holding 15. Master sends a not ACK or Stop to end communication. SCL low. The MSSP1 is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSP1CON2 register. 25.6.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSP1BUF from SSP1SR. It is cleared when the SSP1BUF register is read. 25.6.7.2 SSP1OV Status Flag In receive operation, the SSP1OV bit is set when eight bits are received into the SSP1SR and the BF flag bit is already set from a previous reception. 25.6.7.3 WCOL Status Flag If the user writes the SSP1BUF when a receive is already in progress (i.e., SSP1SR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). 25.6.7.4 Typical Receive Sequence: 1. The user generates a Start condition by setting the SEN bit of the SSP1CON2 register. 2. SSP1IF is set by hardware on completion of the Start. 3. SSP1IF is cleared by software. 4. User writes SSP1BUF with the slave address to transmit and the R/W bit set. 5. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSP1BUF is written to. 6. The MSSP1 module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. 7. The MSSP1 module generates an interrupt at the end of the ninth clock cycle by setting the SSP1IF bit.  2010-2015 Microchip Technology Inc. DS40001413E-page 253

PIC12(L)F1822/16(L)F1823 FIGURE 25-29: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) pt Write to SSP1CON2<4>to start Acknowledge sequenceSDA = ACKDT (SSP1CON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from MasterMaster configured as a receiverSDA = ACKDT = SDA = ACKDT = 10by programming SSP1CON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten hereom Slavenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1ACKD0WACK Bus masterACK is not sentterminatestransfer9967895876512343124PSet SSP1IF at endData shifted in on falling edge of CLKof receiveSet SSP1IF interruat end of Acknow-Set SSP1IF interruptSet SSP1IF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared by softwareCleared by softwareCleared by software(SSP1STAT<4>)Cleared insoftwareand SSP1IF Last bit is shifted into SSP1SR andcontents are unloaded into SSP1BUF SSP1OV is set becauseSSP1BUF is still full Master configured as a receiverRCEN clearedACK from MasterRCEN clearedSDA\ = ACKDT = automatically0by programming SSP1CON2<3> (RCEN = )automatically1 K fr R/ 8 AC A1 7 e, Write to SSP1CON2<0>(SEN = ),1begin Start condition SEN = 0Write to SSP1BUF occurs herstart XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 361245SCLS SSP1IF Cleared by softwareSDA = , SCL = 01while CPU responds to SSP1IF BF (SSP1STAT<0>) SSP1OV ACKEN RCEN DS40001413E-page 254  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 25.6.8 ACKNOWLEDGE SEQUENCE 25.6.9 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSP1CON2 register. At the end of a SSP1CON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDA pin. If the user wishes to gen- the master will assert the SDA line low. When the SDA erate an Acknowledge, then the ACKDT bit should be line is sampled low, the Baud Rate Generator is cleared. If not, the user should set the ACKDT bit before reloaded and counts down to ‘0’. When the Baud Rate starting an Acknowledge sequence. The Baud Rate Generator times out, the SCL pin will be brought high Generator then counts for one rollover period (TBRG) and one TBRG (Baud Rate Generator rollover count) and the SCL pin is deasserted (pulled high). When the later, the SDA pin will be deasserted. When the SDA SCL pin is sampled high (clock arbitration), the Baud pin is sampled high while SCL is high, the P bit of the Rate Generator counts for TBRG. The SCL pin is then SSP1STAT register is set. A TBRG later, the PEN bit is pulled low. Following this, the ACKEN bit is automatically cleared and the SSP1IF bit is set (Figure25-31). cleared, the Baud Rate Generator is turned off and the 25.6.9.1 WCOL Status Flag MSSP1 module then goes into Idle mode (Figure25-30). If the user writes the SSP1BUF when a Stop sequence is in progress, then the WCOL bit is set and the 25.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does If the user writes the SSP1BUF when an Acknowledge not occur). sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 25-30: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSP1CON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSP1IF Cleared in SSP1IF set at Cleared in software the end of receive software SSP1IF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 25-31: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSP1CON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSP1STAT<4>) is set. Falling edge of PEN bit (SSP1CON2<2>) is cleared by 9th clock hardware and the SSP1IF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period.  2010-2015 Microchip Technology Inc. DS40001413E-page 255

PIC12(L)F1822/16(L)F1823 25.6.10 SLEEP OPERATION 25.6.13 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C slave module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP1 interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 25.6.11 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and A Reset disables the MSSP1 module and terminates another master asserts a ‘0’. When the SCL pin floats the current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, 25.6.12 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCL1IF, and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure25-32). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP1 module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit of the SSP1STAT register is SSP1BUF can be written to. When the user services set, or the bus is Idle, with both the S and P bits clear. the bus collision Interrupt Service Routine and if the I2C When the bus is busy, enabling the SSP interrupt will bus is free, the user can resume communication by generate the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge condi- monitored for arbitration to see if the signal level is the tion was in progress when the bus collision occurred, the expected output level. This check is performed by condition is aborted, the SDA and SCL lines are deas- hardware with the result placed in the BCL1IF bit. serted and the respective control bits in the SSP1CON2 register are cleared. When the user services the bus col- The states where arbitration can be lost are: lision Interrupt Service Routine and if the I2C bus is free, • Address Transfer the user can resume communication by asserting a Start • Data Transfer condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSP1IF bit will be set. • An Acknowledge Condition A write to the SSP1BUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSP1STAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 25-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data does not match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCL1IF) BCL1IF DS40001413E-page 256  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 25.6.13.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure25-35). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure25-33). counts down to zero; if the SCL pin is sampled as ‘0’ b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the (Figure25-34). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a fac- pins are monitored. tor during a Start condition is that no two bus masters can assert a Start condition If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: at the exact same time. Therefore, one master will always assert SDA before the • the Start condition is aborted, other. This condition does not cause a bus • the BCL1IF flag is set and collision because the two masters must be • the MSSP1 module is reset to its Idle state allowed to arbitrate the first address fol- (Figure25-33). lowing the Start condition. If the address is The Start condition begins with the SDA and SCL pins the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded and counts down. If the Start or Stop conditions. SCL pin is sampled low while SDA is high, a bus colli- sion occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 25-33: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCL1IF, S bit and SSP1IF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP1 module reset into Idle state. SEN SDA sampled low before Start condition. Set BCL1IF. S bit and SSP1IF set because BCL1IF SDA = 0, SCL = 1. SSP1IF and BCL1IF are cleared by software S SSP1IF SSP1IF and BCL1IF are cleared by software  2010-2015 Microchip Technology Inc. DS40001413E-page 257

PIC12(L)F1822/16(L)F1823 FIGURE 25-34: BUS COLLISION DURING START CONDITION (SCL=0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCL1IF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCL1IF. BCL1IF Interrupt cleared by software S ’0’ ’0’ SSP1IF ’0’ ’0’ FIGURE 25-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSP1IF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCL1IF ’0’ S SSP1IF SDA = 0, SCL = 1, Interrupts cleared set SSP1IF by software DS40001413E-page 258  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 25.6.13.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure25-36). If SDA is sampled high, the BRG is reloaded and begins During a Repeated Start condition, a bus collision counting. If SDA goes from high-to-low before the BRG occurs if: times out, no bus collision occurs because no two a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time. from low level to high level (Case 1). If SCL goes from high-to-low before the BRG times out b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision indicating that another master is attempting to occurs. In this case, another master is attempting to transmit a data ‘1’ (Case 2). transmit a data ‘1’ during the Repeated Start condition, When the user releases SDA and the pin is allowed to see Figure25-37. float high, the BRG is loaded with SSP1ADD and If, at the end of the BRG time-out, both SCL and SDA counts down to zero. The SCL pin is then deasserted are still high, the SDA pin is driven low and the BRG is and when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 25-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCL1IF and release SDA and SCL. RSEN BCL1IF Cleared by software S ’0’ SSP1IF ’0’ FIGURE 25-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCL1IF set BCL1IF. Release SDA and SCL. Interrupt cleared by software RSEN ’0’ S SSP1IF  2010-2015 Microchip Technology Inc. DS40001413E-page 259

PIC12(L)F1822/16(L)F1823 25.6.13.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSP1ADD and a) After the SDA pin has been deasserted and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out (Case 1). occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure25-38). If the SCL pin is sampled low before SDA goes high (Case 2). low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure25-39). FIGURE 25-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCL1IF SDA SDA asserted low SCL PEN BCL1IF P ’0’ SSP1IF ’0’ FIGURE 25-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCL1IF SCL PEN BCL1IF P ’0’ SSP1IF ’0’ DS40001413E-page 260  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 25-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF 89 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 SSP1ADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 267 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 221* SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 264 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 265 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 266 SSP1MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 267 SSP1STAT SMP CKE D/A P S R/W UA BF 263 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode. * Page provides register information. Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 261

PIC12(L)F1822/16(L)F1823 25.7 BAUD RATE GENERATOR module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP1 is The MSSP1 module has a Baud Rate Generator avail- being operated in. able for clock generation in both I2C and SPI Master Table25-4 demonstrates clock rates based on modes. The Baud Rate Generator (BRG) reload value instruction cycles and the BRG value loaded into is placed in the SSP1ADD register (Register25-6). SSP1ADD. When a write occurs to SSP1BUF, the Baud Rate Generator will automatically begin counting down. EQUATION 25-1: Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will FOSC remain in its last state. FCLOCK = ------------------------------------------------- SSPxADD+14 An internal signal “Reload” in Figure25-40 triggers the value from SSP1ADD to be loaded into the BRG counter. This occurs twice for each oscillation of the FIGURE 25-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSP1M<3:0> SSP1ADD<7:0> SSP1M<3:0> Reload Reload SCL Control SSP1CLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSP1ADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 25-4: MSSP1 CLOCK RATE W/BRG FCLOCK FOSC FCY BRG Value (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note 1: Refer to the I/O port electrical and timing specifications in Table30-4 and Figure30-7 to ensure the system is designed to support the I/O requirements. DS40001413E-page 262  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 25-1: SSP1STAT: SSP1 STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I 2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I 2 C™ mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP1 is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSP1ADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSP1BUF is full 0 = Receive not complete, SSP1BUF is empty Transmit (I 2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty  2010-2015 Microchip Technology Inc. DS40001413E-page 263

PIC12(L)F1822/16(L)F1823 REGISTER 25-2: SSP1CON1: SSP1 CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 WCOL SSP1OV SSP1EN CKP SSP1M<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSP1BUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSP1OV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSP1SR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register (must be cleared in software). 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSP1OV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSP1EN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I 2 C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C Master mode: Unused in this mode bit 3-0 SSP1M<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSP1ADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1))(5) 1011 = I2C firmware controlled Master mode (Slave Idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register. 2: When enabled, these pins must be properly configured as input or output. 3: When enabled, the SDA and SCL pins must be configured as inputs. 4: SSP1ADD values of 0, 1 or 2 are not supported for I2C Mode. 5: SSP1ADD value of ‘0’ is not supported. Use SSP1M = 0000 instead. DS40001413E-page 264  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 25-3: SSP1CON2: SSP1 CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCK Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).  2010-2015 Microchip Technology Inc. DS40001413E-page 265

PIC12(L)F1822/16(L)F1823 REGISTER 25-4: SSP1CON3: SSP1 CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSP1STAT register already set, SSP1OV bit of the SSP1CON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSP1OV bit only if the BF bit = 0. 0 = SSP1BUF is only updated when SSP1OV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR2 register is set, and bus goes Idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSP1CON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSP1CON1 register and SCL is held low. 0 = Data holding is disabled Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSP1OV is still set when a new byte is received and BF=1, but hardware continues to write the most recent byte to SSP1BUF. 2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. 3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. DS40001413E-page 266  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 25-5: SSP1MSK: SSP1 MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSP1ADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSP1M<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSP1ADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 25-6: SSP1ADD: MSSP1 ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pat- tern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode — Least Significant Address byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.  2010-2015 Microchip Technology Inc. DS40001413E-page 267

PIC12(L)F1822/16(L)F1823 26.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer • Half-duplex synchronous master independent of device program execution. The • Half-duplex synchronous slave EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous Interface (SCI), can be configured as a full-duplex modes asynchronous system or half-duplex synchronous • Sleep operation system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT The EUSART module implements the following terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems: with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate circuits, serial EEPROMs or other microcontrollers. • Wake-up on Break reception These devices typically do not have internal clocks for • 13-bit Break character transmit baud rate generation and require the external clock signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and receiver are shown in Figure26-1 and Figure26-2. FIGURE 26-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREG Register TXIF 8 MSb LSb TX/CK pin (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT SPEN Baud Rate Generator FOSC ÷ n TX9 BRG16 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 X 0 0 0 SPBRGH SPBRGL BRGH X 1 1 0 0 BRG16 X 1 0 1 0 DS40001413E-page 268  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 26-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN OERR RCIDL RX/DT pin MSb RSR Register LSb Panind BCuoffnetrrol DReactaovery Stop (8) 7 • • • 1 0 START Baud Rate Generator FOSC RX9 ÷ n BRG16 n + 1 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 FIFO SPBRGH SPBRGL BRGH X 1 1 0 0 FERR RX9D RCREG Register BRG16 X 1 0 1 0 8 Data Bus RCIF Interrupt RCIE The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These registers are detailed in Register26-1, Register26-2 and Register26-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output.  2010-2015 Microchip Technology Inc. DS40001413E-page 269

PIC12(L)F1822/16(L)F1823 26.1 EUSART Asynchronous Mode 26.1.1.2 Transmitting Data The EUSART transmits and receives data using the A transmission is initiated by writing a character to the standard non-return-to-zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the implemented with two levels: a VOH mark state which previous character has been completely flushed from represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXREG is immediately represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains consecutively transmitted data bits of the same value all or part of a previous character, the new character stay at the output level of that bit without returning to a data is held in the TXREG until the Stop bit of the neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending transmission port idles in the mark state. Each character character in the TXREG is then transferred to the TSR transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits or nine data bits and is always terminated by one or and Stop bit sequence commences immediately more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data following the transfer of the data to the TSR from the format is eight bits. Each transmitted bit persists for a TXREG. period of 1/(Baud Rate). An on-chip dedicated 26.1.1.3 Transmit Interrupt Flag 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system The TXIF interrupt flag bit of the PIR1 register is set oscillator. See Table26-5 for examples of baud rate whenever the EUSART transmitter is enabled and no configurations. character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR The EUSART transmits and receives the LSb first. The is busy with a character and a new character has been EUSART’s transmitter and receiver are functionally queued for transmission in the TXREG. The TXIF flag bit independent, but share the same data format and baud is not cleared immediately upon writing TXREG. TXIF rate. Parity is not supported by the hardware, but can becomes valid in the second instruction cycle following be implemented in software and stored as the ninth the write execution. Polling TXIF immediately following data bit. the TXREG write will return invalid results. The TXIF bit 26.1.1 EUSART ASYNCHRONOUS is read-only, it cannot be set or cleared by software. TRANSMITTER The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the The EUSART transmitter block diagram is shown in TXIF flag bit will be set whenever the TXREG is empty, Figure26-1. The heart of the transmitter is the serial regardless of the state of TXIE enable bit. Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from To use interrupts when transmitting data, set the TXIE the transmit buffer, which is the TXREG register. bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character 26.1.1.1 Enabling the Transmitter of the transmission to the TXREG. The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: • TXEN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note1: The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set. DS40001413E-page 270  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 26.1.1.4 TSR Status 26.1.1.6 Asynchronous Transmission Set-up: The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRGL register pair and status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired TRMT bit is set when the TSR register is empty and is baud rate (see Section26.3 “EUSART Baud cleared when a character is transferred to the TSR Rate Generator (BRG)”). register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit. No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 con- poll this bit to determine the TSR status. trol bit. A set ninth data bit will indicate that the Note: The TSR register is not mapped in data eight Least Significant data bits are an address memory, so it is not available to the user. when the receiver is set for address detection. 4. Enable the transmission by setting the TXEN 26.1.1.5 Transmitting 9-Bit Characters control bit. This will cause the TXIF interrupt bit The EUSART supports 9-bit character transmissions. to be set. When the TX9 bit of the TXSTA register is set, the 5. If interrupts are desired, set the TXIE interrupt EUSART will shift nine bits out for each character trans- enable bit of the PIE1 register. An interrupt will mitted. The TX9D bit of the TXSTA register is the ninth, occur immediately provided that the GIE and and Most Significant, data bit. When transmitting 9-bit PEIE bits of the INTCON register are also set. data, the TX9D data bit must be written before writing 6. If 9-bit transmission is selected, the ninth bit the eight Least Significant bits into the TXREG. All nine should be loaded into the TX9D data bit. bits of data will be transferred to the TSR shift register 7. Load 8-bit data into the TXREG register. This immediately after the TXREG is written. will start the transmission. A special 9-bit Address mode is available for use with multiple receivers. See Section26.1.2.7 “Address Detection” for more information on the address mode. FIGURE 26-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) FIGURE 26-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Transmit Buffer Reg. Empty Flag) 1 TCY TRMT bit Word 1 Word 2 (Transmit Shift Transmit Shift Reg. Transmit Shift Reg. Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions.  2010-2015 Microchip Technology Inc. DS40001413E-page 271

PIC12(L)F1822/16(L)F1823 TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 279 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 89 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278 SPBRGL BRG<7:0> 280* SPBRGH BRG<15:8> 280* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 TXREG EUSART Transmit Data Register 270* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission. * Page provides register information. Note 1: PIC16(L)F1823 only. DS40001413E-page 272  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 26.1.2 EUSART ASYNCHRONOUS 26.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit, systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data Figure26-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts the baud rate, whereas the serial Receive Shift character reception, without generating an error, and Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data are immediately transferred to a two character recovery circuit counts a full bit time to the center of the First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. start of a third character before software must start This repeats until all data bits have been sampled and servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always Access to the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this 26.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this character. See Section26.1.2.4 “Receive Framing The EUSART receiver is enabled for asynchronous Error” for more information on framing errors. operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have • CREN = 1 been received, the character in the RSR is transferred • SYNC = 0 to the EUSART receive FIFO and the RCIF interrupt • SPEN = 1 flag bit of the PIR1 register is set. The top character in All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the their default state. RCREG register. Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun of the TXSTA register configures the EUSART for condition is cleared. See Section26.1.2.5 asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more RCSTA register enables the EUSART. The programmer information on overrun errors. must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. 26.1.2.3 Receive Interrupts Note1: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is cleared for the receiver to function. an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: • RCIE interrupt enable bit of the PIE1 register • PEIE peripheral interrupt enable bit of the INTCON register • GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.  2010-2015 Microchip Technology Inc. DS40001413E-page 273

PIC12(L)F1822/16(L)F1823 26.1.2.4 Receive Framing Error 26.1.2.7 Address Detection Each character in the receive FIFO buffer has a A special Address Detection mode is available for use corresponding framing error Status bit. A framing error when multiple receivers share the same transmission indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA FERR bit of the RCSTA register. The FERR bit register. represents the status of the top unread character in the Address detection requires 9-bit character reception. receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters before reading the RCREG. with the ninth data bit set will be transferred to the The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt unread character in the receive FIFO. A framing error bit. All other characters will be ignored. (FERR = 1) does not preclude reception of additional Upon receiving an address character, user software characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon Reading the next character from the FIFO buffer will address match, user software must disable address advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next corresponding framing error. Stop bit occurs. When user software detects the end of The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit. affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. 26.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 26.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG. DS40001413E-page 274  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 26.1.2.8 Asynchronous Reception Set-up: 26.1.2.9 9-bit Address Detection Mode Set-up 1. Initialize the SPBRGH, SPBRGL register pair This mode would typically be used in RS-485 systems. and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section26.3 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRGL register pair 2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the 3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section26.3 “EUSART The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”). operation. 2. Clear the ANSEL bit for the RX pin (if applicable). 4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit. PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous INTCON register. operation. 5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the 6. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the 7. The RCIF interrupt flag bit will be set when a INTCON register. character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit. receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN the RCIE interrupt enable bit was also set. bit. 8. Read the RCSTA register to get the error flags 7. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit register. was also set. 10. If an overrun occurred, clear the OERR flag by 9. Read the RCSTA register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. FIGURE 26-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg. Word 1 Word 2 RCREG RCREG RCIDL Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.  2010-2015 Microchip Technology Inc. DS40001413E-page 275

PIC12(L)F1822/16(L)F1823 TABLE 26-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 279 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 87 RCREG EUSART Receive Data Register 273* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278 SPBRGL BRG<7:0> 280* SPBRGH BRG<15:8> 280* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Reception. * Page provides register information. Note 1: PIC16(L)F1823 only. DS40001413E-page 276  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 26.2 Clock Accuracy with The first (preferred) method uses the OSCTUNE Asynchronous Operation register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution The factory calibrates the internal oscillator block out- changes to the system clock source. See Section5.2.2 put (INTOSC). However, the INTOSC frequency may “Internal Clock Sources” for more information. drift as VDD or temperature changes, and this directly The other method adjusts the value in the Baud Rate affects the asynchronous baud rate. Two methods may Generator. This can be done automatically with the be used to adjust the baud rate clock, but both require Auto-Baud Detect feature (see Section26.3.1 a reference clock source of some kind. “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. REGISTER 26-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 277

PIC12(L)F1822/16(L)F1823 REGISTER 26-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001413E-page 278  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 26-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2010-2015 Microchip Technology Inc. DS40001413E-page 279

PIC12(L)F1822/16(L)F1823 26.3 EUSART Baud Rate Generator EXAMPLE 26-1: CALCULATING BAUD (BRG) RATE ERROR The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. FOSC Desired Baud Rate = ------------------------------------------------------------------------ By default, the BRG operates in 8-bit mode. Setting the 64[SPBRGH:SPBRGL]+1 BRG16 bit of the BAUDCON register selects 16-bit Solving for SPBRGH:SPBRGL: mode. FOSC The SPBRGH, SPBRGL register pair determines the --------------------------------------------- Desired Baud Rate period of the free running baud rate timer. In X = ---------------------------------------------–1 64 Asynchronous mode the multiplier of the baud rate 16000000 period is determined by both the BRGH bit of the TXSTA ------------------------ 9600 register and the BRG16 bit of the BAUDCON register. In = ------------------------–1 64 Synchronous mode, the BRGH bit is ignored. = 25.042 = 25 Table26-3 contains the formulas for determining the baud rate. Example26-1 provides a sample calculation 16000000 Calculated Baud Rate = --------------------------- for determining the baud rate and baud rate error. 6425+1 Typical baud rates and error values for various = 9615 asynchronous modes have been computed for your convenience and are shown in Table26-3. It may be Calc. Baud Rate–Desired Baud Rate Error = -------------------------------------------------------------------------------------------- advantageous to use the high baud rate (BRGH = 1), Desired Baud Rate or the 16-bit BRG (BRG16 = 1) to reduce the baud rate 9615–9600 error. The 16-bit BRG mode is used to achieve slow = ---------------------------------- = 0.16% 9600 baud rates for fast oscillator frequencies. Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock. DS40001413E-page 280  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 26-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair. TABLE 26-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 279 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278 SPBRGL BRG<7:0> 280* SPBRGH BRG<15:8> 280* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator. * Page provides register information.  2010-2015 Microchip Technology Inc. DS40001413E-page 281

PIC12(L)F1822/16(L)F1823 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 DS40001413E-page 282  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — —  2010-2015 Microchip Technology Inc. DS40001413E-page 283

PIC12(L)F1822/16(L)F1823 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — — DS40001413E-page 284  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 26.3.1 AUTO-BAUD DETECT and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. Note1: If the WUE bit is set with the ABDEN bit, In the Auto-Baud Detect (ABD) mode, the clock to the auto-baud detection will occur on the byte BRG is reversed. Rather than the BRG clocking the following the Break character (see incoming RX signal, the RX signal is timing the BRG. Section26.3.3 “Auto-Wake-up on The Baud Rate Generator is used to time the period of Break”). a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the that it has five rising edges including the Stop bit edge. incoming character baud rate is within the range of the selected BRG clock source. Setting the ABDEN bit of the BAUDCON register starts Some combinations of oscillator frequency the auto-baud calibration sequence (Figure26-6). and EUSART baud rates are not possible. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of 3: During the auto-baud process, the the receive line, after the Start bit, the SPBRG begins auto-baud counter starts counting at 1. counting up using the BRG counter clock as shown in Upon completion of the auto-baud Table26-6. The fifth rising edge will occur on the RX pin sequence, to achieve maximum accuracy, at the end of the eighth bit period. At that time, an subtract 1 from the SPBRGH:SPBRGL accumulated value totaling the proper BRG period is register pair. left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag TABLE 26-6: BRG COUNTER CLOCK RATES is set. The value in the RCREG needs to be read to BRG Base BRG ABD clear the RCIF interrupt. RCREG content should be BRG16 BRGH Clock Clock discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the 0 0 FOSC/64 FOSC/512 SPBRGL register did not overflow by checking for 00h 0 1 FOSC/16 FOSC/128 in the SPBRGH register. 1 0 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table26-6. During ABD, 1 1 FOSC/4 FOSC/32 both the SPBRGH and SPBRGL registers are used as Note: During the ABD sequence, SPBRGL and a 16-bit counter, independent of the BRG16 bit setting. SPBRGH registers are both used as a 16-bit While calibrating the baud rate period, the SPBRGH counter, independent of BRG16 setting. FIGURE 26-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL XXh 1Ch SPBRGH XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 285

PIC12(L)F1822/16(L)F1823 26.3.2 AUTO-BAUD OVERFLOW 26.3.3.1 Special Considerations During the course of automatic baud detection, the Break Character ABDOVF bit of the BAUDCON register will be set if the To avoid character errors or character fragments during baud rate counter overflows before the fifth rising edge a wake-up event, the wake-up character must be all is detected on the RX pin. The ABDOVF bit indicates zeros. that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register When the wake-up is enabled the function works pair. After the ABDOVF has been set, the counter con- independent of the low time on the data stream. If the tinues to count until the fifth rising edge is detected on WUE bit is set and a valid non-zero character is the RX pin. Upon detecting the fifth RX edge, the hard- received, the low time from the Start bit to the first rising ware will set the RCIF interrupt flag and clear the edge will be interpreted as the wake-up event. The ABDEN bit of the BAUDCON register. The RCIF flag remaining bits in the character will be received as a can be subsequently cleared by reading the RCREG fragmented character and subsequent characters can register. The ABDOVF flag of the BAUDCON register result in framing or overrun errors. can be cleared by software directly. Therefore, the initial character in the transmission must To terminate the auto-baud process before the RCIF be all ‘0’s. This must be 10 or more bit times, 13-bit flag is set, clear the ABDEN bit then clear the ABDOVF times recommended for LIN bus, or any number of bit bit of the BAUDCON register. The ABDOVF bit will times for standard RS-232 devices. remain set if the ABDEN bit is not cleared first. Oscillator Start-up Time Oscillator start-up time must be considered, especially 26.3.3 AUTO-WAKE-UP ON BREAK in applications using oscillators with longer start-up During Sleep mode, all clocks to the EUSART are intervals (i.e., LP, XT or HS/PLL mode). The Sync suspended. Because of this, the Baud Rate Generator Break (or wake-up signal) character must be of is inactive and a proper character reception cannot be sufficient length, and be followed by a sufficient performed. The Auto-Wake-up feature allows the interval, to allow enough time for the selected oscillator controller to wake-up due to activity on the RX/DT line. to start and provide proper initialization of the EUSART. This feature is available only in Asynchronous mode. WUE Bit The Auto-Wake-up feature is enabled by setting the The wake-up event causes a receive interrupt by WUE bit of the BAUDCON register. Once set, the normal setting the RCIF bit. The WUE bit is cleared in receive sequence on RX/DT is disabled, and the hardware by a rising edge on RX/DT. The interrupt EUSART remains in an Idle state, monitoring for a condition is then cleared in software by reading the wake-up event independent of the CPU mode. A RCREG register and discarding its contents. wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break To ensure that no actual data is lost, check the RCIDL or a wake-up signal character for the LIN protocol.) bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not The EUSART module generates an RCIF interrupt occurring, the WUE bit may then be set just prior to coincident with the wake-up event. The interrupt is entering the Sleep mode. generated synchronously to the Q clocks in normal CPU operating modes (Figure26-7), and asynchronously if the device is in Sleep mode (Figure26-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. DS40001413E-page 286  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 26-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 26-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RX/DT Line Note 1 RCIF Cleared due to User Read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set.  2010-2015 Microchip Technology Inc. DS40001413E-page 287

PIC12(L)F1822/16(L)F1823 26.3.4 BREAK CHARACTER SEQUENCE 26.3.5 RECEIVING A BREAK CHARACTER The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break special Break character sequences that are required by character in two ways. the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the Received data To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is bits of the TXSTA register. The Break character trans- assumed to have been initialized to the expected baud mission is then initiated by a write to the TXREG. The rate. value of data written to TXREG will be ignored and all A Break character has been received when; ‘0’s will be transmitted. • RCIF bit is set The SENDB bit is automatically reset by hardware after • FERR bit is set the corresponding Stop bit is sent. This allows the user • RCREG = 00h to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature character in the LIN specification). described in Section26.3.3 “Auto-Wake-up on Break”. By enabling this feature, the EUSART will The TRMT bit of the TXSTA register indicates when the sample the next two transitions on RX/DT, cause an transmit operation is active or Idle, just as it does during RCIF interrupt, and receive the next data byte followed normal transmission. See Figure26-9 for the timing of by another interrupt. the Break character sequence. Note that following a Break character, the user will 26.3.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature. The following sequence will start a message frame For both methods, the user can set the ABDEN bit of header made up of a Break, followed by an auto-baud the BAUDCON register before placing the EUSART in Sync byte. This sequence is typical of a LIN bus Sleep mode. master. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to enable the Break sequence. 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. FIGURE 26-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit) DS40001413E-page 288  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 26.4 EUSART Synchronous Mode 26.4.1.2 Clock Polarity Synchronous serial communications are typically used A clock polarity option is provided for Microwire in systems with a single master and one or more compatibility. Clock polarity is selected with the SCKP slaves. The master device contains the necessary bit of the BAUDCON register. Setting the SCKP bit sets circuitry for baud rate generation and supplies the clock the clock Idle state as high. When the SCKP bit is set, for all devices in the system. Slave devices can take the data changes on the falling edge of each clock. advantage of the master clock by eliminating the inter- Clearing the SCKP bit sets the Idle state as low. When nal clock generation circuitry. the SCKP bit is cleared, the data changes on the rising edge of each clock. There are two signal lines in Synchronous mode: a bidi- rectional data line and a clock line. Slaves use the 26.4.1.3 Synchronous Master Transmission external clock supplied by the master to shift the serial Data is transferred out of the device on the RX/DT pin. data into and out of their respective receive and trans- The RX/DT and TX/CK pin output drivers are automat- mit shift registers. Since the data line is bidirectional, ically enabled when the EUSART is configured for synchronous operation is half-duplex only. Half-duplex synchronous master transmit operation. refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. A transmission is initiated by writing a character to the The EUSART can operate as either a master or slave TXREG register. If the TSR still contains all or part of a device. previous character the new character data is held in the TXREG until the last bit of the previous character has Start and Stop bits are not used in synchronous been transmitted. If this is the first character, or the pre- transmissions. vious character has been completely flushed from the 26.4.1 SYNCHRONOUS MASTER MODE TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character com- The following bits are used to configure the EUSART mences immediately following the transfer of the data for Synchronous Master operation: to the TSR from the TXREG. • SYNC = 1 Each data bit changes on the leading edge of the • CSRC = 1 master clock and remains valid until the subsequent • SREN = 0 (for transmit); SREN = 1 (for receive) leading clock edge. • CREN = 0 (for transmit); CREN = 1 (for receive) Note: The TSR register is not mapped in data • SPEN = 1 memory, so it is not available to the user. Setting the SYNC bit of the TXSTA register configures 26.4.1.4 Synchronous Master Transmission the device for synchronous operation. Setting the CSRC Set-up: bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA 1. Initialize the SPBRGH, SPBRGL register pair register ensures that the device is in the Transmit mode, and the BRGH and BRG16 bits to achieve the otherwise the device will be configured to receive. Setting desired baud rate (see Section26.3 “EUSART the SPEN bit of the RCSTA register enables the Baud Rate Generator (BRG)”). EUSART. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 26.4.1.1 Master Clock 3. Disable Receive mode by clearing bits SREN Synchronous data transfers use a separate clock line, and CREN. which is synchronous with the data. A device config- 4. Enable Transmit mode by setting the TXEN bit. ured as a master transmits the clock on the TX/CK line. 5. If 9-bit transmission is desired, set the TX9 bit. The TX/CK pin output driver is automatically enabled 6. If interrupts are desired, set the TXIE bit of the when the EUSART is configured for synchronous PIE1 register and the GIE and PEIE bits of the transmit or receive operation. Serial data bits change INTCON register. on the leading edge to ensure they are valid at the trail- ing edge of each clock. One clock cycle is generated 7. If 9-bit transmission is selected, the ninth bit for each data bit. Only as many clock cycles are gener- should be loaded in the TX9D bit. ated as there are data bits. 8. Start transmission by loading data to the TXREG register.  2010-2015 Microchip Technology Inc. DS40001413E-page 289

PIC12(L)F1822/16(L)F1823 FIGURE 26-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 26-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 26-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 279 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 89 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278 SPBRGL BRG<7:0> 280* SPBRGH BRG<15:8> 280* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 TXREG EUSART Transmit Data Register 270* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Transmission. * Page provides register information. Note 1: PIC16(L)F1823 only. DS40001413E-page 290  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 26.4.1.5 Synchronous Master Reception buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit Data is received at the RX/DT pin. The RX/DT pin can only be cleared by clearing the overrun condition. output driver is automatically disabled when the If the overrun error occurred when the SREN bit is set EUSART is configured for synchronous master receive and CREN is clear then the error is cleared by reading operation. RCREG. If the overrun occurred when the CREN bit is In Synchronous mode, reception is enabled by setting set then the error condition is cleared by either clearing either the Single Receive Enable bit (SREN of the the CREN bit of the RCSTA register or by clearing the RCSTA register) or the Continuous Receive Enable bit SPEN bit which resets the EUSART. (CREN of the RCSTA register). 26.4.1.8 Receiving 9-bit Characters When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a The EUSART supports 9-bit character reception. When single character. The SREN bit is automatically cleared the RX9 bit of the RCSTA register is set the EUSART at the completion of one character. When CREN is set, will shift nine bits into the RSR for each character clocks are continuously generated until CREN is received. The RX9D bit of the RCSTA register is the cleared. If CREN is cleared in the middle of a character ninth, and Most Significant, data bit of the top unread the CK clock stops immediately and the partial charac- character in the receive FIFO. When reading 9-bit data ter is discarded. If SREN and CREN are both set, then from the receive FIFO buffer, the RX9D data bit must SREN is cleared at the completion of the first character be read before reading the eight Least Significant bits and CREN takes precedence. from the RCREG. To initiate reception, set either SREN or CREN. Data is 26.4.1.9 Synchronous Master Reception sampled at the RX/DT pin on the trailing edge of the Set-up: TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is 1. Initialize the SPBRGH, SPBRGL register pair for received into the RSR, the RCIF bit is set and the char- the appropriate baud rate. Set or clear the acter is automatically transferred to the two character BRGH and BRG16 bits, as required, to achieve receive FIFO. The Least Significant eight bits of the top the desired baud rate. character in the receive FIFO are available in RCREG. 2. Clear the ANSEL bit for the RX pin (if applicable). The RCIF bit remains set as long as there are unread 3. Enable the synchronous master serial port by characters in the receive FIFO. setting bits SYNC, SPEN and CSRC. Note: If the RX/DT function is on an analog pin, 4. Ensure bits CREN and SREN are clear. the corresponding ANSEL bit must be 5. If interrupts are desired, set the RCIE bit of the cleared for the receiver to function. PIE1 register and the GIE and PEIE bits of the INTCON register. 26.4.1.6 Slave Clock 6. If 9-bit reception is desired, set bit RX9. Synchronous data transfers use a separate clock line, 7. Start reception by setting the SREN bit or for which is synchronous with the data. A device configured continuous reception, set the CREN bit. as a slave receives the clock on the TX/CK line. The 8. Interrupt flag bit RCIF will be set when reception TX/CK pin output driver is automatically disabled when of a character is complete. An interrupt will be the device is configured for synchronous slave transmit generated if the enable bit RCIE was set. or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge 9. Read the RCSTA register to get the ninth bit (if of each clock. One data bit is transferred for each clock enabled) and determine if any error occurred cycle. Only as many clock cycles should be received as during reception. there are data bits. 10. Read the 8-bit received data by reading the RCREG register. Note: If the device is configured as a slave and 11. If an overrun error occurs, clear the error by the TX/CK function is on an analog pin, the either clearing the CREN bit of the RCSTA corresponding ANSEL bit must be register or by clearing the SPEN bit which resets cleared. the EUSART. 26.4.1.7 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO  2010-2015 Microchip Technology Inc. DS40001413E-page 291

PIC12(L)F1822/16(L)F1823 FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 26-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 279 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 89 RCREG EUSART Receive Data Register 273* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278 SPBRGL BRG<7:0> 280* SPBRGH BRG<15:8> 280* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception. * Page provides register information. Note 1: PIC16(L)F1823 only. DS40001413E-page 292  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 26.4.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the EUSART for Synchronous slave operation: 1. The first character will immediately transfer to the TSR register and transmit. • SYNC = 1 2. The second word will remain in TXREG register. • CSRC = 0 3. The TXIF bit will not be set. • SREN = 0 (for transmit); SREN = 1 (for receive) 4. After the first character has been shifted out of • CREN = 0 (for transmit); CREN = 1 (for receive) TSR, the TXREG register will transfer the second • SPEN = 1 character to the TSR and the TXIF bit will now be Setting the SYNC bit of the TXSTA register configures the set. device for synchronous operation. Clearing the CSRC bit 5. If the PEIE and TXIE bits are set, the interrupt of the TXSTA register configures the device as a slave. will wake the device from Sleep and execute the Clearing the SREN and CREN bits of the RCSTA register next instruction. If the GIE bit is also set, the ensures that the device is in the Transmit mode, program will call the Interrupt Service Routine. otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the 26.4.2.2 Synchronous Slave Transmission EUSART. Set-up: 26.4.2.1 EUSART Synchronous Slave 1. Set the SYNC and SPEN bits and clear the CSRC bit. Transmit 2. Clear the ANSEL bit for the CK pin (if applicable). The operation of the Synchronous Master and Slave 3. Clear the CREN and SREN bits. modes are identical (see Section26.4.1.3 “Synchronous Master Transmission”), except in the 4. If interrupts are desired, set the TXIE bit of the case of the Sleep mode. PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit transmission is desired, set the TX9 bit. 6. Enable transmission by setting the TXEN bit. 7. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 8. Start transmission by writing the Least Significant eight bits to the TXREG register. TABLE 26-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 279 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 89 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 TXREG EUSART Transmit Data Register 270* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. * Page provides register information. Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 293

PIC12(L)F1822/16(L)F1823 26.4.2.3 EUSART Synchronous Slave 26.4.2.4 Synchronous Slave Reception Reception Set-up: The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the modes is identical (Section26.4.1.5 “Synchronous CSRC bit. Master Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins • Sleep (if applicable). • CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RCIE bit of the never Idle PIE1 register and the GIE and PEIE bits of the INTCON register. • SREN bit, which is a “don’t care” in Slave mode 4. If 9-bit reception is desired, set the RX9 bit. A character may be received while in Sleep mode by 5. Set the CREN bit to enable reception. setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data 6. The RCIF bit will be set when reception is to the RCREG register. If the RCIE enable bit is set, the complete. An interrupt will be generated if the interrupt generated will wake the device from Sleep RCIE bit was set. and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTA register. 8. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 26-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 279 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 89 RCREG EUSART Receive Data Register 273* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception. * Page provides register information. Note 1: PIC16(L)F1823 only. DS40001413E-page 294  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 26.5 EUSART Operation During Sleep 26.5.2 SYNCHRONOUS TRANSMIT DURING SLEEP The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the To transmit during Sleep, all the following conditions system clock and therefore cannot generate the must be met before entering Sleep mode: necessary signals to run the Transmit or Receive Shift • RCSTA and TXSTA Control registers must be registers during Sleep. configured for Synchronous Slave Transmission Synchronous Slave mode uses an externally generated (see Section26.4.2.2 “Synchronous Slave clock to run the Transmit and Receive Shift registers. Transmission Set-up:”). • The TXIF interrupt flag must be cleared by writing 26.5.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the SLEEP TSR and transmit buffer. To receive during Sleep, all the following conditions • If interrupts are desired, set the TXIE bit of the must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON register. • RCSTA and TXSTA Control registers must be • Interrupt enable bits TXIE of the PIE1 register and configured for Synchronous Slave Reception (see PEIE of the INTCON register must set. Section26.4.2.4 “Synchronous Slave Reception Set-up:”). Upon entering Sleep mode, the device will be ready to • If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the PIE1 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been INTCON register. completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and • The RCIF interrupt flag must be cleared by read- the TXIF flag will be set. Thereby, waking the processor ing RCREG to unload any pending characters in from Sleep. At this point, the TXREG is available to the receive buffer. accept another character for transmission, which will Upon entering Sleep mode, the device will be ready to clear the TXIF flag. accept data and clocks on the RX/DT and TX/CK pins, Upon waking from Sleep, the instruction following the respectively. When the data word has been completely SLEEP instruction will be executed. If the Global clocked in by the external device, the RCIF interrupt Interrupt Enable (GIE) bit is also set then the Interrupt flag bit of the PIR1 register will be set. Thereby, waking Service Routine at address 0004h will be called. the processor from Sleep. Upon waking from Sleep, the instruction following the 26.5.3 ALTERNATE PIN LOCATIONS SLEEP instruction will be executed. If the GIE global This module incorporates I/O pins that can be moved to interrupt enable bit of the INTCON register is also set, other locations with the use of the alternate pin function then the Interrupt Service Routine at address 004h will register APFCON. To determine which pins can be be called. moved and what their default locations are upon a reset, see Section12.1 “Alternate Pin Function”for more information.  2010-2015 Microchip Technology Inc. DS40001413E-page 295

PIC12(L)F1822/16(L)F1823 27.0 CAPACITIVE SENSING (CPS) MODULE The Capacitive Sensing (CPS) module allows for an interaction with an end user without a mechanical interface. In a typical application, the CPS module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the CPS module. The CPS module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: • Analog MUX for monitoring multiple inputs • Capacitive sensing oscillator • Multiple current ranges • Multiple voltage reference modes • Multiple timer resources • Software control • Operation during Sleep FIGURE 27-1: CAPACITIVE SENSING BLOCK DIAGRAM Timer0 Module Set TMR0CS T0XCS TMR0IF FOSC/4 0 Overflow T0CKI 0 TMR0 1 CPSCH<3:0> 1 CPSON(2) CPSRNG<1:0> CPSON Capacitive Sensing Timer1 Module CPS0 Oscillator T1CS<1:0> CPS1 CPSOSC CPS2 FOSC CPS3 CPSCLK FOSC/4 0 Int. CPS4(1) Ref- DAC_output Ref. T1OSC/ EN TMR1H:TMR1L CPS5(1) 1 CPSOUT T1CKI CPS6(1) 0 T1GSEL<1:0> CPS7(1) Ref+ FVR T1G 1 Buffer2 Timer1 Gate sync_C1OUT Control Logic sync_C2OUT CPSRM Note 1: Reference CPSCON1 register (Register27-2) for channels implemented on each device. 2: If CPSON=0, disabling capacitive sensing, no channel is selected. DS40001413E-page 296  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 27-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM Oscillator Module VDD (1) (2) + - S Q CPSCLK CPSx Analog Pin (1) (2) R - + Internal References 0 0 Ref- Ref+ 1 DAC_output 1 FVR Buffer2 CPSRM Note 1: Module Enable and Current mode selections are not shown. 2: Comparators remain active in Noise Detection mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 297

PIC12(L)F1822/16(L)F1823 27.1 Analog MUX 27.3 Voltage References The CPS module can monitor up to four inputs for the The capacitive sensing oscillator uses voltage refer- PIC12(L)F1822 (CPSCH<1:0>) and up to eight inputs ences to provide two voltage thresholds for oscillation. for the PIC16(L)F1823 (CPSCH<2:0>). See The upper voltage threshold is referred to as Ref+ and Register27-2 for details. To determine if a frequency the lower voltage threshold is referred to as Ref-. change has occurred the user must: The user can elect to use Fixed Voltage References, • Select the appropriate CPS pin by setting the which are internal to the capacitive sensing oscillator, appropriate CPSCH bits of the CPSCON1 register. or variable voltage references, which are supplied by • Set the corresponding ANSEL bit. the Fixed Voltage Reference (FVR) module and the Digital-to-Analog Converter (DAC) module. • Set the corresponding TRIS bit. • Run the software algorithm. When the Fixed Voltage References are used, the VSS voltage determines the lower threshold level (Ref-) and Selection of the CPSx pin while the module is enabled the VDD voltage determines the upper threshold level will cause the capacitive sensing oscillator to be on the (Ref+). CPSx pin. Failure to set the corresponding ANSEL and TRIS bits can cause the capacitive sensing oscillator to When the variable voltage references are used, the stop, leading to false frequency readings. DAC voltage determines the lower threshold level (Ref-) and the FVR voltage determines the upper 27.2 Capacitive Sensing Oscillator threshold level (Ref+). An advantage of using these ref- erence sources is that oscillation frequency remains The capacitive sensing oscillator consists of a constant constant with changes in VDD. current source and a constant current sink, to produce Different oscillation frequencies can be obtained a triangle waveform. The CPSOUT bit of the through the use of these variable voltage references. CPSCON0 register shows the status of the capacitive The more the upper voltage reference level is lowered sensing oscillator, whether it is a sinking or sourcing and the more the lower voltage reference level is current. The oscillator is designed to drive a capacitive raised, the higher the capacitive sensing oscillator load (single PCB pad) and at the same time, be a clock frequency becomes. source to either Timer0 or Timer1. The oscillator has three different current settings as defined by Selection between the voltage references is controlled CPSRNG<1:0> of the CPSCON0 register. The different by the CPSRM bit of the CPSCON0 register. Setting current settings for the oscillator serve two purposes: this bit selects the variable voltage references and clearing this bit selects the Fixed Voltage References. • Maximize the number of counts in a timer for a fixed time base. Please see Section14.0 “Fixed Voltage Reference (FVR)” and Section17.0 “Digital-to-Analog Converter • Maximize the count differential in the timer during (DAC) Module” for more information on configuring the a change in frequency. variable voltage levels. DS40001413E-page 298  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 27.4 Current Ranges The Noise Detection mode is unique in that it disables the constant-current source associated with the The Capacitive Sensing Oscillator can operate within selected input pin, but leaves the rest of the oscillator several different current ranges, depending on the circuitry and pin structure active. This eliminates the Voltage Reference mode and current range selections. oscillation frequency on the analog pin and greatly Within each of the two Voltage Reference modes there reduces the current consumed by the oscillator module. When noise is introduced onto the pin, the are four current ranges. oscillator is driven at the frequency determined by the Selection between the Voltage Reference modes is noise. This produces a detectable signal at the controlled by the CPSRM bit of the CPSCON0 comparator stage, indicating the presence of activity register. Clearing this bit selects the Fixed Voltage on the pin. Figure27-2 shows a more detailed drawing References provided by the capacitive sensing of the constant-current sources and comparators oscillator module. Setting this bit selects the variable associated with the oscillator and input pin. voltage references supplied by the Fixed Voltage Reference (FVR) module and the Digital-to-Analog Converter (DAC) module. See Section27.3 “Voltage References” for more information on configuring the voltage references. Selecting the current range within the Voltage Reference mode is controlled by configuring the CPSRNG<1:0> bits in the CPSCON0 register. See Table27-1 for proper current mode selection. TABLE 27-1: CURRENT MODE SELECTION CPSRM Voltage Reference Mode CPSRNG<1:0> Current Range(1) 00 Off 01 Low 0 Fixed 10 Medium 11 High 00 Noise Detection 01 Low 1 Variable 10 Medium 11 High Note 1: See Power-Down Currents (IPD) in Section30.3 “DC Characteristics: PIC16(L)F1824/8-I/E (Power-Down)” for more information.  2010-2015 Microchip Technology Inc. DS40001413E-page 299

PIC12(L)F1822/16(L)F1823 27.5 Timer Resources 27.7 Software Control To measure the change in frequency of the capacitive The software portion of the CPS module is required to sensing oscillator, a fixed time base is required. For the determine the change in frequency of the capacitive period of the fixed time base, the capacitive sensing sensing oscillator. This is accomplished by the oscillator is used to clock either Timer0 or Timer1. The following: frequency of the capacitive sensing oscillator is equal • Setting a fixed time base to acquire counts on to the number of counts in the timer divided by the Timer0 or Timer1. period of the fixed time base. • Establishing the nominal frequency for the capacitive sensing oscillator. 27.6 Fixed Time Base • Establishing the reduced frequency for the To measure the frequency of the capacitive sensing capacitive sensing oscillator due to an additional oscillator, a fixed time base is required. Any timer capacitive load. resource or software loop can be used to establish the • Set the frequency threshold. fixed time base. It is up to the end user to determine the method in which the fixed time base is generated. 27.7.1 NOMINAL FREQUENCY (NO CAPACITIVE LOAD) Note: The fixed time base can not be generated by the timer resource that the capacitive To determine the nominal frequency of the capacitive sensing oscillator is clocking. sensing oscillator: • Remove any extra capacitive load on the selected 27.6.1 TIMER0 CPSx pin. To select Timer0 as the timer resource for the CPS • At the start of the fixed time base, clear the timer module: resource. • Set the T0XCS bit of the CPSCON0 register. • At the end of the fixed time base save the value in the timer resource. • Clear the TMR0CS bit of the OPTION register. The value of the timer resource is the number of When Timer0 is chosen as the timer resource, the oscillations of the capacitive sensing oscillator for the capacitive sensing oscillator will be the clock source for given time base. The frequency of the capacitive Timer0. Refer to Section20.0 “Timer0 Module” for sensing oscillator is equal to the number of counts on additional information. in the timer divided by the period of the fixed time base. 27.6.2 TIMER1 27.7.2 REDUCED FREQUENCY To select Timer1 as the timer resource for the CPS (ADDITIONAL CAPACITIVE LOAD) module, set the TMR1CS<1:0> of the T1CON register The extra capacitive load will cause the frequency of the to ‘11’. When Timer1 is chosen as the timer resource, capacitive sensing oscillator to decrease. To determine the capacitive sensing oscillator will be the clock source for Timer1. Because the Timer1 module has a the reduced frequency of the capacitive sensing gate control, developing a time base for the frequency oscillator: measurement can be simplified by using the Timer0 • Add a typical capacitive load on the selected overflow flag. CPSx pin. It is recommend that the Timer0 overflow flag, in con- • Use the same fixed time base as the nominal junction with the Toggle mode of the Timer1 Gate, be frequency measurement. used to develop the fixed time base required by the • At the start of the fixed time base, clear the timer software portion of the CPS module. Refer to resource. Section21.12 “Timer1 Gate Control Register” for • At the end of the fixed time base save the value in additional information. the timer resource. The value of the timer resource is the number of TABLE 27-2: TIMER1 ENABLE FUNCTION oscillations of the capacitive sensing oscillator with an TMR1ON TMR1GE Timer1 Operation additional capacitive load. The frequency of the capac- itive sensing oscillator is equal to the number of counts 0 0 Off on in the timer divided by the period of the fixed time 0 1 Off base. This frequency should be less than the value 1 0 On obtained during the nominal frequency measurement. 1 1 Count Enabled by input DS40001413E-page 300  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 27.7.3 FREQUENCY THRESHOLD The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, “Software Handling for Capacitive Sensing” (DS01103) for more detailed information on the software required for CPS module. Note: For more information on general capacitive sensing refer to Application Notes: • AN1101, “Introduction to Capacitive Sensing” (DS01101) • AN1102, “Layout and Physical Design Guidelines for Capacitive Sensing” (DS01102) 27.8 Operation during Sleep The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts. Note: Timer0 does not operate when in Sleep, and therefore cannot be used for capacitive sense measurements in Sleep.  2010-2015 Microchip Technology Inc. DS40001413E-page 301

PIC12(L)F1822/16(L)F1823 REGISTER 27-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPSON: Capacitive Sensing Module Enable bit 1 = CPS module is enabled 0 = CPS module is disabled bit 6 CPSRM: Capacitive Sensing Reference Mode bit 1 = Capacitive Sensing module is in Variable Voltage Reference mode 0 = Capacitive Sensing module is in Fixed Voltage Reference mode bit 5-4 Unimplemented: Read as ‘0’ bit 3-2 CPSRNG<1:0>: Capacitive Sensing Current Range bits If CPSRM = 0 (Fixed Voltage Reference mode): 00 = Oscillator is off 01 = Oscillator is in low range 10 = Oscillator is in medium range 11 = Oscillator is in high range If CPSRM = 1 (Variable Voltage Reference mode): 00 = Oscillator is on. Noise Detection mode. No Charge/Discharge current is supplied. 01 = Oscillator is in low range 10 = Oscillator is in medium range 11 = Oscillator is in high range bit 1 CPSOUT: Capacitive Sensing Oscillator Status bit 1 = Oscillator is sourcing current (Current flowing out of the pin) 0 = Oscillator is sinking current (Current flowing into the pin) bit 0 T0XCS: Timer0 External Clock Source Select bit If TMR0CS = 1: The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0: 1 = Timer0 clock source is the capacitive sensing oscillator 0 = Timer0 clock source is the T0CKI pin If TMR0CS = 0: Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4 DS40001413E-page 302  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 REGISTER 27-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0(1) R/W-0/0 R/W-0/0 — — — — CPSCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CPSCH<3:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected. If CPSON = 1: 0000 = channel 0, (CPS0) 0001 = channel 1, (CPS1) 0010 = channel 2, (CPS2) 0011 = channel 3, (CPS3) 0100 = channel 4, (CPS4)(1) 0101 = channel 5, (CPS5)(1) 0110 = channel 6, (CPS6)(1) 0111 = channel 7, (CPS7)(1) 1000 = Reserved. Do not use. • • • 1111 = Reserved. Do not use. Note 1: These channels are only implemented on the PIC16(L)F1823.  2010-2015 Microchip Technology Inc. DS40001413E-page 303

PIC12(L)F1822/16(L)F1823 TABLE 27-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 ANSELC(1) — — — — ANSC3 ANSC2 ANSC1 ANSC0 122 CPSCON0 CPSON CPSRM — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 302 CPSCON1 — — — — CPSCH3(1) CPSCH2(1) CPSCH1 CPSCH0 303 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 164 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 173 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the CPS module. Note 1: PIC16(L)F1823 only. DS40001413E-page 304  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 28.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirec- tional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16F/LF182X/PIC12F/LF1822 Memory Programming Specification” (DS41403). 28.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. Some programmers produce VPP greater than VIHH (9.0V), an external circuit is required to limit the VPP voltage. See Figure28-1 for example circuit. FIGURE 28-1: VPP LIMITER EXAMPLE CIRCUIT RJ11-6PIN 1 6 VPP 2 5 VDD 3 4 VSS 4 3 ICSP_DATA 5 2 ICSP_CLOCK 6 1 NC RJ11-6PIN To MPLAB® ICD 2 R1 To Target Board 270 Ohm LM431BCMX 23 AA U1 K1 6 A NC4 7 A NC5 VREF 8 R2 R3 10k 1% 24k 1% Note: The MPLAB ICD 2 produces a VPP voltage greater than the maximum VPP specification of the PIC12(L)F1822/16(L)F1823.  2010-2015 Microchip Technology Inc. DS40001413E-page 305

PIC12(L)F1822/16(L)F1823 28.2 Low-Voltage Programming Entry FIGURE 28-2: ICD RJ-11 STYLE Mode CONNECTOR INTERFACE The Low-Voltage Programming Entry mode allows the PIC12(L)F1822/16(L)F1823 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word 2 is set to ‘1’, the low-voltage ICSP programming entry is enabled. To ICSPDAT disable the Low-Voltage ICSP mode, the LVP bit must 2 4 6 NC VDD be programmed to ‘0’. ICSPCLK 1 3 5 Target Entry into the Low-Voltage Programming Entry mode requires the following steps: VPP/MCLR VSS PC Board Bottom Side 1. MCLR is brought to VIL. 2. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Pin Description* Once the key sequence is complete, MCLR must be 1 = VPP/MCLR held at VIL for as long as Program/Verify mode is to be 2 = VDD Target maintained. 3 = VSS (ground) If low-voltage programming is enabled (LVP = 1), the 4 = ICSPDAT MCLR Reset function is automatically enabled and 5 = ICSPCLK cannot be disabled. See Section7.3 “MCLR” for more 6 = No Connect information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1inch 28.3 Common Programming Interfaces spacing. Refer to Figure28-3. Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6 pin, 6 connector) configuration. See Figure28-2. FIGURE 28-3: PICkit™ STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 1 = VPP/MCLR 2 2 = VDD Target 3 4 3 = VSS (ground) 5 4 = ICSPDAT 6 5 = ICSPCLK 6 = No Connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins. DS40001413E-page 306  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure28-4 for more information. FIGURE 28-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming VDD Device to be Signals Programmed VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required).  2010-2015 Microchip Technology Inc. DS40001413E-page 307

PIC12(L)F1822/16(L)F1823 29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations Each PIC16 instruction is a 14-bit word containing the Any instruction that specifies a file register as part of operation code (opcode) and all required operands. the instruction performs a Read-Modify-Write (R-M-W) The opcodes are broken into three broad categories. operation. The register is read, the data is modified, and the result is stored according to either the instruc- • Byte Oriented tion, or the destination designator ‘d’. A read operation • Bit Oriented is performed on a register even if the instruction writes • Literal and Control to that register. The literal and control category contains the most var- ied instruction word format. TABLE 29-1: OPCODE FIELD DESCRIPTIONS Table29-3 lists the instructions recognized by the MPASMTM assembler. Field Description All instructions are executed within a single instruction f Register file address (0x00 to 0x7F) cycle, with the following exceptions, which may take W Working register (accumulator) two or three cycles: b Bit address within an 8-bit file register • Subroutine takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two k Literal field, constant data or label cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1). • Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0. BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for • One additional instruction cycle will be used when compatibility with all Microchip software tools. any instruction references an indirect file register d Destination select; d = 0: store result in W, and the file select register is pointing to program d = 1: store result in file register f. memory. Default is d = 1. One instruction cycle consists of 4 oscillator cycles; for n FSR or INDF number. (0-1) an oscillator frequency of 4 MHz, this gives a nominal mm Pre-post increment-decrement mode instruction execution rate of 1 MHz. selection All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a TABLE 29-2: ABBREVIATION hexadecimal digit. DESCRIPTIONS Field Description PC Program Counter TO Time-out bit C Carry bit DC Digit carry bit Z Zero bit PD Power-down bit DS40001413E-page 308  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value MOVLP instruction only 13 7 6 0 OPCODE k (literal) k = 7-bit immediate value MOVLB instruction only 13 5 4 0 OPCODE k (literal) k = 5-bit immediate value BRA instruction only 13 9 8 0 OPCODE k (literal) k = 9-bit immediate value FSR Offset instructions 13 7 6 5 0 OPCODE n k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 3 2 1 0 OPCODE n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE  2010-2015 Microchip Technology Inc. DS40001413E-page 309

PIC12(L)F1822/16(L)F1823 TABLE 29-3: PIC12(L)F1822/16(L)F1823 ENHANCED INSTRUCTION SET Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2 ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2 ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2 LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2 LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0000 00xx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 2 INCF f, d Increment f 1 00 1010 dfff ffff Z 2 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 2 MOVWF f Move W to f 1 00 0000 1fff ffff 2 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2 SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 2 BIT-ORIENTED SKIP OPERATIONS BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2 LITERAL OPERATIONS ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLB k Move literal to BSR 1 00 0000 001k kkkk MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk MOVLW k Move literal to W 1 11 0000 kkkk kkkk SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. DS40001413E-page 310  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 29-3: PIC12(L)F1822/16(L)F1823 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected CONTROL OPERATIONS BRA k Relative Branch 2 11 001k kkkk kkkk BRW – Relative Branch with W 2 00 0000 0000 1011 CALL k Call Subroutine 2 10 0kkk kkkk kkkk CALLW – Call Subroutine with W 2 00 0000 0000 1010 GOTO k Go to address 2 10 1kkk kkkk kkkk RETFIE k Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 0100 kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 INHERENT OPERATIONS CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD NOP – No Operation 1 00 0000 0000 0000 OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010 RESET – Software device Reset 1 00 0000 0000 0001 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD TRIS f Load TRIS register with W 1 00 0000 0110 0fff C-COMPILER OPTIMIZED ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3 modifier, mm k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2 MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3 modifier, mm k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2 Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions.  2010-2015 Microchip Technology Inc. DS40001413E-page 311

PIC12(L)F1822/16(L)F1823 29.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k Operands: -32  k  31 Operands: 0  k  255 n  [ 0, 1] Operation: (W) .AND. (k)  (W) Operation: FSR(n) + k  FSR(n) Status Affected: Z Status Affected: None Description: The contents of W register are Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The the contents of the FSRnH:FSRnL result is placed in the W register. register pair. FSRn is limited to the range 0000h - FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W ANDWF AND W with f Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d Operands: 0  k  255 Operands: 0  f  127 d 0,1 Operation: (W) + k  (W) Operation: (W) .AND. (f)  (destination) Status Affected: C, DC, Z Status Affected: Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the Description: AND the W register with register ‘f’. If result is placed in the W register. ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWF Add W and f ASRF Arithmetic Right Shift Syntax: [ label ] ADDWF f,d Syntax: [ label ] ASRF f {,d} Operands: 0  f  127 Operands: 0  f  127 d 0,1 d [0,1] Operation: (W) + (f)  (destination) Operation: (f<7>) dest<7> (f<7:1>)  dest<6:0>, Status Affected: C, DC, Z (f<0>)  C, Description: Add the contents of the W register Status Affected: C, Z with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the Description: The contents of register ‘f’ are shifted result is stored back in register ‘f’. one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in reg- ister ‘f’. ADDWFC ADD W and CARRY bit to f register f C Syntax: [ label ] ADDWFC f {,d} Operands: 0  f  127 d [0,1] Operation: (W) + (f) + (C)  dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data mem- ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. DS40001413E-page 312  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 0  b  7 0  b  7 Operation: 0  (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b [ label ] BRA $+k Operands: 0  f  127 Operands: -256label-PC+1255 0  b < 7 -256  k  255 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k  PC Status Affected: None Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Description: Add the signed 9-bit literal ‘k’ to the instruction is executed. PC. Since the PC will have incre- If bit ‘b’ is ‘1’, then the next mented to fetch the next instruction, instruction is discarded and a NOP is the new address will be PC+1+k. executed instead, making this a This instruction is a 2-cycle instruc- 2-cycle instruction. tion. This branch has a limited range. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W)  PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incre- mented to fetch the next instruction, the new address will be PC+1+(W). This instruction is a 2-cycle instruc- tion. BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0  f  127 0  b  7 Operation: 1  (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set.  2010-2015 Microchip Technology Inc. DS40001413E-page 313

PIC12(L)F1822/16(L)F1823 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<4:3>)  PC<12:11> 1  TO Status Affected: None 1  PD Description: Call Subroutine. First, return address Status Affected: TO, PD (PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch- The eleven-bit immediate address is dog Timer. It also resets the prescaler loaded into PC bits <10:0>. The upper of the WDT. Status bits TO and PD bits of the PC are loaded from are set. PCLATH. CALL is a 2-cycle instruc- tion. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: (PC) +1  TOS, (W)  PC<7:0>, Operation: (f)  (destination) (PCLATH<6:0>) PC<14:8> Status Affected: Z Description: The contents of register ‘f’ are com- Status Affected: None plemented. If ‘d’ is ‘0’, the result is Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is return address (PC + 1) is pushed stored back in register ‘f’. onto the return stack. Then, the con- tents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a 2-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the and the Z bit is set. result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h  (W) 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS40001413E-page 314  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre- mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. is placed back in register ‘f’. If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is NOP is executed instead, making it a executed instead, making it a 2-cycle 2-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<4:3>  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. The OR’ed with the 8-bit literal ‘k’. The eleven-bit immediate value is loaded result is placed in the W register. into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis- mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is is placed back in register ‘f’. placed back in register ‘f’.  2010-2015 Microchip Technology Inc. DS40001413E-page 315

PIC12(L)F1822/16(L)F1823 LSLF Logical Left Shift MOVF Move f Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d Operands: 0  f  127 Operands: 0  f  127 d [0,1] d  [0,1] Operation: (f<7>)  C Operation: (f)  (dest) (f<6:0>)  dest<7:1> Status Affected: Z 0  dest<0> Description: The contents of register f is moved to Status Affected: C, Z a destination dependent upon the Description: The contents of register ‘f’ are shifted status of d. If d = 0, destination is W one bit to the left through the Carry flag. register. If d = 1, the destination is file A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, register f itself. d = 1 is useful to test a the result is placed in W. If ‘d’ is ‘1’, the file register since status flag Z is result is stored back in register ‘f’. affected. Words: 1 C register f 0 Cycles: 1 Example: MOVF FSR, 0 After Instruction LSRF Logical Right Shift W = value in FSR register Syntax: [ label ] LSRF f {,d} Z = 1 Operands: 0  f  127 d [0,1] Operation: 0  dest<7> (f<7:1>)  dest<6:0>, (f<0>)  C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘0’ is shifted into the MSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 0 register f C DS40001413E-page 316  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 MOVIW Move INDFn to W MOVLP Move literal to PCLATH Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k [ label ] MOVIW --FSRn Operands: 0  k  127 [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-- Operation: k  PCLATH [ label ] MOVIW k[FSRn] Status Affected: None Operands: n  [0,1] Description: The 7-bit literal ‘k’ is loaded into the mm  [00,01, 10, 11] PCLATH register. -32  k  31 Operation: INDFn  W Effective address is determined by MOVLW Move literal to W • FSR + 1 (preincrement) Syntax: [ label ] MOVLW k • FSR - 1 (predecrement) • FSR + k (relative offset) Operands: 0  k  255 After the Move, the FSR value will be Operation: k  (W) either: • FSR + 1 (all increments) Status Affected: None • FSR - 1 (all decrements) Description: The 8-bit literal ‘k’ is loaded into W reg- • Unchanged ister. The “don’t cares” will assemble as Status Affected: Z ‘0’s. Words: 1 Mode Syntax mm Cycles: 1 Preincrement ++FSRn 00 Example: MOVLW 0x5A Predecrement --FSRn 01 After Instruction W = 0x5A Postincrement FSRn++ 10 Postdecrement FSRn-- 11 MOVWF Move W to f Syntax: [ label ] MOVWF f Description: This instruction is used to move data between W and one of the indirect Operands: 0  f  127 registers (INDFn). Before/after this Operation: (W)  (f) move, the pointer (FSRn) is updated by Status Affected: None pre/post incrementing/decrementing it. Description: Move data from W register to register Note: The INDFn registers are not ‘f’. physical registers. Any instruction that Words: 1 accesses an INDFn register actually accesses the register at the address Cycles: 1 specified by the FSRn. Example: MOVWF OPTION Before Instruction FSRn is limited to the range 0000h - OPTION = 0xFF FFFFh. Incrementing/decrementing it W = 0x4F beyond these bounds will cause it to After Instruction wrap-around. OPTION = 0x4F W = 0x4F MOVLB Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0  k  15 Operation: k  BSR Status Affected: None Description: The 5-bit literal ‘k’ is loaded into the Bank Select Register (BSR).  2010-2015 Microchip Technology Inc. DS40001413E-page 317

PIC12(L)F1822/16(L)F1823 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] NOP Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn Operands: None [ label ] MOVWI FSRn++ Operation: No operation [ label ] MOVWI FSRn-- [ label ] MOVWI k[FSRn] Status Affected: None Operands: n  [0,1] Description: No operation. mm  [00,01, 10, 11] Words: 1 -32  k  31 Cycles: 1 Operation: W  INDFn Example: NOP Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be Load OPTION_REG Register either: OPTION with W • FSR + 1 (all increments) • FSR - 1 (all decrements) Syntax: [ label ] OPTION Unchanged Operands: None Status Affected: None Operation: (W)  OPTION_REG Status Affected: None Mode Syntax mm Description: Move data from W register to Preincrement ++FSRn 00 OPTION_REG register. Predecrement --FSRn 01 Postincrement FSRn++ 10 Postdecrement FSRn-- 11 RESET Software Reset Syntax: [ label ] RESET Description: This instruction is used to move data between W and one of the indirect Operands: None registers (INDFn). Before/after this Operation: Execute a device Reset. Resets the move, the pointer (FSRn) is updated by nRI flag of the PCON register. pre/post incrementing/decrementing it. Status Affected: None Note: The INDFn registers are not Description: This instruction provides a way to physical registers. Any instruction that execute a hardware Reset by soft- accesses an INDFn register actually ware. accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h - FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. The increment/decrement operation on FSRn WILL NOT affect any Status bits. DS40001413E-page 318  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] RETFIE Syntax: [ label ] RETURN Operands: None Operands: None Operation: TOS  PC, Operation: TOS  PC 1  GIE Status Affected: None Status Affected: None Description: Return from subroutine. The stack is Description: Return from Interrupt. Stack is POPed POPed and the top of the stack (TOS) and Top-of-Stack (TOS) is loaded in is loaded into the program counter. the PC. Interrupts are enabled by This is a 2-cycle instruction. setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 RETLW Return with literal in W RLF Rotate Left f through Carry Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d Operands: 0  k  255 Operands: 0  f  127 Operation: k  (W); d  [0,1] TOS  PC Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the 8-bit literal ‘k’. The program counter is Description: The contents of register ‘f’ are rotated loaded from the top of the stack (the one bit to the left through the Carry return address). This is a 2-cycle flag. If ‘d’ is ‘0’, the result is placed in instruction. the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Words: 1 C Register f Cycles: 2 Example: CALL TABLE;W contains table Words: 1 ;offset value Cycles: 1 • ;W now has table value TABLE • Example: RLF REG1,0 • Before Instruction ADDWF PC ;W = offset REG1 = 1110 0110 RETLW k1 ;Begin table C = 0 RETLW k2 ; After Instruction • REG1 = 1110 0110 • W = 1100 1100 • C = 1 RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8  2010-2015 Microchip Technology Inc. DS40001413E-page 319

PIC12(L)F1822/16(L)F1823 SUBLW Subtract W from literal RRF Rotate Right f through Carry Syntax: [ label ] SUBLW k Syntax: [ label ] RRF f,d Operands: 0 k 255 Operands: 0  f  127 d  [0,1] Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s com- plement method) from the 8-bit literal Description: The contents of register ‘f’ are rotated ‘k’. The result is placed in the W regis- one bit to the right through the Carry ter. flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is C = 0 W  k placed back in register ‘f’. C = 1 W  k C Register f DC = 0 W<3:0>  k<3:0> DC = 1 W<3:0>  k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] SLEEP Syntax: [ label ] SUBWF f,d Operands: None Operands: 0 f 127 d  [0,1] Operation: 00h  WDT, 0  WDT prescaler, Operation: (f) - (W) destination) 1  TO, Status Affected: C, DC, Z 0  PD Description: Subtract (2’s complement method) W Status Affected: TO, PD register from register ‘f’. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is result is stored in the W cleared. Time-out Status bit, TO is register. If ‘d’ is ‘1’, the result is stored set. Watchdog Timer and its pres- back in register ‘f. caler are cleared. The processor is put into Sleep mode C = 0 W  f with the oscillator stopped. C = 1 W  f DC = 0 W<3:0>  f<3:0> DC = 1 W<3:0>  f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB f {,d} Operands: 0  f  127 d  [0,1] Operation: (f) – (W) – (B) dest Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s comple- ment method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001413E-page 320  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k Operands: 0  f  127 Operands: 0 k 255 d  [0,1] Operation: (W) .XOR. k W) Operation: (f<3:0>)  (destination<7:4>), Status Affected: Z (f<7:4>)  (destination<3:0>) Description: The contents of the W register are Status Affected: None XOR’ed with the 8-bit literal ‘k’. The Description: The upper and lower nibbles of regis- result is placed in the W register. ter ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. XORWF Exclusive OR W with f TRIS Load TRIS Register with W Syntax: [ label ] XORWF f,d Syntax: [ label ] TRIS f Operands: 0  f  127 Operands: 5  f  7 d  [0,1] Operation: (W)  TRIS register ‘f’ Operation: (W) .XOR. (f) destination) Status Affected: None Status Affected: Z Description: Move data from W register to TRIS Description: Exclusive OR the contents of the W register. register with register ‘f’. If ‘d’ is ‘0’, the When ‘f’ = 5, TRISA is loaded. result is stored in the W register. If ‘d’ When ‘f’ = 6, TRISB is loaded. is ‘1’, the result is stored back in regis- When ‘f’ = 7, TRISC is loaded. ter ‘f’.  2010-2015 Microchip Technology Inc. DS40001413E-page 321

PIC12(L)F1822/16(L)F1823 30.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias.......................................................................................................-40°C to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC12F1822/16F1823 .............................................................. -0.3V to +6.5V Voltage on VDD with respect to VSS, PIC12LF1822/16LF1823 .......................................................... -0.3V to +4.0V Voltage on MCLR with respect to Vss .................................................................................................-0.3V to +9.0V Voltage on all other pins with respect to VSS ............................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)...............................................................................................................................800 mW Maximum current out of VSS pin, -40°C  TA  +85°C for industrial............................................................... 210 mA Maximum current out of VSS pin, -40°C  TA  +125°C for extended.............................................................. 95 mA Maximum current into VDD pin, -40°C  TA  +85°C for industrial.................................................................. 150 mA Maximum current into VDD pin, -40°C  TA  +125°C for extended................................................................. 70 mA Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA Maximum output current sunk by any I/O pin....................................................................................................25 mA Maximum output current sourced by any I/O pin...............................................................................................25 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating condi- tions for extended periods may affect device reliability. DS40001413E-page 322  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 30-1: PIC12F1822/16F1823 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C 5.5 ) V ( D D V 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-1 for each Oscillator mode’s supported frequencies. FIGURE 30-2: PIC12LF1822/16LF1823 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C V) 3.6 ( D D V 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-1 for each oscillator mode’s supported frequencies.  2010-2015 Microchip Technology Inc. DS40001413E-page 323

PIC12(L)F1822/16(L)F1823 FIGURE 30-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 ± 3% C) ° 60 ( e r u at r e p 25 ± 2% m e T 0 -20 ± 5% -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001413E-page 324  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 30.1 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) PIC12LF1822/16LF1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1822/16F1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. D001 VDD Supply Voltage PIC12LF1822/16LF1823 1.8 — 3.6 V FOSC  16MHz: 2.5 — 3.6 V FOSC  32MHz (Note 2) D001 PIC12F1822/16F1823 1.8 — 5.5 V FOSC  16MHz: 2.5 — 5.5 V FOSC  32MHz (Note 2) D002* VDR RAM Data Retention Voltage(1) PIC12LF1822/16LF1823 1.5 — — V Device in Sleep mode D002* PIC12F1822/16F1823 1.7 — — V Device in Sleep mode VPOR* Power-on Reset Release Voltage — 1.6 — V VPORR* Power-on Reset Rearm Voltage PIC12LF1822/16LF1823 — 0.8 — V Device in Sleep mode PIC12F1822/16F1823 — 1.4 — V Device in Sleep mode D003 VADFVR Fixed Voltage Reference Voltage for -8 6 % 1.024V, VDD  2.5V ADC -8 6 2.048V, VDD  2.5V -8 6 4.096V, VDD  4.75V D003A VCDAFVR Fixed Voltage Reference Voltage for -11 7 % 1.024V, VDD  2.5V Comparator and DAC -11 7 2.048V, VDD  2.5V -11 7 4.096V, VDD  4.75V D003C* TCVFVR Temperature Coefficient, Fixed Voltage — -114 — ppm/ Reference °C D003D* VFVR/ Line Regulation, Fixed Voltage — 0.225 — %/V VIN Reference D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See Section7.1 “Power-on Reset Power-on Reset signal (POR)” for details. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation.  2010-2015 Microchip Technology Inc. DS40001413E-page 325

PIC12(L)F1822/16(L)F1823 FIGURE 30-4: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR(1) POR REARM VSS TVLOW(2) TPOR(3) Note 1: When NPOR is low, the device is held in Reset. 2: TPOR 1s typical. 3: TVLOW 2.7s typical. DS40001413E-page 326  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 30.2 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) PIC12LF1822/16LF1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1822/16F1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D010 — 5.0 15 A 1.8 FOSC = 32kHz, -40°C to +85°C — 8.0 19 A 3.0 LP Oscillator mode D010 — 24 36 A 1.8 FOSC = 32kHz, -40°C to +85°C — 30 48 A 3.0 LP Oscillator mode — 32 66 A 5.0 D010A — 5.0 21 A 1.8 FOSC = 32kHz, -40°C to +125°C LP Oscillator mode — 7.5 25 A 3.0 D010A — 24 60 A 1.8 FOSC = 32kHz, -40°C to +125°C LP Oscillator mode — 30 70 A 3.0 — 32 80 A 5.0 D011 — 60 115 A 1.8 FOSC = 1MHz XT Oscillator mode — 111 200 A 3.0 D011 — 82 135 A 1.8 FOSC = 1MHz XT Oscillator mode — 141 225 A 3.0 — 200 320 A 5.0 D012 — 145 280 A 1.8 FOSC = 4MHz XT Oscillator mode — 260 460 A 3.0 D012 — 165 300 A 1.8 FOSC = 4MHz XT Oscillator mode — 290 500 A 3.0 — 368 700 A 5.0 D013 — 34 170 A 1.8 FOSC = 1MHz EC Oscillator mode, Medium-power mode — 59 250 A 3.0 D013 — 60 200 A 1.8 FOSC = 1MHz EC Oscillator mode — 92 260 A 3.0 Medium-power mode — 126 350 A 5.0 D014 — 118 250 A 1.8 FOSC = 4MHz EC Oscillator mode, — 210 420 A 3.0 Medium-power mode * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 MHz internal RC oscillator with 4x PLL enabled. 4: 8MHz crystal oscillator with 4x PLL enabled. 5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k  2010-2015 Microchip Technology Inc. DS40001413E-page 327

PIC12(L)F1822/16(L)F1823 30.2 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) PIC12LF1822/16LF1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1822/16F1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note D014 — 143 260 A 1.8 FOSC = 4MHz EC Oscillator mode — 240 450 A 3.0 Medium-power mode — 300 550 A 5.0 Supply Current (IDD)(1, 2) D015 — 2.0 20 A 1.8 FOSC = 31kHz LFINTOSC mode — 4.0 22 A 3.0 D015 — 21 45 A 1.8 FOSC = 31kHz LFINTOSC mode — 27 50 A 3.0 — 28 60 A 5.0 D016 — 110 250 A 1.8 FOSC = 500kHz MFINTOSC mode — 150 280 A 3.0 D016 — 132 190 A 1.8 FOSC = 500kHz MFINTOSC mode — 165 230 A 3.0 — 210 280 A 5.0 D017* — 0.55 0.8 mA 1.8 FOSC = 8MHz HFINTOSC mode — 0.8 1.25 mA 3.0 D017* — 0.6 0.9 mA 1.8 FOSC = 8MHz HFINTOSC mode — 0.9 1.4 mA 3.0 — 1.0 1.5 mA 5.0 D018 — 0.8 1.2 mA 1.8 FOSC = 16MHz HFINTOSC mode — 1.3 1.9 mA 3.0 D018 — 0.8 1.2 mA 1.8 FOSC = 16MHz HFINTOSC mode — 1.3 1.8 mA 3.0 — 1.5 2.0 mA 5.0 D019 — 2.2 3.3 mA 3.0 FOSC = 32MHz HFINTOSC mode (Note 3) — 2.3 3.6 mA 3.6 D019 — 2.2 3.3 mA 3.0 FOSC = 32MHz HFINTOSC mode (Note 3) — 2.3 3.6 mA 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 MHz internal RC oscillator with 4x PLL enabled. 4: 8MHz crystal oscillator with 4x PLL enabled. 5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k DS40001413E-page 328  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 30.2 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) PIC12LF1822/16LF1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1822/16F1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D020 — 2.0 3.1 mA 3.0 FOSC = 32MHz HS Oscillator mode (Note 4) — 2.5 3.5 mA 3.6 D020 — 2.0 3.1 mA 3.0 FOSC = 32MHz HS Oscillator mode (Note 4) — 2.5 3.5 mA 5.0 D021 — 210 425 A 1.8 FOSC = 4MHz EXTRC mode (Note 5) — 470 800 A 3.0 D021 — 350 435 A 1.8 FOSC = 4MHz EXTRC mode (Note 5) — 550 800 A 3.0 — 620 850 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 MHz internal RC oscillator with 4x PLL enabled. 4: 8MHz crystal oscillator with 4x PLL enabled. 5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k  2010-2015 Microchip Technology Inc. DS40001413E-page 329

PIC12(L)F1822/16(L)F1823 30.3 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Power-Down) Standard Operating Conditions (unless otherwise stated) PIC12LF1822/16LF1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1822/16F1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D022 — 0.02 1.0 4.0 A 1.8 WDT, BOR, FVR, and T1OSC — 0.03 1.8 4.8 A 3.0 disabled, all Peripherals Inactive D022 — 20 40 50 A 1.8 WDT, BOR, FVR, and T1OSC — 22 45 55 A 3.0 disabled, all Peripherals Inactive — 24 50 60 A 5.0 D023 — 0.3 1.8 10.5 A 1.8 LPWDT Current (Note 1) — 0.5 2.0 16 A 3.0 D023 — 20 41 56 A 1.8 LPWDT Current (Note 1) — 22 46 61 A 3.0 — 24 51 71 A 5.0 D023A — 12 25 35 A 1.8 FVR current (Note 1) — 13 27 37 A 3.0 D023A — 32 65 70 A 1.8 FVR current (Note 1) — 38 75 80 A 3.0 — 68 115 120 A 5.0 D024 — 8.0 15 20 A 3.0 BOR Current (Note 1) D024 — 30 55 65 A 3.0 BOR Current (Note 1) — 33 75 85 A 5.0 D025 — 0.65 4.0 7.0 A 1.8 T1OSC Current (Note 1) — 2.3 4.5 7.5 A 3.0 D025 — 20 42 55 A 1.8 T1OSC Current (Note 1) — 23 45 60 A 3.0 — 25 48 70 A 5.0 D026 — 0.1 1.8 4.0 A 1.8 A/D Current (Note 1, Note 3), no — 0.1 2.0 5.0 A 3.0 conversion in progress D026 — 20 40 55 A 1.8 A/D Current (Note 1, Note 3), no — 22 45 60 A 3.0 conversion in progress — 24 50 70 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: A/D oscillator source is FRC. DS40001413E-page 330  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 30.3 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Power-Down) (Continued) Standard Operating Conditions (unless otherwise stated) PIC12LF1822/16LF1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1822/16F1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D026A* — 250 — — A 1.8 A/D Current (Note 1, Note 3), — 250 — — A 3.0 conversion in progress D026A* — 280 — — A 1.8 A/D Current (Note 1, Note 3), — 280 — — A 3.0 conversion in progress — 280 — — A 5.0 D027 — 2.2 7.0 10 A 1.8 Cap Sense Low Power — 4.2 9.0 12 A 3.0 Oscillator mode (Note 1) D027 — 21 41 45 A 1.8 Cap Sense Low Power — 23 47 55 A 3.0 Oscillator mode (Note 1) — 24 53 68 A 5.0 D027A — 6.3 9 16 A 1.8 Cap Sense Medium Power — 7.9 12 21 A 3.0 Oscillator mode (Note 1) D027A — 21 45 50 A 1.8 Cap Sense Medium Power — 23 55 60 A 3.0 Oscillator mode (Note 1) — 25 60 75 A 5.0 D027B — 16 25 35 A 1.8 Cap Sense High Power — 41 45 45 A 3.0 Oscillator mode (Note 1) D027B — 23 62 100 A 1.8 Cap Sense High Power — 25 90 105 A 3.0 Oscillator mode (Note 1) — 26 100 115 A 5.0 D028 — 8.0 17 22 A 1.8 Comparator Current, Low Power — 8.1 20 25 A 3.0 mode, one comparator enabled (Note 1) D028 — 30 50 55 A 1.8 Comparator Current, Low Power — 33 60 65 A 3.0 mode, one comparator enabled (Note 1) — 35 65 85 A 5.0 D028A — 8.2 18 24 A 1.8 Comparator Current, Low Power — 8.3 21 27 A 3.0 mode, two comparators enabled (Note 1) D028A — 30 51 56 A 1.8 Comparator Current, Low Power — 32 61 66 A 3.0 mode, two comparators enabled (Note 1) — 33 67 87 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: A/D oscillator source is FRC.  2010-2015 Microchip Technology Inc. DS40001413E-page 331

PIC12(L)F1822/16(L)F1823 30.3 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Power-Down) (Continued) Standard Operating Conditions (unless otherwise stated) PIC12LF1822/16LF1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1822/16F1823 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D028B — 30 50 60 A 1.8 Comparator Current, High Power — 31 55 70 A 3.0 mode, one comparator enabled (Note 1) D028B — 60 85 90 A 1.8 Comparator Current, High Power — 62 90 95 A 3.0 mode, one comparator enabled (Note 1) — 64 95 100 A 5.0 D028C — 31 51 61 A 1.8 Comparator Current, High Power — 32 56 71 A 3.0 mode, two comparators enabled D028C — 61 85 90 A 1.8 Comparator Current, High Power — 63 90 95 A 3.0 mode, two comparators enabled (Note 1) — 65 95 100 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: A/D oscillator source is FRC. DS40001413E-page 332  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 30.4 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature-40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage I/O PORT: D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V D030A — — 0.15VDD V 1.8V  VDD  4.5V D031 with Schmitt Trigger buffer — — 0.2VDD V 2.0V  VDD  5.5V with I2C™ levels — — 0.3VDD V with SMBus levels — — 0.8 V 2.7V  VDD  5.5V D032 MCLR, OSC1 (RC mode)(1) — — 0.2VDD V D033 OSC1 (HS mode) — — 0.3VDD V VIH Input High Voltage I/O ports: — — D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V D040A 0.25VDD + — — V 1.8V  VDD  4.5V 0.8 D041 with Schmitt Trigger buffer 0.8VDD — — V 2.0V  VDD  5.5V with I2C™ levels 0.7VDD — — V with SMBus levels 2.1 — — V 2.7V  VDD  5.5V D042 MCLR 0.8VDD — — V D043A OSC1 (HS mode) 0.7VDD — — V D043B OSC1 (RC mode) 0.9VDD — — V VDD > 2.0V, (Note 1) IIL Input Leakage Current(2) D060 I/O ports — ± 5 ± 125 nA VSS  VPIN  VDD, Pin at high-impedance at 85°C ± 5 ± 1000 nA 125°C D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD at 85°C IPUR Weak Pull-up Current D070* 25 100 200 VDD = 3.3V, VPIN = VSS 25 140 300 A VDD = 5.0V, VPIN = VSS VOL Output Low Voltage(4) D080 I/O ports IOL = 8mA, VDD = 5V — — 0.6 V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V VOH Output High Voltage(4) D090 I/O ports IOH = 3.5mA, VDD = 5V VDD - 0.7 — — V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 333

PIC12(L)F1822/16(L)F1823 30.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Program Memory High-Voltage Programming Specifications D110 VIHH Voltage on MCLR/VPP/RA5 pin 8.0 — 9.0 V (Note 3, Note 4) D111 IDDVPP Programming/Erase Current on VPP, — — 10 mA High Voltage Programming D112 VBE VDD for Bulk Erase 2.7 — VDD V max. D113 VPEW VDD for Write or Row Erase VDD — VDD V min. max. D114 IPPPGM Programming/Erase Current on VPP, — 1.0 — mA Low Voltage Programming D115 IDDPGM Programming/Erase Current on VDD, — 5.0 — mA High or Low Voltage Programming Data EEPROM Memory D116 ED Byte Endurance 100K — — E/W -40C to +85C D117 VDRW VDD for Read/Write VDD — VDD V min. max. D118 TDEW Erase/Write Cycle Time — 4.0 5.0 ms D119 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D120 TREF Number of Total Erase/Write Cycles 1M 10M — E/W -40°C to +85°C before Refresh(2) Program Flash Memory D121 EP Cell Endurance 10K — — E/W -40C to +85C (Note 1) D122 VPR VDD for Read VDD — VDD V min. max. D123 TIW Self-timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Refer to Section11.2 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP voltage must be placed between the MPLAB ICD 2 and target system when programming or debugging with the MPLAB ICD 2. DS40001413E-page 334  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 30.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance Junction to Ambient 89.3 C/W 8-pin PDIP package 149.5 C/W 8-pin SOIC package 56.7 C/W 8-pin DFN 3X3mm package 39.4 C/W 8-pin UDFN 3X3mm package 70.0 C/W 14-pin PDIP package 95.3 C/W 14-pin SOIC package 100 C/W 14-pin TSSOP 4x4mm package 45.7 C/W 16-pin QFN 4X4mm package 31.8 C/W 16-pin UQFN 4X4mm package TH02 JC Thermal Resistance Junction to Case 43.1 C/W 8-pin PDIP package 39.9 C/W 8-pin SOIC package 9.0 C/W 8-pin DFN 3X3mm package 40.3 C/W 8-pin UDFN 3X3mm package 32.0 C/W 14-pin PDIP package 31.0 C/W 14-pin SOIC package 24.4 C/W 14-pin TSSOP 4x4mm package 6.3 C/W 16-pin QFN 4X4mm package 24.4 C/W 16-pin UQFN 4X4mm package TH03 TJMAX Maximum Junction Temperature 150 C TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Legend: TBD = To Be Determined Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature. TJ = Junction Temperature.  2010-2015 Microchip Technology Inc. DS40001413E-page 335

PIC12(L)F1822/16(L)F1823 30.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDIx sc SCKx do SDO ss SS dt Data in t0 T0CKI io I/O PORT t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 30-5: LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins, 15 pF for OSC2 output DS40001413E-page 336  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 30.8 AC Characteristics: PIC12(L)F1822/16(L)F1823-I/E FIGURE 30-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 30-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz EC Oscillator mode (low) DC — 4 MHz EC Oscillator mode (medium) DC — 32 MHz EC Oscillator mode (high) Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 4 MHz HS Oscillator mode, VDD  2.7V 1 — 20 MHz HS Oscillator mode, VDD > 2.7V DC — 4 MHz RC Oscillator mode OS02 TOSC External CLKIN Period(1) 27 —  s LP Oscillator mode 250 —  ns XT Oscillator mode 50 —  ns HS Oscillator mode 31.25 —  ns EC Oscillator mode Oscillator Period(1) — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 — DC ns TCY = FOSC/4 OS04* TosH, External CLKIN High, 2 — — s LP oscillator TosL External CLKIN Low 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TosR, External CLKIN Rise, 0 —  ns LP oscillator TosF External CLKIN Fall 0 —  ns XT oscillator 0 —  ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.  2010-2015 Microchip Technology Inc. DS40001413E-page 337

PIC12(L)F1822/16(L)F1823 TABLE 30-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Freq. Sym. Characteristic Min. Typ† Max. Units Conditions No. Tolerance OS08 HFOSC Internal Calibrated HFINTOSC 2% — 16.0 — MHz 0°C  TA  +60°C, VDD  2.5V Frequency(2) 3% — 16.0 — MHz 60°C  TA  +85°C, VDD  2.5V 5% — 16.0 — MHz -40°C  TA  +125°C OS08A MFOSC Internal Calibrated MFINTOSC 2% — 500 — kHz 0°C  TA  +60°C, VDD  2.5V Frequency(2) 3% — 500 — kHz 60°C  TA  +85°C, VDD  2.5V 5% — 500 — kHz -40°C  TA  +125°C OS09 LFOSC Internal LFINTOSC Frequency 25% — 31 — kHz -40°C  TA  +125°C OS10* TIOSC ST HFINTOSC — — 3.2 8 s Wake-up from Sleep Start-up Time MFINTOSC Wake-up from Sleep Start-up Time — — 24 35 s * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an exter- nal clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. 3: By design. TABLE 30-3: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 8 MHz F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz F12 TRC PLL Start-up Time (Lock Time) — — 2 ms F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% % * These parameters are characterized but not tested. † Data in “Typ” column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001413E-page 338  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 30-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19  2010-2015 Microchip Technology Inc. DS40001413E-page 339

PIC12(L)F1822/16(L)F1823 TABLE 30-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS11 TosH2ckL FOSC to CLKOUT (1) — — 70 ns VDD = 3.0-5.0V OS12 TosH2ckH FOSC to CLKOUT (1) — — 72 ns VDD = 3.0-5.0V OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.0-5.0V OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns VDD = 3.0-5.0V (I/O in hold time) OS17 TioV2osH Port input valid to Fosc(Q2 cycle) 20 — — ns (I/O in setup time) OS18* TioR Port output rise time — 40 72 ns VDD = 1.8V — 15 32 VDD = 3.0-5.0V OS19* TioF Port output fall time — 28 55 ns VDD = 1.8V — 15 30 VDD = 3.0-5.0V OS20* Tinp INT pin input high or low time 25 — — ns OS21* Tioc Interrupt-on-change new input level 25 — — ns time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. FIGURE 30-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. DS40001413E-page 340  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to ‘0’. 2ms delay if PWRTE = 0.  2010-2015 Microchip Technology Inc. DS40001413E-page 341

PIC12(L)F1822/16(L)F1823 TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDTLP Watchdog Timer Time-out Period 12 16 20 ms VDD = 3.3V-5V, 1:16 Prescaler used 32 TOST Oscillator Start-up Timer Period(1), (2) — 1024 — Tosc 33* TPWRT Power-up Timer Period, PWRTE=0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low — — 2.0 s or Watchdog Timer Reset 35 VBOR Brown-out Reset Voltage 2.55 2.7 2.85 V BORV= 0 1.80 1.9 2.11 BORV= 1 36* VHYST Brown-out Reset Hysteresis 20 35 75 mV -40°C to +85°C 37* TBORDC Brown-out Reset DC Response 1 3 35 s VDD  VBOR Time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: By design, the oscillators start-up (OST) counts the first 1024 cycles, independent of frequency. 2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. FIGURE 30-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 DS40001413E-page 342  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 30-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value Period 30 or TCY + 40 (1, 2, 4, 8) N Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range 32.4 32.768 33.1 kHz (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync Increment mode * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP (Capture mode) CC01 CC02 CC03 Note: Refer to Figure30-5 for load conditions. TABLE 30-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. CC01* TccL CCP Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCP Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCP Input Period 3TCY + 40 — — ns N = prescale value (1, 4 or 16) N * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2010-2015 Microchip Technology Inc. DS40001413E-page 343

PIC12(L)F1822/16(L)F1823 TABLE 30-8: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS:(1, 2, 3) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — — ±1.7 LSb VREF = 3.0V AD03 EDL Differential Error — — ±1 LSb No missing codes VREF = 3.0V AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V AD05 EGN Gain Error — — ±2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage(4) 1.8 — VDD V VREF = (VREF+ minus VREF-) AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01F capacitor is Analog Voltage Source present on input pin. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. 4: ADC Reference Voltage (REF+) is the selected input, VREF+ pin, VDD pin or the FVR Buffer 1. When the FVR is selected as the reference input, the FVR Buffer 1 output selection must be 2.048V or 4.096V (ADFVR<1:0> = 1x). TABLE 30-9: ADC CONVERSION REQUIREMENTS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD130* TAD A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal RC Oscillator 1.0 2.5 6.0 s ADCS<1:0> = 11 (ADRC mode) Period AD131 TCNV Conversion Time (not including — 11 — TAD Set GO/DONE bit to conversion Acquisition Time)(1) complete AD132* TACQ Acquisition Time — 5.0 — s * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. DS40001413E-page 344  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 30-12: PIC12(L)F1822/16(L)F1823 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 (TOSC/2(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. FIGURE 30-13: PIC12(L)F1822/16(L)F1823 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.  2010-2015 Microchip Technology Inc. DS40001413E-page 345

PIC12(L)F1822/16(L)F1823 TABLE 30-10: COMPARATOR SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param Sym. Characteristics Min. Typ. Max. Units Comments No. CM01 VIOFF Input Offset Voltage — ±7.5 ±60 mV VICM = VDD/2, High-Power mode CM02 VICM Input Common Mode Voltage 0 — VDD V CM03 CMRR Common Mode Rejection Ratio — 50 — dB CM04A Response Time Rising Edge — 400 800 ns High-Power mode CM04B Response Time Falling Edge — 200 400 ns High-Power mode TRESP(1) CM04C Response Time Rising Edge — 1200 — ns Low-Power mode CM04D Response Time Falling Edge — 550 — ns Low-Power mode CM05 TMC2OV Comparator Mode Change to — — 10 s Output Valid* CM06 CHYSTER Comparator Hysteresis(2) — 45 — mV Hysteresis on * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. 2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled. TABLE 30-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param Sym. Characteristics Min. Typ. Max. Units Comments No. DAC01* CLSB Step Size — VDD/32 — V DAC02* CACC Absolute Accuracy — —  1/2 LSb DAC03* CR Unit Resistor Value (R) — 5K —  DAC04* CST Settling Time(1) — — 10 s * These parameters are characterized but not tested. Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’. FIGURE 30-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US120 US122 Note: Refer to Figure30-5 for load conditions. DS40001413E-page 346  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 30-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. US120 TCKH2DTV SYNC XMIT (Master and Slave) 3.0-5.5V — 80 ns Clock high to data-out valid 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time 3.0-5.5V — 45 ns (Master mode) 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns FIGURE 30-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure30-5 for load conditions. TABLE 30-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK  (DT hold time) 10 — ns US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns  2010-2015 Microchip Technology Inc. DS40001413E-page 347

PIC12(L)F1822/16(L)F1823 FIGURE 30-16: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SCKx (CKP = 1) SP79 SP78 SP80 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure30-5 for load conditions. FIGURE 30-17: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SSx SP81 SCKx (CKP = 0) SP71 SP72 SP79 SP73 SCKx (CKP = 1) SP80 SP78 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure30-5 for load conditions. DS40001413E-page 348  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 30-18: SPI SLAVE MODE TIMING (CKE=0) SSx SP70 SCKx SP83 (CKP = 0) SP71 SP72 SP78 SP79 SCKx (CKP = 1) SP79 SP78 SP80 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SP77 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure30-5 for load conditions. FIGURE 30-19: SPI SLAVE MODE TIMING (CKE=1) SP82 SSx SP70 SCKx SP83 (CKP = 0) SP71 SP72 SCKx (CKP = 1) SP80 SDOx MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure30-5 for load conditions.  2010-2015 Microchip Technology Inc. DS40001413E-page 349

PIC12(L)F1822/16(L)F1823 TABLE 30-14: SPI MODE REQUIREMENTS Param Symbol Characteristic Min. Typ† Max. Units Conditions No. SP70* TSSL2SCH, SSx to SCKx or SCKx input 2.25 TCY — — ns TSSL2SCL SP71* TSCH SCKx input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCKx input low time (Slave mode) TCY + 20 — — ns SP73* TDIV2SCH, Setup time of SDIx data input to SCKx edge 100 — — ns TDIV2SCL SP74* TSCH2DIL, Hold time of SDIx data input to SCKx edge 100 — — ns TSCL2DIL SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns 1.8-5.5V — 25 50 ns SP76* TDOF SDOx data output fall time — 10 25 ns SP77* TSSH2DOZ SSx to SDOx output high-impedance 10 — 50 ns SP78* TSCR SCKx output rise time 3.0-5.5V — 10 25 ns (Master mode) 1.8-5.5V — 25 50 ns SP79* TSCF SCKx output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, SDOx data output valid after 3.0-5.5V — — 50 ns TSCL2DOV SCKx edge 1.8-5.5V — — 145 ns SP81* TDOV2SCH, SDOx data output setup to SCKx edge Tcy — — ns TDOV2SCL SP82* TSSL2DOV SDOx data output valid after SS edge — — 50 ns SP83* TSCH2SSH, SSx after SCKx edge 1.5TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-20: I2C™ BUS START/STOP BITS TIMING SCLx SP91 SP93 SP90 SP92 SDAx Start Stop Condition Condition Note: Refer to Figure30-5 for load conditions. DS40001413E-page 350  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 30-21: I2C™ BUS DATA TIMING SP103 SP100 SP102 SP101 SCLx SP90 SP106 SP107 SP91 SP92 SDAx In SP110 SP109 SP109 SDAx Out Note: Refer to Figure30-5 for load conditions. TABLE 30-15: I2C™ BUS START/STOP BITS REQUIREMENTS Param Symbol Characteristic Min. Typ Max. Units Conditions No. SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — Start condition SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first Hold time 400 kHz mode 600 — — clock pulse is generated SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested.  2010-2015 Microchip Technology Inc. DS40001413E-page 351

PIC12(L)F1822/16(L)F1823 TABLE 30-16: I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSPx module 1.5TCY — — SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSPx module 1.5TCY — — SP102* TR SDAx and SCLx 100 kHz mode — 1000 ns rise time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF SP103* TF SDAx and SCLx fall 100 kHz mode — 250 ns time 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from 10-400 pF SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s SP107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2) time 400 kHz mode 100 — ns SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start SP111 CB Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx sig- nal, it must output the next data bit to the SDAx line TR max. + TSU:DAT=1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS40001413E-page 352  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 30-17: CAP SENSE OSCILLATOR SPECIFICATIONS Param. Symbol Characteristic Min. Typ† Max. Units Conditions No. CS01 ISRC Current Source High — -8 — A Medium — -1.5 — A Low — -0.3 — A CS02 ISNK Current Sink High — 7.5 — A Medium — 1.5 — A Low — 0.25 — A CS03 VCTH Cap Threshold — 0.8 — mV CS04 VCTL Cap Threshold — 0.4 — mV CS05 VCHYST CAP HYSTERESIS High — 525 — mV (VCTH - VCTL) Medium — 375 — mV Low — 300 — mV † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-22: CAP SENSE OSCILLATOR VCTH VCTL ISRC ISNK Enabled Enabled  2010-2015 Microchip Technology Inc. DS40001413E-page 353

PIC12(L)F1822/16(L)F1823 30.9 High Temperature Operation Note1: Writes are not allowed for Flash This section outlines the specifications for the following program memory above 125°C. devices operating in the high temperature range between -40°C and 150°C.(2) 2: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 • PIC12F1822(4) hours. Any design in which the total oper- • PIC16F1823(4) ating time from 125°C to 150°C will be When the value of any parameter is identical for both greater than 1,000 hours is not warranted the 125°C Extended and the 150°C High Temp. without prior written approval from temperature ranges, then that value will be found in the Microchip Technology Inc. standard specification tables shown earlier in this 3: The temperature range indicator in the chapter, under the fields listed for the 125°C Extended catalog part number and device marking temperature range. If the value of any parameter is is “H” for -40°C to 150°C. unique to the 150°C High Temp. temperature range, Example: PIC12F1822T-H/SN indicates then it will be listed here, in this section of the data the device is shipped in a Tape and Reel sheet. configuration, in the SOIC package, and If a Silicon Errata exists for the product and it lists a is rated for operation from -40°C to modification to the 125°C Extended temperature range 150°C. value, one that is also shared at the 150°C High Temp. 4: The low voltage versions of these devices, temperature range, then that modified value will apply PIC12LF1822 and PIC16LF1823, is not to both temperature ranges. released for operation above +125°C. 5: Errata Sheet DS80502 lists various mask revisions. 150°C operation applies only to revisions A9 and later. 6: The Capacitive Sensing module (CPS) should not be used in High Temperature devices. Function and its parametrics are not warranted. 7: Only SOIC (SN or SL), TSSOP (ST), and DFN/QFN (MF or ML) packages will be offered, not PDIP or UQFN. TABLE 30-18: ABSOLUTE MAXIMUM RATINGS Parameter Condition Value Max. Current: VDD Source 15 mA Max. Current: VSS Sink 15 mA Max. Current: Pin Source 5 mA Max. Current: Pin Sink 5 mA Max. Storage Temperature — -65°C to 155°C Max. Junction Temperature — +155°C Ambient Temperature under Bias — -40°C to +150°C Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001413E-page 354  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 30-23: PIC12F1822/16F1823 VOLTAGE FREQUENCY GRAPH, -40°C  TA +150°C 5.5 ) V ( D D V 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-1 for each Oscillator mode’s supported frequencies. FIGURE 30-24: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 150 ± 10% 125 C) n ° 85 o e ( ati ur er at p r O pe 25 o ± 5% m N e T 0 -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 355

PIC12(L)F1822/16(L)F1823 TABLE 30-19: DC CHARACTERISTICS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1822/16F1823 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristics Min. Typ. Max. Units Condition No. D001 VDD Supply Voltage 2.5 — 5.5 V FOSC  32 MHz (Note 1) D002* VDR RAM Data Retention Voltage 2.1 — 5.5 V Device in Sleep mode D003 VADFVR Fixed Voltage Reference -10 — 8 % 1.024V, VDD  2.5V Voltage for ADC 2.048V, VDD  2.5V 4.096V, VDD  4.75V D003A VCDAFV Fixed Voltage Reference -13 — 9 % 1.024V, VDD  2.5V R Voltage for ADC 2.048V, VDD  2.5V 4.096V, VDD  4.75V * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: PLL required for 32 MHz operation. DS40001413E-page 356  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 TABLE 30-20: MEMORY PROGRAMMING REQUIREMENTS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1822/16F1823 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristic Min. Typ. Max. Units Conditions No. Data EEPROM Memory D116 ED Byte Endurance 50K — — E/W -40°C to +150°C D118 TDEW Erase/Write Cycle Time — — 6.0 ms -40°C to +150°C D119 TRETD Data Retention — 20 — Years  50K Programming cycles Program Flash Memory D121 EP Cell Endurance — — — — Programming the Flash memory above +125°C is not permitted D124 TRETD Data Retention — 20 — Years TABLE 30-21: OSCILLATOR PARAMETERS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1822/16F1823 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Frequency Sym. Characteristic Min. Typ. Max. Units Conditions No. Tolerance OS08 HFOSC Int. Calibrated HFINTOSC ±5% — 16.0 — MHz -40°C TA 125°C Freq.(1) VDD 2.5V ±10% — 16.0 — MHz -40°C TA 150°C VDD 2.5V OS08A MFOSC Int. Calibrated MFINTOSC ±5% — 500 — kHz -40°C TA 125°C Freq.(1) VDD 2.5V ±10% — 500 — kHz -40°C TA 150°C VDD 2.5V OS09 LFOSC Internal LFINTOSC Freq. ±35% — 31 — kHz -40°C TA 150°C VDD 2.5V † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended. TABLE 30-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1822/16F1823 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristic Min. Typ. Max. Units Conditions No. 31 TWDTLP Low-Power Watchdog Timer 10 16 24 ms VDD = 3.3V-5V Time-out Period (No Prescaler) 1:16 Prescaler used 35 VBOR Brown-out Reset Voltage(1) 2.50 2.70 2.90 V BORV = 0 — — — — BORV = 1 † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended.  2010-2015 Microchip Technology Inc. DS40001413E-page 357

PIC12(L)F1822/16(L)F1823 TABLE 30-23: A/D CONVERTER (ADC) CHARACTERISTICS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1822/16F1823 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristic Min. Typ. Max. Units Conditions No. AD04 EOFF Offset Error — — 3.5 LSB No missing codes VREF = 3.0V † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input. TABLE 30-24: COMPARATOR SPECIFICATIONS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1822/16F1823 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristic Min. Typ. Max. Units Conditions No. CM01 VIOFF Input Offset Voltage — — ±70 mV High-Power mode, VICM = VDD/2 TABLE 30-25: CAP SENSE OSCILLATOR SPECIFICATIONS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1822/16F1823 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristic Min. Typ. Max. Units Conditions No. All All All — — — — This module is not intended for use in high temperature devices. DS40001413E-page 358  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.” represents (mean+3) or (mean-3) respectively, where  is a standard deviation, over each temperature range.  2010-2015 Microchip Technology Inc. DS40001413E-page 359

PIC12(L)F1822/16(L)F1823 FIGURE 31-1: IDD, LP OSCILLATOR MODE (FOSC = 32 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 25 Max. Max: 85°C + 3(cid:305) Typical: 25°C 20 15 A) μ ( D D I 10 Typical 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-2: IDD, LP OSCILLATOR MODE (FOSC = 32 kHz), PIC12F1822 AND PIC16F1823 ONLY 80 Max: 85°C + 3(cid:305) Max. 70 Typical: 25°C 60 50 A) (μ 40 D D Typical I 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001413E-page 360  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC12LF1822 AND PIC16LF1823 ONLY 600 Typical: 25°C 500 4 MHz EXTRC 400 4 MHz XT A) μ 300 ( D D I 1 MHz EXTRC 200 100 1 MHz XT 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC12LF1822 AND PIC16LF1823 ONLY 1000 Max: 85°C + 3(cid:305) 900 800 4 MHz EXTRC 700 600 A) 4 MHz XT μ ( 500 D D I 400 1 MHz EXTRC 300 200 1 MHz XT 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 361

PIC12(L)F1822/16(L)F1823 FIGURE 31-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC12F1822 AND PIC16F1823 ONLY 800 Typical: 25°C 700 4 MHz EXTRC 600 500 A) (μ 400 4 MHz XT D D I 300 1 MHz EXTRC 200 100 1 MHz XT 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-6: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC12F1822 AND PIC16F1823 ONLY 900 Max: 85°C + 3(cid:305) 800 4 MHz EXTRC 700 4 MHz XT 600 500 A) 1 MHz EXTRC μ ( 400 D D I 300 1 MHz XT 200 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001413E-page 362  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-7: IDD, EC OSCILLATOR, LOW-POWER MODE (FOSC = 32 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 18 Max: 85°C + 3(cid:305) Max. 16 Typical: 25°C 14 12 A) 10 μ ( D 8 D I 6 Typical 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-8: IDD, EC OSCILLATOR, LOW-POWER MODE (FOSC = 32 kHz), PIC12F1822 AND PIC16F1823 ONLY 45 Max: 85°C + 3(cid:305) 40 Max. Typical: 25°C 35 30 Typical A) μ 25 ( D ID 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 363

PIC12(L)F1822/16(L)F1823 FIGURE 31-9: IDD, EC OSCILLATOR, LOW-POWER MODE (FOSC = 500 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 80 Max: 85°C + 3(cid:305) 70 Typical: 25°C Max. 60 50 A) μ 40 ( D D Typical I 30 20 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-10: IDD, EC OSCILLATOR, LOW-POWER MODE (FOSC = 500 kHz), PIC12F1822 AND PIC16F1823 ONLY 50 Max: 85°C + 3(cid:305) 45 Typical: 25°C Max. 40 35 A) 30 Typical μ ( D 25 D I 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001413E-page 364  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-11: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC12LF1822 AND PIC16LF1823 ONLY 400 4 MHz 350 Typical: 25°C 300 250 A) μ 200 ( D D I 150 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-12: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, , PIC12LF1822 AND, PIC16LF1823 ONLY 450 400 Max: 85°C + 3(cid:305) 4 MHz 350 300 A) 250 μ ( D D 200 I 150 1 MHz 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 365

PIC12(L)F1822/16(L)F1823 FIGURE 31-13: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC12F1822 AND PIC16F1823 ONLY 450 400 Typical: 25°C 350 4 MHz 300 A) 250 μ ( D ID 200 150 1 MHz 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-14: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC12F1822 AND PIC16F1823 ONLY 450 Max: 85°C + 3(cid:305) 400 4 MHz 350 300 A) 250 μ ( D 1 MHz D 200 I 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001413E-page 366  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-15: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC12LF1822 AND PIC16LF1823 ONLY 3.0 2.5 Typical: 25°C 32 MHz (PLL) 2.0 A) m 1.5 ( D 16 MHz D I 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-16: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC12LF1822 AND PIC16LF1823 ONLY 3.5 3.0 Max: 85°C + 3(cid:305) 32 MHz (PLL) 2.5 A) 2.0 m (D 16 MHz D 1.5 I 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 367

PIC12(L)F1822/16(L)F1823 FIGURE 31-17: IDDTYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC12F1822 AND PIC16F1823 ONLY 2.5 Typical: 25°C 32 MHz (PLL) 2.0 1.5 16 MHz A) m ( D D 1.0 I 8 MHz 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-18: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC12F1822 AND PIC16F1823 ONLY 3.0 32 MHz (PLL) 2.5 Max: 85°C + 3(cid:305) 2.0 A) 16 MHz m 1.5 ( D D I 1.0 8 MHz 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001413E-page 368  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-19: IDD, LFINTOSC MODE (FOSC = 32 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 25 Max. 20 A) 15 μ ( D D I 10 Max: 85°C + 3(cid:305) Typical 5 Typical: 25°C 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-20: IDD, LFINTOSC MODE (FOSC = 32 kHz), PIC12F1822 AND PIC16F1823 ONLY 50 45 Max. 40 35 A) 30 Typical μ ( D 25 D I 20 15 10 Max: 85°C + 3(cid:305) Typical: 25°C 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 369

PIC12(L)F1822/16(L)F1823 FIGURE 31-21: IDD, MFINTOSC MODE (FOSC = 500 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 200 Max: 85°C + 3(cid:305) 180 Typical: 25°C Max. 160 140 120 A) Typical μ 100 ( D D I 80 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-22: IDD, MFINTOSC MODE (FOSC = 500 kHz), PIC12F1822 AND PIC16F1823 ONLY 350 Max: 85°C + 3(cid:305) 300 Typical: 25°C Max. 250 Typical A) 200 μ ( D D 150 I 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001413E-page 370  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-23: IDD TYPICAL, HFINTOSC MODE, PIC12LF1822 AND PIC16LF1823 ONLY 2500 Typical: 25°C 32 MHz (PLL) 2000 A) 1500 16 MHz μ ( D D I 1000 8 MHz 500 4 MHz 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-24: IDD MAXIMUM, HFINTOSC MODE, PIC12LF1822 AND PIC16LF1823 ONLY 3500 32 MHz (PLL) 3000 Max: 85°C + 3(cid:305) 2500 A) 2000 16 MHz μ ( D D I 1500 8 MHz 1000 4 MHz 500 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 371

PIC12(L)F1822/16(L)F1823 FIGURE 31-25: IDD TYPICAL, HFINTOSC MODE, PIC12F1822 AND PIC16F1823 ONLY 3000 Typical: 25°C 2500 32 MHz (PLL) 2000 A) 16 MHz μ 1500 ( D D I 8 MHz 1000 4 MHz 500 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-26: IDD MAXIMUM, HFINTOSC MODE, PIC12F1822 AND PIC16F1823 ONLY 4000 32 MHz (PLL) 3500 Max: 85°C + 3(cid:305) 3000 2500 A) 16 MHz μ 2000 ( D D 8 MHz I 1500 4 MHz 1000 500 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001413E-page 372  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-27: IDD TYPICAL, HS OSCILLATOR, PIC12LF1822 AND PIC16LF1823 ONLY 2.5 Typical: 25°C 2.0 20 MHz 1.5 A) m ( D D 1.0 I 8 MHz 0.5 4 MHz 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-28: IDD MAXIMUM, HS OSCILLATOR, PIC12LF1822 AND PIC16LF1823 ONLY 3.0 Max: 85°C + 3(cid:305) 2.5 20 MHz 2.0 A) m 1.5 ( D 8 MHz D I 1.0 0.5 4 MHz 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 373

PIC12(L)F1822/16(L)F1823 FIGURE 31-29: IDD TYPICAL, HS OSCILLATOR, PIC12F1822 AND PIC16F1823 ONLY 2500 Typical: 25°C 2000 20 MHz 1500 A) μ ( 8 MHz D 1000 D I 500 4 MHz 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-30: IDD MAXIMUM, HS OSCILLATOR, PIC12F1822 AND PIC16F1823 ONLY 3000 Max: 85°C + 3(cid:305) 2500 20 MHz 2000 A) μ 1500 ( D 8 MHz D I 1000 500 4 MHz 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001413E-page 374  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-31: IPD BASE, LOW-POWER SLEEP MODE, PIC12LF1822 AND PIC16LF1823 ONLY 11..44 Max: 85°C + 3(cid:305) 1.2 Typical: 25°C Max. 1.0 A)A) 00..88 μμ (( DD PP I 0.6 0.4 0.2 TTyyppiiccaall 00..00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-32: IPD BASE, LOW-POWER SLEEP MODE, PIC12F1822 AND PIC16F1823 ONLY 5500 MMax: 8855°°CC ++ 33(cid:305) 45 Max. Typical: 25°C 40 35 A)A) 3300 μμ (( 2255 TTyyppiiccaall DD PP I 20 15 10 55 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 375

PIC12(L)F1822/16(L)F1823 FIGURE 31-33: IPD, WATCHDOG TIMER (WDT), PIC12LF1822 AND PIC16LF1823 ONLY 11..22 Max: 85°C + 3(cid:305) Max. 1.0 Typical: 25°C 0.8 A)A TTyyppiiccaall μμ 00..66 (( DD PP II 0.4 0.2 00..00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-34: IPD, WATCHDOG TIMER (WDT), PIC12F1822 AND PIC16F1823 ONLY 5500 45 MMax: 8855°°CC + 33(cid:305) Max. Typical: 25°C 40 35 30 A)A μμ TTyyppiiccaall (( 2255 DD PP II 2200 15 10 5 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001413E-page 376  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-35: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12LF1822 AND PIC16LF1823 ONLY 3300 MMaaxx.. 25 20 A)A μμ 1155 TTyyppiiccaall (( DD PP II 10 Max: 85°C + 3(cid:305) 5 Typical: 25°C 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-36: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12F1822 AND PIC16F1823 ONLY 112200 Max. Max: 85°C + 3(cid:305) 100 Typical: 25°C 80 Typical A) μμ (( 6600 DD PP II 40 20 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 377

PIC12(L)F1822/16(L)F1823 FIGURE 31-37: IPD, BROWN-OUT RESET (BOR), PIC12F1822 AND PIC16F1823 ONLY 6600 Max: 85°C + 3(cid:305) 50 Typical: 25°C Max. 40 A)A) 3300 TTyyppiiccaall μμ (( DD PP II 20 10 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001413E-page 378  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-38: IPD, TIMER1 OSCILLATOR (FOSC = 32 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 66..00 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) Typical: 25°C 5.0 Max. 4.0 A)A μμ 33..00 (( DD PP II TTyyppiiccaall 2.0 1.0 00..00 11.66 11.88 22.00 22.22 22.44 22.66 22.88 33.00 33.22 33.44 33.66 33.88 VDD(V) FIGURE 31-39: IPD, TIMER1 OSCILLATOR (FOSC = 32 kHz), PIC12F1822 AND PIC16F1823 ONLY 5500 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) 4455 Typical: 25°C Max. 40 35 30 A) μμ (( 2255 TTyyppiiccaall DD PP II 2200 15 10 55 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 379

PIC12(L)F1822/16(L)F1823 FIGURE 31-40: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC12LF1822 AND PIC16LF1823 ONLY 1144 12 Max. 10 A) 8 (μ TTyyppiiccaall DD PP II 66 4 Max: 85°C + 3(cid:305) 2 Typical: 25°C 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-41: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC12F1822 AND PIC16F1823 ONLY 6600 Max: 85°C + 3(cid:305) 50 Typical: 25°C Max. 40 A) μμ TTyyppiiccaall (( 3300 DD PP II 20 10 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001413E-page 380  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-42: IPD, COMPARATOR, NORMAL-POWER MODE (CxSP = 1), PIC12LF1822 AND PIC16LF1823 ONLY 6600 Max: 85°C + 3(cid:305) 50 Typical: 25°C 40 Max. A)A ((μμ 3300 DD PP II TTyyppiiccaall 20 10 00 11.66 11.88 22.00 22.22 22.44 22.66 22.88 33.00 33.22 33.44 33.66 33.88 VDD(V) FIGURE 31-43: IPD, COMPARATOR, NORMAL-POWER MODE (CxSP = 1), PIC12F1822 AND PIC16F1823 ONLY 7700 MMaaxx.. 60 50 Typical 40 A)A μμ (( DD 3300 PP II 20 Max: 85°C + 3(cid:305) 10 Typical: 25°C 00 11..55 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 381

PIC12(L)F1822/16(L)F1823 FIGURE 31-44: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 1.64 Typical ) 1.62 V ge ( 1.60 Min. a t ol 1.58 V 1.56 Max: Typical + 3(cid:305) 1.54 Typical: 25°C 1.52 Min: Typical -3(cid:305) 1.50 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 31-45: POR REARM VOLTAGE, PIC12F1822 AND PIC16F1823 ONLY 1.54 1.52 Max: Typical + 3(cid:305) Typical: 25°C 1.50 Min: Typical -3(cid:305) Max. 1.48 ) 1.46 V e ( g 1.44 a t Typical ol 1.42 V 1.40 1.38 Min. 1.36 1.34 -40 -20 0 20 40 60 80 100 120 Temperature (°C) DS40001413E-page 382  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-46: WDT TIME-OUT PERIOD 24 22 Max. 20 ) S 18 Typical m e ( m 16 Ti 14 Min. Max: Typical + 3(cid:305)(-40°C to +125°C) 12 Typical: statistical mean @ 25°C Min: Typical -3(cid:305)(-40°C to +125°C) 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Voltage (V) FIGURE 31-47: PWRT PERIOD 110 100 Max. 90 ) S 80 Typical m e ( m 70 Ti Min. 60 Max: Typical + 3(cid:305)(-40°C to +125°C) 50 Typical: statistical mean @ 25°C Min: Typical -3(cid:305)(-40°C to +125°C) 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Voltage (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 383

PIC12(L)F1822/16(L)F1823 FIGURE 31-48: COMPARATOR HYSTERESIS, NORMAL-POWER MODE (CxSP = 1, CxHYS = 1) 80 70 Max. 60 Typical ) V m 50 ( s si 40 e r Min. e t ys 30 H 20 Max: Typical + 3(cid:305) Typical: 25°C 10 Min: Typical -3(cid:305) 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-49: COMPARATOR HYSTERESIS, LOW-POWER MODE (CxSP = 0, CxHYS = 1) 16 14 Max. 12 Typical ) V m 10 ( s si 8 e er Min. t s 6 y H 4 Max: Typical + 3(cid:305) Typical: 25°C 2 Min: Typical -3(cid:305) 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001413E-page 384  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 FIGURE 31-50: COMPARATOR RESPONSE TIME, NORMAL-POWER MODE (CxSP = 1) 350 300 250 Max. S) 200 n e ( Typical m 150 Ti 100 Max: Typical + 3(cid:305) 50 Typical: 25°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-51: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL-POWER MODE (CxSP = 1) 400 350 Graph represents 3(cid:305)Limits 300 250 ) S 125°C n e ( 200 m Ti 150 Typical 100 -40°C 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2010-2015 Microchip Technology Inc. DS40001413E-page 385

PIC12(L)F1822/16(L)F1823 FIGURE 31-52: COMPARATOR INPUT OFFSET AT 25°C, NORMAL-POWER MODE (CxSP = 1), PIC12F1822 AND PIC16F1823 ONLY 50 40 30 Max. 20 ) V 10 m Typical e ( 0 g ta Min. ol -10 V et -20 s f Of -30 Max: Typical + 3(cid:305) Typical: 25°C -40 Min: Typical -3(cid:305) -50 0.0 1.0 2.0 3.0 4.0 5.0 Common Mode Voltage (V) DS40001413E-page 386  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 32.0 DEVELOPMENT SUPPORT 32.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2010-2015 Microchip Technology Inc. DS40001413E-page 387

PIC12(L)F1822/16(L)F1823 32.2 MPLAB XC Compilers 32.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 32.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 32.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001413E-page 388  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 32.6 MPLAB X SIM Software Simulator 32.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 32.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 32.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 32.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2010-2015 Microchip Technology Inc. DS40001413E-page 389

PIC12(L)F1822/16(L)F1823 32.11 Demonstration/Development 32.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001413E-page 390  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 8-Lead PDIP (300 mil) Example XXXXXXXX 12LF1822 XXXXXNNN E / P e 3 017 YYWW 1010 8-Lead SOIC (3.90 mm) Example 12LF1822 E/SN1010 NNN 017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2015 Microchip Technology Inc. DS40001413E-page 391

PIC12(L)F1822/16(L)F1823 33.1 Package Marking Information (Continuation) 8-Lead DFN (3x3x0.9 mm) Example 8-Lead UDFN (3x3x0.5 mm) XXXX MFLO YYWW 1010 NNN 017 PIN 1 PIN 1 TABLE 33-1: 8-LEAD 3x3x0.9 DFN (MF) TOP MARKING Part Number Marking PIC12F1822T-E/MF MFLO PIC12F1822T-I/MF MFMO PIC12LF1822T-E/MF MFPO PIC12LF1822T-I/MF MFNO TABLE 33-2: 8-LEAD 3x3x0.5 UDFN (RF) TOP MARKING Part Number Marking PIC12F1822T-E/RF DABO PIC12F1822T-I/RF DAAO PIC12LF1822T-E/RF DAHO PIC12LF1822T-I/RF DAGO DS40001413E-page 392  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 33.1 Package Marking Information (Continuation) 14-Lead PDIP (300 mil) Example PIC16F1823 -E/Pe3 0910017 14-Lead SOIC (3.90 mm) Example PIC16F1823 -E/SLe3 0910017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2015 Microchip Technology Inc. DS40001413E-page 393

PIC12(L)F1822/16(L)F1823 33.1 Package Marking Information (Continuation) 14-Lead TSSOP (4.4 mm) Example XXXXXXXX F1823EST YYWW 0910 NNN 017 16-Lead QFN (4x4x0.9 mm) Example 16-Lead UQFN (4x4x0.5 mm) PIC16 PIN 1 PIN 1 F1823 E/ML e3 910017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS40001413E-page 394  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 33.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2  2010-2015 Microchip Technology Inc. DS40001413E-page 395

PIC12(L)F1822/16(L)F1823 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2 DS40001413E-page 396  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001413E-page 397

PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001413E-page 398  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2010-2015 Microchip Technology Inc. DS40001413E-page 399

PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001413E-page 400  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001413E-page 401

PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001413E-page 402  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.10 C 1 2 2X 0.10 C TOP VIEW 0.05 C A1 C A SEATING PLANE 8X (A3) 0.05 C SIDE VIEW 0.10 C A B D2 1 2 L 0.10 C A B E2 NOTE 1 K N e 8X b e 0.10 C A B 2 BOTTOM VIEW Microchip Technology Drawing C04-254A Sheet 1 of 2  2010-2015 Microchip Technology Inc. DS40001413E-page 403

PIC12(L)F1822/16(L)F1823 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Terminals N 8 Pitch e 0.65 BSC Overall Height A 0.45 0.50 0.55 Standoff A1 0.00 0.02 0.05 Terminal Thickness A3 0.065 REF Overall Width E 3.00 BSC Exposed Pad Width E2 1.40 1.50 1.60 Overall Length D 3.00 BSC Exposed Pad Length D2 2.20 2.30 2.40 Terminal Width b 0.25 0.30 0.35 Terminal Length L 0.35 0.45 0.55 Terminal-to-Exposed-Pad K 0.20 - - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-254A Sheet 2 of 2 DS40001413E-page 404  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C X2 E Y2 X1 G1 G2 SILK SCREEN Y1 RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.65 BSC Optional Center Pad Width X2 1.60 Optional Center Pad Length Y2 2.40 Contact Pad Spacing C 2.90 Contact Pad Width (X8) X1 0.35 Contact Pad Length (X8) Y1 0.85 Contact Pad to Contact Pad (X6) G1 0.20 Contact Pad to Center Pad (X8) G2 0.30 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2254A ’((cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8))(cid:18)(cid:6)(cid:10)(cid:8)#(cid:19)(cid:3)(cid:4)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:9)(cid:22)(cid:8)(cid:23)(cid:8)(cid:28)(cid:31)(cid:31)(cid:8)(cid:16)(cid:13)(cid:10)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:9))#(cid:9)%  2010-2015 Microchip Technology Inc. DS40001413E-page 405

PIC12(L)F1822/16(L)F1823 ’((cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8))(cid:18)(cid:6)(cid:10)(cid:8)#(cid:19)(cid:3)(cid:4)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:9)(cid:22)(cid:8)(cid:23)(cid:8)(cid:28)(cid:31)(cid:31)(cid:8)(cid:16)(cid:13)(cid:10)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:9))#(cid:9)% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB E(cid:15)(cid:7)(cid:31)" (cid:19)G;H=(cid:22) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)J(cid:7)!(cid:7)(cid:31)" (cid:6)(cid:19)G GK(cid:6) (cid:6)(cid:25)L G#!7(cid:14)(cid:9)(cid:2)(cid:10))(cid:2)((cid:7)(cid:15)" G 1(cid:23) ((cid:7)(cid:31)(cid:8)(cid:11) (cid:14) (cid:20)1(cid:4)(cid:4)(cid:2)A(cid:22); (cid:13)(cid:10)(cid:12)(cid:2)(cid:31)(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)(cid:31)(cid:7)(cid:15)(cid:17)(cid:2)((cid:16)(cid:28)(cid:15)(cid:14) (cid:25) N N (cid:20)(cid:3)1(cid:4) (cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:25)(cid:3) (cid:20)11@ (cid:20)1<(cid:4) (cid:20)1(cid:24)@ A(cid:28)"(cid:14)(cid:2)(cid:31)(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)(cid:31)(cid:7)(cid:15)(cid:17)(cid:2)((cid:16)(cid:28)(cid:15)(cid:14) (cid:25)1 (cid:20)(cid:4)1@ N N (cid:22)(cid:11)(cid:10)#(cid:16)%(cid:14)(cid:9)(cid:2)(cid:31)(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)#(cid:16)%(cid:14)(cid:9)(cid:2)O(cid:7)%(cid:31)(cid:11) = (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)<1(cid:4) (cid:20)<(cid:3)@ (cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)O(cid:7)%(cid:31)(cid:11) =1 (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)@(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) K3(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)J(cid:14)(cid:15)(cid:17)(cid:31)(cid:11) (cid:21) (cid:20)(cid:5)<@ (cid:20)(cid:5)@(cid:4) (cid:20)(cid:5)(cid:5)@ (cid:13)(cid:7)(cid:12)(cid:2)(cid:31)(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)(cid:31)(cid:7)(cid:15)(cid:17)(cid:2)((cid:16)(cid:28)(cid:15)(cid:14) J (cid:20)11@ (cid:20)1<(cid:4) (cid:20)1@(cid:4) J(cid:14)(cid:28)%(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:4)(cid:29) (cid:20)(cid:4)1(cid:4) (cid:20)(cid:4)1@ E(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)J(cid:14)(cid:28)%(cid:2)O(cid:7)%(cid:31)(cid:11) 71 (cid:20)(cid:4)(cid:23)@ (cid:20)(cid:4)Q(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) J(cid:10)&(cid:14)(cid:9)(cid:2)J(cid:14)(cid:28)%(cid:2)O(cid:7)%(cid:31)(cid:11) 7 (cid:20)(cid:4)1(cid:23) (cid:20)(cid:4)1(cid:29) (cid:20)(cid:4)(cid:3)(cid:3) K3(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)&(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)8 (cid:14)A N N (cid:20)(cid:23)<(cid:4) (cid:21)(cid:25)(cid:12)(cid:5)(cid:11)& 1(cid:20) ((cid:7)(cid:15)(cid:2)1(cid:2)3(cid:7)"#(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)%(cid:14)6(cid:2))(cid:14)(cid:28)(cid:31)#(cid:9)(cid:14)(cid:2)!(cid:28)(cid:18)(cid:2)3(cid:28)(cid:9)(cid:18)’(cid:2)7#(cid:31)(cid:2)!#"(cid:31)(cid:2)7(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)&(cid:7)(cid:31)(cid:11)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)(cid:31)(cid:8)(cid:11)(cid:14)%(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) 8(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7))(cid:7)(cid:8)(cid:28)(cid:15)(cid:31)(cid:2);(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)(cid:31)(cid:14)(cid:9)(cid:7)"(cid:31)(cid:7)(cid:8)(cid:20) <(cid:20) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)%(cid:2)=1(cid:2)%(cid:10)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)#%(cid:14)(cid:2)!(cid:10)(cid:16)%(cid:2))(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)#"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)%(cid:2))(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)#"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:14)6(cid:8)(cid:14)(cid:14)%(cid:2)(cid:20)(cid:4)1(cid:4)>(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)%(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)%(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)=(cid:2)?1(cid:23)(cid:20)@(cid:6)(cid:20) A(cid:22);*(cid:2)A(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)(cid:31)(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)6(cid:28)(cid:8)(cid:31)(cid:2)3(cid:28)(cid:16)#(cid:14)(cid:2)"(cid:11)(cid:10)&(cid:15)(cid:2)&(cid:7)(cid:31)(cid:11)(cid:10)#(cid:31)(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17);(cid:4)(cid:23)(cid:27)(cid:4)(cid:4)@A DS40001413E-page 406  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001413E-page 407

PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001413E-page 408  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2010-2015 Microchip Technology Inc. DS40001413E-page 409

PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001413E-page 410  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001413E-page 411

PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001413E-page 412  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 ’*(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)+(cid:18)(cid:6)(cid:7)(cid:8),(cid:10)(cid:6)(cid:12)(cid:27)(cid:8)(cid:21)(cid:25)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)-(cid:6).(cid:5)(cid:8)(cid:20)/(cid:4)(cid:22)(cid:8)(cid:23)(cid:8)(0(0(cid:31)(cid:29)(cid:30)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"+,(cid:21)% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E E2 2 2 b 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A3 A A1 E(cid:15)(cid:7)(cid:31)" (cid:6)(cid:19)JJ(cid:19)(cid:6)=(cid:13)=(cid:26)(cid:22) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)J(cid:7)!(cid:7)(cid:31)" (cid:6)(cid:19)G GK(cid:6) (cid:6)(cid:25)L G#!7(cid:14)(cid:9)(cid:2)(cid:10))(cid:2)((cid:7)(cid:15)" G 1Q ((cid:7)(cid:31)(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)Q@(cid:2)A(cid:22); K3(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)H(cid:14)(cid:7)(cid:17)(cid:11)(cid:31) (cid:25) (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) 1(cid:20)(cid:4)(cid:4) (cid:22)(cid:31)(cid:28)(cid:15)%(cid:10)))(cid:2) (cid:25)1 (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)@ ;(cid:10)(cid:15)(cid:31)(cid:28)(cid:8)(cid:31)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:25)< (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26)=(cid:30) K3(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)O(cid:7)%(cid:31)(cid:11) = (cid:23)(cid:20)(cid:4)(cid:4)(cid:2)A(cid:22); =6(cid:12)(cid:10)"(cid:14)%(cid:2)((cid:28)%(cid:2)O(cid:7)%(cid:31)(cid:11) =(cid:3) (cid:3)(cid:20)@(cid:4) (cid:3)(cid:20)Q@ (cid:3)(cid:20)(cid:29)(cid:4) K3(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)J(cid:14)(cid:15)(cid:17)(cid:31)(cid:11) (cid:21) (cid:23)(cid:20)(cid:4)(cid:4)(cid:2)A(cid:22); =6(cid:12)(cid:10)"(cid:14)%(cid:2)((cid:28)%(cid:2)J(cid:14)(cid:15)(cid:17)(cid:31)(cid:11) (cid:21)(cid:3) (cid:3)(cid:20)@(cid:4) (cid:3)(cid:20)Q@ (cid:3)(cid:20)(cid:29)(cid:4) ;(cid:10)(cid:15)(cid:31)(cid:28)(cid:8)(cid:31)(cid:2)O(cid:7)%(cid:31)(cid:11) 7 (cid:4)(cid:20)(cid:3)@ (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)<@ ;(cid:10)(cid:15)(cid:31)(cid:28)(cid:8)(cid:31)(cid:2)J(cid:14)(cid:15)(cid:17)(cid:31)(cid:11) J (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)@(cid:4) ;(cid:10)(cid:15)(cid:31)(cid:28)(cid:8)(cid:31)(cid:27)(cid:31)(cid:10)(cid:27)=6(cid:12)(cid:10)"(cid:14)%(cid:2)((cid:28)% W (cid:4)(cid:20)(cid:3)(cid:4) N N (cid:21)(cid:25)(cid:12)(cid:5)(cid:11)& 1(cid:20) ((cid:7)(cid:15)(cid:2)1(cid:2)3(cid:7)"#(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)%(cid:14)6(cid:2))(cid:14)(cid:28)(cid:31)#(cid:9)(cid:14)(cid:2)!(cid:28)(cid:18)(cid:2)3(cid:28)(cid:9)(cid:18)’(cid:2)7#(cid:31)(cid:2)!#"(cid:31)(cid:2)7(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)&(cid:7)(cid:31)(cid:11)(cid:7)(cid:15)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)(cid:31)(cid:8)(cid:11)(cid:14)%(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)"(cid:2)"(cid:28)&(cid:2)"(cid:7)(cid:15)(cid:17)#(cid:16)(cid:28)(cid:31)(cid:14)%(cid:20) <(cid:20) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)%(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)=(cid:2)?1(cid:23)(cid:20)@(cid:6)(cid:20) A(cid:22);* A(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)(cid:31)(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)6(cid:28)(cid:8)(cid:31)(cid:2)3(cid:28)(cid:16)#(cid:14)(cid:2)"(cid:11)(cid:10)&(cid:15)(cid:2)&(cid:7)(cid:31)(cid:11)(cid:10)#(cid:31)(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:26)=(cid:30)* (cid:26)(cid:14))(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)’(cid:2)#"#(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)&(cid:7)(cid:31)(cid:11)(cid:10)#(cid:31)(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2))(cid:10)(cid:9)(cid:2)(cid:7)(cid:15))(cid:10)(cid:9)!(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)#(cid:9)(cid:12)(cid:10)"(cid:14)"(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17);(cid:4)(cid:23)(cid:27)1(cid:3)(cid:5)A  2010-2015 Microchip Technology Inc. DS40001413E-page 413

PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001413E-page 414  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X 0.20 C TOP VIEW 0.10 C A1 C SEATING A PLANE 16X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 0.10 C A B E2 2 e 2 1 NOTE 1 K N L 16X b 0.10 C A B e BOTTOM VIEW Microchip Technology Drawing C04-257A Sheet 1 of 2  2010-2015 Microchip Technology Inc. DS40001413E-page 415

PIC12(L)F1822/16(L)F1823 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 16 Pitch e 0.65 BSC Overall Height A 0.45 0.50 0.55 Standoff A1 0.00 0.02 0.05 Terminal Thickness A3 0.127 REF Overall Width E 4.00 BSC Exposed Pad Width E2 2.50 2.60 2.70 Overall Length D 4.00 BSC Exposed Pad Length D2 2.50 2.60 2.70 Terminal Width b 0.25 0.30 0.35 Terminal Length L 0.30 0.40 0.50 Terminal-to-Exposed-Pad K 0.20 - - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-257A Sheet 2 of 2 DS40001413E-page 416  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 16 1 2 C2 Y2 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.65 BSC Optional Center Pad Width X2 2.70 Optional Center Pad Length Y2 2.70 Contact Pad Spacing C1 4.00 Contact Pad Spacing C2 4.00 Contact Pad Width (X16) X1 0.35 Contact Pad Length (X16) Y1 0.80 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2257A  2010-2015 Microchip Technology Inc. DS40001413E-page 417

PIC12(L)F1822/16(L)F1823 APPENDIX A: DATA SHEET APPENDIX B: MIGRATING FROM REVISION HISTORY OTHER PIC® DEVICES Revision A (03/2010) This section provides comparisons when migrating Original release. from other similar PIC® devices to the PIC12(L)F1822/16(L)F1823 family of devices. Revision B (10/2010) B.1 PIC16F648A to PIC16(L)F1823 Added bits 4 and 5 to FVRCON; Revised Register 6-1; Added Note 1 to Register 8-1; Revised Section 12.0; TABLE B-1: FEATURE COMPARISON Added Temperature Indicator Module section, renum- Feature PIC16F648A PIC16(L)F1823 bering sections; Revised Section 16.1.2; Added Note 4 to Register 16-1; Revised Equation 17-1; Revised bit 0 Max. Operating 20MHz 32MHz in Register 23-1; Added Section 24.1.6, Table 24-3, Speed Section 24.2.6, Section 24.3.9, Section 24.4.8; Max. Program 4K 4K Revised Section 24.4.3; Added Note 5 to Register Memory (Words) 25-2; Revised Section 26.1.1.1; Revised MOVIW and Max. SRAM (Bytes) 256 384 MOVWI; Revised Section 30.0 Electrical Max. EEPROM 256 256 Specifications. (Bytes) Revision C (05/2012) A/D Resolution 10-bit 10-bit Timers (8/16-bit) 2/1 4/1 Updated the Family Types table; Updated Figures 1, 2 and 3; Updated Table 3-3; Added section 5.5.3 Brown-out Reset Y Y Fail-Safe Condition Clearing; Replaced Figure 13-1; Internal Pull-ups RB<7:0> RA<5:0>, RA2 Replaced Equation 16-1; Updated Figure 17-1; Interrupt-on-change RB<7:4> RA<5:0>, Edge Updated the Electrical Specifications section; Added Selectable charts to the DC and AC Characteristics Graphs Comparator 2 2 section; Updated the Product Identification System section; Updated the Packaging Information section; AUSART/EUSART 1/0 0/2 Other minor corrections. Extended WDT N Y Software Control N Y Revision D (05/2014) Option of WDT/BOR Updated with new 8-lead UDFN 3x3x0.5mm package. INTOSC 48 kHz or 31kHz - Updated with new 16-lead UQFN 4x4x0.5mm package. Frequencies 4 MHz 32MHz Updated Product Identification System page and Clock Switching Y Y added new specifications for new packages. Capacitive Sensing N Y Updated Equation 16-1. Updated Figures 5-7, 17-1, CCP/ECCP 2/0 2/2 18-1, 19-2, 19-3, 21-1, 27-1, 27-2, 30-4, 30-9. Updated Enhanced PIC16 N Y Registers 8-3, 11-4, 12-11, 19-1, 24-2, 27-1, 27-2. CPU Updated Sections 5.2.2.5, 16.1.2, 17.0, 18.1, 19.6, MSSPx/SSPx 0 2/0 21.6.2.3, 21.6.2.4, 24.4.3, 27.0, 27.1, 27.4, 30-5, 30-6, Reference Clock N Y 33.1. Updated Tables 1-3, 3-3, 3-8, 7-5, 12-2, 12-3, 21-4, 24-2, 25-1, 25-3, 25-4, 26-1, 26-2, 26-7, 26-8, Data Signal N Y 26-9, 26-10, 27-1, 30-8, 30-9, 30-10, 30-11, 30-14, Modulator 30-17. SR Latch N Y Voltage Reference N Y Revision E (4/2015) DAC Y Y Added Section 30.9: High Temperature Operation in the Electrical Specifications section. Updated Register 19-2. DS40001413E-page 418  2010-2015 Microchip Technology Inc.

PIC12(L)F1822/16(L)F1823 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://www.microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2010-2015 Microchip Technology Inc. DS40001413E-page 419

PIC12(L)F1822/PIC16(L)F1823 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X] - X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC12F1822 - I/MF 301 = Industrial temp., DFN Option Range package, QTP pattern #301. b) PIC16F1823 - I/P = Industrial temp., PDIP package. c) PIC16F1823 - E/ST= Extended temp., TSSOP Device: PIC12F1822, PIC12LF1822 package. PIC16F1823, PIC16LF1823 Tape and Reel Blank = standard packaging (tube or tray) Option: T = Tape and Reel(1) Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Package:(2) JQ = Micro Lead Frame (UQFN) 4x4x0.5mm MF = Micro Lead Frame (DFN) 3x3x0.9mm Note1: Tape and Reel identifier only appears in the ML = Micro Lead Frame (QFN) 4x4x0.9mm catalog part number description. This P = Plastic DIP identifier is used for ordering purposes and RF = Micro Lead Frame (UDFN) 3x3x0.5mm is not printed on the device package. Check SL = SOIC with your Microchip Sales Office for package SN = SOIC availability with the Tape and Reel option. ST = TSSOP 2: Small-form factor packaging options may be available. Please check www.microchip.com/packaging for small Pattern: QTP, SQTP, Code or Special Requirements form-factor package availability, or contact (blank otherwise) your local Sales Office. DS40001413E-page 420  2010-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2010-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-253-4 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2010-2015 Microchip Technology Inc. DS40001413E-page 421

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office China - Xiamen Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 86-592-2388138 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 86-592-2388130 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon China - Zhuhai Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 86-756-3210040 Tel: 45-4450-2828 Technical Support: Tel: 852-2943-5100 Fax: 86-756-3210049 Fax: 45-4485-2829 http://www.microchip.com/ Fax: 852-2401-3431 India - Bangalore France - Paris support Australia - Sydney Tel: 91-80-3090-4444 Tel: 33-1-69-53-63-20 Web Address: Tel: 61-2-9868-6733 Fax: 91-80-3090-4123 Fax: 33-1-69-30-90-79 www.microchip.com Fax: 61-2-9868-6755 India - New Delhi Germany - Dusseldorf Atlanta China - Beijing Tel: 91-11-4160-8631 Tel: 49-2129-3766400 Duluth, GA Tel: 678-957-9614 Tel: 86-10-8569-7000 Fax: 91-11-4160-8632 Germany - Munich Fax: 678-957-1455 Fax: 86-10-8528-2104 India - Pune Tel: 49-89-627-144-0 China - Chengdu Tel: 91-20-3019-1500 Fax: 49-89-627-144-44 Austin, TX Tel: 512-257-3370 Tel: 86-28-8665-5511 Japan - Osaka Germany - Pforzheim Fax: 86-28-8665-7889 Tel: 81-6-6152-7160 Tel: 49-7231-424750 Boston Westborough, MA China - Chongqing Fax: 81-6-6152-9310 Italy - Milan Tel: 774-760-0087 Tel: 86-23-8980-9588 Japan - Tokyo Tel: 39-0331-742611 Fax: 86-23-8980-9500 Tel: 81-3-6880- 3770 Fax: 39-0331-466781 Fax: 774-760-0088 China - Dongguan Fax: 81-3-6880-3771 Italy - Venice Chicago Itasca, IL Tel: 86-769-8702-9880 Korea - Daegu Tel: 39-049-7625286 Tel: 630-285-0071 China - Hangzhou Tel: 82-53-744-4301 Netherlands - Drunen Fax: 630-285-0075 Tel: 86-571-8792-8115 Fax: 82-53-744-4302 Tel: 31-416-690399 Fax: 86-571-8792-8116 Korea - Seoul Fax: 31-416-690340 Cleveland Independence, OH China - Hong Kong SAR Tel: 82-2-554-7200 Poland - Warsaw Tel: 216-447-0464 Tel: 852-2943-5100 Fax: 82-2-558-5932 or Tel: 48-22-3325737 Fax: 852-2401-3431 82-2-558-5934 Fax: 216-447-0643 Spain - Madrid Dallas China - Nanjing Malaysia - Kuala Lumpur Tel: 34-91-708-08-90 Addison, TX Tel: 86-25-8473-2460 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91 Fax: 86-25-8473-2470 Fax: 60-3-6201-9859 Tel: 972-818-7423 Sweden - Stockholm Fax: 972-818-2924 China - Qingdao Malaysia - Penang Tel: 46-8-5090-4654 Tel: 86-532-8502-7355 Tel: 60-4-227-8870 Detroit UK - Wokingham Fax: 86-532-8502-7205 Fax: 60-4-227-4068 Novi, MI Tel: 44-118-921-5800 Tel: 248-848-4000 China - Shanghai Philippines - Manila Fax: 44-118-921-5820 Tel: 86-21-5407-5533 Tel: 63-2-634-9065 Houston, TX Fax: 86-21-5407-5066 Fax: 63-2-634-9069 Tel: 281-894-5983 China - Shenyang Singapore Indianapolis Tel: 86-24-2334-2829 Tel: 65-6334-8870 Noblesville, IN Fax: 86-24-2334-2393 Fax: 65-6334-8850 Tel: 317-773-8323 Fax: 317-773-5453 China - Shenzhen Taiwan - Hsin Chu Tel: 86-755-8864-2200 Tel: 886-3-5778-366 Los Angeles Fax: 86-755-8203-1760 Fax: 886-3-5770-955 Mission Viejo, CA Tel: 949-462-9523 China - Wuhan Taiwan - Kaohsiung Fax: 949-462-9608 Tel: 86-27-5980-5300 Tel: 886-7-213-7828 New York, NY Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 631-435-6000 China - Xian Tel: 886-2-2508-8600 Tel: 86-29-8833-7252 Fax: 886-2-2508-0102 San Jose, CA Tel: 408-735-9110 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Canada - Toronto Fax: 66-2-694-1350 Tel: 905-673-0699 Fax: 905-673-6509 01/27/15 DS40001413E-page 422  2010-2015 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC12LF1822-E/P PIC12LF1822-E/SN PIC16LF1823-E/ML PIC16LF1823-E/P PIC16LF1823-E/SL PIC16LF1823- E/ST PIC12F1822-E/P PIC12F1822-E/SN PIC12F1822-I/P PIC12F1822-I/SN PIC12F1822T-I/SN PIC12LF1822-I/P PIC12LF1822-I/SN PIC12LF1822T-I/SN PIC16F1823-E/ML PIC16F1823-E/P PIC16F1823-E/SL PIC16F1823-E/ST PIC16F1823-I/ML PIC16F1823-I/P PIC16F1823-I/SL PIC16F1823-I/ST PIC16F1823T-I/ML PIC16F1823T-I/SL PIC16F1823T-I/ST PIC16LF1823-I/ML PIC16LF1823-I/P PIC16LF1823-I/SL PIC16LF1823-I/ST PIC16LF1823T-I/ML PIC16LF1823T-I/SL PIC16LF1823T-I/ST PIC12F1822-E/MF PIC12F1822-I/MF PIC12F1822T-I/MF PIC12LF1822- I/MF PIC12LF1822T-I/MF PIC12LF1822-E/MF PIC12F1822T-E/MF PIC16F1823-I/JQ PIC16F1823-E/JQ PIC12F1822T-I/RF PIC16F1823T-I/JQ PIC12LF1822T-I/RF PIC16LF1823-I/JQ PIC16LF1823-E/JQ PIC16LF1823T- I/JQ