PIC16CE62X OTP 8-Bit CMOS MCU with EEPROM Data Memory Devices included in this data sheet: Pin Diagrams • PIC16CE623 PDIP, SOIC, Windowed CERDIP (cid:129) PIC16CE624 (cid:129) PIC16CE625 RA2/AN2/VREF (cid:129)1 18 RA1/AN1 High Performance RISC CPU: RAR4A/T30/ACNK3I 23 PIC 1176 ROAS0C/1A/NC0LKIN (cid:129) Only 35 instructions to learn MCLR/VVPSPS 45 16C 1154 OVDSDC2/CLKOUT (cid:129) All single-cycle instructions (200 ns), except for RB0/INT 6 E 13 RB7 program branches which are two-cycle RRBB12 87 62 1121 RRBB65 (cid:129) Operating speed: RB3 9 X 10 RB4 - DC - 20 MHz clock input - DC - 200 ns instruction cycle Device Program RAM EEPROM SSOP Memory Data Data Memory Memory RA2/AN2/VREF (cid:129)1 20 RA1/AN1 PIC16CE623 512x14 96x8 128x8 RAR4A/T3/0ACNK3I 23 PIC 1198 ROAS0C/1A/NC0LKIN MCLR/VPP 4 1 17 OSC2/CLKOUT PIC16CE624 1Kx14 96x8 128x8 VSS 5 6 16 VDD PIC16CE625 2Kx14 128x8 128x8 RB0/VINSTS 67 CE6 1154 RVDBD7 RB1 8 2 13 RB6 (cid:129) Interrupt capability RB2 9 X 12 RB5 RRBB33 10 11 RB4 (cid:129) 16 special function hardware registers (cid:129) 8-level deep hardware stack (cid:129) Direct, Indirect and Relative addressing modes Peripheral Features: Special Microcontroller Features (cont’d) (cid:129) 13 I/O pins with individual direction control (cid:129) 1,000,000 erase/write cycle EEPROM data (cid:129) High current sink/source for direct LED drive memory (cid:129) Analog comparator module with: (cid:129) EEPROM data retention > 40 years - Two analog comparators (cid:129) Programmable code protection - Programmable on-chip voltage reference (cid:129) Power saving SLEEP mode (VREF) module (cid:129) Selectable oscillator options - Programmable input multiplexing from device (cid:129) Four user programmable ID locations inputs and internal voltage reference CMOS Technology: - Comparator outputs can be output signals (cid:129) Timer0: 8-bit timer/counter with 8-bit (cid:129) Low-power, high-speed CMOS EPROM/EEPROM programmable prescaler technology (cid:129) Fully static design Special Microcontroller Features: (cid:129) Wide operating voltage range (cid:129) In-Circuit Serial Programming (ICSP™) (via two - 2.5V to 5.5V pins) (cid:129) Commercial, industrial and extended temperature (cid:129) Power-on Reset (POR) range (cid:129) Power-up Timer (PWRT) and Oscillator Start-up (cid:129) Low power consumption Timer (OST) - < 2.0 mA @ 5.0V, 4.0 MHz (cid:129) Brown-out Reset - 15 A typical @ 3.0V, 32 kHz (cid:129) Watchdog Timer (WDT) with its own on-chip RC - < 1.0 A typical standby current @ 3.0V oscillator for reliable operation  1998-2013 Microchip Technology Inc. DS40182D-page 1

PIC16CE62X Table of Contents 1.0 General Description...............................................................................................................................................3 2.0 PIC16CE62X Device Varieties..............................................................................................................................5 3.0 Architectural Overview...........................................................................................................................................7 4.0 Memory Organization..........................................................................................................................................11 5.0 I/O Ports...............................................................................................................................................................23 6.0 EEPROM Peripheral Operation...........................................................................................................................29 7.0 Timer0 Module.....................................................................................................................................................35 8.0 Comparator Module.............................................................................................................................................41 9.0 Voltage Reference Module..................................................................................................................................47 10.0 Special Features of the CPU...............................................................................................................................49 11.0 Instruction Set Summary.....................................................................................................................................65 12.0 Development Support..........................................................................................................................................77 13.0 Electrical Specifications.......................................................................................................................................83 14.0 Packaging Information.........................................................................................................................................97 Appendix A: Code for Accessing EEPROM Data Memory........................................................................................103 Index ..........................................................................................................................................................................105 On Line Support..........................................................................................................................................................107 Reader Response.......................................................................................................................................................108 PIC16CE62X Product Identification System ..............................................................................................................109 To Our Valued Customers Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi- sion of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: (cid:129) Microchip’s Worldwide Web site; http://www.microchip.com (cid:129) Your local Microchip sales office (see last page) (cid:129) The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: (cid:129) Fill out and mail in the reader response form in the back of this data sheet. (cid:129) E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. DS40182D-page 2  1998-2013 Microchip Technology Inc.

PIC16CE62X 1.0 GENERAL DESCRIPTION A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software The PIC16CE62X are 18 and 20-Pin EPROM-based lock- up. members of the versatile PIC® family of low-cost, high-performance, CMOS, fully-static, 8-bit A UV-erasable CERDIP-packaged version is ideal for microcontrollers with EEPROM data memory. code development, while the cost-effective One-Time Programmable (OTP) version is suitable for production All PIC® microcontrollers employ an advanced RISC in any volume. architecture. The PIC16CE62X family has enhanced core features, eight-level deep stack, and multiple inter- Table1-1 shows the features of the PIC16CE62X nal and external interrupt sources. The separate mid-range microcontroller families. instruction and data buses of the Harvard architecture A simplified block diagram of the PIC16CE62X is allow a 14-bit wide instruction word with separate 8-bit shown in Figure3-1. wide data. The two-stage instruction pipeline allows all The PIC16CE62X series fits perfectly in applications instructions to execute in a single-cycle, except for pro- ranging from multi-pocket battery chargers to gram branches (which require two cycles). A total of 35 low-power remote sensors. The EPROM technology instructions (reduced instruction set) are available. makes customization of application programs (detec- Additionally, a large register set gives some of the tion levels, pulse generation, timers, etc.) extremely architectural innovations used to achieve a very high fast and convenient. The small footprint packages performance. make this microcontroller series perfect for all applica- PIC16CE62X microcontrollers typically achieve a 2:1 tions with space limitations. Low-cost, low-power, code compression and a 4:1 speed improvement over high-performance, ease of use and I/O flexibility make other 8-bit microcontrollers in their class. the PIC16CE62X very versatile. The PIC16CE623 and PIC16CE624 have 96 bytes of 1.1 Development Support RAM. The PIC16CE625 has 128 bytes of RAM. Each microcontroller contains a 128x8 EEPROM memory The PIC16CE62X family is supported by a full-featured array for storing non-volatile information, such as cali- macro assembler, a software simulator, an in-circuit bration data or security codes. This memory has an emulator, a low-cost development programmer and a endurance of 1,000,000 erase/write cycles and a reten- full-featured programmer. A “C” compiler is also tion of 40 plus years. available. Each device has 13 I/O pins and an 8-bit timer/counter with an 8-bit programmable prescaler. In addition, the PIC16CE62X adds two analog comparators with a programmable on-chip voltage reference module. The comparator module is ideally suited for applications requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers,etc). PIC16CE62X devices have special features to reduce external components, thus reducing system cost, enhancing system reliability and reducing power con- sumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power savings. The user can wake-up the chip from SLEEP through several external and internal interrupts and reset.  1998-2013 Microchip Technology Inc. DS40182D-page 3

PIC16CE62X TABLE 1-1: PIC16CE62X FAMILY OF DEVICES PIC16CE623 PIC16CE624 PIC16CE625 Clock Maximum Frequency of Operation (MHz) 20 20 20 EPROM Program Memory (x14 words) 512 1K 2K Memory Data Memory (bytes) 96 96 128 EEPROM Data Memory (bytes) 128 128 128 Timer Module(s) TMR0 TMR0 TMR0 Peripherals Comparators(s) 2 2 2 Internal Reference Voltage Yes Yes Yes Interrupt Sources 4 4 4 I/O Pins 13 13 13 Voltage Range (Volts) 2.5-5.5 2.5-5.5 2.5-5.5 Features Brown-out Reset Yes Yes Yes Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16CE62X Family devices use serial programming with clock pin RB6 and data pin RB7. DS40182D-page 4  1998-2013 Microchip Technology Inc.

PIC16CE62X 2.0 PIC16CE62X DEVICE 2.3 Quick-Turn-Programming (QTP) VARIETIES Devices A variety of frequency ranges and packaging options are Microchip offers a QTP Programming Service for available. Depending on application and production factory production orders. This service is made requirements the proper device option can be selected available for users who chose not to program a medium using the information in the PIC16CE62X Product to high quantity of units and whose code patterns have Identification System section at the end of this data stabilized. The devices are identical to the OTP devices sheet. When placing orders, please use this page of the but with all EPROM locations and configuration options data sheet to specify the correct part number. already programmed by the factory. Certain code and prototype verification procedures apply before 2.1 UV Erasable Devices production shipments are available. Please contact your Microchip Technology sales office for more details. The UV erasable version, offered in the CERDIP pack- age is optimal for prototype development and pilot 2.4 Serialized Quick-Turn-Programming programs. This version can be erased and (SQTPSM) Devices reprogrammed to any of the oscillator modes. Microchip's PICSTART and PROMATE Microchip offers a unique programming service where a few user-defined locations in each device are programmers both support programming of the PIC16CE62X. programmed with different serial numbers. The serial numbers may be random, pseudo-random or 2.2 One-Time-Programmable (OTP) sequential. Devices Serial programming allows each device to have a unique number which can serve as an entry-code, The availability of OTP devices is especially useful for password or ID number. customers who need the flexibility for frequent code updates and small volume applications. In addition to the program memory, the configuration bits must also be programmed.  1998-2013 Microchip Technology Inc. DS40182D-page 5

PIC16CE62X NOTES: DS40182D-page 6  1998-2013 Microchip Technology Inc.

PIC16CE62X 3.0 ARCHITECTURAL OVERVIEW The PIC16CE62X devices contain an 8-bit ALU and working register. The ALU is a general purpose The high performance of the PIC16CE62X family can arithmetic unit. It performs arithmetic and Boolean be attributed to a number of architectural features functions between data in the working register and any commonly found in RISC microprocessors. To begin register file. with, the PIC16CE62X uses a Harvard architecture in which program and data are accessed from separate The ALU is 8 bits wide and capable of addition, memories using separate buses. This improves subtraction, shift and logical operations. Unless bandwidth over traditional von Neumann architecture otherwise mentioned, arithmetic operations are two's where program and data are fetched from the same complement in nature. In two-operand instructions, memory. Separating program and data memory further typically one operand is the working register allows instructions to be sized differently than 8-bit wide (Wregister). The other operand is a file register or an data word. Instruction opcodes are 14-bits wide making immediate constant. In single operand instructions, the it possible to have all single word instructions. A 14-bit operand is either the W register or a file register. wide program memory access bus fetches a 14-bit The W register is an 8-bit working register used for ALU instruction in a single cycle. A two-stage pipeline over- operations. It is not an addressable register. laps fetch and execution of instructions. Consequently, Depending on the instruction executed, the ALU may all instructions (35) execute in a single-cycle (200 ns @ affect the values of the Carry (C), Digit Carry (DC), and 20 MHz) except for program branches. Zero (Z) bits in the STATUS register. The C and DC bits The table below lists program memory (EPROM), data operate as a Borrow and Digit Borrow out bit memory (RAM) and non-volatile memory (EEPROM) respectively, bit in subtraction. See the SUBLW and for each PIC16CE62X device. SUBWF instructions for examples. Device Program RAM EEPROM A simplified block diagram is shown in Figure3-1, with Memory Data Data a description of the device pins in Table3-1. Memory Memory PIC16CE623 512x14 96x8 128x8 PIC16CE624 1Kx14 96x8 128x8 PIC16CE625 2Kx14 128x8 128x8 The PIC16CE62X can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped in the data memory. The PIC16CE62X family has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make program- ming with the PIC16CE62X simple yet efficient. In addi- tion, the learning curve is reduced significantly.  1998-2013 Microchip Technology Inc. DS40182D-page 7

PIC16CE62X FIGURE 3-1: BLOCK DIAGRAM Data Memory EEPROM DATA Device Program Memory (RAM) MEMORY PIC16CE623 512 x 14 96 x 8 128 x 8 PIC16CE624 1K x 14 96 x 8 128 x 8 PIC16CE625 2K x 14 128 x 8 128 x 8 Voltage 13 Data Bus 8 Reference Program Counter EPROM Program 8 Level Stack RAM Memory (13-bit) File Registers Program Bus 14 RAM Addr (1) 9 Comparator RA0/AN0 Addr MUX Instruction reg RA1/AN1 Direct Addr 7 8 InAddirderct +- RA2/AN2/VREF RA3/AN3 FSR reg +- STATUS reg TMR0 3 MUX Power-up Timer RA4/T0CKI Instruction Decode & Oscillator Control Start-up Timer ALU Power-on Timing Reset Generation W reg I/O Ports Watchdog OSC1/CLKIN Timer OSC2/CLKOUT Brown-out Reset PORTB MCLR/VPP VDD, VSS EESCL EEPROM Data EESDA Memory EEVDD 128 x 8 EEINTF Note 1: Higher order bits are from the STATUS register. DS40182D-page 8  1998-2013 Microchip Technology Inc.

PIC16CE62X TABLE 3-1: PIC16CE62X PINOUT DESCRIPTION DIP/ SSOP I/O/P Buffer Name SOIC Description Pin # Type Type Pin # OSC1/CLKIN 16 18 I ST/CMOS Oscillator crystal input/external clock source input. OSC2/CLKOUT 15 17 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 4 4 I/P ST Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0/AN0 17 19 I/O ST Analog comparator input RA1/AN1 18 20 I/O ST Analog comparator input RA2/AN2/VREF 1 1 I/O ST Analog comparator input or VREF output RA3/AN3 2 2 I/O ST Analog comparator input /output RA4/T0CKI 3 3 I/O ST Can be selected to be the clock input to the Timer0 timer/counter or a comparator output. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 6 7 I/O TTL/ST(1) RB0/INT can also be selected as an external interrupt pin. RB1 7 8 I/O TTL RB2 8 9 I/O TTL RB3 9 10 I/O TTL RB4 10 11 I/O TTL Interrupt on change pin. RB5 11 12 I/O TTL Interrupt on change pin. (2) RB6 12 13 I/O TTL/ST Interrupt on change pin. Serial programming clock. (2) RB7 13 14 I/O TTL/ST Interrupt on change pin. Serial programming data. VSS 5 5,6 P — Ground reference for logic and I/O pins. VDD 14 15,16 P — Positive supply for logic and I/O pins. Legend: O = output I/O = input/output P = power — = Not used I = Input ST = Schmitt Trigger input TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.  1998-2013 Microchip Technology Inc. DS40182D-page 9

PIC16CE62X 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining The clock input (OSC1/CLKIN pin) is internally divided An “Instruction Cycle” consists of four Q cycles (Q1, by four to generate four non-overlapping quadrature Q2, Q3 and Q4). The instruction fetch and execute are clocks namely Q1, Q2, Q3 and Q4. Internally, the pipelined such that fetch takes one instruction cycle, program counter (PC) is incremented every Q1, the while decode and execute takes another instruction instruction is fetched from the program memory and cycle. However, due to the pipelining, each instruction latched into the instruction register in Q4. The effectively executes in one cycle. If an instruction instruction is decoded and executed during the causes the program counter to change (i.e., GOTO) then following Q1 through Q4. The clocks and instruction two cycles are required to complete the instruction execution flow is shown in Figure3-2. (Example3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC+1 PC+2 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 Fetch 4 Flush 5. Instruction @ Fetch SUB_1 Execute SUB_1 address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. DS40182D-page 10  1998-2013 Microchip Technology Inc.

PIC16CE62X 4.0 MEMORY ORGANIZATION FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR THE 4.1 Program Memory Organization PIC16CE624 The PIC16CE62X has a 13-bit program counter capa- PC<12:0> ble of addressing an 8K x 14 program memory space. CALL, RETURN 13 Only the first 512 x 14 (0000h - 01FFh) for the RETFIE, RETLW PIC16CE623, 1K x 14 (0000h - 03FFh) for the PIC16CE624 and 2K x 14 (0000h - 07FFh) for the Stack Level 1 PIC16CE625 are physically implemented. Accessing a Stack Level 2 location above these boundaries will cause a wrap-around within the first 512 x 14 space (PIC16CE623) or 1K x 14 space (PIC16CE624) or 2K Stack Level 8 x 14 space (PIC16CE625). The reset vector is at 0000h and the interrupt vector is at 0004h (Figure4-1, Reset Vector 000h Figure4-2, Figure4-3). FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16CE623 Interrupt Vector 0004 0005 PC<12:0> On-chip Program CALL, RETURN 13 Memory RETFIE, RETLW 03FFh Stack Level 1 0400h Stack Level 2 1FFFh Stack Level 8 FIGURE 4-3: PROGRAM MEMORY MAP AND STACK FOR THE Reset Vector 000h PIC16CE625 PC<12:0> CALL, RETURN 13 RETFIE, RETLW Interrupt Vector 0004 Stack Level 1 0005 Stack Level 2 On-chip Program Memory Stack Level 8 01FFh Reset Vector 0200h 000h 1FFFh Interrupt Vector 0004 0005 On-chip Program Memory 07FFh 0800h 1FFFh  1998-2013 Microchip Technology Inc. DS40182D-page 11

PIC16CE62X 4.2 Data Memory Organization 4.2.1 GENERAL PURPOSE REGISTER FILE The data memory (Figure4-4 and Figure4-5) is The register file is organized as 96 x 8 in the partitioned into two Banks which contain the General PIC16CE623/624 and 128 x 8 in the PIC16CE625. Purpose Registers and the Special Function Registers. Each is accessed either directly or indirectly through Bank 0 is selected when the RP0 bit is cleared. Bank 1 the File Select Register FSR (Section4.4). is selected when the RP0 bit (STATUS <5>) is set. The Special Function Registers are located in the first 32 locations of each Bank. Register locations 20-7Fh (Bank0) on the PIC16CE623/624 and 20-7Fh (Bank0) and A0-BFh (Bank1) on the PIC16CE625 are General Purpose Registers implemented as static RAM. Some special purpose registers are mapped in Bank 1. In all three microcontrollers, address space F0h-FFh (Bank1) is mapped to 70-7Fh (Bank0) as common RAM. DS40182D-page 12  1998-2013 Microchip Technology Inc.

PIC16CE62X FIGURE 4-4: DATA MEMORY MAP FOR FIGURE 4-5: DATA MEMORY MAP FOR THE PIC16CE623/624 THE PIC16CE625 File File File File Address Address Address Address 00h INDF(1) INDF(1) 80h 00h INDF(1) INDF(1) 80h 01h TMR0 OPTION 81h 01h TMR0 OPTION 81h 02h PCL PCL 82h 02h PCL PCL 82h 03h STATUS STATUS 83h 03h STATUS STATUS 83h 04h FSR FSR 84h 04h FSR FSR 84h 05h PORTA TRISA 85h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 06h PORTB TRISB 86h 07h 87h 07h 87h 08h 88h 08h 88h 09h 89h 09h 89h 0Ah PCLATH PCLATH 8Ah 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Ch PIR1 PIE1 8Ch 0Dh 8Dh 0Dh 8Dh 0Eh PCON 8Eh 0Eh PCON 8Eh 0Fh 8Fh 0Fh 8Fh 10h EEINTF 90h 10h EEINTF 90h 11h 91h 11h 91h 12h 92h 12h 92h 13h 93h 13h 93h 14h 94h 14h 94h 15h 95h 15h 95h 16h 96h 16h 96h 17h 97h 17h 97h 18h 98h 18h 98h 19h 99h 19h 99h 1Ah 9Ah 1Ah 9Ah 1Bh 9Bh 1Bh 9Bh 1Ch 9Ch 1Ch 9Ch 1Dh 9Dh 1Dh 9Dh 1Eh 9Eh 1Eh 9Eh 1Fh CMCON VRCON 9Fh 1Fh CMCON VRCON 9Fh 20h A0h 20h A0h General General Purpose Purpose General Register Register Purpose BFh Register C0h EFh F0h Accesses F0h Accesses 70h-7Fh 70h-7Fh 7Fh FFh 7Fh FFh Bank 0 Bank 1 Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. Note 1: Not a physical register.  1998-2013 Microchip Technology Inc. DS40182D-page 13

PIC16CE62X 4.2.2 SPECIAL FUNCTION REGISTERS The special registers can be classified into two sets (core and peripheral). The Special Function Registers The Special Function Registers are registers used by associated with the “core” functions are described in the CPU and peripheral functions for controlling the this section. Those related to the operation of the desired operation of the device (Table4-1). These peripheral features are described in the section of that registers are static RAM. peripheral feature. TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16CE62X Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on other POR Reset resets(1) Bank 0 Addressing this location uses contents of FSR to address data memory (not a physical 00h INDF xxxx xxxx xxxx xxxx register) 01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h STATUS IRP(2) RP1(2) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 07h Unimplemented — — 08h Unimplemented — — 09h Unimplemented — — 0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — CMIF — — — — — — -0-- ---- -0-- ---- 0Dh-1Eh Unimplemented — — 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 Bank 1 Addressing this location uses contents of FSR to address data memory (not a physical xxxx xxxx xxxx xxxx 80h INDF register) 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 87h Unimplemented — — 88h Unimplemented — — 89h Unimplemented — — 8Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 — CMIE — — — — — — -0-- ---- -0-- ---- 8Dh Unimplemented — — 8Eh PCON — — — — — — POR BOD ---- --0x ---- --uq 8Fh-9Eh Unimplemented — — 90h EEINTF — — — — — EESCL EESDA EEVDD ---- -111 ---- -111 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation. Note 2: IRP & RPI bits are reserved; always maintain these bits clear. DS40182D-page 14  1998-2013 Microchip Technology Inc.

PIC16CE62X 4.2.2.1 STATUS REGISTER It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the The STATUS register, shown in Register4-1, contains STATUS register, because these instructions do not the arithmetic status of the ALU, the RESET status and affect any status bit. For other instructions, not affecting the bank select bits for data memory. any status bits, see the “Instruction Set Summary”. The STATUS register can be the destination for any Note 1: The IRP and RP1 bits (STATUS<7:6>) instruction, like any other register. If the STATUS are not used by the PIC16CE62X and register is the destination for an instruction that affects should be programmed as ’0'. Use of the Z, DC or C bits, then the write to these three bits is these bits as general purpose R/W bits disabled. These bits are set or cleared according to the is NOT recommended, since this may device logic. Furthermore, the TO and PD bits are not affect upward compatibility with future writable. Therefore, the result of an instruction with the products. STATUS register as destination may be different than intended. Note 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in For example, CLRF STATUS will clear the upper-three subtraction. See the SUBLW and SUBWF bits and set the Z bit. This leaves the status register as instructions for examples. 000uu1uu (where u = unchanged). REGISTER 4-1: STATUS REGISTER (ADDRESS 03H OR 83H) Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR reset -x = Unknown at POR reset bit 7: IRP: The IRP bit is reserved on the PIC16CE62X, always maintain this bit clear. bit 6:5 RP<1:O>: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.  1998-2013 Microchip Technology Inc. DS40182D-page 15

PIC16CE62X 4.2.2.2 OPTION REGISTER Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT The OPTION register is a readable and writable (PSA = 1). register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 4-2: OPTION REGISTER (ADDRESS 81H) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR reset -x = Unknown at POR reset bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0: PS<2:0>: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 DS40182D-page 16  1998-2013 Microchip Technology Inc.

PIC16CE62X 4.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of The INTCON register is a readable and writable its corresponding enable bit or the global register which contains the various enable and flag bits enable bit, GIE (INTCON<7>). for all interrupt sources except the comparator module. See Section4.2.2.4 and Section4.2.2.5 for a description of the comparator enable and flag bits. REGISTER 4-3: INTCON REGISTER (ADDRESS 0BH OR 8BH) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR reset -x = Unknown at POR reset bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state  1998-2013 Microchip Technology Inc. DS40182D-page 17

PIC16CE62X 4.2.2.4 PIE1 REGISTER This register contains the individual enable bit for the comparator interrupt. REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — CMIE — — — — — — R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR reset -x = Unknown at POR reset bit 7: Unimplemented: Read as '0' bit 6: CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt bit 5-0: Unimplemented: Read as '0' 4.2.2.5 PIR1 REGISTER This register contains the individual flag bit for the com- parator interrupt. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 4-5: PIR1 REGISTER (ADDRESS 0CH) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — CMIF — — — — — — R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR reset -x = Unknown at POR reset bit 7: Unimplemented: Read as '0' bit 6: CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed 0 = Comparator input has not changed bit 5-0: Unimplemented: Read as '0' DS40182D-page 18  1998-2013 Microchip Technology Inc.

PIC16CE62X 4.2.2.6 PCON REGISTER The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR reset, WDT reset or a Brown-out Reset. Note: BOD is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOD is cleared, indicating a brown-out has occurred. The BOD status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming BODEN bit in the configuration word). REGISTER 4-6: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — POR BOD R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR reset -x = Unknown at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOD: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)  1998-2013 Microchip Technology Inc. DS40182D-page 19

PIC16CE62X 4.3 PCL and PCLATH 4.3.2 STACK The program counter (PC) is 13 bits wide. The low byte The PIC16CE62X family has an 8 level deep x 13-bit comes from the PCL register, which is a readable and wide hardware stack (Figure4-2 and Figure4-3). The writable register. The high byte (PC<12:8>) is not directly stack space is not part of either program or data readable or writable and comes from PCLATH. On any space and the stack pointer is not readable or writ- reset, the PC is cleared. Figure4-6 shows the two able. The PC is PUSHed onto the stack when a CALL situations for the loading of the PC. The upper example in instruction is executed or an interrupt causes a the figure shows how the PC is loaded on a write to PCL branch. The stack is POPed in the event of a (PCLATH<4:0>  PCH). The lower example in the figure RETURN, RETLW or a RETFIE instruction execution. shows how the PC is loaded during a CALL or GOTO PCLATH is not affected by a PUSH or POP operation. instruction (PCLATH<4:3>  PCH). The stack operates as a circular buffer. This means that FIGURE 4-6: LOADING OF PC IN after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first DIFFERENT SITUATIONS push. The tenth push overwrites the second push (and so on). PCH PCL Note 1: There are no STATUS bits to indicate 12 8 7 0 Instruction with stack overflow or stack underflow PC PCL as conditions. Destination PCLATH<4:0> 8 5 ALU result Note 2: There are no instruction/mnemonics called PUSH or POP. These are actions that occur from the execution of the PCLATH CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an PCH PCL interrupt address. 12 11 10 8 7 0 PC GOTO, CALL PCLATH<4:3> 11 2 Opcode <10:0> PCLATH 4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note, “Implementing a Table Read" (AN556). DS40182D-page 20  1998-2013 Microchip Technology Inc.

PIC16CE62X 4.4 Indirect Addressing, INDF and FSR A simple program to clear RAM location 20h-2Fh using Registers indirect addressing is shown in Example4-1. The INDF register is not a physical register. Addressing EXAMPLE 4-1: INDIRECT ADDRESSING the INDF register will cause indirect addressing. movlw 0x20 ;initialize pointer Indirect addressing is possible by using the INDF reg- movwf FSR ;to RAM ister. Any instruction using the INDF register actually NEXT clrf INDF ;clear INDF register accesses data pointed to by the File Select Register incf FSR ;inc pointer (FSR). Reading INDF itself indirectly will produce 00h. btfss FSR,4 ;all done? Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An goto NEXT ;no clear next effective 9-bit address is obtained by concatenating the ;yes continue 8-bit FSR register and the IRP bit (STATUS<7>), as CONTINUE: shown in Figure4-7. However, IRP is not used in the PIC16CE62X. FIGURE 4-7: DIRECT/INDIRECT ADDRESSING PIC16CE62X Direct Addressing Indirect Addressing RP1 RP0(1) 6 from opcode 0 IRP(1) 7 FSR Register 0 bank select location select bank select location select 00 01 10 11 00h 180h not used Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail see Figure4-4 and Figure4-5. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS40182D-page 21

PIC16CE62X NOTES: DS40182D-page 22  1998-2013 Microchip Technology Inc.

PIC16CE62X 5.0 I/O PORTS Note: On reset, the TRISA register is set to all inputs. The digital inputs are disabled and The PIC16CE62X parts have two ports, PORTA and the comparator inputs are forced to ground PORTB. Some pins for these I/O ports are multiplexed to reduce excess current consumption. with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, TRISA controls the direction of the RA pins, even when that pin may not be used as a general purpose I/O pin. they are being used as comparator inputs. The user must make sure to keep the pins configured as inputs 5.1 PORTA and TRISA Registers when using them as comparator inputs. PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input The RA2 pin will also function as the output for the and an open drain output. Port RA4 is multiplexed with the voltage reference. When in this mode, the VREF pin is a T0CKI clock input. All other RA port pins have Schmitt very high impedance output. The user must configure Trigger input levels and full CMOS output drivers. All pins TRISA<2> bit as an input and use high impedance have data direction bits (TRIS registers), which can con- loads. figure these pins as input or output. In one of the comparator modes defined by the A '1' in the TRISA register puts the corresponding output CMCON register, pins RA3 and RA4 become outputs driver in a hi- impedance mode. A '0' in the TRISA register of the comparators. The TRISA<4:3> bits must be puts the contents of the output latch on the selected pin(s). cleared to enable outputs to use this function. Reading the PORTA register reads the status of the pins, EXAMPLE 5-1: INITIALIZING PORTA whereas writing to it will write to the port latch. All write CLRF PORTA ;Initialize PORTA by setting operations are read-modify-write operations. So a write ;output data latches to a port implies that the port pins are first read, then this MOVLW 0X07 ;Turn comparators off and value is modified and written to the port data latch. MOVWF CMCON ;enable pins for I/O ;functions The PORTA pins are multiplexed with comparator and BSF STATUS, RP0 ;Select Bank1 voltage reference functions. The operation of these MOVLW 0x1F ;Value used to initialize pins are selected by control bits in the CMCON ;data direction (Comparator Control Register) register and the MOVWF TRISA ;Set RA<4:0> as inputs VRCON (Voltage Reference Control Register) register. ;TRISA<7:5> are always When selected as a comparator input, these pins will ;read as '0'. read as'0's. FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN FIGURE 5-1: BLOCK DIAGRAM OF RA<1:0> PINS Data Bus D Q Data WR VDD VDD Bus D Q PortA CK Q P WR VDD VDD Data Latch PortA CK Q P D Q Data Latch WR N RA2 Pin D Q TRISA CK Q I/O Pin WR N TRIS Latch VSS TRISA CK Q Analog Input Mode TRIS Latch VSS Analog Schmitt Trigger Input Mode Input Buffer RD TRISA Schmitt Trigger Input Buffer Q D RD TRISA Q D EN EN RD PORTA RD PORTA To Comparator VROE To Comparator VREF  1998-2013 Microchip Technology Inc. DS40182D-page 23

PIC16CE62X FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN Data Comparator Mode = 110 Bus D Q Comparator Output WR VDD VDD PORTA CK Q P Data Latch D Q RA3 Pin WR N TRISA CK Q TRIS Latch VSS Analog Input Mode Schmitt Trigger Input Buffer RD TRISA Q D EN RD PORTA To Comparator FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN Data Comparator Mode = 110 Bus D Q Comparator Output WR PORTA CK Q Data Latch D Q RA4 Pin WR N TRISA CK Q TRIS Latch VSS Schmitt Trigger Input Buffer RD TRISA Q D EN RD PORTA TMR0 Clock Input DS40182D-page 24  1998-2013 Microchip Technology Inc.

PIC16CE62X TABLE 5-1: PORTA FUNCTIONS Buffer Name Bit # Function Type RA0/AN0 bit0 ST Input/output or comparator input RA1/AN1 bit1 ST Input/output or comparator input RA2/AN2/VREF bit2 ST Input/output or comparator input or VREF output RA3/AN3 bit3 ST Input/output or comparator input/output RA4/T0CKI bit4 ST Input/output or external clock input for TMR0 or comparator output. Output is open drain type. Legend: ST = Schmitt Trigger input TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR Resets 05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 Legend: — = Unimplemented locations, read as ‘0’, x = unknown, u = unchanged Note: Shaded bits are not used by PORTA.  1998-2013 Microchip Technology Inc. DS40182D-page 25

PIC16CE62X 5.2 PORTB and TRISB Registers This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the PORTB is an 8-bit wide, bi-directional port. The interrupt in the following manner: corresponding data direction register is TRISB. A '1' in a) Any read or write of PORTB. This will end the the TRISB register puts the corresponding output driver mismatch condition. in a high impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected b) Clear flag bit RBIF. pin(s). A mismatch condition will continue to set flag bit RBIF. Reading PORTB register reads the status of the pins, Reading PORTB will end the mismatch condition and whereas writing to it will write to the port latch. All write allow flag bit RBIF to be cleared. operations are read-modify-write operations. So a write This interrupt on mismatch feature, together with to a port implies that the port pins are first read, then software configurable pull-ups on these four pins allow this value is modified and written to the port data latch. easy interface to a key pad and make it possible for Each of the PORTB pins has a weak internal pull-up wake-up on key-depression. (See AN552, “Implement- (200 A typical). A single control bit can turn on all the ing Wake-Up on Key Strokes”.) pull-ups. This is done by clearing the RBPU Note: If a change on the I/O pin should occur (OPTION<7>) bit. The weak pull-up is automatically when the read operation is being executed turned off when the port pin is configured as an output. (start of the Q2 cycle), then the RBIF inter- The pull-ups are disabled on Power-on Reset. rupt flag may not getset. Four of PORTB’s pins, RB<7:4>, have an interrupt on The interrupt on change feature is recommended for change feature. Only pins configured as inputs can wake-up on key depression operation and operations cause this interrupt to occur (i.e., any RB<7:4> pin con- where PORTB is only used for the interrupt on change figured as an output is excluded from the interrupt on feature. Polling of PORTB is not recommended while change comparison). The input pins of RB<7:4> are using the interrupt on change feature. compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB<7:4> are FIGURE 5-6: BLOCK DIAGRAM OF OR’ed together to generate the RBIF interrupt (flag RB<3:0> PINS latched in INTCON<0>). VDD FIGURE 5-5: BLOCK DIAGRAM OF RBPU(1) P RB<7:4> PINS weak Data Bus Data Latch pull-up I/O pin VDD D Q RBPU(1) P WR PORTB weak CK Data Latch pull-up I/O pin Data Bus D Q D Q TTL WR PORTB CK WR TRISB(1) Input CK Buffer TRIS Latch D Q WR TRISB(1) TTL CK Input RD TRISB Buffer ST Q D Buffer RD PORTB EN RD TRISB Latch Q D RB0/INT RD PORTB EN ST Set RBIF Buffer RD Port From other Q D Note 1: TRISB = 1 enables weak pull-up if RBPU = '0' RB<7:4> pins (OPTION<7>). EN RD Port RB<7:6> in serial programming mode Note 1: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>). DS40182D-page 26  1998-2013 Microchip Technology Inc.

PIC16CE62X TABLE 5-3: PORTB FUNCTIONS Name Bit # Buffer Type Function RB0/INT bit0 TTL/ST(1) Input/output or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock pin. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data pin. Legend: ST = Schmitt Trigger, TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode. TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR Resets 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: u = unchanged, x = unknown Note: Shaded bits are not used by PORTB.  1998-2013 Microchip Technology Inc. DS40182D-page 27

PIC16CE62X 5.3 I/O Programming Considerations EXAMPLE 5-2: READ-MODIFY-WRITE INSTRUCTIONS ON AN 5.3.1 BI-DIRECTIONAL I/O PORTS I/O PORT ;Initial PORT settings: PORTB<7:4> Inputs Any instruction which writes, operates internally as a ; read followed by a write operation. The BCF and BSF ; PORTB<3:0> Outputs instructions, for example, read the register into the ;PORTB<7:6> have external pull-up and are not CPU, execute the bit operation and write the result back ;connected to other circuitry to the register. Caution must be used when these ; instructions are applied to a port with both inputs and ; PORT latch PORT pins outputs defined. For example, a BSF operation on bit5 ; ---------- ---------- of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on BCF PORTB, 7 ;01pp pppp 11pp pppp BCF PORTB, 6 ;10pp pppp 11pp pppp bit5 and PORTB is written to the output latches. If BSF STATUS,RP0 ; another bit of PORTB is used as a bidirectional I/O pin BCF TRISB, 7 ;10pp pppp 11pp pppp (i.e., bit0) and it is defined as an input at this time, the BCF TRISB, 6 ;10pp pppp 10pp pppp input signal present on the pin itself would be read into ; the CPU and re-written to the data latch of this ;Note that the user may have expected the pin particular pin, overwriting the previous content. As long ;values to be 00pp pppp. The 2nd BCF caused as the pin stays in the input mode, no problem occurs. ;RB7 to be latched as the pin value (High). However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. 5.3.2 SUCCESSIVE OPERATIONS ON I/O PORTS Reading the port register, reads the values of the port The actual write to an I/O port happens at the end of an pins. Writing to the port register writes the value to the instruction cycle, whereas for reading, the data must be port latch. When using read modify write instructions valid at the beginning of the instruction cycle (i.e., BCF, BSF, etc.) on a port, the value of the port pins (Figure5-7). Therefore, care must be exercised if a is read, the desired operation is done to this value, and write followed by a read operation is carried out on the this value is then written to the port latch. same I/O port. The sequence of instructions should Example5-2 shows the effect of two sequential allow the pin voltage to stabilize (load dependent) read-modify-write instructions (i.e., BCF, BSF, etc.) on before the next instruction causes that file to be read an I/Oport. into the CPU. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. A pin actively outputting a Low or High should not be When in doubt, it is better to separate these instruc- driven from external devices at the same time in order tions with an NOP or another instruction not accessing to change the level on this pin (“wired-or”, “wired-and”). this I/O port. The resulting high output currents may damage the chip. FIGURE 5-7: SUCCESSIVE I/O OPERATION Note: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC This example shows write to PORTB PC PC PC + 1 PC + 2 PC + 3 followed by a read from PORTB. InIsntsrutrcutiocnti o n MOVWF PORTB MOVF PORTB, W NOP NOP Note that: feFtechtcehded Write to Read PORTB PORTB data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and RRBB< <77:0:0>> TPD = propagation delay of Q1 cycle to output valid. Port pin Therefore, at higher clock frequencies, sampled here a write followed by a read may be TPD problematic. Execute Execute Execute MOVWF MOVF NOP PORTB PORTB, W DS40182D-page 28  1998-2013 Microchip Technology Inc.

PIC16CE62X 6.0 EEPROM PERIPHERAL The code for these functions is available on our web OPERATION site (www.microchip.com). The code will be accessed by either including the source code FL62XINC.ASM or The PIC16CE623/624/625 each have 128 bytes of by linking FLASH62X.ASM. FLASH62.IMC provides EEPROM data memory. The EEPROM data memory external definition to the calling program. supports a bi-directional, 2-wire bus and data transmis- sion protocol. These two-wires are serial data (SDA) 6.0.1 SERIAL DATA and serial clock (SCL), and are mapped to bit1 and bit2, SDA is a bi-directional pin used to transfer addresses respectively, of the EEINTF register (SFR 90h). In addi- and data into and data out of the memory. tion, the power to the EEPROM can be controlled using bit0 (EEVDD) of the EEINTF register. For most appli- For normal data transfer, SDA is allowed to change only cations, all that is required is calls to the following func- during SCL low. Changes during SCL high are tions: reserved for indicating the START and STOP condi- tions. ; Byte_Write: Byte write routine ; Inputs:EEPROM Address EEADDR 6.0.2 SERIAL CLOCK ; EEPROM Data EEDATA ; Outputs: Return 01 in W if OK, else This SCL input is used to synchronize the data transfer ; return 00 in W to and from the memory. ; ; Read_Current: Read EEPROM at address 6.0.3 EEINTF REGISTER currently held by EE device. ; Inputs:NONE The EEINTF register (SFR 90h) controls the access to ; Outputs: EEPROM Data EEDATA the EEPROM. Register 6-1 details the function of each ; Return 01 in W if OK, else bit. User code must generate the clock and data sig- ; return 00 in W nals. ; ; Read_Random: Read EEPROM byte at supplied ; address ; Inputs:EEPROM Address EEADDR ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, ; else return 00 in W REGISTER 6-1: EEINTF REGISTER (ADDRESS 90h) U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1      EESCL EESDA EEVDD R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-3: Unimplemented: Read as '0' bit 2: EESCL: Clock line to the EEPROM 1 = Clock high 0 = Clock low bit 1: EESDA: Data line to EEPROM 1 = Data line is high (pin is tri-stated, line is pulled high by a pull-up resistor) 0 = Data line is low bit 0: EEVDD: VDD control bit for EEPROM 1 = VDD is turned on to EEPROM 0 = VDD is turned off to EEPROM (all pins are tri-stated and the EEPROM is powered down) Note: EESDA, EESCL and EEVDD will read ‘0’ if EEVDD is turned off.  1998-2013 Microchip Technology Inc. DS40182D-page 29

PIC16CE62X 6.1 Bus Characteristics 6.1.5 ACKNOWLEDGE In this section, the term “processor” refers to the portion The EEPROM will generate an acknowledge after the of the PIC16CE62X that interfaces to the EEPROM reception of each byte. The processor must generate through software manipulating the EEINTF register. an extra clock pulse which is associated with this The following bus protocol is to be used with the acknowledge bit. EEPROM data memory. Note: Acknowledge bits are not generated if an (cid:129) Data transfer may be initiated only when the bus internal programming cycle is in progress. is not busy. When the EEPROM acknowledges, it pulls down the (cid:129) During data transfer, the data line must remain SDA line during the acknowledge clock pulse in such a stable whenever the clock line is HIGH. Changes way that the SDA line is stable LOW during the HIGH in the data line while the clock line is HIGH will be period of the acknowledge related clock pulse. Of interpreted by the EEPROM as a START or STOP course, setup and hold times must be taken into condition. account. The processor must signal an end of data to Accordingly, the following bus conditions have been the EEPROM by not generating an acknowledge bit on defined (Figure6-1). the last byte that has been clocked out of the EEPROM. In this case, the EEPROM must leave the data line 6.1.1 BUS NOT BUSY (A) HIGH to enable the processor to generate the STOP condition (Figure6-2). Both data and clock lines remain HIGH. 6.1.2 START DATA TRANSFER (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 6.1.3 STOP DATA TRANSFER (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. 6.1.4 DATA VALID (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the processor and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first-in, first-out fashion. DS40182D-page 30  1998-2013 Microchip Technology Inc.

PIC16CE62X FIGURE 6-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (C) (D) (C) (A) SCL SDA START ADDRESS OR DATA STOP CONDITION ACKNOWLEDGE ALLOWED CONDITION VALID TO CHANGE FIGURE 6-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point Receiver must release the SDA line at this allowing the Receiver to pull the SDA line low to point so the Transmitter can continue acknowledge the previous eight bits of data. sending data. 6.2 Device Addressing FIGURE 6-3: CONTROL BYTE FORMAT After generating a START condition, the processor Read/Write Bit transmits a control byte consisting of a EEPROM address and a Read/Write bit that indicates what type Device Select Don’t Care of operation is to be performed. The EEPROM address Bits Bits consists of a 4-bit device code (1010) followed by three don't care bits. S 1 0 1 0 X X X R/W ACK The last bit of the control byte determines the operation to be performed. When set to a one, a read operation EEPROM Address is selected, and when set to a zero, a write operation is selected. (Figure6-3). The bus is monitored for its cor- Start Bit Acknowledge Bit responding EEPROM address all the time. It generates an acknowledge bit if the EEPROM address was true and it is not in a programming mode.  1998-2013 Microchip Technology Inc. DS40182D-page 31

PIC16CE62X 6.3 Write Operations 6.4 Acknowledge Polling 6.3.1 BYTE WRITE Since the EEPROM will not acknowledge during a write cycle, this can be used to determine when the cycle is Following the start signal from the processor, the complete (this feature can be used to maximize bus device code (4 bits), the don't care bits (3 bits), and the throughput). Once the stop condition for a write com- R/W bit, which is a logic low, is placed onto the bus by mand has been issued from the processor, the the processor. This indicates to the EEPROM that a EEPROM initiates the internally timed write cycle. ACK byte with a word address will follow after it has gener- polling can be initiated immediately. This involves the ated an acknowledge bit during the ninth clock cycle. processor sending a start condition followed by the Therefore, the next byte transmitted by the processor is control byte for a write command (R/W = 0). If the the word address and will be written into the address device is still busy with the write cycle, then no ACK will pointer of the EEPROM. After receiving another be returned. If no ACK is returned, then the start bit and acknowledge signal from the EEPROM, the processor control byte must be re-sent. If the cycle is complete, will transmit the data word to be written into the then the device will return the ACK and the processor addressed memory location. The EEPROM acknowl- can then proceed with the next read or write command. edges again and the processor generates a stop con- See Figure6-4 for flow diagram. dition. This initiates the internal write cycle, and during this time, the EEPROM will not generate acknowledge FIGURE 6-4: ACKNOWLEDGE POLLING signals (Figure6-5). FLOW 6.3.2 PAGE WRITE Send The write control byte, word address and the first data Write Command byte are transmitted to the EEPROM in the same way as in a byte write. But instead of generating a stop con- dition, the processor transmits up to eight data bytes to Send Stop the EEPROM, which are temporarily stored in the on- Condition to chip page buffer and will be written into the memory Initiate Write Cycle after the processor has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. Send Start The higher order five bits of the word address remains constant. If the processor should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously Send Control Byte received data will be overwritten. As with the byte write with R/W = 0 operation, once the stop condition is received, an inter- nal write cycle will begin (Figure6-6). Did EEPROM NO Acknowledge (ACK = 0)? YES Next Operation FIGURE 6-5: BYTE WRITE S S T BUS ACTIVITY CONTROL WORD T PROCESSOR A BYTE ADDRESS DATA O R P T SDA LINE S 1 0 1 0 X X X 0 X P A A A BUS ACTIVITY C C C K K K X = Don’t Care Bit DS40182D-page 32  1998-2013 Microchip Technology Inc.

PIC16CE62X FIGURE 6-6: PAGE WRITE BUS ACTIVITY S PROCESSOR T CONTROL WORD S AR BYTE ADDRESS (n) DATAn DATAn + 1 DATAn + 7 TO T P SDA LINE S P A A A A A C C C C C BUS ACTIVITY K K K K K 6.5 Read Operation 6.8 Sequential Read Read operations are initiated in the same way as write Sequential reads are initiated in the same way as a ran- operations with the exception that the R/W bit of the dom read except that after the EEPROM transmits the EEPROM address is set to one. There are three basic first data byte, the processor issues an acknowledge as types of read operations: current address read, random opposed to a stop condition in a random read. This read, and sequential read. directs the EEPROM to transmit the next sequentially addressed 8-bit word (Figure6-9). 6.6 Current Address Read To provide sequential reads, the EEPROM contains an The EEPROM contains an address counter that main- internal address pointer which is incremented by one at tains the address of the last word accessed, internally the completion of each operation. This address pointer incremented by one. Therefore, if the previous access allows the entire memory contents to be serially read (either a read or write operation) was to address n, the during one operation. next current address read operation would access data 6.9 Noise Protection from address n + 1. Upon receipt of the EEPROM address with R/W bit set to one, the EEPROM issues The EEPROM employs a VCC threshold detector cir- an acknowledge and transmits the eight bit data word. cuit, which disables the internal erase/write logic if the The processor will not acknowledge the transfer, but VCC is below 1.5 volts at nominal conditions. does generate a stop condition and the EEPROM dis- continues transmission (Figure6-7). The SCL and SDA inputs have Schmitt trigger and filter circuits, which suppress noise spikes to assure proper 6.7 Random Read device operation even on a noisy bus. Random read operations allow the processor to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the EEPROM as part of a write operation. After the word address is sent, the processor generates a start condi- tion following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the processor issues the control byte again, but with the R/W bit set to a one. The EEPROM will then issue an acknowledge and trans- mits the eight bit data word. The processor will not acknowledge the transfer, but does generate a stop condition and the EEPROM discontinues transmission (Figure6-8).  1998-2013 Microchip Technology Inc. DS40182D-page 33

PIC16CE62X FIGURE 6-7: CURRENT ADDRESS READ S BUS ACTIVITY TA CONTROL ST PROCESSOR R BYTE DATAn O T P SDA LINE S P BUS ACTIVITY A N C O K A C K FIGURE 6-8: RANDOM READ S S T T S BUS ACTIVITY A CONTROL WORD A CONTROL T PROCESSOR R BYTE ADDRESS (n) R BYTE DATAn O T T P SDA LINE S S P A A A N BUS ACTIVITY C C C O K K K A C K FIGURE 6-9: SEQUENTIAL READ S A A A T BUS ACTIVITY CONTROL C C C O PROCESSOR BYTE K K K P SDA LINE P A N BUS ACTIVITY C DATAn DATAn + 1 DATAn + 2 DATAn + X O K A C K DS40182D-page 34  1998-2013 Microchip Technology Inc.

PIC16CE62X 7.0 TIMER0 MODULE bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are The Timer0 module timer/counter has the following discussed in detail in Section7.2. features: The prescaler is shared between the Timer0 module (cid:129) 8-bit timer/counter and the Watchdog Timer. The prescaler assignment is (cid:129) Readable and writable controlled in software by the control bit PSA (cid:129) 8-bit software programmable prescaler (OPTION<3>). Clearing the PSA bit will assign the (cid:129) Internal or external clock select prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 (cid:129) Interrupt on overflow from FFh to 00h module, prescale value of 1:2, 1:4, ..., 1:256 are (cid:129) Edge select for external clock selectable. Section7.3 details the operation of the Figure7-1 is a simplified block diagram of the Timer0 prescaler. module. 7.1 Timer0 Interrupt Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the TMR0 will increment Timer0 interrupt is generated when the TMR0 register every instruction cycle (without prescaler). If Timer0 is timer/counter overflows from FFh to 00h. This overflow written, the increment is inhibited for the following two sets the T0IF bit. The interrupt can be masked by cycles (Figure7-2 and Figure7-3). The user can work clearing the T0IE bit (INTCON<5>). The T0IF bit around this by writing an adjusted value to TMR0. (INTCON<2>) must be cleared in software by the Counter mode is selected by setting the T0CS bit. In Timer0 module interrupt service routine before this mode Timer0 will increment either on every rising re-enabling this interrupt. The Timer0 interrupt cannot or falling edge of pin RA4/T0CKI. The incrementing wake the processor from SLEEP since the timer is shut edge is determined by the source edge (T0SE) control off during SLEEP. See Figure7-4 for Timer0 interrupt timing. FIGURE 7-1: TIMER0 BLOCK DIAGRAM Data Bus RA4/T0CKI FOSC/4 0 pin PSout 8 1 Sync with 1 Internal TMR0 clocks Programmable 0 PSout Prescaler T0SE (2 TCY delay) Set Flag bit T0IF PS<2:0> PSA on Overflow T0CS Note 1: Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register. 2: The prescaler is shared with Watchdog Timer (Figure7-6) FIGURE 7-2: TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction Fetch MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W TMR0 T0 T0+1 T0+2 NT0 NT0+1 NT0+2 T0 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2  1998-2013 Microchip Technology Inc. DS40182D-page 35

PIC16CE62X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch TMR0 T0 T0+1 NT0 NT0+1 Instruction Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 FIGURE 7-4: TIMER0 INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) TMR0 timer FEh FFh 00h 01h 02h 1 1 T0IF bit (INTCON<2>) GIE bit (INTCON<7>) Interrupt Latency Time INSTRUCTION FLOW PC PC PC +1 PC +1 0004h 0005h Instruction fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h) Instruction executed Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h) Note 1: T0IF interrupt flag is sampled here (every Q1). 2: Interrupt latency = 3TCY, where TCY = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. DS40182D-page 36  1998-2013 Microchip Technology Inc.

PIC16CE62X 7.2 Using Timer0 with External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type When an external clock input is used for Timer0, it must prescaler so that the prescaler output is symmetrical. meet certain requirements. The external clock For the external clock to meet the sampling requirement is due to internal phase clock (TOSC) requirement, the ripple-counter must be taken into synchronization. Also, there is a delay in the actual account. Therefore, it is necessary for T0CKI to have a incrementing of Timer0 after synchronization. period of at least 4TOSC (and a small RC delay of 40ns) divided by the prescaler value. The only requirement on 7.2.1 EXTERNAL CLOCK SYNCHRONIZATION T0CKI high and low time is that they do not violate the When no prescaler is used, the external clock input is minimum pulse width requirement of 10ns. Refer to the same as the prescaler output. The synchronization parameters 40, 41 and 42 in the electrical specification of T0CKI with the internal phase clocks is of the desired device. accomplished by sampling the prescaler output on the 7.2.2 TIMER0 INCREMENT DELAY Q2 and Q4 cycles of the internal phase clocks (Figure7-5). Therefore, it is necessary for T0CKI to be Since the prescaler output is synchronized with the high for at least 2TOSC (and a small RC delay of 20 ns) internal clocks, there is a small delay from the time the and low for at least 2TOSC (and a small RC delay of external clock edge occurs to the time the TMR0 is 20ns). Refer to the electrical specification of the actually incremented. Figure7-5 shows the delay from desired device. the external clock edge to the timer incrementing. FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse External Clock Input or Prescaler output (2) misses sampling (1) (3) External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = ±4TOSC max. 2: External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.  1998-2013 Microchip Technology Inc. DS40182D-page 37

PIC16CE62X 7.3 Prescaler The PSA and PS<2:0> bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. An 8-bit counter is available as a prescaler for the When assigned to the Timer0 module, all instructions Timer0 module, or as a postscaler for the Watchdog writing to the TMR0 register (i.e., CLRF 1, MOVWF 1, Timer, respectively (Figure7-6). For simplicity, this BSF 1,x....etc.) will clear the prescaler. When counter is being referred to as “prescaler” throughout assigned to WDT, a CLRWDT instruction will clear the this data sheet. Note that there is only one prescaler prescaler along with the Watchdog Timer. The available which is mutually exclusive between the prescaler is not readable or writable. Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer and vice-versa. FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKOUT (= FOSC/4) Data Bus 8 M 0 1 T0CKI U M SYNC pin 1 X 0 U 2 TMR0 reg X Cycles T0SE T0CS PSA Set flag bit T0IF on Overflow 0 8-bit Prescaler M U Watchdog 1 X 8 Timer 8-to-1MUX PS<2:0> PSA 0 1 WDT Enable bit M U X PSA WDT Time-out Note: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. DS40182D-page 38  1998-2013 Microchip Technology Inc.

PIC16CE62X 7.3.1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the TMR0 module, use the sequence shown in Example7-2. This The prescaler assignment is fully under software precaution must be taken even if the WDT is disabled. control (i.e., it can be changed “on-the-fly” during program execution). To avoid an unintended device EXAMPLE 7-2: CHANGING PRESCALER RESET, the following instruction sequence (WDTTIMER0) (Example7-1) must be executed when changing the prescaler assignment from Timer0 to WDT. CLRWDT ;Clear WDT and ;prescaler EXAMPLE 7-1: CHANGING PRESCALER BSF STATUS, RP0 (TIMER0WDT) MOVLW b'xxxx0xxx' ;Select TMR0, new 1.BCF STATUS, RP0 ;Skip if already in ;prescale value and ; Bank 0 ;clock source 2.CLRWDT ;Clear WDT MOVWF OPTION_REG 3.CLRF TMR0 ;Clear TMR0 & Prescaler BCF STATUS, RP0 4.BSF STATUS, RP0 ;Bank 1 5.MOVLW '00101111’b ;These 3 lines (5, 6, 7) 6.MOVWF OPTION ; are required only if ; desired PS<2:0> are 7.CLRWDT ; 000 or 001 8.MOVLW '00101xxx’b ;Set Postscaler to 9.MOVWF OPTION ; desired WDT rate 10.BCF STATUS, RP0 ;Return to Bank 0 TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR Resets 01h TMR0 Timer0 module register xxxx xxxx uuuu uuuu 0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 Legend: — = Unimplemented locations, read as ‘0’, x = unknown, u = unchanged. Note: Shaded bits are not used by TMR0 module.  1998-2013 Microchip Technology Inc. DS40182D-page 39

PIC16CE62X NOTES: DS40182D-page 40  1998-2013 Microchip Technology Inc.

PIC16CE62X 8.0 COMPARATOR MODULE The CMCON register, shown in Register8-1, controls the comparator input and output multiplexers. A block The comparator module contains two analog diagram of the comparator is shown in Figure8-1. comparators. The inputs to the comparators are multiplexed with the RA0 through RA3 pins. The on-chip voltage reference (Section9.0) can also be an input to the comparators. REGISTER 8-1: CMCON REGISTER (ADDRESS 1Fh) R-0 R-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT — — CIS CM2 CM1 CM0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: C2OUT: Comparator 2 output 1 = C2 VIN+ > C2 VIN– 0 = C2 VIN+ < C2 VIN– bit 6: C1OUT: Comparator 1 output 1 = C1 VIN+ > C1 VIN– 0 = C1 VIN+ < C1 VIN– bit 5-4: Unimplemented: Read as '0' bit 3: CIS: Comparator Input Switch When CM<2:0>: = 001: 1 = C1 VIN– connects to RA3 0 = C1 VIN– connects to RA0 When CM<2:0> = 010: 1 = C1 VIN– connects to RA3 C2 VIN– connects to RA2 0 = C1 VIN– connects to RA0 C2 VIN– connects to RA1 bit 2-0: CM<2:0>: Comparator mode Figure8-1.  1998-2013 Microchip Technology Inc. DS40182D-page 41

PIC16CE62X 8.1 Comparator Configuration mode is changed, the comparator output level may not be valid for the specified mode change delay shown There are eight modes of operation for the in Table13-1. comparators. The CMCON register is used to select Note: Comparator interrupts should be disabled the mode. Figure8-1 shows the eight possible modes. during a comparator mode change, other- The TRISA register controls the data direction of the wise a false interrupt may occur. comparator pins for each mode. If the comparator FIGURE 8-1: COMPARATOR I/O OPERATING MODES A VIN- - D VIN- - RA0/AN0 Off RA0/AN0 Off C1 C1 A VIN+ + (Read as '0') D VIN+ + (Read as '0') RA3/AN3 RA3/AN3 A VIN- - D VIN- - RA1/AN1 Off RA1/AN1 Off C2 C2 A VIN+ + (Read as '0') D VIN+ + (Read as '0') RA2/AN2 RA2/AN2 CM<2:0> = 000 CM<2:0> = 111 Comparators Reset Comparators Off RA0/AN0 A VIN- - C1 C1OUT RA0/AN0 A CIS=0VIN- - A VIN+ + RA3/AN3 A CIS=1 C1 C1OUT RA3/AN3 VIN+ + A VIN- - RA1/AN1 A CIS=0 RA1/AN1 C2 C2OUT VIN- - A VIN+ + RA2/AN2 A CIS=1 C2 C2OUT RA2/AN2 VIN+ + CM<2:0> = 100 From VREF Module Two Independent Comparators Four Inputs Multiplexed to CM<2:0> = 010 Two Comparators A VIN- - A VIN- - RA0/AN0 RA0/AN0 C1 C1OUT C1 C1OUT D VIN++ D VIN+ + RA3/AN3 RA3/AN3 A VIN- - A VIN- - RA1/AN1 RA1/AN1 C2 C2OUT C2 C2OUT A VIN+ + A VIN+ + RA2/AN2 RA2/AN2 RA4 Open Drain CM<2:0> = 011 CM<2:0> = 110 Two Common Reference Comparators Two Common Reference Comparators with Outputs D VIN- - A CIS=0 RA0/AN0 Off RA0/AN0 VIN- - C1 RA3/AN3 D VIN+ + (Read as '0') RA3/AN3 A CVISIN=+1 + C1 C1OUT A VIN- - RA1/AN1 A VIN+ + C2 C2OUT RA1/AN1 A VIN- - C2 C2OUT RA2/AN2 A VIN++ RA2/AN2 CM<2:0> = 101 CM<2:0> = 001 One Independent Comparator Three Inputs Multiplexed to Two Comparators A = Analog Input, Port Reads Zeros Always D = Digital Input CIS = CMCON<3>, Comparator Input Switch DS40182D-page 42  1998-2013 Microchip Technology Inc.

PIC16CE62X The code example in Example8-1 depicts the steps 8.3 Comparator Reference required to configure the comparator module. RA3 and RA4 are configured as digital output. RA0 and RA1 are An external or internal reference signal may be used configured as the V- inputs and RA2 as the V+ input to depending on the comparator operating mode. The both comparators. analog signal that is present at VIN– is compared to the signal at VIN+, and the digital output of the comparator EXAMPLE 8-1: INITIALIZING is adjusted accordingly (Figure8-2). COMPARATOR MODULE FIGURE 8-2: SINGLE COMPARATOR FLAG_REGEQU 0X20 CLRF FLAG_REG ;Init flag register CLRF PORTA ;Init PORTA MOVF CMCON,W ;Move comparator contents to W VIN+ + ANDLW 0xC0 ;Mask comparator bits Output IORWF FLAG_REG,F ;Store bits in flag register VIN– – MOVLW 0x03 ;Init comparator mode MOVWF CMCON ;CM<2:0> = 011 BSF STATUS,RP0 ;Select Bank1 MOVLW 0x07 ;Initialize data direction MOVWF TRISA ;Set RA<2:0> as inputs ;RA<4:3> as outputs ;TRISA<7:5> always read ‘0’ VVININ–– BCF STATUS,RP0 ;Select Bank 0 CALL DELAY 10 ;10s delay VVININ++ MOVF CMCON,F ;Read CMCON to end change condition BCF PIR1,CMIF ;Clear pending interrupts BSF STATUS,RP0 ;Select Bank 1 BSF PIE1,CMIE ;Enable comparator interrupts Output BCF STATUS,RP0 ;Select Bank 0 Output BSF INTCON,PEIE ;Enable peripheral interrupts BSF INTCON,GIE ;Global interrupt enable 8.2 Comparator Operation 8.3.1 EXTERNAL REFERENCE SIGNAL A single comparator is shown in Figure8-2 along with When external voltage references are used, the the relationship between the analog input levels and comparator module can be configured to have the com- the digital output. When the analog input at VIN+ is less parators operate from the same or different reference than the analog input VIN–, the output of the sources. However, threshold detector applications may comparator is a digital low level. When the analog input require the same reference. The reference signal must at VIN+ is greater than the analog input VIN–, the output be between VSS and VDD and can be applied to either of the comparator is a digital high level. The shaded pin of the comparator(s). areas of the output of the comparator in Figure8-2 represent the uncertainty due to input offsets and 8.3.2 INTERNAL REFERENCE SIGNAL response time. The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section 13, Instruction Sets, contains a detailed description of the Voltage Reference Module that provides this signal. The internal reference signal is used when the comparators are in mode CM<2:0>=010 (Figure8-1). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators.  1998-2013 Microchip Technology Inc. DS40182D-page 43

PIC16CE62X 8.4 Comparator Response Time 8.5 Comparator Outputs Response time is the minimum time, after selecting a The comparator outputs are read through the CMCON new reference voltage or input source, before the register. These bits are read only. The comparator comparator output has a valid level. If the internal refer- outputs may also be directly output to the RA3 and RA4 ence is changed, the maximum delay of the internal I/O pins. When the CM<2:0> = 110, multiplexors in the voltage reference must be considered when using the output path of the RA3 and RA4 pins will switch and the comparator outputs, otherwise the maximum delay of output of each pin will be the unsynchronized output of the comparators should be used (Table13-1 ). the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure8-3 shows the comparator output block diagram. The TRISA bits will still function as an output enable/disable for the RA3 and RA4 pins while in this mode. Note 1: When reading the PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. 2: Analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified. FIGURE 8-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + - To RA3 or RA4 Pin Data Q D Bus RD CMCON EN Set CMIF Q D Bit From Other EN Comparator CL RD CMCON NRESET DS40182D-page 44  1998-2013 Microchip Technology Inc.

PIC16CE62X 8.6 Comparator Interrupts wake-up the device from SLEEP mode when enabled. While the comparator is powered-up, higher sleep The comparator interrupt flag is set whenever there is currents than shown in the power down current a change in the output value of either comparator. specification will occur. Each comparator that is Software will need to maintain information about the operational will consume additional current as shown in status of the output bits, as read from CMCON<7:6>, to the comparator specifications. To minimize power determine the actual change that has occurred. The consumption while in SLEEP mode, turn off the CMIF bit, PIR1<6>, is the comparator interrupt flag. comparators, CM<2:0>=111, before entering sleep. If The CMIF bit must be reset by clearing ‘0’. Since it is the device wakes-up from sleep, the contents of the also possible to write a '1' to this register, a simulated CMCON register are not affected. interrupt may be initiated. 8.8 Effects of a RESET The CMIE bit (PIE1<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In A device reset forces the CMCON register to its reset addition, the GIE bit must also be set. If any of these state. This forces the comparator module to be in the bits are clear, the interrupt is not enabled, though the comparator reset mode, CM<2:0>=000. This ensures CMIF bit will still be set if an interrupt condition occurs. that all potential inputs are analog inputs. Device cur- Note: If a change in the CMCON register rent is minimized when analog inputs are present at (C1OUT or C2OUT) should occur when a reset time. The comparators will be powered-down read operation is being executed (start of during the reset interval. the Q2 cycle), then the CMIF (PIR1<6>) 8.9 Analog Input Connection interrupt flag may not get set. Considerations The user, in the interrupt service routine, can clear the interrupt in the following manner: A simplified circuit for an analog input is shown in Figure8-4. Since the analog pins are connected to a a) Any read or write of CMCON. This will end the mismatch condition. digital output, they have reverse biased diodes to VDD and VSS. The analog input therefore, must be between b) Clear flag bit CMIF. VSS and VDD. If the input voltage deviates from this A mismatch condition will continue to set flag bit CMIF. range by more than 0.6V in either direction, one of the Reading CMCON will end the mismatch condition, and diodes is forward biased and a latch-up may occur. A allow flag bit CMIF to be cleared. maximum source impedance of 10k is recommended for the analog sources. Any external 8.7 Comparator Operation During SLEEP component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little When a comparator is active and the device is placed leakage current. in SLEEP mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will FIGURE 8-4: ANALOG INPUT MODEL VDD VT = 0.6V RS < 10K RIC AIN VA C5 PpIFN VT = 0.6V I±L5E0A0K AnGAE VSS Legend CPIN = Input capacitance VT = Threshold voltage ILEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect resistance RS = Source impedance VA = Analog voltage  1998-2013 Microchip Technology Inc. DS40182D-page 45

PIC16CE62X TABLE 8-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR Resets 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — CMIF — — — — — — -0-- ---- -0-- ---- 8Ch PIE1 — CMIE — — — — — — -0-- ---- -0-- ---- 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 Legend: - = Unimplemented, read as "0", x = Unknown, u = unchanged DS40182D-page 46  1998-2013 Microchip Technology Inc.

PIC16CE62X 9.0 VOLTAGE REFERENCE 9.1 Configuring the Voltage Reference MODULE The Voltage Reference can output 16 distinct voltage The Voltage Reference is a 16-tap resistor ladder levels for each range. network that provides a selectable voltage reference. The equations used to calculate the output of the The resistor ladder is segmented to provide two ranges Voltage Reference are as follows: of VREF values and has a power-down function to conserve power when the reference is not being used. if VRR = 1: VREF = (VR<3:0>/24) x VDD The VRCON register controls the operation of the if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD reference as shown in Register9-1. The block diagram The setting time of the Voltage Reference must be is given in Figure9-1. considered when changing the VREF output (Table13-1). Example9-1 shows an example of how to configure the Voltage Reference for an output voltage of 1.25V with VDD = 5.0V. REGISTER 9-1: VRCON REGISTER (ADDRESS 9Fh) R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN VROE VRR — VR3 VR2 VR1 VR0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: VREN: VREF Enable 1 = VREF circuit powered on 0 = VREF circuit powered down, no IDD drain bit 6: VROE: VREF Output Enable 1 = VREF is output on RA2 pin 0 = VREF is disconnected from RA2 pin bit 5: VRR: VREF Range selection 1 = Low Range 0 = High Range bit 4: Unimplemented: Read as '0' bit 3-0: VR<3:0>: VREF value selection 0  VR [3:0]  15 when VRR = 1: VREF = (VR<3:0>/ 24) * VDD when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD FIGURE 9-1: VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages VREN 8R R R R R 8R VRR VR3 VREF 16-1 Analog Mux (From VRCON<3:0>) VR0 Note: R is defined in Table13-2.  1998-2013 Microchip Technology Inc. DS40182D-page 47

PIC16CE62X EXAMPLE 9-1: VOLTAGE REFERENCE 9.4 Effects of a Reset CONFIGURATION A device reset disables the Voltage Reference by clear- MOVLW 0x02 ; 4 Inputs Muxed ing bit VREN (VRCON<7>). This reset also disconnects MOVWF CMCON ; to 2 comps. the reference from the RA2 pin by clearing bit VROE BSF STATUS,RP0 ; go to Bank 1 (VRCON<6>) and selects the high voltage range by MOVLW 0x07 ; RA3-RA0 are clearing bit VRR (VRCON<5>). The VREF value select MOVWF TRISA ; outputs bits, VRCON<3:0>, are also cleared. MOVLW 0xA6 ; enable VREF 9.5 Connection Considerations MOVWF VRCON ; low range ; set VR<3:0>=6 The Voltage Reference Module operates BCF STATUS,RP0 ; go to Bank 0 independently of the comparator module. The output of CALL DELAY10 ; 10s delay the reference generator may be connected to the RA2 pin if the TRISA<2> bit is set and the VROE bit, 9.2 Voltage Reference Accuracy/Error VRCON<6>, is set. Enabling the Voltage Reference output onto the RA2 pin with an input signal present will The full range of VSS to VDD cannot be realized due to increase current consumption. Connecting RA2 as a the construction of the module. The transistors on the digital output with VREF enabled will also increase top and bottom of the resistor ladder network current consumption. (Figure9-1) keep VREF from approaching VSS or VDD. The Voltage Reference is VDD derived and therefore, The RA2 pin can be used as a simple D/A output with the VREF output changes with fluctuations in VDD. The limited drive capability. Due to the limited drive absolute accuracy of the Voltage Reference can be capability, a buffer must be used in conjunction with the found in Table13-2. Voltage Reference output for external connections to VREF. Figure9-2 shows an example buffering 9.3 Operation During Sleep technique. When the device wakes up from sleep through an interrupt or a Watchdog Timer time-out, the contents of the VRCON register are not affected. To minimize current consumption in SLEEP mode, the Voltage Reference should be disabled. FIGURE 9-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE R(1) RA2 VREF Module (cid:129) + (cid:129) VREF Output – Voltage Reference Output Impedance Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>. TABLE 9-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE Value On Value On Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR / BOD Resets 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 Legend: - = Unimplemented, read as "0" DS40182D-page 48  1998-2013 Microchip Technology Inc.

PIC16CE62X 10.0 SPECIAL FEATURES OF THE The PIC16CE62X has a Watchdog Timer which is CPU controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that Special circuits to deal with the needs of real time appli- offer necessary delays on power-up. One is the cations are what sets a microcontroller apart from other Oscillator Start-up Timer (OST), intended to keep the processors. The PIC16CE62X family has a host of chip in reset until the crystal oscillator is stable. The such features intended to maximize system reliability, other is the Power-up Timer (PWRT), which provides a minimize cost through elimination of external compo- fixed delay of 72ms (nominal) on power-up only, and is nents, provide power saving operating modes and offer designed to keep the part in reset while the power code protection. supply stabilizes. There is also circuitry to reset the These are: device if a brown-out occurs, which provides at least a 72ms reset. With these three functions on-chip, most 1. OSC selection applications need no external reset circuitry. 2. Reset The SLEEP mode is designed to offer a very low Power-on Reset (POR) current power-down mode. The user can wake-up from Power-up Timer (PWRT) SLEEP through external reset, Watchdog Timer Oscillator Start-Up Timer (OST) wake-up or through an interrupt. Several oscillator Brown-out Reset (BOD) options are also made available to allow the part to fit 3. Interrupts the application. The RC oscillator option saves system 4. Watchdog Timer (WDT) cost, while the LP crystal option saves power. A set of 5. SLEEP configuration bits are used to select various options. 6. Code protection 7. ID Locations 8. In-circuit serial programming  1998-2013 Microchip Technology Inc. DS40182D-page 49

PIC16CE62X 10.1 Configuration Bits The user will note that address 2007h is beyond the user program memory space. In fact, it belongs The configuration bits can be programmed (read as '0') to the special test/configuration memory space or left unprogrammed (read as '1') to select various (2000h –3FFFh), which can be accessed only during device configurations. These bits are mapped in programming. program memory location 2007h. REGISTER 10-1: CONFIGURATION WORD CP1 CP0(2) CP1 CP0(2) CP1 CP0(2) — BODEN(1) CP1 CP0(2) PWRTE(1) WDTE F0SC1 F0SC0 CONFIG Address bit13 bit0 REGISTER: 2007h bit 13-8, CP1:CP0 Pairs: Code protection bit pairs(2) 5-4: Code protection for 2K program memory 11 = Program memory code protection off 10 = 0400h-07FFh code protected 01 = 0200h-07FFh code protected 00 = 0000h-07FFh code protected Code protection for 1K program memory 11 = Program memory code protection off 10 =Program memory code protection on 01 = 0200h-03FFh code protected 00 = 0000h-03FFh code protected Code protection for 0.5K program memory 11 = Program memory code protection off 10 = Program memory code protection off 01 = Program memory code protection off 00 = 0000h-01FFh code protected bit 7: Unimplemented: Read as '1' bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOD enabled 0 = BOD disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed. DS40182D-page 50  1998-2013 Microchip Technology Inc.

PIC16CE62X 10.2 Oscillator Configurations TABLE 10-1: CERAMIC RESONATORS, PIC16CE62X 10.2.1 OSCILLATOR TYPES Ranges Tested: The PIC16CE62X can be operated in four different Mode Freq OSC1 OSC2 oscillator options. The user can program two configuration bits (FOSC1 and FOSC0) to select one of XT 455 kHz 68 - 100 pF 68 - 100 pF 2.0 MHz 15 - 68 pF 15 - 68 pF these four modes: 4.0 MHz 15 - 68 pF 15 - 68 pF (cid:129) LP Low Power Crystal HS 8.0 MHz 10 - 68 pF 10 - 68 pF (cid:129) XT Crystal/Resonator 16.0 MHz 10 - 22 pF 10 - 22 pF (cid:129) HS High Speed Crystal/Resonator These values are for design guidance only. See notes at bottom of page. (cid:129) RC Resistor/Capacitor 10.2.2 CRYSTAL OSCILLATOR / CERAMIC TABLE 10-2: CAPACITOR SELECTION FOR RESONATORS CRYSTAL OSCILLATOR, PIC16CE62X In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish Osc Type Crystal Cap. Range Cap. Range Freq C1 C2 oscillation (Figure10-1). The PIC16CE62X oscillator design requires the use of a parallel cut crystal. Use of LP 32 kHz 33 pF 33 pF a series cut crystal may give a frequency out of the 200 kHz 15 pF 15 pF crystal manufacturers specifications. When in XT, LP or XT 200 kHz 47-68 pF 47-68 pF HS modes, the device can have an external clock 1 MHz 15 pF 15 pF source to drive the OSC1 pin (Figure10-2). 4 MHz 15 pF 15 pF FIGURE 10-1: CRYSTAL OPERATION HS 4 MHz 15 pF 15 pF (OR CERAMIC RESONATOR) 8 MHz 15-33 pF 15-33 pF (HS, XT OR LP OSC 20 MHz 15-33 pF 15-33 pF CONFIGURATION) These values are for design guidance only. See notes at OSC1 bottom of page. C1 To Internal Logic 1. Recommended values of C1 and C2 are identical to the ranges tested table. XTAL SLEEP RF 2. Higher capacitance increases the stability of oscillator, OSC2 but also increases the start-up time. RS 3. Since each resonator/crystal has its own characteris- C2 see Note PIC16CE62X tics, the user should consult the resonator/crystal manufacturer for appropriate values of external com- See Table10-1 and Table10-2 for recommended values ponents. of C1 and C2. 4. Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level spec- Note: A series resistor may be required for AT ification. strip cut crystals. FIGURE 10-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Clock From OSC1 ext. system PIC16CE62X Open OSC2  1998-2013 Microchip Technology Inc. DS40182D-page 51

PIC16CE62X 10.2.3 EXTERNAL CRYSTAL OSCILLATOR 10.2.4 RC OSCILLATOR CIRCUIT For timing insensitive applications the “RC” device Either a prepackaged oscillator can be used or a simple option offers additional cost savings. The RC oscillator oscillator circuit with TTL gates can be built. Prepack- frequency is a function of the supply voltage, the aged oscillators provide a wide operating range and resistor (Rext) and capacitor (Cext) values, and the better stability. A well-designed crystal oscillator will operating temperature. In addition to this, the oscillator provide good performance with TTL gates. Two types of frequency will vary from unit to unit due to normal crystal oscillator circuits can be used; one with series process parameter variation. Furthermore, the resonance or one with parallel resonance. difference in lead frame capacitance between package types will also affect the oscillation frequency, Figure10-3 shows implementation of a parallel reso- especially for low Cext values. The user also needs to nant oscillator circuit. The circuit is designed to use the take into account variation due to tolerance of external fundamental frequency of the crystal. The 74AS04 R and C components used. Figure10-5 shows how the inverter performs the 180 phase shift that a parallel R/C combination is connected to the PIC16CE62X. For oscillator requires. The 4.7k resistor provides the Rext values below 2.2 k, the oscillator operation may negative feedback for stability. The 10k become unstable, or stop completely. For very high potentiometers bias the 74AS04 in the linear region. Rext values (i.e., 1 M), the oscillator becomes This could be used for external oscillator designs. sensitive to noise, humidity and leakage. Thus, we FIGURE 10-3: EXTERNAL PARALLEL recommend to keep Rext between 3 k and 100 k. RESONANT CRYSTAL Although the oscillator will operate with no external OSCILLATOR CIRCUIT capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or +5V To Other small external capacitance, the oscillation frequency Devices can vary dramatically due to changes in external 10k capacitances, such as PCB trace capacitance or 4.7k 74AS04 PIC16CE62X package lead frame capacitance. 74AS04 CLKIN See Section14.0 for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will 10k affect RC frequency more for large R) and for smaller C XTAL (since variation of input capacitance will affect RC fre- 10k quency more). See Section14.0 for variation of oscillator frequency 20 pF 20 pF due to VDD for given Rext/Cext values, as well as frequency variation due to operating temperature for Figure10-4 shows a series resonant oscillator circuit. given R, C, and VDD values. This circuit is also designed to use the fundamental The oscillator frequency, divided by 4, is available on frequency of the crystal. The inverter performs a 180 the OSC2/CLKOUT pin and can be used for test pur- phase shift in a series resonant oscillator circuit. The poses or to synchronize other logic (Figure3-2 for 330k resistors provide the negative feedback to bias waveform). the inverters in their linear region. FIGURE 10-5: RC OSCILLATOR MODE FIGURE 10-4: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT VDD PIC16CE62X Rext To other OSC1 330 330 Devices Internal Clock 74AS04 74AS04 74AS04 PIC16CE62X Cext CLKIN 0.1 F VDD FOSC/4 OSC2/CLKOUT XTAL DS40182D-page 52  1998-2013 Microchip Technology Inc.

PIC16CE62X 10.3 Reset state” on Power-on reset, MCLR reset, WDT reset and MCLR reset during SLEEP. They are not affected by a The PIC16CE62X differentiates between various kinds WDT wake-up, since this is viewed as the resumption of reset: of normal operation. TO and PD bits are set or cleared a) Power-on reset (POR) differently in different reset situations as indicated in Table10-4. These bits are used in software to deter- b) MCLR reset during normal operation mine the nature of the reset. See Table10-6 for a full c) MCLR reset during SLEEP description of reset states of all registers. d) WDT reset (normal operation) A simplified block diagram of the on-chip reset circuit is e) WDT wake-up (SLEEP) shown in Figure10-6. f) Brown-out Reset (BOD) The MCLR reset path has a noise filter to detect and Some registers are not affected in any reset condition. ignore small pulses. See Table13-5 for pulse width Their status is unknown on POR and unchanged in any specification. other reset. Most other registers are reset to a “reset FIGURE 10-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/ VPP Pin SLEEP WDT WDT Module Time-out Reset VDD rise detect Power-on Reset VDD Brown-out Reset BODEN S OST/PWRT OST Chip_Reset 10-bit Ripple-counter R Q OSC1/ CLKIN Pin PWRT On-chip(1) 10-bit Ripple-counter RC OSC Enable PWRT See Table10-3 for time-out situations. Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.  1998-2013 Microchip Technology Inc. DS40182D-page 53

PIC16CE62X 10.4 Power-on Reset (POR), Power-up The Power-Up Time delay will vary from chip-to-chip Timer (PWRT), Oscillator Start-up and due to VDD, temperature and process variation. Timer (OST) and Brown-out Reset See DC parameters for details. (BOD) 10.4.3 OSCILLATOR START-UP TIMER (OST) 10.4.1 POWER-ON RESET (POR) The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the The on-chip POR circuit holds the chip in reset until PWRT delay is over. This ensures that the crystal VDD has reached a high enough level for proper opera- oscillator or resonator has started and stabilized. tion. To take advantage of the POR, just tie the MCLR pin through a resistor to VDD. This will eliminate exter- The OST time-out is invoked only for XT, LP and HS nal RC components usually needed to create Power-on modes and only on power-on reset or wake-up from Reset. A maximum rise time for VDD is required. See SLEEP. electrical specifications for details. 10.4.4 BROWN-OUT RESET (BOD) The POR circuit does not produce an internal reset when VDD declines. The PIC16CE62X members have on-chip Brown-out When the device starts normal operation (exits the Reset circuitry. A configuration bit, BOREN, can disable reset condition), device operating parameters (voltage, (if clear/programmed) or enable (if set) the Brown-out frequency, temperature, etc.) must be met to ensure Reset circuitry. If VDD falls below 4.0V (refer to BVDD operation. If these conditions are not met, the device parameter D005) for greater than parameter (TBOR) in Table13-5, the brown-out situation will reset the chip. A must be held in reset until the operating conditions are met. reset won’t occur if VDD falls below 4.0V for less than parameter (TBOR). For additional information, refer to Application Note On any reset (Power-on, Brown-out, Watch-dog, etc.) AN607, “Power-up Trouble Shooting”. the chip will remain in reset until VDD rises above BVDD. 10.4.2 POWER-UP TIMER (PWRT) The Power-up Timer will then be invoked and will keep the chip in reset an additional 72ms. The Power-up Timer provides a fixed 72ms (nominal) time-out on power-up only, from POR or Brown-out If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset Reset. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as PWRT is and the Power-up Timer will be re-initialized. Once VDD active. The PWRT delay allows the VDD to rise to an rises above BVDD, the Power-Up Timer will execute a 72ms reset. The Power-up Timer should always be acceptable level. A configuration bit, PWRTE, can enabled when Brown-out Reset is enabled. Figure10-7 disable (if set) or enable (if cleared or programmed) the shows typical Brown-out situations. Power-up Timer. The Power-up Timer should always be enabled when Brown-out Reset is enabled. FIGURE 10-7: BROWN-OUT SITUATIONS VDD BVDD Internal 72 ms Reset VDD BVDD Internal <72 ms 72 ms Reset VDD BVDD Internal 72 ms Reset DS40182D-page 54  1998-2013 Microchip Technology Inc.

PIC16CE62X 10.4.5 TIME-OUT SEQUENCE 10.4.6 POWER CONTROL (PCON)/STATUS REGISTER On power-up, the time-out sequence is as follows: First PWRT time-out is invoked after POR has expired, then The power control/status register, PCON (address OST is activated. The total time-out will vary based on 8Eh) has two bits. oscillator configuration and PWRTE bit status. For Bit0 is BOR (Brown-out). BOR is unknown on example, in RC mode with PWRTE bit erased (PWRT power-on-reset. It must then be set by the user and disabled), there will be no time-out at all. Figure10-8, checked on subsequent resets to see if BOR = 0 Figure10-9 and Figure10-10 depict time-out indicating that a brown-out has occurred. The BOR sequences. status bit is a don’t care and is not necessarily Since the time-outs occur from the POR pulse, if MCLR predictable if the brown-out circuit is disabled (by is kept low long enough, the time-outs will expire. Then setting BODEN bit = 0 in the Configuration word). bringing MCLR high will begin execution immediately Bit1 is POR (Power-on-reset). It is a ‘0’ on (see Figure10-9). This is useful for testing purposes or power-on-reset and unaffected otherwise. The user to synchronize more than one PIC® device operating in must write a ‘1’ to this bit following a power-on-reset. parallel. On a subsequent reset, if POR is ‘0’, it will indicate that Table10-5 shows the reset conditions for some special a power-on-reset must have occurred (VDD may have registers, while Table10-6 shows the reset conditions gone too low). for all the registers. TABLE 10-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Wake-up Oscillator Configuration Brown-out Reset from SLEEP PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC RC 72 ms — 72 ms — TABLE 10-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 X 1 1 Power-on-reset 0 X 0 X Illegal, TO is set on POR 0 X X 0 Illegal, PD is set on POR 1 0 X X Brown-out Reset 1 1 0 u WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR reset during normal operation 1 1 1 0 MCLR reset during SLEEP Legend: x = unknown, u = unchanged  1998-2013 Microchip Technology Inc. DS40182D-page 55

PIC16CE62X TABLE 10-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR reset during normal operation 000h 000u uuuu ---- --uu MCLR reset during SLEEP 000h 0001 0uuu ---- --uu WDT reset 000h 0000 uuuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 000x xuuu ---- --u0 Interrupt Wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set and the PC is loaded with the interrupt vector (0004h) after execution of PC+1. TABLE 10-6: INITIALIZATION CONDITION FOR REGISTERS (cid:129) MCLR Reset during normal operation (cid:129) MCLR Reset during (cid:129) Wake-up from SLEEP SLEEP through interrupt (cid:129) WDT Reset (cid:129) Wake-up from SLEEP Register Address Power-on Reset (cid:129) Brown-out Reset (1) through WDT time-out W - xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h - - - TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h 0000 0000 0000 0000 PC + 1(3) STATUS 03h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu PORTA 05h ---x xxxx ---u uuuu ---u uuuu PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu CMCON 1Fh 00-- 0000 00-- 0000 uu-- uuuu PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh 0000 000x 0000 000u uuuu uqqq(2) PIR1 0Ch -0-- ---- -0-- ---- -q-- ----(2,5) OPTION 81h 1111 1111 1111 1111 uuuu uuuu TRISA 85h ---1 1111 ---1 1111 ---u uuuu TRISB 86h 1111 1111 1111 1111 uuuu uuuu PIE1 8Ch -0-- ---- -0-- ---- -u-- ---- PCON 8Eh ---- --0x ---- --uq(1,6) ---- --uu EEINTF 90h ---- -111 ---- -111 ---- -111 VRCON 9Fh 000- 0000 000- 0000 uuu- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’,q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table10-5 for reset value for specific condition. 5: If wake-up was due to comparator input changing , then bit 6 = 1. All other interrupts generating a wake-up will cause bit 6 = u. 6: If reset was due to brown-out, then PCON bit 0 = 0. All other resets will cause bit 0 = u. DS40182D-page 56  1998-2013 Microchip Technology Inc.

PIC16CE62X FIGURE 10-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 10-10:TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  1998-2013 Microchip Technology Inc. DS40182D-page 57

PIC16CE62X FIGURE 10-11:EXTERNAL POWER-ON FIGURE 10-13:EXTERNAL BROWN-OUT RESET CIRCUIT (FOR SLOW PROTECTION CIRCUIT 2 VDD POWER-UP) VDD VDD VDD VDD R1 Q1 D R MCLR R2 R1 40k PIC16CE62X MCLR PIC16CE62X C Note 1: External power-on reset circuit is required only Note 1: This brown-out circuit is less expensive, if VDD power-up slope is too slow. The diode D albeit less accurate. Transistor Q1 turns off helps discharge the capacitor quickly when when VDD is below a certain level such that: VDD powers down. 2: < 40 k is recommended to make sure that R1 VDD x = 0.7 V voltage drop across R does not violate the R1 + R2 device’s electrical specification. 2: Internal brown-out detection should be dis- 3: R1 = 100 to 1 k will limit any current flowing abled when using this circuit. into MCLR from external capacitor C in the 3: Resistors should be adjusted for the charac- event of MCLR/VPP pin breakdown due to teristics of the transistor. Electrostatic Discharge (ESD) or Electrical Overstress (EOS). FIGURE 10-14:EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3 FIGURE 10-12:EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD VDD VDD MCP809 bypass VDD VSS capacitor 33k VDD RST 10k MCLR MCLR PIC16CE62X 40k PIC16CE62X This brown-out protection circuit employs Microchip Technology’s MCP809 microcontroller supervisor. The MCP8XX and MCP1XX families of supervisors provide push-pull and open collector outputs with both high and Note 1: This circuit will activate reset when VDD low active reset pins. There are 7 different trip point goes below (Vz + 0.7V) where Vz=Zener selections to accommodate 5V and 3V systems. voltage. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit. DS40182D-page 58  1998-2013 Microchip Technology Inc.

PIC16CE62X 10.5 Interrupts the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in soft- The PIC16CE62X has 4 sources of interrupt: ware before re-enabling interrupts to avoid RB0/INT (cid:129) External interrupt RB0/INT recursive interrupts. (cid:129) TMR0 overflow interrupt For external interrupt events, such as the INT pin or (cid:129) PortB change interrupts (pins RB<7:4>) PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency (cid:129) Comparator interrupt depends on when the interrupt event occurs The interrupt control register (INTCON) records (Figure10-16). The latency is the same for one or two individual interrupt requests in flag bits. It also has cycle instructions. Once in the interrupt service routine individual and global interrupt enable bits. the source(s) of the interrupt can be determined by poll- A global interrupt enable bit, GIE (INTCON<7>) ing the interrupt flag bits. The interrupt flag bit(s) must enables (if set) all un-masked interrupts or disables (if be cleared in software before re-enabling interrupts to cleared) all interrupts. Individual interrupts can be avoid multiple interrupt requests. disabled through their corresponding enable bits in Note 1: Individual interrupt flag bits are set, INTCON register. GIE is cleared on reset. regardless of the status of their The “return from interrupt” instruction, RETFIE, exits corresponding mask bit or the GIE bit. interrupt routine, as well as sets the GIE bit, which 2: When an instruction that clears the GIE re-enable RB0/INT interrupts. bit is executed, any interrupts that were pending for execution in the next cycle The INT pin interrupt, the RB port change interrupt and are ignored. The CPU will execute a NOP the TMR0 overflow interrupt flags are contained in the in the cycle immediately following the INTCON register. instruction which clears the GIE bit. The The peripheral interrupt flag is contained in the special interrupts which were ignored are still register PIR1. The corresponding interrupt enable bit is pending to be serviced when the GIE bit is set again. contained in special registers PIE1. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine, the source(s) of FIGURE 10-15:INTERRUPT LOGIC Wake-up T0IF (If in SLEEP mode) T0IE INTF INTE Interrupt RBIF to CPU RBIE CMIF CMIE PEIE GIE  1998-2013 Microchip Technology Inc. DS40182D-page 59

PIC16CE62X 10.5.1 RB0/INT INTERRUPT 10.5.3 PORTB INTERRUPT External interrupt on RB0/INT pin is edge triggered; An input change on PORTB <7:4> sets the RBIF either rising if INTEDG bit (OPTION<6>) is set, or fall- (INTCON<0>) bit. The interrupt can be enabled/dis- ing, if INTEDG bit is clear. When a valid edge appears abled by setting/clearing the RBIE (INTCON<4>) bit. on the RB0/INT pin, the INTF bit (INTCON<1>) is set. For operation of PORTB (Section5.2). This interrupt can be disabled by clearing the INTE Note: If a change on the I/O pin should occur control bit (INTCON<4>). The INTF bit must be cleared when the read operation is being executed in software in the interrupt service routine before (start of the Q2 cycle), then the RBIF inter- re-enabling this interrupt. The RB0/INT interrupt can rupt flag may not get set. wake-up the processor from SLEEP, if the INTE bit was set prior to going into SLEEP. The status of the GIE bit 10.5.4 COMPARATOR INTERRUPT decides whether or not the processor branches to the interrupt vector following wake-up. See Section10.8 for See Section8.6 for complete description of comparator details on SLEEP and Figure10-19 for timing of interrupts. wake-up from SLEEP through RB0/INT interrupt. 10.5.2 TMR0 INTERRUPT An overflow (FFh  00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section7.0. FIGURE 10-16:INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 4 INT pin 1 1 INTF flag 5 Interrupt Latency 2 (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 PC+1 0004h 0005h Instruction fetched Inst (PC) Inst (PC+1) — Inst (0004h) Inst (0005h) Instruction Inst (PC-1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) executed Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles. DS40182D-page 60  1998-2013 Microchip Technology Inc.

PIC16CE62X 10.6 Context Saving During Interrupts 10.7 Watchdog Timer (WDT) During an interrupt, only the return PC value is saved The Watchdog Timer is a free running on-chip RC oscil- on the stack. Typically, users may wish to save key reg- lator which does not require any external components. isters during an interrupt (i.e. W register and STATUS This RC oscillator is separate from the RC oscillator of register). This will have to be implemented in software. the CLKIN pin. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device Example10-1 stores and restores the STATUS and W have been stopped, for example, by execution of a registers. The user register, W_TEMP, must be defined SLEEP instruction. During normal operation, a WDT in both banks and must be defined at the same offset time-out generates a device RESET. If the device is in from the bank base address (i.e., W_TEMP is defined SLEEP mode, a WDT time-out causes the device to at 0x70 in Bank 0 and it must also be defined at 0xF0 wake-up and continue with normal operation. The WDT in Bank 1). The user register, STATUS_TEMP, must be can be permanently disabled by programming the con- defined in Bank 0. The Example10-1: figuration bit WDTE as clear (Section10.1). (cid:129) Stores the W register (cid:129) Stores the STATUS register in Bank 0 10.7.1 WDT PERIOD (cid:129) Executes the ISR code The WDT has a nominal time-out period of 18 ms, (with (cid:129) Restores the STATUS (and bank select bit no prescaler). The time-out periods vary with tempera- register) ture, VDD and process variations from part to part (see (cid:129) Restores the W register DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be EXAMPLE 10-1: SAVING THE STATUS AND assigned to the WDT under software control by writing W REGISTERS IN RAM to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. MOVWF W_TEMP ;copy W to temp register, ;could be in either bank The CLRWDT and SLEEP instructions clear the WDT SWAPF STATUS,W ;swap status to be saved into W and the postscaler, if assigned to the WDT, and prevent BCF STATUS,RP0 ;change to bank 0 regardless it from timing out and generating a device RESET. ;of current bank The TO bit in the STATUS register will be cleared upon MOVWF STATUS_TEMP ;save status to bank 0 ;register a Watchdog Timer time-out. : 10.7.2 WDT PROGRAMMING CONSIDERATIONS : (ISR) : It should also be taken in account that under worst case SWAPF STATUS_TEMP,W ;swap STATUS_TEMP register conditions (VDD = Min., Temperature = Max., max. ;into W, sets bank to original WDT prescaler), it may take several seconds before a ;state WDT time-out occurs. MOVWF STATUS ;move W into STATUS register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W  1998-2013 Microchip Technology Inc. DS40182D-page 61

PIC16CE62X FIGURE 10-17:WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure7-6) 0 M Postscaler Watchdog (cid:129) 1 U Timer X 8 8 - to -1 MUX PS<2:0> PSA WDT Enable Bit (cid:129) To TMR0 (Figure7-6) 0 1 MUX PSA WDT Time-out Note: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. FIGURE 10-18:SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits  BOREN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: _ = Unimplemented location, read as “0”, + = Reserved for future use Note: Shaded cells are not used by the Watchdog Timer. DS40182D-page 62  1998-2013 Microchip Technology Inc.

PIC16CE62X 10.8 Power-Down Mode (SLEEP) The first event will cause a device reset. The two latter events are considered a continuation of program exe- The Power-down mode is entered by executing a cution. The TO and PD bits in the STATUS register can SLEEP instruction. be used to determine the cause of device reset. PD If enabled, the Watchdog Timer will be cleared but bit, which is set on power-up is cleared when SLEEP is keeps running, the PD bit in the STATUS register is invoked. TO bit is cleared if WDT wake-up occurred. cleared, the TO bit is set and the oscillator driver is When the SLEEP instruction is being executed, the turned off. The I/O ports maintain the status they had next instruction (PC + 1) is pre-fetched. For the device before SLEEP was executed (driving high, low, or to wake-up through an interrupt event, the correspond- hi-impedance). ing interrupt enable bit must be set (enabled). Wake-up For lowest current consumption in this mode, all I/O is regardless of the state of the GIE bit. If the GIE bit is pins should be either at VDD or VSS, with no external clear (disabled), the device continues execution at the circuitry drawing current from the I/O pin, and the com- instruction after the SLEEP instruction. If the GIE bit is parators and VREF should be disabled. I/O pins that are set (enabled), the device executes the instruction after hi-impedance inputs should be pulled high or low exter- the SLEEP instruction and then branches to the inter- nally to avoid switching currents caused by floating rupt address (0004h). In cases where the execution of inputs. The T0CKI input should also be at VDD or VSS the instruction following SLEEP is not desirable, the for lowest current consumption. The contribution from user should have an NOP after the SLEEP instruction. on chip pull-ups on PORTB should be considered. Note: If the global interrupts are disabled (GIE is The MCLR pin must be at a logic high level (VIHMC). cleared), but any interrupt source has both its interrupt enable bit and the correspond- Note: It should be noted that a RESET generated ing interrupt flag bits set, the device will by a WDT time-out does not drive MCLR immediately wake-up from sleep. The pin low. sleep instruction is completely executed. 10.8.1 WAKE-UP FROM SLEEP The WDT is cleared when the device wakes-up from sleep, regardless of the source of wake-up. The device can wake-up from SLEEP through one of the following events: 1. External reset input on MCLR pin 2. Watchdog Timer Wake-up (if WDT was enabled) 3. Interrupt from RB0/INT pin, RB Port change, or the Peripheral Interrupt (Comparator). FIGURE 10-19:WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency GIE bit Processor in (INTCON<7>) SLEEP INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h Ifentscthruecdtion Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) Ienxsetcruuctetidon Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale) This delay does not occur for RC osc mode. 3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference.  1998-2013 Microchip Technology Inc. DS40182D-page 63

PIC16CE62X 10.9 Code Protection 10.11 In-Circuit Serial Programming If the code protection bit(s) have not been The PIC16CE62X microcontrollers can be serially programmed, the on-chip program memory can be programmed while in the end application circuit. This is read out for verification purposes. simply done with two lines for clock and data, and three other lines for power, ground, and the programming Note: Microchip does not recommend code voltage. This allows customers to manufacture boards protecting windowed devices. with unprogrammed devices, and then program the microcontroller just before shipping the product. This 10.10 ID Locations also allows the most recent firmware or a custom Four memory locations (2000h-2003h) are designated firmware to be programmed. as ID locations where the user can store checksum or The device is placed into a program/verify mode by other code-identification numbers. These locations are holding the RB6 and RB7 pins low, while raising the not accessible during normal execution but are MCLR (VPP) pin from VIL to VIHH (see programming readable and writable during program/verify. Only the specification). RB6 becomes the programming clock least significant 4 bits of the ID locations are used. and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X/9XX Programming Specifications (Liter- ature #DS30228). A typical in-circuit serial programming connection is shown in Figure10-20. FIGURE 10-20:TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections External Connector PIC16CE62X Signals +5V VDD 0V VSS VPP MCLR/VPP CLK RB6 Data I/O RB7 VDD To Normal Connections DS40182D-page 64  1998-2013 Microchip Technology Inc.

PIC16CE62X 11.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped into three basic categories: Each PIC16CE62X instruction is a 14-bit word divided into an OPCODE which specifies the instruction type (cid:129) Byte-oriented operations and one or more operands which further specify the (cid:129) Bit-oriented operations operation of the instruction. The PIC16CE62X instruc- (cid:129) Literal and control operations tion set summary in Table11-2 lists byte-oriented, All instructions are executed within one single bit-oriented, and literal and control operations. instruction cycle, unless a conditional test is true or the Table11-1 shows the opcode field descriptions. program counter is changed as a result of an For byte-oriented instructions, 'f' represents a file instruction. In this case, the execution takes two register designator and 'd' represents a destination instruction cycles with the second cycle executed as a designator. The file register designator specifies which NOP. One instruction cycle consists of four oscillator file register is to be used by the instruction. periods. Thus, for an oscillator frequency of 4 MHz, the The destination designator specifies where the result of normal instruction execution time is 1s. If a the operation is to be placed. If 'd' is zero, the result is conditional test is true or the program counter is placed in the W register. If 'd' is one, the result is placed changed as a result of an instruction, the instruction in the file register specified in the instruction. execution time is 2 s. For bit-oriented instructions, 'b' represents a bit field Table11-1 lists the instructions recognized by the designator which selects the number of the bit affected MPASM assembler. by the operation, while 'f' represents the number of the Figure11-1 shows the three general formats that the file in which the bit is located. instructions can have. For literal and control operations, 'k' represents an Note: To maintain upward compatibility with eight or eleven bit constant or literal value. future PIC® MCU products, do not use the TABLE 11-1: OPCODE FIELD OPTION and TRIS instructions. DESCRIPTIONS All examples use the following format to represent a hexadecimal number: Field Description 0xhh f Register file address (0x00 to 0x7F) where h signifies a hexadecimal digit. W Working register (accumulator) b Bit address within an 8-bit file register FIGURE 11-1: GENERAL FORMAT FOR k Literal field, constant data or label INSTRUCTIONS x Don't care location (= 0 or 1) Byte-oriented file register operations The assembler will generate code with x = 0. It is the 13 8 7 6 0 recommended form of use for compatibility with all Microchip software tools. OPCODE d f (FILE #) d Destination select; d = 0: store result in W, d = 0 for destination W d = 1: store result in file register f. d = 1 for destination f Default is d = 1 f = 7-bit file register address label Label name TOS Top of Stack Bit-oriented file register operations PC Program Counter 13 10 9 7 6 0 PCLATH Program Counter High Latch OPCODE b (BIT #) f (FILE #) GIE Global Interrupt Enable bit b = 3-bit bit address WDT Watchdog Timer/Counter f = 7-bit file register address TO Time-out bit PD Power-down bit Literal and control operations dest Destination either the W register or the specified register file location General [ ] Options 13 8 7 0 ( ) Contents OPCODE k (literal)  Assigned to k = 8-bit immediate value < > Register bit field  In the set of CALL and GOTO instructions only italics User defined term (font is courier) 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value  1998-2013 Microchip Technology Inc. DS40182D-page 65

PIC16CE62X TABLE 11-2: PIC16CE62X INSTRUCTION SET Mnemonic, Description Cycles 14-Bit Opcode Status Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0000 0011 Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS40182D-page 66  1998-2013 Microchip Technology Inc.

PIC16CE62X 11.1 Instruction Descriptions ADDLW Add Literal and W ANDLW AND Literal with W Syntax: [ label ] ADDLW k Syntax: [ label ] ANDLW k Operands: 0  k  255 Operands: 0  k  255 Operation: (W) + k  (W) Operation: (W) .AND. (k)  (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 111x kkkk kkkk Encoding: 11 1001 kkkk kkkk Description: The contents of the W register are Description: The contents of W register are added to the eight bit literal 'k' and the AND’ed with the eight bit literal 'k'. The result is placed in the W register. result is placed in the W register. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example ADDLW 0x15 Example ANDLW 0x5F Before Instruction Before Instruction W = 0x10 W = 0xA3 After Instruction After Instruction W = 0x25 W = 0x03 ADDWF Add W and f ANDWF AND W with f Syntax: [ label ] ADDWF f,d Syntax: [ label ] ANDWF f,d Operands: 0  f  127 Operands: 0  f  127 d  d  Operation: (W) + (f)  (dest) Operation: (W) .AND. (f)  (dest) Status Affected: C, DC, Z Status Affected: Z Encoding: 00 0111 dfff ffff Encoding: 00 0101 dfff ffff Description: Add the contents of the W register Description: AND the W register with register 'f'. If with register 'f'. If 'd' is 0, the result is 'd' is 0, the result is stored in the W stored in the W register. If 'd' is 1, the register. If 'd' is 1, the result is stored result is stored back in register 'f'. back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example ADDWF FSR, 0 Example ANDWF FSR, 1 Before Instruction Before Instruction W = 0x17 W = 0x17 FSR= 0xC2 FSR= 0xC2 After Instruction After Instruction W = 0xD9 W = 0x17 FSR= 0xC2 FSR= 0x02  1998-2013 Microchip Technology Inc. DS40182D-page 67

PIC16CE62X BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 0  b  7 0  b  7 Operation: 0  (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Encoding: 01 00bb bfff ffff Encoding: 01 10bb bfff ffff Description: Bit 'b' in register 'f' is cleared. Description: If bit 'b' in register 'f' is '0', then the next instruction is skipped. Words: 1 If bit 'b' is '0', then the next instruction Cycles: 1 fetched during the current instruction execution is discarded, and a NOP is Example BCF FLAG_REG, 7 executed instead, making this a Before Instruction two-cycle instruction. FLAG_REG = 0xC7 Words: 1 After Instruction FLAG_REG = 0x47 Cycles: 1(2) Example HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE (cid:129) (cid:129) (cid:129) Before Instruction PC = address HERE After Instruction if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0  f  127 0  b  7 Operation: 1  (f<b>) Status Affected: None Encoding: 01 01bb bfff ffff Description: Bit 'b' in register 'f' is set. Words: 1 Cycles: 1 Example BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A DS40182D-page 68  1998-2013 Microchip Technology Inc.

PIC16CE62X BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRF f Operands: 0  f  127 Operands: 0  f  127 0  b < 7 Operation: 00h  (f) Operation: skip if (f<b>) = 1 1  Z Status Affected: None Status Affected: Z Encoding: 01 11bb bfff ffff Encoding: 00 0001 1fff ffff Description: If bit 'b' in register 'f' is '1' then the next Description: The contents of register 'f' are cleared instruction is skipped. and the Z bit is set. If bit 'b' is '1', then the next instruction Words: 1 fetched during the current instruction execution, is discarded and a NOP is Cycles: 1 executed instead, making this a Example CLRF FLAG_REG two-cycle instruction. Before Instruction Words: 1 FLAG_REG = 0x5A Cycles: 1(2) After Instruction FLAG_REG = 0x00 Example HERE BTFSS FLAG,1 Z = 1 FALSE GOTO PROCESS_CODE TRUE (cid:129) (cid:129) (cid:129) Before Instruction PC = address HERE After Instruction if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE CLRW Clear W CALL Call Subroutine Syntax: [ label ] CLRW Syntax: [ label ] CALL k Operands: None Operands: 0  k  2047 Operation: 00h  (W) 1  Z Operation: (PC)+ 1 TOS, k  PC<10:0>, Status Affected: Z (PCLATH<4:3>)  PC<12:11> Encoding: 00 0001 0000 0011 Status Affected: None Description: W register is cleared. Zero bit (Z) is Encoding: 10 0kkk kkkk kkkk set. Description: Call Subroutine. First, return address Words: 1 (PC+1) is pushed onto the stack. The Cycles: 1 eleven bit immediate address is Example CLRW loaded into PC bits <10:0>. The upper bits of the PC are loaded from Before Instruction PCLATH. CALL is a two-cycle instruc- W = 0x5A tion. After Instruction W = 0x00 Words: 1 Z = 1 Cycles: 2 Example HERE CALL THERE Before Instruction PC = Address HERE After Instruction PC = Address THERE TOS= Address HERE+1  1998-2013 Microchip Technology Inc. DS40182D-page 69

PIC16CE62X CLRWDT Clear Watchdog Timer DECF Decrement f Syntax: [ label ] CLRWDT Syntax: [ label ] DECF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: 00h  WDT 0  WDT prescaler, Operation: (f) - 1  (dest) 1  TO Status Affected: Z 1  PD Encoding: 00 0011 dfff ffff Status Affected: TO, PD Description: Decrement register 'f'. If 'd' is 0, the Encoding: 00 0000 0110 0100 result is stored in the W register. If 'd' Description: CLRWDT instruction resets the is 1, the result is stored back in regis- Watchdog Timer. It also resets the ter 'f'. prescaler of the WDT. Status bits TO Words: 1 and PD are set. Cycles: 1 Words: 1 Example DECF CNT, 1 Cycles: 1 Before Instruction Example CLRWDT CNT = 0x01 Before Instruction Z = 0 WDT counter = ? After Instruction After Instruction CNT = 0x00 WDT counter = 0x00 Z = 1 WDT prescaler= 0 TO = 1 PD = 1 COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF f,d Syntax: [ label ] DECFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f)  (dest) Operation: (f) - 1  (dest); skip if result = 0 Status Affected: Z Status Affected: None Encoding: 00 1001 dfff ffff Encoding: 00 1011 dfff ffff Description: The contents of register 'f' are Description: The contents of register 'f' are complemented. If 'd' is 0, the result is decremented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is placed in the W register. If 'd' is 1, the stored back in register 'f'. result is placed back in register 'f'. Words: 1 If the result is 0, the next instruction, which is already fetched, is discarded. Cycles: 1 A NOP is executed instead making it a Example COMF REG1,0 two-cycle instruction. Before Instruction Words: 1 REG1 = 0x13 Cycles: 1(2) After Instruction REG1 = 0x13 Example HERE DECFSZ CNT, 1 W = 0xEC GOTO LOOP CONTINUE (cid:129) (cid:129) (cid:129) Before Instruction PC = address HERE After Instruction CNT = CNT - 1 if CNT= 0, PC = address CONTINUE if CNT 0, PC = address HERE+1 DS40182D-page 70  1998-2013 Microchip Technology Inc.

PIC16CE62X GOTO Unconditional Branch INCFSZ Increment f, Skip if 0 Syntax: [ label ] GOTO k Syntax: [ label ] INCFSZ f,d Operands: 0  k  2047 Operands: 0  f  127 d  [0,1] Operation: k  PC<10:0> PCLATH<4:3>  PC<12:11> Operation: (f) + 1  (dest), skip if result = 0 Status Affected: None Status Affected: None Encoding: 10 1kkk kkkk kkkk Encoding: 00 1111 dfff ffff Description: GOTO is an unconditional branch. The Description: The contents of register 'f' are eleven bit immediate value is loaded incremented. If 'd' is 0, the result is into PC bits <10:0>. The upper bits of placed in the W register. If 'd' is 1, the PC are loaded from PCLATH<4:3>. result is placed back in register 'f'. GOTO is a two-cycle instruction. If the result is 0, the next instruction, Words: 1 which is already fetched, is discarded. A NOP is executed instead making it a Cycles: 2 two-cycle instruction. Example GOTO THERE Words: 1 After Instruction Cycles: 1(2) PC = Address THERE Example HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE (cid:129) (cid:129) (cid:129) Before Instruction PC = address HERE After Instruction CNT = CNT + 1 if CNT= 0, PC = address CONTINUE if CNT 0, PC = address HERE +1 INCF Increment f Syntax: [ label ] INCF f,d IORLW Inclusive OR Literal with W Operands: 0  f  127 Syntax: [ label ] IORLW k d  [0,1] Operands: 0  k  255 Operation: (f) + 1  (dest) Operation: (W) .OR. k  (W) Status Affected: Z Status Affected: Z Encoding: 00 1010 dfff ffff Encoding: 11 1000 kkkk kkkk Description: The contents of register 'f' are Description: The contents of the W register are incremented. If 'd' is 0, the result is OR’ed with the eight bit literal 'k'. The placed in the W register. If 'd' is 1, the result is placed in the W register. result is placed back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example IORLW 0x35 Example INCF CNT, 1 Before Instruction Before Instruction W = 0x9A CNT = 0xFF After Instruction Z = 0 W = 0xBF After Instruction Z = 1 CNT = 0x00 Z = 1  1998-2013 Microchip Technology Inc. DS40182D-page 71

PIC16CE62X IORWF Inclusive OR W with f MOVF Move f Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (W) .OR. (f)  (dest) Operation: (f)  (dest) Status Affected: Z Status Affected: Z Encoding: 00 0100 dfff ffff Encoding: 00 1000 dfff ffff Description: Inclusive OR the W register with Description: The contents of register f are moved register 'f'. If 'd' is 0, the result is to a destination dependant upon the placed in the W register. If 'd' is 1, the status of d. If d = 0, destination is W result is placed back in register 'f'. register. If d = 1, the destination is file Words: 1 register f itself. d = 1 is useful to test a file register since status flag Z is Cycles: 1 affected. Example IORWF RESULT, 0 Words: 1 Before Instruction Cycles: 1 RESULT = 0x13 Example MOVF FSR, 0 W = 0x91 After Instruction After Instruction RESULT = 0x13 W = value in FSR register W = 0x93 Z = 1 Z = 1 MOVLW Move Literal to W MOVWF Move W to f Syntax: [ label ] MOVLW k Syntax: [ label ] MOVWF f Operands: 0  k  255 Operands: 0  f  127 Operation: k  (W) Operation: (W)  (f) Status Affected: None Status Affected: None Encoding: 11 00xx kkkk kkkk Encoding: 00 0000 1fff ffff Description: The eight bit literal 'k' is loaded into W Description: Move data from W register to register register. The don’t cares will assemble 'f'. as 0’s. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example MOVWF OPTION Example MOVLW 0x5A Before Instruction After Instruction OPTION = 0xFF W = 0x5A W = 0x4F After Instruction OPTION = 0x4F W = 0x4F DS40182D-page 72  1998-2013 Microchip Technology Inc.

PIC16CE62X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] NOP Syntax: [ label ] RETFIE Operands: None Operands: None Operation: No operation Operation: TOS  PC, 1  GIE Status Affected: None Status Affected: None Encoding: 00 0000 0xx0 0000 Encoding: 00 0000 0000 1001 Description: No operation. Description: Return from Interrupt. Stack is POPed Words: 1 and Top of Stack (TOS) is loaded in Cycles: 1 the PC. Interrupts are enabled by Example NOP setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example RETFIE After Interrupt PC = TOS GIE = 1 OPTION Load Option Register RETLW Return with Literal in W Syntax: [ label ] OPTION Syntax: [ label ] RETLW k Operands: None Operands: 0  k  255 Operation: (W)  OPTION Operation: k  (W); Status Affected: None TOS  PC Encoding: 00 0000 0110 0010 Status Affected: None Description: The contents of the W register are Encoding: 11 01xx kkkk kkkk loaded in the OPTION register. This instruction is supported for code Description: The W register is loaded with the eight compatibility with PIC16C5X products. bit literal 'k'. The program counter is Since OPTION is a readable/writable loaded from the top of the stack (the register, the user can directly return address). This is a two-cycle addressit. instruction. Words: 1 Words: 1 Cycles: 1 Cycles: 2 Example Example CALL TABLE ;W contains table ;offset value To maintain upward compatibility (cid:129) ;W now has table with future PIC® MCU products, do value (cid:129) not use this instruction. TABLE (cid:129) ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; (cid:129) (cid:129) (cid:129) RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8  1998-2013 Microchip Technology Inc. DS40182D-page 73

PIC16CE62X RETURN Return from Subroutine RRF Rotate Right f through Carry Syntax: [ label ] RETURN Syntax: [ label ] RRF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: TOS  PC Operation: See description below Status Affected: None Status Affected: C Encoding: 00 0000 0000 1000 Encoding: 00 1100 dfff ffff Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) Description: The contents of register 'f' are rotated is loaded into the program counter. one bit to the right through the Carry This is a two cycle instruction. Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is Words: 1 placed back in register 'f'. Cycles: 2 C Register f Example RETURN After Interrupt Words: 1 PC = TOS Cycles: 1 Example RRF REG1,0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 0111 0011 C = 0 RLF Rotate Left f through Carry SLEEP Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP Operands: 0  f  127 Operands: None d  [0,1] Operation: 00h  WDT, Operation: See description below 0  WDT prescaler, Status Affected: C 1  TO, Encoding: 00 1101 dfff ffff 0  PD Description: The contents of register 'f' are rotated Status Affected: TO, PD one bit to the left through the Carry Encoding: 00 0000 0110 0011 Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is Description: The power-down status bit, PD is stored back in register 'f'. cleared. Time-out status bit, TO is C Register f set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP Words: 1 mode with the oscillator stopped. Cycles: 1 See Section10.8 for more details. Example RLF REG1,0 Words: 1 Before Instruction Cycles: 1 REG1 = 1110 0110 Example: SLEEP C = 0 After Instruction REG1 = 1110 0110 W = 1100 1100 C = 1 DS40182D-page 74  1998-2013 Microchip Technology Inc.

PIC16CE62X SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF f,d Operands: 0 k 255 Operands: 0 f 127 d  [0,1] Operation: k - (W) W) Operation: (f) - (W) dest) Status C, DC, Z Affected: Status C, DC, Z Affected: Encoding: 11 110x kkkk kkkk Encoding: 00 0010 dfff ffff Description: The W register is subtracted (2’s com- plement method) from the eight bit literal Description: Subtract (2’s complement method) 'k'. The result is placed in the W register. Wregister from register 'f'. If 'd' is 0, the Words: 1 result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. Cycles: 1 Words: 1 Example 1: SUBLW 0x02 Cycles: 1 Before Instruction Example 1: SUBWF REG1,1 W = 1 Before Instruction C = ? After Instruction REG1 = 3 W = 2 W = 1 C = ? C = 1; result is positive After Instruction Example 2: Before Instruction REG1 = 1 W = 2 W = 2 C = ? C = 1; result is positive After Instruction Example 2: Before Instruction W = 0 REG1 = 2 C = 1; result is zero W = 2 Example 3: Before Instruction C = ? W = 3 After Instruction C = ? REG1 = 0 After Instruction W = 2 C = 1; result is zero W = 0xFF C = 0; result is nega- Example 3: Before Instruction tive REG1 = 1 W = 2 C = ? After Instruction REG1 = 0xFF W = 2 C = 0; result is negative  1998-2013 Microchip Technology Inc. DS40182D-page 75

PIC16CE62X SWAPF Swap Nibbles in f XORLW Exclusive OR Literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k Operands: 0  f  127 Operands: 0 k 255 d  [0,1] Operation: (W) .XOR. k W) Operation: (f<3:0>)  (dest<7:4>), Status Affected: Z (f<7:4>)  (dest<3:0>) Encoding: 11 1010 kkkk kkkk Status Affected: None Description: The contents of the W register are Encoding: 00 1110 dfff ffff XOR’ed with the eight bit literal 'k'. Description: The upper and lower nibbles of The result is placed in the register 'f' are exchanged. If 'd' is 0, Wregister. the result is placed in W register. If 'd' Words: 1 is 1, the result is placed in register 'f'. Cycles: 1 Words: 1 Example: XORLW 0xAF Cycles: 1 Before Instruction Example SWAPF REG, 0 W = 0xB5 Before Instruction After Instruction REG1 = 0xA5 W = 0x1A After Instruction REG1 = 0xA5 W = 0x5A TRIS Load TRIS Register XORWF Exclusive OR W with f Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d Operands: 5  f  7 Operands: 0  f  127 Operation: (W)  TRIS register f; d  [0,1] Status Affected: None Operation: (W) .XOR. (f) dest) Encoding: 00 0000 0110 0fff Status Affected: Z Description: The instruction is supported for code Encoding: 00 0110 dfff ffff compatibility with the PIC16C5X Description: Exclusive OR the contents of the products. Since TRIS registers are Wregister with register 'f'. If 'd' is 0, readable and writable, the user can the result is stored in the W register. If directly address them. 'd' is 1, the result is stored back in reg- Words: 1 ister 'f'. Cycles: 1 Words: 1 Example Cycles: 1 To maintain upward compatibility Example XORWF REG 1 with future PIC® MCU products, do not use this instruction. Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 DS40182D-page 76  1998-2013 Microchip Technology Inc.

PIC16CE62X 12.0 DEVELOPMENT SUPPORT MPLAB allows you to: The PIC® microcontrollers are supported with a full (cid:129) Edit your source files (either assembly or ‘C’) range of hardware and software development tools: (cid:129) One touch assemble (or compile) and download to PIC MCU tools (automatically updates all proj- (cid:129) Integrated Development Environment ect information) - MPLAB® IDE Software (cid:129) Debug using: (cid:129) Assemblers/Compilers/Linkers - source files - MPASM Assembler - absolute listing file - MPLAB-C17 and MPLAB-C18 C Compilers - object code - MPLINK/MPLIB Linker/Librarian The ability to use MPLAB with Microchip’s simulator, (cid:129) Simulators MPLAB-SIM, allows a consistent platform and the abil- - MPLAB-SIM Software Simulator ity to easily switch from the cost-effective simulator to (cid:129) Emulators the full featured emulator with minimal retraining. - MPLAB-ICEReal-Time In-Circuit Emulator - PICMASTER®/PICMASTER-CE In-Circuit 12.2 MPASM Assembler Emulator MPASM is a full featured universal macro assembler for - ICEPIC™ all PIC MCUs. It can produce absolute code directly in (cid:129) In-Circuit Debugger the form of HEX files for device programmers, or it can - MPLAB-ICD for PIC16F877 generate relocatable objects for MPLINK. (cid:129) Device Programmers MPASM has a command line interface and a Windows - PRO MATE II Universal Programmer shell and can be used as a standalone application on a - PICSTART Plus Entry-Level Prototype Windows 3.x or greater system. MPASM generates relocatable object files, Intel standard HEX files, MAP Programmer files to detail memory usage and symbol reference, an (cid:129) Low-Cost Demonstration Boards absolute LST file which contains source lines and gen- - SIMICE erated machine code, and a COD file for MPLAB - PICDEM-1 debugging. - PICDEM-2 MPASM features include: - PICDEM-3 (cid:129) MPASM and MPLINK are integrated into MPLAB - PICDEM-17 projects. - SEEVAL (cid:129) MPASM allows user defined macros to be created - KEELOQ for streamlined assembly. (cid:129) MPASM allows conditional assembly for multi pur- 12.1 MPLAB Integrated Development pose source files. Environment Software (cid:129) MPASM directives allow complete control over the The MPLAB IDE software brings an ease of software assembly process. development previously unseen in the 8-bit microcon- troller market. MPLAB is a Windows-based applica- 12.3 MPLAB-C17 and MPLAB-C18 C Compilers tion which contains: (cid:129) Multiple functionality The MPLAB-C17 and MPLAB-C18 Code Development - editor Systems are complete ANSI ‘C’ compilers and inte- - simulator grated development environments for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrol- - programmer (sold separately) lers, respectively. These compilers provide powerful - emulator (sold separately) integration capabilities and ease of use not found with (cid:129) A full featured editor other compilers. (cid:129) A project manager For easier source level debugging, the compilers pro- (cid:129) Customizable tool bar and key mapping vide symbol information that is compatible with the (cid:129) A status bar MPLAB IDE memory display. (cid:129) On-line help 12.4 MPLINK/MPLIB Linker/Librarian MPLINK is a relocatable linker for MPASM and MPLAB-C17 and MPLAB-C18. It can link relocatable objects from assembly or C source files along with pre- compiled libraries using directives from a linker script.  1998-2013 Microchip Technology Inc. DS40182D-page 7-77

PIC16CE62X MPLIB is a librarian for pre-compiled code to be used opment tools. The PC platform and Microsoft® Windows with MPLINK. When a routine from a library is called 3.x/95/98 environment were chosen to best make these from another source file, only the modules that contains features available to you, the end user. that routine will be linked in with the application. This MPLAB-ICE 2000 is a full-featured emulator system allows large libraries to be used efficiently in many dif- with enhanced trace, trigger, and data monitoring fea- ferent applications. MPLIB manages the creation and tures. Both systems use the same processor modules modification of library files. and will operate across the full operating speed range MPLINK features include: of the PIC MCU. (cid:129) MPLINK works with MPASM and MPLAB-C17 12.7 PICMASTER/PICMASTER CE and MPLAB-C18. (cid:129) MPLINK allows all memory areas to be defined as The PICMASTER system from Microchip Technology is sections to provide link-time flexibility. a full-featured, professional quality emulator system. This flexible in-circuit emulator provides a high-quality, MPLIB features include: universal platform for emulating Microchip 8-bit PIC (cid:129) MPLIB makes linking easier because single librar- microcontrollers (MCUs). PICMASTER systems are ies can be included instead of many smaller files. sold worldwide, with a CE compliant model available for (cid:129) MPLIB helps keep code maintainable by grouping European Union (EU) countries. related modules together. 12.8 ICEPIC (cid:129) MPLIB commands allow libraries to be created and modules to be added, listed, replaced, ICEPIC is a low-cost in-circuit emulation solution for the deleted, or extracted. Microchip Technology PIC16C5X, PIC16C6X, 12.5 MPLAB-SIM Software Simulator PIC16C7X, and PIC16CXXX families of 8-bit one-time- programmable (OTP) microcontrollers. The modular The MPLAB-SIM Software Simulator allows code system can support different subsets of PIC16C5X or development in a PC host environment by simulating PIC16CXXX products through the use of the PIC series microcontrollers on an instruction level. interchangeable personality modules or daughter On any given instruction, the data areas can be exam- boards. The emulator is capable of emulating without ined or modified and stimuli can be applied from a file target application circuitry being present. or user-defined key press to any of the pins. The exe- 12.9 MPLAB-ICD In-Circuit Debugger cution can be performed in single step, execute until break, or trace mode. Microchip's In-Circuit Debugger, MPLAB-ICD, is a pow- MPLAB-SIM fully supports symbolic debugging using erful, low-cost run-time development tool. This tool is MPLAB-C17 and MPLAB-C18 and MPASM. The Soft- based on the flash PIC16F877 and can be used to ware Simulator offers the flexibility to develop and develop for this and other PIC microcontrollers from the debug code outside of the laboratory environment mak- PIC16CXXX family. MPLAB-ICD utilizes the In-Circuit ing it an excellent multi-project software development Debugging capability built into the PIC16F87X. This tool. feature, along with Microchip's In-Circuit Serial Pro- gramming protocol, offers cost-effective in-circuit flash 12.6 MPLAB-ICE High Performance programming and debugging from the graphical user Universal In-Circuit Emulator with interface of the MPLAB Integrated Development Envi- MPLAB IDE ronment. This enables a designer to develop and debug source code by watching variables, single-step- The MPLAB-ICE Universal In-Circuit Emulator is ping and setting break points. Running at full speed intended to provide the product development engineer enables testing hardware in real-time. The MPLAB-ICD with a complete microcontroller design tool set for PIC is also a programmer for the flash PIC16F87X family. microcontrollers (MCUs). Software control of MPLAB- ICE is provided by the MPLAB Integrated Development 12.10 PRO MATE II Universal Programmer Environment (IDE), which allows editing, “make” and download, and source debugging from a single envi- The PRO MATE II Universal Programmer is a full-fea- ronment. tured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE Interchangeable processor modules allow the system compliant. to be easily reconfigured for emulation of different pro- cessors. The universal architecture of the MPLAB-ICE The PRO MATE II has programmable VDD and VPP allows expansion to support new PIC microcontrollers. supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has The MPLAB-ICE Emulator System has been designed an LCD display for instructions and error messages, as a real-time emulation system with advanced fea- keys to enter commands and a modular detachable tures that are generally found on more expensive devel- socket assembly to support various package types. In DS40182D-page 7-78  1998-2013 Microchip Technology Inc.

PIC16CE62X stand-alone mode the PRO MATE II can read, verify or 12.14 PICDEM-2 Low-Cost PIC16CXX program PIC devices. It can also set code-protect bits Demonstration Board in this mode. The PICDEM-2 is a simple demonstration board that 12.11 PICSTART Plus Entry Level supports the PIC16C62, PIC16C64, PIC16C65, Development System PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to The PICSTART programmer is an easy-to-use, low- run the basic demonstration programs. The user cost prototype programmer. It connects to the PC via can program the sample microcontrollers provided one of the COM (RS-232) ports. MPLAB Integrated with the PICDEM-2 board, on a PRO MATE II pro- Development Environment software makes using the grammer or PICSTART-Plus, and easily test firmware. programmer simple and efficient. The MPLAB-ICE emulator may also be used with the PICSTART Plus supports all PIC devices with up to 40 PICDEM-2 board to test firmware. Additional prototype pins. Larger pin count devices such as the PIC16C92X, area has been provided to the user for adding addi- and PIC17C76X may be supported with an adapter tional hardware and connecting it to the microcontroller socket. PICSTART Plus is CE compliant. socket(s). Some of the features include a RS-232 inter- face, push-button switches, a potentiometer for simu- 12.12 SIMICE Entry-Level lated analog input, a Serial EEPROM to demonstrate Hardware Simulator usage of the I2C bus and separate headers for connec- tion to an LCD module and a keypad. SIMICE is an entry-level hardware development sys- tem designed to operate in a PC-based environment 12.15 PICDEM-3 Low-Cost PIC16CXXX with Microchip’s simulator MPLAB-SIM. Both SIMICE Demonstration Board and MPLAB-SIM run under Microchip Technology’s MPLAB Integrated Development Environment (IDE) The PICDEM-3 is a simple demonstration board that software. Specifically, SIMICE provides hardware sim- supports the PIC16C923 and PIC16C924 in the PLCC ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and package. It will also support future 44-pin PLCC PIC16C5X families of PIC 8-bit microcontrollers. SIM- microcontrollers with a LCD Module. All the neces- ICE works in conjunction with MPLAB-SIM to provide sary hardware and software is included to run the non-real-time I/O port emulation. SIMICE enables a basic demonstration programs. The user can pro- developer to run simulator code for driving the target gram the sample microcontrollers provided with system. In addition, the target system can provide input the PICDEM-3 board, on a PRO MATE II program- to the simulator code. This capability allows for simple mer or PICSTART Plus with an adapter socket, and and interactive debugging without having to manually easily test firmware. The MPLAB-ICE emulator may generate MPLAB-SIM stimulus files. SIMICE is a valu- also be used with the PICDEM-3 board to test firm- able debugging tool for entry-level system develop- ware. Additional prototype area has been provided to ment. the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include 12.13 PICDEM-1 Low-Cost PIC MCU an RS-232 interface, push-button switches, a potenti- Demonstration Board ometer for simulated analog input, a thermistor and separate headers for connection to an external LCD The PICDEM-1 is a simple board which demonstrates module and a keypad. Also provided on the PICDEM-3 the capabilities of several of Microchip’s microcontrol- board is an LCD panel, with 4 commons and 12 seg- lers. The microcontrollers supported are: PIC16C5X ments, that is capable of displaying time, temperature (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, and day of the week. The PICDEM-3 provides an addi- PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and tional RS-232 interface and Windows 3.1 software for PIC17C44. All necessary hardware and software is showing the demultiplexed LCD signals on a PC. A sim- included to run basic demo programs. The users can ple serial interface allows the user to construct a hard- program the sample microcontrollers provided with ware demultiplexer for the LCD signals. the PICDEM-1 board, on a PROMATE II or PICSTART-Plus programmer, and easily test firm- 12.16 PICDEM-17 ware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the The PICDEM-17 is an evaluation board that demon- firmware to the emulator for testing. Additional proto- strates the capabilities of several Microchip microcon- type area is available for the user to build some addi- trollers, including PIC17C752, PIC17C756, tional hardware and connect it to the microcontroller PIC17C762, and PIC17C766. All necessary hardware socket(s). Some of the features include an RS-232 is included to run basic demo programs, which are sup- interface, a potentiometer for simulated analog input, plied on a 3.5-inch disk. A programmed sample is push-button switches and eight LEDs connected to included, and the user may erase it and program it with PORTB. the other sample programs using the PRO MATE II or PICSTART Plus device programmers and easily debug  1998-2013 Microchip Technology Inc. DS40182D-page 7-79

PIC16CE62X and test the sample code. In addition, PICDEM-17 sup- ports down-loading of programs to and executing out of external FLASH memory on board. The PICDEM-17 is also usable with the MPLAB-ICE or PICMASTER emu- lator, and all of the sample programs can be run and modified using either emulator. Additionally, a gener- ous prototype area is available for user hardware. 12.17 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in trade- off analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system. 12.18 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS40182D-page 7-80  1998-2013 Microchip Technology Inc.

PIC16CE62X TABLE 12-1: DEVELOPMENT TOOLS FROM MICROCHIP 0152PCM  7 7 6, 7 XXXFRCM     4, 7 3, 7 XXXSCH     72, 5, 6 XXC39 4, //XXXXCC4522   63, 6 2, 6 C 2XXC81CIP        6 1 C PI h XX7C71CIP         wit 1) 0 0 4 6 X4C71CIP         1 V D er ( g XX9C61CIP         ug b e D uit XX8F61CIP       Circ n- D I X8C61CIP         ®-IC B A L XX7C61CIP        MP e h e t X7C61CIP      *   †† o us w t o h X26F61CIP   ** ** ** on n o ati m XXXC61CIP         or nf or i X6C61CIP      *   † om f c p. hi c X5C61CIP          cro mi ww.e. X0X0X0C4211CCIPIP®MPLABIntegratedDevelopment Environment®MPLAB C17 Compiler ®MPLAB C18 Compiler MPASM/MPLINK®MPLAB-ICE PICMASTER/PICMASTER-CE ICEPICLow-CostIn-Circuit Emulator ®MPLAB-ICD In-Circuit Debugger PICSTARTPlus Low-Cost Universal Dev. Kit PRO MATE II Universal Programmer SIMICE PICDEM-1 PICDEM-2 PICDEM-3 PICDEM-14A PICDEM-17 ® KLEvaluation KitEEOQ KL Transponder KitEEOQ microID™ Programmer’s Kit 125 kHz microID Developer’s Kit 125 kHz Anticollision microID Developer’s Kit 13.56 MHz Anticollision microID Developer’s Kit MCP2510 CAN Developer’s Kit Contact the Microchip Technology Inc. web site at wContact Microchip Technology Inc. for availability datDevelopment tool is available on select devices. slooT erawtfoS srotalumE reggubeD sremmargorP stiK lavE dna sdraoB omeD ***†  1998-2013 Microchip Technology Inc. DS40182D-page 7-81

PIC16CE62X NOTES: DS40182D-page 7-82  1998-2013 Microchip Technology Inc.

PIC16CE62X 13.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings † Ambient Temperature under bias..............................................................................................................-40 to +125C Storage Temperature................................................................................................................................-65 to +150C Voltage on any pin with respect to VSS (except VDD and MCLR)........................................................-0.6V to VDD +0.6V Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.0V Voltage on RA4 with respect to VSS...........................................................................................................................8.5V Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V Voltage on RA4 with respect to VSS...........................................................................................................................8.5V Total power Dissipation (Note 1)...............................................................................................................................1.0W Maximum Current out of VSS pin...........................................................................................................................300 mA Maximum Current into VDD pin.............................................................................................................................250 mA Input Clamp Current, IIK (VI <0 or VI> VDD)20 mA Output Clamp Current, IOK (VO <0 or VO>VDD)20 mA Maximum Output Current sunk by any I/O pin........................................................................................................25 mA Maximum Output Current sourced by any I/O pin...................................................................................................25 mA Maximum Current sunk byPORTA and PORTB...................................................................................................200 mA Maximum Current sourced by PORTA and PORTB..............................................................................................200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100¾ should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  1998-2013 Microchip Technology Inc. DS40182D-page 83

PIC16CE62X FIGURE 13-1: PIC16CE62X VOLTAGE-FREQUENCY GRAPH, 0C  TA  +70C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. FIGURE 13-2: PIC16CE62X VOLTAGE-FREQUENCY GRAPH, -40C  TA  0C, +70C  TA  +125C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. DS40182D-page 84  1998-2013 Microchip Technology Inc.

PIC16CE62X FIGURE 13-3: PIC16LCE62X VOLTAGE-FREQUENCY GRAPH, -40C  TA  +125C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.  1998-2013 Microchip Technology Inc. DS40182D-page 85

PIC16CE62X 13.1 DC CHARACTERISTICS: PIC16CE62X-04 (Commercial, Industrial, Extended) PIC16CE62X-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature –40C  TA  +85C for industrial and DC CHARACTERISTICS 0C  TA  +70C for commercial and –40C  TA  +125C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. D001 VDD Supply Voltage 3.0 – 5.5 V See Figure13-1 through Figure13-3 D002 VDR RAM Data Retention – 1.5* – V Device in SLEEP mode Voltage (Note 1) D003 VPOR VDD start voltage to – VSS – V See section on power-on reset for details ensure Power-on Reset D004 SVDD VDD rise rate to ensure 0.05* – – V/ms See section on power-on reset for details Power-on Reset D005 VBOR Brown-out Detect Voltage 3.7 4.0 4.35 V BOREN configuration bit is cleared D010 IDD Supply Current (Note 2, 4) – 1.2 2.0 mA FOSC = 4 MHz, VDD = 5.5V, WDT disabled, XT osc mode, (Note 4)* – 0.4 1.2 mA FOSC = 4 MHz, VDD = 3.0V, WDT disabled, XT osc mode, (Note 4) – 1.0 2.0 mA FOSC = 10 MHz, VDD = 3.0V, WDT disabled, HS osc mode, (Note 6) – 4.0 6.0 mA FOSC = 20 MHz, VDD = 4.5V, WDT disabled, HS osc mode – 4.0 7.0 mA FOSC = 20 MHz, VDD = 5.5V, WDT disabled*, HS osc mode – 35 70 A FOSC = 32 kHz, VDD = 3.0V, WDT disabled, LP osc mode D020 IPD Power Down Current (Note 3) – – 2.2 A VDD = 3.0V – – 5.0 A VDD = 4.5V* – – 9.0 A VDD = 5.5V – – 15 A VDD = 5.5V Extended D022 IWDT WDT Current (Note 5) – 6.0 10 A VDD = 4.0V 12 A (125C) D022A IBOR Brown-out Reset Current (Note 5) – 75 125 A BOD enabled, VDD = 5.0V D023 ICOMP Comparator Current for each – 30 60 A VDD = 4.0V Comparator (Note 5) D023A IVREF VREF Current (Note 5) – 80 135 A VDD = 4.0V IEE Write Operating Current – 3 mA VCC = 5.5V, SCL = 400 kHz IEE Read Operating Current – 1 mA IEE Standby Current – 30 A VCC = 3.0V, EE VDD = VCC IEE Standby Current – 100 A VCC = 3.0V, EE VDD = VCC 1A FOSC LP Oscillator Operating Frequency 0 – 200 kHz All temperatures RC Oscillator Operating Frequency 0 – 4 MHz All temperatures XT Oscillator Operating Frequency 0 – 4 MHz All temperatures HS Oscillator Operating Frequency 0 – 20 MHz All temperatures * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con- sumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the for- mula Ir = VDD/2Rext (mA) with Rext in k. 5: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: Commercial temperature range only. DS40182D-page 86  1998-2013 Microchip Technology Inc.

PIC16CE62X 13.2 DC CHARACTERISTICS: PIC16LCE62X-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature –40C  TA  +85C for industrial and DC CHARACTERISTICS 0C  TA  +70C for commercial and –40C  TA  +125C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. D001 VDD Supply Voltage 2.5 – 5.5 V See Figure13-1 through Figure13-3 D002 VDR RAM Data Retention – 1.5* – V Device in SLEEP mode Voltage (Note 1) D003 VPOR VDD start voltage to – VSS – V See section on power-on reset for details ensure Power-on Reset D004 SVDD VDD rise rate to ensure .05* – – V/ms See section on power-on reset for details Power-on Reset D005 VBOR Brown-out Detect Voltage 3.7 4.0 4.35 V BOREN configuration bit is cleared D010 IDD Supply Current (Note 2) – 1.2 2.0 mA FOSC = 4 MHz, VDD = 5.5V, WDT disabled, XT osc mode, (Note 4)* – – 1.1 mA FOSC = 4 MHz, VDD = 2.5V, WDT disabled, XT osc mode, (Note 4) – 35 70 A FOSC = 32 kHz, VDD = 2.5V, WDT disabled, LP osc mode D020 IPD Power Down Current (Note 3) – – 2.0 A VDD = 2.5V – – 2.2 A VDD = 3.0V* – – 9.0 A VDD = 5.5V – – 15 A VDD = 5.5V Extended D022 IWDT WDT Current (Note 5) – 6.0 10 A VDD=4.0V 12 A (125C) D022A IBOR Brown-out Reset Current – 75 125 A BOD enabled, VDD = 5.0V (Note 5) D023 ICOMP Comparator Current for each – 30 60 A VDD = 4.0V Comparator (Note 5) D023A IVREF VREF Current (Note 5) – 80 135 A VDD = 4.0V IEE Write Operating Current – 3 mA VCC = 5.5V, SCL = 400 kHz IEE Read Operating Current – 1 mA IEE Standby Current – 30 A VCC = 3.0V, EE VDD = VCC IEE Standby Current – 100 A VCC = 3.0V, EE VDD = VCC 1A FOSC LP Oscillator Operating Frequency 0 — 200 kHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 20 MHz All temperatures * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con- sumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the for- mula Ir = VDD/2Rext (mA) with Rext in k. 5: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: Commercial temperature range only.  1998-2013 Microchip Technology Inc. DS40182D-page 87

PIC16CE62X 13.3 DC CHARACTERISTICS: PIC16CE62X-04 (Commercial, Industrial, Extended) PIC16CE62X-20 (Commercial, Industrial, Extended) PIC16LCE62X (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature –40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial and –40°C  TA  +125°C for extended Operating voltage VDD range as described in DC spec Table13-1 Parm Sym Characteristic Min Typ† Max Unit Conditions No. VIL Input Low Voltage I/O ports D030 with TTL buffer VSS – 0.8V V VDD = 4.5V to 5.5V, Otherwise 0.15VDD D031 with Schmitt Trigger input VSS 0.2VDD V D032 MCLR, RA4/T0CKI,OSC1 (in RC VSS – 0.2VDD V Note1 mode) D033 OSC1 (in XT and HS) VSS – 0.3VDD V OSC1 (in LP) VSS – 0.6VDD - 1.0 V VIH Input High Voltage I/O ports D040 with TTL buffer 2.0V – VDD V VDD = 4.5V to 5.5V, Otherwise .25VDD + 0.8V VDD D041 with Schmitt Trigger input 0.8VDD VDD D042 MCLR RA4/T0CKI 0.8VDD – VDD V D043 OSC1 (XT, HS and LP) 0.7VDD – VDD V D043A OSC1 (in RC mode) 0.9VDD Note1 D070 IPURB PORTB weak pull-up current 50 200 400 A VDD = 5.0V, VPIN = VSS Input Leakage Current IIL (Notes 2, 3) I/O ports (Except PORTA) 1.0 A VSS  VPIN  VDD, pin at hi-impedance D060 PORTA – – 0.5 A Vss VPIN VDD, pin at hi-impedance D061 RA4/T0CKI – – 1.0 A Vss VPIN VDD D063 OSC1, MCLR – – 5.0 A Vss VPIN VDD, XT, HS and LP osc configuration VOL Output Low Voltage D080 I/O ports – – 0.6 V IOL=8.5 mA, VDD=4.5V, -40 to +85C – – 0.6 V IOL=7.0 mA, VDD=4.5V, +125C D083 OSC2/CLKOUT (RC only) – – 0.6 V IOL=1.6 mA, VDD=4.5V, -40 to +85C – – 0.6 V IOL=1.2 mA, VDD=4.5V, +125C VOH Output High Voltage (Note 3) D090 I/O ports (Except RA4) VDD-0.7 – – V IOH=-3.0 mA, VDD=4.5V, -40 to +85C VDD-0.7 – – V IOH=-2.5 mA, VDD=4.5V, +125C D092 OSC2/CLKOUT (RC only) VDD-0.7 – – V IOH=-1.3 mA, VDD=4.5V, -40 to +85C VDD-0.7 – – V IOH=-1.0 mA, VDD=4.5V, +125C *D150 VOD Open-Drain High Voltage 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100 COSC OSC2 pin 15 pF In XT, HS and LP modes when external 2 clock used to drive OSC1. D101 Cio All I/O pins/OSC2 (in RC mode) 50 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16CE62X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. DS40182D-page 88  1998-2013 Microchip Technology Inc.

PIC16CE62X TABLE 13-1: COMPARATOR SPECIFICATIONS Operating Conditions: VDD range as described in Table 12-1, -40C<TA<+125C. . Param No. Characteristics Sym Min Typ Max Units Comments D300 Input offset voltage VIOFF  5.0  10 mV D301 Input common mode voltage VICM 0 VDD - 1.5 V D302 CMRR CMRR +55* db 300 Response Time(1) TRESP 150* 400* ns PIC16CE62X 301 Comparator Mode Change to TMC2OV 10* s Output Valid * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD. TABLE 13-2: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: VDD range as described in Table 12-1, -40C<TA<+125C. Param Characteristics Sym Min Typ Max Units Comments No. D310 Resolution VRES VDD/24 VDD/32 LSB D311 Absolute Accuracy VRAA +1/4 LSB Low Range (VRR=1) +1/2 LSB High Range (VRR=0) D312 Unit Resistor Value (R) VRUR 2K*  Figure9-1 310 Settling Time(1) TSET 10* s * These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.  1998-2013 Microchip Technology Inc. DS40182D-page 89

PIC16CE62X 13.4 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp ck CLKOUT osc OSC1 io I/O port t0 T0CKI mc MCLR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-Impedance FIGURE 13-4: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464 CL = 50 pF for all pins except OSC2 15 pF for OSC2 output DS40182D-page 90  1998-2013 Microchip Technology Inc.

PIC16CE62X 13.5 Timing Diagrams and Specifications FIGURE 13-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 13-3: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 1A Fosc External CLKIN Frequency DC — 4 MHz XT and RC osc mode, VDD=5.0V (Note 1) DC — 20 MHz HS osc mode DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode, VDD=5.0V (Note 1) 0.1 — 4 MHz XT osc mode 1 — 20 MHz HS osc mode DC – 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 50 — — ns HS osc mode 5 — — s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 50 — 1,000 ns HS osc mode 5 — — s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY=FOSC/4 3* TosL, External Clock in (OSC1) High or 100* — — ns XT oscillator, TOSC L/H duty cycle TosH Low Time 2* — — s LP oscillator, TOSC L/H duty cycle 20* — — ns HS oscillator, TOSC L/H duty cycle 4* TosR, External Clock in (OSC1) Rise or 25* — — ns XT oscillator TosF Fall Time 50* — — ns LP oscillator 15* — — ns HS oscillator * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1998-2013 Microchip Technology Inc. DS40182D-page 91

PIC16CE62X FIGURE 13-6: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 22 CLKOUT 23 13 18 12 14 19 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: All tests must be do with specified capacitance loads (Figure13-4) 50 pF on I/O pins and CLKOUT TABLE 13-4: CLKOUT AND I/O TIMING REQUIREMENTS Parameter # Sym Characteristic Min Typ† Max Units 10* TosH2ckL OSC1 to CLKOUT (1) — 75 200 ns 11* TosH2ckH OSC1 to CLKOUT (1) — 75 200 ns 12* TckR CLKOUT rise time (1) — 35 100 ns 13* TckF CLKOUT fall time (1) — 35 100 ns 14* TckL2ioV CLKOUT  to Port out valid (1) — — 20 ns 15* TioV2ckH Port in valid before CLKOUT  (1) Tosc +200 ns — — ns 16* TckH2ioI Port in hold after CLKOUT  (1) 0 — — ns 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold 100 — — ns time) 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time — 10 40 ns 21* TioF Port output fall time — 10 40 ns 22* Tinp RB0/INT pin high or low time 25 — — ns 23 Trbp RB<7:4> change interrupt high or low time TCY — — ns * These parameters are characterized but not tested † Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS40182D-page 92  1998-2013 Microchip Technology Inc.

PIC16CE62X FIGURE 13-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins FIGURE 13-8: BROWN-OUT RESET TIMING VDD BVDD 35 TABLE 13-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2000 — — ns -40 to +85C 31 Twdt Watchdog Timer Time-out Period 7* 18 33* ms VDD = 5.0V, -40 to +85C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33 Tpwrt Power-up Timer Period 28* 72 132* ms VDD = 5.0V, -40 to +85C 34 TIOZ I/O hi-impedance from MCLR low — 2.0 s 35 TBOR Brown-out Reset Pulse Width 100* — — s 3.7V  VDD  4.3V * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.  1998-2013 Microchip Technology Inc. DS40182D-page 93

PIC16CE62X FIGURE 13-9: TIMER0 CLOCK TIMING RA4/T0CKI 40 41 42 TMR0 TABLE 13-6: TIMER0 CLOCK REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 42 Tt0P T0CKI Period TCY + 40* — — ns N = prescale value N (1, 2, 4, ..., 256) * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40182D-page 94  1998-2013 Microchip Technology Inc.

PIC16CE62X 13.6 EEPROM Timing FIGURE 13-10:BUS TIMING DATA TF TR THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT TSU:STO THD:STA SDA IN TSP TAA THD:STA TAA TBUF SDA OUT TABLE 13-7: AC CHARACTERISTICS STANDARD Vcc = 4.5 - 5.5V Parameter Symbol MODE FAST MODE Units Remarks Min. Max. Min. Max. Clock frequency FCLK — 100 — 400 kHz Clock high time THIGH 4000 — 600 — ns Clock low time TLOW 4700 — 1300 — ns SDA and SCL rise time TR — 1000 — 300 ns (Note 1) SDA and SCL fall time TF — 300 — 300 ns (Note 1) START condition hold time THD:STA 4000 — 600 — ns After this period the first clock pulse is generated START condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated START condition Data input hold time THD:DAT 0 — 0 — ns (Note 2) Data input setup time TSU:DAT 250 — 100 — ns STOP condition setup time TSU:STO 4000 — 600 — ns Output valid from clock TAA — 3500 — 900 ns (Note 2) Bus free time TBUF 4700 — 1300 — ns Time the bus must be free before a new transmission can start Output fall time from VIH TOF — 250 20 + 0.1 250 ns (Note 1), CB  100 pF minimum to VIL maximum CB Input filter spike suppression TSP — 50 — 50 ns (Note 3) (SDA and SCL pins) Write cycle time TWR — 10 — 10 ms Byte or Page mode Endurance 10M — 10M 25°C, VCC = 5.0V, Block — — cycles 1M 1M Mode (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike sup- pression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.  1998-2013 Microchip Technology Inc. DS40182D-page 95

PIC16CE62X NOTES: DS40182D-page 96  1998-2013 Microchip Technology Inc.

PIC16CE62X 14.0 PACKAGING INFORMATION 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 W2 D 2 n 1 W1 E A A2 c L A1 eB B1 B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .100 2.54 Top to Seating Plane A .170 .183 .195 4.32 4.64 4.95 Ceramic Package Height A2 .155 .160 .165 3.94 4.06 4.19 Standoff A1 .015 .023 .030 0.38 0.57 0.76 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Ceramic Pkg. Width E1 .285 .290 .295 7.24 7.37 7.49 Overall Length D .880 .900 .920 22.35 22.86 23.37 Tip to Seating Plane L .125 .138 .150 3.18 3.49 3.81 Lead Thickness c .008 .010 .012 0.20 0.25 0.30 Upper Lead Width B1 .050 .055 .060 1.27 1.40 1.52 Lower Lead Width B .016 .019 .021 0.41 0.47 0.53 Overall Row Spacing eB .345 .385 .425 8.76 9.78 10.80 Window Width W1 .130 .140 .150 3.30 3.56 3.81 Window Length W2 .190 .200 .210 4.83 5.08 5.33 *Controlling Parameter JEDEC Equivalent: MO-036 Drawing No. C04-010  1998-2013 Microchip Technology Inc. DS40182D-page 97

PIC16CE62X 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1  E A2 A c L A1 B1  B p eB Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .890 .898 .905 22.61 22.80 22.99 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 DS40182D-page 98  1998-2013 Microchip Technology Inc.

PIC16CE62X 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1  c A A2  L A1  Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 20 20 Pitch p .026 0.66 Overall Height A .068 .073 .078 1.73 1.85 1.98 Molded Package Thickness A2 .064 .068 .072 1.63 1.73 1.83 Standoff A1 .002 .006 .010 0.05 0.15 0.25 Overall Width E .299 .309 .322 7.59 7.85 8.18 Molded Package Width E1 .201 .207 .212 5.11 5.25 5.38 Overall Length D .278 .284 .289 7.06 7.20 7.34 Foot Length L .022 .030 .037 0.56 0.75 0.94 Lead Thickness c .004 .007 .010 0.10 0.18 0.25 Foot Angle  0 4 8 0.00 101.60 203.20 Lead Width B .010 .013 .015 0.25 0.32 0.38 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072  1998-2013 Microchip Technology Inc. DS40182D-page 99

PIC16CE62X 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E p E1 D 2 B n 1 h  45 c A A2   L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .291 .295 .299 7.39 7.49 7.59 Overall Length D .446 .454 .462 11.33 11.53 11.73 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle  0 4 8 0 4 8 Lead Thickness c .009 .011 .012 0.23 0.27 0.30 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top  0 12 15 0 12 15 Mold Draft Angle Bottom  0 12 15 0 12 15 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051 DS40182D-page 100  1998-2013 Microchip Technology Inc.

PIC16CE62X 14.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX PIC16CE625 XXXXXXXXXXXXXXXXX -04I/P423 AABBCDE 9907CDK 18-Lead SOIC (.300") Example XXXXXXXXXXXX XXXXXXXXXXXX PIC16CE625 XXXXXXXXXXXX -04I/SO218 AABBCDE 9907CDK 18-Lead CERDIP Windowed Example XXXXXXXX 16CE625 XXXXXXXX /JW AABBCDE 9907CBA 20-Lead SSOP Example XXXXXXXXXX PIC16CE625 XXXXXXXXXX -04I/218 AABBCDE 9907CBP Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  1998-2013 Microchip Technology Inc. DS40182D-page 101

PIC16CE62X NOTES: DS40182D-page 102  1998-2013 Microchip Technology Inc.

PIC16CE62X APPENDIX A: CODE FOR APPENDIX B:REVISION HISTORY ACCESSING EEPROM Revision D (January 2013) DATA MEMORY Added a note to each package outline drawing. Please check our web site at www.microchip.com for code availability.  1998-2013 Microchip Technology Inc. DS40182D-page 103

PIC16CE62X NOTES: DS40182D-page 104  1998-2013 Microchip Technology Inc.

PIC16CE62X INDEX BTFSC........................................................................68 BTFSS........................................................................69 A CALL...........................................................................69 ADDLW Instruction.............................................................67 CLRF..........................................................................69 ADDWF Instruction.............................................................67 CLRW.........................................................................69 ANDLW Instruction.............................................................67 CLRWDT....................................................................70 ANDWF Instruction.............................................................67 COMF.........................................................................70 Architectural Overview..........................................................7 DECF..........................................................................70 Assembler DECFSZ.....................................................................70 MPASM Assembler.....................................................77 GOTO.........................................................................71 B INCF...........................................................................71 BCF Instruction...................................................................68 INCFSZ.......................................................................71 Block Diagram IORLW........................................................................71 TIMER0.......................................................................35 IORWF........................................................................72 TMR0/WDT PRESCALER..........................................38 MOVF.........................................................................72 Brown-Out Detect (BOD)....................................................54 MOVLW......................................................................72 BSF Instruction...................................................................68 MOVWF......................................................................72 BTFSC Instruction...............................................................68 NOP............................................................................73 BTFSS Instruction...............................................................69 OPTION......................................................................73 RETFIE.......................................................................73 C RETLW.......................................................................73 CALL Instruction.................................................................69 RETURN.....................................................................74 Clocking Scheme/Instruction Cycle....................................10 RLF.............................................................................74 CLRF Instruction.................................................................69 RRF............................................................................74 CLRW Instruction................................................................69 SLEEP........................................................................74 CLRWDT Instruction...........................................................70 SUBLW.......................................................................75 CMCON Register................................................................41 SUBWF.......................................................................75 Code Protection..................................................................64 SWAPF.......................................................................76 COMF Instruction................................................................70 TRIS...........................................................................76 Comparator Configuration...................................................42 XORLW......................................................................76 Comparator Interrupts.........................................................45 XORWF......................................................................76 Comparator Module............................................................41 Instruction Set Summary....................................................65 Comparator Operation........................................................43 INT Interrupt.......................................................................60 Comparator Reference.......................................................43 INTCON Register................................................................17 Configuration Bits................................................................50 Interrupts............................................................................59 Configuring the Voltage Reference.....................................47 IORLW Instruction..............................................................71 Crystal Operation................................................................51 IORWF Instruction..............................................................72 D K Data Memory Organization.................................................12 KeeLoq Evaluation and Programming Tools...................80 DECF Instruction.................................................................70 M DECFSZ Instruction............................................................70 Development Support.........................................................77 MOVF Instruction................................................................72 MOVLW Instruction.............................................................72 E MOVWF Instruction............................................................72 EEPROM Peripheral Operation..........................................29 MPLAB Integrated Development Environment Software....77 Errata....................................................................................2 N External Crystal Oscillator Circuit.......................................52 NOP Instruction..................................................................73 G O General purpose Register File............................................12 GOTO Instruction................................................................71 One-Time-Programmable (OTP) Devices............................5 OPTION Instruction............................................................73 I OPTION Register................................................................16 I/O Ports..............................................................................23 Oscillator Configurations.....................................................51 I/O Programming Considerations........................................28 Oscillator Start-up Timer (OST)..........................................54 ID Locations........................................................................64 P INCF Instruction..................................................................71 INCFSZ Instruction.............................................................71 Package Marking Information...........................................101 In-Circuit Serial Programming.............................................64 Packaging Information........................................................97 Indirect Addressing, INDF and FSR Registers...................21 PCL and PCLATH...............................................................20 Instruction Flow/Pipelining..................................................10 PCON Register...................................................................19 Instruction Set PICDEM-1 Low-Cost PIC MCU Demo Board.....................79 ADDLW.......................................................................67 PICDEM-2 Low-Cost PIC16CXX Demo Board...................79 ADDWF.......................................................................67 PICDEM-3 Low-Cost PIC16CXXX Demo Board................79 ANDLW.......................................................................67 PICSTART Plus Entry Level Development System.........79 ANDWF.......................................................................67 PIE1 Register.....................................................................18 BCF.............................................................................68 Pinout Description.................................................................9 BSF.............................................................................68 PIR1 Register.....................................................................18  1998-2013 Microchip Technology Inc. DS40182D-page 105

PIC16CE62X Port RB Interrupt.................................................................60 PORTA................................................................................23 PORTB................................................................................26 Power Control/Status Register (PCON)..............................55 Power-Down Mode (SLEEP)...............................................63 Power-On Reset (POR)......................................................54 Power-up Timer (PWRT).....................................................54 Prescaler.............................................................................38 PRO MATE II Universal Programmer...............................79 Program Memory Organization...........................................11 Q Quick-Turnaround-Production (QTP) Devices......................5 R RC Oscillator.......................................................................52 Reset...................................................................................53 RETFIE Instruction..............................................................73 RETLW Instruction..............................................................73 RETURN Instruction............................................................74 RLF Instruction....................................................................74 RRF Instruction...................................................................74 S SEEVAL Evaluation and Programming System...............80 Serialized Quick-Turnaround-Production (SQTP) Devices...5 SLEEP Instruction...............................................................74 Software Simulator (MPLAB-SIM).......................................78 Special Features of the CPU...............................................49 Special Function Registers.................................................14 Stack...................................................................................20 Status Register....................................................................15 SUBLW Instruction..............................................................75 SUBWF Instruction..............................................................75 SWAPF Instruction..............................................................76 T Timer0 TIMER0.......................................................................35 TIMER0 (TMR0) Interrupt...........................................35 TIMER0 (TMR0) Module.............................................35 TMR0 with External Clock...........................................37 Timer1 Switching Prescaler Assignment.................................39 Timing Diagrams and Specifications...................................91 TMR0 Interrupt....................................................................60 TRIS Instruction..................................................................76 TRISA..................................................................................23 TRISB..................................................................................26 V Voltage Reference Module..................................................47 VRCON Register.................................................................47 W Watchdog Timer (WDT)......................................................61 WWW, On-Line Support........................................................2 X XORLW Instruction.............................................................76 XORWF Instruction.............................................................76 DS40182D-page 106  1998-2013 Microchip Technology Inc.

PIC16XXXXXX FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or field application engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  1998-2013 Microchip Technology Inc. DS40182D-page 107

PIC16XXXXXX FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16xxxxxx family Literature Number: DS40182D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS40182D-page 108  1998-2013 Microchip Technology Inc.

PIC16CE62X PIC16CE62X PRODUCT IDENTIFICATION SYSTEM To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. PART NO. -XX X /XX XXX Pattern: 3-Digit Pattern Code for QTP (blank otherwise) Package: P = PDIP SO = SOIC (Gull Wing, 300 mil body) SS = SSOP (209 mil) JW* = Windowed CERDIP Examples: a) PIC16CE623-04/P301 = Temperature - = 0°C to +70°C Commercial temp., PDIP pack- Range: I = –40°C to +85°C age, 4 MHz, normal VDD limits, E = –40°C to +125°C QTP pattern #301. b) PIC16CE623-04I/SO = Industrial temp., SOIC pack- Frequency 04 = 200kHz (LP osc) Range: 04 = 4 MHz (XT and RC osc) age, 4MHz, industrial VDD lim- its. 20 = 20 MHz (HS osc) Device: PIC16CE62X :VDD range 3.0V to 5.5V PIC16CE62XT:VDD range 3.0V to 5.5V (Tape and Reel) * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Worldwide Site (www.microchip.com)  1998-2013 Microchip Technology Inc. DS40182D-page 109

PIC16CE62X NOTES: DS40182D-page 110  1998-2013 Microchip Technology Inc.

PIC16CE62X NOTES:  1998-2013 Microchip Technology Inc. DS40182D-page 111

PIC16CE62X DS40182D-page 112  1998-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1998-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769768 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  1998-2013 Microchip Technology Inc. DS40182D-page 113

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